asap7/riscv32i adder map logic and optimization with resizer #1432
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vijayank88
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This would be better filed as an issue. |
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I am working on
asap7/riscv32i
design with different manual macro placement for lab exercise tutorial. Trying to fix timing violations with multiple variables.The following max path not optimized during placement stage,
With default setup timing reports as follows,
Placement: 3_4_place_resized.log
CTS report: 4_1_cts.log
Post Route Report: 6_report.log
If I remove adder map logic, there is no negative slack.
Placement: 3_4_place_resized.log
CTS report: 4_1_cts.log
Post Route Report: 6_report.log
So where the issue coming from?
ADDER_MAP_FILE
?cc\ @maliberty @gadfort
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