From 439dcfafc5af3e018a80e8112bc515249e1cbfbc Mon Sep 17 00:00:00 2001 From: Nashe Mncube Date: Thu, 26 Sep 2024 13:36:12 +0100 Subject: [PATCH] [llvm][ARM][NFC] Renaming FeaturePrefLoopAlignment (#109932) The feature 'FeaturePrefLoopAlignment' was misleading as it was used to set the alignment of branch targets such as functions. Renamed to FeaturePreferfBranchAlignment. --- llvm/lib/Target/ARM/ARMFeatures.td | 8 ++++---- llvm/lib/Target/ARM/ARMISelLowering.cpp | 5 +++-- llvm/lib/Target/ARM/ARMProcessors.td | 16 ++++++++-------- llvm/lib/Target/ARM/ARMSubtarget.cpp | 2 +- llvm/lib/Target/ARM/ARMSubtarget.h | 6 ++++-- 5 files changed, 20 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMFeatures.td b/llvm/lib/Target/ARM/ARMFeatures.td index dc0e86c696f63a..c1449adc34dc7f 100644 --- a/llvm/lib/Target/ARM/ARMFeatures.td +++ b/llvm/lib/Target/ARM/ARMFeatures.td @@ -372,11 +372,11 @@ def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Prefers32BitThumb", "true", "Prefer 32-bit Thumb instrs">; -def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2", - "Prefer 32-bit alignment for loops">; +def FeaturePreferBranchAlign32 : SubtargetFeature<"loop-align", "PreferBranchLogAlignment","2", + "Prefer 32-bit alignment for branch targets">; -def FeaturePrefLoopAlign64 : SubtargetFeature<"loop-align-64", "PrefLoopLogAlignment","3", - "Prefer 64-bit alignment for loops">; +def FeaturePreferBranchAlign64 : SubtargetFeature<"branch-align-64", "PreferBranchLogAlignment","3", + "Prefer 64-bit alignment for branch targets">; def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "4", "Model MVE instructions as a 1 beat per tick architecture">; diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index f891aece26848c..1733424a8b669f 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1635,8 +1635,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, // Prefer likely predicted branches to selects on out-of-order cores. PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder(); - setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment())); - setPrefFunctionAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment())); + setPrefLoopAlignment(Align(1ULL << Subtarget->getPreferBranchLogAlignment())); + setPrefFunctionAlignment( + Align(1ULL << Subtarget->getPreferBranchLogAlignment())); setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4)); } diff --git a/llvm/lib/Target/ARM/ARMProcessors.td b/llvm/lib/Target/ARM/ARMProcessors.td index a66a2c0b1981d8..ce767b2b968e17 100644 --- a/llvm/lib/Target/ARM/ARMProcessors.td +++ b/llvm/lib/Target/ARM/ARMProcessors.td @@ -324,7 +324,7 @@ def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, ProcM3, - FeaturePrefLoopAlign32, + FeaturePreferBranchAlign32, FeatureUseMISched, FeatureHasNoBranchPredictor]>; @@ -335,7 +335,7 @@ def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, FeatureVFP4_D16_SP, - FeaturePrefLoopAlign32, + FeaturePreferBranchAlign32, FeatureHasSlowFPVMLx, FeatureHasSlowFPVFMx, FeatureUseMISched, @@ -344,7 +344,7 @@ def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em, ProcM7, FeatureFPARMv8_D16, - FeaturePrefLoopAlign64, + FeaturePreferBranchAlign64, FeatureUseMIPipeliner, FeatureUseMISched]>; @@ -355,7 +355,7 @@ def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, FeatureDSP, FeatureFPARMv8_D16_SP, - FeaturePrefLoopAlign32, + FeaturePreferBranchAlign32, FeatureHasSlowFPVMLx, FeatureHasSlowFPVFMx, FeatureUseMISched, @@ -365,7 +365,7 @@ def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, FeatureDSP, FeatureFPARMv8_D16_SP, - FeaturePrefLoopAlign32, + FeaturePreferBranchAlign32, FeatureHasSlowFPVMLx, FeatureHasSlowFPVFMx, FeatureUseMISched, @@ -377,7 +377,7 @@ def : ProcessorModel<"cortex-m55", CortexM55Model, [ARMv81mMainline, FeatureFPARMv8_D16, FeatureUseMISched, FeatureHasNoBranchPredictor, - FeaturePrefLoopAlign32, + FeaturePreferBranchAlign32, FeatureHasSlowFPVMLx, HasMVEFloatOps, FeatureFixCMSE_CVE_2021_35465]>; @@ -386,7 +386,7 @@ def : ProcessorModel<"cortex-m85", CortexM85Model, [ARMv81mMainline, FeatureDSP, FeatureFPARMv8_D16, FeaturePACBTI, - FeaturePrefLoopAlign64, + FeaturePreferBranchAlign64, FeatureUseMISched, HasMVEFloatOps]>; @@ -396,7 +396,7 @@ def : ProcessorModel<"cortex-m52", CortexM55Model, [ARMv81mMainline, FeatureHasNoBranchPredictor, FeaturePACBTI, FeatureUseMISched, - FeaturePrefLoopAlign32, + FeaturePreferBranchAlign32, FeatureHasSlowFPVMLx, FeatureMVEVectorCostFactor1, HasMVEFloatOps]>; diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 13018e647e8223..f9d822873bb004 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -302,7 +302,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { LdStMultipleTiming = SingleIssuePlusExtras; MaxInterleaveFactor = 4; if (!isThumb()) - PrefLoopLogAlignment = 3; + PreferBranchLogAlignment = 3; break; case Kryo: break; diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index fa20f4b590bea5..1ca5bd4a620c4c 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -133,7 +133,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo { int PreISelOperandLatencyAdjustment = 2; /// What alignment is preferred for loop bodies and functions, in log2(bytes). - unsigned PrefLoopLogAlignment = 0; + unsigned PreferBranchLogAlignment = 0; /// The cost factor for MVE instructions, representing the multiple beats an // instruction can take. The default is 2, (set in initSubtargetFeatures so @@ -476,7 +476,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo { return isROPI() || !isTargetELF(); } - unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; } + unsigned getPreferBranchLogAlignment() const { + return PreferBranchLogAlignment; + } unsigned getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const {