UART DMA #36
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liquiddandruff
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Jun 10, 2018
Setup: - OBC/RF board set 1 compiled with STX strobe in rfTxTestSequence(). - OBC/RF board set 2 compiled with SRX strobe in rfTxTestSequence(). - In UART prompt, enter on both sets: > task resume 10 - Set 1 sample output: ... radio task (0x0) S 0x3d < 0x0f tx_underflowed:no tx_numbytes:0 S 0x3d < 0x0f TX FIFO_BYTES_AVAILABLE: 0xf S 0xbd < 0x00 RX FIFO_BYTES_AVAILABLE: 0x0 S 0x3d < 0x0f 62 Bytes Radio TX FIFO written AFTER: tx_underflowed:no tx_numbytes:62 S 0x35 < 0x02 STX strobed... S 0x3d < 0x24 StatusByte: 0x24 radio task (0x0) S 0x3d < 0x0f tx_underflowed:no tx_numbytes:0 S 0x3d < 0x0f TX FIFO_BYTES_AVAILABLE: 0xf S 0xbd < 0x00 RX FIFO_BYTES_AVAILABLE: 0x0 S 0x3d < 0x0f 62 Bytes Radio TX FIFO written AFTER: tx_underflowed:no tx_numbytes:62 S 0x35 < 0x02 STX strobed... S 0x3d < 0x24 StatusByte: 0x24 radio task (0x0) S 0x3d < 0x0f tx_underflowed:no tx_numbytes:0 S 0x3d < 0x0f TX FIFO_BYTES_AVAILABLE: 0xf S 0xbd < 0x00 RX FIFO_BYTES_AVAILABLE: 0x0 S 0x3d < 0x0f 62 Bytes Radio TX FIFO written AFTER: tx_underflowed:no tx_numbytes:62 S 0x35 < 0x02 STX strobed... S 0x3d < 0x24 StatusByte: 0x24 - Set 2 sample output: ... radio task (0x0) S 0x3d < 0x02 tx_underflowed:no tx_numbytes:62 S 0x3d < 0x02 TX FIFO_BYTES_AVAILABLE: 0x2 S 0xbd < 0x0f RX FIFO_BYTES_AVAILABLE: 0xf S 0x3d < 0x02 Radio did not write AFTER: tx_underflowed:no tx_numbytes:62 S 0x34 < 0x02 STX strobed... S 0x3d < 0x12 StatusByte: 0x12 RX Byte #0: 3e RX Byte #1: 10 RX Byte #2: 02 RX Byte #3: 03 RX Byte #4: 04 RX Byte #5: 05 RX Byte #6: 06 RX Byte #7: 07 RX Byte #8: 08 RX Byte #9: 09 RX Byte #10: 0a RX Byte #11: 0b RX Byte #12: 0c RX Byte #13: 0d RX Byte #14: 0e RX Byte #15: 0f RX Byte #16: 10 RX Byte #17: 11 RX Byte #18: 12 RX Byte #19: 13 RX Byte #20: 14 RX Byte #21: 15 RX Byte #22: 16 RX Byte #23: 17 RX Byte #24: 18 RX Byte #25: 19 RX Byte #26: 1a RX Byte #27: 1b RX Byte #28: 1c RX Byte #29: 1d RX Byte #30: 1e RX Byte #31: 1f RX Byte #32: 20 RX Byte #33: 21 RX Byte #34: 22 RX Byte #35: 23 RX Byte #36: 24 RX Byte #37: 25 RX Byte #38: 26 RX Byte #39: 27 RX Byte #40: 28 RX Byte #41: 29 RX Byte #42: 2a RX Byte #43: 2b RX Byte #44: 2c RX Byte #45: 2d RX Byte #46: 2e RX Byte #47: 2f RX Byte #48: 30 RX Byte #49: 31 RX Byte #50: 32 RX Byte #51: 33 RX Byte #52: 34 RX Byte #53: 35 RX Byte #54: 36 RX Byte #55: 37 RX Byte #56: 38 RX Byte #57: 39 RX Byte #58: 3a RX Byte #59: 3b RX Byte #60: 3c RX Byte #61: 3d RX Byte #62: e8 RX Byte #63: ba Misc: - Fix calculation of fifo bytes in writeToTxFIFO. - TODO: readFromRxFIFO changed to always queuering FIFO_RX; change to check only when needed. - Create IS_STATE macro to check state easily.
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It would be nice to use DMA for the UART to free up resources.
http://www.ti.com/lit/an/spna213/spna213.pdf
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