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RTC Error Checks and Tests #21
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We also need a RTOS task that will periodically (once every few seconds) check to see if the current RTC value is greater than the previous RTC value. If not, enter SAFE mode. It should also check RTC registers for failure. Pseudocode:
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Similar to the task above, which is basically a constant sanity check that will be run, we need a simple test suite for the RTC. It should:
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richarthurs
changed the title
Add error checks to RTC driver
RTC Error Checks and Tests
Feb 27, 2018
liquiddandruff
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Jun 10, 2018
Setup: - OBC/RF board set 1 compiled with STX strobe in rfTxTestSequence(). - OBC/RF board set 2 compiled with SRX strobe in rfTxTestSequence(). - In UART prompt, enter on both sets: > task resume 10 - Set 1 sample output: ... radio task (0x0) S 0x3d < 0x0f tx_underflowed:no tx_numbytes:0 S 0x3d < 0x0f TX FIFO_BYTES_AVAILABLE: 0xf S 0xbd < 0x00 RX FIFO_BYTES_AVAILABLE: 0x0 S 0x3d < 0x0f 62 Bytes Radio TX FIFO written AFTER: tx_underflowed:no tx_numbytes:62 S 0x35 < 0x02 STX strobed... S 0x3d < 0x24 StatusByte: 0x24 radio task (0x0) S 0x3d < 0x0f tx_underflowed:no tx_numbytes:0 S 0x3d < 0x0f TX FIFO_BYTES_AVAILABLE: 0xf S 0xbd < 0x00 RX FIFO_BYTES_AVAILABLE: 0x0 S 0x3d < 0x0f 62 Bytes Radio TX FIFO written AFTER: tx_underflowed:no tx_numbytes:62 S 0x35 < 0x02 STX strobed... S 0x3d < 0x24 StatusByte: 0x24 radio task (0x0) S 0x3d < 0x0f tx_underflowed:no tx_numbytes:0 S 0x3d < 0x0f TX FIFO_BYTES_AVAILABLE: 0xf S 0xbd < 0x00 RX FIFO_BYTES_AVAILABLE: 0x0 S 0x3d < 0x0f 62 Bytes Radio TX FIFO written AFTER: tx_underflowed:no tx_numbytes:62 S 0x35 < 0x02 STX strobed... S 0x3d < 0x24 StatusByte: 0x24 - Set 2 sample output: ... radio task (0x0) S 0x3d < 0x02 tx_underflowed:no tx_numbytes:62 S 0x3d < 0x02 TX FIFO_BYTES_AVAILABLE: 0x2 S 0xbd < 0x0f RX FIFO_BYTES_AVAILABLE: 0xf S 0x3d < 0x02 Radio did not write AFTER: tx_underflowed:no tx_numbytes:62 S 0x34 < 0x02 STX strobed... S 0x3d < 0x12 StatusByte: 0x12 RX Byte #0: 3e RX Byte #1: 10 RX Byte #2: 02 RX Byte #3: 03 RX Byte #4: 04 RX Byte #5: 05 RX Byte #6: 06 RX Byte #7: 07 RX Byte #8: 08 RX Byte #9: 09 RX Byte #10: 0a RX Byte #11: 0b RX Byte #12: 0c RX Byte #13: 0d RX Byte #14: 0e RX Byte #15: 0f RX Byte #16: 10 RX Byte #17: 11 RX Byte #18: 12 RX Byte #19: 13 RX Byte #20: 14 RX Byte #21: 15 RX Byte #22: 16 RX Byte #23: 17 RX Byte #24: 18 RX Byte #25: 19 RX Byte #26: 1a RX Byte #27: 1b RX Byte #28: 1c RX Byte #29: 1d RX Byte #30: 1e RX Byte #31: 1f RX Byte #32: 20 RX Byte #33: 21 RX Byte #34: 22 RX Byte #35: 23 RX Byte #36: 24 RX Byte #37: 25 RX Byte #38: 26 RX Byte #39: 27 RX Byte #40: 28 RX Byte #41: 29 RX Byte #42: 2a RX Byte #43: 2b RX Byte #44: 2c RX Byte #45: 2d RX Byte #46: 2e RX Byte #47: 2f RX Byte #48: 30 RX Byte #49: 31 RX Byte #50: 32 RX Byte #51: 33 RX Byte #52: 34 RX Byte #53: 35 RX Byte #54: 36 RX Byte #55: 37 RX Byte #56: 38 RX Byte #57: 39 RX Byte #58: 3a RX Byte #59: 3b RX Byte #60: 3c RX Byte #61: 3d RX Byte #62: e8 RX Byte #63: ba Misc: - Fix calculation of fifo bytes in writeToTxFIFO. - TODO: readFromRxFIFO changed to always queuering FIFO_RX; change to check only when needed. - Create IS_STATE macro to check state easily.
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The RTC has a lot of bits that can be checked to determine if it has lost power or undergone a reset for some other reason. It can also provide an estimate if time data has been corrupted.
rtc_get_startup_status() needs to be fleshed out to log errors, and another function that periodically checks the status of the RTC needs to be created.
Resources: [1] http://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-EOA9-S3.pdf
[2] http://www.abracon.com/realtimeclock/AB-RTCMC-32.768kHz-EOA9-S3-Application-Manual.pdf
Bits that should be checked:
CTRL_STATUS -> PON (1 = time might be bad)
CTRL_STATUS -> SR (1 = time might be bad)
CTRL_STATUS -> V2F (1 = time might be bad)
CTRL_STATUS -> V1F (1 = time might be bad)
CONTROL_INT FLAG -> V2IF (1 = time might be bad)
CONTROL_INT FLAG -> V1IF (1 = notable event, but time is ok)
These bits should be set for configuration at startup:
CONTROL_INT -> SRIE = 1
CONTROL_INT -> V2IE = 1
CONTROL_INT -> V1IE = 1
CTRL_STATUS -> PON = 0
Assert a system reset [2 - page 24] at first power on (PON = 1)
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