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The current design is following the 400MHz schematic in the datasheet. This needs to be redesigned to optimise for 435MHz
The text was updated successfully, but these errors were encountered:
high noise measurement could be from layout. However, the matching is good so it might not be the layout at all.
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The current design is following the 400MHz schematic in the datasheet. This needs to be redesigned to optimise for 435MHz
The text was updated successfully, but these errors were encountered: