diff --git a/.github/workflows/workspace.yml b/.github/workflows/workspace.yml index 3f3eeace1..dc2b0f795 100644 --- a/.github/workflows/workspace.yml +++ b/.github/workflows/workspace.yml @@ -17,7 +17,7 @@ jobs: - uses: RustCrypto/actions/cargo-cache@master - uses: dtolnay/rust-toolchain@master with: - toolchain: 1.60.0 + toolchain: 1.71.0 components: clippy - run: cargo clippy --all -- -D warnings diff --git a/blake2/src/as_bytes.rs b/blake2/src/as_bytes.rs index 743a5adc3..c77fcd6df 100644 --- a/blake2/src/as_bytes.rs +++ b/blake2/src/as_bytes.rs @@ -19,19 +19,12 @@ pub trait AsBytes { impl AsBytes for [T] { #[inline] fn as_bytes(&self) -> &[u8] { - unsafe { - slice::from_raw_parts(self.as_ptr() as *const u8, self.len() * mem::size_of::()) - } + unsafe { slice::from_raw_parts(self.as_ptr() as *const u8, mem::size_of_val(self)) } } #[inline] fn as_mut_bytes(&mut self) -> &mut [u8] { - unsafe { - slice::from_raw_parts_mut( - self.as_mut_ptr() as *mut u8, - self.len() * mem::size_of::(), - ) - } + unsafe { slice::from_raw_parts_mut(self.as_mut_ptr() as *mut u8, mem::size_of_val(self)) } } } diff --git a/blake2/src/simd/simd_opt/u32x4.rs b/blake2/src/simd/simd_opt/u32x4.rs index 8b34e76e8..7190d96f7 100644 --- a/blake2/src/simd/simd_opt/u32x4.rs +++ b/blake2/src/simd/simd_opt/u32x4.rs @@ -25,7 +25,7 @@ pub fn rotate_right_const(vec: u32x4, n: u32) -> u32x4 { #[inline(always)] fn rotate_right_any(vec: u32x4, n: u32) -> u32x4 { - let r = n as u32; + let r = n; let l = 32 - r; (vec >> u32x4::new(r, r, r, r)) ^ (vec << u32x4::new(l, l, l, l)) diff --git a/blake2/tests/mac.rs b/blake2/tests/mac.rs index 97fbc9d70..dd75a5703 100644 --- a/blake2/tests/mac.rs +++ b/blake2/tests/mac.rs @@ -16,7 +16,7 @@ fn blake2b_new_test() { .chain_update(DATA) .finalize() .into_bytes(); - let res2 = ::new_from_slice(&key) + let res2 = ::new_from_slice(key) .unwrap() .chain_update(DATA) .finalize() diff --git a/streebog/src/table.rs b/streebog/src/table.rs index 337578285..f47eb6133 100644 --- a/streebog/src/table.rs +++ b/streebog/src/table.rs @@ -2077,6 +2077,7 @@ mod test { use super::SHUFFLED_LIN_TABLE; use crate::consts::{A, P}; + #[allow(clippy::needless_range_loop)] fn gen_table() -> [[u64; 256]; 8] { let mut table: [[u64; 256]; 8] = [[0; 256]; 8]; for i in 0..8 { diff --git a/tiger/src/lib.rs b/tiger/src/lib.rs index a5f1f8d80..ed2830a7d 100644 --- a/tiger/src/lib.rs +++ b/tiger/src/lib.rs @@ -91,7 +91,7 @@ impl UpdateCore for TigerCore { impl FixedOutputCore for TigerCore { #[inline] fn finalize_fixed_core(&mut self, buffer: &mut Buffer, out: &mut Output) { - let bs = Self::BlockSize::U64 as u64; + let bs = Self::BlockSize::U64; let pos = buffer.get_pos() as u64; let bit_len = 8 * (pos + bs * self.block_len); @@ -165,7 +165,7 @@ impl UpdateCore for Tiger2Core { impl FixedOutputCore for Tiger2Core { #[inline] fn finalize_fixed_core(&mut self, buffer: &mut Buffer, out: &mut Output) { - let bs = Self::BlockSize::U64 as u64; + let bs = Self::BlockSize::U64; let pos = buffer.get_pos() as u64; let bit_len = 8 * (pos + bs * self.block_len);