From e03342ff6b237d3ac6c38e133cb23b9770281f4a Mon Sep 17 00:00:00 2001 From: Fan YANG Date: Fri, 31 May 2024 19:46:47 +0800 Subject: [PATCH] [bsp][hpmicro] add HPM5300EVK,HPM5301EVKLITE and HPM6800EVK support & update hpm_sdk - added new boards: hpm5300evk, hpm5301evklite and hpm6800evk - upgaded hpm_sdk - driver updates and bugfixes - add hpmicro BSPs to CI Signed-off-by: Fan YANG --- .github/workflows/bsp_buildings.yml | 19 + bsp/hpmicro/.ignore_format.yml | 3 + bsp/hpmicro/hpm5300evk/.config | 1061 + bsp/hpmicro/hpm5300evk/Kconfig | 21 + bsp/hpmicro/hpm5300evk/README.md | 113 + bsp/hpmicro/hpm5300evk/README_zh.md | 112 + bsp/hpmicro/hpm5300evk/SConscript | 17 + bsp/hpmicro/hpm5300evk/SConstruct | 75 + .../hpm5300evk/applications/SConscript | 14 + bsp/hpmicro/hpm5300evk/applications/main.c | 38 + bsp/hpmicro/hpm5300evk/board/Kconfig | 236 + bsp/hpmicro/hpm5300evk/board/SConscript | 18 + bsp/hpmicro/hpm5300evk/board/board.c | 662 + bsp/hpmicro/hpm5300evk/board/board.h | 385 + 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.../hpm_sdk/soc/HPM6750/hpm_bcfg_regs.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_bgpr_regs.h | 108 +- .../hpm_sdk/soc/HPM6750/hpm_bpor_regs.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_clock_drv.c | 109 +- .../hpm_sdk/soc/HPM6750/hpm_clock_drv.h | 286 +- .../hpm_sdk/soc/HPM6750/hpm_csr_regs.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_dmamux_regs.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_dmamux_src.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_gpiom_regs.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_gpiom_soc_drv.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_interrupt.h | 210 +- .../hpm_sdk/soc/HPM6750/hpm_ioc_regs.h | 4 +- .../libraries/hpm_sdk/soc/HPM6750/hpm_iomux.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_l1c_drv.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_otp_drv.c | 35 +- .../hpm_sdk/soc/HPM6750/hpm_otp_drv.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_pcfg_drv.h | 51 +- .../hpm_sdk/soc/HPM6750/hpm_pcfg_regs.h | 35 +- .../hpm_sdk/soc/HPM6750/hpm_pgpr_regs.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_pmic_iomux.h | 192 +- .../hpm_sdk/soc/HPM6750/hpm_ppor_drv.h | 38 +- .../hpm_sdk/soc/HPM6750/hpm_ppor_regs.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_romapi.h | 9 +- .../hpm_sdk/soc/HPM6750/hpm_sdxc_soc_drv.h | 48 +- .../hpm_sdk/soc/HPM6750/hpm_ses_reg.xml | 2360 +- .../soc/HPM6750/hpm_ses_riscv_cpu_regs.xml | 2 +- .../libraries/hpm_sdk/soc/HPM6750/hpm_soc.h | 258 +- .../hpm_sdk/soc/HPM6750/hpm_soc_feature.h | 28 +- .../hpm_sdk/soc/HPM6750/hpm_soc_ip_feature.h | 13 + .../hpm_sdk/soc/HPM6750/hpm_sysctl_drv.c | 87 +- .../hpm_sdk/soc/HPM6750/hpm_sysctl_drv.h | 40 +- .../hpm_sdk/soc/HPM6750/hpm_sysctl_regs.h | 14 +- .../hpm_sdk/soc/HPM6750/hpm_trgm_regs.h | 2 +- .../hpm_sdk/soc/HPM6750/hpm_trgmmux_src.h | 2 +- .../hpm_sdk/soc/HPM6750/soc_modules.list | 97 +- .../libraries/hpm_sdk/soc/HPM6750/system.c | 7 - .../soc/HPM6750/toolchains/gcc/flash.ld | 108 +- .../HPM6750/toolchains/gcc/flash_sdram_uf2.ld | 107 +- .../HPM6750/toolchains/gcc/flash_sdram_xip.ld | 109 +- .../soc/HPM6750/toolchains/gcc/flash_uf2.ld | 109 +- .../soc/HPM6750/toolchains/gcc/flash_xip.ld | 110 +- .../hpm_sdk/soc/HPM6750/toolchains/gcc/ram.ld | 73 +- .../soc/HPM6750/toolchains/gcc/ram_core1.ld | 79 +- .../soc/HPM6750/toolchains/gcc/start.S | 28 + .../hpm_sdk/soc/HPM6750/toolchains/reset.c | 77 +- .../soc/HPM6750/toolchains/segger/flash.icf | 111 - .../toolchains/segger/flash_sdram_uf2.icf | 113 - .../toolchains/segger/flash_sdram_xip.icf | 120 - .../HPM6750/toolchains/segger/flash_uf2.icf | 113 - .../HPM6750/toolchains/segger/flash_xip.icf | 121 - .../soc/HPM6750/toolchains/segger/ram.icf | 98 - .../HPM6750/toolchains/segger/ram_core1.icf | 94 - .../soc/HPM6750/toolchains/segger/startup.s | 390 - .../hpm_sdk/soc/HPM6750/toolchains/trap.c | 21 +- .../hpm_sdk/soc/HPM6750/toolchains/vectors.h | 285 +- .../hpm_sdk/soc/HPM6880/HPM6880_svd.xml | 54354 ++++++++++++++ .../libraries/hpm_sdk/soc/HPM6880/SConscript | 25 + .../hpm_sdk/soc/HPM6880/boot/hpm_bootheader.c | 42 + .../hpm_sdk/soc/HPM6880/boot/hpm_bootheader.h | 64 + .../hpm_sdk/soc/HPM6880/hpm_batt_iomux.h | 141 + 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.../hpm_sdk/soc/HPM6880/hpm_otp_drv.c | 181 + .../hpm_sdk/soc/HPM6880/hpm_otp_drv.h | 137 + .../hpm_sdk/soc/HPM6880/hpm_pcfg_drv.h | 888 + .../hpm_sdk/soc/HPM6880/hpm_pcfg_regs.h | 1363 + .../hpm_sdk/soc/HPM6880/hpm_pgpr_regs.h | 211 + .../hpm_sdk/soc/HPM6880/hpm_plic_drv.h | 186 + .../hpm_sdk/soc/HPM6880/hpm_pmic_iomux.h | 147 + .../hpm_sdk/soc/HPM6880/hpm_ppor_drv.h | 155 + .../hpm_sdk/soc/HPM6880/hpm_ppor_regs.h | 139 + .../hpm_sdk/soc/HPM6880/hpm_romapi.h | 1016 + .../soc/HPM6880/hpm_romapi_xpi_soc_def.h | 80 + .../hpm_sdk/soc/HPM6880/hpm_sdxc_soc_drv.h | 162 + .../hpm_sdk/soc/HPM6880/hpm_ses_reg.xml | 60238 ++++++++++++++++ .../soc/HPM6880/hpm_ses_riscv_cpu_regs.xml | 770 + .../libraries/hpm_sdk/soc/HPM6880/hpm_soc.h | 814 + .../hpm_sdk/soc/HPM6880/hpm_soc_feature.h | 221 + .../hpm_sdk/soc/HPM6880/hpm_soc_ip_feature.h | 26 + .../hpm_sdk/soc/HPM6880/hpm_sysctl_drv.c | 244 + .../hpm_sdk/soc/HPM6880/hpm_sysctl_drv.h | 1220 + .../hpm_sdk/soc/HPM6880/hpm_sysctl_regs.h | 1297 + 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.../hpm_sdk/soc/ip/hpm_ddrphy_regs.h | 5989 ++ .../libraries/hpm_sdk/soc/ip/hpm_dmav2_regs.h | 596 + .../libraries/hpm_sdk/soc/ip/hpm_enet_regs.h | 4 +- .../libraries/hpm_sdk/soc/ip/hpm_ewdg_regs.h | 465 + .../libraries/hpm_sdk/soc/ip/hpm_ffa_regs.h | 25 +- .../libraries/hpm_sdk/soc/ip/hpm_gpio_regs.h | 71 +- .../libraries/hpm_sdk/soc/ip/hpm_gpu_regs.h | 651 + .../libraries/hpm_sdk/soc/ip/hpm_gwc_regs.h | 209 + .../libraries/hpm_sdk/soc/ip/hpm_i2s_regs.h | 2 +- .../libraries/hpm_sdk/soc/ip/hpm_lcb_regs.h | 325 + .../libraries/hpm_sdk/soc/ip/hpm_lcdc_regs.h | 2 +- .../libraries/hpm_sdk/soc/ip/hpm_linv2_regs.h | 466 + .../libraries/hpm_sdk/soc/ip/hpm_lvb_regs.h | 442 + .../libraries/hpm_sdk/soc/ip/hpm_mcan_regs.h | 64 +- .../hpm_sdk/soc/ip/hpm_mipi_csi_phy_regs.h | 961 + .../hpm_sdk/soc/ip/hpm_mipi_csi_regs.h | 3618 + .../hpm_sdk/soc/ip/hpm_mipi_dsi_phy_regs.h | 993 + .../hpm_sdk/soc/ip/hpm_mipi_dsi_regs.h | 2882 + .../libraries/hpm_sdk/soc/ip/hpm_mmc_regs.h | 1621 + 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bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgm_soc_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/hpm_trgmmux_src.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/soc_modules.list create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/system.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_uf2.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/flash_xip.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/initfini.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/ram.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/gcc/start.S create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/reset.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/trap.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM5361/toolchains/vectors.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/HPM6280_svd.xml create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/hpm_soc_ip_feature.h delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_uf2.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/flash_xip.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/ram_core1.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6280/toolchains/segger/startup.s create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/HPM6360_svd.xml create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/hpm_soc_ip_feature.h delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_uf2.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_sdram_xip.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_uf2.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/flash_xip.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/ram.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6360/toolchains/segger/startup.s create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/HPM6750_svd.xml create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/hpm_soc_ip_feature.h delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_uf2.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_sdram_xip.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_uf2.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/flash_xip.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/ram_core1.icf delete mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6750/toolchains/segger/startup.s create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/HPM6880_svd.xml create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/SConscript create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/boot/hpm_bootheader.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/boot/hpm_bootheader.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_batt_iomux.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bcfg_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bcfg_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bgpr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bpor_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_bpor_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_clock_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_clock_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_csr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_dmamux_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_dmamux_src.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_enet_soc_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_gpiom_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_gpiom_soc_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_interrupt.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ioc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_iomux.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_l1c_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_l1c_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_mcan_soc.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_misc.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_otp_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_otp_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pcfg_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pcfg_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pgpr_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_plic_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_pmic_iomux.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ppor_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ppor_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_romapi.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_romapi_xpi_soc_def.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sdxc_soc_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ses_reg.xml create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_ses_riscv_cpu_regs.xml create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc_feature.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_soc_ip_feature.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_drv.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_drv.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/hpm_sysctl_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/soc_modules.list create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/system.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_sdram_uf2.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_sdram_xip.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_uf2.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/flash_xip.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/initfini.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/ram.ld create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/gcc/start.S create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/reset.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/trap.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/HPM6880/toolchains/vectors.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ddrctl_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ddrphy_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_dmav2_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_ewdg_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gpu_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_gwc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lcb_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_linv2_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_lvb_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_csi_phy_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_csi_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_phy_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mipi_dsi_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_mmc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_opamp_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_pixelmux_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_plb_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qeiv2_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_qeo_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_rdc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdadc_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sdmv2_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_sei_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/soc/ip/hpm_smix_regs.h create mode 100644 bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.c create mode 100644 bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.h diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index 95f5edd46cb..cce98770fef 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -326,6 +326,17 @@ jobs: - "bluetrum/ab32vg1-ab-prougen" - "bouffalo_lab/bl60x" - "bouffalo_lab/bl70x" + - RTT_BSP: "hpmicro" + RTT_TOOL_CHAIN: "RISC-V-GCC-RV32" + SUB_RTT_BSP: + - "hpmicro/hpm6750evkmini" + - "hpmicro/hpm6750evk" + - "hpmicro/hpm6750evk2" + - "hpmicro/hpm6300evk" + - "hpmicro/hpm6200evk" + - "hpmicro/hpm5300evk" + - "hpmicro/hpm5301evklite" + - "hpmicro/hpm6800evk" - RTT_BSP: "llvm-arm" RTT_TOOL_CHAIN: "llvm-arm" SUB_RTT_BSP: @@ -406,6 +417,14 @@ jobs: /opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc --version echo "RTT_EXEC_PATH=/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin" >> $GITHUB_ENV + - name: Install riscv32-unknown-elf Toolchains + if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'RISC-V-GCC-RV32' && success() }} + run: | + wget -q https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2022.05.15/riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz + sudo tar zxf riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz -C /opt + /opt/riscv32-unknown-elf-newlib-multilib/bin/riscv32-unknown-elf-gcc --version + echo "RTT_EXEC_PATH=/opt/riscv32-unknown-elf-newlib-multilib/bin/" >> $GITHUB_ENV + - name: Install Riscv-none-embed ToolChains if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv-none-embed' && success() }} run: | diff --git a/bsp/hpmicro/.ignore_format.yml b/bsp/hpmicro/.ignore_format.yml index cad99bf4706..65bf18b330a 100644 --- a/bsp/hpmicro/.ignore_format.yml +++ b/bsp/hpmicro/.ignore_format.yml @@ -8,4 +8,7 @@ dir_path: - hpm6750evk/startup - hpm6750evk2/startup - hpm6750evkmini/startup + - hpm5300evk/startup + - hpm5301evklite/startup + - hpm6800evk/startup - libraries/hpm_sdk diff --git a/bsp/hpmicro/hpm5300evk/.config b/bsp/hpmicro/hpm5300evk/.config new file mode 100644 index 00000000000..1bd33fdf9b3 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/.config @@ -0,0 +1,1061 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 + +# +# kservice optimization +# +# CONFIG_RT_USING_TINY_FFS is not set + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# CONFIG_RT_USING_DEBUG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +# CONFIG_RT_USING_HW_ATOMIC is not set +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +# CONFIG_ARCH_USING_HW_THREAD_SELF is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +CONFIG_RT_USING_LEGACY=y +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_USING_DMA is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM5000=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_EWDG is not set +# CONFIG_BSP_USING_MCAN is not set +# CONFIG_BSP_USING_ADC is not set diff --git a/bsp/hpmicro/hpm5300evk/Kconfig b/bsp/hpmicro/hpm5300evk/Kconfig new file mode 100644 index 00000000000..79b160b8567 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hpmicro/hpm5300evk/README.md b/bsp/hpmicro/hpm5300evk/README.md new file mode 100644 index 00000000000..4e6ad210a66 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/README.md @@ -0,0 +1,113 @@ +# HPMicro HPM5300EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM5300EVK development board. + +The document consists of the following parts: + +- HPM5300EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM5300EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| CAN | √ | | +| On-Board Debugger | √ | ft2232 | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Aug 16 2023 18:18:18 + 2006 - 2024 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5300EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm5300evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5300evk/README_zh.md b/bsp/hpmicro/hpm5300evk/README_zh.md new file mode 100644 index 00000000000..9b7086ddc10 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/README_zh.md @@ -0,0 +1,112 @@ +# 先楫 HPM5300EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM5300EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM5300EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + + HPM5300EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| CAN | √ | | +| 板载调试器 | √ | ft2232 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\cmsis_dap.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5300.cfg -f boards\debug_scripts\boards\hpm5300evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Aug 16 2023 18:18:18 + 2006 - 2023 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5300EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm5300evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5300evk/SConscript b/bsp/hpmicro/hpm5300evk/SConscript new file mode 100644 index 00000000000..014c428d0a3 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm5300evk/SConstruct b/bsp/hpmicro/hpm5300evk/SConstruct new file mode 100644 index 00000000000..3dadc575c01 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/SConstruct @@ -0,0 +1,75 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hpm_library = 'hpm_sdk' +rtconfig.BSP_LIBRARY_TYPE = hpm_library + +# include soc +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript'))) + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) + +# include components +objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5300evk/applications/SConscript b/bsp/hpmicro/hpm5300evk/applications/SConscript new file mode 100644 index 00000000000..a65aa4d8553 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/applications/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5300evk/applications/main.c b/bsp/hpmicro/hpm5300evk/applications/main.c new file mode 100644 index 00000000000..0bbf6370382 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/applications/main.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2021 hpmicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" +#include + +void thread_entry(void *arg); + + +int main(void) +{ + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + + +void thread_entry(void *arg) +{ + rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT); + + while(1){ + rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON); + rt_thread_mdelay(500); + rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm5300evk/board/Kconfig b/bsp/hpmicro/hpm5300evk/board/Kconfig new file mode 100644 index 00000000000..20bc12d04ba --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/Kconfig @@ -0,0 +1,236 @@ +menu "Hardware Drivers Config" + +config SOC_HPM5000 + bool + select SOC_SERIES_HPM5300 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default y + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default y + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1" + default y + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + endif + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + default n + endif + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + default n + endif + endif + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + endif + + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + endif + endif + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + default n + config BSP_USING_USB_HOST + bool "Enable USB HOST" + select RT_USING_CACHE + default n + endif + + menuconfig BSP_USING_EWDG + bool "Enable EWDG" + default n + select RT_USING_WDT if BSP_USING_EWDG + if BSP_USING_EWDG + config BSP_USING_EWDG0 + bool "Enable EWDG0" + default n + config BSP_USING_EWDG1 + bool "Enable EWDG1" + default n + endif + + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN if BSP_USING_MCAN + if BSP_USING_MCAN + config BSP_USING_MCAN0 + bool "Enable MCAN0" + default n + config BSP_USING_MCAN1 + bool "Enable MCAN1" + default n + config BSP_USING_MCAN2 + bool "Enable MCAN2" + default n + config BSP_USING_MCAN3 + bool "Enable MCAN3" + default n + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default y + if BSP_USING_ADC16 + config BSP_USING_ADC0 + bool "Enable ADC0" + default y + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + endif +endmenu + +endmenu diff --git a/bsp/hpmicro/hpm5300evk/board/SConscript b/bsp/hpmicro/hpm5300evk/board/SConscript new file mode 100644 index 00000000000..dcd1e3543fd --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/SConscript @@ -0,0 +1,18 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D25', 'HPM5361'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5300evk/board/board.c b/bsp/hpmicro/hpm5300evk/board/board.c new file mode 100644 index 00000000000..ce3f1ee0cee --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/board.c @@ -0,0 +1,662 @@ +/* + * Copyright (c) 2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_usb_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_pcfg_drv.h" + +static board_timer_cb timer_cb; + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0}; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + * uart rx pin when configuring pin function will cause a wrong data to be received. + * And a uart rx dma request will be generated by default uart fifo dma trigger level. + */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + + /* Configure the UART clock to 24MHz */ + clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t)BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_banner(void) +{ + const uint8_t banner[] = "\n" +"----------------------------------------------------------------------\n" +"$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n" +"$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n" +"$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n" +"$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n" +"$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n" +"$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n" +"$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n" +"\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n" +"----------------------------------------------------------------------\n"; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %luHz\n", clock_get_frequency(clock_cpu0)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb)); + printf("mchtmr0:\t %luHz\n", clock_get_frequency(clock_mchtmr0)); + printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); + printf("==============================\n"); +} + +void board_init(void) +{ + init_xtal_pins(); + init_py_pins_as_pgpio(); + board_init_usb_dp_dm_pins(); + + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_usb_dp_dm_pins(void) +{ + /* Disconnect usb dp/dm pins pull down 45ohm resistance */ + + while (sysctl_resource_any_is_busy(HPM_SYSCTL)) { + ; + } + if (pllctlv2_xtal_is_stable(HPM_PLLCTLV2) && pllctlv2_xtal_is_enabled(HPM_PLLCTLV2)) { + if (clock_check_in_group(clock_usb0, 0)) { + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + } else { + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + } + } else { + uint8_t tmp; + tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal); + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); + clock_add_to_group(clock_usb0, 0); + usb_phy_disable_dp_dm_pulldown(HPM_USB0); + clock_remove_from_group(clock_usb0, 0); + while (sysctl_resource_target_is_busy(HPM_SYSCTL, sysctl_resource_usb0)) { + ; + } + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, tmp); + } +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32UL * 1000UL * 9U); + + /* Select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + + /* group0[0] */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_ahb, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_rom, 0); + clock_add_to_group(clock_can0, 0); + clock_add_to_group(clock_can1, 0); + clock_add_to_group(clock_can2, 0); + clock_add_to_group(clock_can3, 0); + clock_add_to_group(clock_ptpc, 0); + clock_add_to_group(clock_gptmr0, 0); + clock_add_to_group(clock_gptmr1, 0); + clock_add_to_group(clock_gptmr2, 0); + clock_add_to_group(clock_gptmr3, 0); + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + clock_add_to_group(clock_spi0, 0); + clock_add_to_group(clock_spi1, 0); + clock_add_to_group(clock_spi2, 0); + clock_add_to_group(clock_spi3, 0); + clock_add_to_group(clock_uart0, 0); + clock_add_to_group(clock_uart1, 0); + clock_add_to_group(clock_uart2, 0); + clock_add_to_group(clock_uart3, 0); + clock_add_to_group(clock_uart4, 0); + clock_add_to_group(clock_uart5, 0); + clock_add_to_group(clock_uart6, 0); + /* group0[1] */ + clock_add_to_group(clock_uart7, 0); + clock_add_to_group(clock_watchdog0, 0); + clock_add_to_group(clock_watchdog1, 0); + clock_add_to_group(clock_mbx0, 0); + clock_add_to_group(clock_tsns, 0); + clock_add_to_group(clock_crc0, 0); + clock_add_to_group(clock_adc0, 0); + clock_add_to_group(clock_adc1, 0); + clock_add_to_group(clock_dac0, 0); + clock_add_to_group(clock_dac1, 0); + clock_add_to_group(clock_acmp, 0); + clock_add_to_group(clock_opa0, 0); + clock_add_to_group(clock_opa1, 0); + clock_add_to_group(clock_mot0, 0); + clock_add_to_group(clock_rng, 0); + clock_add_to_group(clock_sdp, 0); + clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_usb0, 0); + + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Bump up DCDC voltage to 1175mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1175); + + /* Configure CPU to 480MHz, AXI/AHB to 160MHz */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3); + /* Configure PLL0 Post Divider */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 960MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 600MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 400MHz */ + /* Configure PLL0 Frequency to 960MHz */ + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 960000000); + + clock_update_core_clock(); + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); +} + +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); + gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN); +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); +} + +void board_init_usb_pins(void) +{ + init_usb_pins(); + usb_hcd_set_power_ctrl_polarity(BOARD_USB, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); + + /* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ + /* usb_phy_using_internal_vbus(BOARD_USB); */ +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_led_toggle(void) +{ + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + clock_add_to_group(clock_spi1, 0); + return clock_get_frequency(clock_spi1); + } + return 0; +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +{ + (void) usb_index; + (void) level; +} + +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U); + } + + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk2, 2U); + } + + freq = clock_get_frequency(clock_adc1); + } + + return freq; +} + +void board_init_adc16_pins(void) +{ + init_adc_pins(); +} + +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_DAC0) { + if (clk_src_ahb == true) { + /* Configure the DAC clock to 180MHz */ + clock_set_dac_source(clock_dac0, clk_dac_src_ahb0); + } else { + /* Configure the DAC clock to 166MHz */ + clock_set_dac_source(clock_dac0, clk_dac_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2); + } + + freq = clock_get_frequency(clock_dac0); + } else if (ptr == HPM_DAC1) { + if (clk_src_ahb == true) { + /* Configure the DAC clock to 180MHz */ + clock_set_dac_source(clock_dac1, clk_dac_src_ahb0); + } else { + /* Configure the DAC clock to 166MHz */ + clock_set_dac_source(clock_dac1, clk_dac_src_ana3); + clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); + } + + freq = clock_get_frequency(clock_dac1); + } + + return freq; +} + +void board_init_can(MCAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(MCAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_MCAN0) { + clock_add_to_group(clock_can0, 0); + clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can0); + } + if (ptr == HPM_MCAN1) { + clock_add_to_group(clock_can1, 0); + clock_set_source_divider(clock_can1, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can1); + } + if (ptr == HPM_MCAN2) { + clock_add_to_group(clock_can2, 0); + clock_set_source_divider(clock_can2, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can2); + } + if (ptr == HPM_MCAN3) { + clock_add_to_group(clock_can3, 0); + clock_set_source_divider(clock_can3, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can3); + } + return freq; +} + +uint32_t board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + (void) ptr; + + clock_add_to_group(clock_mot0, 0); + freq = clock_get_frequency(clock_mot0); + + return freq; +} + +void board_init_rgb_pwm_pins(void) +{ + init_led_pins_as_pwm(); +} + +void board_disable_output_rgb_led(uint8_t color) +{ + (void) color; +} + +void board_enable_output_rgb_led(uint8_t color) +{ + (void) color; +} + +void board_init_dac_pins(DAC_Type *ptr) +{ + init_dac_pins(ptr); +} + +uint8_t board_get_led_pwm_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_init_pmp(void) +{ +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART1) { + clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); + clock_add_to_group(clock_uart1, 0); + freq = clock_get_frequency(clock_uart1); + } else if (ptr == HPM_UART2) { + clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 8); + clock_add_to_group(clock_uart2, 0); + freq = clock_get_frequency(clock_uart2); + } else if (ptr == HPM_UART3) { + clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 8); + clock_add_to_group(clock_uart3, 0); + freq = clock_get_frequency(clock_uart3); + } else if (ptr == HPM_UART7) { + clock_set_source_divider(clock_uart7, clk_src_pll0_clk2, 6); /* 80MHz */ + clock_add_to_group(clock_uart7, 0); + freq = clock_get_frequency(clock_uart7); + } + return freq; +} + +void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) +{ + init_sei_pins(ptr, sei_ctrl_idx); +} + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + if (i2c_get_line_scl_status(ptr) == false) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (i2c_get_line_sda_status(ptr) == false) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + i2s_gen_reset_signal(ptr, 9); + board_delay_ms(100); + printf("I2C bus is cleared\n"); +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + if (ptr == NULL) { + return; + } + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + + clock_add_to_group(clock_i2c0, 0); + clock_add_to_group(clock_i2c1, 0); + clock_add_to_group(clock_i2c2, 0); + clock_add_to_group(clock_i2c3, 0); + /* Configure the I2C clock to 24MHz */ + clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + while (1) { + } + } + +} + +void board_init_adc_qeiv2_pins(void) +{ + init_adc_qeiv2_pins(); +} + +void board_lin_transceiver_control(bool enable) +{ + init_lin_transceiver_ctrl_pin(); + if (enable) { + gpio_set_pin_output_with_initial(BOARD_12V_EN_GPIO_CTRL, BOARD_12V_EN_GPIO_INDEX, BOARD_12V_EN_GPIO_PIN, 1); /* enable 12v output */ + gpio_set_pin_output_with_initial(BOARD_LIN_TRANSCEIVER_GPIO_CTRL, BOARD_LIN_TRANSCEIVER_GPIO_INDEX, BOARD_LIN_TRANSCEIVER_GPIO_PIN, 1); /* disable transceiver sleep */ + } else { + gpio_set_pin_output_with_initial(BOARD_12V_EN_GPIO_CTRL, BOARD_12V_EN_GPIO_INDEX, BOARD_12V_EN_GPIO_PIN, 0); /* disable 12v output */ + gpio_set_pin_output_with_initial(BOARD_LIN_TRANSCEIVER_GPIO_CTRL, BOARD_LIN_TRANSCEIVER_GPIO_INDEX, BOARD_LIN_TRANSCEIVER_GPIO_PIN, 0); /* enable transceiver sleep */ + } +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0; + clock_name_t gptmr_clock =0; + uint32_t HPM_GPTMR = (uint32_t)ptr; + bool gptmr_valid = true; + + switch(HPM_GPTMR){ + case HPM_GPTMR0_BASE: + gptmr_clock = clock_gptmr0; + break; + case HPM_GPTMR1_BASE: + gptmr_clock = clock_gptmr1; + break; + case HPM_GPTMR2_BASE: + gptmr_clock = clock_gptmr2; + break; + case HPM_GPTMR3_BASE: + gptmr_clock = clock_gptmr3; + break; + default: + gptmr_valid = false; + } + if(gptmr_valid) + { + clock_add_to_group(gptmr_clock, 0); + clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4); + freq = clock_get_frequency(gptmr_clock); + } + return freq; +} diff --git a/bsp/hpmicro/hpm5300evk/board/board.h b/bsp/hpmicro/hpm5300evk/board/board.h new file mode 100644 index 00000000000..ab2718b88e4 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/board.h @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include +#include "hpm_common.h" +#include "hpm_clock_drv.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm5300evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_4 /* align with used pin */ + +/* dma section */ +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_HDMA +#define TEST_DMA_IRQ IRQn_HDMA + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif + +/* uart section */ +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART2 +#define BOARD_APP_UART_IRQ IRQn_UART2 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart2 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX +#endif + +/* uart lin sample section */ +#define BOARD_UART_LIN HPM_UART3 +#define BOARD_UART_LIN_IRQ IRQn_UART3 +#define BOARD_UART_LIN_CLK_NAME clock_uart3 +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOA +#define BOARD_UART_LIN_TX_PIN (15U) /* PA15 should align with used pin in pinmux configuration */ + + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif + +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_UART_BASE +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#endif +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif +#endif + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) /* Check */ +#define BOARD_FLASH_SIZE (SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR0 +#define BOARD_GPTMR_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM HPM_GPTMR0 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0 + +/* User LED */ +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LED_GPIO_PIN 23 + +#define BOARD_LED_OFF_LEVEL 1 +#define BOARD_LED_ON_LEVEL 0 + +/* 12V Power Enable for lin transceiver */ +#define BOARD_SUPPORT_LIN_TRANSCEIVER_CONTROL 1 +#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0 +#define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_12V_EN_GPIO_PIN 24 +#define BOARD_LIN_TRANSCEIVER_GPIO_CTRL HPM_GPIO0 +#define BOARD_LIN_TRANSCEIVER_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LIN_TRANSCEIVER_GPIO_PIN 13 + + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* User button */ +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_APP_GPIO_PIN 9 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI1 +#define BOARD_APP_SPI_CLK_NAME clock_spi1 +#define BOARD_APP_SPI_IRQ IRQn_SPI1 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PA26 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (13U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* DAC section */ +#define BOARD_DAC_BASE HPM_DAC0 +#define BOARD_DAC_IRQn IRQn_DAC0 +#define BOARD_APP_DAC_CLOCK_NAME clock_dac0 + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* SDXC section */ +#define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_SDCARD_SUPPORT_1V8 (0) + +/* MCAN section */ +#define BOARD_APP_CAN_BASE HPM_MCAN3 +#define BOARD_APP_CAN_IRQn IRQn_MCAN3 + +/* CALLBACK TIMER section */ +#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_mot0 +#define BOARD_APP_PWM_OUT1 2 +#define BOARD_APP_PWM_OUT2 3 +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM0 +#define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM0_SYNCI + +/*BLDC pwm*/ +/*PWM define*/ +#define BOARD_BLDCPWM HPM_PWM0 +#define BOARD_BLDC_UH_PWM_OUTPIN (6U) +#define BOARD_BLDC_UL_PWM_OUTPIN (7U) +#define BOARD_BLDC_VH_PWM_OUTPIN (4U) +#define BOARD_BLDC_VL_PWM_OUTPIN (5U) +#define BOARD_BLDC_WH_PWM_OUTPIN (2U) +#define BOARD_BLDC_WL_PWM_OUTPIN (3U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM0 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_INDEX_6 (6U) +#define BOARD_BLDCPWM_CMP_INDEX_7 (7U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) + +/*HALL define*/ + +/*RDC*/ +#define BOARD_RDC_TRGM HPM_TRGM0 +#define BOARD_RDC_TRGIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_RDC_TRGO_0 +#define BOARD_RDC_TRG_NUM TRGM_TRGOCFG_MOT_GPIO0 +#define BOARD_RDC_TRG_ADC_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_RDC_ADC_I_BASE HPM_ADC0 +#define BOARD_RDC_ADC_Q_BASE HPM_ADC1 +#define BOARD_RDC_ADC_I_CHN (5U) +#define BOARD_RDC_ADC_Q_CHN (6U) +#define BOARD_RDC_ADC_IRQn IRQn_ADC0 +#define BOARD_RDC_ADC_TRIG_FLAG adc16_event_trig_complete +#define BOARD_RDC_ADC_TRG ADC16_CONFIG_TRG0A + +/*QEI*/ +#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 +#define BOARD_BLDC_QEIV2_BASE HPM_QEI1 +#define BOARD_BLDC_QEIV2_IRQ IRQn_QEI1 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) +#define BOARD_BLDC_QEI_ADC_MATRIX_ADC0 trgm_adc_matrix_output_to_qei1_adc0 +#define BOARD_BLDC_QEI_ADC_MATRIX_ADC1 trgm_adc_matrix_output_to_qei1_adc1 + +/*Timer define*/ +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/*adc*/ +#define BOARD_BLDC_ADC_MODULE (ADCX_MODULE_ADC16) +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (5U) +#define BOARD_BLDC_ADC_CH_V (6U) +#define BOARD_BLDC_ADC_CH_W (4U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) +#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_PLB_COUNTER HPM_PLB +#define BOARD_PLB_PWM_BASE HPM_PWM0 +#define BOARD_PLB_PWM_CLOCK_NAME clock_mot0 +#define BOARD_PLB_TRGM HPM_TRGM0 +#define BOARD_PLB_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF) +#define BOARD_PLB_IN_PWM_TRG_NUM (TRGM_TRGOCFG_PLB_IN_00) +#define BOARD_PLB_IN_PWM_PULSE_TRG_NUM (TRGM_TRGOCFG_PLB_IN_02) +#define BOARD_PLB_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLB_OUT00) +#define BOARD_PLB_IO_TRG_NUM (TRGM_TRGOCFG_MOT_GPIO2) +#define BOARD_PLB_IO_TRG_SHIFT (2) +#define BOARD_PLB_PWM_CMP (8U) +#define BOARD_PLB_PWM_CHN (8U) +#define BOARD_PLB_CHN plb_chn0 + +/* QEO */ +#define BOARD_QEO HPM_QEO0 +#define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo0 + +/* moto */ +#define BOARD_MOTOR_CLK_NAME clock_mot0 + +/* SEI */ +#define BOARD_SEI HPM_SEI +#define BOARD_SEI_CTRL SEI_CTRL_1 +#define BOARD_SEI_IRQn IRQn_SEI1 + +/* USB */ +#define BOARD_USB HPM_USB0 + +/* OPAMP */ +#define BOARD_APP_OPAMP HPM_OPAMP0 + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR2 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr2 + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR2 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2 +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); +void board_init_gpio_pins(void); +void board_init_led_pins(void); +void board_init_usb_pins(void); +void board_led_write(uint8_t state); +void board_led_toggle(void); +void board_init_uart(UART_Type *ptr); +uint32_t board_init_spi_clock(SPI_Type *ptr); +void board_init_spi_pins(SPI_Type *ptr); +void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +void board_init_adc16_pins(void); +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); +void board_init_can(MCAN_Type *ptr); +uint32_t board_init_can_clock(MCAN_Type *ptr); +void board_init_rgb_pwm_pins(void); +void board_disable_output_rgb_led(uint8_t color); +void board_enable_output_rgb_led(uint8_t color); +void board_init_dac_pins(DAC_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); + +void board_init_usb_dp_dm_pins(void); +void board_init_clock(void); +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); + +uint8_t board_get_led_gpio_off_level(void); +uint8_t board_get_led_pwm_off_level(void); + +void board_init_pmp(void); + +uint32_t board_init_uart_clock(UART_Type *ptr); +void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); + +void board_init_i2c(I2C_Type *ptr); + +void board_init_adc_qeiv2_pins(void); + +void board_lin_transceiver_control(bool enable); +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); +uint32_t board_init_pwm_clock(PWM_Type *ptr); +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg new file mode 100644 index 00000000000..7d495f5b380 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/boards/hpm5300evk.cfg @@ -0,0 +1,79 @@ +# Copyright (c) 2023 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit 6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3000000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x7 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x6 0x1000 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +$_TARGET0 configure -event reset-init { + init_clock +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 00000000000..0aa1eed3dad --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 8000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 00000000000..782edbcf509 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 00000000000..e2c01a2d788 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 00000000000..5d565c0ecc3 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 00000000000..a9421a83877 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg new file mode 100644 index 00000000000..c57a36d0174 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/debug_scripts/openocd/soc/hpm5300.cfg @@ -0,0 +1,13 @@ +# Copyright (c) 2021 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm5301 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 diff --git a/bsp/hpmicro/hpm5300evk/board/fal_cfg.h b/bsp/hpmicro/hpm5300evk/board/fal_cfg.h new file mode 100644 index 00000000000..40d0330d450 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/fal_cfg.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern const struct fal_flash_dev stm32f2_onchip_flash; +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 256*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 512*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 768*1024, 256*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm5300evk/board/fal_flash_port.c b/bsp/hpmicro/hpm5300evk/board/fal_flash_port.c new file mode 100644 index 00000000000..1ed9fdffd69 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/fal_flash_port.c @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2022-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-01-31 hpmicro Fix random crashing issue if the global interrupt is always enabled + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + + +#define FAL_ENTER_CRITICAL() do {\ + disable_global_irq(CSR_MSTATUS_MIE_MASK);\ + }while(0) + +#define FAL_EXIT_CRITICAL() do {\ + enable_global_irq(CSR_MSTATUS_MIE_MASK);\ + }while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + s_flashcfg.device_info.clk_freq_for_non_read_cmd = 0U; + /* update the flash chip information */ + uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) +{ + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) +{ + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; + int ret = (int)size; + + uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, size_t size) +{ + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + uint32_t block_size; + uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld new file mode 100644 index 00000000000..7f3af8a529c --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld @@ -0,0 +1,288 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(8); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + . = ALIGN(8); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + __ramfunc_start__ = .; + *(.fast) + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + . = ALIGN(8); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM + + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > DLM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + /* __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); */ + +} diff --git a/bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld new file mode 100644 index 00000000000..196cbe56efe --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld @@ -0,0 +1,244 @@ +/* + * Copyright 2021-2023 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x2000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x8000; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x8000; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x98000, LENGTH = NONCACHEABLE_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > ILM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > ILM + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .tdata : AT(etext) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + .data : AT(etext + __tdata_end__ - __tdata_start__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__finit_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) + KEEP(*(.finit_array)) + PROVIDE(__finit_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + .fast : AT(etext + __data_end__ - __tdata_start__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > DLM + + .rel : { + KEEP(*(.rel*)) + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > DLM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); +} diff --git a/bsp/hpmicro/hpm5300evk/board/pinmux.c b/bsp/hpmicro/hpm5300evk/board/pinmux.c new file mode 100644 index 00000000000..2f17df67529 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/pinmux.c @@ -0,0 +1,325 @@ +/* + * Copyright (c) 2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ +#include "board.h" +#include "pinmux.h" + +void init_xtal_pins(void) +{ + /* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ +} + +void init_py_pins_as_pgpio(void) +{ + /* Set PY00-PY05 default function to PGPIO */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PGPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PGPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_PGPIO_Y_02; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_PGPIO_Y_03; + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_PGPIO_Y_04; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_PGPIO_Y_05; +} + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; + } else if (ptr == HPM_UART2) { + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_UART2_TXD; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_UART2_RXD; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART2_DE; + } else if (ptr == HPM_UART3) { + /* using for uart_lin function */ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_UART3_RXD; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_UART3_TXD; + } else if (ptr == HPM_UART7) { + /* using for uart_lin function */ + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_UART7_TXD; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_UART7_RXD; + } else { + ; + } +} + +void init_lin_transceiver_ctrl_pin(void) +{ + /* PA24 is used to control the 12V power supply of the LIN transceiver */ + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_GPIO_A_24; + /* PA13 is used to control the LIN transceiver not to enter sleep mode */ + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_GPIO_A_13; +} + +/* for uart_lin case, need to configure pin as gpio to sent break signal */ +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + /* pull-up */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + if (ptr == HPM_UART3) { + HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PA15].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_GPIO_A_14; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_GPIO_A_15; + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB03].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else if (ptr == HPM_I2C1) { + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB06].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB07].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + } else { + ; + } +} + +void init_gpio_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_SPI1_CS_1; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_SPI1_CS_0; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPIO_A_25; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + } +} + + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR0) { + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1; + } +} + +void init_hall_trgm_pins(void) +{ + init_qeiv2_uvw_pins(HPM_QEI1); +} + +void init_qei_trgm_pins(void) +{ + init_qeiv2_ab_pins(HPM_QEI1); +} + +void init_butn_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; + HPM_IOC->PAD[IOC_PAD_PA09].PAD_CTL = pad_ctl; +} + +void init_acmp_pins(void) +{ + /* configure to ACMP_COMP_1(ALT16) function */ + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_ACMP_COMP_1; + /* configure to CMP1_INN4 function */ + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_pwm_pins(PWM_Type *ptr) +{ + if (ptr == HPM_PWM0) { + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_PWM0_P_2; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_PWM0_P_3; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_PWM0_P_4; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_PWM0_P_5; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_PWM0_P_6; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_PWM0_P_7; + } +} + +void init_adc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC0.13 */ +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */ +} + +void init_adc_qeiv2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.4 /ADC1.4 */ + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ +} + +void init_usb_pins(void) +{ + /* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ + + /* Package QFN32 should be set PA26 and PA27 pins as analog type to enable USB_P and USB_N. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ + + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR; + + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; +} + +void init_can_pins(MCAN_Type *ptr) +{ + if (ptr == HPM_MCAN3) { + HPM_IOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_MCAN3_RXD; + HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_MCAN3_TXD; + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_SOC_GPIO_Y_04; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_GPIO_Y_05; + } +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPIO_A_23; +} + +void init_led_pins_as_pwm(void) +{ + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_TRGM0_P_03; +} + +void init_dac_pins(DAC_Type *ptr) +{ + if (ptr == HPM_DAC0) { + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC0.OUT */ + } else if (ptr == HPM_DAC1) { + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC1.OUT */ + } +} + +void init_plb_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02; +} + +void init_qeo_pins(QEO_Type *ptr) +{ + if (ptr == HPM_QEO0) { + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_QEO0_A; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_QEO0_B; + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_QEO0_Z; + } +} + +void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) +{ + if (ptr == HPM_SEI) { + if (sei_ctrl_idx == SEI_CTRL_1) { + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_SEI1_DE; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_SEI1_CK; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_SEI1_TX; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_SEI1_RX; + } + } +} + +void init_rdc_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_RDC0_EXC_P; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + +/*The GPIO is designed for debug */ +#ifdef RDC_SAMPLE_TEST_GPIO_OUTPUT + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_TRGM0_P_00; +#endif +} + +void init_qeiv2_uvw_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI1) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_QEI1_Z; + } +} + +void init_qeiv2_ab_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI1) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; + } +} + +void init_qeiv2_abz_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI1) { + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_QEI1_A; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_QEI1_B; + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_QEI1_Z; + } +} + +void init_opamp_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} diff --git a/bsp/hpmicro/hpm5300evk/board/pinmux.h b/bsp/hpmicro/hpm5300evk/board/pinmux.h new file mode 100644 index 00000000000..1ff17798655 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/pinmux.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_xtal_pins(void); +void init_py_pins_as_pgpio(void); +void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_pwm_pins(PWM_Type *ptr); +void init_adc_pins(void); +void init_adc_bldc_pins(void); +void init_adc_qeiv2_pins(void); +void init_usb_pins(void); +void init_can_pins(MCAN_Type *ptr); +void init_dac_pins(DAC_Type *ptr); +void init_led_pins_as_gpio(void); +void init_led_pins_as_pwm(void); +void init_plb_pins(void); +void init_qeo_pins(QEO_Type *ptr); +void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); +void init_rdc_pin(void); +void init_qeiv2_uvw_pins(QEIV2_Type *ptr); +void init_qeiv2_ab_pins(QEIV2_Type *ptr); +void init_qeiv2_abz_pins(QEIV2_Type *ptr); +void init_opamp_pins(void); +void init_lin_transceiver_ctrl_pin(void); +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm5300evk/board/rtt_board.c b/bsp/hpmicro/hpm5300evk/board/rtt_board.c new file mode 100644 index 00000000000..407d5ac9ecd --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/rtt_board.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" + +extern int rt_hw_uart_init(void); +void os_tick_config(void); +void rtt_board_init(void); + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_mgr_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Configure the USB pins*/ + board_init_usb_pins(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL); +} + +void app_led_write(uint32_t index, bool state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void BOARD_LED_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +void app_init_usb_pins(void) +{ + board_init_usb_pins(); +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE = (1UL << 31); + + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); diff --git a/bsp/hpmicro/hpm5300evk/board/rtt_board.h b/bsp/hpmicro/hpm5300evk/board/rtt_board.h new file mode 100644 index 00000000000..78b51752c62 --- /dev/null +++ b/bsp/hpmicro/hpm5300evk/board/rtt_board.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2021 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" +#include + +/* gpio section */ +#define APP_LED0_PIN_NUM GET_PIN(A, 23) +#define APP_LED_ON (1) +#define APP_LED_OFF (0) + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* CAN section */ +#define BOARD_CAN_NAME "can0" +#define BOARD_CAN_HWFILTER_INDEX (0U) + +/* UART section */ +#define BOARD_UART_NAME "uart2" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE + +/* PWM section */ +#define BOARD_PWM_NAME "pwm0" +#define BOARD_PWM_CHANNEL (6) + +#define IRQn_PendSV IRQn_DEBUG0 + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); +void app_init_usb_pins(void); + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + + + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm5300evk/figures/board.png b/bsp/hpmicro/hpm5300evk/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..35c083c12082a7ecac68634ed58037c110c0563d GIT binary patch literal 374390 zcmV)(K#RYLP)z4^0U$8jc@nN?@G%i94ETmTRxK~mf#k`k${P0?-1 zZp&@AyQ3#2VtVFZn_qe&x_fN3Wm#=%m#mGFOmW{y0K~q%{ch(}W#;^lRp(y32Quac z0lataId!VCvNFH?GOLKM{PA@nL_}3pRRBOlP_--ew_UU!x=(k-ZUX=j>8>As>cHb& z( zOV<42sEJ5Kx}M}Wrh5(x^RP_rcyaNoMUgJP`gS=Z5sJ*;f{2S9TYS;{bwr)y?>K9V z!?~>+0Aiw41w{K|@u|hP+YFJ3^)~sSfGUWBqSB{zl8El85(iY}@TY646W4+E55Ma` z%ZpQUKop%0AMVED)Wd?pA9&V8)M*hBEw=d?Pu(_yw-4m-{h#*j9eca@)Zz`@R4z*9 z)5d36<9F=pVfh>o%ctFcSXPG>U_Q&;6#&!lJKj%-bf_DL2R^q{ zhoKR|1`BfJma5XbL@(}>yFBNSncn4y}NkF7T``3eRxS891$WZD5MrU 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