diff --git a/.github/labeler.yml b/.github/labeler.yml index 8729ad37db8..324f3f0a868 100644 --- a/.github/labeler.yml +++ b/.github/labeler.yml @@ -72,17 +72,169 @@ Component: - changed-files: - any-glob-to-any-file: components/** +RT-Smart: +- changed-files: + - any-glob-to-any-file: components/lwp/** + 'component: lwp': - changed-files: - - any-glob-to-any-file: components/lwp** + - any-glob-to-any-file: components/lwp/** 'component: dfsv1': - changed-files: - - any-glob-to-any-file: components/dfs_v1** + - any-glob-to-any-file: components/dfs_v1/** 'component: dfsv2': - changed-files: - - any-glob-to-any-file: components/dfs_v2** + - any-glob-to-any-file: components/dfs_v2/** + +'component: net': +- changed-files: + - any-glob-to-any-file: components/net/** + +'component: net/at': +- changed-files: + - any-glob-to-any-file: components/net/at/** + +'component: net/lwip': +- changed-files: + - any-glob-to-any-file: components/net/lwip/** + +'component: net/netdev': +- changed-files: + - any-glob-to-any-file: components/net/netdev/** + +'component: net/sal': +- changed-files: + - any-glob-to-any-file: components/net/sal/** + +'component: drivers': +- changed-files: + - any-glob-to-any-file: components/drivers/** + +'component: drivers/audio': +- changed-files: + - any-glob-to-any-file: components/drivers/audio/** + +'component: drivers/can': +- changed-files: + - any-glob-to-any-file: components/drivers/can/** + +'component: drivers/clk': +- changed-files: + - any-glob-to-any-file: components/drivers/clk/** + +'component: drivers/core': +- changed-files: + - any-glob-to-any-file: components/drivers/core/** + +'component: drivers/cputime': +- changed-files: + - any-glob-to-any-file: components/drivers/cputime/** + +'component: drivers/graphic': +- changed-files: + - any-glob-to-any-file: components/drivers/graphic/** + +'component: drivers/hwcrypto': +- changed-files: + - any-glob-to-any-file: components/drivers/hwcrypto/** + +'component: drivers/hwtimer': +- changed-files: + - any-glob-to-any-file: components/drivers/hwtimer/** + +'component: drivers/i2c': +- changed-files: + - any-glob-to-any-file: components/drivers/i2c/** + +'component: drivers/ipc': +- changed-files: + - any-glob-to-any-file: components/drivers/ipc/** + +'component: drivers/ktime': +- changed-files: + - any-glob-to-any-file: components/drivers/ktime/** + +'component: drivers/misc': +- changed-files: + - any-glob-to-any-file: components/drivers/misc/** + +'component: drivers/mtd': +- changed-files: + - any-glob-to-any-file: components/drivers/mtd/** + +'component: drivers/ofw': +- changed-files: + - any-glob-to-any-file: components/drivers/ofw/** + +'component: drivers/pci': +- changed-files: + - any-glob-to-any-file: components/drivers/pci/** + +'component: drivers/phy': +- changed-files: + - any-glob-to-any-file: components/drivers/phy/** + +'component: drivers/pic': +- changed-files: + - any-glob-to-any-file: components/drivers/pic/** + +'component: drivers/pinctrl': +- changed-files: + - any-glob-to-any-file: components/drivers/pinctrl/** + +'component: drivers/pm': +- changed-files: + - any-glob-to-any-file: components/drivers/pm/** + +'component: drivers/rtc': +- changed-files: + - any-glob-to-any-file: components/drivers/rtc/** + +'component: drivers/sdio': +- changed-files: + - any-glob-to-any-file: components/drivers/sdio/** + +'component: drivers/sensor_v1': +- changed-files: + - any-glob-to-any-file: components/drivers/sensor/v1/** + +'component: drivers/sensor_v2': +- changed-files: + - any-glob-to-any-file: components/drivers/sensor/v2/** + +'component: drivers/serial': +- changed-files: + - any-glob-to-any-file: components/drivers/serial/** + +'component: drivers/spi': +- changed-files: + - any-glob-to-any-file: components/drivers/spi/** + +'component: drivers/touch': +- changed-files: + - any-glob-to-any-file: components/drivers/touch/** + +'component: drivers/usb': +- changed-files: + - any-glob-to-any-file: components/drivers/usb/** + +'component: drivers/virtio': +- changed-files: + - any-glob-to-any-file: components/drivers/virtio/** + +'component: drivers/watchdog': +- changed-files: + - any-glob-to-any-file: components/drivers/watchdog/** + +'component: drivers/wlan': +- changed-files: + - any-glob-to-any-file: components/drivers/wlan/** + +'component: finsh': +- changed-files: + - any-glob-to-any-file: components/finsh/** libcpu: - changed-files: diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index 5a2a90d68da..ed9f9005359 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -234,6 +234,7 @@ jobs: - "renesas/ra8d1-ek" - "renesas/ra8d1-vision-board" - "renesas/rzt2m_rsk" + - "renesas/rzn2l_rsk" - "frdm-k64f" - "xplorer4330/M4" - RTT_BSP: "gd32_n32_apm32" diff --git a/.github/workflows/doxygen.yml b/.github/workflows/doxygen.yml index 447c66634c8..a4580be1be1 100644 --- a/.github/workflows/doxygen.yml +++ b/.github/workflows/doxygen.yml @@ -3,27 +3,13 @@ on: # Runs at 16:00 UTC (BeiJing 00:00) on the 30st of every month schedule: - cron: '0 16 30 * *' - push: - branches: - - master - paths-ignore: - - '**/README.md' - - '**/README_zh.md' - pull_request: - branches: - - master - paths-ignore: - - bsp/** - - examples/** - - .github/** - - '**/README.md' - - '**/README_zh.md' + workflow_dispatch: jobs: build: runs-on: ubuntu-latest name: doxygen_doc generate - if: github.repository_owner == 'RT-Thread' && false + if: github.repository_owner == 'RT-Thread' steps: - uses: actions/checkout@v4 with: diff --git a/.github/workflows/file_check.yml b/.github/workflows/format_check.yml similarity index 100% rename from .github/workflows/file_check.yml rename to .github/workflows/format_check.yml diff --git a/.github/workflows/spell_check.yml b/.github/workflows/spell_check.yml index af0942c2783..1cc6a91d8c0 100644 --- a/.github/workflows/spell_check.yml +++ b/.github/workflows/spell_check.yml @@ -1,11 +1,6 @@ name: Check Spelling on: - push: - branches: - - master - paths: - - 'documentation/**' pull_request: branches: - master diff --git a/bsp/apm32/apm32f030r8-miniboard/applications/main.c b/bsp/apm32/apm32f030r8-miniboard/applications/main.c index b341b8f997a..e0c781e2e13 100644 --- a/bsp/apm32/apm32f030r8-miniboard/applications/main.c +++ b/bsp/apm32/apm32f030r8-miniboard/applications/main.c @@ -17,11 +17,10 @@ int main(void) { - int count = 1; /* set LED2 pin mode to output */ rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED2_PIN, PIN_HIGH); rt_thread_mdelay(500); diff --git a/bsp/apm32/apm32f051r8-evalboard/applications/main.c b/bsp/apm32/apm32f051r8-evalboard/applications/main.c index 421afebe8dc..71e6e6605ca 100644 --- a/bsp/apm32/apm32f051r8-evalboard/applications/main.c +++ b/bsp/apm32/apm32f051r8-evalboard/applications/main.c @@ -17,11 +17,10 @@ int main(void) { - int count = 1; /* set LED2 pin mode to output */ rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); - while (count++) + while (1) { rt_pin_write(LED1_PIN, PIN_HIGH); rt_thread_mdelay(500); diff --git a/bsp/cvitek/drivers/drv_pinmux.h b/bsp/cvitek/drivers/drv_pinmux.h index 56f228d2653..0bc989a86c3 100644 --- a/bsp/cvitek/drivers/drv_pinmux.h +++ b/bsp/cvitek/drivers/drv_pinmux.h @@ -12,22 +12,29 @@ /** * @brief Function Selection Type - * - * FIXME: At present, we only define the ones we will use, - * not all of them. We will need to add them later. */ typedef enum _fs_type { fs_none = 0, + ADC1, + ADC2, + ADC3, AUX0, AUX1, AUX2, CAM_HS0, CAM_MCLK0, CAM_MCLK1, + CAM_PD0, + CAM_PD1, + CAM_RST0, CAM_VS0, CLK25M, CLK32K, + CR_4WTDI, + CR_4WTDO, + CV_SCL0, + CV_SDA0, DBG_0, DBG_1, DBG_2, @@ -49,6 +56,10 @@ typedef enum _fs_type DBG_19, EMMC_CLK, EMMC_CMD, + EMMC_DAT0, + EMMC_DAT1, + EMMC_DAT2, + EMMC_DAT3, EMMC_DAT_0, EMMC_DAT_1, EMMC_DAT_2, @@ -56,6 +67,8 @@ typedef enum _fs_type EMMC_RSTN, EPHY_LNK_LED, EPHY_SPD_LED, + GPIO_RTX, + GPIO_ZQ, IIC0_SCL, IIC0_SDA, IIC1_SCL, @@ -95,9 +108,41 @@ typedef enum _fs_type MUX_SPI1_MISO, MUX_SPI1_MOSI, MUX_SPI1_SCK, + PAD_AUD_AINL_MIC, + PAD_AUD_AINR_MIC, + PAD_AUD_AOUTL, + PAD_AUD_AOUTR, + PAD_ETH_RXM, + PAD_ETH_RXP, + PAD_ETH_TXM, + PAD_ETH_TXP, + PAD_MIPIRX0N, + PAD_MIPIRX0P, + PAD_MIPIRX1N, + PAD_MIPIRX1P, + PAD_MIPIRX2N, + PAD_MIPIRX2P, + PAD_MIPIRX3N, + PAD_MIPIRX3P, + PAD_MIPIRX4N, + PAD_MIPIRX4P, + PAD_MIPIRX5N, + PAD_MIPIRX5P, + PAD_MIPI_TXM0, + PAD_MIPI_TXM1, + PAD_MIPI_TXM2, + PAD_MIPI_TXM3, + PAD_MIPI_TXM4, + PAD_MIPI_TXP0, + PAD_MIPI_TXP1, + PAD_MIPI_TXP2, + PAD_MIPI_TXP3, + PAD_MIPI_TXP4, PKG_TYPE0, PKG_TYPE1, PKG_TYPE2, + PTEST, + PWM0_BUCK, PWM_0, PWM_1, PWM_2, @@ -115,6 +160,9 @@ typedef enum _fs_type PWM_14, PWM_15, PWR_BUTTON1, + PWR_GPIO0, + PWR_GPIO1, + PWR_GPIO2, PWR_GPIO_0, PWR_GPIO_1, PWR_GPIO_2, @@ -195,12 +243,22 @@ typedef enum _fs_type RMII0_TXD1, RMII0_TXEN, RSTN, + SD0_CD, + SD0_CLK, + SD0_CMD, + SD0_D0, + SD0_D1, + SD0_D2, + SD0_D3, + SD0_PWR_EN, SD1_CLK, SD1_CMD, SD1_D0, SD1_D1, SD1_D2, SD1_D3, + SD1_GPIO0, + SD1_GPIO1, SDIO0_CD, SDIO0_CLK, SDIO0_CMD, @@ -237,6 +295,7 @@ typedef enum _fs_type SPINOR_MOSI, SPINOR_SCK, SPINOR_WP_X, + SPK_EN, UART0_RX, UART0_TX, UART1_CTS, @@ -304,6 +363,18 @@ typedef enum _fs_type VI2_D_5, VI2_D_6, VI2_D_7, + VIVO_CLK, + VIVO_D0, + VIVO_D1, + VIVO_D2, + VIVO_D3, + VIVO_D4, + VIVO_D5, + VIVO_D6, + VIVO_D7, + VIVO_D8, + VIVO_D9, + VIVO_D10, VO_CLK0, VO_CLK1, VO_D_0, @@ -429,6 +500,7 @@ typedef enum _fs_type XGPIOC_23, XGPIOC_24, XGPIOC_25, + XTAL_XIN, } fs_type; /** diff --git a/bsp/k230/.config b/bsp/k230/.config new file mode 100644 index 00000000000..5a8eb350484 --- /dev/null +++ b/bsp/k230/.config @@ -0,0 +1,1360 @@ + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_HOOKLIST=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y + +# +# kservice optimization +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice optimization + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG=y +# end of klibc optimization + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_PAGE_MAX_ORDER=11 +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +CONFIG_RT_USING_DEVICE_OPS=y +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_SCHED_THREAD_CTX=y +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart" +CONFIG_RT_VER_NUM=0x50200 +CONFIG_RT_USING_STDC_ATOMIC=y +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +CONFIG_ARCH_MM_MMU=y +CONFIG_KERNEL_VADDR_START=0xFFFFFFC000220000 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV_FPU=y +CONFIG_ARCH_RISCV_FPU_D=y +CONFIG_ARCH_RISCV64=y +CONFIG_ARCH_USING_NEW_CTX_SWITCH=y +CONFIG_ARCH_REMAP_KERNEL=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=8192 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V2=y +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +# CONFIG_RT_DFS_ELM_USE_EXFAT is not set +# end of elm-chan's FatFs, Generic FAT Filesystem Module + +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +CONFIG_RT_USING_DFS_PTYFS=y +CONFIG_RT_USING_DFS_CROMFS=y +CONFIG_RT_USING_DFS_TMPFS=y +# CONFIG_RT_USING_DFS_MQUEUE is not set +CONFIG_RT_USING_PAGECACHE=y + +# +# page cache config +# +CONFIG_RT_PAGECACHE_COUNT=4096 +CONFIG_RT_PAGECACHE_ASPACE_COUNT=1024 +CONFIG_RT_PAGECACHE_PRELOAD=4 +CONFIG_RT_PAGECACHE_HASH_NR=1024 +CONFIG_RT_PAGECACHE_GC_WORK_LEVEL=90 +CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70 +# end of page cache config +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +CONFIG_RT_USING_CPUTIME=y +CONFIG_RT_USING_CPUTIME_RISCV=y +CONFIG_CPUTIME_TIMER_FREQ=25000000 +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=8192 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=8192 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_KTIME=y +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +CONFIG_RT_USING_POSIX_DEVIO=y +CONFIG_RT_USING_POSIX_STDIO=y +CONFIG_RT_USING_POSIX_POLL=y +CONFIG_RT_USING_POSIX_SELECT=y +# CONFIG_RT_USING_POSIX_EVENTFD is not set +CONFIG_RT_USING_POSIX_EPOLL=y +CONFIG_RT_USING_POSIX_SIGNALFD=y +CONFIG_RT_SIGNALFD_MAX_NUM=10 +# CONFIG_RT_USING_POSIX_TIMERFD is not set +CONFIG_RT_USING_POSIX_SOCKET=y +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set +CONFIG_RT_USING_POSIX_DELAY=y +CONFIG_RT_USING_POSIX_CLOCK=y +CONFIG_RT_USING_POSIX_TIMER=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +# end of Docking with protocol stacks + +CONFIG_SAL_USING_POSIX=y +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_LINK_STATUS_CALLBACK is not set +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=8 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +# end of Static IPv4 Address + +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=8192 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=8192 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_RT_LWIP_NETIF_NAMESIZE=6 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_DEBUG is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_RESOURCE_ID=y +CONFIG_RT_USING_ADT=y +CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set +CONFIG_RT_USING_LWP=y +CONFIG_LWP_DEBUG=y +CONFIG_LWP_DEBUG_INIT=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +CONFIG_RT_USING_LDSO=y +# CONFIG_ELF_DEBUG_ENABLE is not set +# CONFIG_ELF_LOAD_RANDOMIZE is not set +CONFIG_LWP_USING_TERMINAL=y +CONFIG_LWP_PTY_MAX_PARIS_LIMIT=64 + +# +# Memory management +# +# CONFIG_RT_USING_MEMBLOCK is not set +# end of Memory management + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +CONFIG_PKG_USING_ZLIB=y +CONFIG_PKG_ZLIB_PATH="/packages/misc/zlib" +# CONFIG_ZLIB_USING_SAMPLE is not set +# CONFIG_PKG_USING_ZLIB_V100 is not set +# CONFIG_PKG_USING_ZLIB_V123 is not set +CONFIG_PKG_USING_ZLIB_LATEST_VERSION=y +CONFIG_PKG_ZLIB_VER="latest" +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# +# Drivers Configuration +# +# CONFIG_BSP_USING_SDIO is not set +# end of Drivers Configuration + +CONFIG_BOARD_fpgac908=y +CONFIG___STACKSIZE__=8192 +CONFIG_C908_PLIC_PHY_ADDR=0xF00000000 +CONFIG_BSP_ROOTFS_TYPE_CROMFS=y diff --git a/bsp/k230/.gitignore b/bsp/k230/.gitignore new file mode 100644 index 00000000000..fffebd9e3ab --- /dev/null +++ b/bsp/k230/.gitignore @@ -0,0 +1,9 @@ +#Build & install directories +build/ +packages/ +install/ + +rtthread.* + +__pycache__ +.config.old diff --git a/bsp/k230/Kconfig b/bsp/k230/Kconfig new file mode 100644 index 00000000000..e8d957f1fd9 --- /dev/null +++ b/bsp/k230/Kconfig @@ -0,0 +1,46 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +rsource "board/Kconfig" + +config BOARD_fpgac908 + bool + select ARCH_RISCV64 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_CACHE + select ARCH_MM_MMU + select ARCH_RISCV_FPU_D + select ARCH_REMAP_KERNEL if RT_USING_SMART + default y + +config __STACKSIZE__ + int "stack size for interrupt" + default 4096 + +config C908_PLIC_PHY_ADDR + int "PLIC base address" + default 0xF00000000 + +config BSP_ROOTFS_TYPE_CROMFS + bool "Use CROMFS as ROOTFS" + select RT_USING_DFS_CROMFS + select PKG_USING_ZLIB + select PKG_USING_ZLIB_LATEST_VERSION + default y diff --git a/bsp/k230/README.md b/bsp/k230/README.md new file mode 100644 index 00000000000..66b5f3d5592 --- /dev/null +++ b/bsp/k230/README.md @@ -0,0 +1,38 @@ +# rt-smart canaan porting + +## 下载依赖的软件包 + +在软件包无需变更的情况下只须执行一次 +``` +source ~/.env/env.sh +pkgs --update +``` + +## 将根文件系统编译进内核 + +为了方便测试，这里将根文件系统制作成CROMFS格式转换成C代码编译进内核。 + +1. 在 https://github.com/RT-Thread/userapps 页面下载riscv64预编译镜像 +2. 解压后将其中的ext4.img挂载到一个目录中 +``` +sudo mount ext4.img dir +``` +3. 删除其中一些不必要的文件以减小内核体积 +``` +du -ha # 查看文件大小 +sudo rm -rf dir/www dir/usr/share/fonts dir/tc + +``` +4. 生成cromfs文件 +工具位于 https://github.com/RT-Thread/userapps/tree/main/tools/cromfs +``` +sudo ./cromfs-tool-x64 dir crom.img ./ # 将生成的cromfs_data.c放入applications目录 +``` + +## 编译 + +``` +export RTT_EXEC_PATH=/mnt/e/tools/riscv64gc/bin # 你自己的编译器路径 + +scons -j8 +``` diff --git a/bsp/k230/SConscript b/bsp/k230/SConscript new file mode 100644 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/k230/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/k230/SConstruct b/bsp/k230/SConstruct new file mode 100644 index 00000000000..c800dc6f5ce --- /dev/null +++ b/bsp/k230/SConstruct @@ -0,0 +1,37 @@ +import os +import sys +import rtconfig + +from rtconfig import RTT_ROOT +import sys + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False) + +stack_size = 4096 + +stack_lds = open('link_stacksize.lds', 'w') +if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__') +stack_lds.write('__STACKSIZE__ = %d;' % stack_size) +stack_lds.close() + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/k230/applications/SConscript b/bsp/k230/applications/SConscript new file mode 100644 index 00000000000..9ffdfd6d3ac --- /dev/null +++ b/bsp/k230/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/k230/applications/main.c b/bsp/k230/applications/main.c new file mode 100644 index 00000000000..664f925e156 --- /dev/null +++ b/bsp/k230/applications/main.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + */ + +#include +#include +#include +#include + +int main(void) +{ + printf("Hello RISC-V\n"); + + return 0; +} diff --git a/bsp/k230/applications/mnt.c b/bsp/k230/applications/mnt.c new file mode 100644 index 00000000000..931dac0933d --- /dev/null +++ b/bsp/k230/applications/mnt.c @@ -0,0 +1,58 @@ +#include + +#ifdef RT_USING_DFS +#include + +rt_weak uint8_t *cromfs_get_partition_data(uint32_t *len) +{ + return RT_NULL; +} + +static int mnt_cromfs(void) +{ + uint32_t length = 0; + uint8_t *data = cromfs_get_partition_data(&length); + int ret = -1; + + if (data && length) + { + ret = dfs_mount(NULL, "/", "crom", 0, data); + } + + return ret; +} + +int mnt_init(void) +{ + rt_err_t ret; + + ret = mnt_cromfs(); + if (ret != RT_EOK) + { + rt_kprintf("CromFS mount failed!\n"); + return ret; + } + + mkdir("/dev/shm", 0x777); + + if (dfs_mount(RT_NULL, "/dev/shm", "tmp", 0, 0) != 0) + { + rt_kprintf("Dir /dev/shm mount failed!\n"); + } + +#ifdef BSP_SD_SDIO_DEV + while (mmcsd_wait_cd_changed(100) != MMCSD_HOST_PLUGED) + ; + + if (dfs_mount(BSP_SD_MNT_DEVNAME, "/mnt", "elm", 0, 0) != 0) + { + rt_kprintf("Dir /mnt mount failed!\n"); + } +#endif + + rt_kprintf("file system initialization done!\n"); + + return 0; +} +INIT_ENV_EXPORT(mnt_init); +#endif diff --git a/bsp/k230/board/Kconfig b/bsp/k230/board/Kconfig new file mode 100644 index 00000000000..df2ac7fa070 --- /dev/null +++ b/bsp/k230/board/Kconfig @@ -0,0 +1,38 @@ +menu "Drivers Configuration" + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + default n + + if BSP_USING_SDIO + config BSP_USING_SDIO0 + bool "Enable SDIO0" + default n + + if BSP_USING_SDIO0 + config BSP_SDIO0_EMMC + bool "Enable eMMC" + default y + + config BSP_SDIO0_1V8 + bool "Enable 1.8V" + default y + endif + + config BSP_USING_SDIO1 + bool "Enable SDIO1" + default y + + config BSP_SD_SDIO_DEV + int "SDIO device SdCard on" + range 0 1 + default 1 + + config BSP_SD_MNT_DEVNAME + string "The name of the SD-BlkDev to be mounted" + default "sd13" + endif + + +endmenu diff --git a/bsp/k230/board/SConscript b/bsp/k230/board/SConscript new file mode 100644 index 00000000000..faea9c1bd9b --- /dev/null +++ b/bsp/k230/board/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +objs = [group] + +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/k230/board/board.c b/bsp/k230/board/board.c new file mode 100644 index 00000000000..14e35beee3a --- /dev/null +++ b/bsp/k230/board/board.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#include +#include +#include + +#include "board.h" +#include "tick.h" + +#include "drv_uart.h" + +#include + +#ifdef RT_USING_SMART +#include +#include "page.h" + +/* respect to boot loader, must be 0xFFFFFFC000200000 */ +RT_STATIC_ASSERT(kmem_region, KERNEL_VADDR_START == 0xFFFFFFC000220000); + +rt_region_t init_page_region = {(rt_size_t)RT_HW_PAGE_START, (rt_size_t)RT_HW_PAGE_END}; + +extern size_t MMUTable[]; + +struct mem_desc platform_mem_desc[] = { + {KERNEL_VADDR_START, (rt_size_t)RT_HW_PAGE_END - 1, (rt_size_t)ARCH_MAP_FAILED, NORMAL_MEM}, +}; + +#define NUM_MEM_DESC (sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0])) + +#endif /* RT_USING_SMART */ + +#ifndef ARCH_REMAP_KERNEL +#define IOREMAP_VEND USER_VADDR_START +#else +#define IOREMAP_VEND 0ul +#endif + +//初始化BSS节区 +void init_bss(void) +{ + unsigned int *dst; + + dst = &__bss_start; + while (dst < &__bss_end) + { + *dst++ = 0; + } +} + +static void __rt_assert_handler(const char *ex_string, const char *func, rt_size_t line) +{ + rt_kprintf("(%s) assertion failed at function:%s, line number:%d \n", ex_string, func, line); + asm volatile("ebreak":::"memory"); +} + +//BSP的C入口 +void primary_cpu_entry(void) +{ + //关中断 + rt_hw_interrupt_disable(); + rt_assert_set_hook(__rt_assert_handler); + //启动RT-Thread Smart内核 + entry(); +} + +#define IOREMAP_SIZE (1ul << 30) + +//这个初始化程序由内核主动调用，此时调度器还未启动，因此在此不能使用依赖线程上下文的函数 +void rt_hw_board_init(void) +{ +#ifdef RT_USING_SMART + /* init data structure */ + rt_hw_mmu_map_init(&rt_kernel_space, (void *)(IOREMAP_VEND - IOREMAP_SIZE), IOREMAP_SIZE, (rt_size_t *)MMUTable, PV_OFFSET); + + /* init page allocator */ + rt_page_init(init_page_region); + + /* setup region, and enable MMU */ + rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, NUM_MEM_DESC); +#endif + +#ifdef RT_USING_HEAP + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); +#endif + /* initalize interrupt */ + rt_hw_interrupt_init(); + + /* initialize hardware interrupt */ + rt_hw_uart_init(); + + rt_hw_tick_init(); + +#ifdef RT_USING_CONSOLE + /* set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif /* RT_USING_CONSOLE */ + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +void rt_hw_cpu_reset(void) +{ + sbi_shutdown(); + while(1); +} +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); diff --git a/bsp/k230/board/board.h b/bsp/k230/board/board.h new file mode 100644 index 00000000000..1947c2b0bb3 --- /dev/null +++ b/bsp/k230/board/board.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + */ + +#ifndef BOARD_H__ +#define BOARD_H__ + +#include + +extern unsigned int __sram_size; +extern unsigned int __sram_base; +extern unsigned int __sram_end; +#define RAM_END (rt_size_t)((void *)&__sram_end) + +extern unsigned int __bss_start; +extern unsigned int __bss_end; + +#define RT_HW_HEAP_BEGIN ((void *)&__bss_end) +#define RT_HW_HEAP_END ((void *)(((rt_size_t)RT_HW_HEAP_BEGIN) + 8 * 1024 * 1024)) + +#define RT_HW_PAGE_START ((void *)((rt_size_t)RT_HW_HEAP_END + sizeof(rt_size_t))) +#define RT_HW_PAGE_END ((void *)(RAM_END)) + +void rt_hw_board_init(void); +void rt_init_user_mem(struct rt_thread *thread, const char *name, unsigned long *entry); + +#endif diff --git a/bsp/k230/drivers/SConscript b/bsp/k230/drivers/SConscript new file mode 100644 index 00000000000..1b5c289ce1a --- /dev/null +++ b/bsp/k230/drivers/SConscript @@ -0,0 +1,21 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = [] +CPPPATH = [cwd] + +src += Glob('*.c') + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +objs = [group] + +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/k230/drivers/interdrv/SConscript b/bsp/k230/drivers/interdrv/SConscript new file mode 100644 index 00000000000..7af43915886 --- /dev/null +++ b/bsp/k230/drivers/interdrv/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Interdrv', src, depend = [''], CPPPATH = CPPPATH) + +objs = [group] + +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/k230/drivers/interdrv/sdio/SConscript b/bsp/k230/drivers/interdrv/sdio/SConscript new file mode 100644 index 00000000000..9d22e04def8 --- /dev/null +++ b/bsp/k230/drivers/interdrv/sdio/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Sdio', src, depend = ['BSP_USING_SDIO'], CPPPATH = CPPPATH) + +objs = [group] + +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/k230/drivers/interdrv/sdio/drv_sdhci.c b/bsp/k230/drivers/interdrv/sdio/drv_sdhci.c new file mode 100644 index 00000000000..cef781ddc58 --- /dev/null +++ b/bsp/k230/drivers/interdrv/sdio/drv_sdhci.c @@ -0,0 +1,930 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2017-10-10 Tanek first version + * 2021-07-07 linzhenxing add sd card drivers in mmu + * 2021-07-14 linzhenxing add emmc + */ + +#include +#include +#include + +#include "board.h" +#include "drv_sdhci.h" +#include "riscv_io.h" +#include +#include +#include + +#ifdef RT_USING_SDIO + +#define DBG_TAG "drv_sdhci" +#ifdef RT_SDIO_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_WARNING +#endif /* RT_SDIO_DEBUG */ +#include + +#if defined(BSP_USING_SDIO0) || defined(BSP_USING_SDIO1) + +#define SDHCI_SDMA_ENABLE +#define CACHE_LINESIZE (64) + +#define BIT(x) (1 << x) +#define DWC_MSHC_PTR_VENDOR1 0x500 +#define MSHC_CTRL_R (DWC_MSHC_PTR_VENDOR1 + 0x08) +#define EMMC_CTRL_R (DWC_MSHC_PTR_VENDOR1 + 0x2c) +#define SDHCI_VENDER_AT_CTRL_REG (DWC_MSHC_PTR_VENDOR1 + 0x40) +#define SDHCI_VENDER_AT_STAT_REG (DWC_MSHC_PTR_VENDOR1 + 0x44) +#define SDHCI_TUNE_CLK_STOP_EN_MASK BIT(16) +#define SDHCI_TUNE_SWIN_TH_VAL_LSB (24) +#define SDHCI_TUNE_SWIN_TH_VAL_MASK (0xFF) +#define CARD_IS_EMMC 0 +#define EMMC_RST_N 2 +#define EMMC_RST_N_OE 3 + +#define DWC_MSHC_PTR_PHY_REGS 0x300 +#define DWC_MSHC_PHY_CNFG (DWC_MSHC_PTR_PHY_REGS + 0x0) +#define PAD_SN_LSB 20 +#define PAD_SN_MASK 0xF +#define PAD_SN_DEFAULT ((0x8 & PAD_SN_MASK) << PAD_SN_LSB) +#define PAD_SP_LSB 16 +#define PAD_SP_MASK 0xF +#define PAD_SP_DEFAULT ((0x9 & PAD_SP_MASK) << PAD_SP_LSB) +#define PHY_PWRGOOD BIT(1) +#define PHY_RSTN BIT(0) + +#define DWC_MSHC_CMDPAD_CNFG (DWC_MSHC_PTR_PHY_REGS + 0x4) +#define DWC_MSHC_DATPAD_CNFG (DWC_MSHC_PTR_PHY_REGS + 0x6) +#define DWC_MSHC_CLKPAD_CNFG (DWC_MSHC_PTR_PHY_REGS + 0x8) +#define DWC_MSHC_STBPAD_CNFG (DWC_MSHC_PTR_PHY_REGS + 0xA) +#define DWC_MSHC_RSTNPAD_CNFG (DWC_MSHC_PTR_PHY_REGS + 0xC) +#define TXSLEW_N_LSB 9 +#define TXSLEW_N_MASK 0xF +#define TXSLEW_P_LSB 5 +#define TXSLEW_P_MASK 0xF +#define WEAKPULL_EN_LSB 3 +#define WEAKPULL_EN_MASK 0x3 +#define RXSEL_LSB 0 +#define RXSEL_MASK 0x3 + +#define DWC_MSHC_COMMDL_CNFG (DWC_MSHC_PTR_PHY_REGS + 0x1C) +#define DWC_MSHC_SDCLKDL_CNFG (DWC_MSHC_PTR_PHY_REGS + 0x1D) +#define DWC_MSHC_SDCLKDL_DC (DWC_MSHC_PTR_PHY_REGS + 0x1E) +#define DWC_MSHC_SMPLDL_CNFG (DWC_MSHC_PTR_PHY_REGS + 0x20) +#define DWC_MSHC_ATDL_CNFG (DWC_MSHC_PTR_PHY_REGS + 0x21) + +#define DWC_MSHC_PHY_PAD_SD_CLK \ + ((1 << TXSLEW_N_LSB) | (3 << TXSLEW_P_LSB) | (0 << WEAKPULL_EN_LSB) | (2 << RXSEL_LSB)) +#define DWC_MSHC_PHY_PAD_SD_DAT \ + ((1 << TXSLEW_N_LSB) | (3 << TXSLEW_P_LSB) | (1 << WEAKPULL_EN_LSB) | (2 << RXSEL_LSB)) +#define DWC_MSHC_PHY_PAD_SD_STB \ + ((1 << TXSLEW_N_LSB) | (3 << TXSLEW_P_LSB) | (2 << WEAKPULL_EN_LSB) | (2 << RXSEL_LSB)) +#define DWC_MSHC_PHY_PAD_EMMC_CLK \ + ((2 << TXSLEW_N_LSB) | (2 << TXSLEW_P_LSB) | (0 << WEAKPULL_EN_LSB) | (1 << RXSEL_LSB)) +#define DWC_MSHC_PHY_PAD_EMMC_DAT \ + ((2 << TXSLEW_N_LSB) | (2 << TXSLEW_P_LSB) | (1 << WEAKPULL_EN_LSB) | (1 << RXSEL_LSB)) +#define DWC_MSHC_PHY_PAD_EMMC_STB \ + ((2 << TXSLEW_N_LSB) | (2 << TXSLEW_P_LSB) | (2 << WEAKPULL_EN_LSB) | (1 << RXSEL_LSB)) + +static struct sdhci_host* sdhci_host0; +static struct sdhci_host* sdhci_host1; + +static inline void sdhci_writel(struct sdhci_host* host, uint32_t val, int reg) +{ + writel(val, (void*)host->mapbase + reg); +} + +static inline void sdhci_writew(struct sdhci_host* host, uint16_t val, int reg) +{ + writew((uint16_t)val, (void*)host->mapbase + reg); +} + +static inline void sdhci_writeb(struct sdhci_host* host, uint8_t val, int reg) +{ + writeb((uint8_t)val, (void*)host->mapbase + reg); +} + +static inline uint32_t sdhci_readl(struct sdhci_host* host, int reg) +{ + return (uint32_t)readl((void*)host->mapbase + reg); +} + +static inline uint16_t sdhci_readw(struct sdhci_host* host, int reg) +{ + return (uint16_t)readw((void*)host->mapbase + reg); +} + +static inline uint8_t sdhci_readb(struct sdhci_host* host, int reg) +{ + return (uint8_t)readb((void*)host->mapbase + reg); +} + +static void emmc_reg_display(struct sdhci_host* host) +{ + rt_kprintf("SD_MASA_R:%x\n", sdhci_readl(host, SDHCI_DMA_ADDRESS)); + rt_kprintf("BLCOKSIZE_R:%x\n", sdhci_readw(host, SDHCI_BLOCK_SIZE)); + rt_kprintf("BLOCKCOUNT_R:%x\n", sdhci_readw(host, SDHCI_BLOCK_COUNT)); + rt_kprintf("ARGUMENT_R:%x\n", sdhci_readl(host, SDHCI_ARGUMENT)); + rt_kprintf("XFER_MODE_R:%x\n", sdhci_readw(host, SDHCI_TRANSFER_MODE)); + rt_kprintf("CMD_R:%x\n", sdhci_readw(host, SDHCI_COMMAND)); + rt_kprintf("RESP0_R:%x\n", sdhci_readl(host, SDHCI_RESPONSE)); + rt_kprintf("RESP1_R:%x\n", sdhci_readl(host, SDHCI_RESPONSE + 4)); + rt_kprintf("RESP2_R:%x\n", sdhci_readl(host, SDHCI_RESPONSE + 8)); + rt_kprintf("RESP3_R:%x\n", sdhci_readl(host, SDHCI_RESPONSE + 12)); + rt_kprintf("BUF_DATA_R:%x\n", sdhci_readl(host, SDHCI_BUFFER)); + rt_kprintf("PSTATE_REG_R:%x\n", sdhci_readl(host, SDHCI_PRESENT_STATE)); + rt_kprintf("HOST_CTL_R:%x\n", sdhci_readb(host, SDHCI_HOST_CONTROL)); + rt_kprintf("PWR_CTRL_R:%x\n", sdhci_readb(host, SDHCI_POWER_CONTROL)); + rt_kprintf("BGAP_CTRL_R:%x\n", sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); + rt_kprintf("WUP_CTRL_R:%x\n", sdhci_readb(host, SDHCI_WAKE_UP_CONTROL)); + rt_kprintf("CLK_CTRL_R:%x\n", sdhci_readw(host, SDHCI_CLOCK_CONTROL)); + rt_kprintf("TOUT_CTRL_R:%x\n", sdhci_readb(host, SDHCI_TIMEOUT_CONTROL)); + rt_kprintf("SW_RSR_R:%x\n", sdhci_readb(host, SDHCI_SOFTWARE_RESET)); + rt_kprintf("NORMAL_INT_STAT_R:%x\n", sdhci_readw(host, SDHCI_INT_STATUS)); + rt_kprintf("ERROR_INT_STAT_R:%x\n", sdhci_readw(host, SDHCI_INT_STATUS + 2)); + rt_kprintf("NORMAL_INT_STAT_EN_R:%x\n", sdhci_readw(host, SDHCI_INT_ENABLE)); + rt_kprintf("ERROR_INT_STAT_EN_R:%x\n", sdhci_readw(host, SDHCI_INT_ENABLE + 2)); + rt_kprintf("NORNAL_INT_SIGNAL_EN_R:%x\n", sdhci_readw(host, SDHCI_SIGNAL_ENABLE)); + rt_kprintf("ERROR_INT_SIGNAL_EN_R:%x\n", sdhci_readw(host, SDHCI_SIGNAL_ENABLE + 2)); + rt_kprintf("AUTO_CMD_STAT_R:%x\n", sdhci_readw(host, SDHCI_AUTO_CMD_STATUS)); + rt_kprintf("HOST_CTRL2_R:%x\n", sdhci_readw(host, SDHCI_HOST_CONTROL2)); + rt_kprintf("CAPABILITIES1_R:%x\n", sdhci_readl(host, SDHCI_CAPABILITIES)); + rt_kprintf("CAPABILITIES2_R:%x\n", sdhci_readl(host, SDHCI_CAPABILITIES_1)); + rt_kprintf("FORCE_AUTO_CMD_STAT_R:%x\n", sdhci_readw(host, SDHCI_MAX_CURRENT)); + rt_kprintf("FORCE_ERROR_INT_STAT_R:%x\n", sdhci_readw(host, SDHCI_SET_ACMD12_ERROR)); + rt_kprintf("AMDA_ERR_STAT_STAT_R:%x\n", sdhci_readl(host, SDHCI_ADMA_ERROR)); + rt_kprintf("AMDA_SA_LOW_STAT_R:%x\n", sdhci_readl(host, SDHCI_ADMA_ADDRESS)); + rt_kprintf("AMDA_SA_HIGH_STAT_R:%x\n", sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI)); +} + +static inline void delay_1k(unsigned int uicnt) +{ + int i, j; + + for (i = 0; i < uicnt; i++) + for (j = 0; j < 1000; j++) + asm("nop"); +} + +static void dwcmshc_phy_1_8v_init(struct sdhci_host* host) +{ + sdhci_writew(host, DWC_MSHC_PHY_PAD_EMMC_DAT, DWC_MSHC_CMDPAD_CNFG); + sdhci_writew(host, DWC_MSHC_PHY_PAD_EMMC_DAT, DWC_MSHC_DATPAD_CNFG); + sdhci_writew(host, DWC_MSHC_PHY_PAD_EMMC_CLK, DWC_MSHC_CLKPAD_CNFG); + sdhci_writew(host, DWC_MSHC_PHY_PAD_EMMC_STB, DWC_MSHC_STBPAD_CNFG); + sdhci_writew(host, DWC_MSHC_PHY_PAD_EMMC_DAT, DWC_MSHC_RSTNPAD_CNFG); +} + +static void dwcmshc_phy_3_3v_init(struct sdhci_host* host) +{ + sdhci_writew(host, DWC_MSHC_PHY_PAD_SD_DAT, DWC_MSHC_CMDPAD_CNFG); + sdhci_writew(host, DWC_MSHC_PHY_PAD_SD_DAT, DWC_MSHC_DATPAD_CNFG); + sdhci_writew(host, DWC_MSHC_PHY_PAD_SD_CLK, DWC_MSHC_CLKPAD_CNFG); + sdhci_writew(host, DWC_MSHC_PHY_PAD_SD_STB, DWC_MSHC_STBPAD_CNFG); + sdhci_writew(host, DWC_MSHC_PHY_PAD_SD_DAT, DWC_MSHC_RSTNPAD_CNFG); +} + +static void dwcmshc_phy_delay_config(struct sdhci_host* host) +{ + sdhci_writeb(host, 1, DWC_MSHC_COMMDL_CNFG); + if (host->tx_delay_line > 256) { + LOG_E("host%d: tx_delay_line err\n", host->index); + } else if (host->tx_delay_line > 128) { + sdhci_writeb(host, 0x1, DWC_MSHC_SDCLKDL_CNFG); + sdhci_writeb(host, host->tx_delay_line - 128, DWC_MSHC_SDCLKDL_DC); + } else { + sdhci_writeb(host, 0x0, DWC_MSHC_SDCLKDL_CNFG); + sdhci_writeb(host, host->tx_delay_line, DWC_MSHC_SDCLKDL_DC); + } + sdhci_writeb(host, host->rx_delay_line, DWC_MSHC_SMPLDL_CNFG); + sdhci_writeb(host, 0xc, DWC_MSHC_ATDL_CNFG); + sdhci_writel(host, (sdhci_readl(host, SDHCI_VENDER_AT_CTRL_REG) | BIT(16) | BIT(17) | BIT(19) | BIT(20)), SDHCI_VENDER_AT_CTRL_REG); + sdhci_writel(host, 0x0, SDHCI_VENDER_AT_STAT_REG); +} + +static int dwcmshc_phy_init(struct sdhci_host* host) +{ + uint32_t reg; + uint32_t timeout = 15000; + /* reset phy */ + sdhci_writew(host, 0, DWC_MSHC_PHY_CNFG); + + /* Disable the clock */ + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (host->io_fixed_1v8) { + uint32_t data = sdhci_readw(host, SDHCI_HOST_CONTROL2); + data |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, data, SDHCI_HOST_CONTROL2); + dwcmshc_phy_1_8v_init(host); + } else { + dwcmshc_phy_3_3v_init(host); + } + + dwcmshc_phy_delay_config(host); + + /* Wait max 150 ms */ + while (1) { + reg = sdhci_readl(host, DWC_MSHC_PHY_CNFG); + if (reg & PHY_PWRGOOD) + break; + if (!timeout) { + return -1; + } + timeout--; + + delay_1k(1); + } + + reg = PAD_SN_DEFAULT | PAD_SP_DEFAULT; + sdhci_writel(host, reg, DWC_MSHC_PHY_CNFG); + + /* de-assert the phy */ + reg |= PHY_RSTN; + sdhci_writel(host, reg, DWC_MSHC_PHY_CNFG); + + return 0; +} + +static void sdhci_reset(struct sdhci_host* host, uint8_t mask) +{ + unsigned long timeout; + + /* Wait max 100 ms */ + timeout = 100; + sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); + while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { + if (timeout == 0) { + LOG_E("%s: Reset 0x%x never completed.\n", + __func__, (int)mask); + return; + } + timeout--; + delay_1k(1); + } + if (mask == SDHCI_RESET_ALL) { + if (host->index == 0) { + uint16_t emmc_ctl = sdhci_readw(host, EMMC_CTRL_R); + if (host->is_emmc_card) + emmc_ctl |= (1 << CARD_IS_EMMC); + else + emmc_ctl &= ~(1 << CARD_IS_EMMC); + sdhci_writeb(host, emmc_ctl, EMMC_CTRL_R); + } + if (host->have_phy) + dwcmshc_phy_init(host); + else + sdhci_writeb(host, host->mshc_ctrl_r, MSHC_CTRL_R); + } +} + +static uint32_t sdhci_get_present_status_flag(struct sdhci_host* sdhci_host) +{ + return sdhci_readl(sdhci_host, SDHCI_PRESENT_STATE); +} + +static uint32_t sdhci_get_int_status_flag(struct sdhci_host* sdhci_host) +{ + return sdhci_readl(sdhci_host, SDHCI_INT_STATUS); +} + +static void sdhci_clear_int_status_flag(struct sdhci_host* sdhci_host, uint32_t mask) +{ + sdhci_writel(sdhci_host, mask, SDHCI_INT_STATUS); +} + +static void sdhic_error_recovery(struct sdhci_host* sdhci_host) +{ + uint32_t status; + /* get host present status */ + status = sdhci_get_present_status_flag(sdhci_host); + /* check command inhibit status flag */ + if ((status & SDHCI_CMD_INHIBIT) != 0U) { + /* reset command line */ + sdhci_reset(sdhci_host, SDHCI_RESET_CMD); + } + /* check data inhibit status flag */ + if ((status & SDHCI_DATA_INHIBIT) != 0U) { + /* reset data line */ + sdhci_reset(sdhci_host, SDHCI_RESET_DATA); + } +} + +static rt_err_t sdhci_receive_command_response(struct sdhci_host* sdhci_host, struct sdhci_command* command) +{ + if (command->responseType == card_response_type_r2) { + /* CRC is stripped so we need to do some shifting. */ + for (int i = 0; i < 4; i++) { + command->response[3 - i] = sdhci_readl(sdhci_host, SDHCI_RESPONSE + (3 - i) * 4) << 8; + if (i != 3) + command->response[3 - i] |= sdhci_readb(sdhci_host, SDHCI_RESPONSE + (3 - i) * 4 - 1); + } + } else { + command->response[0] = sdhci_readl(sdhci_host, SDHCI_RESPONSE); + } + /* check response error flag */ + if ((command->responseErrorFlags != 0U) && ((command->responseType == card_response_type_r1) || (command->responseType == card_response_type_r1b) || (command->responseType == card_response_type_r6) || (command->responseType == card_response_type_r5))) { + if (((command->responseErrorFlags) & (command->response[0U])) != 0U) + return -1; // kStatus_USDHC_SendCommandFailed; + } + + return 0; +} + +static void sdhci_send_command(struct sdhci_host* sdhci_host, struct sdhci_command* command, rt_bool_t enDMA) +{ + RT_ASSERT(RT_NULL != command); + + uint32_t cmd_r, xfer_mode; + struct sdhci_data* sdhci_data = sdhci_host->sdhci_data; + + cmd_r = SDHCI_MAKE_CMD(command->index, command->flags); + + if (sdhci_data != RT_NULL) { +#ifdef SDHCI_SDMA_ENABLE + rt_ubase_t start_addr, dma_addr; + if (sdhci_data->rxData) + start_addr = (rt_ubase_t)((uint8_t*)sdhci_data->rxData); + else + start_addr = (rt_ubase_t)((uint8_t*)sdhci_data->txData); + rt_hw_cpu_dcache_clean((void*)start_addr, sdhci_data->blockSize * sdhci_data->blockCount); + command->flags2 |= sdhci_enable_dma_flag; + dma_addr = rt_kmem_v2p((void*)start_addr); + sdhci_writel(sdhci_host, dma_addr, SDHCI_DMA_ADDRESS); +#endif + sdhci_writew(sdhci_host, SDHCI_MAKE_BLKSZ(7, sdhci_data->blockSize), SDHCI_BLOCK_SIZE); + sdhci_writew(sdhci_host, sdhci_data->blockCount, SDHCI_BLOCK_COUNT); + } + xfer_mode = command->flags2 & 0x1ff; + sdhci_writew(sdhci_host, xfer_mode, SDHCI_TRANSFER_MODE); + sdhci_writel(sdhci_host, command->argument, SDHCI_ARGUMENT); + sdhci_writew(sdhci_host, cmd_r, SDHCI_COMMAND); +} + +static rt_err_t sdhci_wait_command_done(struct sdhci_host* sdhci_host, struct sdhci_command* command, rt_bool_t executeTuning) +{ + RT_ASSERT(RT_NULL != command); + rt_uint32_t event; + /* tuning cmd do not need to wait command done */ + if (executeTuning) + return 0; + /* Wait command complete or USDHC encounters error. */ + rt_event_recv(&sdhci_host->event, SDHCI_INT_ERROR | SDHCI_INT_RESPONSE, + RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &event); + if (event & SDHCI_INT_ERROR) { + LOG_D("%s: Error detected in status(0x%X)!\n", __func__, sdhci_host->error_code); + return -1; + } + return sdhci_receive_command_response(sdhci_host, command); +} + +static rt_err_t sdhci_transfer_data_blocking(struct sdhci_host* sdhci_host, struct sdhci_data* data, rt_bool_t enDMA) +{ +#ifdef SDHCI_SDMA_ENABLE + rt_err_t err; + rt_uint32_t event; + + while (1) { + err = rt_event_recv(&sdhci_host->event, SDHCI_INT_ERROR | SDHCI_INT_DATA_END | SDHCI_INT_DMA_END, + RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, 1000, &event); + if (err == -RT_ETIMEOUT) { + rt_kprintf("%s: Transfer data timeout\n", __func__); + return -1; + } + if (event & SDHCI_INT_ERROR) { + LOG_D("%s: Error detected in status(0x%X)!\n", __func__, sdhci_host->error_code); + emmc_reg_display(sdhci_host); + return -1; + } + if (event & SDHCI_INT_DMA_END) { + sdhci_writel(sdhci_host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); + sdhci_writel(sdhci_host, sdhci_readl(sdhci_host, SDHCI_DMA_ADDRESS), SDHCI_DMA_ADDRESS); + } + if (event & SDHCI_INT_DATA_END) { + if (data && data->rxData) + rt_hw_cpu_dcache_invalidate((void*)data->rxData, data->blockSize * data->blockCount); + return 0; + } + } +#else + uint32_t stat, rdy, mask, timeout, block; + + block = 0; + timeout = 1000000; + rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; + mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE; + + while (1) { + stat = sdhci_get_int_status_flag(sdhci_host); + if (stat & SDHCI_INT_ERROR) { + LOG_D("%s: Error detected in status(0x%X)!\n", __func__, stat); + emmc_reg_display(sdhci_host); + return -1; + } + if (stat & rdy) { + if (!(sdhci_readl(sdhci_host, SDHCI_PRESENT_STATE) & mask)) { + continue; + } + sdhci_clear_int_status_flag(sdhci_host, rdy); + if (data->rxData) { + for (int i = 0; i < data->blockSize / 4; i++) + data->rxData[i + block * data->blockSize] = sdhci_readl(sdhci_host, SDHCI_BUFFER); + } else { + for (int i = 0; i < data->blockSize / 4; i++) + sdhci_writel(sdhci_host, data->txData[i + block * data->blockSize], SDHCI_BUFFER); + } + block++; + if (block >= data->blockCount) + return 0; + } + if (timeout == 0) { + rt_kprintf("%s: Transfer data timeout\n", __func__); + return -1; + } + timeout--; + delay_1k(1); + } +#endif +} + +static rt_err_t sdhci_set_transfer_config(struct sdhci_host* sdhci_host, struct sdhci_command* sdhci_command, struct sdhci_data* sdhci_data) +{ + RT_ASSERT(sdhci_command); + /* Define the flag corresponding to each response type. */ + switch (sdhci_command->responseType) { + case card_response_type_none: + break; + case card_response_type_r1: /* Response 1 */ + case card_response_type_r5: /* Response 5 */ + case card_response_type_r6: /* Response 6 */ + case card_response_type_r7: /* Response 7 */ + + sdhci_command->flags |= (sdhci_cmd_resp_short | sdhci_enable_cmd_crc_flag | sdhci_enable_cmd_index_chk_flag); + break; + + case card_response_type_r1b: /* Response 1 with busy */ + case card_response_type_r5b: /* Response 5 with busy */ + sdhci_command->flags |= (sdhci_cmd_resp_short_busy | sdhci_enable_cmd_crc_flag | sdhci_enable_cmd_index_chk_flag); + break; + + case card_response_type_r2: /* Response 2 */ + sdhci_command->flags |= (sdhci_cmd_resp_long | sdhci_enable_cmd_crc_flag); + break; + + case card_response_type_r3: /* Response 3 */ + case card_response_type_r4: /* Response 4 */ + sdhci_command->flags |= (sdhci_cmd_resp_short); + break; + + default: + break; + } + + if (sdhci_command->type == card_command_type_abort) { + sdhci_command->flags |= sdhci_enable_command_type_abort; + } else if (sdhci_command->type == card_command_type_resume) { + sdhci_command->flags |= sdhci_enable_command_type_resume; + } else if (sdhci_command->type == card_command_type_suspend) { + sdhci_command->flags |= sdhci_enable_command_type_suspend; + } else if (sdhci_command->type == card_command_type_normal) { + sdhci_command->flags |= sdhci_enable_command_type_normal; + } + + if (sdhci_data) { + sdhci_command->flags |= sdhci_enable_cmd_data_present_flag; + sdhci_command->flags2 |= sdhci_enable_block_count_flag; + + if (sdhci_data->rxData) { + sdhci_command->flags2 |= sdhci_data_read_flag; + } + if (sdhci_data->blockCount > 1U) { + sdhci_command->flags2 |= (sdhci_multiple_block_flag); + /* auto command 12 */ + if (sdhci_data->enableAutoCommand12) { + /* Enable Auto command 12. */ + sdhci_command->flags2 |= sdhci_enable_auto_command12_flag; + } + /* auto command 23 */ + if (sdhci_data->enableAutoCommand23) { + sdhci_command->flags2 |= sdhci_enable_auto_command23_flag; + } + } + } + return 0; +} + +static rt_err_t sdhci_transfer_blocking(struct sdhci_host* sdhci_host) +{ + RT_ASSERT(sdhci_host); + struct sdhci_command* sdhci_command = sdhci_host->sdhci_command; + struct sdhci_data* sdhci_data = sdhci_host->sdhci_data; + rt_bool_t enDMA = false; + int ret = RT_EOK; + + /* Wait until command/data bus out of busy status. */ + while (sdhci_get_present_status_flag(sdhci_host) & sdhci_command_inhibit_flag) { + } + while (sdhci_data && (sdhci_get_present_status_flag(sdhci_host) & sdhci_data_inhibit_flag)) { + } + sdhci_writel(sdhci_host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); + + ret = sdhci_set_transfer_config(sdhci_host, sdhci_command, sdhci_data); + if (ret != 0) { + return ret; + } + sdhci_writel(sdhci_host, sdhci_readl(sdhci_host, SDHCI_SIGNAL_ENABLE) | + SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_SIGNAL_ENABLE); + rt_event_control(&sdhci_host->event, RT_IPC_CMD_RESET, 0); + sdhci_send_command(sdhci_host, sdhci_command, enDMA); + /* wait command done */ + ret = sdhci_wait_command_done(sdhci_host, sdhci_command, ((sdhci_data == RT_NULL) ? false : sdhci_data->executeTuning)); + /* transfer data */ + if ((sdhci_data != RT_NULL) && (ret == 0)) { + ret = sdhci_transfer_data_blocking(sdhci_host, sdhci_data, enDMA); + } + sdhci_writel(sdhci_host, sdhci_readl(sdhci_host, SDHCI_SIGNAL_ENABLE) & + ~(SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK), SDHCI_SIGNAL_ENABLE); + sdhci_writel(sdhci_host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); + sdhci_reset(sdhci_host, SDHCI_RESET_CMD); + sdhci_reset(sdhci_host, SDHCI_RESET_DATA); + return ret; +} + +static void sdhci_init(struct sdhci_host* host) +{ + sdhci_reset(host, SDHCI_RESET_ALL); + sdhci_writeb(host, SDHCI_CTRL_HISPD, SDHCI_HOST_CONTROL); + sdhci_writeb(host, 0x7, SDHCI_TIMEOUT_CONTROL); + sdhci_writeb(host, SDHCI_POWER_ON | SDHCI_POWER_330, SDHCI_POWER_CONTROL); + sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); + while ((sdhci_readw(host, SDHCI_CLOCK_CONTROL) & SDHCI_CLOCK_INT_STABLE) == 0) + ; + sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK, SDHCI_INT_ENABLE); + sdhci_writel(host, SDHCI_INT_CARD_INT, SDHCI_SIGNAL_ENABLE); +} + +static void sdhci_irq(int vector, void* param) +{ + struct sdhci_host* host = param; + uint32_t status = sdhci_get_int_status_flag(host); + + if (status & (SDHCI_INT_ERROR | SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | SDHCI_INT_RESPONSE)) { + host->error_code = (status >> 16) & 0xffff; + rt_event_send(&host->event, status & (SDHCI_INT_ERROR | SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | SDHCI_INT_RESPONSE)); + } + if (status & SDHCI_INT_CARD_INT) + sdio_irq_wakeup(host->host); + sdhci_clear_int_status_flag(host, status); +} + +static void kd_mmc_request(struct rt_mmcsd_host* host, struct rt_mmcsd_req* req) +{ + struct sdhci_host* mmcsd; + struct rt_mmcsd_cmd* cmd; + struct rt_mmcsd_data* data; + rt_err_t error; + struct sdhci_data sdhci_data = { 0 }; + struct sdhci_command sdhci_command = { 0 }; + + RT_ASSERT(host != RT_NULL); + RT_ASSERT(req != RT_NULL); + + mmcsd = (struct sdhci_host*)host->private_data; + RT_ASSERT(mmcsd != RT_NULL); + + cmd = req->cmd; + RT_ASSERT(cmd != RT_NULL); + + LOG_D("\tcmd->cmd_code: %02d, cmd->arg: %08x, cmd->flags: %08x --> ", cmd->cmd_code, cmd->arg, cmd->flags); + + data = cmd->data; + + sdhci_command.index = cmd->cmd_code; + sdhci_command.argument = cmd->arg; + + if (cmd->cmd_code == STOP_TRANSMISSION) + sdhci_command.type = card_command_type_abort; + else + sdhci_command.type = card_command_type_normal; + + switch (cmd->flags & RESP_MASK) { + case RESP_NONE: + sdhci_command.responseType = card_response_type_none; + break; + case RESP_R1: + sdhci_command.responseType = card_response_type_r1; + break; + case RESP_R1B: + sdhci_command.responseType = card_response_type_r1b; + break; + case RESP_R2: + sdhci_command.responseType = card_response_type_r2; + break; + case RESP_R3: + sdhci_command.responseType = card_response_type_r3; + break; + case RESP_R4: + sdhci_command.responseType = card_response_type_r4; + break; + case RESP_R6: + sdhci_command.responseType = card_response_type_r6; + break; + case RESP_R7: + sdhci_command.responseType = card_response_type_r7; + break; + case RESP_R5: + sdhci_command.responseType = card_response_type_r5; + break; + default: + RT_ASSERT(RT_NULL); + } + + sdhci_command.flags = 0; + sdhci_command.flags2 = 0; + sdhci_command.responseErrorFlags = 0; + mmcsd->sdhci_command = &sdhci_command; + + if (data) { + if (req->stop != RT_NULL) + sdhci_data.enableAutoCommand12 = true; + else + sdhci_data.enableAutoCommand12 = false; + + sdhci_data.enableAutoCommand23 = false; + + sdhci_data.blockSize = data->blksize; + sdhci_data.blockCount = data->blks; + + if (data->flags == DATA_DIR_WRITE) { + sdhci_data.txData = data->buf; + sdhci_data.rxData = RT_NULL; + } else { + sdhci_data.rxData = data->buf; + sdhci_data.txData = RT_NULL; + } +#ifdef SDHCI_SDMA_ENABLE + uint32_t sz = sdhci_data.blockSize * sdhci_data.blockCount; + uint32_t pad = 0; + if (sz & (CACHE_LINESIZE - 1)) + pad = (sz + (CACHE_LINESIZE - 1)) & ~(CACHE_LINESIZE - 1); + if (sdhci_data.rxData && (((uint64_t)(sdhci_data.rxData) & (CACHE_LINESIZE - 1)) || pad)) { + sdhci_data.rxData = rt_malloc_align(pad ? pad : sz, CACHE_LINESIZE); + } else if (((uint64_t)(sdhci_data.txData) & (CACHE_LINESIZE - 1)) || pad) { + sdhci_data.txData = rt_malloc_align(pad ? pad : sz, CACHE_LINESIZE); + rt_memcpy(sdhci_data.txData, data->buf, sz); + } +#endif + mmcsd->sdhci_data = &sdhci_data; + } else { + mmcsd->sdhci_data = RT_NULL; + } + error = sdhci_transfer_blocking(mmcsd); +#ifdef SDHCI_SDMA_ENABLE + if (data && sdhci_data.rxData && sdhci_data.rxData != data->buf) { + rt_memcpy(data->buf, sdhci_data.rxData, sdhci_data.blockSize * sdhci_data.blockCount); + rt_free_align(sdhci_data.rxData); + } else if (data && sdhci_data.txData && sdhci_data.txData != data->buf) { + rt_free_align(sdhci_data.txData); + } +#endif + if (error == -1) { + LOG_D(" ***USDHC_TransferBlocking error: %d*** --> \n", error); + cmd->err = -RT_ERROR; + } + + if ((cmd->flags & RESP_MASK) == RESP_R2) { + cmd->resp[3] = sdhci_command.response[0]; + cmd->resp[2] = sdhci_command.response[1]; + cmd->resp[1] = sdhci_command.response[2]; + cmd->resp[0] = sdhci_command.response[3]; + LOG_D(" resp 0x%08X 0x%08X 0x%08X 0x%08X\n", + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } else { + cmd->resp[0] = sdhci_command.response[0]; + LOG_D(" resp 0x%08X\n", cmd->resp[0]); + } + mmcsd_req_complete(host); +} + +static void kd_mmc_clock_freq_change(struct sdhci_host* host, uint32_t clock) +{ + uint32_t div, val; + + val = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + val &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_PROG_CLOCK_MODE); + sdhci_writew(host, val, SDHCI_CLOCK_CONTROL); + + if (clock == 0) + return; + + if (host->max_clk <= clock) { + div = 1; + } else { + for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { + if ((host->max_clk / div) <= clock) + break; + } + } + div >>= 1; + val &= ~((SDHCI_DIV_MASK << SDHCI_DIVIDER_SHIFT) | SDHCI_DIV_HI_MASK); + val |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; + val |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) + << SDHCI_DIVIDER_HI_SHIFT; + val |= SDHCI_CLOCK_CARD_EN | SDHCI_PROG_CLOCK_MODE; + sdhci_writew(host, val, SDHCI_CLOCK_CONTROL); + while ((sdhci_readw(host, SDHCI_CLOCK_CONTROL) & SDHCI_CLOCK_INT_STABLE) == 0) + ; +} + +static void kd_set_iocfg(struct rt_mmcsd_host* host, struct rt_mmcsd_io_cfg* io_cfg) +{ + struct sdhci_host* mmcsd; + unsigned int sdhci_clk; + unsigned int bus_width; + uint8_t ctrl; + RT_ASSERT(host != RT_NULL); + RT_ASSERT(host->private_data != RT_NULL); + RT_ASSERT(io_cfg != RT_NULL); + + mmcsd = (struct sdhci_host*)host->private_data; + sdhci_clk = io_cfg->clock; + bus_width = io_cfg->bus_width; + + LOG_D("%s: sdhci_clk=%d, bus_width:%d\n", __func__, sdhci_clk, bus_width); + + kd_mmc_clock_freq_change(mmcsd, sdhci_clk); + ctrl = sdhci_readb(mmcsd, SDHCI_HOST_CONTROL); + ctrl &= ~(SDHCI_CTRL_4BITBUS | SDHCI_CTRL_8BITBUS); + if (bus_width == 3) + ctrl |= SDHCI_CTRL_8BITBUS; + else if (bus_width == 2) + ctrl |= SDHCI_CTRL_4BITBUS; + sdhci_writeb(mmcsd, ctrl, SDHCI_HOST_CONTROL); +} + +static void kd_enable_sdio_irq(struct rt_mmcsd_host* mmcsd_host, rt_int32_t en) +{ + struct sdhci_host* host = (struct sdhci_host*)mmcsd_host->private_data; + uint32_t val; + + val = sdhci_readw(host, SDHCI_INT_ENABLE); + if (en) + val |= SDHCI_INT_CARD_INT; + else + val &= ~SDHCI_INT_CARD_INT; + sdhci_writew(host, val, SDHCI_INT_ENABLE); +} + +static const struct rt_mmcsd_host_ops ops = { + kd_mmc_request, + kd_set_iocfg, + RT_NULL, + kd_enable_sdio_irq, + RT_NULL, +}; + +void kd_sdhci0_reset(int value) +{ + struct sdhci_host* host = sdhci_host0; + + uint16_t emmc_ctl = sdhci_readw(host, EMMC_CTRL_R); + emmc_ctl |= (1 << EMMC_RST_N_OE); + if (value) + emmc_ctl |= (1 << EMMC_RST_N); + else + emmc_ctl &= ~(1 << EMMC_RST_N); + sdhci_writeb(host, emmc_ctl, EMMC_CTRL_R); +} + +void kd_sdhci_change(int id) +{ + if (id == 0) + mmcsd_change(sdhci_host0->host); + else if (id == 1) + mmcsd_change(sdhci_host1->host); +} + +rt_int32_t kd_sdhci_init(void) +{ + uint32_t val; + void* hi_sys_virt_addr = rt_ioremap((void*)0x91585000, 0x10); +#ifdef BSP_USING_SDIO0 + val = readl(hi_sys_virt_addr + 0); + val |= 1 << 6 | 1 << 4; + writel(val, hi_sys_virt_addr + 0); + sdhci_host0 = rt_malloc(sizeof(struct sdhci_host)); + if (!sdhci_host0) + return -1; + + rt_memset(sdhci_host0, 0, sizeof(struct sdhci_host)); + sdhci_host0->mapbase = (void*)rt_ioremap((void*)SDEMMC0_BASE, 0x1000); + sdhci_host0->index = 0; + sdhci_host0->have_phy = 1; + sdhci_host0->mshc_ctrl_r = 0; + sdhci_host0->rx_delay_line = 0x0d; + sdhci_host0->tx_delay_line = 0xc0; +#ifdef BSP_SDIO0_EMMC + sdhci_host0->is_emmc_card = 1; +#else + sdhci_host0->is_emmc_card = 0; +#endif +#ifdef BSP_SDIO0_1V8 + sdhci_host0->io_fixed_1v8 = 1; +#else + sdhci_host0->io_fixed_1v8 = 0; +#endif + sdhci_host0->sdhci_data = RT_NULL; + sdhci_host0->sdhci_command = RT_NULL; + sdhci_host0->max_clk = 200000000; + sdhci_init(sdhci_host0); + + rt_event_init(&sdhci_host0->event, "sd0_event", RT_IPC_FLAG_PRIO); + rt_hw_interrupt_install(IRQN_SD0, sdhci_irq, sdhci_host0, "sd0"); + rt_hw_interrupt_umask(IRQN_SD0); + + struct rt_mmcsd_host* mmcsd_host0 = mmcsd_alloc_host(); + if (!mmcsd_host0) { + rt_free(sdhci_host0); + return -1; + } + mmcsd_host0->ops = &ops; + mmcsd_host0->freq_min = 400000; + mmcsd_host0->freq_max = 50000000; +#ifdef BSP_SDIO0_EMMC + strncpy(mmcsd_host0->name, "emmc", sizeof(mmcsd_host0->name) - 1); + mmcsd_host0->flags = MMCSD_BUSWIDTH_8 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; +#else + strncpy(mmcsd_host0->name, "sd0", sizeof(mmcsd_host0->name) - 1); + mmcsd_host0->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; +#endif + mmcsd_host0->valid_ocr = sdhci_host0->io_fixed_1v8 ? VDD_165_195 : VDD_32_33 | VDD_33_34; +#ifdef BSP_USING_CYW43XX + mmcsd_host0->valid_ocr = VDD_32_33 | VDD_33_34; +#endif + mmcsd_host0->max_seg_size = 512 * 512; + mmcsd_host0->max_dma_segs = 1; + mmcsd_host0->max_blk_size = 512; + mmcsd_host0->max_blk_count = 4096; + mmcsd_host0->private_data = sdhci_host0; + sdhci_host0->host = mmcsd_host0; +#endif +#ifdef BSP_USING_SDIO1 + val = readl(hi_sys_virt_addr + 8); + val |= 1 << 2 | 1 << 0; + writel(val, hi_sys_virt_addr + 8); + sdhci_host1 = rt_malloc(sizeof(struct sdhci_host)); + if (!sdhci_host1) + return -2; + + rt_memset(sdhci_host1, 0, sizeof(struct sdhci_host)); + sdhci_host1->mapbase = (void*)rt_ioremap((void*)SDEMMC1_BASE, 0x1000); + sdhci_host1->index = 1; + sdhci_host1->have_phy = 0; + sdhci_host1->mshc_ctrl_r = 0; + sdhci_host1->rx_delay_line = 0; + sdhci_host1->tx_delay_line = 0; + sdhci_host1->sdhci_data = RT_NULL; + sdhci_host1->sdhci_command = RT_NULL; + sdhci_host1->max_clk = 100000000; + sdhci_init(sdhci_host1); + + rt_event_init(&sdhci_host1->event, "sd1_event", RT_IPC_FLAG_PRIO); + rt_hw_interrupt_install(IRQN_SD1, sdhci_irq, sdhci_host1, "sd1"); + rt_hw_interrupt_umask(IRQN_SD1); + + struct rt_mmcsd_host* mmcsd_host1 = mmcsd_alloc_host(); + if (!mmcsd_host1) { + rt_free(sdhci_host1); + return -2; + } + strncpy(mmcsd_host1->name, "sd1", sizeof(mmcsd_host1->name) - 1); + mmcsd_host1->ops = &ops; + mmcsd_host1->freq_min = 400000; + mmcsd_host1->freq_max = 50000000; + mmcsd_host1->valid_ocr = VDD_32_33 | VDD_33_34; + mmcsd_host1->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + mmcsd_host1->max_seg_size = 512 * 512; + mmcsd_host1->max_dma_segs = 1; + mmcsd_host1->max_blk_size = 512; + mmcsd_host1->max_blk_count = 4096; + mmcsd_host1->private_data = sdhci_host1; + sdhci_host1->host = mmcsd_host1; +#endif +#ifdef BSP_SD_SDIO_DEV + kd_sdhci_change(BSP_SD_SDIO_DEV); +#endif + rt_iounmap(hi_sys_virt_addr); + return 0; +} +INIT_DEVICE_EXPORT(kd_sdhci_init); + +#endif /*defined(BSP_USING_SDIO0) || defined(BSP_USING_SDIO1)*/ + +#endif /*defined(RT_USING_SDIO)*/ diff --git a/bsp/k230/drivers/interdrv/sdio/drv_sdhci.h b/bsp/k230/drivers/interdrv/sdio/drv_sdhci.h new file mode 100644 index 00000000000..71bc774bc05 --- /dev/null +++ b/bsp/k230/drivers/interdrv/sdio/drv_sdhci.h @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __DRV_SDHCI__ +#define __DRV_SDHCI__ + +#define false 0 +#define true 1 +#define SDEMMC0_BASE 0x91580000 +#define SDEMMC1_BASE 0x91581000 +#define IRQN_SD0 142 +#define IRQN_SD1 144 + +/* + * Controller registers + */ + +#define SDHCI_DMA_ADDRESS 0x00 +#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS + +#define SDHCI_BLOCK_SIZE 0x04 +#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) + +#define SDHCI_BLOCK_COUNT 0x06 + +#define SDHCI_ARGUMENT 0x08 + +#define SDHCI_TRANSFER_MODE 0x0C +#define SDHCI_TRNS_DMA 0x01 +#define SDHCI_TRNS_BLK_CNT_EN 0x02 +#define SDHCI_TRNS_AUTO_CMD12 0x04 +#define SDHCI_TRNS_AUTO_CMD23 0x08 +#define SDHCI_TRNS_AUTO_SEL 0x0C +#define SDHCI_TRNS_READ 0x10 +#define SDHCI_TRNS_MULTI 0x20 + +#define SDHCI_COMMAND 0x0E +#define SDHCI_CMD_RESP_MASK 0x03 +#define SDHCI_CMD_CRC 0x08 +#define SDHCI_CMD_INDEX 0x10 +#define SDHCI_CMD_DATA 0x20 +#define SDHCI_CMD_ABORTCMD 0xC0 + +#define SDHCI_CMD_RESP_NONE 0x00 +#define SDHCI_CMD_RESP_LONG 0x01 +#define SDHCI_CMD_RESP_SHORT 0x02 +#define SDHCI_CMD_RESP_SHORT_BUSY 0x03 + +#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) +#define SDHCI_GET_CMD(c) ((c >> 8) & 0x3f) + +#define SDHCI_RESPONSE 0x10 + +#define SDHCI_BUFFER 0x20 + +#define SDHCI_PRESENT_STATE 0x24 +#define SDHCI_CMD_INHIBIT 0x00000001 +#define SDHCI_DATA_INHIBIT 0x00000002 +#define SDHCI_DOING_WRITE 0x00000100 +#define SDHCI_DOING_READ 0x00000200 +#define SDHCI_SPACE_AVAILABLE 0x00000400 +#define SDHCI_DATA_AVAILABLE 0x00000800 +#define SDHCI_CARD_PRESENT 0x00010000 +#define SDHCI_CARD_PRES_SHIFT 16 +#define SDHCI_CD_STABLE 0x00020000 +#define SDHCI_CD_LVL 0x00040000 +#define SDHCI_CD_LVL_SHIFT 18 +#define SDHCI_WRITE_PROTECT 0x00080000 +#define SDHCI_DATA_LVL_MASK 0x00F00000 +#define SDHCI_DATA_LVL_SHIFT 20 +#define SDHCI_DATA_0_LVL_MASK 0x00100000 +#define SDHCI_CMD_LVL 0x01000000 + +#define SDHCI_HOST_CONTROL 0x28 +#define SDHCI_CTRL_LED 0x01 +#define SDHCI_CTRL_4BITBUS 0x02 +#define SDHCI_CTRL_HISPD 0x04 +#define SDHCI_CTRL_DMA_MASK 0x18 +#define SDHCI_CTRL_SDMA 0x00 +#define SDHCI_CTRL_ADMA1 0x08 +#define SDHCI_CTRL_ADMA32 0x10 +#define SDHCI_CTRL_ADMA64 0x18 +#define SDHCI_CTRL_ADMA3 0x18 +#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_CDTEST_INS 0x40 +#define SDHCI_CTRL_CDTEST_EN 0x80 + +#define SDHCI_POWER_CONTROL 0x29 +#define SDHCI_POWER_ON 0x01 +#define SDHCI_POWER_180 0x0A +#define SDHCI_POWER_300 0x0C +#define SDHCI_POWER_330 0x0E + +#define SDHCI_BLOCK_GAP_CONTROL 0x2A + +#define SDHCI_WAKE_UP_CONTROL 0x2B +#define SDHCI_WAKE_ON_INT 0x01 +#define SDHCI_WAKE_ON_INSERT 0x02 +#define SDHCI_WAKE_ON_REMOVE 0x04 + +#define SDHCI_CLOCK_CONTROL 0x2C +#define SDHCI_DIVIDER_SHIFT 8 +#define SDHCI_DIVIDER_HI_SHIFT 6 +#define SDHCI_DIV_MASK 0xFF +#define SDHCI_DIV_MASK_LEN 8 +#define SDHCI_DIV_HI_MASK 0x300 +#define SDHCI_PROG_CLOCK_MODE 0x0020 +#define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_PLL_EN 0x0008 +#define SDHCI_CLOCK_INT_STABLE 0x0002 +#define SDHCI_CLOCK_INT_EN 0x0001 + +#define SDHCI_TIMEOUT_CONTROL 0x2E + +#define SDHCI_SOFTWARE_RESET 0x2F +#define SDHCI_RESET_ALL 0x01 +#define SDHCI_RESET_CMD 0x02 +#define SDHCI_RESET_DATA 0x04 + +#define SDHCI_INT_STATUS 0x30 +#define SDHCI_INT_ENABLE 0x34 +#define SDHCI_SIGNAL_ENABLE 0x38 +#define SDHCI_INT_RESPONSE 0x00000001 +#define SDHCI_INT_DATA_END 0x00000002 +#define SDHCI_INT_BLK_GAP 0x00000004 +#define SDHCI_INT_DMA_END 0x00000008 +#define SDHCI_INT_SPACE_AVAIL 0x00000010 +#define SDHCI_INT_DATA_AVAIL 0x00000020 +#define SDHCI_INT_CARD_INSERT 0x00000040 +#define SDHCI_INT_CARD_REMOVE 0x00000080 +#define SDHCI_INT_CARD_INT 0x00000100 +#define SDHCI_INT_RETUNE 0x00001000 +#define SDHCI_INT_CQE 0x00004000 +#define SDHCI_INT_ERROR 0x00008000 +#define SDHCI_INT_TIMEOUT 0x00010000 +#define SDHCI_INT_CRC 0x00020000 +#define SDHCI_INT_END_BIT 0x00040000 +#define SDHCI_INT_INDEX 0x00080000 +#define SDHCI_INT_DATA_TIMEOUT 0x00100000 +#define SDHCI_INT_DATA_CRC 0x00200000 +#define SDHCI_INT_DATA_END_BIT 0x00400000 +#define SDHCI_INT_BUS_POWER 0x00800000 +#define SDHCI_INT_AUTO_CMD_ERR 0x01000000 +#define SDHCI_INT_ADMA_ERROR 0x02000000 + +#define SDHCI_INT_NORMAL_MASK 0x00007FFF +#define SDHCI_INT_ERROR_MASK 0xFFFF8000 + +#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | SDHCI_INT_AUTO_CMD_ERR) +#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | SDHCI_INT_BLK_GAP) +#define SDHCI_INT_ALL_MASK ((unsigned int)-1) + +#define SDHCI_CQE_INT_ERR_MASK ( \ + SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT) + +#define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE) + +#define SDHCI_AUTO_CMD_STATUS 0x3C +#define SDHCI_AUTO_CMD_TIMEOUT 0x00000002 +#define SDHCI_AUTO_CMD_CRC 0x00000004 +#define SDHCI_AUTO_CMD_END_BIT 0x00000008 +#define SDHCI_AUTO_CMD_INDEX 0x00000010 + +#define SDHCI_HOST_CONTROL2 0x3E +#define SDHCI_CTRL_UHS_MASK 0x0007 +#define SDHCI_CTRL_UHS_SDR12 0x0000 +#define SDHCI_CTRL_UHS_SDR25 0x0001 +#define SDHCI_CTRL_UHS_SDR50 0x0002 +#define SDHCI_CTRL_UHS_SDR104 0x0003 +#define SDHCI_CTRL_UHS_DDR50 0x0004 +#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_VDD_180 0x0008 +#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 +#define SDHCI_CTRL_DRV_TYPE_B 0x0000 +#define SDHCI_CTRL_DRV_TYPE_A 0x0010 +#define SDHCI_CTRL_DRV_TYPE_C 0x0020 +#define SDHCI_CTRL_DRV_TYPE_D 0x0030 +#define SDHCI_CTRL_EXEC_TUNING 0x0040 +#define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CMD23_ENABLE 0x0800 +#define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 +#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 + +#define SDHCI_CAPABILITIES 0x40 +#define SDHCI_TIMEOUT_CLK_MASK GENMASK(5, 0) +#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 +#define SDHCI_CLOCK_BASE_MASK GENMASK(13, 8) +#define SDHCI_CLOCK_V3_BASE_MASK GENMASK(15, 8) +#define SDHCI_MAX_BLOCK_MASK 0x00030000 +#define SDHCI_MAX_BLOCK_SHIFT 16 +#define SDHCI_CAN_DO_8BIT 0x00040000 +#define SDHCI_CAN_DO_ADMA2 0x00080000 +#define SDHCI_CAN_DO_ADMA1 0x00100000 +#define SDHCI_CAN_DO_HISPD 0x00200000 +#define SDHCI_CAN_DO_SDMA 0x00400000 +#define SDHCI_CAN_DO_SUSPEND 0x00800000 +#define SDHCI_CAN_VDD_330 0x01000000 +#define SDHCI_CAN_VDD_300 0x02000000 +#define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT_V4 0x08000000 +#define SDHCI_CAN_64BIT 0x10000000 + +#define SDHCI_CAPABILITIES_1 0x44 +#define SDHCI_SUPPORT_SDR50 0x00000001 +#define SDHCI_SUPPORT_SDR104 0x00000002 +#define SDHCI_SUPPORT_DDR50 0x00000004 +#define SDHCI_DRIVER_TYPE_A 0x00000010 +#define SDHCI_DRIVER_TYPE_C 0x00000020 +#define SDHCI_DRIVER_TYPE_D 0x00000040 +#define SDHCI_RETUNING_TIMER_COUNT_MASK GENMASK(11, 8) +#define SDHCI_USE_SDR50_TUNING 0x00002000 +#define SDHCI_RETUNING_MODE_MASK GENMASK(15, 14) +#define SDHCI_CLOCK_MUL_MASK GENMASK(23, 16) +#define SDHCI_CAN_DO_ADMA3 0x08000000 +#define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ + +#define SDHCI_MAX_CURRENT 0x48 +#define SDHCI_MAX_CURRENT_LIMIT GENMASK(7, 0) +#define SDHCI_MAX_CURRENT_330_MASK GENMASK(7, 0) +#define SDHCI_MAX_CURRENT_300_MASK GENMASK(15, 8) +#define SDHCI_MAX_CURRENT_180_MASK GENMASK(23, 16) +#define SDHCI_MAX_CURRENT_MULTIPLIER 4 + +/* 4C-4F reserved for more max current */ + +#define SDHCI_SET_ACMD12_ERROR 0x50 +#define SDHCI_SET_INT_ERROR 0x52 + +#define SDHCI_ADMA_ERROR 0x54 + +/* 55-57 reserved */ + +#define SDHCI_ADMA_ADDRESS 0x58 +#define SDHCI_ADMA_ADDRESS_HI 0x5C + +/* 60-FB reserved */ + +#define SDHCI_PRESET_FOR_HIGH_SPEED 0x64 +#define SDHCI_PRESET_FOR_SDR12 0x66 +#define SDHCI_PRESET_FOR_SDR25 0x68 +#define SDHCI_PRESET_FOR_SDR50 0x6A +#define SDHCI_PRESET_FOR_SDR104 0x6C +#define SDHCI_PRESET_FOR_DDR50 0x6E +#define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ +#define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) +#define SDHCI_PRESET_CLKGEN_SEL BIT(10) +#define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) + +#define SDHCI_SLOT_INT_STATUS 0xFC + +#define SDHCI_HOST_VERSION 0xFE +#define SDHCI_VENDOR_VER_MASK 0xFF00 +#define SDHCI_VENDOR_VER_SHIFT 8 +#define SDHCI_SPEC_VER_MASK 0x00FF +#define SDHCI_SPEC_VER_SHIFT 0 +#define SDHCI_SPEC_100 0 +#define SDHCI_SPEC_200 1 +#define SDHCI_SPEC_300 2 +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 +#define SDHCI_SPEC_420 5 + +/* + * End of controller registers. + */ +#define SDHCI_MAX_DIV_SPEC_300 2046 +/*! @brief Transfer flag mask */ +enum sdhci_transfer_mode +{ + sdhci_enable_dma_flag = SDHCI_TRNS_DMA, /*!< Enable DMA */ + + sdhci_enable_block_count_flag = SDHCI_TRNS_BLK_CNT_EN, /*!< Enable block count */ + sdhci_enable_auto_command12_flag = SDHCI_TRNS_AUTO_CMD12, /*!< Enable auto CMD12 */ + sdhci_data_read_flag = SDHCI_TRNS_READ, /*!< Enable data read */ + sdhci_multiple_block_flag = SDHCI_TRNS_MULTI, /*!< Multiple block data read/write */ + sdhci_enable_auto_command23_flag = SDHCI_TRNS_AUTO_CMD23, /*!< Enable auto CMD23 */ + sdhci_enable_auto_commamd_sel_flag = SDHCI_TRNS_AUTO_SEL, /* Enable auto command sel*/ +}; + +enum sdhci_command_flag +{ + sdhci_cmd_resp_nono = SDHCI_CMD_RESP_NONE, + sdhci_cmd_resp_long = SDHCI_CMD_RESP_LONG, + sdhci_cmd_resp_short = SDHCI_CMD_RESP_SHORT, + sdhci_cmd_resp_short_busy = SDHCI_CMD_RESP_SHORT_BUSY, + + sdhci_enable_cmd_crc_flag = SDHCI_CMD_CRC, + sdhci_enable_cmd_index_chk_flag = SDHCI_CMD_INDEX, + sdhci_enable_cmd_data_present_flag = SDHCI_CMD_DATA, + + sdhci_enable_command_type_normal = 0x00, + sdhci_enable_command_type_suspend = 0x40, + sdhci_enable_command_type_resume = 0x80, + sdhci_enable_command_type_abort = 0xc0, +}; + +/*! @brief Present status flag mask */ +enum sdhci_present_status_flag +{ + sdhci_command_inhibit_flag = 0x1, /*!< Command inhibit */ + sdhci_data_inhibit_flag = 0x2, /*!< Data inhibit */ + sdhci_data_line_active_flag = 0x4, /*!< Data line active */ + sdhci_write_transfer_active_flag = 0x100, /*!< Write transfer active */ + sdhci_read_transfer_active_flag = 0x200, /*!< Read transfer active */ + sdhci_buffer_write_enable_flag = 0x400, /*!< Buffer write enable */ + sdhci_buffer_read_enable_flag = 0x800, /*!< Buffer read enable */ + + sdhci_card_insert_flag = 0x10000, /*!< Card inserted */ + sdhci_sd_clock_stable_flag = 0x20000, /*!< SD bus clock stable */ + sdhci_card_detect_pin_level_flag = 0x40000, /*!< card detect pin level */ + sdhci_write_protect_switch_pin_level_flag = 0x80000, /**/ + + sdhci_data0_line_level_flag = (1U << 20), /*!< Data0 line signal level */ + sdhci_data1_line_level_flag = (1U << (20 + 1U)), /*!< Data1 line signal level */ + sdhci_data2_line_level_flag = (1U << (20 + 2U)), /*!< Data2 line signal level */ + sdhci_data3_line_level_flag = (1U << (20 + 3U)), /*!< Data3 line signal level */ + sdhci_data4_line_level_flag = (1U << (4 + 0U)), /*!< Data4 line signal level */ + sdhci_data5_line_level_flag = (1U << (4 + 1U)), /*!< Data5 line signal level */ + sdhci_data6_line_level_flag = (1U << (4 + 2U)), /*!< Data6 line signal level */ + sdhci_data7_line_level_flag = (1U << (4 + 3U)), /*!< Data7 line signal level */ + + sdhci_command_line_signal_level_flag =0x1000000, + sdhci_host_reg_voltage_stable_flag = 0x2000000, + sdhci_command_not_issued_by_error_flag = 0x8000000, + sdhci_sub_command_status_flag = 0x10000000, + sdhci_in_dormant_status_flag = 0x20000000, + sdhci_lane_synchronization_flag = 0x40000000, + sdhci_uhs_ii_interface_detection_flag = 0x80000000, +}; + +/*! @brief Interrupt status flag mask */ +enum sdhci_interrupt_status_flag +{ + sdhci_command_complete_flag = 0x1, /*!< Command complete */ + sdhci_data_complete_flag = 0x2, /*!< Data complete */ + sdhci_block_gap_event_flag = 0x4, /*!< Block gap event */ + sdhci_dma_complete_flag = 0x8, /*!< DMA interrupt */ + sdhci_buffer_write_ready_flag = 0x10, /*!< Buffer write ready */ + sdhci_buffer_read_ready_flag = 0x20, /*!< Buffer read ready */ + sdhci_card_insertion_flag = 0x40, /*!< Card inserted */ + sdhci_card_removal_flag = 0x80, /*!< Card removed */ + sdhci_card_interrupt_flag = 0x100, /*!< Card interrupt */ + + sdhci_command_timeout_flag = 0x10000, /*!< Command timeout error */ + sdhci_command_crc_error_flag = 0x20000, /*!< Command CRC error */ + sdhci_command_end_bit_error_flag = 0x40000, /*!< Command end bit error */ + sdhci_command_index_error_flag = 0x80000, /*!< Command index error */ + sdhci_data_timeout_flag = 0x100000, /*!< Data timeout error */ + sdhci_data_crc_error_flag = 0x200000, /*!< Data CRC error */ + sdhci_data_end_bit_error_flag = 0x400000, /*!< Data end bit error */ + sdhci_auto_command_error_flag = 0x1000000, /*!< Auto CMD error */ + sdhci_dma_error_flag = 0x2000000, /*!< ADMA error */ + sdhci_tuning_error_flag = 0x4000000, /* tuning err*/ + sdhci_response_err_flag = 0x8000000, /*resp error*/ + + sdhci_command_error_flag = (sdhci_command_timeout_flag | sdhci_command_crc_error_flag | sdhci_command_end_bit_error_flag | + sdhci_command_index_error_flag), /*!< Command error */ + sdhci_data_error_flag = (sdhci_data_timeout_flag | sdhci_data_crc_error_flag | sdhci_data_end_bit_error_flag | + sdhci_auto_command_error_flag), /*!< Data error */ + sdhci_error_flag = (sdhci_command_error_flag | sdhci_data_error_flag | sdhci_dma_error_flag), /*!< All error */ + sdhci_data_flag = (sdhci_data_complete_flag | sdhci_dma_complete_flag | sdhci_buffer_write_ready_flag | + sdhci_buffer_read_ready_flag | sdhci_data_error_flag | sdhci_dma_error_flag), /*!< Data interrupts */ + sdhci_command_flag = (sdhci_command_error_flag | sdhci_command_complete_flag), /*!< Command interrupts */ + sdhci_card_detect_flag = (sdhci_card_insertion_flag | sdhci_card_removal_flag), /*!< Card detection interrupts */ + sdhci_sdr104_tuning_flag = (sdhci_tuning_error_flag), + + sdhci_all_interrupt_flags = (sdhci_block_gap_event_flag | sdhci_card_detect_flag | sdhci_command_flag | + sdhci_data_flag | sdhci_error_flag | sdhci_sdr104_tuning_flag), /*!< All flags mask */ +}; + +/*! @brief USDHC status */ +enum sdhci_status +{ + sdhci_status_busy_transferring = 65, /*!< Transfer is on-going */ + sdhci_status_prepare_adma_descriptor_failed = 66, /*!< Set DMA descriptor failed */ + sdhci_status_send_command_failed = 67, /*!< Send command failed */ + sdhci_status_transfer_data_failed = 68, /*!< Transfer data failed */ + sdhci_status_dma_data_addr_no_align = 69, /*!< data address not align */ + sdhci_status_retuning_request = 70, /*!< re-tuning request */ + sdhci_status_tuning_error = 71, /*!< tuning error */ + +}; + +/* ADMA2 data alignment */ +#define SDHCI_ADMA2_ALIGN 4 +#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) + +/*! @brief The bit shift for LENGTH field in ADMA2's descriptor */ +#define SDHCI_ADMA2_DESCRIPTOR_LENGTH_SHIFT (16U) +/*! @brief The bit mask for LENGTH field in ADMA2's descriptor */ +#define SDHCI_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU) +/*! @brief The maximum value of LENGTH field in ADMA2's descriptor */ +#define SDHCI_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDHCI_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U) + +#define SDHCI_DESC_VALID (0x1U << 0) +#define SDHCI_DESC_END (0x1U << 1) +#define SDHCI_DESC_INT (0x1U << 2) +#define SDHCI_DESC_TRAN (0x2U << 4) +struct sdhci_64bit_adma2_descriptor +{ + uint32_t attribute; + uint32_t address; +}; + +/*! @brief The command type */ +enum sdhci_card_command_type +{ + card_command_type_normal = 0U, /*!< Normal command */ + card_command_type_suspend = 1U, /*!< Suspend command */ + card_command_type_resume = 2U, /*!< Resume command */ + card_command_type_abort = 3U, /*!< Abort command */ +}; + +/*! + * @brief The command response type. + * + * Define the command response type from card to host controller. + */ +enum sdhci_card_response_type +{ + card_response_type_none = 0U, /*!< Response type: none */ + card_response_type_r1 = 1U, /*!< Response type: R1 */ + card_response_type_r1b = 2U, /*!< Response type: R1b */ + card_response_type_r2 = 3U, /*!< Response type: R2 */ + card_response_type_r3 = 4U, /*!< Response type: R3 */ + card_response_type_r4 = 5U, /*!< Response type: R4 */ + card_response_type_r5 = 6U, /*!< Response type: R5 */ + card_response_type_r5b = 7U, /*!< Response type: R5b */ + card_response_type_r6 = 8U, /*!< Response type: R6 */ + card_response_type_r7 = 9U, /*!< Response type: R7 */ +}; + +/*! + * @brief Card data descriptor + * + * Defines a structure to contain data-related attribute. 'enableIgnoreError' is used for the case that upper card + * driver + * want to ignore the error event to read/write all the data not to stop read/write immediately when error event + * happen for example bus testing procedure for MMC card. + */ +struct sdhci_data +{ + rt_bool_t enableAutoCommand12; /*!< Enable auto CMD12 */ + rt_bool_t enableAutoCommand23; /*!< Enable auto CMD23 */ + rt_bool_t enableIgnoreError; /*!< Enable to ignore error event to read/write all the data */ + rt_bool_t executeTuning; /*!< execute tuning flag */ + + size_t blockSize; /*!< Block size */ + uint32_t blockCount; /*!< Block count */ + uint32_t *rxData; /*!< Buffer to save data read */ + const uint32_t *txData; /*!< Data buffer to write */ +}; + +/*! + * @brief Card command descriptor + * + * Define card command-related attribute. + */ +struct sdhci_command +{ + uint32_t index; /*!< Command index */ + uint32_t argument; /*!< Command argument */ + enum sdhci_card_command_type type; /*!< Command type */ + enum sdhci_card_response_type responseType; /*!< Command response type */ + uint32_t response[4U]; /*!< Response for this command */ + uint32_t responseErrorFlags; /*!< response error flag, the flag which need to check + the command reponse*/ + uint16_t flags; /*!< Cmd flags */ + uint16_t flags2; /*xfer mode*/ +}; + +struct sdhci_host +{ + struct rt_mmcsd_host *host; + void *mapbase; + struct sdhci_data *sdhci_data; + struct sdhci_command *sdhci_command; + void *usdhc_adma2_table; + struct rt_event event; + uint16_t error_code; + uint32_t max_clk; + uint8_t index; + uint8_t is_emmc_card; + uint8_t io_fixed_1v8; + uint8_t have_phy; + uint8_t mshc_ctrl_r; + uint32_t rx_delay_line; + uint32_t tx_delay_line; +}; + +#endif /*__DRV_SDHCI__*/ diff --git a/bsp/k230/drivers/interdrv/uart/SConscript b/bsp/k230/drivers/interdrv/uart/SConscript new file mode 100644 index 00000000000..0961d64537c --- /dev/null +++ b/bsp/k230/drivers/interdrv/uart/SConscript @@ -0,0 +1,19 @@ +# RT-Thread building script for component + +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Uart', src, depend = [''], CPPPATH = CPPPATH) + +objs = [group] + +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/k230/drivers/interdrv/uart/drv_uart.c b/bsp/k230/drivers/interdrv/uart/drv_uart.c new file mode 100644 index 00000000000..dc6a9dbf8a4 --- /dev/null +++ b/bsp/k230/drivers/interdrv/uart/drv_uart.c @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2019-2020 + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include +#include +#include +#include + +#include "board.h" +#include "drv_uart.h" +#include "riscv_io.h" +#include "board.h" + +#define UART_DEFAULT_BAUDRATE 115200 +#define UART_CLK 50000000 +#define UART_ADDR 0x91403000UL +#define UART_IRQ 0x13 + + +#define UART_RBR (0x00) /* receive buffer register */ +#define UART_THR (0x00) /* transmit holding register */ +#define UART_DLL (0x00) /* divisor latch low register */ +#define UART_DLH (0x04) /* diviso latch high register */ +#define UART_IER (0x04) /* interrupt enable register */ +#define UART_IIR (0x08) /* interrupt identity register */ +#define UART_FCR (0x08) /* FIFO control register */ +#define UART_LCR (0x0c) /* line control register */ +#define UART_MCR (0x10) /* modem control register */ +#define UART_LSR (0x14) /* line status register */ +#define UART_MSR (0x18) /* modem status register */ +#define UART_SCH (0x1c) /* scratch register */ +#define UART_USR (0x7c) /* status register */ +#define UART_TFL (0x80) /* transmit FIFO level */ +#define UART_RFL (0x84) /* RFL */ +#define UART_HALT (0xa4) /* halt tx register */ +#define UART_DLF (0xc0) /* Divisor Latch Fraction Register */ + +#define BIT(x) (1 << x) + +/* Line Status Rigster */ +#define UART_LSR_RXFIFOE (BIT(7)) +#define UART_LSR_TEMT (BIT(6)) +#define UART_LSR_THRE (BIT(5)) +#define UART_LSR_BI (BIT(4)) +#define UART_LSR_FE (BIT(3)) +#define UART_LSR_PE (BIT(2)) +#define UART_LSR_OE (BIT(1)) +#define UART_LSR_DR (BIT(0)) +#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ + +/* Line Control Register */ +#define UART_LCR_DLAB (BIT(7)) +#define UART_LCR_SBC (BIT(6)) +#define UART_LCR_PARITY_MASK (BIT(5)|BIT(4)) +#define UART_LCR_EPAR (1 << 4) +#define UART_LCR_OPAR (0 << 4) +#define UART_LCR_PARITY (BIT(3)) +#define UART_LCR_STOP (BIT(2)) +#define UART_LCR_DLEN_MASK (BIT(1)|BIT(0)) +#define UART_LCR_WLEN5 (0) +#define UART_LCR_WLEN6 (1) +#define UART_LCR_WLEN7 (2) +#define UART_LCR_WLEN8 (3) + +/* Halt Register */ +#define UART_HALT_LCRUP (BIT(2)) +#define UART_HALT_FORCECFG (BIT(1)) +#define UART_HALT_HTX (BIT(0)) + +/* Interrupt Enable Register */ +#define UART_IER_MASK (0xff) +#define UART_IER_PTIME (BIT(7)) +#define UART_IER_RS485 (BIT(4)) +#define UART_IER_MSI (BIT(3)) +#define UART_IER_RLSI (BIT(2)) +#define UART_IER_THRI (BIT(1)) +#define UART_IER_RDI (BIT(0)) + +/* Interrupt ID Register */ +#define UART_IIR_FEFLAG_MASK (BIT(6)|BIT(7)) +#define UART_IIR_IID_MASK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) +#define UART_IIR_IID_MSTA (0) +#define UART_IIR_IID_NOIRQ (1) +#define UART_IIR_IID_THREMP (2) +#define UART_IIR_IID_RXDVAL (4) +#define UART_IIR_IID_LINESTA (6) +#define UART_IIR_IID_BUSBSY (7) +#define UART_IIR_IID_CHARTO (12) + +struct device_uart +{ + rt_ubase_t hw_base; + rt_uint32_t irqno; +}; + +static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg); +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg); +static int drv_uart_putc(struct rt_serial_device *serial, char c); +static int drv_uart_getc(struct rt_serial_device *serial); + +const struct rt_uart_ops _uart_ops = +{ + rt_uart_configure, + uart_control, + drv_uart_putc, + drv_uart_getc, + //TODO: add DMA support + RT_NULL +}; + +struct rt_serial_device serial1; +struct device_uart uart1; + +#define write32(addr, val) writel(val, (void*)(addr)) +#define read32(addr) readl((void*)(addr)) + +static void _uart_init(void *uart_base) +{ + uint32_t bdiv; + uint32_t dlf; + uint32_t dlh; + uint32_t dll; + + bdiv = UART_CLK / UART_DEFAULT_BAUDRATE; + dlh = bdiv >> 12; + dll = (bdiv - (dlh << 12)) / 16; + dlf = bdiv - (dlh << 12) - dll * 16; + if(dlh == 0 && dll == 0) + { + dll = 1; + dlf = 0; + } + + write32(uart_base + UART_LCR, 0x00); + /* Disable all interrupts */ + write32(uart_base + UART_IER, 0x00); + /* Enable DLAB */ + write32(uart_base + UART_LCR, 0x80); + if (bdiv) { + /* Set divisor low byte */ + write32(uart_base + UART_DLL, dll); + /* Set divisor high byte */ + write32(uart_base + UART_DLH, dlh); + /* Set divisor fraction byte*/ + write32(uart_base + UART_DLF, dlf); + } + /* 8 bits, no parity, one stop bit */ + write32(uart_base + UART_LCR, 0x03); + /* Enable FIFO */ + write32(uart_base + UART_FCR, 0x01); + /* No modem control DTR RTS */ + write32(uart_base + UART_MCR, 0x00); + /* Clear line status */ + read32(uart_base + UART_LSR); + /* Read receive buffer */ + read32(uart_base + UART_RBR); + read32(uart_base + UART_USR); + read32(uart_base + UART_FCR); + /* Set scratchpad */ + write32(uart_base + UART_SCH, 0x00); + //enable uart rx irq + // write32(uart_base + UART_IER, 0x01); +} + +static void uart_set_isr(void *uart_base, uint8_t enable, uint32_t irq_type) +{ + uint32_t value; + + value = read32(uart_base + UART_IER); + + if (enable) + { + value |= irq_type; + } + else + { + value &= ~irq_type; + } + write32(uart_base + UART_IER, value); +} + +/* + * UART interface + */ +static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + return (RT_EOK); +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct device_uart *uart = (struct device_uart*)serial->parent.user_data; + +#ifdef RT_USING_SERIAL_V2 + rt_ubase_t ctrl_flag = 0; + rt_ubase_t ctrl_arg; +#endif + +#ifdef RT_USING_SERIAL_V2 + ctrl_arg = (rt_ubase_t)arg; + + if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING)) + { + ctrl_flag |= RT_DEVICE_FLAG_INT_RX; + } +#endif + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: +#ifdef RT_USING_SERIAL_V2 + if (ctrl_flag & RT_DEVICE_FLAG_INT_RX) +#else + if ((size_t)arg == RT_DEVICE_FLAG_INT_RX) +#endif + { + uart_set_isr((void*)(uart->hw_base), 0, UART_IER_RDI); + } + break; + + case RT_DEVICE_CTRL_SET_INT: +#ifdef RT_USING_SERIAL_V2 + if (ctrl_flag & RT_DEVICE_FLAG_INT_RX) +#else + if ((size_t)arg == RT_DEVICE_FLAG_INT_RX) +#endif + { + uart_set_isr((void*)(uart->hw_base), 1, UART_IER_RDI); + } + break; +#ifdef RT_USING_SERIAL_V2 + case RT_DEVICE_CTRL_CONFIG: + if (ctrl_flag & RT_DEVICE_FLAG_INT_RX) + { + uart_set_isr((void*)(uart->hw_base), 1, UART_IER_RDI); + } + break; +#endif + + case RT_FIOMMAP2: + { + struct dfs_mmap2_args *mmap2 = (struct dfs_mmap2_args *)arg; + if (mmap2) + { + if (mmap2->length > 0x400) + { + return -RT_ENOMEM; + } + + mmap2->ret = lwp_map_user_phy(lwp_self(), RT_NULL, (void*)(uart->hw_base), mmap2->length, 0); + } + break; + } + } + + return (RT_EOK); +} + +static int drv_uart_putc(struct rt_serial_device *serial, char c) +{ + volatile uint32_t *sed_buf; + volatile uint32_t *sta; + struct device_uart *uart = (struct device_uart*)serial->parent.user_data; + + sed_buf = (uint32_t *)(uart->hw_base + UART_THR); + sta = (uint32_t *)(uart->hw_base + UART_USR); + + /* FIFO status, contain valid data */ + // while (!(*sta & 0x02)); + while (!(read32(uart->hw_base + UART_LSR) & 0x20)); + + *sed_buf = c; + + return (1); +} + +static int drv_uart_getc(struct rt_serial_device *serial) +{ + struct device_uart *uart = (struct device_uart*)serial->parent.user_data; + volatile uint32_t *lsr = (uint32_t *)(uart->hw_base + UART_LSR); + volatile uint32_t *rbr = (uint32_t *)(uart->hw_base + UART_RBR); + + if (!(*lsr & UART_LSR_DR)) + { + return -1; + } + return (int)*rbr; +} + +static void rt_hw_uart_isr(int irq, void *param) +{ + struct rt_serial_device *serial = (struct rt_serial_device*)param; + struct device_uart *uart; + size_t uart_base; + uint32_t iir, lsr; + + uart = (struct device_uart*)serial->parent.user_data; + uart_base = uart->hw_base; + + iir = readb((void*)(uart_base + UART_IIR)) & UART_IIR_IID_MASK; + lsr = readb((void*)(uart_base + UART_LSR)); + // rt_kprintf("uart isr iir:%x lsr:%x\r\n", iir, lsr); + + if (iir == UART_IIR_IID_BUSBSY) + { + (void)readb((void*)(uart_base + UART_USR)); + } + else if (lsr & (UART_LSR_DR | UART_LSR_BI)) + { + #ifdef RT_USING_SERIAL_V2 + struct rt_serial_rx_fifo *rx_fifo; + uint8_t data; + + rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + RT_ASSERT(rx_fifo != RT_NULL); + + do { + data = readb((void*)(uart_base + UART_RBR)); + rt_ringbuffer_putchar(&(rx_fifo->rb), data); + lsr = readb((void*)(uart_base + UART_LSR)); + } while(lsr & UART_LSR_DR); + + #endif + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + } + else if (iir & UART_IIR_IID_CHARTO) + /* has charto irq but no dr lsr? just read and ignore */ + { + readb((void*)(uart_base + UART_RBR)); + } +} + +/* + * UART Initiation + */ +int rt_hw_uart_init(void) +{ + struct rt_serial_device *serial; + struct device_uart *uart; + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + { + serial = &serial1; + uart = &uart1; + + serial->ops = &_uart_ops; + serial->config = config; + serial->config.baud_rate = UART_DEFAULT_BAUDRATE; + + uart->hw_base = (rt_base_t)rt_ioremap((void *)UART_ADDR, 0x1000); + uart->irqno = UART_IRQ; + + _uart_init((void*)(uart->hw_base)); + + rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, "uart1"); + rt_hw_interrupt_umask(uart->irqno); + + rt_hw_serial_register(serial, + RT_CONSOLE_DEVICE_NAME, + RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + uart); + } + + return 0; +} diff --git a/bsp/k230/drivers/interdrv/uart/drv_uart.h b/bsp/k230/drivers/interdrv/uart/drv_uart.h new file mode 100644 index 00000000000..a7a18d0ddea --- /dev/null +++ b/bsp/k230/drivers/interdrv/uart/drv_uart.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2019-2020, Xim + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#ifndef __DRV_UART_H__ +#define __DRV_UART_H__ + +void rt_hw_uart_start_rx_thread(); +int rt_hw_uart_init(void); +void drv_uart_puts(char *str); // for syscall + +#endif /* __DRV_UART_H__ */ diff --git a/bsp/k230/link.lds b/bsp/k230/link.lds new file mode 100644 index 00000000000..ad731cd615e --- /dev/null +++ b/bsp/k230/link.lds @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020/12/12 bernard The first version + */ + +INCLUDE "link_stacksize.lds" + +OUTPUT_ARCH( "riscv" ) + +/* + * Memory layout: + * 2M ==> +128K: Bootloader(sbi) + * 2M+128K ==> +sizeof(rtthread.bin): Kernel + * ~ ==> 32M: Heap + * 32M - 66M: Page + */ + +MEMORY +{ + SRAM(wx) : ORIGIN = 0xFFFFFFC000220000, LENGTH = 64M - 128K +} + +ENTRY(_start) +SECTIONS +{ + . = ORIGIN(SRAM) ; + + /* __STACKSIZE__ = 4096; */ + __sram_base = ORIGIN(SRAM); + __sram_size = LENGTH(SRAM); + __sram_end = __sram_base + __sram_size; + __text_start = .; + .start : + { + *(.start); + } > SRAM + + . = ALIGN(8); + + .text : + { + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(8); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(8); + + /* section information for initial. */ + . = ALIGN(8); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(8); + + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + + . = ALIGN(8); + _etext = .; + } > SRAM + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } > SRAM + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM + + . = ALIGN(8); + __text_end = .; + __text_size = __text_end - __text_start; + + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.sdata) + *(.sdata.*) + } > SRAM + + /* stack for dual core */ + .stack : + { + . = ALIGN(64); + __stack_start__ = .; + + . += __STACKSIZE__; + __stack_cpu0 = .; + + . += __STACKSIZE__; + __stack_cpu1 = .; + } > SRAM + + . = ALIGN(8); + + .osdebug : + { + _osdebug_start = .; + . += 87K; + _osdebug_end = .; + } > SRAM + + . = ALIGN(8); + + .sbss : + { + __bss_start = .; + *(.sbss) + *(.sbss.*) + *(.dynsbss) + *(.scommon) + } > SRAM + + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + __bss_end = .; + } > SRAM + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/k230/link_stacksize.lds b/bsp/k230/link_stacksize.lds new file mode 100644 index 00000000000..13e6ee8b1c3 --- /dev/null +++ b/bsp/k230/link_stacksize.lds @@ -0,0 +1 @@ +__STACKSIZE__ = 8192; \ No newline at end of file diff --git a/bsp/k230/mkfm.sh b/bsp/k230/mkfm.sh new file mode 100644 index 00000000000..ef84e8965d2 --- /dev/null +++ b/bsp/k230/mkfm.sh @@ -0,0 +1,77 @@ +#/bin/sh + +#add_firmHead xxx.bin "-n" +#output fn_$1 fa_$1 fs_$1 +add_firmHead() +{ + local filename="$1" + local firmware_gen="tools/firmware_gen.py" + + if [ $# -ge 2 ]; then + firmArgs="$2" #add k230 firmware head + cp ${filename} ${filename}.t; python3 ${firmware_gen} -i ${filename}.t -o f${firmArgs##-}${filename} ${firmArgs}; + else + #add k230 firmware head + firmArgs="-n"; cp ${filename} ${filename}.t; python3 ${firmware_gen} -i ${filename}.t -o f${firmArgs##-}_${filename} ${firmArgs}; + fi + rm -rf ${filename}.t +} + +k230_gzip() +{ + local filename="$1" + local k230_gzip_tool="tools/k230_priv_gzip " + + ${k230_gzip_tool} -n8 -f -k ${filename} || ${k230_gzip_tool} -n9 -f -k ${filename} || \ + ${k230_gzip_tool} -n7 -f -k ${filename} || ${k230_gzip_tool} -n6 -f -k ${filename} || \ + ${k230_gzip_tool} -n5 -f -k ${filename} || ${k230_gzip_tool} -n4 -f -k ${filename} + + sed -i -e "1s/\x08/\x09/" ${filename}.gz +} + +bin_gzip_ubootHead_firmHead() +{ + local mkimage="tools/mkimage" + local file_full_path="$1" + local filename=$(basename ${file_full_path}) + local mkimgArgs="$2" + local firmArgs="$3" + + [ "$(dirname ${file_full_path})" == "$(pwd)" ] || cp ${file_full_path} . + + k230_gzip ${filename} + + #add uboot head + ${mkimage} -A riscv -C gzip ${mkimgArgs} -d ${filename}.gz ug_${filename} + + add_firmHead ug_${filename} + rm -rf ${filename} ${filename}.gz ug_${filename} +} + +gen_rtt_bin() +{ + local filename="fw_payload.bin" + local CONFIG_MEM_RTT_SYS_BASE="0x200000" + + bin_gzip_ubootHead_firmHead "opensbi/build/platform/kendryte/fpgac908/firmware/${filename}" \ + "-O opensbi -T multi -a ${CONFIG_MEM_RTT_SYS_BASE} -e ${CONFIG_MEM_RTT_SYS_BASE} -n rtt" + + mv fn_ug_${filename} rtt_system.bin +} + +build_sbi() +{ + cc=~/.tools/gnu_gcc/riscv64-linux-musleabi_for_x86_64-pc-linux-gnu/bin/riscv64-unknown-linux-musl- + + if [ -n "$1" ]; then + cc=$1 + fi + + cd opensbi && make FW_PAYLOAD_PATH=../rtthread.bin FW_FDT_PATH=hw.dtb PLATFORM=kendryte/fpgac908 CROSS_COMPILE=$cc + + cd .. +} + +build_sbi $1 + +gen_rtt_bin diff --git a/bsp/k230/rtconfig.h b/bsp/k230/rtconfig.h new file mode 100644 index 00000000000..20caf683810 --- /dev/null +++ b/bsp/k230/rtconfig.h @@ -0,0 +1,491 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_USING_SMART +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_HOOKLIST +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 8192 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 8192 +#define RT_USING_CPU_USAGE_TRACER + +/* kservice optimization */ + +/* end of kservice optimization */ + +/* klibc optimization */ + +#define RT_KLIBC_USING_PRINTF_LONGLONG +/* end of klibc optimization */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_PAGE_MAX_ORDER 11 +#define RT_USING_MEMPOOL +#define RT_USING_SLAB +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_SCHED_THREAD_CTX +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x50200 +#define RT_USING_STDC_ATOMIC +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_MM_MMU +#define KERNEL_VADDR_START 0xFFFFFFC000220000 +#define ARCH_RISCV +#define ARCH_RISCV_FPU +#define ARCH_RISCV_FPU_D +#define ARCH_RISCV64 +#define ARCH_USING_NEW_CTX_SWITCH +#define ARCH_REMAP_KERNEL + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 8192 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V2 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +/* end of elm-chan's FatFs, Generic FAT Filesystem Module */ +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_PTYFS +#define RT_USING_DFS_CROMFS +#define RT_USING_DFS_TMPFS +#define RT_USING_PAGECACHE + +/* page cache config */ + +#define RT_PAGECACHE_COUNT 4096 +#define RT_PAGECACHE_ASPACE_COUNT 1024 +#define RT_PAGECACHE_PRELOAD 4 +#define RT_PAGECACHE_HASH_NR 1024 +#define RT_PAGECACHE_GC_WORK_LEVEL 90 +#define RT_PAGECACHE_GC_STOP_LEVEL 70 +/* end of page cache config */ +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_CPUTIME +#define RT_USING_CPUTIME_RISCV +#define CPUTIME_TIMER_FREQ 25000000 +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 8192 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 8192 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_PIN +#define RT_USING_KTIME +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + +#define RT_USING_POSIX_FS +#define RT_USING_POSIX_DEVIO +#define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_POLL +#define RT_USING_POSIX_SELECT +#define RT_USING_POSIX_EPOLL +#define RT_USING_POSIX_SIGNALFD +#define RT_SIGNALFD_MAX_NUM 10 +#define RT_USING_POSIX_SOCKET +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_DELAY +#define RT_USING_POSIX_CLOCK +#define RT_USING_POSIX_TIMER + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +/* end of Docking with protocol stacks */ +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 8 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +/* end of Static IPv4 Address */ +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 8192 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 8192 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define RT_LWIP_NETIF_NAMESIZE 6 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +#define RT_USING_RESOURCE_ID +#define RT_USING_ADT +#define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF +/* end of Utilities */ +#define RT_USING_LWP +#define LWP_DEBUG +#define LWP_DEBUG_INIT +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 +#define RT_USING_LDSO +#define LWP_USING_TERMINAL +#define LWP_PTY_MAX_PARIS_LIMIT 64 + +/* Memory management */ + +/* end of Memory management */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +#define PKG_USING_ZLIB +#define PKG_USING_ZLIB_LATEST_VERSION +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* Drivers Configuration */ + +/* end of Drivers Configuration */ +#define BOARD_fpgac908 +#define __STACKSIZE__ 8192 +#define C908_PLIC_PHY_ADDR 0xF00000000 +#define BSP_ROOTFS_TYPE_CROMFS + +#endif diff --git a/bsp/k230/rtconfig.py b/bsp/k230/rtconfig.py new file mode 100644 index 00000000000..5d7f5b3b218 --- /dev/null +++ b/bsp/k230/rtconfig.py @@ -0,0 +1,54 @@ +import os + +# toolchains options +ARCH ='risc-v' +VENDOR ='t-head' +CPU ='c908' +CROSS_TOOL ='gcc' + +RTT_ROOT = os.getenv('RTT_ROOT', r'../..') + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin' +else: + print('Please make sure your toolchains is GNU GCC!') + exit(0) + +EXEC_PATH = os.getenv('RTT_EXEC_PATH', EXEC_PATH) + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + #PREFIX = 'riscv64-unknown-elf-' + PREFIX = os.getenv('RTT_CC_PREFIX') or 'riscv64-unknown-linux-musl-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcmodel=medany -march=rv64imafdc -mabi=lp64' + CFLAGS = DEVICE + ' -Wno-cpp -fvar-tracking -ffreestanding -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -D_POSIX_SOURCE ' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__ASSEMBLY__' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' + ' -lsupc++ -lgcc -static' + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O2 -g -gdwarf-2' + AFLAGS += ' -g -gdwarf-2' + else: + CFLAGS += ' -O2 -g -gdwarf-2' + + CXXFLAGS = CFLAGS + +POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/renesas/README.md b/bsp/renesas/README.md index e7e95d78804..ef89868352f 100644 --- a/bsp/renesas/README.md +++ b/bsp/renesas/README.md @@ -19,7 +19,9 @@ RA 系列 BSP 目前支持情况如下表所示： | [ra8m1-ek](ra8m1-ek) | Renesas 官方 EK-RA8M1 开发板 | | [ra8d1-ek](ra8d1-ek) | Renesas 官方 EK-RA8D1 开发板 | | [ra8d1-vision-board](ra8d1-vision-board) | Renesas 联合 RT-Thread RA8D1-Vision-Board 开发板 | +| **RZ 系列** | | | [rzt2m_rsk](rzt2m_rsk) | Renesas 官方 RSK-RZT2M 开发板 | +| [rzn2l_rsk](rzn2l_rsk) | Renesas 官方 RSK-RZN2L 开发板 | 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示： diff --git a/bsp/renesas/rzn2l_rsk/.api_xml b/bsp/renesas/rzn2l_rsk/.api_xml new file mode 100644 index 00000000000..fc9bf0b30e4 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.api_xml @@ -0,0 +1,2 @@ + + diff --git a/bsp/renesas/rzn2l_rsk/.config b/bsp/renesas/rzn2l_rsk/.config new file mode 100644 index 00000000000..6f402d9bc83 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.config @@ -0,0 +1,1194 @@ + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice optimization +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice optimization + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# end of klibc optimization + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=512 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_R=y +CONFIG_ARCH_ARM_CORTEX_R52=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_RENESAS=y +CONFIG_SOC_SERIES_R9A07G0=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_R9A07G084=y + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_ETHERCAT_EOE is not set +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_ONCHIP_FLASH is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_ONCHIP_RTC is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=256 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_CANFD is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_TIM is not set +# CONFIG_BSP_USING_ETH is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# CONFIG_BSP_USING_RW007 is not set +# end of Board extended module Drivers +# end of Hardware Drivers Config diff --git a/bsp/renesas/rzn2l_rsk/.secure_azone b/bsp/renesas/rzn2l_rsk/.secure_azone new file mode 100644 index 00000000000..585ba89ca37 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.secure_azone @@ -0,0 +1,4 @@ + + + + diff --git a/bsp/renesas/rzn2l_rsk/.secure_xml b/bsp/renesas/rzn2l_rsk/.secure_xml new file mode 100644 index 00000000000..0ee0319050f --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.secure_xml @@ -0,0 +1,125 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/rzn2l_rsk/.settings/standalone.prefs b/bsp/renesas/rzn2l_rsk/.settings/standalone.prefs new file mode 100644 index 00000000000..5e6ead989e8 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/.settings/standalone.prefs @@ -0,0 +1,24 @@ +#Sat Sep 14 16:03:03 CST 2024 +com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp_xspi0_boot.icf +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.1.fsp.2.0.0/all=1441545198,rzn/arm/CMSIS_5/LICENSE.txt|4247764709,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h|1135074086,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h|510668081,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h|4245531541,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h|1887099957,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h|3334069041,rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/all= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#rzn2l_rsk\#\#xspi0_x1_boot\#\#2.0.0/all=907937621,script/fsp_xspi0_boot.icf|3822962514,rzn/board/rzn2l_rsk/board_leds.c|358444977,rzn/board/rzn2l_rsk/board_init.c|2067006575,rzn/board/rzn2l_rsk/board.h|736691883,rzn/board/rzn2l_rsk/board_ethernet_phy.h|1631979823,rzn/board/rzn2l_rsk/board_leds.h|1430483072,rzn/board/rzn2l_rsk/board_init.h +com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.86814920=false +com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.0.0/all=908052335,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|3563504244,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|870156648,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c|368480523,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c|3243637314,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1280798555,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|3352808441,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h|1310386533,rzn/fsp/src/bsp/mcu/all/bsp_io.h|3643995939,rzn/fsp/src/bsp/mcu/all/bsp_cache.h|1033616941,rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h|1572168446,rzn/fsp/src/bsp/mcu/all/bsp_io.c|3001342594,rzn/fsp/src/bsp/mcu/all/bsp_common.h|263477342,rzn/fsp/src/bsp/mcu/all/bsp_reset.h|2534029381,rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h|4193244082,rzn/fsp/src/bsp/mcu/all/bsp_irq.h|2136575248,rzn/fsp/src/bsp/mcu/all/bsp_tfu.h|2170977041,rzn/fsp/src/bsp/mcu/all/bsp_delay.c|526389185,rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h|8162287,rzn/fsp/src/bsp/mcu/all/bsp_clocks.h|3045644015,rzn/fsp/src/bsp/mcu/all/bsp_common.c|1908923075,rzn/fsp/src/bsp/mcu/all/bsp_clocks.c|1289851302,rzn/fsp/src/bsp/mcu/all/bsp_irq.c|358242822,rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c|2321472163,rzn/fsp/src/bsp/mcu/all/bsp_cache.c|225356254,rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h|2518644892,rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c|392613868,rzn/fsp/src/bsp/mcu/all/bsp_reset.c|2238656401,rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h|1611830052,rzn/fsp/src/bsp/mcu/all/bsp_delay.h|2060190483,rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h|1543064539,rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h|3717942516,rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c|3396795463,rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c|2195931215,rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c|1126344352,rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h|1926319940,rzn/fsp/inc/fsp_features.h|2508067197,rzn/fsp/inc/fsp_version.h|3571247719,rzn/fsp/inc/fsp_common_api.h|3347087544,rzn/fsp/inc/instances/r_ioport.h|1765016794,rzn/fsp/inc/api/bsp_api.h|250199021,rzn/fsp/inc/api/r_ioport_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#R9A07G084M04GBG\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#fsp\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=false +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#all\#\#Memory\#\#\#\#2.0.0/all= +com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#Core\#\#\#\#5.7.0+renesas.1.fsp.2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.0.0/all=2921827146,rzn/fsp/src/r_sci_uart/r_sci_uart.c|4093801030,rzn/fsp/inc/instances/r_sci_uart.h|1119704027,rzn/fsp/inc/api/r_uart_api.h|3586794436,rzn/fsp/inc/api/r_transfer_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.0.0/all=3243637314,rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#device\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#rzn2l\#\#fsp\#\#\#\#2.0.0/all=2989202485,rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c|1967641730,rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h|1508541487,rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h|1088535767,rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c|1458388275,rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h|617637586,rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#2.0.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#2.0.0/all=615913359,rzn/fsp/src/r_ioport/r_ioport.c|3347087544,rzn/fsp/inc/instances/r_ioport.h|250199021,rzn/fsp/inc/api/r_ioport_api.h diff --git a/bsp/renesas/rzn2l_rsk/Kconfig b/bsp/renesas/rzn2l_rsk/Kconfig new file mode 100644 index 00000000000..896f127335a --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/Kconfig @@ -0,0 +1,17 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +# you can change the RTT_ROOT default "rt-thread" +# example : default "F:/git_repositories/rt-thread" + +PKGS_DIR := packages + +ENV_DIR := / + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +source "$(BSP_DIR)/board/Kconfig" diff --git a/bsp/renesas/rzn2l_rsk/README.md b/bsp/renesas/rzn2l_rsk/README.md new file mode 100644 index 00000000000..e12338d8ec4 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/README.md @@ -0,0 +1,168 @@ +# Renesas RSK-RZN2L Development Board BSP Documentation + +**English** | [**中文**](./README_zh.md) + +## Introduction + +This document provides the BSP (Board Support Package) for the Renesas RSK-RZN2L development board. By following the Quick Start Guide, developers can quickly get started with the BSP and run RT-Thread on the development board. + +The main contents include: + +- Development Board Introduction +- BSP Quick Start Guide + +## Development Board Introduction + +The RSK-RZN2L MCU evaluation board is based on Renesas RZ/N2L and is designed for developing embedded system applications with flexible software package configuration and IDE support. + +The front appearance of the development board is shown below: + +![image-20240914173709363](figures/image-20240914173709363.png) + +The commonly used **onboard resources** for this development board are as follows: + +- MPU: R9A07G084M04GBG, maximum operating frequency of 400MHz, Arm® Cortex®-R52 with on-chip FPU (Floating Point Unit) and NEON™, 1.5 MB on-chip SRAM, Ethernet MAC, EtherCAT, USB 2.0 High-Speed, CAN/CANFD, various communication interfaces such as xSPI and ΔΣ interfaces, and security functions. +- Debug Interface: Onboard J-Link interface +- Expansion Interface: Two PMOD connectors + +**More detailed information and tools** + +## Peripheral Support + +The current peripheral support in this BSP is as follows: + +| **On-chip Peripheral** | **Support Status** | **Remarks** | +| :----------------- | :----------------- | :------------- | +| UART | Supported | UART0 is the default log output port | +| GPIO | Supported | | +| HWIMER | Supported | | +| IIC | Supported | | +| WDT | Supported | | +| RTC | Supported | | +| ADC | Supported | | +| DAC | Supported | | +| SPI | Supported | | +| FLASH | Supported | | +| PWM | Supported | | +| CAN | Supported | | +| ETH | Supported | | +| More updates... | | | + +## Instructions + +The instructions are divided into the following two sections: + +- Quick Start + + This section is for beginners who are new to RT-Thread. By following simple steps, you can run the RT-Thread OS on this development board and observe the experimental results. + +- Advanced Usage + + This section is for developers who want to use more resources on the development board with RT-Thread. Using the ENV tool to configure the BSP, you can enable more onboard resources and achieve more advanced features. + +### Quick Start + +Currently, this BSP only provides an IAR project. Below is an example of how to get the system running using the [IAR Embedded Workbench for Arm](https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/) development environment. + +**Hardware Connection** + +Connect the development board to the PC using a USB data cable, and use the J-Link interface to download and debug programs. + +**Compilation and Download** + +- Go to the BSP directory, open ENV, and use the command `scons --target=iar` to generate the IAR project. +- Compile: Double-click the `project.eww` file to open the IAR project and compile the program. +- Debug: Click `Project->Download and Debug` in the IAR toolbar to download and start debugging. + +**View Running Results** + +After successfully downloading the program, the system will run automatically and print system information. + +Connect the corresponding serial port of the development board to the PC. Open the corresponding serial port in a terminal tool (115200-8-1-N). After resetting the device, you can see the RT-Thread output. Enter the `help` command to view the supported commands in the system. + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Mar 14 2024 18:26:01 + 2006 - 2024 Copyright by RT-Thread team + +Hello RT-Thread! +================================================== +This is a iar project which mode is xspi0 execution! +================================================== +msh >help +RT-Thread shell commands: +clear - clear the terminal screen +version - show RT-Thread version information +list - list objects +backtrace - print backtrace of a thread +help - RT-Thread shell help +ps - List threads in the system +free - Show the memory usage in the system +pin - pin [option] + +msh > +``` + +**Application Entry Function** + +The application layer's entry function is in `src\hal_entry.c` in the `void hal_entry(void)` function. User source files can be placed directly in the `src` directory. + +```c +#define LED_PIN BSP_IO_PORT_18_PIN_2 /* Onboard LED pins */ + +void hal_entry(void) +{ + rt_kprintf("\nHello RT-Thread!\n"); + rt_kprintf("==================================================\n"); + rt_kprintf("This is a iar project which mode is xspi0 execution!\n"); + rt_kprintf("==================================================\n"); + + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} +``` + +### Advanced Usage + +**Resources and Documentation** + +- [Development Board Official Homepage](https://www.renesas.cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzn2l-integrated-tsn-compliant-3-port-gigabit-ethernet-switch-enables-various-industrial-applications) +- [Development Board Data Sheet](https://www.renesas.cn/zh/document/dst/rzn2l-group-datasheet?r=1622651) +- [Development Board Hardware Manual](https://www.renesas.cn/zh/document/mah/rzn2l-group-users-manual-hardware?r=1622651) +- [RZ/N2L MCU Quick Start Guide](https://www.renesas.cn/zh/document/apn/rzt2-rzn2-device-setup-guide-flash-boot-application-note?r=1622651) +- [RZ/N2L Easy Download Guide](https://www.renesas.cn/zh/document/gde/rzn2l-easy-download-guide?r=1622651) +- [Renesas RZ/N2L Group](https://www.renesas.cn/zh/document/fly/renesas-rzn2l-group?r=1622651) + +**FSP Configuration** + +If you need to modify Renesas BSP peripheral configurations or add new peripheral ports, you will need to use the Renesas [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) configuration tool. Please follow the steps below. If you encounter any issues during the configuration, feel free to ask on the [RT-Thread Community Forum](https://club.rt-thread.org/). + +1. [Download the Flexible Software Package (FSP) | Renesas](https://github.com/renesas/rzn-fsp/releases/download/v2.0.0/setup_rznfsp_v2_0_0_rzsc_v2024-01.1.exe), please use version FSP 2.0.0. +2. Refer to the document [How to Import Board Support Package](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191) to add the **"RSK-RZN2L Board Support Package"** to FSP. +3. Refer to the document: [RA Series Using FSP to Configure Peripheral Drivers](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动). + +**ENV Configuration** + +- How to use the ENV tool: [RT-Thread ENV Tool User Manual](https://www.rt-thread.org/document/site/#/development-tools/env/env) + +By default, this BSP only enables UART0. To use more advanced features like components, software packages, etc., you need to configure the BSP using the ENV tool. + +Steps: +1. Open the env tool in the BSP directory. +2. Enter the `menuconfig` command to configure the project. After configuration, save and exit. +3. Enter the `pkgs --update` command to update the software packages. +4. Enter the `scons --target=iar` command to regenerate the project. + +## Contact Information + +If you have any thoughts or suggestions during usage, feel free to contact us via the [RT-Thread Community Forum](https://club.rt-thread.org/). + +## Contribute Code + +If you are interested in the RSK-RZN2L and have some exciting projects to share with the community, we welcome your code contributions. You can refer to [How to Contribute Code to RT-Thread](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github). \ No newline at end of file diff --git a/bsp/renesas/rzn2l_rsk/README_zh.md b/bsp/renesas/rzn2l_rsk/README_zh.md new file mode 100644 index 00000000000..6c7579e7468 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/README_zh.md @@ -0,0 +1,168 @@ +# 瑞萨 RSK-RZN2L 开发板 BSP 说明 + +**中文** | [**English**](./README.md) + +## 简介 + +本文档为瑞萨 RSK-RZN2L 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。 + +主要内容如下： + +- 开发板介绍 +- BSP 快速上手指南 + +## 开发板介绍 + +基于瑞萨 RZ/N2L 开发的 RSK-RZN2L MCU 评估板，通过灵活配置软件包和 IDE，对嵌入系统应用程序进行开发。 + +开发板正面外观如下图： + +![image-20240914173709363](figures/image-20240914173709363.png) + +该开发板常用 **板载资源** 如下： + +- MPU：R9A07G084M04GBG，最大工作频率 400MHz，Arm® Cortex®-R52 片上浮点单元（FPU）和 NEON™，1.5 MB 片上 SRAM，Ethernet MAC，EtherCAT，USB 2.0 高速，CAN/CANFD，xSPI 和 ΔΣ 接口等各种通信接口，以及安全功能。 +- 调试接口：板载 J-Link 接口 +- 扩展接口：两个 PMOD 连接器 + +**更多详细资料及工具** + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **片上外设** | **支持情况** | **备注** | +| :----------------- | :----------------- | :------------- | +| UART | 支持 | UART0 为默认日志输出端口 | +| GPIO | 支持 | | +| HWIMER | 支持 | | +| IIC | 支持 | | +| WDT | 支持 | | +| RTC | 支持 | | +| ADC | 支持 | | +| DAC | 支持 | | +| SPI | 支持 | | +| FLASH | 支持 | | +| PWM | 支持 | | +| CAN | 支持 | | +| ETH | 支持 | | +| 持续更新中... | | | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + +### 快速上手 + +本 BSP 目前仅提供 IAR 工程。下面以 [IAR Embedded Workbench for Arm](https://www.iar.com/products/architectures/arm/iar-embedded-workbench-for-arm/) 开发环境为例，介绍如何将系统运行起来。 + +**硬件连接** + +使用 USB 数据线连接开发板到 PC，使用 J-link 接口下载和 DEBUG 程序。 + +**编译下载** + +- 进入 bsp 目录下，打开 ENV 使用命令 `scons --target=iar` 生成 IAR工程。 +- 编译：双击 project.eww 文件，打开 IAR 工程，编译程序。 +- 调试：IAR 左上方导航栏点击 `Project->Download and Debug`下载并启动调试。 + +**查看运行结果** + +下载程序成功之后，系统会自动运行并打印系统信息。 + +连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。 + +```bash + \ | / +- RT - Thread Operating System + / | \ 5.1.0 build Mar 14 2024 18:26:01 + 2006 - 2024 Copyright by RT-Thread team + +Hello RT-Thread! +================================================== +This is a iar project which mode is xspi0 execution! +================================================== +msh >help +RT-Thread shell commands: +clear - clear the terminal screen +version - show RT-Thread version information +list - list objects +backtrace - print backtrace of a thread +help - RT-Thread shell help +ps - List threads in the system +free - Show the memory usage in the system +pin - pin [option] + +msh > +``` + +**应用入口函数** + +应用层的入口函数在 **src\hal_entry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。 + +```c +#define LED_PIN BSP_IO_PORT_18_PIN_2 /* Onboard LED pins */ + +void hal_entry(void) +{ + rt_kprintf("\nHello RT-Thread!\n"); + rt_kprintf("==================================================\n"); + rt_kprintf("This is a iar project which mode is xspi0 execution!\n"); + rt_kprintf("==================================================\n"); + + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} +``` + +### 进阶使用 + +**资料及文档** + +- [开发板官网主页](https://www.renesas.cn/zh/products/microcontrollers-microprocessors/rz-mpus/rzn2l-integrated-tsn-compliant-3-port-gigabit-ethernet-switch-enables-various-industrial-applications) +- [开发板数据手册](https://www.renesas.cn/zh/document/dst/rzn2l-group-datasheet?r=1622651) +- [开发板硬件手册](https://www.renesas.cn/zh/document/mah/rzn2l-group-users-manual-hardware?r=1622651) +- [RZ/N2L MCU 快速入门指南](https://www.renesas.cn/zh/document/apn/rzt2-rzn2-device-setup-guide-flash-boot-application-note?r=1622651) +- [RZ/N2L Easy Download Guide](https://www.renesas.cn/zh/document/gde/rzn2l-easy-download-guide?r=1622651) +- [Renesas RZ/N2L Group](https://www.renesas.cn/zh/document/fly/renesas-rzn2l-group?r=1622651) + +**FSP 配置** + +需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。 + +1. [下载灵活配置软件包 (FSP) | Renesas](https://github.com/renesas/rzn-fsp/releases/download/v2.0.0/setup_rznfsp_v2_0_0_rzsc_v2024-01.1.exe)，请使用 FSP 2.0.0 版本 +2. 如何将 **”RSK-RZN2L板级支持包“**添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191) +3. 请参考文档：[RA系列使用FSP配置外设驱动](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/tutorial/make-bsp/renesas-ra/RA系列使用FSP配置外设驱动?id=ra系列使用-fsp-配置外设驱动)。 + +**ENV 配置** + +- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env) + +此 BSP 默认只开启了 UART0 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。 + +步骤如下： +1. 在 bsp 下打开 env 工具。 +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 +3. 输入`pkgs --update`命令更新软件包。 +4. 输入`scons --target=iar` 命令重新生成工程。 + +## 联系人信息 + +在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们 [RT-Thread 社区论坛](https://club.rt-thread.org/) + +## 贡献代码 + +如果您对 RSK-RZN2L 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。 diff --git a/bsp/renesas/rzn2l_rsk/SConscript b/bsp/renesas/rzn2l_rsk/SConscript new file mode 100644 index 00000000000..889ba12c85f --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/SConscript @@ -0,0 +1,28 @@ +# for module compiling +import os +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +CPPPATH = [cwd] +group = [] +list = os.listdir(cwd) + +if rtconfig.PLATFORM in ['iccarm']: + group = DefineGroup('', src, depend = [''], CPPPATH = CPPPATH) +elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): + if GetOption('target') != 'mdk5': + CPPPATH = [cwd] + src = Glob('./src/*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + group = group + SConscript(os.path.join(d, 'SConscript')) + +Return('group') diff --git a/bsp/renesas/rzn2l_rsk/SConstruct b/bsp/renesas/rzn2l_rsk/SConstruct new file mode 100644 index 00000000000..ec52972c99a --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/SConstruct @@ -0,0 +1,54 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +rtconfig.BSP_LIBRARY_TYPE = None + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/renesas/rzn2l_rsk/board/Kconfig b/bsp/renesas/rzn2l_rsk/board/Kconfig new file mode 100644 index 00000000000..994910cf14a --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/board/Kconfig @@ -0,0 +1,201 @@ +menu "Hardware Drivers Config" + + config SOC_R9A07G084 + bool + select SOC_SERIES_R9A07G0 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + + menu "Onboard Peripheral Drivers" + + config BSP_USING_ETHERCAT_EOE + bool "Enable EtherCAT EOE example" + select BSP_USING_ETH + default n + if BSP_USING_ETHERCAT_EOE + config RT_LWIP_IPADDR + string "set static ip address for eoe slaver" + default "192.168.10.100" + config RT_LWIP_GWADDR + string "set static gateway address for eoe slaver" + default "192.168.10.1" + config RT_LWIP_MSKADDR + string "set static mask address for eoe slaver" + default "255.255.255.0" + endif + + endmenu + + menu "On-chip Peripheral Drivers" + + rsource "../../libraries/HAL_Drivers/Kconfig" + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + select RT_USING_SERIAL_V2 + if BSP_USING_UART + + menuconfig BSP_USING_UART0 + bool "Enable UART0" + default n + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + + menuconfig BSP_USING_CANFD + bool "Enable CANFD" + default n + select RT_USING_CAN + select RT_CAN_USING_CANFD + if BSP_USING_CANFD + config BSP_USING_CANFD0 + bool "Enable CANFD0" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + default n + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C + config BSP_USING_HW_I2C + bool "Enable Hardware I2C BUS" + default n + if BSP_USING_HW_I2C + config BSP_USING_HW_I2C0 + bool "Enable Hardware I2C0 BUS" + default n + endif + if BSP_USING_HW_I2C + config BSP_USING_HW_I2C1 + bool "Enable Hardware I2C1 BUS" + default n + endif + if !BSP_USING_HW_I2C + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default y + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + hex "i2c1 scl pin number" + range 0x0000 0x0B0F + default 0x0B03 + config BSP_I2C1_SDA_PIN + hex "I2C1 sda pin number" + range 0x0000 0x0B0F + default 0x050E + endif + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0 BUS" + default n + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM0 + bool "Enable TIM0" + default n + config BSP_USING_TIM1 + bool "Enable TIM1" + default n + endif + + config BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_SAL + select RT_USING_LWIP + select RT_USING_NETDEV + default n + + endmenu + + menu "Board extended module Drivers" + menuconfig BSP_USING_RW007 + bool "Enable RW007" + default n + select PKG_USING_RW007 + select BSP_USING_SPI + select BSP_USING_SPI2 + select RT_USING_MEMPOOL + select RW007_NOT_USE_EXAMPLE_DRIVERS + + if BSP_USING_RW007 + config RA_RW007_SPI_BUS_NAME + string "RW007 BUS NAME" + default "spi2" + + config RA_RW007_CS_PIN + hex "(HEX)CS pin index" + default 0x1207 + + config RA_RW007_BOOT0_PIN + hex "(HEX)BOOT0 pin index (same as spi clk pin)" + default 0x1204 + + config RA_RW007_BOOT1_PIN + hex "(HEX)BOOT1 pin index (same as spi cs pin)" + default 0x1207 + + config RA_RW007_INT_BUSY_PIN + hex "(HEX)INT/BUSY pin index" + default 0x1102 + + config RA_RW007_RST_PIN + hex "(HEX)RESET pin index" + default 0x1706 + endif + endmenu +endmenu diff --git a/bsp/renesas/rzn2l_rsk/board/SConscript b/bsp/renesas/rzn2l_rsk/board/SConscript new file mode 100644 index 00000000000..a27ea8e470c --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/board/SConscript @@ -0,0 +1,16 @@ +import os +from building import * + +objs = [] +cwd = GetCurrentDir() +list = os.listdir(cwd) +CPPPATH = [cwd] +src = Glob('*.c') + +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/renesas/rzn2l_rsk/board/board.h b/bsp/renesas/rzn2l_rsk/board/board.h new file mode 100644 index 00000000000..cf53068064e --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/board/board.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-11 Wangyuqiang first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#define RZ_SRAM_SIZE 512 /* The SRAM size of the chip needs to be modified */ +#define RZ_SRAM_END (0x10000000 + RZ_SRAM_SIZE * 1024 - 1) + +#ifdef __ARMCC_VERSION +extern int Image$$RAM_END$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$RAM_END$$ZI$$Base) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +#define HEAP_BEGIN (0x10000000) +#endif + +#define HEAP_END RZ_SRAM_END + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define MAX_HANDLERS (512) +#define GIC_IRQ_START 0 +#define GIC_ACK_INTID_MASK (0x000003FFU) +/* number of interrupts on board */ +#define ARM_GIC_NR_IRQS (448) +/* only one GIC available */ +#define ARM_GIC_MAX_NR 1 +/* end defined */ + +#define GICV3_DISTRIBUTOR_BASE_ADDR (0x100000) + +/* the basic constants and interfaces needed by gic */ +rt_inline rt_uint32_t platform_get_gic_dist_base(void) +{ + rt_uint32_t gic_base; + + __get_cp(15, 1, gic_base, 15, 3, 0); + return gic_base + GICV3_DISTRIBUTOR_BASE_ADDR; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/renesas/rzn2l_rsk/board/ports/SConscript b/bsp/renesas/rzn2l_rsk/board/ports/SConscript new file mode 100644 index 00000000000..e8ac9ae59e6 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/board/ports/SConscript @@ -0,0 +1,16 @@ +import os +from building import * + +objs = [] +src = Glob('*.c') +cwd = GetCurrentDir() +CPPPATH = [cwd] + +objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/renesas/rzn2l_rsk/board/ports/gpio_cfg.h b/bsp/renesas/rzn2l_rsk/board/ports/gpio_cfg.h new file mode 100644 index 00000000000..d179d4ab6ca --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/board/ports/gpio_cfg.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-11 Wangyuqiang first version + */ + +/* Number of IRQ channels on the device */ +#define RA_IRQ_MAX 16 + +/* PIN to IRQx table */ +#define PIN2IRQX_TABLE \ +{ \ + switch (pin) \ + { \ + case BSP_IO_PORT_00_PIN_1: \ + case BSP_IO_PORT_09_PIN_2: \ + case BSP_IO_PORT_18_PIN_3: \ + return 0; \ + case BSP_IO_PORT_00_PIN_3: \ + case BSP_IO_PORT_07_PIN_4: \ + case BSP_IO_PORT_18_PIN_4: \ + return 1; \ + case BSP_IO_PORT_01_PIN_2: \ + return 2; \ + case BSP_IO_PORT_01_PIN_4: \ + return 3; \ + case BSP_IO_PORT_02_PIN_0: \ + case BSP_IO_PORT_22_PIN_2: \ + return 4; \ + case BSP_IO_PORT_03_PIN_5: \ + case BSP_IO_PORT_13_PIN_2: \ + return 5; \ + case BSP_IO_PORT_14_PIN_2: \ + case BSP_IO_PORT_21_PIN_5: \ + return 6; \ + case BSP_IO_PORT_16_PIN_3: \ + return 7; \ + case BSP_IO_PORT_03_PIN_6: \ + case BSP_IO_PORT_16_PIN_6: \ + return 8; \ + case BSP_IO_PORT_03_PIN_7: \ + case BSP_IO_PORT_21_PIN_6: \ + return 9; \ + case BSP_IO_PORT_04_PIN_4: \ + case BSP_IO_PORT_18_PIN_1: \ + case BSP_IO_PORT_21_PIN_7: \ + return 10; \ + case BSP_IO_PORT_10_PIN_4: \ + case BSP_IO_PORT_18_PIN_6: \ + return 11; \ + case BSP_IO_PORT_05_PIN_0: \ + case BSP_IO_PORT_05_PIN_4: \ + case BSP_IO_PORT_05_PIN_6: \ + return 12; \ + case BSP_IO_PORT_00_PIN_4: \ + case BSP_IO_PORT_00_PIN_7: \ + case BSP_IO_PORT_05_PIN_1: \ + return 13; \ + case BSP_IO_PORT_02_PIN_2: \ + case BSP_IO_PORT_03_PIN_0: \ + case BSP_IO_PORT_05_PIN_2: \ + return 14; \ + case BSP_IO_PORT_02_PIN_3: \ + case BSP_IO_PORT_05_PIN_3: \ + case BSP_IO_PORT_22_PIN_0: \ + return 15; \ + default : \ + return -1; \ + } \ +} diff --git a/bsp/renesas/rzn2l_rsk/buildinfo.ipcf b/bsp/renesas/rzn2l_rsk/buildinfo.ipcf new file mode 100644 index 00000000000..f80fac71ee5 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/buildinfo.ipcf @@ -0,0 +1,153 @@ + + + + R9A07G084M04 + + + $PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include + $PROJ_DIR$/rzn/fsp/inc + $PROJ_DIR$/rzn/fsp/inc/api + $PROJ_DIR$/rzn/fsp/inc/instances + $PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr + $PROJ_DIR$/rzn_cfg/fsp_cfg + $PROJ_DIR$/rzn_cfg/fsp_cfg/bsp + $PROJ_DIR$/rzn_gen + $PROJ_DIR$/src + $PROJ_DIR$ + + + _RZN_ORDINAL=1 + _RZN_CORE=CR52_0 + _RENESAS_RZN_ + + + $PROJ_DIR$/rzn/arm/CMSIS_5/CMSIS/Core_R/Include + $PROJ_DIR$/rzn/fsp/inc + $PROJ_DIR$/rzn/fsp/inc/api + $PROJ_DIR$/rzn/fsp/inc/instances + $PROJ_DIR$/rzn/fsp/src/bsp/mcu/all/cr + $PROJ_DIR$/rzn_cfg/fsp_cfg + $PROJ_DIR$/rzn_cfg/fsp_cfg/bsp + $PROJ_DIR$/rzn_gen + $PROJ_DIR$/src + $PROJ_DIR$ + + + _RZN_ORDINAL=1 + _RZN_CORE=CR52_0 + _RENESAS_RZN_ + + + true + $PROJ_DIR$/script/fsp_xspi0_boot.icf + + + --config_search "$PROJ_DIR$" + + + system_init + + + + + RASC_EXE_PATH + D:\manufacture_apps\Renesas\fsp\rzn_v2.0.0\eclipse\rasc.exe + + + + + + rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h + rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h + rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h + rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h + rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h + rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h + rzn/arm/CMSIS_5/LICENSE.txt + rzn/board/rzn2l_rsk/board.h + rzn/board/rzn2l_rsk/board_ethernet_phy.h + rzn/board/rzn2l_rsk/board_init.c + rzn/board/rzn2l_rsk/board_init.h + rzn/board/rzn2l_rsk/board_leds.c + rzn/board/rzn2l_rsk/board_leds.h + rzn/fsp/inc/api/bsp_api.h + rzn/fsp/inc/api/r_ioport_api.h + rzn/fsp/inc/api/r_transfer_api.h + rzn/fsp/inc/api/r_uart_api.h + rzn/fsp/inc/fsp_common_api.h + rzn/fsp/inc/fsp_features.h + rzn/fsp/inc/fsp_version.h + rzn/fsp/inc/instances/r_ioport.h + rzn/fsp/inc/instances/r_sci_uart.h + rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h + rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h + rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h + rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c + rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c + rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c + rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c + rzn/fsp/src/bsp/mcu/all/bsp_cache.c + rzn/fsp/src/bsp/mcu/all/bsp_cache.h + rzn/fsp/src/bsp/mcu/all/bsp_clocks.c + rzn/fsp/src/bsp/mcu/all/bsp_clocks.h + rzn/fsp/src/bsp/mcu/all/bsp_common.c + rzn/fsp/src/bsp/mcu/all/bsp_common.h + rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h + rzn/fsp/src/bsp/mcu/all/bsp_delay.c + rzn/fsp/src/bsp/mcu/all/bsp_delay.h + rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h + rzn/fsp/src/bsp/mcu/all/bsp_io.c + rzn/fsp/src/bsp/mcu/all/bsp_io.h + rzn/fsp/src/bsp/mcu/all/bsp_irq.c + rzn/fsp/src/bsp/mcu/all/bsp_irq.h + rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h + rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h + rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c + rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h + rzn/fsp/src/bsp/mcu/all/bsp_reset.c + rzn/fsp/src/bsp/mcu/all/bsp_reset.h + rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c + rzn/fsp/src/bsp/mcu/all/bsp_tfu.h + rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c + rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h + rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c + rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h + rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c + rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h + rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h + rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h + rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c + rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c + rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h + rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h + rzn/fsp/src/r_ioport/r_ioport.c + rzn/fsp/src/r_sci_uart/r_sci_uart.c + + + rzn_cfg/fsp_cfg/bsp/board_cfg.h + rzn_cfg/fsp_cfg/bsp/bsp_cfg.h + rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h + rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h + rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h + rzn_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h + rzn_cfg/fsp_cfg/bsp/bsp_memory_cfg.h + rzn_cfg/fsp_cfg/bsp/bsp_pin_cfg.h + rzn_cfg/fsp_cfg/r_ioport_cfg.h + rzn_cfg/fsp_cfg/r_sci_uart_cfg.h + + + rzn_gen/bsp_clock_cfg.h + rzn_gen/common_data.c + rzn_gen/common_data.h + rzn_gen/hal_data.c + rzn_gen/hal_data.h + rzn_gen/main.c + rzn_gen/pin_data.c + rzn_gen/vector_data.c + rzn_gen/vector_data.h + + + src/hal_entry.c + + + diff --git a/bsp/renesas/rzn2l_rsk/configuration.xml b/bsp/renesas/rzn2l_rsk/configuration.xml new file mode 100644 index 00000000000..e2a3575d5f0 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/configuration.xml @@ -0,0 +1,1111 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Board Support Package Common Files + Renesas.RZN.2.0.0.pack + + + Memory Config Checking + Renesas.RZN.2.0.0.pack + + + I/O Port + Renesas.RZN.2.0.0.pack + + + Arm CMSIS Version 5 - Core + Arm.CMSIS5.5.7.0+renesas.1.fsp.2.0.0.pack + + + RSK+RZN2L Board Support Files (xSPI0 x1 boot mode) + Renesas.RZN_board_rzn2l_rsk.2.0.0.pack + + + Board support package for R9A07G084M04GBG + Renesas.RZN_mcu_rzn2l.2.0.0.pack + + + Board support package for RZN2L + Renesas.RZN_mcu_rzn2l.2.0.0.pack + + + Board support package for RZN2L - FSP Data + Renesas.RZN_mcu_rzn2l.2.0.0.pack + + + SCI UART + Renesas.RZN.2.0.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/renesas/rzn2l_rsk/figures/image-20240914173709363.png b/bsp/renesas/rzn2l_rsk/figures/image-20240914173709363.png new file mode 100644 index 00000000000..f36978de7bc Binary files /dev/null and b/bsp/renesas/rzn2l_rsk/figures/image-20240914173709363.png differ diff --git a/bsp/renesas/rzn2l_rsk/memory_regions.icf b/bsp/renesas/rzn2l_rsk/memory_regions.icf new file mode 100644 index 00000000000..619084b72f3 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/memory_regions.icf @@ -0,0 +1,38 @@ + + /* generated memory regions file - do not edit */ + define symbol ATCM_START = 0x00000000; + define symbol ATCM_LENGTH = 0x20000; + define symbol BTCM_START = 0x00100000; + define symbol BTCM_LENGTH = 0x20000; + define symbol SYSTEM_RAM_START = 0x10000000; + define symbol SYSTEM_RAM_LENGTH = 0x180000; + define symbol SYSTEM_RAM_MIRROR_START = 0x30000000; + define symbol SYSTEM_RAM_MIRROR_LENGTH = 0x180000; + define symbol xSPI0_CS0_SPACE_MIRROR_START = 0x40000000; + define symbol xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol xSPI0_CS1_SPACE_MIRROR_START = 0x44000000; + define symbol xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol xSPI1_CS0_SPACE_MIRROR_START = 0x48000000; + define symbol xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol CS0_SPACE_MIRROR_START = 0x50000000; + define symbol CS0_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol CS2_SPACE_MIRROR_START = 0x54000000; + define symbol CS2_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol CS3_SPACE_MIRROR_START = 0x58000000; + define symbol CS3_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol CS5_SPACE_MIRROR_START = 0x5C000000; + define symbol CS5_SPACE_MIRROR_LENGTH = 0x4000000; + define symbol xSPI0_CS0_SPACE_START = 0x60000000; + define symbol xSPI0_CS0_SPACE_LENGTH = 0x4000000; + define symbol xSPI0_CS1_SPACE_START = 0x64000000; + define symbol xSPI0_CS1_SPACE_LENGTH = 0x4000000; + define symbol xSPI1_CS0_SPACE_START = 0x68000000; + define symbol xSPI1_CS0_SPACE_LENGTH = 0x4000000; + define symbol CS0_SPACE_START = 0x70000000; + define symbol CS0_SPACE_LENGTH = 0x4000000; + define symbol CS2_SPACE_START = 0x74000000; + define symbol CS2_SPACE_LENGTH = 0x4000000; + define symbol CS3_SPACE_START = 0x78000000; + define symbol CS3_SPACE_LENGTH = 0x4000000; + define symbol CS5_SPACE_START = 0x7C000000; + define symbol CS5_SPACE_LENGTH = 0x4000000; diff --git a/bsp/renesas/rzn2l_rsk/project.ewd b/bsp/renesas/rzn2l_rsk/project.ewd new file mode 100644 index 00000000000..f60045d9c51 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/project.ewd @@ -0,0 +1,3276 @@ + + + 4 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + 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$PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler_comm.c + + + $PROJ_DIR$\..\..\..\src\scheduler_up.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + libcpu + + $PROJ_DIR$\..\..\..\libcpu\arm\common\atomic_arm.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\div0.c + + + $PROJ_DIR$\..\..\..\libcpu\arm\common\showmem.c + + + + POSIX + + + $PROJ_DIR$\buildinfo.ipcf + + diff --git a/bsp/renesas/rzn2l_rsk/project.eww b/bsp/renesas/rzn2l_rsk/project.eww new file mode 100644 index 00000000000..c2cb02eb1e8 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/renesas/rzn2l_rsk/rtconfig.h b/bsp/renesas/rzn2l_rsk/rtconfig.h new file mode 100644 index 00000000000..d682c565ba5 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rtconfig.h @@ -0,0 +1,344 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 + +/* kservice optimization */ + +/* end of kservice optimization */ + +/* klibc optimization */ + +/* end of klibc optimization */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 512 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50200 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define ARCH_ARM +#define ARCH_ARM_CORTEX_R +#define ARCH_ARM_CORTEX_R52 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_RENESAS +#define SOC_SERIES_R9A07G0 + +/* Hardware Drivers Config */ + +#define SOC_R9A07G084 + +/* Onboard Peripheral Drivers */ + +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 256 +#define BSP_UART0_TX_BUFSIZE 0 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Board extended module Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rtconfig.py b/bsp/renesas/rzn2l_rsk/rtconfig.py new file mode 100644 index 00000000000..57a98c2bcb6 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rtconfig.py @@ -0,0 +1,123 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-r52' +CROSS_TOOL='gcc' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'D:/IAR Systems/Embedded Workbench 9.2' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +# BUILD = 'release' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + NM = PREFIX + 'nm' + + DEVICE = ' -mcpu=cortex-r52 -marm -mfloat-abi=hard -mfpu=neon-fp-armv8 -munaligned-access -fdiagnostics-parseable-fixits -Og -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -funwind-tables' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=arm ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T script/fsp_xspi0_boot.ld -L script/' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g -Wall' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -Os' + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' + # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-R52' + CFLAGS += ' -e' + CFLAGS += ' --arm' + CFLAGS += ' --float-abi=hard' + CFLAGS += ' --fpu=neon-fp-armv8' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-R52' + AFLAGS += ' --arm' + AFLAGS += ' --float-abi hard' + AFLAGS += ' --fpu neon-fp-armv8' + # AFLAGS += ' --unaligned-access' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "script/fsp_xspi0_boot.icf"' + LFLAGS += ' --entry Reset_Handler' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/renesas/rzn2l_rsk/rzn/SConscript b/bsp/renesas/rzn2l_rsk/rzn/SConscript new file mode 100644 index 00000000000..41038bee62c --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/SConscript @@ -0,0 +1,28 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm']: + Return('group') +elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): + if GetOption('target') != 'mdk5': + src += Glob(cwd + '/fsp/src/bsp/mcu/all/*.c') + src += Glob(cwd + '/fsp/src/bsp/mcu/all/cr/*.c') + src += Glob(cwd + '/fsp/src/bsp/mcu/r*/*.c') + src += Glob(cwd + '/fsp/src/r_*/*.c') + src += Glob(cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/*.c') + src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c'] + src += [cwd + '/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c'] + CPPPATH = [ cwd + '/arm/CMSIS_5/CMSIS/Core_R/Include', + cwd + '/fsp/inc', + cwd + '/fsp/inc/api', + cwd + '/fsp/inc/instances',] + +group = DefineGroup('rzn', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h new file mode 100644 index 00000000000..e1e68604b26 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_compiler.h @@ -0,0 +1,290 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @date 31. August 2021 + ******************************************************************************/ +/* + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This file is based on the "\CMSIS\Core\Include\cmsis_compliler.h" + * + * Changes: + * - No Changes. + */ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h new file mode 100644 index 00000000000..174b5b8e561 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_cp15.h @@ -0,0 +1,783 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @date 02. February 2024 + ******************************************************************************/ +/* + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This file is based on the "CMSIS\Core_A\Include\cmsis_cp15.h" + * + * Changes: + * Renesas Electronics Corporation on 2021-08-31 + * - Changed to be related to Cortex-R52 by + * Renesas Electronics Corporation on 2024-02-02 + * - Functions are sorted according to the Arm technical reference. + * - Added some functions to convert BSP into C language. + */ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get CTR + \return Cache Type Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CTR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Get CSSELR + \return CSSELR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; + __get_CP(15, 2, result, 0, 0, 0); + return result; +} + +/** \brief Set CSSELR + */ +__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value) +{ + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get SCTLR + + This function assigns the given value to the System Control Register. + + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set SCTLR + \param [in] value System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t value) +{ + __set_CP(15, 0, value, 1, 0, 0); +} + + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] value Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t value) +{ + __set_CP(15, 0, value, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] value Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t value) +{ + __set_CP(15, 0, value, 1, 0, 2); +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] value Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t value) +{ + __set_CP(15, 0, value, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] value Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t value) +{ + __set_CP(15, 0, value, 3, 0, 0); +} + +/** \brief Get ICC_PMR + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_PMR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 4, 6, 0); + return result; +} + +/** \brief Set ICC_PMR + */ +__STATIC_FORCEINLINE void __set_ICC_PMR(uint32_t value) +{ + __set_CP(15, 0, value, 4, 6, 0); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] value Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t value) +{ + __set_CP(15, 0, value, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] value Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t value) +{ + __set_CP(15, 0, value, 5, 0, 1); +} + +/** \brief Set PRSELR + + This function assigns the given value to the Protection Region Selection Register. + + \param [in] value Protection Region Selection Register to set + */ +__STATIC_FORCEINLINE void __set_PRSELR(uint32_t value) +{ + __set_CP(15, 0, value, 6, 2, 1); +} + +/** \brief Get PRBAR + + This function returns the value of the Protection Region Base Address Register. + + \return Protection Region Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_PRBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 6, 3, 0); + return result; +} + +/** \brief Set PRBAR + + This function assigns the given value to the Protection Region Base Address Register. + + \param [in] value Protection Region Base Address Register to set + */ +__STATIC_FORCEINLINE void __set_PRBAR(uint32_t value) +{ + __set_CP(15, 0, value, 6, 3, 0); +} + +/** \brief Get PRLAR + + This function returns the value of the Protection Region Limit Address Register. + + \return Protection Region Limit Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_PRLAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 6, 3, 1); + return result; +} + +/** \brief Set PRLAR + + This function assigns the given value to the Protection Region Limit Address Register. + + \param [in] value Protection Region Limit Address Register to set + */ +__STATIC_FORCEINLINE void __set_PRLAR(uint32_t value) +{ + __set_CP(15, 0, value, 6, 3, 1); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set ICIVAU + */ +__STATIC_FORCEINLINE void __set_ICIVAU(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 1); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCIVAC + */ +__STATIC_FORCEINLINE void __set_DCIVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCISW + */ +__STATIC_FORCEINLINE void __set_DCISW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 6, 2); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCCVAC + */ +__STATIC_FORCEINLINE void __set_DCCVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCCSW + */ +__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 10, 2); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set DCCIVAC + */ +__STATIC_FORCEINLINE void __set_DCCIVAC(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 1); +} + +/** \brief Set DCCISW + */ +__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value) +{ + __set_CP(15, 0, value, 7, 14, 2); +} + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set MAIR0 + + This function assigns the given value to the Memory Attribute Indirection Registers 0. + + \param [in] value Memory Attribute Indirection Registers 0 to set + */ +__STATIC_FORCEINLINE void __set_MAIR0(uint32_t value) +{ + __set_CP(15, 0, value, 10, 2, 0); +} + +/** \brief Set MAIR1 + + This function assigns the given value to the Memory Attribute Indirection Registers 1. + + \param [in] value Memory Attribute Indirection Registers 1 to set + */ +__STATIC_FORCEINLINE void __set_MAIR1(uint32_t value) +{ + __set_CP(15, 0, value, 10, 2, 1); +} + +/** \brief Get IMP_SLAVEPCTLR + + This function returns the value of the Slave Port Control Register. + + \return Slave Port Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_IMP_SLAVEPCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 11, 0, 0); + return result; +} + +/** \brief Set IMP_SLAVEPCTLR + + This function assigns the given value to the Slave Port Control Register. + + \param [in] value Slave Port Control Register value to set + */ +__STATIC_FORCEINLINE void __set_IMP_SLAVEPCTLR(uint32_t value) +{ + __set_CP(15, 0, value, 11, 0, 0); +} + +/** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] value Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t value) +{ + __set_CP(15, 0, value, 12, 0, 0); +} + +/** \brief Get MVBAR + + This function returns the value of the Monitor Vector Base Address Register. + + \return Monitor Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_MVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Set MVBAR + + This function assigns the given value to the Monitor Vector Base Address Register. + + \param [in] value Monitor Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_MVBAR(uint32_t value) +{ + __set_CP(15, 0, value, 12, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get ICC_RPR + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_RPR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 11, 3); + return result; +} + +/** \brief Get ICC_IAR1 + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_IAR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 12, 0); + return result; +} + +/** \brief Set ICC_EOIR1 + */ +__STATIC_FORCEINLINE void __set_ICC_EOIR1(uint32_t value) +{ + __set_CP(15, 0, value, 12, 12, 0); +} + +/** \brief Get ICC_HPPIR1 + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_HPPIR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 12, 2); + return result; +} + +/** \brief Get ICC_BPR1 + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_BPR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 12, 3); + return result; +} + +/** \brief Set ICC_BPR1 + */ +__STATIC_FORCEINLINE void __set_ICC_BPR1(uint32_t value) +{ + __set_CP(15, 0, value, 12, 12, 3); +} + +/** \brief Get ICC_CTLR + */ +__STATIC_FORCEINLINE uint32_t __get_ICC_CTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 12, 4); + return result; +} + +/** \brief Set ICC_CTLR + */ +__STATIC_FORCEINLINE void __set_ICC_CTLR(uint32_t value) +{ + __set_CP(15, 0, value, 12, 12, 4); +} + +/** \brief Set ICC_IGRPEN1 + */ +__STATIC_FORCEINLINE void __set_ICC_IGRPEN1(uint32_t value) +{ + __set_CP(15, 0, value, 12, 12, 7); +} + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 0, 0); + return result; +} + +/** \brief Set CNTKCTL + + This function assigns the given value to Counter-timer Kernel Control Register (CNTKCTL). + + \param [in] value CNTKCTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTKCTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 1, 0); +} + +/** \brief Get CNTKCTL + + This function returns the value of the Counter-timer kernel Control Register (CNTKCTL). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTKCTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 1, 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +/** \brief Set CNTV_CTL + + This function assigns the given value to PL1 Virtual Timer Control Register (CNTV_CTL). + + \param [in] value CNTV_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTV_CTL(uint32_t value) +{ + __set_CP(15, 0, value, 14, 3, 1); +} + +/** \brief Get CNTV_CTL register + \return CNTV_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTV_CTL(void) +{ + uint32_t result; + __get_CP(15, 0, result, 14, 3, 1); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get CNTPCT + + This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). + + \return CNTPCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void) +{ + uint64_t result; + __get_CP64(15, 0, result, 14); + return result; +} + +/** \brief Set ICC_SGI1R + */ +__STATIC_FORCEINLINE void __set_ICC_SGI1R(uint64_t value) +{ + __set_CP64(15, 0, value, 12); +} + +/** \brief Get CNTVCT + + This function returns the value of the 64 bits PL1 Virtual Count Register (CNTVCT). + + \return CNTVCT Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTVCT(void) +{ + uint64_t result; + __get_CP64(15, 1, result, 14); + return result; +} + +/** \brief Set CNTP_CVAL + + This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \param [in] value CNTP_CVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value) +{ + __set_CP64(15, 2, value, 14); +} + +/** \brief Get CNTP_CVAL + + This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). + + \return CNTP_CVAL Register value + */ +__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void) +{ + uint64_t result; + __get_CP64(15, 2, result, 14); + return result; +} + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h new file mode 100644 index 00000000000..1e6e8bddcb3 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_gcc.h @@ -0,0 +1,2233 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @date 02. February 2024 + ******************************************************************************/ +/* + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This file is based on the "\CMSIS\Core\Include\cmsis_gcc.h" + * + * Changes: + * Renesas Electronics Corporation on 2021-08-31 + * - Add CP15 descriptions by + * Renesas Electronics Corporation on 2024-02-02 + * - Added functions related to FPEXC registers. + */ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +/** + * \brief Get FPEXC + * \details Returns the current value of the Floating Point Exception Control register. + * \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC (void) +{ +#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined(__FPU_USED) && (__FPU_USED == 1U))) + + uint32_t result; + + __ASM volatile ("VMRS %0, fpexc" : "=r" (result)); + + return result; +#else + + return 0U; +#endif +} + +/** + * \brief Set FPEXC + * \details Assigns the given value to the Floating Point Exception Control register. + * \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC (uint32_t fpexc) +{ +#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined(__FPU_USED) && (__FPU_USED == 1U))) + + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#else + (void) fpexc; +#endif +} + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h new file mode 100644 index 00000000000..a6882cfe80b --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_iccarm.h @@ -0,0 +1,958 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @date 02. February 2024 + ******************************************************************************/ +// ------------------------------------------------------------------------------ +// +// Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. +// +// This file is based on the "\CMSIS\Core\Include\cmsis_iccarm.h" +// +// Changes: +// Renesas Electronics Corporation on 2021-08-31 +// - Changed to be related to Cortex-R52 by +// Renesas Electronics Corporation on 2024-02-02 +// - Added functions related to FPEXC registers. +// - Moved the process of defining compiler macros for CPU architectures to renesas.h. +// +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", (VALUE))) + #else + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void) VALUE) + + #define __get_FPEXC() (0) + #define __set_FPEXC(VALUE) ((void) VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + ((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT))) + + #define __get_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) + + #define __set_CP64(cp, op1, Rt, CRm) \ + __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + + #define __get_FPEXC() (0) + #define __set_FPEXC(VALUE) ((void) VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h new file mode 100644 index 00000000000..fa9f84c16f7 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/cmsis_version.h @@ -0,0 +1,46 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @date 31. August 2021 + ******************************************************************************/ +/* + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This file is based on the "\CMSIS\Core\Include\cmsis_version.h" + * + * Changes: + * - No Changes. + */ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h new file mode 100644 index 00000000000..615ae49a34d --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/CMSIS/Core_R/Include/core_cr52.h @@ -0,0 +1,312 @@ +/**************************************************************************//** + * @file core_cr52.h + * @brief CMSIS Cortex-R52 Core Peripheral Access Layer Header File + * @date 31. August 2021 + ******************************************************************************/ +/* + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This file is based on the "\CMSIS\Core\Include\core_armv8mml.h" + * + * Changes: + * Renesas Electronics Corporation on 2021-08-31 + * - Changed to be related to Cortex-R52 by + */ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CR52_H_GENERIC +#define __CORE_CR52_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_R52 + @{ + */ + +#if defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #define __FPU_D32 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #ifndef __ARMVFP_D16__ + #define __FPU_D32 1U + #endif + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif +#endif + +#include "cmsis_version.h" + +/* CMSIS CR52 definitions */ +#define __CR52_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CR52_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CR52_CMSIS_VERSION ((__CR52_CMSIS_VERSION_MAIN << 16U) | \ + __CR52_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_R (52U) /*!< Cortex-R Core */ + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CR52_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CR52_H_DEPENDANT +#define __CORE_CR52_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_R52 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_GIC Generic Interrupt Controller (GIC) + \brief Type definitions for the GIC Registers + @{ +*/ + + /** + \brief Structure type to access the Generic Interrupt Controller (GIC) for GICD. + */ +typedef struct +{ + __IOM uint32_t GICD_CTLR; /*!< Offset: 0x0000 (R/W) Distributor Control Register */ + __IM uint32_t GICD_TYPER; /*!< Offset: 0x0004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t GICD_IIDR; /*!< Offset: 0x0008 (R/ ) Distributor Implementer Identification Register */ + uint32_t RESERVED0[30U]; + __IOM uint32_t GICD_IGROUPR[30U]; /*!< Offset: 0x0084 (R/W) Interrupt Group Registers 1 - 30 */ + uint32_t RESERVED1[2U]; + __IOM uint32_t GICD_ISENABLER[30U]; /*!< Offset: 0x0104 (R/W) Interrupt Set-Enable Registers 1 - 30 */ + uint32_t RESERVED2[2U]; + __IOM uint32_t GICD_ICENABLER[30U]; /*!< Offset: 0x0184 (R/W) Interrupt Clear-Enable Registers 1 - 30 */ + uint32_t RESERVED3[2U]; + __IOM uint32_t GICD_ISPENDR[30U]; /*!< Offset: 0x0204 (R/W) Interrupt Set-Pending Registers 1 - 30 */ + uint32_t RESERVED4[2U]; + __IOM uint32_t GICD_ICPENDR[30U]; /*!< Offset: 0x0284 (R/W) Interrupt Clear-Pending Registers 1 - 30 */ + uint32_t RESERVED5[2U]; + __IOM uint32_t GICD_ISACTIVER[30U]; /*!< Offset: 0x0304 (R/W) Interrupt Set-Active Registers 1 - 30 */ + uint32_t RESERVED6[2U]; + __IOM uint32_t GICD_ICACTIVER[30U]; /*!< Offset: 0x0384 (R/W) Interrupt Clear-Active Registers 1 - 30 */ + uint32_t RESERVED7[9U]; + __IOM uint32_t GICD_IPRIORITYR[240U]; /*!< Offset: 0x0420 (R/W) Interrupt Priority Registers 8 - 247 */ + uint32_t RESERVED8[266U]; + __IOM uint32_t GICD_ICFGR[60U]; /*!< Offset: 0x0C08 (R/W) Interrupt Configuration Registers 2 - 61 */ +} GICD_Type; + + /** + \brief Structure type to access the Generic Interrupt Controller (GIC) for GICR for Control target. + */ +typedef struct +{ + __IM uint32_t GICR_CTLR; /*!< Offset: 0x0000 (R/ ) Redistributor Control Register */ + __IM uint32_t GICR_IIDR; /*!< Offset: 0x0004 (R/ ) Redistributor Implementer Identification Register */ + __IM uint32_t GICR_TYPER[2]; /*!< Offset: 0x0008 (R/ ) Redistributor Type Register */ + uint32_t RESERVED0; + __IOM uint32_t GICR_WAKER; /*!< Offset: 0x0014 (R/W) Redistributor Wake Register */ +} GICR_CONTROL_TARGET_Type; + + /** + \brief Structure type to access the Generic Interrupt Controller (GIC) for GICR for SGI and PPI. + */ +typedef struct +{ + uint32_t RESERVED0[32]; + __IOM uint32_t GICR_IGROUPR0; /*!< Offset: 0x0080 (R/W) Interrupt Group Register 0 */ + uint32_t RESERVED1[31]; + __IOM uint32_t GICR_ISENABLER0; /*!< Offset: 0x0100 (R/W) Interrupt Set-Enable Register 0 */ + uint32_t RESERVED2[31]; + __IOM uint32_t GICR_ICENABLER0; /*!< Offset: 0x0180 (R/W) Interrupt Clear-Enable Register 0 */ + uint32_t RESERVED3[31]; + __IOM uint32_t GICR_ISPENDR0; /*!< Offset: 0x0200 (R/W) Interrupt Set-Pending Register 0 */ + uint32_t RESERVED4[31]; + __IOM uint32_t GICR_ICPENDR0; /*!< Offset: 0x0280 (R/W) Interrupt Clear-Pending Register 0 */ + uint32_t RESERVED5[31]; + __IOM uint32_t GICR_ISACTIVER0; /*!< Offset: 0x0300 (R/W) Interrupt Set-Active Register 0 */ + uint32_t RESERVED6[31]; + __IOM uint32_t GICR_ICACTIVER0; /*!< Offset: 0x0380 (R/W) Interrupt Clear-Active Register 0 */ + uint32_t RESERVED7[31]; + __IOM uint32_t GICR_IPRIORITYR[8]; /*!< Offset: 0x0400 (R/W) Interrupt Priority Registers 0 - 7 */ + uint32_t RESERVED8[504]; + __IM uint32_t GICR_ICFGR0; /*!< Offset: 0x0C00 (R/ ) Interrupt Configuration Register 0 */ + __IOM uint32_t GICR_ICFGR1; /*!< Offset: 0x0C04 (R/W) Interrupt Configuration Register 1 */ +} GICR_SGI_PPI_Type; + +/*@} end of group CMSIS_GIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define GIC0_BASE (0x94000000UL) /*!< GIC0 Base Address */ +#define GIC1_BASE (0x9C000000UL) /*!< GIC1 Base Address */ +#define GICR_TARGET0_BASE (0x00100000UL) /*!< GICR Base Address (for Control target 0) */ +#define GICR_TARGET0_SGI_PPI_BASE (0x00110000UL) /*!< GICR Base Address (for SGI and PPI target 0) */ + +#define GICD0 ((GICD_Type *) GIC0_BASE ) /*!< GICD configuration struct */ +#define GICD1 ((GICD_Type *) GIC1_BASE ) /*!< GICD configuration struct */ +#define GICR0_TARGET0_IFREG ((GICR_CONTROL_TARGET_Type *) (GIC0_BASE + GICR_TARGET0_BASE) ) /*!< GICR configuration struct for Control target 0 */ +#define GICR1_TARGET0_IFREG ((GICR_CONTROL_TARGET_Type *) (GIC1_BASE + GICR_TARGET0_BASE) ) /*!< GICR configuration struct for Control target 0 */ +#define GICR0_TARGET0_INTREG ((GICR_SGI_PPI_Type *) (GIC0_BASE + GICR_TARGET0_SGI_PPI_BASE) ) /*!< GICR configuration struct for SGI and PPI target 0 */ +#define GICR1_TARGET0_INTREG ((GICR_SGI_PPI_Type *) (GIC1_BASE + GICR_TARGET0_SGI_PPI_BASE) ) /*!< GICR configuration struct for SGI and PPI target 0 */ + +/*@} */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief Get CPSR Register + + This function returns the content of the CPSR Register. + + \return CPSR Register value + */ +__STATIC_INLINE uint32_t __get_CPSR(void) +{ + register uint32_t __regCPSR __ASM("cpsr"); + return(__regCPSR); +} + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ + + +#include + + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* __CORE_CR52_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/LICENSE.txt b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/LICENSE.txt new file mode 100644 index 00000000000..8dada3edaf5 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/arm/CMSIS_5/LICENSE.txt @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. Definitions. + + "License" shall mean the terms and conditions for use, reproduction, + and distribution as defined by Sections 1 through 9 of this document. + + "Licensor" shall mean the copyright owner or entity authorized by + the copyright owner that is granting the License. + + "Legal Entity" shall mean the union of the acting entity and all + other entities that control, are controlled by, or are under common + control with that entity. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board.h b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board.h new file mode 100644 index 00000000000..0cf82a0faf3 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board.h @@ -0,0 +1,67 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * File Name : board.h + * Description : Includes and API function available for this board. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARDS + * @defgroup BOARD_RZN2L_RSK + * @brief BSP for the RZN2L_RSK Board + * + * The RZN2L_RSK is a development kit for the Renesas RZN2L microcontroller. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_H +#define BOARD_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Board Specific Includes. */ +#include "board_init.h" +#include "board_leds.h" +#include "board_ethernet_phy.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BOARD_RZN2L_RSK + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_CONFIG_RZN2L) */ + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_ethernet_phy.h b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_ethernet_phy.h new file mode 100644 index 00000000000..fb4f299cc81 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_ethernet_phy.h @@ -0,0 +1,60 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RZN2_RSK + * @defgroup BOARD_RZN2_RSK_ETHERNET_PHY Board Ethernet Phy + * @brief Ethernet Phy information for this board. + * + * This is code specific to the RZN2_RSK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_ETHERNET_PHY_H +#define BSP_ETHERNET_PHY_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define ETHER_PHY_CFG_TARGET_VSC8541_ENABLE (1) +#define ETHER_PHY_LSI_TYPE_KIT_COMPONENT ETHER_PHY_LSI_TYPE_VSC8541 + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RZN2_RSK_ETHERNET_PHY) */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_init.c b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_init.c new file mode 100644 index 00000000000..f3a4c789b93 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_init.c @@ -0,0 +1,67 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * File Name : board_init.c + * Description : This module calls any initialization code specific to this BSP. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RZN2L_RSK_INIT + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if defined(BOARD_RZN2L_RSK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Performs any initialization specific to this BSP. + * + * @param[in] p_args Pointer to arguments of the user's choice. + **********************************************************************************************************************/ +void bsp_init (void * p_args) +{ + FSP_PARAMETER_NOT_USED(p_args); +} + +#endif + +/** @} (end addtogroup BOARD_RZN2L_RSK_INIT) */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_init.h b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_init.h new file mode 100644 index 00000000000..7c57fe415ca --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_init.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * File Name : board_init.h + * Description : This module calls any initialization code specific to this BSP. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RZN2L_RSK + * @defgroup BOARD_RZN2L_RSK_INIT + * @brief Board specific code for the RZN2L_RSK Board + * + * This include file is specific to the RZN2L_RSK board. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_INIT_H +#define BOARD_INIT_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +void bsp_init(void * p_args); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RZN2L_RSK_INIT) */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_leds.c b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_leds.c new file mode 100644 index 00000000000..32ac2a0da32 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_leds.c @@ -0,0 +1,77 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * File Name : board_leds.c + * Description : This module has information about the LEDs on this board. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BOARD_RZN2L_RSK_LEDS + * + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#if defined(BOARD_RZN2L_RSK) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Array of LED IOPORT pins. */ +static const uint32_t g_bsp_prv_leds[][2] = +{ + {(uint32_t) BSP_IO_PORT_18_PIN_2, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED0 + {(uint32_t) BSP_IO_PORT_22_PIN_3, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED1 + {(uint32_t) BSP_IO_PORT_04_PIN_1, (uint32_t) BSP_IO_REGION_SAFE}, ///< RLED2 + {(uint32_t) BSP_IO_PORT_17_PIN_3, (uint32_t) BSP_IO_REGION_SAFE} ///< RLED3 +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Structure with LED information for this board. */ + +const bsp_leds_t g_bsp_leds = +{ + .led_count = (uint16_t) (sizeof(g_bsp_prv_leds) / sizeof(g_bsp_prv_leds[0])), + .p_leds = g_bsp_prv_leds +}; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +#endif + +/** @} (end addtogroup BOARD_RZN2L_RSK_LEDS) */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_leds.h b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_leds.h new file mode 100644 index 00000000000..fdae49f91d8 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/board/rzn2l_rsk/board_leds.h @@ -0,0 +1,81 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * File Name : board_leds.h + * Description : This module has information about the LEDs on this board. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BOARD_RZN2L_RSK + * @defgroup BOARD_RZN2L_RSK_LEDS Board LEDs + * @brief LED information for this board. + * + * This is code specific to the RZN2L_RSK board. It includes info on the number of LEDs and which pins are they + * are on. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BOARD_LEDS_H +#define BOARD_LEDS_H + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Information on how many LEDs and what pins they are on. */ +typedef struct st_bsp_leds +{ + uint16_t led_count; ///< The number of LEDs on this board + uint32_t const (*p_leds)[2]; ///< Pointer to an array of IOPORT pins for controlling LEDs +} bsp_leds_t; + +/** Available user-controllable LEDs on this board. These enums can be can be used to index into the array of LED pins + * found in the bsp_leds_t structure. */ +typedef enum e_bsp_led +{ + BSP_LED_RLED0 = 0, ///< Green + BSP_LED_RLED1 = 1, ///< Yellow + BSP_LED_RLED2 = 2, ///< Red + BSP_LED_RLED3 = 3, ///< Red +} bsp_led_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Public Functions + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/** @} (end defgroup BOARD_RZN2L_RSK_LEDS) */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/bsp_api.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/bsp_api.h new file mode 100644 index 00000000000..b2c951b125b --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/bsp_api.h @@ -0,0 +1,111 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_API_H +#define BSP_API_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* FSP Common Includes. */ +#include "fsp_common_api.h" + +/* Gets MCU configuration information. */ +#include "bsp_cfg.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Store warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic push + +/* CMSIS-CORE currently generates 2 warnings when compiling with GCC. One in core_cmInstr.h and one in core_cm4_simd.h. + * We are not modifying these files so we will ignore these warnings temporarily. */ + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wsign-conversion" +#endif + +/* Vector information for this project. This is generated by the tooling. */ +#include "../../src/bsp/mcu/all/bsp_exceptions.h" +#include "vector_data.h" + +/* CMSIS-CORE Renesas Device Files. Must come after bsp_feature.h, which is included in bsp_cfg.h. */ +#include "../../src/bsp/cmsis/Device/RENESAS/Include/renesas.h" +#include "../../src/bsp/cmsis/Device/RENESAS/Include/system.h" + +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + +/* Restore warning settings for 'conversion' and 'sign-conversion' to as specified on command line. */ + #pragma GCC diagnostic pop +#endif + +#if defined(BSP_API_OVERRIDE) + #include BSP_API_OVERRIDE +#else + +/* BSP Common Includes. */ + #include "../../src/bsp/mcu/all/bsp_common.h" + +/* BSP MCU Specific Includes. */ + #include "../../src/bsp/mcu/all/bsp_register_protection.h" + #include "../../src/bsp/mcu/all/bsp_irq.h" + #include "../../src/bsp/mcu/all/bsp_io.h" + #include "../../src/bsp/mcu/all/bsp_group_irq.h" + #include "../../src/bsp/mcu/all/bsp_clocks.h" + #include "../../src/bsp/mcu/all/bsp_module_stop.h" + #include "../../src/bsp/mcu/all/bsp_security.h" + +/* Factory MCU information. */ + #include "../../inc/fsp_features.h" + +/* BSP Common Includes (Other than bsp_common.h) */ + #include "../../src/bsp/mcu/all/bsp_delay.h" + #include "../../src/bsp/mcu/all/bsp_mcu_api.h" + +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +fsp_err_t R_FSP_VersionGet(fsp_pack_version_t * const p_version); + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/r_ioport_api.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/r_ioport_api.h new file mode 100644 index 00000000000..d6b3049b844 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/r_ioport_api.h @@ -0,0 +1,206 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_SYSTEM_INTERFACES + * @defgroup IOPORT_API I/O Port Interface + * @brief Interface for accessing I/O ports and configuring I/O functionality. + * + * @section IOPORT_API_SUMMARY Summary + * The IOPort shared interface provides the ability to access the IOPorts of a device at both bit and port level. + * Port and pin direction can be changed. + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_API_H +#define R_IOPORT_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#ifndef BSP_OVERRIDE_IOPORT_SIZE_T + +/** IO port type used with ports */ +typedef uint16_t ioport_size_t; ///< IO port size +#endif + +/** Pin identifier and pin configuration value */ +typedef struct st_ioport_pin_cfg +{ + uint32_t pin_cfg; ///< Pin configuration - Use ioport_cfg_options_t parameters to configure + bsp_io_port_pin_t pin; ///< Pin identifier +} ioport_pin_cfg_t; + +/** Multiple pin configuration data for loading into registers by R_IOPORT_Open() */ +typedef struct st_ioport_cfg +{ + uint16_t number_of_pins; ///< Number of pins for which there is configuration data + ioport_pin_cfg_t const * p_pin_cfg_data; ///< Pin configuration data + const void * p_extend; ///< Pointer to hardware extend configuration +} ioport_cfg_t; + +/** IOPORT control block. Allocate an instance specific control block to pass into the IOPORT API calls. + */ +typedef void ioport_ctrl_t; + +/** IOPort driver structure. IOPort functions implemented at the HAL layer will follow this API. */ +typedef struct st_ioport_api +{ + /** Initialize internal driver data and initial pin configurations. Called during startup. Do + * not call this API during runtime. Use @ref ioport_api_t::pinsCfg for runtime reconfiguration of + * multiple pins. + * + * @param[in] p_ctrl Pointer to control structure. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* open)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Close the API. + * + * @param[in] p_ctrl Pointer to control structure. + **/ + fsp_err_t (* close)(ioport_ctrl_t * const p_ctrl); + + /** Configure multiple pins. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] p_cfg Pointer to pin configuration data array. + */ + fsp_err_t (* pinsCfg)(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); + + /** Configure settings for an individual pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] cfg Configuration options for the pin. + */ + fsp_err_t (* pinCfg)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); + + /** Read the event input data of the specified pin and return the level. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] p_pin_event Pointer to return the event data. + */ + fsp_err_t (* pinEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); + + /** Write pin event data. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin event data is to be written to. + * @param[in] pin_value Level to be written to pin output event. + */ + fsp_err_t (* pinEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); + + /** Read level of a pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be read. + * @param[in] p_pin_value Pointer to return the pin level. + */ + fsp_err_t (* pinRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); + + /** Write specified level to a pin. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] pin Pin to be written to. + * @param[in] level State to be written to the pin. + */ + fsp_err_t (* pinWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); + + /** Set the direction of one or more pins on a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port being configured. + * @param[in] direction_values Value controlling direction of pins on port. + * @param[in] mask Mask controlling which pins on the port are to be configured. + */ + fsp_err_t (* portDirectionSet)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, + ioport_size_t mask); + + /** Read captured event data for a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be read. + * @param[in] p_event_data Pointer to return the event data. + */ + fsp_err_t (* portEventInputRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); + + /** Write event output data for a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port event data will be written to. + * @param[in] event_data Data to be written as event data to specified port. + * @param[in] mask_value Each bit set to 1 in the mask corresponds to that bit's value in event data. + * being written to port. + */ + fsp_err_t (* portEventOutputWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, + ioport_size_t mask_value); + + /** Read states of pins on the specified port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be read. + * @param[in] p_port_value Pointer to return the port value. + */ + fsp_err_t (* portRead)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); + + /** Write to multiple pins on a port. + * + * @param[in] p_ctrl Pointer to control structure. + * @param[in] port Port to be written to. + * @param[in] value Value to be written to the port. + * @param[in] mask Mask controlling which pins on the port are written to. + */ + fsp_err_t (* portWrite)(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); +} ioport_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_ioport_instance +{ + ioport_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + ioport_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + ioport_api_t const * p_api; ///< Pointer to the API structure for this instance +} ioport_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT_API) + **********************************************************************************************************************/ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/r_transfer_api.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/r_transfer_api.h new file mode 100644 index 00000000000..530c88dc9de --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/r_transfer_api.h @@ -0,0 +1,402 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_TRANSFER_INTERFACES + * @defgroup TRANSFER_API Transfer Interface + * + * @brief Interface for data transfer functions. + * + * @section TRANSFER_API_SUMMARY Summary + * The transfer interface supports background data transfer (no CPU intervention). + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_TRANSFER_API_H +#define R_TRANSFER_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Common error codes and definitions. */ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define TRANSFER_SETTINGS_MODE_BITS (30U) +#define TRANSFER_SETTINGS_SIZE_BITS (28U) +#define TRANSFER_SETTINGS_SRC_ADDR_BITS (26U) +#define TRANSFER_SETTINGS_CHAIN_MODE_BITS (22U) +#define TRANSFER_SETTINGS_IRQ_BITS (21U) +#define TRANSFER_SETTINGS_REPEAT_AREA_BITS (20U) +#define TRANSFER_SETTINGS_DEST_ADDR_BITS (18U) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Transfer control block. Allocate an instance specific control block to pass into the transfer API calls. + */ +typedef void transfer_ctrl_t; + +#ifndef BSP_OVERRIDE_TRANSFER_MODE_T + +/** Transfer mode describes what will happen when a transfer request occurs. */ +typedef enum e_transfer_mode +{ + /** In normal mode, each transfer request causes a transfer of @ref transfer_size_t from the source pointer to + * the destination pointer. The transfer length is decremented and the source and address pointers are + * updated according to @ref transfer_addr_mode_t. After the transfer length reaches 0, transfer requests + * will not cause any further transfers. */ + TRANSFER_MODE_NORMAL = 0, + + /** Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the + * repeat area and the transfer length will be reset to their initial values. If DMAC is used, the + * transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats + * transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is + * used, the transfer repeats continuously (no limit to the number of repeat transfers). */ + TRANSFER_MODE_REPEAT = 1, + + /** In block mode, each transfer request causes transfer_info_t::length transfers of @ref transfer_size_t. + * After each individual transfer, the source and destination pointers are updated according to + * @ref transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is + * decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any + * further transfers. */ + TRANSFER_MODE_BLOCK = 2, + + /** In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets + * within a block (to split blocks into arrays of their first data, second data, etc.) */ + TRANSFER_MODE_REPEAT_BLOCK = 3 +} transfer_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_SIZE_T + +/** Transfer size specifies the size of each individual transfer. + * Total transfer length = transfer_size_t * transfer_length_t + */ +typedef enum e_transfer_size +{ + TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value + TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value + TRANSFER_SIZE_4_BYTE = 2 ///< Each transfer transfers a 32-bit value +} transfer_size_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_ADDR_MODE_T + +/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ +typedef enum e_transfer_addr_mode +{ + /** Address pointer remains fixed after each transfer. */ + TRANSFER_ADDR_MODE_FIXED = 0, + + /** Offset is added to the address pointer after each transfer. */ + TRANSFER_ADDR_MODE_OFFSET = 1, + + /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_INCREMENTED = 2, + + /** Address pointer is decremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_DECREMENTED = 3 +} transfer_addr_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_REPEAT_AREA_T + +/** Repeat area options (source or destination). In @ref TRANSFER_MODE_REPEAT, the selected pointer returns to its + * original value after transfer_info_t::length transfers. In @ref TRANSFER_MODE_BLOCK and @ref TRANSFER_MODE_REPEAT_BLOCK, + * the selected pointer returns to its original value after each transfer. */ +typedef enum e_transfer_repeat_area +{ + /** Destination area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_DESTINATION = 0, + + /** Source area repeated in @ref TRANSFER_MODE_REPEAT or @ref TRANSFER_MODE_BLOCK or @ref TRANSFER_MODE_REPEAT_BLOCK. */ + TRANSFER_REPEAT_AREA_SOURCE = 1 +} transfer_repeat_area_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CHAIN_MODE_T + +/** Chain transfer mode options. + * @note Only applies for DTC. */ +typedef enum e_transfer_chain_mode +{ + /** Chain mode not used. */ + TRANSFER_CHAIN_MODE_DISABLED = 0, + + /** Switch to next transfer after a single transfer from this @ref transfer_info_t. */ + TRANSFER_CHAIN_MODE_EACH = 2, + + /** Complete the entire transfer defined in this @ref transfer_info_t before chaining to next transfer. */ + TRANSFER_CHAIN_MODE_END = 3 +} transfer_chain_mode_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_IRQ_T + +/** Interrupt options. */ +typedef enum e_transfer_irq +{ + /** Interrupt occurs only after last transfer. If this transfer is chained to a subsequent transfer, + * the interrupt will occur only after subsequent chained transfer(s) are complete. + * @warning DTC triggers the interrupt of the activation source. Choosing TRANSFER_IRQ_END with DTC will + * prevent activation source interrupts until the transfer is complete. */ + TRANSFER_IRQ_END = 0, + + /** Interrupt occurs after each transfer. + * @note Not available in all HAL drivers. See HAL driver for details. */ + TRANSFER_IRQ_EACH = 1 +} transfer_irq_t; + +#endif + +#ifndef BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T + +/** Callback function parameter data. */ +typedef struct st_transfer_callback_args_t +{ + void const * p_context; ///< Placeholder for user data. Set in @ref transfer_api_t::open function in ::transfer_cfg_t. +} transfer_callback_args_t; + +#endif + +/** Driver specific information. */ +typedef struct st_transfer_properties +{ + uint32_t block_count_max; ///< Maximum number of blocks + uint32_t block_count_remaining; ///< Number of blocks remaining + uint32_t transfer_length_max; ///< Maximum number of transfers + uint32_t transfer_length_remaining; ///< Number of transfers remaining +} transfer_properties_t; + +#ifndef BSP_OVERRIDE_TRANSFER_INFO_T + +/** This structure specifies the properties of the transfer. + * @warning When using DTC, this structure corresponds to the descriptor block registers required by the DTC. + * The following components may be modified by the driver: p_src, p_dest, num_blocks, and length. + * @warning When using DTC, do NOT reuse this structure to configure multiple transfers. Each transfer must + * have a unique transfer_info_t. + * @warning When using DTC, this structure must not be allocated in a temporary location. Any instance of this + * structure must remain in scope until the transfer it is used for is closed. + * @note When using DTC, consider placing instances of this structure in a protected section of memory. */ +typedef struct st_transfer_info +{ + union + { + struct + { + uint32_t : 16; + uint32_t : 2; + + /** Select what happens to destination pointer after each transfer. */ + transfer_addr_mode_t dest_addr_mode : 2; + + /** Select to repeat source or destination area, unused in @ref TRANSFER_MODE_NORMAL. */ + transfer_repeat_area_t repeat_area : 1; + + /** Select if interrupts should occur after each individual transfer or after the completion of all planned + * transfers. */ + transfer_irq_t irq : 1; + + /** Select when the chain transfer ends. */ + transfer_chain_mode_t chain_mode : 2; + + uint32_t : 2; + + /** Select what happens to source pointer after each transfer. */ + transfer_addr_mode_t src_addr_mode : 2; + + /** Select number of bytes to transfer at once. @see transfer_info_t::length. */ + transfer_size_t size : 2; + + /** Select mode from @ref transfer_mode_t. */ + transfer_mode_t mode : 2; + } transfer_settings_word_b; + + uint32_t transfer_settings_word; + }; + + void const * volatile p_src; ///< Source pointer + void * volatile p_dest; ///< Destination pointer + + /** Number of blocks to transfer when using @ref TRANSFER_MODE_BLOCK (both DTC an DMAC) or + * @ref TRANSFER_MODE_REPEAT (DMAC only) or + * @ref TRANSFER_MODE_REPEAT_BLOCK (DMAC only), unused in other modes. */ + volatile uint16_t num_blocks; + + /** Length of each transfer. Range limited for @ref TRANSFER_MODE_BLOCK, @ref TRANSFER_MODE_REPEAT, + * and @ref TRANSFER_MODE_REPEAT_BLOCK + * see HAL driver for details. */ + volatile uint16_t length; +} transfer_info_t; + +#endif + +/** Driver configuration set in @ref transfer_api_t::open. All elements except p_extend are required and must be + * initialized. */ +typedef struct st_transfer_cfg +{ + /** Pointer to transfer configuration options. If using chain transfer (DTC only), this can be a pointer to + * an array of chained transfers that will be completed in order. */ + transfer_info_t * p_info; + + void const * p_extend; ///< Extension parameter for hardware specific settings. +} transfer_cfg_t; + +/** Select whether to start single or repeated transfer with software start. */ +typedef enum e_transfer_start_mode +{ + TRANSFER_START_MODE_SINGLE = 0, ///< Software start triggers single transfer. + TRANSFER_START_MODE_REPEAT = 1 ///< Software start transfer continues until transfer is complete. +} transfer_start_mode_t; + +/** Transfer functions implemented at the HAL layer will follow this API. */ +typedef struct st_transfer_api +{ + /** Initial configuration. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_cfg Pointer to configuration structure. All elements of this structure + * must be set by user. + */ + fsp_err_t (* open)(transfer_ctrl_t * const p_ctrl, transfer_cfg_t const * const p_cfg); + + /** Reconfigure the transfer. + * Enable the transfer if p_info is valid. + * + * @param[in,out] p_ctrl Pointer to control block. Must be declared by user. Elements set here. + * @param[in] p_info Pointer to a new transfer info structure. + */ + fsp_err_t (* reconfigure)(transfer_ctrl_t * const p_ctrl, transfer_info_t * p_info); + + /** Reset source address pointer, destination address pointer, and/or length, keeping all other settings the same. + * Enable the transfer if p_src, p_dest, and length are valid. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or number of blocks in block mode. In DMAC only, + * resets number of repeats (initially stored in transfer_info_t::num_blocks) in + * repeat mode. Not used in repeat mode for DTC. + */ + fsp_err_t (* reset)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint16_t const num_transfers); + + /** Enable transfer. Transfers occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as activation source). + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* enable)(transfer_ctrl_t * const p_ctrl); + + /** Disable transfer. Transfers do not occur after the activation source event (or when + * @ref transfer_api_t::softwareStart is called if no peripheral event is chosen as the DMAC activation source). + * @note If a transfer is in progress, it will be completed. Subsequent transfer requests do not cause a + * transfer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* disable)(transfer_ctrl_t * const p_ctrl); + + /** Start transfer in software. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * @note Not supported for DTC. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] mode Select mode from @ref transfer_start_mode_t. + */ + fsp_err_t (* softwareStart)(transfer_ctrl_t * const p_ctrl, transfer_start_mode_t mode); + + /** Stop transfer in software. The transfer will stop after completion of the current transfer. + * @note Not supported for DTC. + * @note Only applies for transfers started with TRANSFER_START_MODE_REPEAT. + * @warning Only works if no peripheral event is chosen as the DMAC activation source. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* softwareStop)(transfer_ctrl_t * const p_ctrl); + + /** Provides information about this transfer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[out] p_properties Driver specific information. + */ + fsp_err_t (* infoGet)(transfer_ctrl_t * const p_ctrl, transfer_properties_t * const p_properties); + + /** Releases hardware lock. This allows a transfer to be reconfigured using @ref transfer_api_t::open. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + */ + fsp_err_t (* close)(transfer_ctrl_t * const p_ctrl); + + /** To update next transfer information without interruption during transfer. + * Allow further transfer continuation. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_src Pointer to source. Set to NULL if source pointer should not change. + * @param[in] p_dest Pointer to destination. Set to NULL if destination pointer should not change. + * @param[in] num_transfers Transfer length in normal mode or block mode. + */ + fsp_err_t (* reload)(transfer_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, + uint32_t const num_transfers); + + /** Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Control block set in @ref transfer_api_t::open call for this transfer. + * @param[in] p_callback Callback function to register + * @param[in] p_context Pointer to send to callback function + * @param[in] p_callback_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(transfer_ctrl_t * const p_ctrl, void (* p_callback)(transfer_callback_args_t *), + void const * const p_context, transfer_callback_args_t * const p_callback_memory); +} transfer_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_transfer_instance +{ + transfer_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + transfer_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + transfer_api_t const * p_api; ///< Pointer to the API structure for this instance +} transfer_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup TRANSFER_API) + **********************************************************************************************************************/ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/r_uart_api.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/r_uart_api.h new file mode 100644 index 00000000000..23585bd3903 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/api/r_uart_api.h @@ -0,0 +1,268 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup RENESAS_CONNECTIVITY_INTERFACES + * @defgroup UART_API UART Interface + * @brief Interface for UART communications. + * + * @section UART_INTERFACE_SUMMARY Summary + * The UART interface provides common APIs for UART HAL drivers. The UART interface supports the following features: + * - Full-duplex UART communication + * - Interrupt driven transmit/receive processing + * - Callback function with returned event code + * - Runtime baud-rate change + * - Hardware resource locking during a transaction + * - CTS/RTS hardware flow control support (with an associated IOPORT pin) + * + * + * @{ + **********************************************************************************************************************/ + +#ifndef R_UART_API_H +#define R_UART_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** UART Event codes */ +#ifndef BSP_OVERRIDE_UART_EVENT_T +typedef enum e_sf_event +{ + UART_EVENT_RX_COMPLETE = (1UL << 0), ///< Receive complete event + UART_EVENT_TX_COMPLETE = (1UL << 1), ///< Transmit complete event + UART_EVENT_RX_CHAR = (1UL << 2), ///< Character received + UART_EVENT_ERR_PARITY = (1UL << 3), ///< Parity error event + UART_EVENT_ERR_FRAMING = (1UL << 4), ///< Mode fault error event + UART_EVENT_ERR_OVERFLOW = (1UL << 5), ///< FIFO Overflow error event + UART_EVENT_BREAK_DETECT = (1UL << 6), ///< Break detect error event + UART_EVENT_TX_DATA_EMPTY = (1UL << 7), ///< Last byte is transmitting, ready for more data +} uart_event_t; +#endif +#ifndef BSP_OVERRIDE_UART_DATA_BITS_T + +/** UART Data bit length definition */ +typedef enum e_uart_data_bits +{ + UART_DATA_BITS_9 = 0U, ///< Data bits 9-bit + UART_DATA_BITS_8 = 2U, ///< Data bits 8-bit + UART_DATA_BITS_7 = 3U, ///< Data bits 7-bit +} uart_data_bits_t; +#endif +#ifndef BSP_OVERRIDE_UART_PARITY_T + +/** UART Parity definition */ +typedef enum e_uart_parity +{ + UART_PARITY_OFF = 0U, ///< No parity + UART_PARITY_ZERO = 1U, ///< Zero parity + UART_PARITY_EVEN = 2U, ///< Even parity + UART_PARITY_ODD = 3U, ///< Odd parity +} uart_parity_t; +#endif + +/** UART Stop bits definition */ +typedef enum e_uart_stop_bits +{ + UART_STOP_BITS_1 = 0U, ///< Stop bit 1-bit + UART_STOP_BITS_2 = 1U, ///< Stop bits 2-bit +} uart_stop_bits_t; + +/** UART transaction definition */ +typedef enum e_uart_dir +{ + UART_DIR_RX_TX = 3U, ///< Both RX and TX + UART_DIR_RX = 1U, ///< Only RX + UART_DIR_TX = 2U, ///< Only TX +} uart_dir_t; + +/** UART driver specific information */ +typedef struct st_uart_info +{ + /** Maximum bytes that can be written at this time. Only applies if uart_cfg_t::p_transfer_tx is not NULL. */ + uint32_t write_bytes_max; + + /** Maximum bytes that are available to read at one time. Only applies if uart_cfg_t::p_transfer_rx is not NULL. */ + uint32_t read_bytes_max; +} uart_info_t; + +/** UART Callback parameter definition */ +typedef struct st_uart_callback_arg +{ + uint32_t channel; ///< Device channel number + uart_event_t event; ///< Event code + + /** Contains the next character received for the events UART_EVENT_RX_CHAR, UART_EVENT_ERR_PARITY, + * UART_EVENT_ERR_FRAMING, or UART_EVENT_ERR_OVERFLOW. Otherwise unused. */ + uint32_t data; + void const * p_context; ///< Context provided to user during callback +} uart_callback_args_t; + +/** UART Configuration */ +typedef struct st_uart_cfg +{ + /* UART generic configuration */ + uint8_t channel; ///< Select a channel corresponding to the channel number of the hardware. + uart_data_bits_t data_bits; ///< Data bit length (8 or 7 or 9) + uart_parity_t parity; ///< Parity type (none or odd or even) + uart_stop_bits_t stop_bits; ///< Stop bit length (1 or 2) + uint8_t rxi_ipl; ///< Receive interrupt priority + IRQn_Type rxi_irq; ///< Receive interrupt IRQ number + uint8_t txi_ipl; ///< Transmit interrupt priority + IRQn_Type txi_irq; ///< Transmit interrupt IRQ number + uint8_t tei_ipl; ///< Transmit end interrupt priority + IRQn_Type tei_irq; ///< Transmit end interrupt IRQ number + uint8_t eri_ipl; ///< Error interrupt priority + IRQn_Type eri_irq; ///< Error interrupt IRQ number + + /** Optional transfer instance used to receive multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the read API is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_rx; + + /** Optional transfer instance used to send multiple bytes without interrupts. Set to NULL if unused. + * If NULL, the number of bytes allowed in the write APIs is limited to one byte at a time. */ + transfer_instance_t const * p_transfer_tx; + + /* Configuration for UART Event processing */ + void (* p_callback)(uart_callback_args_t * p_args); ///< Pointer to callback function + void const * p_context; ///< User defined context passed into callback function + + /* Pointer to UART peripheral specific configuration */ + void const * p_extend; ///< UART hardware dependent configuration +} uart_cfg_t; + +/** UART control block. Allocate an instance specific control block to pass into the UART API calls. + */ +typedef void uart_ctrl_t; + +/** Shared Interface definition for UART */ +typedef struct st_uart_api +{ + /** Open UART device. + * + * @param[in,out] p_ctrl Pointer to the UART control block. Must be declared by user. Value set here. + * @param[in] uart_cfg_t Pointer to UART configuration structure. All elements of this structure must be set by + * user. + */ + fsp_err_t (* open)(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); + + /** Read from UART device. The read buffer is used until the read is complete. When a transfer is complete, the + * callback is called with event UART_EVENT_RX_COMPLETE. Bytes received outside an active transfer are received in + * the callback function with event UART_EVENT_RX_CHAR. + * The maximum transfer size is reported by infoGet(). + * + * @param[in] p_ctrl Pointer to the UART control block for the channel. + * @param[in] p_dest Destination address to read data from. + * @param[in] bytes Read data length. + */ + fsp_err_t (* read)(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); + + /** Write to UART device. The write buffer is used until write is complete. Do not overwrite write buffer + * contents until the write is finished. When the write is complete (all bytes are fully transmitted on the wire), + * the callback called with event UART_EVENT_TX_COMPLETE. + * The maximum transfer size is reported by infoGet(). + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_src Source address to write data to. + * @param[in] bytes Write data length. + */ + fsp_err_t (* write)(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); + + /** Change baud rate. + * @warning Calling this API aborts any in-progress transmission and disables reception until the new baud + * settings have been applied. + * + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_baudrate_info Pointer to module specific information for configuring baud rate. + */ + fsp_err_t (* baudSet)(uart_ctrl_t * const p_ctrl, void const * const p_baudrate_info); + + /** Get the driver specific information. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] baudrate Baud rate in bps. + */ + fsp_err_t (* infoGet)(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); + + /** + * Abort ongoing transfer. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] communication_to_abort Type of abort request. + */ + fsp_err_t (* communicationAbort)(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(uart_ctrl_t * const p_ctrl, void (* p_callback)(uart_callback_args_t *), + void const * const p_context, uart_callback_args_t * const p_callback_memory); + + /** Close UART device. + * + * @param[in] p_ctrl Pointer to the UART control block. + */ + fsp_err_t (* close)(uart_ctrl_t * const p_ctrl); + + /** Stop ongoing read and return the number of bytes remaining in the read. + * + * @param[in] p_ctrl Pointer to the UART control block. + * @param[in,out] remaining_bytes Pointer to location to store remaining bytes for read. + */ + fsp_err_t (* readStop)(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); +} uart_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_uart_instance +{ + uart_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + uart_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + uart_api_t const * p_api; ///< Pointer to the API structure for this instance +} uart_instance_t; + +/** @} (end defgroup UART_API) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/fsp_common_api.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/fsp_common_api.h new file mode 100644 index 00000000000..6bc678d533a --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/fsp_common_api.h @@ -0,0 +1,394 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_COMMON_API_H +#define FSP_COMMON_API_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +/* Includes FSP version macros. */ +#include "fsp_version.h" + +/*******************************************************************************************************************//** + * @ingroup RENESAS_COMMON + * @defgroup RENESAS_ERROR_CODES Common Error Codes + * All FSP modules share these common error codes. + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** This macro is used to suppress compiler messages about a parameter not being used in a function. The nice thing + * about using this implementation is that it does not take any extra RAM or ROM. */ + +#define FSP_PARAMETER_NOT_USED(p) (void) ((p)) + +/** Determine if a C++ compiler is being used. + * If so, ensure that standard C is used to process the API information. */ +#if defined(__cplusplus) + #define FSP_CPP_HEADER extern "C" { + #define FSP_CPP_FOOTER } +#else + #define FSP_CPP_HEADER + #define FSP_CPP_FOOTER +#endif + +/** FSP Header and Footer definitions */ +#define FSP_HEADER FSP_CPP_HEADER +#define FSP_FOOTER FSP_CPP_FOOTER + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/** Macro to be used when argument to function is ignored since function call is NSC and the parameter is statically + * defined on the Secure side. */ +#define FSP_SECURE_ARGUMENT (NULL) + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Common error codes */ +typedef enum e_fsp_err +{ + FSP_SUCCESS = 0, + + FSP_ERR_ASSERTION = 1, ///< A critical assertion has failed + FSP_ERR_INVALID_POINTER = 2, ///< Pointer points to invalid memory location + FSP_ERR_INVALID_ARGUMENT = 3, ///< Invalid input parameter + FSP_ERR_INVALID_CHANNEL = 4, ///< Selected channel does not exist + FSP_ERR_INVALID_MODE = 5, ///< Unsupported or incorrect mode + FSP_ERR_UNSUPPORTED = 6, ///< Selected mode not supported by this API + FSP_ERR_NOT_OPEN = 7, ///< Requested channel is not configured or API not open + FSP_ERR_IN_USE = 8, ///< Channel/peripheral is running/busy + FSP_ERR_OUT_OF_MEMORY = 9, ///< Allocate more memory in the driver's cfg.h + FSP_ERR_HW_LOCKED = 10, ///< Hardware is locked + FSP_ERR_IRQ_BSP_DISABLED = 11, ///< IRQ not enabled in BSP + FSP_ERR_OVERFLOW = 12, ///< Hardware overflow + FSP_ERR_UNDERFLOW = 13, ///< Hardware underflow + FSP_ERR_ALREADY_OPEN = 14, ///< Requested channel is already open in a different configuration + FSP_ERR_APPROXIMATION = 15, ///< Could not set value to exact result + FSP_ERR_CLAMPED = 16, ///< Value had to be limited for some reason + FSP_ERR_INVALID_RATE = 17, ///< Selected rate could not be met + FSP_ERR_ABORTED = 18, ///< An operation was aborted + FSP_ERR_NOT_ENABLED = 19, ///< Requested operation is not enabled + FSP_ERR_TIMEOUT = 20, ///< Timeout error + FSP_ERR_INVALID_BLOCKS = 21, ///< Invalid number of blocks supplied + FSP_ERR_INVALID_ADDRESS = 22, ///< Invalid address supplied + FSP_ERR_INVALID_SIZE = 23, ///< Invalid size/length supplied for operation + FSP_ERR_WRITE_FAILED = 24, ///< Write operation failed + FSP_ERR_ERASE_FAILED = 25, ///< Erase operation failed + FSP_ERR_INVALID_CALL = 26, ///< Invalid function call is made + FSP_ERR_INVALID_HW_CONDITION = 27, ///< Detected hardware is in invalid condition + FSP_ERR_INVALID_FACTORY_FLASH = 28, ///< Factory flash is not available on this MCU + FSP_ERR_INVALID_STATE = 30, ///< API or command not valid in the current state + FSP_ERR_NOT_ERASED = 31, ///< Erase verification failed + FSP_ERR_SECTOR_RELEASE_FAILED = 32, ///< Sector release failed + FSP_ERR_NOT_INITIALIZED = 33, ///< Required initialization not complete + FSP_ERR_NOT_FOUND = 34, ///< The requested item could not be found + FSP_ERR_NO_CALLBACK_MEMORY = 35, ///< Non-secure callback memory not provided for non-secure callback + FSP_ERR_BUFFER_EMPTY = 36, ///< No data available in buffer + FSP_ERR_INVALID_DATA = 37, ///< Accuracy of data is not guaranteed + + /* Start of RTOS only error codes */ + FSP_ERR_INTERNAL = 100, ///< Internal error + FSP_ERR_WAIT_ABORTED = 101, ///< Wait aborted + + /* Start of UART specific */ + FSP_ERR_FRAMING = 200, ///< Framing error occurs + FSP_ERR_BREAK_DETECT = 201, ///< Break signal detects + FSP_ERR_PARITY = 202, ///< Parity error occurs + FSP_ERR_RXBUF_OVERFLOW = 203, ///< Receive queue overflow + FSP_ERR_QUEUE_UNAVAILABLE = 204, ///< Can't open s/w queue + FSP_ERR_INSUFFICIENT_SPACE = 205, ///< Not enough space in transmission circular buffer + FSP_ERR_INSUFFICIENT_DATA = 206, ///< Not enough data in receive circular buffer + + /* Start of SPI specific */ + FSP_ERR_TRANSFER_ABORTED = 300, ///< The data transfer was aborted. + FSP_ERR_MODE_FAULT = 301, ///< Mode fault error. + FSP_ERR_READ_OVERFLOW = 302, ///< Read overflow. + FSP_ERR_SPI_PARITY = 303, ///< Parity error. + FSP_ERR_OVERRUN = 304, ///< Overrun error. + + /* Start of CGC Specific */ + FSP_ERR_CLOCK_INACTIVE = 400, ///< Inactive clock specified as system clock. + FSP_ERR_CLOCK_ACTIVE = 401, ///< Active clock source cannot be modified without stopping first. + FSP_ERR_NOT_STABILIZED = 403, ///< Clock has not stabilized after its been turned on/off + FSP_ERR_PLL_SRC_INACTIVE = 404, ///< PLL initialization attempted when PLL source is turned off + FSP_ERR_OSC_STOP_DET_ENABLED = 405, ///< Illegal attempt to stop LOCO when Oscillation stop is enabled + FSP_ERR_OSC_STOP_DETECTED = 406, ///< The Oscillation stop detection status flag is set + FSP_ERR_OSC_STOP_CLOCK_ACTIVE = 407, ///< Attempt to clear Oscillation Stop Detect Status with PLL/MAIN_OSC active + FSP_ERR_CLKOUT_EXCEEDED = 408, ///< Output on target output clock pin exceeds maximum supported limit + FSP_ERR_USB_MODULE_ENABLED = 409, ///< USB clock configure request with USB Module enabled + FSP_ERR_HARDWARE_TIMEOUT = 410, ///< A register read or write timed out + FSP_ERR_LOW_VOLTAGE_MODE = 411, ///< Invalid clock setting attempted in low voltage mode + + /* Start of FLASH Specific */ + FSP_ERR_PE_FAILURE = 500, ///< Unable to enter Programming mode. + FSP_ERR_CMD_LOCKED = 501, ///< Peripheral in command locked state + FSP_ERR_FCLK = 502, ///< FCLK must be >= 4 MHz + FSP_ERR_INVALID_LINKED_ADDRESS = 503, ///< Function or data are linked at an invalid region of memory + FSP_ERR_BLANK_CHECK_FAILED = 504, ///< Blank check operation failed + + /* Start of CAC Specific */ + FSP_ERR_INVALID_CAC_REF_CLOCK = 600, ///< Measured clock rate < reference clock rate + + /* Start of IIRFA Specific */ + FSP_ERR_INVALID_RESULT = 700, ///< The result of one or more calculations was +/- infinity. + + /* Start of GLCD Specific */ + FSP_ERR_CLOCK_GENERATION = 1000, ///< Clock cannot be specified as system clock + FSP_ERR_INVALID_TIMING_SETTING = 1001, ///< Invalid timing parameter + FSP_ERR_INVALID_LAYER_SETTING = 1002, ///< Invalid layer parameter + FSP_ERR_INVALID_ALIGNMENT = 1003, ///< Invalid memory alignment found + FSP_ERR_INVALID_GAMMA_SETTING = 1004, ///< Invalid gamma correction parameter + FSP_ERR_INVALID_LAYER_FORMAT = 1005, ///< Invalid color format in layer + FSP_ERR_INVALID_UPDATE_TIMING = 1006, ///< Invalid timing for register update + FSP_ERR_INVALID_CLUT_ACCESS = 1007, ///< Invalid access to CLUT entry + FSP_ERR_INVALID_FADE_SETTING = 1008, ///< Invalid fade-in/fade-out setting + FSP_ERR_INVALID_BRIGHTNESS_SETTING = 1009, ///< Invalid gamma correction parameter + + /* Start of JPEG Specific */ + FSP_ERR_JPEG_ERR = 1100, ///< JPEG error + FSP_ERR_JPEG_SOI_NOT_DETECTED = 1101, ///< SOI not detected until EOI detected. + FSP_ERR_JPEG_SOF1_TO_SOFF_DETECTED = 1102, ///< SOF1 to SOFF detected. + FSP_ERR_JPEG_UNSUPPORTED_PIXEL_FORMAT = 1103, ///< Unprovided pixel format detected. + FSP_ERR_JPEG_SOF_ACCURACY_ERROR = 1104, ///< SOF accuracy error: other than 8 detected. + FSP_ERR_JPEG_DQT_ACCURACY_ERROR = 1105, ///< DQT accuracy error: other than 0 detected. + FSP_ERR_JPEG_COMPONENT_ERROR1 = 1106, ///< Component error 1: the number of SOF0 header components detected is other than 1, 3, or 4. + FSP_ERR_JPEG_COMPONENT_ERROR2 = 1107, ///< Component error 2: the number of components differs between SOF0 header and SOS. + FSP_ERR_JPEG_SOF0_DQT_DHT_NOT_DETECTED = 1108, ///< SOF0, DQT, and DHT not detected when SOS detected. + FSP_ERR_JPEG_SOS_NOT_DETECTED = 1109, ///< SOS not detected: SOS not detected until EOI detected. + FSP_ERR_JPEG_EOI_NOT_DETECTED = 1110, ///< EOI not detected (default) + FSP_ERR_JPEG_RESTART_INTERVAL_DATA_NUMBER_ERROR = 1111, ///< Restart interval data number error detected. + FSP_ERR_JPEG_IMAGE_SIZE_ERROR = 1112, ///< Image size error detected. + FSP_ERR_JPEG_LAST_MCU_DATA_NUMBER_ERROR = 1113, ///< Last MCU data number error detected. + FSP_ERR_JPEG_BLOCK_DATA_NUMBER_ERROR = 1114, ///< Block data number error detected. + FSP_ERR_JPEG_BUFFERSIZE_NOT_ENOUGH = 1115, ///< User provided buffer size not enough + FSP_ERR_JPEG_UNSUPPORTED_IMAGE_SIZE = 1116, ///< JPEG Image size is not aligned with MCU + + /* Start of touch panel framework specific */ + FSP_ERR_CALIBRATE_FAILED = 1200, ///< Calibration failed + + /* Start of IIRFA specific */ + FSP_ERR_IIRFA_ECC_1BIT = 1300, ///< 1-bit ECC error detected + FSP_ERR_IIRFA_ECC_2BIT = 1301, ///< 2-bit ECC error detected + + /* Start of IP specific */ + FSP_ERR_IP_HARDWARE_NOT_PRESENT = 1400, ///< Requested IP does not exist on this device + FSP_ERR_IP_UNIT_NOT_PRESENT = 1401, ///< Requested unit does not exist on this device + FSP_ERR_IP_CHANNEL_NOT_PRESENT = 1402, ///< Requested channel does not exist on this device + + /* Start of USB specific */ + FSP_ERR_USB_FAILED = 1500, + FSP_ERR_USB_BUSY = 1501, + FSP_ERR_USB_SIZE_SHORT = 1502, + FSP_ERR_USB_SIZE_OVER = 1503, + FSP_ERR_USB_NOT_OPEN = 1504, + FSP_ERR_USB_NOT_SUSPEND = 1505, + FSP_ERR_USB_PARAMETER = 1506, + + /* Start of Message framework specific */ + FSP_ERR_NO_MORE_BUFFER = 2000, ///< No more buffer found in the memory block pool + FSP_ERR_ILLEGAL_BUFFER_ADDRESS = 2001, ///< Buffer address is out of block memory pool + FSP_ERR_INVALID_WORKBUFFER_SIZE = 2002, ///< Work buffer size is invalid + FSP_ERR_INVALID_MSG_BUFFER_SIZE = 2003, ///< Message buffer size is invalid + FSP_ERR_TOO_MANY_BUFFERS = 2004, ///< Number of buffer is too many + FSP_ERR_NO_SUBSCRIBER_FOUND = 2005, ///< No message subscriber found + FSP_ERR_MESSAGE_QUEUE_EMPTY = 2006, ///< No message found in the message queue + FSP_ERR_MESSAGE_QUEUE_FULL = 2007, ///< No room for new message in the message queue + FSP_ERR_ILLEGAL_SUBSCRIBER_LISTS = 2008, ///< Message subscriber lists is illegal + FSP_ERR_BUFFER_RELEASED = 2009, ///< Buffer has been released + + /* Start of 2DG Driver specific */ + FSP_ERR_D2D_ERROR_INIT = 3000, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_DEINIT = 3001, ///< D/AVE 2D has an error in the initialization + FSP_ERR_D2D_ERROR_RENDERING = 3002, ///< D/AVE 2D has an error in the rendering + FSP_ERR_D2D_ERROR_SIZE = 3003, ///< D/AVE 2D has an error in the rendering + + /* Start of ETHER Driver specific */ + FSP_ERR_ETHER_ERROR_NO_DATA = 4000, ///< No Data in Receive buffer. + FSP_ERR_ETHER_ERROR_LINK = 4001, ///< ETHERC/EDMAC has an error in the Auto-negotiation + FSP_ERR_ETHER_ERROR_MAGIC_PACKET_MODE = 4002, ///< As a Magic Packet is being detected, and transmission/reception is not enabled + FSP_ERR_ETHER_ERROR_TRANSMIT_BUFFER_FULL = 4003, ///< Transmit buffer is not empty + FSP_ERR_ETHER_ERROR_FILTERING = 4004, ///< Detect multicast frame when multicast frame filtering enable + FSP_ERR_ETHER_ERROR_PHY_COMMUNICATION = 4005, ///< ETHERC/EDMAC has an error in the phy communication + FSP_ERR_ETHER_RECEIVE_BUFFER_ACTIVE = 4006, ///< Receive buffer is active. + + /* Start of ETHER_PHY Driver specific */ + FSP_ERR_ETHER_PHY_ERROR_LINK = 5000, ///< PHY is not link up. + FSP_ERR_ETHER_PHY_NOT_READY = 5001, ///< PHY has an error in the Auto-negotiation + + /* Start of BYTEQ library specific */ + FSP_ERR_QUEUE_FULL = 10000, ///< Queue is full, cannot queue another data + FSP_ERR_QUEUE_EMPTY = 10001, ///< Queue is empty, no data to dequeue + + /* Start of CTSU Driver specific */ + FSP_ERR_CTSU_SCANNING = 6000, ///< Scanning. + FSP_ERR_CTSU_NOT_GET_DATA = 6001, ///< Not processed previous scan data. + FSP_ERR_CTSU_INCOMPLETE_TUNING = 6002, ///< Incomplete initial offset tuning. + FSP_ERR_CTSU_DIAG_NOT_YET = 6003, ///< Diagnosis of data collected no yet. + FSP_ERR_CTSU_DIAG_LDO_OVER_VOLTAGE = 6004, ///< Diagnosis of LDO over voltage failed. + FSP_ERR_CTSU_DIAG_CCO_HIGH = 6005, ///< Diagnosis of CCO into 19.2uA failed. + FSP_ERR_CTSU_DIAG_CCO_LOW = 6006, ///< Diagnosis of CCO into 2.4uA failed. + FSP_ERR_CTSU_DIAG_SSCG = 6007, ///< Diagnosis of SSCG frequency failed. + FSP_ERR_CTSU_DIAG_DAC = 6008, ///< Diagnosis of non-touch count value failed. + FSP_ERR_CTSU_DIAG_OUTPUT_VOLTAGE = 6009, ///< Diagnosis of LDO output voltage failed. + FSP_ERR_CTSU_DIAG_OVER_VOLTAGE = 6010, ///< Diagnosis of over voltage detection circuit failed. + FSP_ERR_CTSU_DIAG_OVER_CURRENT = 6011, ///< Diagnosis of over current detection circuit failed. + FSP_ERR_CTSU_DIAG_LOAD_RESISTANCE = 6012, ///< Diagnosis of LDO internal resistance value failed. + FSP_ERR_CTSU_DIAG_CURRENT_SOURCE = 6013, ///< Diagnosis of Current source value failed. + FSP_ERR_CTSU_DIAG_SENSCLK_GAIN = 6014, ///< Diagnosis of SENSCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_SUCLK_GAIN = 6015, ///< Diagnosis of SUCLK frequency gain failed. + FSP_ERR_CTSU_DIAG_CLOCK_RECOVERY = 6016, ///< Diagnosis of SUCLK clock recovery function failed. + FSP_ERR_CTSU_DIAG_CFC_GAIN = 6017, ///< Diagnosis of CFC oscillator gain failed. + + /* Start of SDMMC specific */ + FSP_ERR_CARD_INIT_FAILED = 40000, ///< SD card or eMMC device failed to initialize. + FSP_ERR_CARD_NOT_INSERTED = 40001, ///< SD card not installed. + FSP_ERR_DEVICE_BUSY = 40002, ///< Device is holding DAT0 low or another operation is ongoing. + FSP_ERR_CARD_NOT_INITIALIZED = 40004, ///< SD card was removed. + FSP_ERR_CARD_WRITE_PROTECTED = 40005, ///< Media is write protected. + FSP_ERR_TRANSFER_BUSY = 40006, ///< Transfer in progress. + FSP_ERR_RESPONSE = 40007, ///< Card did not respond or responded with an error. + + /* Start of FX_IO specific */ + FSP_ERR_MEDIA_FORMAT_FAILED = 50000, ///< Media format failed. + FSP_ERR_MEDIA_OPEN_FAILED = 50001, ///< Media open failed. + + /* Start of CAN specific */ + FSP_ERR_CAN_DATA_UNAVAILABLE = 60000, ///< No data available. + FSP_ERR_CAN_MODE_SWITCH_FAILED = 60001, ///< Switching operation modes failed. + FSP_ERR_CAN_INIT_FAILED = 60002, ///< Hardware initialization failed. + FSP_ERR_CAN_TRANSMIT_NOT_READY = 60003, ///< Transmit in progress. + FSP_ERR_CAN_RECEIVE_MAILBOX = 60004, ///< Mailbox is setup as a receive mailbox. + FSP_ERR_CAN_TRANSMIT_MAILBOX = 60005, ///< Mailbox is setup as a transmit mailbox. + FSP_ERR_CAN_MESSAGE_LOST = 60006, ///< Receive message has been overwritten or overrun. + FSP_ERR_CAN_TRANSMIT_FIFO_FULL = 60007, ///< Transmit FIFO is full. + + /* Start of SF_WIFI Specific */ + FSP_ERR_WIFI_CONFIG_FAILED = 70000, ///< WiFi module Configuration failed. + FSP_ERR_WIFI_INIT_FAILED = 70001, ///< WiFi module initialization failed. + FSP_ERR_WIFI_TRANSMIT_FAILED = 70002, ///< Transmission failed + FSP_ERR_WIFI_INVALID_MODE = 70003, ///< API called when provisioned in client mode + FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. + FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. + FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point + FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error + FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter + FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters + FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value + FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result + FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow + FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured + FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure + FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure + FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error + + /* Start of SF_CELLULAR Specific */ + FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. + FSP_ERR_CELLULAR_INIT_FAILED = 80001, ///< Cellular module initialization failed. + FSP_ERR_CELLULAR_TRANSMIT_FAILED = 80002, ///< Transmission failed + FSP_ERR_CELLULAR_FW_UPTODATE = 80003, ///< Firmware is uptodate + FSP_ERR_CELLULAR_FW_UPGRADE_FAILED = 80004, ///< Firmware upgrade failed + FSP_ERR_CELLULAR_FAILED = 80005, ///< Cellular Failed. + FSP_ERR_CELLULAR_INVALID_STATE = 80006, ///< API Called in invalid state. + FSP_ERR_CELLULAR_REGISTRATION_FAILED = 80007, ///< Cellular Network registration failed + + /* Start of SF_BLE specific */ + FSP_ERR_BLE_FAILED = 90001, ///< BLE operation failed + FSP_ERR_BLE_INIT_FAILED = 90002, ///< BLE device initialization failed + FSP_ERR_BLE_CONFIG_FAILED = 90003, ///< BLE device configuration failed + FSP_ERR_BLE_PRF_ALREADY_ENABLED = 90004, ///< BLE device Profile already enabled + FSP_ERR_BLE_PRF_NOT_ENABLED = 90005, ///< BLE device not enabled + + /* Start of SF_BLE_ABS specific */ + FSP_ERR_BLE_ABS_INVALID_OPERATION = 91001, ///< Invalid operation is executed. + FSP_ERR_BLE_ABS_NOT_FOUND = 91002, ///< Valid data or free space is not found. + + /* Start of Crypto specific (0x10000) @note Refer to sf_cryoto_err.h for Crypto error code. */ + FSP_ERR_CRYPTO_CONTINUE = 0x10000, ///< Continue executing function + FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT = 0x10001, ///< Hardware resource busy + FSP_ERR_CRYPTO_SCE_FAIL = 0x10002, ///< Internal I/O buffer is not empty + FSP_ERR_CRYPTO_SCE_HRK_INVALID_INDEX = 0x10003, ///< Invalid index + FSP_ERR_CRYPTO_SCE_RETRY = 0x10004, ///< Retry + FSP_ERR_CRYPTO_SCE_VERIFY_FAIL = 0x10005, ///< Verify is failed + FSP_ERR_CRYPTO_SCE_ALREADY_OPEN = 0x10006, ///< HW SCE module is already opened + FSP_ERR_CRYPTO_NOT_OPEN = 0x10007, ///< Hardware module is not initialized + FSP_ERR_CRYPTO_UNKNOWN = 0x10008, ///< Some unknown error occurred + FSP_ERR_CRYPTO_NULL_POINTER = 0x10009, ///< Null pointer input as a parameter + FSP_ERR_CRYPTO_NOT_IMPLEMENTED = 0x1000a, ///< Algorithm/size not implemented + FSP_ERR_CRYPTO_RNG_INVALID_PARAM = 0x1000b, ///< An invalid parameter is specified + FSP_ERR_CRYPTO_RNG_FATAL_ERROR = 0x1000c, ///< A fatal error occurred + FSP_ERR_CRYPTO_INVALID_SIZE = 0x1000d, ///< Size specified is invalid + FSP_ERR_CRYPTO_INVALID_STATE = 0x1000e, ///< Function used in an valid state + FSP_ERR_CRYPTO_ALREADY_OPEN = 0x1000f, ///< control block is already opened + FSP_ERR_CRYPTO_INSTALL_KEY_FAILED = 0x10010, ///< Specified input key is invalid. + FSP_ERR_CRYPTO_AUTHENTICATION_FAILED = 0x10011, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL = 0x10012, ///< Failure to Init Cipher + FSP_ERR_CRYPTO_SCE_AUTHENTICATION = 0x10013, ///< Authentication failed + FSP_ERR_CRYPTO_SCE_PARAMETER = 0x10014, ///< Input date is illegal. + FSP_ERR_CRYPTO_SCE_PROHIBIT_FUNCTION = 0x10015, ///< An invalid function call occurred. + + /* Start of Crypto RSIP specific (0x10100) */ + FSP_ERR_CRYPTO_RSIP_RESOURCE_CONFLICT = 0x10100, ///< Hardware resource is busy + FSP_ERR_CRYPTO_RSIP_FATAL = 0x10101, ///< Hardware fatal error or unexpected return + FSP_ERR_CRYPTO_RSIP_FAIL = 0x10102, ///< Internal error + FSP_ERR_CRYPTO_RSIP_KEY_SET_FAIL = 0x10103, ///< Input key type is illegal + FSP_ERR_CRYPTO_RSIP_AUTHENTICATION = 0x10104, ///< Authentication failed + + /* Start of SF_CRYPTO specific */ + FSP_ERR_CRYPTO_COMMON_NOT_OPENED = 0x20000, ///< Crypto Framework Common is not opened + FSP_ERR_CRYPTO_HAL_ERROR = 0x20001, ///< Cryoto HAL module returned an error + FSP_ERR_CRYPTO_KEY_BUF_NOT_ENOUGH = 0x20002, ///< Key buffer size is not enough to generate a key + FSP_ERR_CRYPTO_BUF_OVERFLOW = 0x20003, ///< Attempt to write data larger than what the buffer can hold + FSP_ERR_CRYPTO_INVALID_OPERATION_MODE = 0x20004, ///< Invalid operation mode. + FSP_ERR_MESSAGE_TOO_LONG = 0x20005, ///< Message for RSA encryption is too long. + FSP_ERR_RSA_DECRYPTION_ERROR = 0x20006, ///< RSA Decryption error. + + /** @note SF_CRYPTO APIs may return an error code starting from 0x10000 which is of Crypto module. + * Refer to sf_cryoto_err.h for Crypto error codes. + */ + + /* Start of Sensor specific */ + FSP_ERR_SENSOR_INVALID_DATA = 0x30000, ///< Data is invalid. + FSP_ERR_SENSOR_IN_STABILIZATION = 0x30001, ///< Sensor is stabilizing. + FSP_ERR_SENSOR_MEASUREMENT_NOT_FINISHED = 0x30002, ///< Measurement is not finished. + + /* Start of COMMS specific */ + FSP_ERR_COMMS_BUS_NOT_OPEN = 0x40000, ///< Bus is not open. +} fsp_err_t; + +/** @} */ + +/*********************************************************************************************************************** + * Function prototypes + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/fsp_features.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/fsp_features.h new file mode 100644 index 00000000000..5313968fc24 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/fsp_features.h @@ -0,0 +1,562 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_FEATURES_H +#define FSP_FEATURES_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include + +/* Different compiler support. */ +#include "fsp_common_api.h" +#include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Available modules. */ +typedef enum e_fsp_ip +{ + FSP_IP_CGC = 1, ///< Clock Generation Circuit + FSP_IP_CLMA = 2, ///< Clock Monitor Circuit + FSP_IP_MSTP = 3, ///< Module Stop + FSP_IP_ICU = 4, ///< Interrupt Control Unit + FSP_IP_BSC = 5, ///< Bus State Contoller + FSP_IP_CKIO = 6, ///< CKIO + FSP_IP_DMAC = 7, ///< DMA Controller + FSP_IP_ELC = 8, ///< Event Link Controller + FSP_IP_IOPORT = 9, ///< I/O Ports + FSP_IP_MTU3 = 10, ///< Multi-Function Timer Pulse Unit + FSP_IP_POE3 = 11, ///< Port Output Enable for MTU3 + FSP_IP_GPT = 12, ///< General PWM Timer + FSP_IP_POEG = 13, ///< Port Output Enable for GPT + FSP_IP_TFU = 14, ///< Arithmetic Unit for Trigonometric Functions + FSP_IP_CMT = 15, ///< Compare Match Timer + FSP_IP_CMTW = 16, ///< Compare Match Timer W + FSP_IP_WDT = 17, ///< Watch Dog Timer + FSP_IP_RTC = 18, ///< Real Time Clock + FSP_IP_ETHSS = 19, ///< Ethernet Subsystem + FSP_IP_GMAC = 20, ///< Ethernet MAC + FSP_IP_ETHSW = 21, ///< Ethernet Switch + FSP_IP_ESC = 22, ///< EtherCAT Slave Controller + FSP_IP_USBHS = 23, ///< USB High Speed + FSP_IP_SCI = 24, ///< Serial Communications Interface + FSP_IP_IIC = 25, ///< I2C Bus Interface + FSP_IP_CANFD = 26, ///< Controller Area Network with Flexible Data Rate + FSP_IP_SPI = 27, ///< Serial Peripheral Interface + FSP_IP_XSPI = 28, ///< expanded Serial Peripheral Interface + FSP_IP_CRC = 29, ///< Cyclic Redundancy Check Calculator + FSP_IP_BSCAN = 30, ///< Boundary Scan + FSP_IP_DSMIF = 31, ///< Delta Sigma Interface + FSP_IP_ADC12 = 32, ///< 12-Bit A/D Converter + FSP_IP_TSU = 33, ///< Temperature Sensor + FSP_IP_DOC = 34, ///< Data Operation Circuit + FSP_IP_SYSRAM = 35, ///< System SRAM + FSP_IP_ENCIF = 36, ///< Encoder Interface + FSP_IP_SHOSTIF = 37, ///< Serial Host Interface + FSP_IP_PHOSTIF = 38, ///< Parallel Host Interface +} fsp_ip_t; + +/** Signals that can be mapped to an interrupt. */ +typedef enum e_fsp_signal +{ + FSP_SIGNAL_INTCPU0 = (0), ///< Software interrupt 0 + FSP_SIGNAL_INTCPU1 = (1), ///< Software interrupt 1 + FSP_SIGNAL_INTCPU2 = (2), ///< Software interrupt 2 + FSP_SIGNAL_INTCPU3 = (3), ///< Software interrupt 3 + FSP_SIGNAL_INTCPU4 = (4), ///< Software interrupt 4 + FSP_SIGNAL_INTCPU5 = (5), ///< Software interrupt 5 + FSP_SIGNAL_IRQ0 = (6), ///< External pin interrupt 0 + FSP_SIGNAL_IRQ1 = (7), ///< External pin interrupt 1 + FSP_SIGNAL_IRQ2 = (8), ///< External pin interrupt 2 + FSP_SIGNAL_IRQ3 = (9), ///< External pin interrupt 3 + FSP_SIGNAL_IRQ4 = (10), ///< External pin interrupt 4 + FSP_SIGNAL_IRQ5 = (11), ///< External pin interrupt 5 + FSP_SIGNAL_IRQ6 = (12), ///< External pin interrupt 6 + FSP_SIGNAL_IRQ7 = (13), ///< External pin interrupt 7 + FSP_SIGNAL_IRQ8 = (14), ///< External pin interrupt 8 + FSP_SIGNAL_IRQ9 = (15), ///< External pin interrupt 9 + FSP_SIGNAL_IRQ10 = (16), ///< External pin interrupt 10 + FSP_SIGNAL_IRQ11 = (17), ///< External pin interrupt 11 + FSP_SIGNAL_IRQ12 = (18), ///< External pin interrupt 12 + FSP_SIGNAL_IRQ13 = (19), ///< External pin interrupt 13 + FSP_SIGNAL_BSC_CMI = (20), ///< Refresh compare match interrupt + FSP_SIGNAL_DMAC0_INT0 = (21), ///< DMAC0 transfer completion 0 + FSP_SIGNAL_DMAC0_INT1 = (22), ///< DMAC0 transfer completion 1 + FSP_SIGNAL_DMAC0_INT2 = (23), ///< DMAC0 transfer completion 2 + FSP_SIGNAL_DMAC0_INT3 = (24), ///< DMAC0 transfer completion 3 + FSP_SIGNAL_DMAC0_INT4 = (25), ///< DMAC0 transfer completion 4 + FSP_SIGNAL_DMAC0_INT5 = (26), ///< DMAC0 transfer completion 5 + FSP_SIGNAL_DMAC0_INT6 = (27), ///< DMAC0 transfer completion 6 + FSP_SIGNAL_DMAC0_INT7 = (28), ///< DMAC0 transfer completion 7 + FSP_SIGNAL_DMAC1_INT0 = (37), ///< DMAC1 transfer completion 0 + FSP_SIGNAL_DMAC1_INT1 = (38), ///< DMAC1 transfer completion 1 + FSP_SIGNAL_DMAC1_INT2 = (39), ///< DMAC1 transfer completion 2 + FSP_SIGNAL_DMAC1_INT3 = (40), ///< DMAC1 transfer completion 3 + FSP_SIGNAL_DMAC1_INT4 = (41), ///< DMAC1 transfer completion 4 + FSP_SIGNAL_DMAC1_INT5 = (42), ///< DMAC1 transfer completion 5 + FSP_SIGNAL_DMAC1_INT6 = (43), ///< DMAC1 transfer completion 6 + FSP_SIGNAL_DMAC1_INT7 = (44), ///< DMAC1 transfer completion 7 + FSP_SIGNAL_CMT0_CMI = (53), ///< CMT0 Compare match + FSP_SIGNAL_CMT1_CMI = (54), ///< CMT1 Compare match + FSP_SIGNAL_CMT2_CMI = (55), ///< CMT2 Compare match + FSP_SIGNAL_CMT3_CMI = (56), ///< CMT3 Compare match + FSP_SIGNAL_CMT4_CMI = (57), ///< CMT4 Compare match + FSP_SIGNAL_CMT5_CMI = (58), ///< CMT5 Compare match + FSP_SIGNAL_CMTW0_CMWI = (59), ///< CMTW0 Compare match + FSP_SIGNAL_CMTW0_IC0I = (60), ///< CMTW0 Input capture of register 0 + FSP_SIGNAL_CMTW0_IC1I = (61), ///< CMTW0 Input capture of register 1 + FSP_SIGNAL_CMTW0_OC0I = (62), ///< CMTW0 Output compare of register 0 + FSP_SIGNAL_CMTW0_OC1I = (63), ///< CMTW0 Output compare of register 1 + FSP_SIGNAL_CMTW1_CMWI = (64), ///< CMTW1 Compare match + FSP_SIGNAL_CMTW1_IC0I = (65), ///< CMTW1 Input capture of register 0 + FSP_SIGNAL_CMTW1_IC1I = (66), ///< CMTW1 Input capture of register 1 + FSP_SIGNAL_CMTW1_OC0I = (67), ///< CMTW1 Output compare of register 0 + FSP_SIGNAL_CMTW1_OC1I = (68), ///< CMTW1 Output compare of register 1 + FSP_SIGNAL_TGIA0 = (69), ///< MTU0.TGRA input capture/compare match + FSP_SIGNAL_TGIB0 = (70), ///< MTU0.TGRB input capture/compare match + FSP_SIGNAL_TGIC0 = (71), ///< MTU0.TGRC input capture/compare match + FSP_SIGNAL_TGID0 = (72), ///< MTU0.TGRD input capture/compare match + FSP_SIGNAL_TCIV0 = (73), ///< MTU0.TCNT overflow + FSP_SIGNAL_TGIE0 = (74), ///< MTU0.TGRE compare match + FSP_SIGNAL_TGIF0 = (75), ///< MTU0.TGRF compare match + FSP_SIGNAL_TGIA1 = (76), ///< MTU1.TGRA input capture/compare match + FSP_SIGNAL_TGIB1 = (77), ///< MTU1.TGRB input capture/compare match + FSP_SIGNAL_TCIV1 = (78), ///< MTU1.TCNT overflow + FSP_SIGNAL_TCIU1 = (79), ///< MTU1.TCNT underflow + FSP_SIGNAL_TGIA2 = (80), ///< MTU2.TGRA input capture/compare match + FSP_SIGNAL_TGIB2 = (81), ///< MTU2.TGRB input capture/compare match + FSP_SIGNAL_TCIV2 = (82), ///< MTU2.TCNT overflow + FSP_SIGNAL_TCIU2 = (83), ///< MTU2.TCNT underflow + FSP_SIGNAL_TGIA3 = (84), ///< MTU3.TGRA input capture/compare match + FSP_SIGNAL_TGIB3 = (85), ///< MTU3.TGRB input capture/compare match + FSP_SIGNAL_TGIC3 = (86), ///< MTU3.TGRC input capture/compare match + FSP_SIGNAL_TGID3 = (87), ///< MTU3.TGRD input capture/compare match + FSP_SIGNAL_TCIV3 = (88), ///< MTU3.TCNT overflow + FSP_SIGNAL_TGIA4 = (89), ///< MTU4.TGRA input capture/compare match + FSP_SIGNAL_TGIB4 = (90), ///< MTU4.TGRB input capture/compare match + FSP_SIGNAL_TGIC4 = (91), ///< MTU4.TGRC input capture/compare match + FSP_SIGNAL_TGID4 = (92), ///< MTU4.TGRD input capture/compare match + FSP_SIGNAL_TCIV4 = (93), ///< MTU4.TCNT overflow/underflow + FSP_SIGNAL_TGIU5 = (94), ///< MTU5.TGRU input capture/compare match + FSP_SIGNAL_TGIV5 = (95), ///< MTU5.TGRV input capture/compare match + FSP_SIGNAL_TGIW5 = (96), ///< MTU5.TGRW input capture/compare match + FSP_SIGNAL_TGIA6 = (97), ///< MTU6.TGRA input capture/compare match + FSP_SIGNAL_TGIB6 = (98), ///< MTU6.TGRB input capture/compare match + FSP_SIGNAL_TGIC6 = (99), ///< MTU6.TGRC input capture/compare match + FSP_SIGNAL_TGID6 = (100), ///< MTU6.TGRD input capture/compare match + FSP_SIGNAL_TCIV6 = (101), ///< MTU6.TCNT overflow + FSP_SIGNAL_TGIA7 = (102), ///< MTU7.TGRA input capture/compare match + FSP_SIGNAL_TGIB7 = (103), ///< MTU7.TGRB input capture/compare match + FSP_SIGNAL_TGIC7 = (104), ///< MTU7.TGRC input capture/compare match + FSP_SIGNAL_TGID7 = (105), ///< MTU7.TGRD input capture/compare match + FSP_SIGNAL_TCIV7 = (106), ///< MTU7.TCNT overflow/underflow + FSP_SIGNAL_TGIA8 = (107), ///< MTU8.TGRA input capture/compare match + FSP_SIGNAL_TGIB8 = (108), ///< MTU8.TGRB input capture/compare match + FSP_SIGNAL_TGIC8 = (109), ///< MTU8.TGRC input capture/compare match + FSP_SIGNAL_TGID8 = (110), ///< MTU8.TGRD input capture/compare match + FSP_SIGNAL_TCIV8 = (111), ///< MTU8.TCNT overflow + FSP_SIGNAL_OEI1 = (112), ///< Output enable interrupt 1 + FSP_SIGNAL_OEI2 = (113), ///< Output enable interrupt 2 + FSP_SIGNAL_OEI3 = (114), ///< Output enable interrupt 3 + FSP_SIGNAL_OEI4 = (115), ///< Output enable interrupt 4 + FSP_SIGNAL_GPT0_CCMPA = (116), ///< GPT0 GTCCRA input capture/compare match + FSP_SIGNAL_GPT0_CCMPB = (117), ///< GPT0 GTCCRB input capture/compare match + FSP_SIGNAL_GPT0_CMPC = (118), ///< GPT0 GTCCRC compare match + FSP_SIGNAL_GPT0_CMPD = (119), ///< GPT0 GTCCRD compare match + FSP_SIGNAL_GPT0_CMPE = (120), ///< GPT0 GTCCRE compare match + FSP_SIGNAL_GPT0_CMPF = (121), ///< GPT0 GTCCRF compare match + FSP_SIGNAL_GPT0_OVF = (122), ///< GPT0 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT0_UDF = (123), ///< GPT0 GTCNT underflow + FSP_SIGNAL_GPT0_DTE = (124), ///< GPT0 Dead time error + FSP_SIGNAL_GPT1_CCMPA = (125), ///< GPT1 GTCCRA input capture/compare match + FSP_SIGNAL_GPT1_CCMPB = (126), ///< GPT1 GTCCRB input capture/compare match + FSP_SIGNAL_GPT1_CMPC = (127), ///< GPT1 GTCCRC compare match + FSP_SIGNAL_GPT1_CMPD = (128), ///< GPT1 GTCCRD compare match + FSP_SIGNAL_GPT1_CMPE = (129), ///< GPT1 GTCCRE compare match + FSP_SIGNAL_GPT1_CMPF = (130), ///< GPT1 GTCCRF compare match + FSP_SIGNAL_GPT1_OVF = (131), ///< GPT1 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT1_UDF = (132), ///< GPT1 GTCNT underflow + FSP_SIGNAL_GPT1_DTE = (133), ///< GPT1 Dead time error + FSP_SIGNAL_GPT2_CCMPA = (134), ///< GPT2 GTCCRA input capture/compare match + FSP_SIGNAL_GPT2_CCMPB = (135), ///< GPT2 GTCCRB input capture/compare match + FSP_SIGNAL_GPT2_CMPC = (136), ///< GPT2 GTCCRC compare match + FSP_SIGNAL_GPT2_CMPD = (137), ///< GPT2 GTCCRD compare match + FSP_SIGNAL_GPT2_CMPE = (138), ///< GPT2 GTCCRE compare match + FSP_SIGNAL_GPT2_CMPF = (139), ///< GPT2 GTCCRF compare match + FSP_SIGNAL_GPT2_OVF = (140), ///< GPT2 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT2_UDF = (141), ///< GPT2 GTCNT underflow + FSP_SIGNAL_GPT2_DTE = (142), ///< GPT2 Dead time error + FSP_SIGNAL_GPT3_CCMPA = (143), ///< GPT3 GTCCRA input capture/compare match + FSP_SIGNAL_GPT3_CCMPB = (144), ///< GPT3 GTCCRB input capture/compare match + FSP_SIGNAL_GPT3_CMPC = (145), ///< GPT3 GTCCRC compare match + FSP_SIGNAL_GPT3_CMPD = (146), ///< GPT3 GTCCRD compare match + FSP_SIGNAL_GPT3_CMPE = (147), ///< GPT3 GTCCRE compare match + FSP_SIGNAL_GPT3_CMPF = (148), ///< GPT3 GTCCRF compare match + FSP_SIGNAL_GPT3_OVF = (149), ///< GPT3 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT3_UDF = (150), ///< GPT3 GTCNT underflow + FSP_SIGNAL_GPT3_DTE = (151), ///< GPT3 Dead time error + FSP_SIGNAL_GPT4_CCMPA = (152), ///< GPT4 GTCCRA input capture/compare match + FSP_SIGNAL_GPT4_CCMPB = (153), ///< GPT4 GTCCRB input capture/compare match + FSP_SIGNAL_GPT4_CMPC = (154), ///< GPT4 GTCCRC compare match + FSP_SIGNAL_GPT4_CMPD = (155), ///< GPT4 GTCCRD compare match + FSP_SIGNAL_GPT4_CMPE = (156), ///< GPT4 GTCCRE compare match + FSP_SIGNAL_GPT4_CMPF = (157), ///< GPT4 GTCCRF compare match + FSP_SIGNAL_GPT4_OVF = (158), ///< GPT4 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT4_UDF = (159), ///< GPT4 GTCNT underflow + FSP_SIGNAL_GPT4_DTE = (160), ///< GPT4 Dead time error + FSP_SIGNAL_GPT5_CCMPA = (161), ///< GPT5 GTCCRA input capture/compare match + FSP_SIGNAL_GPT5_CCMPB = (162), ///< GPT5 GTCCRB input capture/compare match + FSP_SIGNAL_GPT5_CMPC = (163), ///< GPT5 GTCCRC compare match + FSP_SIGNAL_GPT5_CMPD = (164), ///< GPT5 GTCCRD compare match + FSP_SIGNAL_GPT5_CMPE = (165), ///< GPT5 GTCCRE compare match + FSP_SIGNAL_GPT5_CMPF = (166), ///< GPT5 GTCCRF compare match + FSP_SIGNAL_GPT5_OVF = (167), ///< GPT5 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT5_UDF = (168), ///< GPT5 GTCNT underflow + FSP_SIGNAL_GPT5_DTE = (169), ///< GPT5 Dead time error + FSP_SIGNAL_GPT6_CCMPA = (170), ///< GPT6 GTCCRA input capture/compare match + FSP_SIGNAL_GPT6_CCMPB = (171), ///< GPT6 GTCCRB input capture/compare match + FSP_SIGNAL_GPT6_CMPC = (172), ///< GPT6 GTCCRC compare match + FSP_SIGNAL_GPT6_CMPD = (173), ///< GPT6 GTCCRD compare match + FSP_SIGNAL_GPT6_CMPE = (174), ///< GPT6 GTCCRE compare match + FSP_SIGNAL_GPT6_CMPF = (175), ///< GPT6 GTCCRF compare match + FSP_SIGNAL_GPT6_OVF = (176), ///< GPT6 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT6_UDF = (177), ///< GPT6 GTCNT underflow + FSP_SIGNAL_GPT6_DTE = (178), ///< GPT6 Dead time error + FSP_SIGNAL_GPT7_CCMPA = (179), ///< GPT7 GTCCRA input capture/compare match + FSP_SIGNAL_GPT7_CCMPB = (180), ///< GPT7 GTCCRB input capture/compare match + FSP_SIGNAL_GPT7_CMPC = (181), ///< GPT7 GTCCRC compare match + FSP_SIGNAL_GPT7_CMPD = (182), ///< GPT7 GTCCRD compare match + FSP_SIGNAL_GPT7_CMPE = (183), ///< GPT7 GTCCRE compare match + FSP_SIGNAL_GPT7_CMPF = (184), ///< GPT7 GTCCRF compare match + FSP_SIGNAL_GPT7_OVF = (185), ///< GPT7 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT7_UDF = (186), ///< GPT7 GTCNT underflow + FSP_SIGNAL_GPT7_DTE = (187), ///< GPT7 Dead time error + FSP_SIGNAL_GPT8_CCMPA = (188), ///< GPT8 GTCCRA input capture/compare match + FSP_SIGNAL_GPT8_CCMPB = (189), ///< GPT8 GTCCRB input capture/compare match + FSP_SIGNAL_GPT8_CMPC = (190), ///< GPT8 GTCCRC compare match + FSP_SIGNAL_GPT8_CMPD = (191), ///< GPT8 GTCCRD compare match + FSP_SIGNAL_GPT8_CMPE = (192), ///< GPT8 GTCCRE compare match + FSP_SIGNAL_GPT8_CMPF = (193), ///< GPT8 GTCCRF compare match + FSP_SIGNAL_GPT8_OVF = (194), ///< GPT8 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT8_UDF = (195), ///< GPT8 GTCNT underflow + FSP_SIGNAL_GPT8_DTE = (196), ///< GPT8 Dead time error + FSP_SIGNAL_GPT9_CCMPA = (197), ///< GPT9 GTCCRA input capture/compare match + FSP_SIGNAL_GPT9_CCMPB = (198), ///< GPT9 GTCCRB input capture/compare match + FSP_SIGNAL_GPT9_CMPC = (199), ///< GPT9 GTCCRC compare match + FSP_SIGNAL_GPT9_CMPD = (200), ///< GPT9 GTCCRD compare match + FSP_SIGNAL_GPT9_CMPE = (201), ///< GPT9 GTCCRE compare match + FSP_SIGNAL_GPT9_CMPF = (202), ///< GPT9 GTCCRF compare match + FSP_SIGNAL_GPT9_OVF = (203), ///< GPT9 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT9_UDF = (204), ///< GPT9 GTCNT underflow + FSP_SIGNAL_GPT9_DTE = (205), ///< GPT9 Dead time error + FSP_SIGNAL_GPT10_CCMPA = (206), ///< GPT10 GTCCRA input capture/compare match + FSP_SIGNAL_GPT10_CCMPB = (207), ///< GPT10 GTCCRB input capture/compare match + FSP_SIGNAL_GPT10_CMPC = (208), ///< GPT10 GTCCRC compare match + FSP_SIGNAL_GPT10_CMPD = (209), ///< GPT10 GTCCRD compare match + FSP_SIGNAL_GPT10_CMPE = (210), ///< GPT10 GTCCRE compare match + FSP_SIGNAL_GPT10_CMPF = (211), ///< GPT10 GTCCRF compare match + FSP_SIGNAL_GPT10_OVF = (212), ///< GPT10 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT10_UDF = (213), ///< GPT10 GTCNT underflow + FSP_SIGNAL_GPT10_DTE = (214), ///< GPT10 Dead time error + FSP_SIGNAL_GPT11_CCMPA = (215), ///< GPT11 GTCCRA input capture/compare match + FSP_SIGNAL_GPT11_CCMPB = (216), ///< GPT11 GTCCRB input capture/compare match + FSP_SIGNAL_GPT11_CMPC = (217), ///< GPT11 GTCCRC compare match + FSP_SIGNAL_GPT11_CMPD = (218), ///< GPT11 GTCCRD compare match + FSP_SIGNAL_GPT11_CMPE = (219), ///< GPT11 GTCCRE compare match + FSP_SIGNAL_GPT11_CMPF = (220), ///< GPT11 GTCCRF compare match + FSP_SIGNAL_GPT11_OVF = (221), ///< GPT11 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT11_UDF = (222), ///< GPT11 GTCNT underflow + FSP_SIGNAL_GPT11_DTE = (223), ///< GPT11 Dead time error + FSP_SIGNAL_GPT12_CCMPA = (224), ///< GPT12 GTCCRA input capture/compare match + FSP_SIGNAL_GPT12_CCMPB = (225), ///< GPT12 GTCCRB input capture/compare match + FSP_SIGNAL_GPT12_CMPC = (226), ///< GPT12 GTCCRC compare match + FSP_SIGNAL_GPT12_CMPD = (227), ///< GPT12 GTCCRD compare match + FSP_SIGNAL_GPT12_CMPE = (228), ///< GPT12 GTCCRE compare match + FSP_SIGNAL_GPT12_CMPF = (229), ///< GPT12 GTCCRF compare match + FSP_SIGNAL_GPT12_OVF = (230), ///< GPT12 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT12_UDF = (231), ///< GPT12 GTCNT underflow + FSP_SIGNAL_GPT12_DTE = (232), ///< GPT12 Dead time error + FSP_SIGNAL_GPT13_CCMPA = (233), ///< GPT13 GTCCRA input capture/compare match + FSP_SIGNAL_GPT13_CCMPB = (234), ///< GPT13 GTCCRB input capture/compare match + FSP_SIGNAL_GPT13_CMPC = (235), ///< GPT13 GTCCRC compare match + FSP_SIGNAL_GPT13_CMPD = (236), ///< GPT13 GTCCRD compare match + FSP_SIGNAL_GPT13_CMPE = (237), ///< GPT13 GTCCRE compare match + FSP_SIGNAL_GPT13_CMPF = (238), ///< GPT13 GTCCRF compare match + FSP_SIGNAL_GPT13_OVF = (239), ///< GPT13 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT13_UDF = (240), ///< GPT13 GTCNT underflow + FSP_SIGNAL_GPT13_DTE = (241), ///< GPT13 Dead time error + FSP_SIGNAL_POEG0_GROUP0 = (242), ///< POEG group A interrupt for channels in LLPP + FSP_SIGNAL_POEG0_GROUP1 = (243), ///< POEG group B interrupt for channels in LLPP + FSP_SIGNAL_POEG0_GROUP2 = (244), ///< POEG group C interrupt for channels in LLPP + FSP_SIGNAL_POEG0_GROUP3 = (245), ///< POEG group D interrupt for channels in LLPP + FSP_SIGNAL_POEG1_GROUP0 = (246), ///< POEG group A interrupt for channels in NONSAFETY + FSP_SIGNAL_POEG1_GROUP1 = (247), ///< POEG group B interrupt for channels in NONSAFETY + FSP_SIGNAL_POEG1_GROUP2 = (248), ///< POEG group C interrupt for channels in NONSAFETY + FSP_SIGNAL_POEG1_GROUP3 = (249), ///< POEG group D interrupt for channels in NONSAFETY + FSP_SIGNAL_GMAC_LPI = (250), ///< GMAC1 energy efficient + FSP_SIGNAL_GMAC_PMT = (251), ///< GMAC1 power management + FSP_SIGNAL_GMAC_SBD = (252), ///< GMAC1 general interrupt + FSP_SIGNAL_ETHSW_INTR = (253), ///< Ethernet Switch interrupt + FSP_SIGNAL_ETHSW_DLR = (254), ///< Ethernet Switch DLR interrupt + FSP_SIGNAL_ETHSW_PRP = (255), ///< Ethernet Switch PRP interrupt + FSP_SIGNAL_ETHSW_IHUB = (256), ///< Ethernet Switch Integrated Hub interrupt + FSP_SIGNAL_ETHSW_PTRN0 = (257), ///< Ethernet Switch RX Pattern Matcher interrupt 0 + FSP_SIGNAL_ETHSW_PTRN1 = (258), ///< Ethernet Switch RX Pattern Matcher interrupt 1 + FSP_SIGNAL_ETHSW_PTRN2 = (259), ///< Ethernet Switch RX Pattern Matcher interrupt 2 + FSP_SIGNAL_ETHSW_PTRN3 = (260), ///< Ethernet Switch RX Pattern Matcher interrupt 3 + FSP_SIGNAL_ETHSW_PTRN4 = (261), ///< Ethernet Switch RX Pattern Matcher interrupt 4 + FSP_SIGNAL_ETHSW_PTRN5 = (262), ///< Ethernet Switch RX Pattern Matcher interrupt 5 + FSP_SIGNAL_ETHSW_PTRN6 = (263), ///< Ethernet Switch RX Pattern Matcher interrupt 6 + FSP_SIGNAL_ETHSW_PTRN7 = (264), ///< Ethernet Switch RX Pattern Matcher interrupt 7 + FSP_SIGNAL_ETHSW_PTRN8 = (265), ///< Ethernet Switch RX Pattern Matcher interrupt 8 + FSP_SIGNAL_ETHSW_PTRN9 = (266), ///< Ethernet Switch RX Pattern Matcher interrupt 9 + FSP_SIGNAL_ETHSW_PTRN10 = (267), ///< Ethernet Switch RX Pattern Matcher interrupt 10 + FSP_SIGNAL_ETHSW_PTRN11 = (268), ///< Ethernet Switch RX Pattern Matcher interrupt 11 + FSP_SIGNAL_ETHSW_PTPOUT0 = (269), ///< Ethernet switch timer pulse output 0 + FSP_SIGNAL_ETHSW_PTPOUT1 = (270), ///< Ethernet switch timer pulse output 1 + FSP_SIGNAL_ETHSW_PTPOUT2 = (271), ///< Ethernet switch timer pulse output 2 + FSP_SIGNAL_ETHSW_PTPOUT3 = (272), ///< Ethernet switch timer pulse output 3 + FSP_SIGNAL_ETHSW_TDMAOUT0 = (273), ///< Ethernet Switch TDMA timer output 0 + FSP_SIGNAL_ETHSW_TDMAOUT1 = (274), ///< Ethernet Switch TDMA timer output 1 + FSP_SIGNAL_ETHSW_TDMAOUT2 = (275), ///< Ethernet Switch TDMA timer output 2 + FSP_SIGNAL_ETHSW_TDMAOUT3 = (276), ///< Ethernet Switch TDMA timer output 3 + FSP_SIGNAL_ESC_SYNC0 = (277), ///< EtherCAT Sync0 interrupt + FSP_SIGNAL_ESC_SYNC1 = (278), ///< EtherCAT Sync1 interrupt + FSP_SIGNAL_ESC_CAT = (279), ///< EtherCAT interrupt + FSP_SIGNAL_ESC_SOF = (280), ///< EtherCAT SOF interrupt + FSP_SIGNAL_ESC_EOF = (281), ///< EtherCAT EOF interrupt + FSP_SIGNAL_ESC_WDT = (282), ///< EtherCAT WDT interrupt + FSP_SIGNAL_ESC_RST = (283), ///< EtherCAT RESET interrupt + FSP_SIGNAL_USB_HI = (284), ///< USB (Host) interrupt + FSP_SIGNAL_USB_FI = (285), ///< USB (Function) interrupt + FSP_SIGNAL_USB_FDMA0 = (286), ///< USB (Function) DMA 0 transmit completion + FSP_SIGNAL_USB_FDMA1 = (287), ///< USB (Function) DMA 1 transmit completion + FSP_SIGNAL_SCI0_ERI = (288), ///< SCI0 Receive error + FSP_SIGNAL_SCI0_RXI = (289), ///< SCI0 Receive data full + FSP_SIGNAL_SCI0_TXI = (290), ///< SCI0 Transmit data empty + FSP_SIGNAL_SCI0_TEI = (291), ///< SCI0 Transmit end + FSP_SIGNAL_SCI1_ERI = (292), ///< SCI1 Receive error + FSP_SIGNAL_SCI1_RXI = (293), ///< SCI1 Receive data full + FSP_SIGNAL_SCI1_TXI = (294), ///< SCI1 Transmit data empty + FSP_SIGNAL_SCI1_TEI = (295), ///< SCI1 Transmit end + FSP_SIGNAL_SCI2_ERI = (296), ///< SCI2 Receive error + FSP_SIGNAL_SCI2_RXI = (297), ///< SCI2 Receive data full + FSP_SIGNAL_SCI2_TXI = (298), ///< SCI2 Transmit data empty + FSP_SIGNAL_SCI2_TEI = (299), ///< SCI2 Transmit end + FSP_SIGNAL_SCI3_ERI = (300), ///< SCI3 Receive error + FSP_SIGNAL_SCI3_RXI = (301), ///< SCI3 Receive data full + FSP_SIGNAL_SCI3_TXI = (302), ///< SCI3 Transmit data empty + FSP_SIGNAL_SCI3_TEI = (303), ///< SCI3 Transmit end + FSP_SIGNAL_SCI4_ERI = (304), ///< SCI4 Receive error + FSP_SIGNAL_SCI4_RXI = (305), ///< SCI4 Receive data full + FSP_SIGNAL_SCI4_TXI = (306), ///< SCI4 Transmit data empty + FSP_SIGNAL_SCI4_TEI = (307), ///< SCI4 Transmit end + FSP_SIGNAL_IIC0_EEI = (308), ///< IIC0 Transfer error or event generation + FSP_SIGNAL_IIC0_RXI = (309), ///< IIC0 Receive data full + FSP_SIGNAL_IIC0_TXI = (310), ///< IIC0 Transmit data empty + FSP_SIGNAL_IIC0_TEI = (311), ///< IIC0 Transmit end + FSP_SIGNAL_IIC1_EEI = (312), ///< IIC1 Transfer error or event generation + FSP_SIGNAL_IIC1_RXI = (313), ///< IIC1 Receive data full + FSP_SIGNAL_IIC1_TXI = (314), ///< IIC1 Transmit data empty + FSP_SIGNAL_IIC1_TEI = (315), ///< IIC1 Transmit end + FSP_SIGNAL_CAN_RXF = (316), ///< CANFD RX FIFO interrupt + FSP_SIGNAL_CAN_GLERR = (317), ///< CANFD Global error interrupt + FSP_SIGNAL_CAN0_TX = (318), ///< CAFND0 Channel TX interrupt + FSP_SIGNAL_CAN0_CHERR = (319), ///< CAFND0 Channel CAN error interrupt + FSP_SIGNAL_CAN0_COMFRX = (320), ///< CAFND0 Common RX FIFO or TXQ interrupt + FSP_SIGNAL_CAN1_TX = (321), ///< CAFND1 Channel TX interrupt + FSP_SIGNAL_CAN1_CHERR = (322), ///< CAFND1 Channel CAN error interrupt + FSP_SIGNAL_CAN1_COMFRX = (323), ///< CAFND1 Common RX FIFO or TXQ interrupt + FSP_SIGNAL_SPI0_SPRI = (324), ///< SPI0 Reception buffer full + FSP_SIGNAL_SPI0_SPTI = (325), ///< SPI0 Transmit buffer empty + FSP_SIGNAL_SPI0_SPII = (326), ///< SPI0 SPI idle + FSP_SIGNAL_SPI0_SPEI = (327), ///< SPI0 errors + FSP_SIGNAL_SPI0_SPCEND = (328), ///< SPI0 Communication complete + FSP_SIGNAL_SPI1_SPRI = (329), ///< SPI1 Reception buffer full + FSP_SIGNAL_SPI1_SPTI = (330), ///< SPI1 Transmit buffer empty + FSP_SIGNAL_SPI1_SPII = (331), ///< SPI1 SPI idle + FSP_SIGNAL_SPI1_SPEI = (332), ///< SPI1 errors + FSP_SIGNAL_SPI1_SPCEND = (333), ///< SPI1 Communication complete + FSP_SIGNAL_SPI2_SPRI = (334), ///< SPI2 Reception buffer full + FSP_SIGNAL_SPI2_SPTI = (335), ///< SPI2 Transmit buffer empty + FSP_SIGNAL_SPI2_SPII = (336), ///< SPI2 SPI idle + FSP_SIGNAL_SPI2_SPEI = (337), ///< SPI2 errors + FSP_SIGNAL_SPI2_SPCEND = (338), ///< SPI2 Communication complete + FSP_SIGNAL_XSPI0_INT = (339), ///< xSPI0 Interrupt + FSP_SIGNAL_XSPI0_INTERR = (340), ///< xSPI0 Error interrupt + FSP_SIGNAL_XSPI1_INT = (341), ///< xSPI1 Interrupt + FSP_SIGNAL_XSPI1_INTERR = (342), ///< xSPI1 Error interrupt + FSP_SIGNAL_DSMIF0_CDRUI = (343), ///< DSMIF0 current data register update (ORed ch0 to ch2) + FSP_SIGNAL_DSMIF1_CDRUI = (344), ///< DSMIF1 current data register update (ORed ch3 to ch5) + FSP_SIGNAL_ADC0_ADI = (345), ///< ADC0 A/D scan end interrupt + FSP_SIGNAL_ADC0_GBADI = (346), ///< ADC0 A/D scan end interrupt for Group B + FSP_SIGNAL_ADC0_GCADI = (347), ///< ADC0 A/D scan end interrupt for Group C + FSP_SIGNAL_ADC0_CMPAI = (348), ///< ADC0 Window A compare match + FSP_SIGNAL_ADC0_CMPBI = (349), ///< ADC0 Window B compare match + FSP_SIGNAL_ADC1_ADI = (350), ///< ADC1 A/D scan end interrupt + FSP_SIGNAL_ADC1_GBADI = (351), ///< ADC1 A/D scan end interrupt for Group B + FSP_SIGNAL_ADC1_GCADI = (352), ///< ADC1 A/D scan end interrupt for Group C + FSP_SIGNAL_ADC1_CMPAI = (353), ///< ADC1 Window A compare match + FSP_SIGNAL_ADC1_CMPBI = (354), ///< ADC1 Window B compare match + FSP_SIGNAL_MBX_INT0 = (372), ///< Mailbox (Host CPU to Cortex-R52) interrupt 0 + FSP_SIGNAL_MBX_INT1 = (373), ///< Mailbox (Host CPU to Cortex-R52) interrupt 1 + FSP_SIGNAL_MBX_INT2 = (374), ///< Mailbox (Host CPU to Cortex-R52) interrupt 2 + FSP_SIGNAL_MBX_INT3 = (375), ///< Mailbox (Host CPU to Cortex-R52) interrupt 3 + FSP_SIGNAL_CPU0_ERR0 = (384), ///< Cortex-R52 CPU0 error event 0 + FSP_SIGNAL_CPU0_ERR1 = (385), ///< Cortex-R52 CPU0 error event 1 + FSP_SIGNAL_PERI_ERR0 = (388), ///< Peripherals error event 0 + FSP_SIGNAL_PERI_ERR1 = (389), ///< Peripherals error event 1 + FSP_SIGNAL_SHOST_INT = (390), ///< SHOSTIF interrupt + FSP_SIGNAL_PHOST_INT = (391), ///< PHOSTIF interrupt + FSP_SIGNAL_INTCPU6 = (392), ///< Software interrupt 6 + FSP_SIGNAL_INTCPU7 = (393), ///< Software interrupt 7 + FSP_SIGNAL_IRQ14 = (394), ///< External pin interrupt 14 + FSP_SIGNAL_IRQ15 = (395), ///< External pin interrupt 15 + FSP_SIGNAL_GPT14_CCMPA = (396), ///< GPT14 GTCCRA input capture/compare match + FSP_SIGNAL_GPT14_CCMPB = (397), ///< GPT14 GTCCRB input capture/compare match + FSP_SIGNAL_GPT14_CMPC = (398), ///< GPT14 GTCCRC compare match + FSP_SIGNAL_GPT14_CMPD = (399), ///< GPT14 GTCCRD compare match + FSP_SIGNAL_GPT14_CMPE = (400), ///< GPT14 GTCCRE compare match + FSP_SIGNAL_GPT14_CMPF = (401), ///< GPT14 GTCCRF compare match + FSP_SIGNAL_GPT14_OVF = (402), ///< GPT14 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT14_UDF = (403), ///< GPT14 GTCNT underflow + FSP_SIGNAL_GPT15_CCMPA = (404), ///< GPT15 GTCCRA input capture/compare match + FSP_SIGNAL_GPT15_CCMPB = (405), ///< GPT15 GTCCRB input capture/compare match + FSP_SIGNAL_GPT15_CMPC = (406), ///< GPT15 GTCCRC compare match + FSP_SIGNAL_GPT15_CMPD = (407), ///< GPT15 GTCCRD compare match + FSP_SIGNAL_GPT15_CMPE = (408), ///< GPT15 GTCCRE compare match + FSP_SIGNAL_GPT15_CMPF = (409), ///< GPT15 GTCCRF compare match + FSP_SIGNAL_GPT15_OVF = (410), ///< GPT15 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT15_UDF = (411), ///< GPT15 GTCNT underflow + FSP_SIGNAL_GPT16_CCMPA = (412), ///< GPT16 GTCCRA input capture/compare match + FSP_SIGNAL_GPT16_CCMPB = (413), ///< GPT16 GTCCRB input capture/compare match + FSP_SIGNAL_GPT16_CMPC = (414), ///< GPT16 GTCCRC compare match + FSP_SIGNAL_GPT16_CMPD = (415), ///< GPT16 GTCCRD compare match + FSP_SIGNAL_GPT16_CMPE = (416), ///< GPT16 GTCCRE compare match + FSP_SIGNAL_GPT16_CMPF = (417), ///< GPT16 GTCCRF compare match + FSP_SIGNAL_GPT16_OVF = (418), ///< GPT16 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT16_UDF = (419), ///< GPT16 GTCNT underflow + FSP_SIGNAL_GPT17_CCMPA = (420), ///< GPT17 GTCCRA input capture/compare match + FSP_SIGNAL_GPT17_CCMPB = (421), ///< GPT17 GTCCRB input capture/compare match + FSP_SIGNAL_GPT17_CMPC = (422), ///< GPT17 GTCCRC compare match + FSP_SIGNAL_GPT17_CMPD = (423), ///< GPT17 GTCCRD compare match + FSP_SIGNAL_GPT17_CMPE = (424), ///< GPT17 GTCCRE compare match + FSP_SIGNAL_GPT17_CMPF = (425), ///< GPT17 GTCCRF compare match + FSP_SIGNAL_GPT17_OVF = (426), ///< GPT17 GTCNT overflow (GTPR compare match) + FSP_SIGNAL_GPT17_UDF = (427), ///< GPT17 GTCNT underflow + FSP_SIGNAL_POEG2_GROUP0 = (428), ///< POEG group A interrupt for channels in SAFETY + FSP_SIGNAL_POEG2_GROUP1 = (429), ///< POEG group B interrupt for channels in SAFETY + FSP_SIGNAL_POEG2_GROUP2 = (430), ///< POEG group C interrupt for channels in SAFETY + FSP_SIGNAL_POEG2_GROUP3 = (431), ///< POEG group D interrupt for channels in SAFETY + FSP_SIGNAL_RTC_ALM = (432), ///< Alarm interrupt + FSP_SIGNAL_RTC_1S = (433), ///< 1 second interrupt + FSP_SIGNAL_RTC_PRD = (434), ///< Fixed interval interrupt + FSP_SIGNAL_SCI5_ERI = (435), ///< SCI5 Receive error + FSP_SIGNAL_SCI5_RXI = (436), ///< SCI5 Receive data full + FSP_SIGNAL_SCI5_TXI = (437), ///< SCI5 Transmit data empty + FSP_SIGNAL_SCI5_TEI = (438), ///< SCI5 Transmit end + FSP_SIGNAL_IIC2_EEI = (439), ///< IIC2 Transfer error or event generation + FSP_SIGNAL_IIC2_RXI = (440), ///< IIC2 Receive data full + FSP_SIGNAL_IIC2_TXI = (441), ///< IIC2 Transmit data empty + FSP_SIGNAL_IIC2_TEI = (442), ///< IIC2 Transmit end + FSP_SIGNAL_SPI3_SPRI = (443), ///< SPI3 Reception buffer full + FSP_SIGNAL_SPI3_SPTI = (444), ///< SPI3 Transmit buffer empty + FSP_SIGNAL_SPI3_SPII = (445), ///< SPI3 SPI idle + FSP_SIGNAL_SPI3_SPEI = (446), ///< SPI3 errors + FSP_SIGNAL_SPI3_SPCEND = (447), ///< SPI3 Communication complete + FSP_SIGNAL_DREQ = (448), ///< External DMA request + FSP_SIGNAL_CAN_RF_DMAREQ0 = (449), ///< CAFND RX FIFO 0 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ1 = (450), ///< CAFND RX FIFO 1 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ2 = (451), ///< CAFND RX FIFO 2 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ3 = (452), ///< CAFND RX FIFO 3 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ4 = (453), ///< CAFND RX FIFO 4 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ5 = (454), ///< CAFND RX FIFO 5 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ6 = (455), ///< CAFND RX FIFO 6 DMA request + FSP_SIGNAL_CAN_RF_DMAREQ7 = (456), ///< CAFND RX FIFO 7 DMA request + FSP_SIGNAL_CAN0_CF_DMAREQ = (457), ///< CAFND0 First common FIFO DMA request + FSP_SIGNAL_CAN1_CF_DMAREQ = (458), ///< CAFND1 First common FIFO DMA request + FSP_SIGNAL_ADC0_WCMPM = (459), ///< ADC0 compare match + FSP_SIGNAL_ADC0_WCMPUM = (460), ///< ADC0 compare mismatch + FSP_SIGNAL_ADC1_WCMPM = (461), ///< ADC1 compare match + FSP_SIGNAL_ADC1_WCMPUM = (462), ///< ADC1 compare mismatch + FSP_SIGNAL_TCIV4_OF = (463), ///< MTU4.TCNT overflow + FSP_SIGNAL_TCIV4_UF = (464), ///< MTU4.TCNT underflow + FSP_SIGNAL_TCIV7_OF = (465), ///< MTU7.TCNT overflow + FSP_SIGNAL_TCIV7_UF = (466), ///< MTU7.TCNT underflow + FSP_SIGNAL_IOPORT_GROUP1 = (467), ///< Input edge detection of input port group 1 + FSP_SIGNAL_IOPORT_GROUP2 = (468), ///< Input edge detection of input port group 2 + FSP_SIGNAL_IOPORT_SINGLE0 = (469), ///< Input edge detection of single input port 0 + FSP_SIGNAL_IOPORT_SINGLE1 = (470), ///< Input edge detection of single input port 1 + FSP_SIGNAL_IOPORT_SINGLE2 = (471), ///< Input edge detection of single input port 2 + FSP_SIGNAL_IOPORT_SINGLE3 = (472), ///< Input edge detection of single input port 3 + FSP_SIGNAL_GPT0_ADTRGA = (473), ///< GPT0 GTADTRA compare match + FSP_SIGNAL_GPT0_ADTRGB = (474), ///< GPT0 GTADTRB compare match + FSP_SIGNAL_GPT1_ADTRGA = (475), ///< GPT1 GTADTRA compare match + FSP_SIGNAL_GPT1_ADTRGB = (476), ///< GPT1 GTADTRB compare match + FSP_SIGNAL_GPT2_ADTRGA = (477), ///< GPT2 GTADTRA compare match + FSP_SIGNAL_GPT2_ADTRGB = (478), ///< GPT2 GTADTRB compare match + FSP_SIGNAL_GPT3_ADTRGA = (479), ///< GPT3 GTADTRA compare match + FSP_SIGNAL_GPT3_ADTRGB = (480), ///< GPT3 GTADTRB compare match + FSP_SIGNAL_GPT4_ADTRGA = (481), ///< GPT4 GTADTRA compare match + FSP_SIGNAL_GPT4_ADTRGB = (482), ///< GPT4 GTADTRB compare match + FSP_SIGNAL_GPT5_ADTRGA = (483), ///< GPT5 GTADTRA compare match + FSP_SIGNAL_GPT5_ADTRGB = (484), ///< GPT5 GTADTRB compare match + FSP_SIGNAL_GPT6_ADTRGA = (485), ///< GPT6 GTADTRA compare match + FSP_SIGNAL_GPT6_ADTRGB = (486), ///< GPT6 GTADTRB compare match + FSP_SIGNAL_GPT7_ADTRGA = (487), ///< GPT7 GTADTRA compare match + FSP_SIGNAL_GPT7_ADTRGB = (488), ///< GPT7 GTADTRB compare match + FSP_SIGNAL_GPT8_ADTRGA = (489), ///< GPT8 GTADTRA compare match + FSP_SIGNAL_GPT8_ADTRGB = (490), ///< GPT8 GTADTRB compare match + FSP_SIGNAL_GPT9_ADTRGA = (491), ///< GPT9 GTADTRA compare match + FSP_SIGNAL_GPT9_ADTRGB = (492), ///< GPT9 GTADTRB compare match + FSP_SIGNAL_GPT10_ADTRGA = (493), ///< GPT10 GTADTRA compare match + FSP_SIGNAL_GPT10_ADTRGB = (494), ///< GPT10 GTADTRB compare match + FSP_SIGNAL_GPT11_ADTRGA = (495), ///< GPT11 GTADTRA compare match + FSP_SIGNAL_GPT11_ADTRGB = (496), ///< GPT11 GTADTRB compare match + FSP_SIGNAL_GPT12_ADTRGA = (497), ///< GPT12 GTADTRA compare match + FSP_SIGNAL_GPT12_ADTRGB = (498), ///< GPT12 GTADTRB compare match + FSP_SIGNAL_GPT13_ADTRGA = (499), ///< GPT13 GTADTRA compare match + FSP_SIGNAL_GPT13_ADTRGB = (500), ///< GPT13 GTADTRB compare match + FSP_SIGNAL_NONE +} fsp_signal_t; + +typedef void (* fsp_vector_t)(void); + +/** @} (end addtogroup BSP_MCU) */ + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/fsp_version.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/fsp_version.h new file mode 100644 index 00000000000..274f97a19cf --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/fsp_version.h @@ -0,0 +1,80 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef FSP_VERSION_H +#define FSP_VERSION_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" + +/*******************************************************************************************************************//** + * @addtogroup RENESAS_COMMON + * @{ + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** FSP pack major version. */ +#define FSP_VERSION_MAJOR (2U) + +/** FSP pack minor version. */ +#define FSP_VERSION_MINOR (0U) + +/** FSP pack patch version. */ +#define FSP_VERSION_PATCH (0U) + +/** FSP pack version build number (currently unused). */ +#define FSP_VERSION_BUILD (0U) + +/** Public FSP version name. */ +#define FSP_VERSION_STRING ("2.0.0") + +/** Unique FSP version ID. */ +#define FSP_VERSION_BUILD_STRING ("Built with RZ/N Flexible Software Package version 2.0.0") + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** FSP Pack version structure */ +typedef union st_fsp_pack_version +{ + /** Version id */ + uint32_t version_id; + + /** Code version parameters, little endian order. */ + struct version_id_b_s + { + uint8_t build; ///< Build version of FSP Pack + uint8_t patch; ///< Patch version of FSP Pack + uint8_t minor; ///< Minor version of FSP Pack + uint8_t major; ///< Major version of FSP Pack + } version_id_b; +} fsp_pack_version_t; + +/** @} */ + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/instances/r_ioport.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/instances/r_ioport.h new file mode 100644 index 00000000000..b9f4e1b93e3 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/instances/r_ioport.h @@ -0,0 +1,212 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +#ifndef R_IOPORT_H +#define R_IOPORT_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#include "r_ioport_api.h" +#include "r_ioport_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define IOPORT_SINGLE_PORT_NUM (4) +#define IOPORT_PORT_GROUP_NUM (2) +#define IOPORT_PORT_GROUP_1 (0) +#define IOPORT_PORT_GROUP_2 (1) +#define IOPORT_SINGLE_PORT_0 (0) +#define IOPORT_SINGLE_PORT_1 (1) +#define IOPORT_SINGLE_PORT_2 (2) +#define IOPORT_SINGLE_PORT_3 (3) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Pin selection for port group + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_pin_selection +{ + IOPORT_EVENT_PIN_SELECTION_NONE = 0x00, ///< No pin selection for port group + IOPORT_EVENT_PIN_SELECTION_PIN_0 = 0x01, ///< Select pin 0 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_1 = 0x02, ///< Select pin 1 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_2 = 0x04, ///< Select pin 2 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_3 = 0x08, ///< Select pin 3 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_4 = 0x10, ///< Select pin 4 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_5 = 0x20, ///< Select pin 5 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_6 = 0x40, ///< Select pin 6 to port group + IOPORT_EVENT_PIN_SELECTION_PIN_7 = 0x80, ///< Select pin 7 to port group +} ioport_event_pin_selection_t; + +/** Port group operation + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_output_operation +{ + IOPORT_EVENT_OUTPUT_OPERATION_LOW = 0x0, ///< Set Low output to output operation + IOPORT_EVENT_OUTPUT_OPERATION_HIGH = 0x1, ///< Set High output to output operation + IOPORT_EVENT_OUTPUT_OPERATION_TOGGLE = 0x2, ///< Set toggle output to output operation + IOPORT_EVENT_OUTPUT_OPERATION_BUFFER = 0x3, ///< Set buffer value output to output operation +} ioport_event_output_operation_t; + +/** Input port group event control + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_control +{ + IOPORT_EVENT_CONTROL_DISABLE = 0x0, ///< Disable function related with event link + IOPORT_EVENT_CONTROL_ENABLE = 0x1, ///< Enable function related with event link +} ioport_event_control_t; + +/** Single port event direction + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_direction +{ + IOPORT_EVENT_DIRECTION_OUTPUT = 0x0, ///< Set output direction to single port + IOPORT_EVENT_DIRECTION_INPUT = 0x1, ///< Set input direction to single port +} ioport_event_direction_t; + +/** Input event edge detection + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_detection +{ + IOPORT_EVENT_DETECTION_RISING_EDGE = 0x0, ///< Set rising edge to event detection for input event + IOPORT_EVENT_DETECTION_FALLING_EDGE = 0x1, ///< Set falling edge to event detection for input event + IOPORT_EVENT_DETECTION_BOTH_EGDE = 0x2, ///< Set both edges to event detection for input event +} ioport_event_detection_t; + +/** Initial value for buffer register + * @note Event link must be configured by the ELC + */ +typedef enum e_ioport_event_initial_buffer_value +{ + IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW = 0U, ///< Set low input to initial value of buffer register for input port group + IOPORT_EVENT_INITIAL_BUFFER_VALUE_HIGH = 1U, ///< Set high input to initial value of buffer register for input port group +} ioport_event_initial_buffer_value_t; + +/** Single port configuration + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_event_single +{ + ioport_event_control_t event_control; ///< Event link control for single port + ioport_event_direction_t direction; ///< Event direction for single port + uint16_t port_num; ///< Port number specified to single port + ioport_event_output_operation_t operation; ///< Single port operation select + ioport_event_detection_t edge_detection; ///< Edge detection select +} ioport_event_single_t; + +/** Output port group configuration + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_event_group_output +{ + uint8_t pin_select; ///< Port number specified to output port group + ioport_event_output_operation_t operation; ///< Port group operation select +} ioport_event_group_output_t; + +/** Input port group configuration + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_event_group_input +{ + ioport_event_control_t event_control; ///< Event link control for input port group + ioport_event_detection_t edge_detection; ///< Edge detection select + ioport_event_control_t overwrite_control; ///< Buffer register overwrite control + uint8_t pin_select; ///< Port number specified to input port group + uint8_t buffer_init_value; ///< Buffer register initial value +} ioport_event_group_input_t; + +/** IOPORT extended configuration for event link function + * @note Event link must be configured by the ELC + */ +typedef struct st_ioport_extend_cfg +{ + ioport_event_group_output_t port_group_output_cfg[IOPORT_PORT_GROUP_NUM]; ///< Output port group configuration + ioport_event_group_input_t port_group_input_cfg[IOPORT_PORT_GROUP_NUM]; ///< Input port group configuration + ioport_event_single_t single_port_cfg[IOPORT_SINGLE_PORT_NUM]; ///< Single input port configuration +} ioport_extend_cfg_t; + +/** IOPORT private control block. DO NOT MODIFY. Initialization occurs when R_IOPORT_Open() is called. */ +typedef struct st_ioport_instance_ctrl +{ + uint32_t open; // Whether or not ioport is open + void const * p_context; // Pointer to context to be passed into callback + ioport_cfg_t const * p_cfg; // Pointer to the configuration block +} ioport_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const ioport_api_t g_ioport_on_ioport; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ + +fsp_err_t R_IOPORT_Open(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_Close(ioport_ctrl_t * const p_ctrl); +fsp_err_t R_IOPORT_PinsCfg(ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg); +fsp_err_t R_IOPORT_PinCfg(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg); +fsp_err_t R_IOPORT_PinEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event); +fsp_err_t R_IOPORT_PinEventOutputWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value); +fsp_err_t R_IOPORT_PinRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value); +fsp_err_t R_IOPORT_PinWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level); +fsp_err_t R_IOPORT_PortDirectionSet(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask); +fsp_err_t R_IOPORT_PortEventInputRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data); +fsp_err_t R_IOPORT_PortEventOutputWrite(ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value); +fsp_err_t R_IOPORT_PortRead(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value); +fsp_err_t R_IOPORT_PortWrite(ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask); + +/*******************************************************************************************************************//** + * @} (end defgroup IOPORT) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif // R_IOPORT_H diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/instances/r_sci_uart.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/instances/r_sci_uart.h new file mode 100644 index 00000000000..fd403941112 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/inc/instances/r_sci_uart.h @@ -0,0 +1,246 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SCI_UART_H +#define R_SCI_UART_H + +/*******************************************************************************************************************//** + * @addtogroup SCI_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_uart_api.h" +#include "r_sci_uart_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Enumeration for SCI clock source */ +typedef enum e_sci_uart_clock +{ + SCI_UART_CLOCK_INT, ///< Use internal clock for baud generation + SCI_UART_CLOCK_INT_WITH_BAUDRATE_OUTPUT, ///< Use internal clock for baud generation and output on SCK + SCI_UART_CLOCK_EXT8X, ///< Use external clock 8x baud rate + SCI_UART_CLOCK_EXT16X ///< Use external clock 16x baud rate +} sci_uart_clock_t; + +/** UART flow control mode definition */ +typedef enum e_sci_uart_flow_control +{ + SCI_UART_FLOW_CONTROL_RTS = 0U, ///< Use CTSn_RTSn pin for RTS + SCI_UART_FLOW_CONTROL_CTS = 1U, ///< Use CTSn_RTSn pin for CTS + SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS = 3U, ///< Use CTSn pin for CTS, CTSn_RTSn pin for RTS + SCI_UART_FLOW_CONTROL_CTSRTS = 5U, ///< Use SCI pin for CTS, external pin for RTS +} sci_uart_flow_control_t; + +/** UART instance control block. */ +typedef struct st_sci_uart_instance_ctrl +{ + /* Parameters to control UART peripheral device */ + uint8_t fifo_depth; // FIFO depth of the UART channel + uint8_t rx_transfer_in_progress; // Set to 1 if a receive transfer is in progress, 0 otherwise + uint8_t data_bytes : 2; // 1 byte for 7 or 8 bit data, 2 bytes for 9 bit data + uint8_t bitrate_modulation : 1; // 1 if bit rate modulation is enabled, 0 otherwise + uint32_t open; // Used to determine if the channel is configured + + bsp_io_port_pin_t flow_pin; + + /* Source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint8_t const * p_tx_src; + + /* Size of source buffer pointer used to fill hardware FIFO from transmit ISR. */ + uint32_t tx_src_bytes; + + /* Destination buffer pointer used for receiving data. */ + uint8_t const * p_rx_dest; + + /* Size of destination buffer pointer used for receiving data. */ + uint32_t rx_dest_bytes; + + /* Pointer to the configuration block. */ + uart_cfg_t const * p_cfg; + + /* Base register for this channel */ + R_SCI0_Type * p_reg; + + void (* p_callback)(uart_callback_args_t *); // Pointer to callback that is called when a uart_event_t occurs. + uart_callback_args_t * p_callback_memory; // Pointer to non-secure memory that can be used to pass arguments to a callback in non-secure memory. + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} sci_uart_instance_ctrl_t; + +/** Receive FIFO trigger configuration. */ +typedef enum e_sci_uart_rx_fifo_trigger +{ + SCI_UART_RX_FIFO_TRIGGER_1 = 0x1, ///< Callback after each byte is received without buffering + SCI_UART_RX_FIFO_TRIGGER_MAX = 0xF, ///< Callback when FIFO is full or after 15 bit times with no data (fewer interrupts) +} sci_uart_rx_fifo_trigger_t; + +/** Asynchronous Start Bit Edge Detection configuration. */ +typedef enum e_sci_uart_start_bit +{ + SCI_UART_START_BIT_LOW_LEVEL = 0x0, ///< Detect low level on RXDn pin as start bit + SCI_UART_START_BIT_FALLING_EDGE = 0x1, ///< Detect falling level on RXDn pin as start bit +} sci_uart_start_bit_t; + +/** Noise cancellation configuration. */ +typedef enum e_sci_uart_noise_cancellation +{ + SCI_UART_NOISE_CANCELLATION_DISABLE = 0x0, ///< Disable noise cancellation + SCI_UART_NOISE_CANCELLATION_ENABLE = 0x1, ///< Enable noise cancellation, The base clock signal divided by 1 + SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_1 = 0x2, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 1 + SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_2 = 0x3, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 2 + SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_4 = 0x4, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 4 + SCI_UART_NOISE_CANCELLATION_ENABLE_FILTER_CKS_DIV_8 = 0x5, ///< Enable noise cancellation, The on-chip baud rate generator source clock divided by 8 +} sci_uart_noise_cancellation_t; + +/** RS-485 Enable/Disable. */ +typedef enum e_sci_uart_rs485_enable +{ + SCI_UART_RS485_DISABLE = 0, ///< RS-485 disabled. + SCI_UART_RS485_ENABLE = 1, ///< RS-485 enabled. +} sci_uart_rs485_enable_t; + +/** The polarity of the RS-485 DE signal. */ +typedef enum e_sci_uart_rs485_de_polarity +{ + SCI_UART_RS485_DE_POLARITY_HIGH = 0, ///< The DE signal is high when a write transfer is in progress. + SCI_UART_RS485_DE_POLARITY_LOW = 1, ///< The DE signal is low when a write transfer is in progress. +} sci_uart_rs485_de_polarity_t; + +/** Source clock selection options for SCI. */ +typedef enum e_sci_uart_clock_source +{ + SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK = 0, + SCI_UART_CLOCK_SOURCE_SCI1ASYNCCLK = 1, + SCI_UART_CLOCK_SOURCE_SCI2ASYNCCLK = 2, + SCI_UART_CLOCK_SOURCE_SCI3ASYNCCLK = 3, + SCI_UART_CLOCK_SOURCE_SCI4ASYNCCLK = 4, + SCI_UART_CLOCK_SOURCE_SCI5ASYNCCLK = 5, + SCI_UART_CLOCK_SOURCE_PCLKM = 6, +} sci_uart_clock_source_t; + +/** Baudrate calculation configuration. */ +typedef struct st_sci_uart_baud_calculation +{ + uint32_t baudrate; ///< Target baudrate + bool bitrate_modulation; ///< Whether bitrate modulation use or not + uint32_t baud_rate_error_x_1000; ///< Max baudrate percent error +} sci_uart_baud_calculation_t; + +/** Register settings to achieve a desired baud rate and modulation duty. */ +typedef struct st_sci_baud_setting_t +{ + union + { + uint32_t baudrate_bits; + + struct + { + uint32_t : 4; + uint32_t bgdm : 1; ///< Baud Rate Generator Double-Speed Mode Select + uint32_t abcs : 1; ///< Asynchronous Mode Base Clock Select + uint32_t abcse : 1; ///< Asynchronous Mode Extended Base Clock Select 1 + uint32_t : 1; + uint32_t brr : 8; ///< Bit Rate Register setting + uint32_t brme : 1; ///< Bit Rate Modulation Enable + uint32_t : 3; + uint32_t cks : 2; ///< CKS value to get divisor (CKS = N) + uint32_t : 2; + uint32_t mddr : 8; ///< Modulation Duty Register setting + } baudrate_bits_b; + }; +} sci_baud_setting_t; + +/** Configuration settings for controlling the DE signal for RS-485. */ +typedef struct st_sci_uart_rs485_setting +{ + sci_uart_rs485_enable_t enable; ///< Enable the DE signal. + sci_uart_rs485_de_polarity_t polarity; ///< DE signal polarity. + uint8_t assertion_time : 5; ///< Time in baseclock units after assertion of the DE signal and before the start of the write transfer. + uint8_t negation_time : 5; ///< Time in baseclock units after the end of a write transfer and before the DE signal is negated. +} sci_uart_rs485_setting_t; + +/** UART on SCI device Configuration */ +typedef struct st_sci_uart_extended_cfg +{ + sci_uart_clock_t clock; ///< The source clock for the baud-rate generator. If internal optionally output baud rate on SCK + sci_uart_start_bit_t rx_edge_start; ///< Start reception on falling edge + sci_uart_noise_cancellation_t noise_cancel; ///< Noise cancellation setting + + sci_baud_setting_t * p_baud_setting; ///< Register settings for a desired baud rate. + + sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel has no FIFO or if DMAC is used. + + bsp_io_port_pin_t flow_control_pin; ///< UART Driver Enable pin + sci_uart_flow_control_t flow_control; ///< CTS/RTS function + sci_uart_rs485_setting_t rs485_setting; ///< RS-485 settings. + + /** Clock source to generate SCK can either be selected as PCLKM or SCInASYNCCLK. */ + sci_uart_clock_source_t clock_source; +} sci_uart_extended_cfg_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const uart_api_t g_uart_on_sci; + +/** @endcond */ + +fsp_err_t R_SCI_UART_Open(uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg); +fsp_err_t R_SCI_UART_Read(uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes); +fsp_err_t R_SCI_UART_Write(uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes); +fsp_err_t R_SCI_UART_BaudSet(uart_ctrl_t * const p_ctrl, void const * const p_baud_setting); +fsp_err_t R_SCI_UART_InfoGet(uart_ctrl_t * const p_ctrl, uart_info_t * const p_info); +fsp_err_t R_SCI_UART_Close(uart_ctrl_t * const p_ctrl); +fsp_err_t R_SCI_UART_Abort(uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort); +fsp_err_t R_SCI_UART_BaudCalculate(sci_uart_baud_calculation_t const * const p_baud_target, + sci_uart_clock_source_t clock_source, + sci_baud_setting_t * const p_baud_setting); +fsp_err_t R_SCI_UART_CallbackSet(uart_ctrl_t * const p_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void const * const p_context, + uart_callback_args_t * const p_callback_memory); +fsp_err_t R_SCI_UART_ReadStop(uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes); + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_UART) + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h new file mode 100644 index 00000000000..ae4df5d449c --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/R9A07G084.h @@ -0,0 +1,46278 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup R9A07G084 + * @{ + */ + +#ifndef R9A07G084_H + #define R9A07G084_H + + #ifdef __cplusplus +extern "C" { + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ----------------Configuration of the Cortex-M Processor and Core Peripherals---------------- */ + #ifdef RENESAS_CORTEX_M4 + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M0PLUS) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 0 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #include "core_cm0plus.h" /*!< Cortex-M0 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M23) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 0 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #include "core_cm23.h" /*!< Cortex-M23 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_M33) + #define __MPU_PRESENT 1 /*!< MPU present or not */ + #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ + #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #define __VTOR_PRESENT 1 /*!< Vector table VTOR register available or not */ + #define __DSP_PRESENT 1 /*!< DSP present or not */ + #include "core_cm33.h" /*!< Cortex-M33 processor and core peripherals */ + #elif defined(RENESAS_CORTEX_R52) + #define __FPU_PRESENT 1 /*!< FPU present or not */ + #include "core_cr52.h" /*!< Cortex-R52 processor and core peripherals */ + #endif + + #include "system.h" /*!< System */ + + #ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I + #endif + #ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O + #endif + #ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO + #endif + +/* ======================================== Start of section using anonymous unions ======================================== */ + #if defined(__CC_ARM) + #pragma push + #pragma anon_unions + #elif defined(__ICCARM__) + #pragma language=extended + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning 586 + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #else + #warning Not supported compiler type + #endif + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + +/** + * @brief R_CANFD_CFDC [CFDC] (CANFD Channel [0..1] Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel n Nominal Bit Rate Configuration Register */ + + struct + { + __IOM uint32_t NBRP : 10; /*!< [9..0] Nominal Bit Rate Prescaler */ + __IOM uint32_t NSJW : 7; /*!< [16..10] Nominal Bit Rate Resynchronization Jump Width Control */ + __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Nominal Bit Rate Time Segment 1 Control */ + __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Nominal Bit Rate Time Segment 2 Control */ + } NCFG_b; + }; + + union + { + __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel n Control Register */ + + struct + { + __IOM uint32_t CHMDC : 2; /*!< [1..0] Mode Select */ + __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Stop Mode */ + __IOM uint32_t RTBO : 1; /*!< [3..3] Forcible Return from Bus-Off */ + uint32_t : 4; + __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ + __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ + __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ + __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ + __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ + __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ + __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ + __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ + __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission Abort Interrupt Enable */ + __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error Occurrence Counter Overflow Interrupt Enable */ + __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt Enable */ + __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt + * Enable */ + uint32_t : 1; + __IOM uint32_t BOM : 2; /*!< [22..21] Bus-Off Recovery Mode Select */ + __IOM uint32_t ERRD : 1; /*!< [23..23] Error Display Mode Select */ + __IOM uint32_t CTME : 1; /*!< [24..24] Communication Test Mode Enable */ + __IOM uint32_t CTMS : 2; /*!< [26..25] Communication Test Mode Select */ + uint32_t : 3; + __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test Enable */ + __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode Enable */ + } CTR_b; + }; + + union + { + __IOM uint32_t STS; /*!< (@ 0x00000008) Channel n Status Register */ + + struct + { + __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel Reset Status Flag */ + __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel Halt Status Flag */ + __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel Stop Status Flag */ + __IM uint32_t EPSTS : 1; /*!< [3..3] Error Passive Status Flag */ + __IM uint32_t BOSTS : 1; /*!< [4..4] Bus-Off Status Flag */ + __IM uint32_t TRMSTS : 1; /*!< [5..5] Transmit Status Flag */ + __IM uint32_t RECSTS : 1; /*!< [6..6] Receive Status Flag */ + __IM uint32_t COMSTS : 1; /*!< [7..7] Communication Status Flag */ + __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ + uint32_t : 7; + __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ + __IM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ + } STS_b; + }; + + union + { + __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel n Error Flag Register */ + + struct + { + __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ + __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ + __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ + __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ + __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ + __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ + __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ + __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ + __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error Flag */ + __IOM uint32_t FERR : 1; /*!< [9..9] Form Error Flag */ + __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error Flag */ + __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error Flag */ + __IOM uint32_t B1ERR : 1; /*!< [12..12] Recessive Bit Error Flag */ + __IOM uint32_t B0ERR : 1; /*!< [13..13] Dominant Bit Error Flag */ + __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error Flag */ + uint32_t : 1; + __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Calculation Data (CRC length: 15 bits) */ + uint32_t : 1; + } ERFL_b; + }; +} R_CANFD_CFDC_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDC2 [CFDC2] (Channel Configuration Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bit Rate Configuration Register */ + + struct + { + __IOM uint32_t DBRP : 8; /*!< [7..0] Data Bit Rate Prescaler Division Ratio Setting */ + __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Data Bit Rate Time Segment 1 Control */ + uint32_t : 3; + __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Data Bit Rate Time Segment 2 Control */ + uint32_t : 4; + __IOM uint32_t DSJW : 4; /*!< [27..24] Data Bit Rate Resynchronization Jump Width Control */ + uint32_t : 4; + } DCFG_b; + }; + + union + { + __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel n CAN-FD Configuration Register */ + + struct + { + __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ + uint32_t : 5; + __IOM uint32_t TDCOC : 1; /*!< [8..8] Transmitter Delay Compensation Offset Configuration */ + __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ + __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ + uint32_t : 5; + __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ + __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD Multi Gateway Enable */ + __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF Configuration Bit */ + __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS Configuration Bit */ + uint32_t : 1; + __IOM uint32_t FDOE : 1; /*!< [28..28] FD-Only Enable */ + __IOM uint32_t REFE : 1; /*!< [29..29] RX Edge Filter Enable */ + __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN-Only Enable */ + __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD Frame Distinction Enable */ + } FDCFG_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel n CAN-FD Control Register */ + + struct + { + __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ + __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ + uint32_t : 30; + } FDCTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel n CAN-FD Status Register */ + + struct + { + __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ + __IOM uint32_t EOCO : 1; /*!< [8..8] Error Occurrence Counter Overflow Flag */ + __IOM uint32_t SOCO : 1; /*!< [9..9] Successful Occurrence Counter Overflow Flag */ + uint32_t : 5; + __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ + __IM uint32_t EOC : 8; /*!< [23..16] Error Occurrence Counter */ + __IM uint32_t SOC : 8; /*!< [31..24] Successful Occurrence Counter */ + } FDSTS_b; + }; + + union + { + __IM uint32_t FDCRC; /*!< (@ 0x00000010) Channel n CAN-FD CRC Register */ + + struct + { + __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register Value */ + uint32_t : 4; + __IM uint32_t SCNT : 4; /*!< [28..25] Stuff Bit Count */ + uint32_t : 3; + } FDCRC_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel n Bus Load Control Register */ + + struct + { + __IOM uint32_t BLCE : 1; /*!< [0..0] Bus Load Counter Enable */ + uint32_t : 7; + __OM uint32_t BLCLD : 1; /*!< [8..8] Bus Load Counter Load */ + uint32_t : 23; + } BLCT_b; + }; + + union + { + __IM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel n Bus Load Status Register */ + + struct + { + uint32_t : 3; + __IM uint32_t BLC : 29; /*!< [31..3] Bus Load Counter Status */ + } BLSTS_b; + }; +} R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_CANFD_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Register n */ + + struct + { + __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ + __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ + __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ + __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ + } ID_b; + }; + + union + { + __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Register n */ + + struct + { + __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ + __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ + __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ + __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ + } M_b; + }; + + union + { + __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Register + * n */ + + struct + { + __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ + __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing Destination + * 0 */ + __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing Destination + * 1 */ + __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing Destination + * 2 */ + __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ + __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction + * Pointer */ + uint32_t : 2; + __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ + __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer */ + } P0_b; + }; + + union + { + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Register + * n */ + + struct + { + __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 18; + } P1_b; + }; +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + + struct + { + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Bit */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + + struct + { + __IOM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IOM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + + struct + { + __IOM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + union + { + __IM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p + * = 0 to 15, n = 0 to 31) */ + + struct + { + __IM uint32_t RMDB_LL : 8; /*!< [7..0] RX Message Buffer Data Byte (4 * p) */ + __IM uint32_t RMDB_LH : 8; /*!< [15..8] RX Message Buffer Data Byte (4 * p + 1) */ + __IM uint32_t RMDB_HL : 8; /*!< [23..16] RX Message Buffer Data Byte (4 * p + 2) */ + __IM uint32_t RMDB_HH : 8; /*!< [31..24] RX Message Buffer Data Byte (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field p Register n (p + * = 0 to 63, n = 0 to 31) */ + + struct + { + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register n */ + + struct + { + __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR bit */ + __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE bit */ + } ID_b; + }; + + union + { + __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register n */ + + struct + { + __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Value */ + uint32_t : 12; + __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register n */ + + struct + { + __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t CFDRFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ + } FDSTS_b; + }; + + union + { + union + { + __IM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0 + * to 15, n = 0 to 7) */ + + struct + { + __IM uint32_t RFDB_LL : 8; /*!< [7..0] RX FIFO Buffer Data Byte (4 * p) */ + __IM uint32_t RFDB_LH : 8; /*!< [15..8] RX FIFO Buffer Data Byte (4 * p + 1) */ + __IM uint32_t RFDB_HL : 8; /*!< [23..16] RX FIFO Buffer Data Byte (4 * p + 2) */ + __IM uint32_t RFDB_HH : 8; /*!< [31..24] RX FIFO Buffer Data Byte (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field p Register n (p = 0 + * to 63, n = 0 to 7) */ + + struct + { + __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + + struct + { + __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] THL Entry Enable */ + __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR bit */ + __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register n */ + + struct + { + __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Value */ + uint32_t : 12; + __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Control/Status Register + * n */ + + struct + { + __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t CFIFL : 2; /*!< [9..8] COMMON FIFO Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ + } FDCSTS_b; + }; + + union + { + union + { + __IOM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p + * = 0 to 15, n = 0 to 5) */ + + struct + { + __IOM uint32_t CFDB_LL : 8; /*!< [7..0] Common FIFO Buffer Data Bytes (4 * p) */ + __IOM uint32_t CFDB_LH : 8; /*!< [15..8] Common FIFO Buffer Data Bytes (4 * p + 1) */ + __IOM uint32_t CFDB_HL : 8; /*!< [23..16] Common FIFO Buffer Data Bytes (4 * p + 2) */ + __IOM uint32_t CFDB_HH : 8; /*!< [31..24] Common FIFO Buffer Data Bytes (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field p Register n (p + * = 0 to 63, n = 0 to 5) */ + + struct + { + __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Bytes */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) + */ +typedef struct +{ + union + { + __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + + struct + { + __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ + __IM uint32_t BN : 7; /*!< [9..3] Buffer Number */ + uint32_t : 5; + __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer Indication */ + __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ + } ACC0_b; + }; + + union + { + __IM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + + struct + { + __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ + __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ + uint32_t : 14; + } ACC1_b; + }; +} R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register n (n = 0 to 127) */ + + struct + { + __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ + __IOM uint32_t THLEN : 1; /*!< [29..29] Tx History List Entry */ + __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR bit */ + __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE bit */ + } ID_b; + }; + + union + { + __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register n (n = 0 to + * 127) */ + + struct + { + uint32_t : 28; + __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ + } PTR_b; + }; + + union + { + __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register n (n + * = 0 to 127) */ + + struct + { + __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ + uint32_t : 6; + __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ + } FDCTR_b; + }; + + union + { + union + { + __IOM uint32_t DF_WD[16]; /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p + * = 0 to 15, n = 0 to 127) */ + + struct + { + __IOM uint32_t TMDB_LL : 8; /*!< [7..0] TX Message Buffer Data Byte (4 * p) */ + __IOM uint32_t TMDB_LH : 8; /*!< [15..8] TX Message Buffer Data Byte (4 * p + 1) */ + __IOM uint32_t TMDB_HL : 8; /*!< [23..16] TX Message Buffer Data Byte (4 * p + 2) */ + __IOM uint32_t TMDB_HH : 8; /*!< [31..24] TX Message Buffer Data Byte (4 * p + 3) */ + } DF_WD_b[16]; + }; + + union + { + __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field p Register n (p + * = 0 to 63, n = 0 to 5) */ + + struct + { + __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Bytes */ + } DF_b[64]; + }; + }; + __IM uint32_t RESERVED[13]; +} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ + +/** + * @brief R_CMT_UNT_CM [CM] (2 Timer Start Register Pairs) + */ +typedef struct +{ + union + { + __IOM uint16_t CR; /*!< (@ 0x00000000) Compare Match Timer Control Register */ + + struct + { + __IOM uint16_t CKS : 2; /*!< [1..0] Clock Select */ + uint16_t : 4; + __IOM uint16_t CMIE : 1; /*!< [6..6] Compare Match Interrupt Enable */ + uint16_t : 9; + } CR_b; + }; + __IOM uint16_t CNT; /*!< (@ 0x00000002) Compare Match Timer Counter Register */ + __IOM uint16_t COR; /*!< (@ 0x00000004) Compare Match Timer Constant Register */ +} R_CMT_UNT_CM_Type; /*!< Size = 6 (0x6) */ + +/** + * @brief R_CMT_UNT [UNT] (3 Timer Start Register Units) + */ +typedef struct +{ + union + { + __IOM uint16_t CMSTR0; /*!< (@ 0x00000000) Compare Match Timer Start Register */ + + struct + { + __IOM uint16_t STR0 : 1; /*!< [0..0] CMT Channel n Count Start */ + __IOM uint16_t STR1 : 1; /*!< [1..1] CMT Channel n+1 Count Start */ + uint16_t : 14; + } CMSTR0_b; + }; + __IOM R_CMT_UNT_CM_Type CM[2]; /*!< (@ 0x00000002) 2 Timer Start Register Pairs */ + __IM uint16_t RESERVED[505]; +} R_CMT_UNT_Type; /*!< Size = 1024 (0x400) */ + +/** + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + */ +typedef struct +{ + union + { + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L y (y = 0 to 2) */ + + struct + { + __IOM uint8_t SVA0 : 1; /*!< [0..0] 10-bit Address LSB */ + __IOM uint8_t SVA : 7; /*!< [7..1] 7-bit Address/10-bit Address Lower Bits */ + } L_b; + }; + + union + { + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U y (y = 0 to 2) */ + + struct + { + __IOM uint8_t FS : 1; /*!< [0..0] 7-bit/10-bit Address Format Select */ + __IOM uint8_t SVA : 2; /*!< [2..1] 10-bit Address Upper Bits */ + uint8_t : 5; + } U_b; + }; +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ + +/** + * @brief R_DMAC0_GRP_CH_N [N] (DMAC Address Registers [0..1]) + */ +typedef struct +{ + __IOM uint32_t SA; /*!< (@ 0x00000000) Nextm0 Source Address Register n (m = 0, 1) (n + * = 0 to 7) */ + __IOM uint32_t DA; /*!< (@ 0x00000004) Nextm0 Destination Address Register n (m = 0, + * 1) (n = 0 to 7) */ + __IOM uint32_t TB; /*!< (@ 0x00000008) Nextm0 Transaction Byte Register n (m = 0, 1) + * (n = 0 to 7) */ +} R_DMAC0_GRP_CH_N_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_DMAC0_GRP_CH [CH] (DMAC channel Control Register [0..7]) + */ +typedef struct +{ + __IOM R_DMAC0_GRP_CH_N_Type N[2]; /*!< (@ 0x00000000) DMAC Address Registers [0..1] */ + __IM uint32_t CRSA; /*!< (@ 0x00000018) Current Source Address Register n (n = 0 to 7) */ + __IM uint32_t CRDA; /*!< (@ 0x0000001C) Current Destination Address Register n (n = 0 + * to 7) */ + __IM uint32_t CRTB; /*!< (@ 0x00000020) Current Transaction Byte Register n (n = 0 to + * 7) */ + + union + { + __IM uint32_t CHSTAT; /*!< (@ 0x00000024) Channel Status Register n (n = 0 to 7) */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] DMA Activation Enable */ + __IM uint32_t RQST : 1; /*!< [1..1] DMA Transfer Request */ + __IM uint32_t TACT : 1; /*!< [2..2] DMAC Operating Status */ + __IM uint32_t SUS : 1; /*!< [3..3] Suspend */ + __IM uint32_t ER : 1; /*!< [4..4] DMA Error */ + __IM uint32_t END : 1; /*!< [5..5] DMA Transfer Completion Interrupt */ + __IM uint32_t TC : 1; /*!< [6..6] DMA Transfer Completion (total number of data bytes for + * transaction) */ + __IM uint32_t SR : 1; /*!< [7..7] Next Register Select */ + __IM uint32_t DL : 1; /*!< [8..8] Descriptor Load */ + __IM uint32_t DW : 1; /*!< [9..9] Descriptor Write Back */ + __IM uint32_t DER : 1; /*!< [10..10] Descriptor Error */ + __IM uint32_t MODE : 1; /*!< [11..11] DMA Mode */ + uint32_t : 4; + __IM uint32_t INTM : 1; /*!< [16..16] DMA Transfer Completion Interrupt Request Mask */ + uint32_t : 15; + } CHSTAT_b; + }; + + union + { + __IOM uint32_t CHCTRL; /*!< (@ 0x00000028) Channel Control Register n (n = 0 to 7) */ + + struct + { + __IOM uint32_t SETEN : 1; /*!< [0..0] DMA Activation Enable */ + __IOM uint32_t CLREN : 1; /*!< [1..1] DMA Activation Enable Clear */ + __IOM uint32_t STG : 1; /*!< [2..2] Software Trigger */ + __IOM uint32_t SWRST : 1; /*!< [3..3] Software Reset */ + __IOM uint32_t CLRRQ : 1; /*!< [4..4] DMA Transfer Request Clear */ + __IOM uint32_t CLREND : 1; /*!< [5..5] END Clear */ + __IOM uint32_t CLRTC : 1; /*!< [6..6] TC Clear */ + uint32_t : 1; + __IOM uint32_t SETSUS : 1; /*!< [8..8] Suspend Request */ + __IOM uint32_t CLRSUS : 1; /*!< [9..9] Suspend Clear */ + uint32_t : 6; + __IOM uint32_t SETINTM : 1; /*!< [16..16] DMA Transfer Completion Interrupt Request Mask */ + __IOM uint32_t CLRINTM : 1; /*!< [17..17] DMA Transfer Completion Interrupt Request Mask Clear */ + uint32_t : 14; + } CHCTRL_b; + }; + + union + { + __IOM uint32_t CHCFG; /*!< (@ 0x0000002C) Channel Configuration Register n (n = 0 to 7) */ + + struct + { + __IOM uint32_t SEL : 3; /*!< [2..0] Pin Select */ + __IOM uint32_t REQD : 1; /*!< [3..3] DMA Activation Request Source Select */ + __IOM uint32_t LOEN : 1; /*!< [4..4] L Detection Enable */ + __IOM uint32_t HIEN : 1; /*!< [5..5] H Detection Enable */ + __IOM uint32_t LVL : 1; /*!< [6..6] Level Detection Enable */ + uint32_t : 1; + __IOM uint32_t AM : 3; /*!< [10..8] ACK Mode */ + uint32_t : 1; + __IOM uint32_t SDS : 4; /*!< [15..12] Source Data Size */ + __IOM uint32_t DDS : 4; /*!< [19..16] Destination Data Size */ + __IOM uint32_t SAD : 1; /*!< [20..20] Source Address Count Direction */ + __IOM uint32_t DAD : 1; /*!< [21..21] Destination Address Count Direction */ + __IOM uint32_t TM : 1; /*!< [22..22] Transfer Mode */ + uint32_t : 1; + __IOM uint32_t DEM : 1; /*!< [24..24] DMA Transfer Completion Interrupt Mask */ + __IOM uint32_t TCM : 1; /*!< [25..25] TEND Mask */ + uint32_t : 1; + __IOM uint32_t SBE : 1; /*!< [27..27] Buffer Flush Enable */ + __IOM uint32_t RSEL : 1; /*!< [28..28] Next Register Select */ + __IOM uint32_t RSW : 1; /*!< [29..29] RSEL Reverse */ + __IOM uint32_t REN : 1; /*!< [30..30] Register Set Enable */ + __IOM uint32_t DMS : 1; /*!< [31..31] DMA Mode Select */ + } CHCFG_b; + }; + + union + { + __IOM uint32_t CHITVL; /*!< (@ 0x00000030) Channel Interval Register n (n = 0 to 7) */ + + struct + { + __IOM uint32_t ITVL : 16; /*!< [15..0] Interval */ + uint32_t : 16; + } CHITVL_b; + }; + + union + { + __IOM uint32_t CHEXT; /*!< (@ 0x00000034) Channel Extension Register n (n = 0 to 7) */ + + struct + { + __IOM uint32_t SPR : 3; /*!< [2..0] Source PROT */ + uint32_t : 1; + __IOM uint32_t SCA : 4; /*!< [7..4] Source CACHE */ + __IOM uint32_t DPR : 3; /*!< [10..8] Destination PROT */ + uint32_t : 1; + __IOM uint32_t DCA : 4; /*!< [15..12] Destination CACHE */ + uint32_t : 16; + } CHEXT_b; + }; + __IOM uint32_t NXLA; /*!< (@ 0x00000038) Next Link Address Register n (n = 0 to 7) */ + __IM uint32_t CRLA; /*!< (@ 0x0000003C) Current Link Address Register n (n = 0 to 7) */ +} R_DMAC0_GRP_CH_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_DMAC0_GRP [GRP] (8 channel Registers) + */ +typedef struct +{ + __IOM R_DMAC0_GRP_CH_Type CH[8]; /*!< (@ 0x00000000) DMAC channel Control Register [0..7] */ + __IM uint32_t RESERVED[64]; + + union + { + __IOM uint32_t DCTRL; /*!< (@ 0x00000300) DMA Control Register A */ + + struct + { + __IOM uint32_t PR : 1; /*!< [0..0] Priority Control Select */ + __IOM uint32_t LVINT : 1; /*!< [1..1] Sets the interrupt output mode. */ + uint32_t : 30; + } DCTRL_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IM uint32_t DSTAT_EN; /*!< (@ 0x00000310) DMA Status EN Register A */ + + struct + { + __IM uint32_t EN00 : 1; /*!< [0..0] Channel 0 EN */ + __IM uint32_t EN01 : 1; /*!< [1..1] Channel 1 EN */ + __IM uint32_t EN02 : 1; /*!< [2..2] Channel 2 EN */ + __IM uint32_t EN03 : 1; /*!< [3..3] Channel 3 EN */ + __IM uint32_t EN04 : 1; /*!< [4..4] Channel 4 EN */ + __IM uint32_t EN05 : 1; /*!< [5..5] Channel 5 EN */ + __IM uint32_t EN06 : 1; /*!< [6..6] Channel 6 EN */ + __IM uint32_t EN07 : 1; /*!< [7..7] Channel 7 EN */ + uint32_t : 24; + } DSTAT_EN_b; + }; + + union + { + __IM uint32_t DSTAT_ER; /*!< (@ 0x00000314) DMA Status ER Register A */ + + struct + { + __IM uint32_t ER00 : 1; /*!< [0..0] Channel 0 ER */ + __IM uint32_t ER01 : 1; /*!< [1..1] Channel 1 ER */ + __IM uint32_t ER02 : 1; /*!< [2..2] Channel 2 ER */ + __IM uint32_t ER03 : 1; /*!< [3..3] Channel 3 ER */ + __IM uint32_t ER04 : 1; /*!< [4..4] Channel 4 ER */ + __IM uint32_t ER05 : 1; /*!< [5..5] Channel 5 ER */ + __IM uint32_t ER06 : 1; /*!< [6..6] Channel 6 ER */ + __IM uint32_t ER07 : 1; /*!< [7..7] Channel 7 ER */ + uint32_t : 24; + } DSTAT_ER_b; + }; + + union + { + __IM uint32_t DSTAT_END; /*!< (@ 0x00000318) DMA Status END Register A */ + + struct + { + __IM uint32_t END00 : 1; /*!< [0..0] Channel 0 END */ + __IM uint32_t END01 : 1; /*!< [1..1] Channel 1 END */ + __IM uint32_t END02 : 1; /*!< [2..2] Channel 2 END */ + __IM uint32_t END03 : 1; /*!< [3..3] Channel 3 END */ + __IM uint32_t END04 : 1; /*!< [4..4] Channel 4 END */ + __IM uint32_t END05 : 1; /*!< [5..5] Channel 5 END */ + __IM uint32_t END06 : 1; /*!< [6..6] Channel 6 END */ + __IM uint32_t END07 : 1; /*!< [7..7] Channel 7 END */ + uint32_t : 24; + } DSTAT_END_b; + }; + __IM uint32_t RESERVED2; + + union + { + __IM uint32_t DSTAT_SUS; /*!< (@ 0x00000320) DMA Status SUS Register A */ + + struct + { + __IM uint32_t SUS00 : 1; /*!< [0..0] Channel 0 SUS */ + __IM uint32_t SUS01 : 1; /*!< [1..1] Channel 1 SUS */ + __IM uint32_t SUS02 : 1; /*!< [2..2] Channel 2 SUS */ + __IM uint32_t SUS03 : 1; /*!< [3..3] Channel 3 SUS */ + __IM uint32_t SUS04 : 1; /*!< [4..4] Channel 4 SUS */ + __IM uint32_t SUS05 : 1; /*!< [5..5] Channel 5 SUS */ + __IM uint32_t SUS06 : 1; /*!< [6..6] Channel 6 SUS */ + __IM uint32_t SUS07 : 1; /*!< [7..7] Channel 7 SUS */ + uint32_t : 24; + } DSTAT_SUS_b; + }; +} R_DMAC0_GRP_Type; /*!< Size = 804 (0x324) */ + +/** + * @brief R_PORT_DRCTL [DRCTL] (I/O Buffer [0..24] Function Switching Register) + */ +typedef struct +{ + union + { + __IOM uint32_t L; /*!< (@ 0x00000000) I/O Buffer m Function Switching Register 0-3 */ + + struct + { + __IOM uint32_t DRV0 : 2; /*!< [1..0] Pm_0 Driving Ability Control */ + __IOM uint32_t PUD0 : 2; /*!< [3..2] Pm_0 Pull-Up/Down Control */ + __IOM uint32_t SMT0 : 1; /*!< [4..4] Pm_0 Schmitt Trigger Control */ + __IOM uint32_t SR0 : 1; /*!< [5..5] Pm_0 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV1 : 2; /*!< [9..8] Pm_1 Driving Ability Control */ + __IOM uint32_t PUD1 : 2; /*!< [11..10] Pm_1 Pull-Up/Down Control */ + __IOM uint32_t SMT1 : 1; /*!< [12..12] Pm_1 Schmitt Trigger Control */ + __IOM uint32_t SR1 : 1; /*!< [13..13] Pm_1 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV2 : 2; /*!< [17..16] Pm_2 Driving Ability Control */ + __IOM uint32_t PUD2 : 2; /*!< [19..18] Pm_2 Pull-Up/Down Control */ + __IOM uint32_t SMT2 : 1; /*!< [20..20] Pm_2 Schmitt Trigger Control */ + __IOM uint32_t SR2 : 1; /*!< [21..21] Pm_2 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV3 : 2; /*!< [25..24] Pm_3 Driving Ability Control */ + __IOM uint32_t PUD3 : 2; /*!< [27..26] Pm_3 Pull-Up/Down Control */ + __IOM uint32_t SMT3 : 1; /*!< [28..28] Pm_3 Schmitt Trigger Control */ + __IOM uint32_t SR3 : 1; /*!< [29..29] Pm_3 Slew Rate Control */ + uint32_t : 2; + } L_b; + }; + + union + { + __IOM uint32_t H; /*!< (@ 0x00000004) I/O Buffer m Function Switching Register 4-7 */ + + struct + { + __IOM uint32_t DRV4 : 2; /*!< [1..0] Pm_4 Driving Ability Control */ + __IOM uint32_t PUD4 : 2; /*!< [3..2] Pm_4 Pull-Up/Down Control */ + __IOM uint32_t SMT4 : 1; /*!< [4..4] Pm_4 Schmitt Trigger Control */ + __IOM uint32_t SR4 : 1; /*!< [5..5] Pm_4 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV5 : 2; /*!< [9..8] Pm_5 Driving Ability Control */ + __IOM uint32_t PUD5 : 2; /*!< [11..10] Pm_5 Pull-Up/Down Control */ + __IOM uint32_t SMT5 : 1; /*!< [12..12] Pm_5 Schmitt Trigger Control */ + __IOM uint32_t SR5 : 1; /*!< [13..13] Pm_5 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV6 : 2; /*!< [17..16] Pm_6 Driving Ability Control */ + __IOM uint32_t PUD6 : 2; /*!< [19..18] Pm_6 Pull-Up/Down Control */ + __IOM uint32_t SMT6 : 1; /*!< [20..20] Pm_6 Schmitt Trigger Control */ + __IOM uint32_t SR6 : 1; /*!< [21..21] Pm_6 Slew Rate Control */ + uint32_t : 2; + __IOM uint32_t DRV7 : 2; /*!< [25..24] Pm_7 Driving Ability Control */ + __IOM uint32_t PUD7 : 2; /*!< [27..26] Pm_7 Pull-Up/Down Control */ + __IOM uint32_t SMT7 : 1; /*!< [28..28] Pm_7 Schmitt Trigger Control */ + __IOM uint32_t SR7 : 1; /*!< [29..29] Pm_7 Slew Rate Control */ + uint32_t : 2; + } H_b; + }; +} R_PORT_DRCTL_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_PORT_NSR_ELC_PDBF [ELC_PDBF] (ELC Port Buffer Register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint8_t BY; /*!< (@ 0x00000000) ELC Port Buffer Register n */ + + struct + { + __IOM uint8_t PB0 : 1; /*!< [0..0] Port Buffer 0 */ + __IOM uint8_t PB1 : 1; /*!< [1..1] Port Buffer 1 */ + __IOM uint8_t PB2 : 1; /*!< [2..2] Port Buffer 2 */ + __IOM uint8_t PB3 : 1; /*!< [3..3] Port Buffer 3 */ + __IOM uint8_t PB4 : 1; /*!< [4..4] Port Buffer 4 */ + __IOM uint8_t PB5 : 1; /*!< [5..5] Port Buffer 5 */ + __IOM uint8_t PB6 : 1; /*!< [6..6] Port Buffer 6 */ + __IOM uint8_t PB7 : 1; /*!< [7..7] Port Buffer 7 */ + } BY_b; + }; + __IM uint8_t RESERVED[3]; +} R_PORT_NSR_ELC_PDBF_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_ETHSW_PTP_SWTM [SWTM] (Ethernet Switch Timer output pins 0-3 Registers) + */ +typedef struct +{ + union + { + __IOM uint32_t EN; /*!< (@ 0x00000000) PTP Timer Pulse Output Enable n Register */ + + struct + { + __IOM uint32_t OUTEN : 1; /*!< [0..0] Enable ETHSW_PTPOUTn Signal Output */ + uint32_t : 31; + } EN_b; + }; + + union + { + __IOM uint32_t STSEC; /*!< (@ 0x00000004) PTP Timer Pulse Start Second n Register */ + + struct + { + __IOM uint32_t STSEC : 32; /*!< [31..0] STSEC */ + } STSEC_b; + }; + + union + { + __IOM uint32_t STNS; /*!< (@ 0x00000008) PTP Timer Pulse Start Nanosecond n Register */ + + struct + { + __IOM uint32_t STNS : 32; /*!< [31..0] Start Time by Nanosecond */ + } STNS_b; + }; + + union + { + __IOM uint32_t PSEC; /*!< (@ 0x0000000C) PTP Timer Pulse Period Second n Register */ + + struct + { + __IOM uint32_t PSEC : 32; /*!< [31..0] PSEC */ + } PSEC_b; + }; + + union + { + __IOM uint32_t PNS; /*!< (@ 0x00000010) PTP Timer Pulse Period Nanosecond n Register */ + + struct + { + __IOM uint32_t PNS : 32; /*!< [31..0] Period by Nanosecond */ + } PNS_b; + }; + + union + { + __IOM uint32_t WTH; /*!< (@ 0x00000014) PTP Timer Pulse Width n Register */ + + struct + { + __IOM uint32_t WIDTH : 16; /*!< [15..0] Set the Pulse Width of ETHSW_PTPOUTn in the cycle number + * of ts_clk (8 ns). */ + uint32_t : 16; + } WTH_b; + }; + + union + { + __IOM uint32_t MAXP; /*!< (@ 0x00000018) PTP Timer Pulse Max Second n Register */ + + struct + { + __IOM uint32_t MAXP : 32; /*!< [31..0] Sets the boundary value in nanoseconds to carry from + * the nanosecond field to the second field. The same value + * as ATIME_EVT_PERIOD register must be set. */ + } MAXP_b; + }; + + union + { + __IOM uint32_t LATSEC; /*!< (@ 0x0000001C) PTP Timer Pulse Latch Second n Register */ + + struct + { + __IOM uint32_t LATSEC : 32; /*!< [31..0] LATSEC */ + } LATSEC_b; + }; + + union + { + __IOM uint32_t LATNS; /*!< (@ 0x00000020) PTP Timer Pulse Latch Nanosecond n Register */ + + struct + { + __IOM uint32_t LATNS : 32; /*!< [31..0] LATNS */ + } LATNS_b; + }; + __IM uint32_t RESERVED[55]; +} R_ETHSW_PTP_SWTM_Type; /*!< Size = 256 (0x100) */ + +/** + * @brief R_ETHSW_MGMT_ADDR [MGMT_ADDR] (MAC Address [0..3] for Bridge Protocol Frame Register) + */ +typedef struct +{ + union + { + __IOM uint32_t lo; /*!< (@ 0x00000000) Lower MAC Address */ + + struct + { + __IOM uint32_t BPDU_DST : 32; /*!< [31..0] Additional MAC address defining a Bridge Protocol Frame + * (BPDU) in addition to the commonly-known addresses */ + } lo_b; + }; + + union + { + __IOM uint32_t hi; /*!< (@ 0x00000004) Higher MAC Address */ + + struct + { + __IOM uint32_t BPDU_DST : 16; /*!< [15..0] Bits [7:0] is 5th byte, bits [15:8] is 6th (last) byte */ + __IOM uint32_t MASK : 8; /*!< [23..16] 8-bit mask for comparing the last byte of the MAC address. */ + uint32_t : 8; + } hi_b; + }; +} R_ETHSW_MGMT_ADDR_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_ESC_FMMU [FMMU] (FMMU [0..7] Registers (n = 0 to 7)) + */ +typedef struct +{ + union + { + __IM uint32_t L_START_ADR; /*!< (@ 0x00000000) FMMU Logical Start Address n Register (n = 0 + * to 7) */ + + struct + { + __IM uint32_t LSTAADR : 32; /*!< [31..0] Logical Start Address Setting */ + } L_START_ADR_b; + }; + + union + { + __IM uint16_t LEN; /*!< (@ 0x00000004) FMMU Length n Register (n = 0 to 7) */ + + struct + { + __IM uint16_t FMMULEN : 16; /*!< [15..0] Area Size Specification */ + } LEN_b; + }; + + union + { + __IM uint8_t L_START_BIT; /*!< (@ 0x00000006) FMMU Logical Start Bit n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t LSTABIT : 3; /*!< [2..0] Start Bit Setting */ + uint8_t : 5; + } L_START_BIT_b; + }; + + union + { + __IM uint8_t L_STOP_BIT; /*!< (@ 0x00000007) FMMU Logical Stop Bit n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t LSTPBIT : 3; /*!< [2..0] Last Bit Setting */ + uint8_t : 5; + } L_STOP_BIT_b; + }; + + union + { + __IM uint16_t P_START_ADR; /*!< (@ 0x00000008) FMMU Physical Start Address n Register (n = 0 + * to 7) */ + + struct + { + __IM uint16_t PHYSTAADR : 16; /*!< [15..0] Physical Start Address Setting */ + } P_START_ADR_b; + }; + + union + { + __IM uint8_t P_START_BIT; /*!< (@ 0x0000000A) FMMU Physical Start Bit n Register (n = 0 to + * 7) */ + + struct + { + __IM uint8_t PHYSTABIT : 3; /*!< [2..0] Physical Start Bit Setting */ + uint8_t : 5; + } P_START_BIT_b; + }; + + union + { + __IM uint8_t TYPE; /*!< (@ 0x0000000B) FMMU Type n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t READ : 1; /*!< [0..0] Read Access Mapping Setting */ + __IM uint8_t WRITE : 1; /*!< [1..1] Write Access Mapping Setting */ + uint8_t : 6; + } TYPE_b; + }; + + union + { + __IM uint8_t ACT; /*!< (@ 0x0000000C) FMMU Activate n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t ACTIVATE : 1; /*!< [0..0] FMMU Enable/Disable */ + uint8_t : 7; + } ACT_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; +} R_ESC_FMMU_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_ESC_SM [SM] (SyncManager [0..7] Registers (n = 0 to 7)) + */ +typedef struct +{ + union + { + __IM uint16_t P_START_ADR; /*!< (@ 0x00000000) SyncManager Physical Start Address n Register + * (n = 0 to 7) */ + + struct + { + __IM uint16_t SMSTAADDR : 16; /*!< [15..0] Physical Start Address Setting */ + } P_START_ADR_b; + }; + + union + { + __IM uint16_t LEN; /*!< (@ 0x00000002) SyncManager Length n Register (n = 0 to 7) */ + + struct + { + __IM uint16_t SMLEN : 16; /*!< [15..0] Area Size Setting */ + } LEN_b; + }; + + union + { + __IM uint8_t CONTROL; /*!< (@ 0x00000004) SyncManager Control n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t OPEMODE : 2; /*!< [1..0] Operating Mode Setting */ + __IM uint8_t DIR : 2; /*!< [3..2] Transfer Direction Setting */ + __IM uint8_t IRQECAT : 1; /*!< [4..4] ECAT Event Interrupt Setting */ + __IM uint8_t IRQPDI : 1; /*!< [5..5] AL Event Interrupt Setting */ + __IM uint8_t WDTRGEN : 1; /*!< [6..6] Watchdog Trigger Setting */ + uint8_t : 1; + } CONTROL_b; + }; + + union + { + __IM uint8_t STATUS; /*!< (@ 0x00000005) SyncManager Status n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t INTWR : 1; /*!< [0..0] Write Complete Interrupt State Indication */ + __IM uint8_t INTRD : 1; /*!< [1..1] Read Complete Interrupt State Indication */ + uint8_t : 1; + __IM uint8_t MAILBOX : 1; /*!< [3..3] Mailbox Status Indication */ + __IM uint8_t BUFFERED : 2; /*!< [5..4] Buffer Status Indication */ + __IM uint8_t RDBUF : 1; /*!< [6..6] Read State Indication */ + __IM uint8_t WRBUF : 1; /*!< [7..7] Write State Indication */ + } STATUS_b; + }; + + union + { + __IM uint8_t ACT; /*!< (@ 0x00000006) SyncManager Activate n Register (n = 0 to 7) */ + + struct + { + __IM uint8_t SMEN : 1; /*!< [0..0] SyncManager Enable/Disable */ + __IM uint8_t REPEATREQ : 1; /*!< [1..1] Repeat Request */ + uint8_t : 4; + __IM uint8_t LATCHECAT : 1; /*!< [6..6] ECAT Latch Event Specification */ + __IM uint8_t LATCHPDI : 1; /*!< [7..7] PDI Latch Event Specification */ + } ACT_b; + }; + + union + { + __IOM uint8_t PDI_CONT; /*!< (@ 0x00000007) SyncManager PDI Control n Register (n = 0 to + * 7) */ + + struct + { + __IOM uint8_t DEACTIVE : 1; /*!< [0..0] SyncManager Operation Indication/Setting */ + __IOM uint8_t REPEATACK : 1; /*!< [1..1] Repeat Acknowledge */ + uint8_t : 6; + } PDI_CONT_b; + }; +} R_ESC_SM_Type; /*!< Size = 8 (0x8) */ + +/** + * @brief R_USBF_PIPE_TR [PIPE_TR] (PIPEn Transaction Counter Registers (n=1-5)) + */ +typedef struct +{ + union + { + __IOM uint16_t E; /*!< (@ 0x00000000) PIPEn Transaction Counter Enable Register */ + + struct + { + uint16_t : 8; + __IOM uint16_t TRCLR : 1; /*!< [8..8] Transaction Counter Clear */ + __IOM uint16_t TRENB : 1; /*!< [9..9] Transaction Counter Enable */ + uint16_t : 6; + } E_b; + }; + + union + { + __IOM uint16_t N; /*!< (@ 0x00000002) PIPEn Transaction Counter Register */ + + struct + { + __IOM uint16_t TRNCNT : 16; /*!< [15..0] Transaction Counter */ + } N_b; + }; +} R_USBF_PIPE_TR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_USBF_CHa_N [N] (Address Registers n (n=0-1)) + */ +typedef struct +{ + union + { + __IOM uint32_t SA; /*!< (@ 0x00000000) Next Source Address Register */ + + struct + { + __IOM uint32_t SAWD : 32; /*!< [31..0] Source Address or Write Data */ + } SA_b; + }; + + union + { + __IOM uint32_t DA; /*!< (@ 0x00000004) Next Destination Address Register */ + + struct + { + __IOM uint32_t DA : 32; /*!< [31..0] Destination Address */ + } DA_b; + }; + + union + { + __IOM uint32_t TB; /*!< (@ 0x00000008) Next Transaction Byte Register */ + + struct + { + __IOM uint32_t TB : 32; /*!< [31..0] Transaction Byte */ + } TB_b; + }; +} R_USBF_CHa_N_Type; /*!< Size = 12 (0xc) */ + +/** + * @brief R_USBF_CHa [CHa] (Next Register Set) + */ +typedef struct +{ + __IOM R_USBF_CHa_N_Type N[2]; /*!< (@ 0x00000000) Address Registers n (n=0-1) */ + + union + { + __IM uint32_t CRSA; /*!< (@ 0x00000018) Current Source Address Register */ + + struct + { + __IM uint32_t CRSA : 32; /*!< [31..0] Source Address */ + } CRSA_b; + }; + + union + { + __IM uint32_t CRDA; /*!< (@ 0x0000001C) Current Destination Address Register */ + + struct + { + __IM uint32_t CRDA : 32; /*!< [31..0] Destination Address */ + } CRDA_b; + }; + + union + { + __IM uint32_t CRTB; /*!< (@ 0x00000020) Current Transaction Byte Register */ + + struct + { + __IM uint32_t CRTB : 32; /*!< [31..0] Transaction Byte */ + } CRTB_b; + }; + + union + { + __IM uint32_t CHSTAT; /*!< (@ 0x00000024) Channel Status Register */ + + struct + { + __IM uint32_t EN : 1; /*!< [0..0] Enable */ + __IM uint32_t RQST : 1; /*!< [1..1] Request */ + __IM uint32_t TACT : 1; /*!< [2..2] Transaction Active */ + __IM uint32_t SUS : 1; /*!< [3..3] Suspend */ + __IM uint32_t ER : 1; /*!< [4..4] Error */ + __IM uint32_t END : 1; /*!< [5..5] USB_FDMAn Interrupted */ + __IM uint32_t TC : 1; /*!< [6..6] Terminal Count */ + __IM uint32_t SR : 1; /*!< [7..7] Selected Register Set */ + __IM uint32_t DL : 1; /*!< [8..8] Descriptor Load */ + __IM uint32_t DW : 1; /*!< [9..9] Descriptor WriteBack */ + __IM uint32_t DER : 1; /*!< [10..10] Descriptor Error */ + __IM uint32_t MODE : 1; /*!< [11..11] DMA Mode */ + uint32_t : 4; + __IM uint32_t INTM : 1; /*!< [16..16] Interrupt Mask */ + __IM uint32_t DMARQM : 1; /*!< [17..17] DMAREQ Mask */ + __IM uint32_t SWPRQ : 1; /*!< [18..18] Sweep Request */ + uint32_t : 5; + __IM uint32_t DNUM : 8; /*!< [31..24] Data Number */ + } CHSTAT_b; + }; + + union + { + __OM uint32_t CHCTRL; /*!< (@ 0x00000028) Channel Control Register */ + + struct + { + __OM uint32_t SETEN : 1; /*!< [0..0] Set Enable */ + __OM uint32_t CLREN : 1; /*!< [1..1] Clear Enable */ + __OM uint32_t STG : 1; /*!< [2..2] Software Trigger */ + __OM uint32_t SWRST : 1; /*!< [3..3] Software Reset */ + __OM uint32_t CLRRQ : 1; /*!< [4..4] Clear Request */ + __OM uint32_t CLREND : 1; /*!< [5..5] Clear End */ + __OM uint32_t CLRTC : 1; /*!< [6..6] Clear TC */ + __OM uint32_t CLRDER : 1; /*!< [7..7] Clear DER */ + __OM uint32_t SETSUS : 1; /*!< [8..8] Set Suspend */ + __OM uint32_t CLRSUS : 1; /*!< [9..9] Clear Suspend */ + uint32_t : 2; + __OM uint32_t SETREN : 1; /*!< [12..12] Set Register Set Enable */ + uint32_t : 1; + __OM uint32_t SETSSWPRQ : 1; /*!< [14..14] Set Software Sweep Request */ + uint32_t : 1; + __OM uint32_t SETINTM : 1; /*!< [16..16] Set Interrupt Mask */ + __OM uint32_t CLRINTM : 1; /*!< [17..17] Clear Interrupt Mask */ + __OM uint32_t SETDMARQM : 1; /*!< [18..18] SET DMAREQ Mask */ + __OM uint32_t CLRDMARQM : 1; /*!< [19..19] Clear DMAREQ Mask */ + uint32_t : 12; + } CHCTRL_b; + }; + + union + { + __IOM uint32_t CHCFG; /*!< (@ 0x0000002C) Channel Configuration Register */ + + struct + { + __IOM uint32_t SEL : 1; /*!< [0..0] Terminal Select */ + uint32_t : 2; + __IOM uint32_t REQD : 1; /*!< [3..3] Request Direction */ + __IOM uint32_t LOEN : 1; /*!< [4..4] Sets the transfer request signal between the USB control + * and the DMAC. */ + __IOM uint32_t HIEN : 1; /*!< [5..5] Sets the transfer request signal between the USB control + * and the DMAC. */ + __IOM uint32_t LVL : 1; /*!< [6..6] Sets the transfer request signal between the USB control + * and the DMAC. */ + uint32_t : 1; + __IOM uint32_t AM : 3; /*!< [10..8] These bits set the transfer request signal between the + * USB control and the DMAC. */ + __IOM uint32_t DRRP : 1; /*!< [11..11] Descriptor Read Repeat */ + __IOM uint32_t SDS : 4; /*!< [15..12] Source Data Size */ + __IOM uint32_t DDS : 4; /*!< [19..16] Destination Data Size */ + __IOM uint32_t SAD : 1; /*!< [20..20] Source Address Direction */ + __IOM uint32_t DAD : 1; /*!< [21..21] Destination Address Direction */ + __IOM uint32_t TM : 1; /*!< [22..22] Sets the transfer request signal between the USB control + * and the DMAC. */ + __IOM uint32_t WONLY : 1; /*!< [23..23] Write Only Mode */ + __IOM uint32_t DEM : 1; /*!< [24..24] USB_FDMAn Mask */ + uint32_t : 1; + __IOM uint32_t DIM : 1; /*!< [26..26] Descriptor Interrupt Mask */ + __IOM uint32_t SBE : 1; /*!< [27..27] Sweep Buffer Enable */ + __IOM uint32_t RSEL : 1; /*!< [28..28] Register Set Select */ + __IOM uint32_t RSW : 1; /*!< [29..29] Register Select Switch */ + __IOM uint32_t REN : 1; /*!< [30..30] Register Set Enable */ + __IOM uint32_t DMS : 1; /*!< [31..31] DMA Mode Select */ + } CHCFG_b; + }; + + union + { + __IOM uint32_t CHITVL; /*!< (@ 0x00000030) Channel Interval Register */ + + struct + { + __IOM uint32_t ITVL : 16; /*!< [15..0] Interval */ + uint32_t : 16; + } CHITVL_b; + }; + + union + { + __IOM uint32_t CHEXT; /*!< (@ 0x00000034) Channel Extension Register */ + + struct + { + __IOM uint32_t SPR : 4; /*!< [3..0] Source PROT */ + uint32_t : 4; + __IOM uint32_t DPR : 4; /*!< [11..8] Destination PROT */ + uint32_t : 20; + } CHEXT_b; + }; + + union + { + __IOM uint32_t NXLA; /*!< (@ 0x00000038) Next Link Address Register */ + + struct + { + __IOM uint32_t NXLA : 32; /*!< [31..0] Next Link Address */ + } NXLA_b; + }; + + union + { + __IM uint32_t CRLA; /*!< (@ 0x0000003C) Current Link Address Register */ + + struct + { + __IM uint32_t CRLA : 32; /*!< [31..0] Current Link Address */ + } CRLA_b; + }; +} R_USBF_CHa_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_USBF_CHb [CHb] (Skip Register Set) + */ +typedef struct +{ + union + { + __IOM uint32_t SCNT; /*!< (@ 0x00000000) Source Continuous Register */ + + struct + { + __IOM uint32_t SCNT : 32; /*!< [31..0] Source Continuous */ + } SCNT_b; + }; + + union + { + __IOM uint32_t SSKP; /*!< (@ 0x00000004) Source Skip Register */ + + struct + { + __IOM uint32_t SSKP : 32; /*!< [31..0] Source Skip */ + } SSKP_b; + }; + + union + { + __IOM uint32_t DCNT; /*!< (@ 0x00000008) Destination Continuous Register */ + + struct + { + __IOM uint32_t DCNT : 32; /*!< [31..0] Destination Continuous */ + } DCNT_b; + }; + + union + { + __IOM uint32_t DSKP; /*!< (@ 0x0000000C) Destination Skip Register */ + + struct + { + __IOM uint32_t DSKP : 32; /*!< [31..0] Destination Skip */ + } DSKP_b; + }; + __IM uint32_t RESERVED[4]; +} R_USBF_CHb_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_XSPI0_CSa [CSa] (xSPI Command Map Configuration Register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint32_t CMCFG0; /*!< (@ 0x00000000) xSPI Command Map Configuration Register 0 CSn */ + + struct + { + __IOM uint32_t FFMT : 2; /*!< [1..0] Frame format */ + __IOM uint32_t ADDSIZE : 2; /*!< [3..2] Address size */ + uint32_t : 12; + __IOM uint32_t ADDRPEN : 8; /*!< [23..16] Address Replace Enable */ + __IOM uint32_t ADDRPCD : 8; /*!< [31..24] Address Replace Code */ + } CMCFG0_b; + }; + + union + { + __IOM uint32_t CMCFG1; /*!< (@ 0x00000004) xSPI Command Map Configuration Register 1 CSn */ + + struct + { + __IOM uint32_t RDCMD : 16; /*!< [15..0] Read command */ + __IOM uint32_t RDLATE : 5; /*!< [20..16] Read latency cycle */ + uint32_t : 11; + } CMCFG1_b; + }; + + union + { + __IOM uint32_t CMCFG2; /*!< (@ 0x00000008) xSPI Command Map Configuration Register 2 CSn */ + + struct + { + __IOM uint32_t WRCMD : 16; /*!< [15..0] Write command */ + __IOM uint32_t WRLATE : 5; /*!< [20..16] Write latency cycle */ + uint32_t : 11; + } CMCFG2_b; + }; + __IM uint32_t RESERVED; +} R_XSPI0_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_BUF [BUF] (xSPI Command Manual Buf [0..3]) + */ +typedef struct +{ + union + { + __IOM uint32_t CDT; /*!< (@ 0x00000000) xSPI Command Manual Type Buf */ + + struct + { + __IOM uint32_t CMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t ADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t DATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + __IOM uint32_t LATE : 5; /*!< [13..9] Latency cycle */ + uint32_t : 1; + __IOM uint32_t TRTYPE : 1; /*!< [15..15] Transaction Type */ + __IOM uint32_t CMD : 16; /*!< [31..16] Command (1-2 bytes) */ + } CDT_b; + }; + + union + { + __IOM uint32_t CDA; /*!< (@ 0x00000004) xSPI Command Manual Address Buf */ + + struct + { + __IOM uint32_t ADD : 32; /*!< [31..0] Address */ + } CDA_b; + }; + + union + { + __IOM uint32_t CDD0; /*!< (@ 0x00000008) xSPI Command Manual Data 0 Buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD0_b; + }; + + union + { + __IOM uint32_t CDD1; /*!< (@ 0x0000000C) xSPI Command Manual Data 1 Buf */ + + struct + { + __IOM uint32_t DATA : 32; /*!< [31..0] Write/Read Data */ + } CDD1_b; + }; +} R_XSPI0_BUF_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_XSPI0_CSb [CSb] (xSPI Command Calibration Control register [0..1]) + */ +typedef struct +{ + union + { + __IOM uint32_t CCCTL0; /*!< (@ 0x00000000) xSPI Command Calibration Control Register 0 CSn */ + + struct + { + __IOM uint32_t CAEN : 1; /*!< [0..0] Automatic Calibration Enable */ + __IOM uint32_t CANOWR : 1; /*!< [1..1] Calibration no write mode */ + uint32_t : 6; + __IOM uint32_t CAITV : 5; /*!< [12..8] Calibration interval */ + uint32_t : 3; + __IOM uint32_t CASFTSTA : 5; /*!< [20..16] Calibration DS shift start value */ + uint32_t : 3; + __IOM uint32_t CASFTEND : 5; /*!< [28..24] Calibration DS shift end value */ + uint32_t : 3; + } CCCTL0_b; + }; + + union + { + __IOM uint32_t CCCTL1; /*!< (@ 0x00000004) xSPI Command Calibration Control Register 1 CSn */ + + struct + { + __IOM uint32_t CACMDSIZE : 2; /*!< [1..0] Command Size */ + __IOM uint32_t CAADDSIZE : 3; /*!< [4..2] Address size */ + __IOM uint32_t CADATASIZE : 4; /*!< [8..5] Write/Read Data Size */ + uint32_t : 7; + __IOM uint32_t CAWRLATE : 5; /*!< [20..16] Write Latency cycle */ + uint32_t : 3; + __IOM uint32_t CARDLATE : 5; /*!< [28..24] Read Latency cycle */ + uint32_t : 3; + } CCCTL1_b; + }; + + union + { + __IOM uint32_t CCCTL2; /*!< (@ 0x00000008) xSPI Command Calibration Control Register 2 CSn */ + + struct + { + __IOM uint32_t CAWRCMD : 16; /*!< [15..0] Calibration pattern write command */ + __IOM uint32_t CARDCMD : 16; /*!< [31..16] Calibration pattern read command */ + } CCCTL2_b; + }; + + union + { + __IOM uint32_t CCCTL3; /*!< (@ 0x0000000C) xSPI Command Calibration Control Register 3 CSn */ + + struct + { + __IOM uint32_t CAADD : 32; /*!< [31..0] Calibration pattern address */ + } CCCTL3_b; + }; + + union + { + __IOM uint32_t CCCTL4; /*!< (@ 0x00000010) xSPI Command Calibration Control Register 4 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL4_b; + }; + + union + { + __IOM uint32_t CCCTL5; /*!< (@ 0x00000014) xSPI Command Calibration Control Register 5 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL5_b; + }; + + union + { + __IOM uint32_t CCCTL6; /*!< (@ 0x00000018) xSPI Command Calibration Control Register 6 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL6_b; + }; + + union + { + __IOM uint32_t CCCTL7; /*!< (@ 0x0000001C) xSPI Command Calibration Control Register 7 CSn */ + + struct + { + __IOM uint32_t CADATA : 32; /*!< [31..0] Calibration pattern data */ + } CCCTL7_b; + }; +} R_XSPI0_CSb_Type; /*!< Size = 32 (0x20) */ + +/** + * @brief R_SYSRAM0_W [W] (System SRAM Wn Registers (n = 0 to 3)) + */ +typedef struct +{ + union + { + __IOM uint32_t EC710CTL; /*!< (@ 0x00000000) ECC Control Register */ + + struct + { + __IM uint32_t ECEMF : 1; /*!< [0..0] ECC Error Indicate Flag */ + __IM uint32_t ECER1F : 1; /*!< [1..1] 1-Bit ECC Error Detection/Correction Flag */ + __IM uint32_t ECER2F : 1; /*!< [2..2] 2-Bit ECC Error Detection Flag */ + __IOM uint32_t EC1EDIC : 1; /*!< [3..3] 1-Bit ECC Error Detection Interrupt Control */ + __IOM uint32_t EC2EDIC : 1; /*!< [4..4] 2-Bit ECC Error Detection Interrupt Control */ + __IOM uint32_t EC1ECP : 1; /*!< [5..5] 1-Bit ECC Error Correction Enable */ + __IOM uint32_t ECERVF : 1; /*!< [6..6] ECC Error Determination Enable */ + __IOM uint32_t ECTHM : 1; /*!< [7..7] ECC Function Through Mode Enable */ + uint32_t : 1; + __IOM uint32_t ECER1C : 1; /*!< [9..9] 1-Bit ECC Error Detection Clear */ + __IOM uint32_t ECER2C : 1; /*!< [10..10] 2-Bit ECC Error Detection Clear */ + __IM uint32_t ECOVFF : 1; /*!< [11..11] ECC Error Address Capture Overflow Flag */ + uint32_t : 2; + __IOM uint32_t EMCA : 2; /*!< [15..14] Access Control to ECC Mode Selection */ + __IM uint32_t ECEDF0 : 2; /*!< [17..16] ECC Error Address Capture Flag m (m = 0) */ + __IM uint32_t ECEDF1 : 2; /*!< [19..18] ECC Error Address Capture Flag m (m = 1) */ + __IM uint32_t ECEDF2 : 2; /*!< [21..20] ECC Error Address Capture Flag m (m = 2) */ + __IM uint32_t ECEDF3 : 2; /*!< [23..22] ECC Error Address Capture Flag m (m = 3) */ + __IM uint32_t ECEDF4 : 2; /*!< [25..24] ECC Error Address Capture Flag m (m = 4) */ + __IM uint32_t ECEDF5 : 2; /*!< [27..26] ECC Error Address Capture Flag m (m = 5) */ + __IM uint32_t ECEDF6 : 2; /*!< [29..28] ECC Error Address Capture Flag m (m = 6) */ + __IM uint32_t ECEDF7 : 2; /*!< [31..30] ECC Error Address Capture Flag m (m = 7) */ + } EC710CTL_b; + }; + + union + { + __IOM uint32_t EC710TMC; /*!< (@ 0x00000004) ECC Test Mode Control Register */ + + struct + { + __IOM uint32_t ECREIS : 1; /*!< [0..0] ECC Redundancy Bit Input Data Select */ + __IOM uint32_t ECDCS : 1; /*!< [1..1] ECC Decode Input Select */ + __IOM uint32_t ECENS : 1; /*!< [2..2] ECC Encode Input Select */ + __IOM uint32_t ECREOS : 1; /*!< [3..3] ECC Redundancy Bit Output Data Select */ + __IOM uint32_t ECTRRS : 1; /*!< [4..4] RAM Read Test Mode Select */ + uint32_t : 2; + __IOM uint32_t ECTMCE : 1; /*!< [7..7] Test Mode Enable */ + uint32_t : 6; + __IOM uint32_t ETMA : 2; /*!< [15..14] ECTMCE Write Enable */ + uint32_t : 16; + } EC710TMC_b; + }; + + union + { + __IOM uint32_t EC710TRC; /*!< (@ 0x00000008) ECC Redundancy Bit Data Control Test Register */ + + struct + { + __IOM uint32_t ECERDB : 7; /*!< [6..0] ECC Redundancy Bit Input/Output Substitute Buffer Register */ + uint32_t : 1; + __IM uint32_t ECECRD : 7; /*!< [14..8] ECC Encode Test Register */ + uint32_t : 1; + __IM uint32_t ECHORD : 7; /*!< [22..16] ECC 7-Redundancy-Bit Data Retain Test Register */ + uint32_t : 1; + __IM uint32_t ECSYND : 7; /*!< [30..24] ECC Decode Syndrome Register */ + uint32_t : 1; + } EC710TRC_b; + }; + + union + { + __IOM uint32_t EC710TED; /*!< (@ 0x0000000C) ECC Encode/Decode Input/Output Switchover Test + * Register */ + + struct + { + __IOM uint32_t ECEDB : 32; /*!< [31..0] 32-Bit Data Test Register for ECC Encode/Decode */ + } EC710TED_b; + }; + + union + { + __IM uint32_t EC710EAD[8]; /*!< (@ 0x00000010) ECC Error Address [0..7] Register 0 */ + + struct + { + __IM uint32_t ECEAD : 15; /*!< [14..0] Bit Error Address */ + uint32_t : 17; + } EC710EAD_b[8]; + }; + __IM uint32_t RESERVED[4]; +} R_SYSRAM0_W_Type; /*!< Size = 64 (0x40) */ + +/** + * @brief R_MPU0_RGN [RGN] (Master MPU Safety Region Start Address Register [0..7]) + */ +typedef struct +{ + union + { + __IOM uint32_t STADD; /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register */ + + struct + { + __IOM uint32_t RDPR : 1; /*!< [0..0] Enable read protection for region m of master MPU */ + __IOM uint32_t WRPR : 1; /*!< [1..1] Enable write protection for region m of master MPU */ + uint32_t : 8; + __IOM uint32_t STADDR : 22; /*!< [31..10] Start address for MPU region */ + } STADD_b; + }; + + union + { + __IOM uint32_t ENDADD; /*!< (@ 0x00000004) Master MPU Safety Region End Address Register */ + + struct + { + uint32_t : 10; + __IOM uint32_t ENDADDR : 22; /*!< [31..10] End address for MPU region */ + } ENDADD_b; + }; + __IM uint32_t RESERVED[2]; +} R_MPU0_RGN_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_DSMIF0_CH [CH] (Channel Registers [0..2]) + */ +typedef struct +{ + union + { + __IOM uint32_t DSICR; /*!< (@ 0x00000000) Interrupt Control Register */ + + struct + { + __IOM uint32_t IOEL : 1; /*!< [0..0] Overcurrent lower limit detection interrupt enable */ + __IOM uint32_t IOEH : 1; /*!< [1..1] Overcurrent upper limit exceeded output interrupt enable */ + __IOM uint32_t ISE : 1; /*!< [2..2] Short circuit detection error interrupt enable */ + __IOM uint32_t IUE : 1; /*!< [3..3] Current data register update interrupt enable */ + uint32_t : 28; + } DSICR_b; + }; + + union + { + __IOM uint32_t DSCMCCR; /*!< (@ 0x00000004) Current Measurement Clock Control Register */ + + struct + { + __IOM uint32_t CKDIR : 1; /*!< [0..0] A/D conversion clock master/slave switching */ + uint32_t : 6; + __IOM uint32_t SEDGE : 1; /*!< [7..7] Sampling edge selection */ + __IOM uint32_t CKDIV : 6; /*!< [13..8] A/D conversion clock division ratio */ + uint32_t : 18; + } DSCMCCR_b; + }; + + union + { + __IOM uint32_t DSCMFCR; /*!< (@ 0x00000008) Current Measurement Filter Control Register */ + + struct + { + __IOM uint32_t CMSINC : 2; /*!< [1..0] Current measurement filter order setting */ + uint32_t : 6; + __IOM uint32_t CMDEC : 8; /*!< [15..8] Decimation ratio selection for current measurement */ + __IOM uint32_t CMSH : 5; /*!< [20..16] Data shift setting for current measurement */ + uint32_t : 11; + } DSCMFCR_b; + }; + + union + { + __IOM uint32_t DSCMCTCR; /*!< (@ 0x0000000C) Current Measurement Capture Trigger Control Register */ + + struct + { + __IOM uint32_t CTSELA : 3; /*!< [2..0] Current capture trigger A selection bit */ + uint32_t : 5; + __IOM uint32_t CTSELB : 3; /*!< [10..8] Current capture trigger B selection bit */ + uint32_t : 5; + __IOM uint32_t DITSEL : 2; /*!< [17..16] Current measurement filter initialization trigger selection + * bit for frequency division counter for decimation. */ + uint32_t : 5; + __IOM uint32_t DEDGE : 1; /*!< [23..23] Current measurement filter initialization trigger for + * division counter for decimation edge selection bit. The + * trigger from ELC is usually used positive edge. Change + * from the initial value if necessary. */ + uint32_t : 8; + } DSCMCTCR_b; + }; + + union + { + __IOM uint32_t DSEDCR; /*!< (@ 0x00000010) Error Detect Control Register */ + + struct + { + __IOM uint32_t SDE : 1; /*!< [0..0] Short circuit detection enable bit */ + uint32_t : 31; + } DSEDCR_b; + }; + + union + { + __IOM uint32_t DSOCFCR; /*!< (@ 0x00000014) Overcurrent Detect Filter Control Register */ + + struct + { + __IOM uint32_t OCSINC : 2; /*!< [1..0] Overcurrent detection filter order setting */ + uint32_t : 6; + __IOM uint32_t OCDEC : 8; /*!< [15..8] Decimation ratio selection for overcurrent detection */ + __IOM uint32_t OCSH : 5; /*!< [20..16] Data shift setting for overcurrent detection */ + uint32_t : 11; + } DSOCFCR_b; + }; + + union + { + __IOM uint32_t DSOCLTR; /*!< (@ 0x00000018) Overcurrent Low Threshold Register */ + + struct + { + __IOM uint32_t OCMPTBL : 16; /*!< [15..0] Overcurrent detection lower limit */ + uint32_t : 16; + } DSOCLTR_b; + }; + + union + { + __IOM uint32_t DSOCHTR; /*!< (@ 0x0000001C) Overcurrent High Threshold Register */ + + struct + { + __IOM uint32_t OCMPTBH : 16; /*!< [15..0] Overcurrent detection upper limit */ + uint32_t : 16; + } DSOCHTR_b; + }; + + union + { + __IOM uint32_t DSSCTSR; /*!< (@ 0x00000020) Short Circuit Threshold Setting Register */ + + struct + { + __IOM uint32_t SCNTL : 13; /*!< [12..0] Short circuit detection low continuous detection count */ + uint32_t : 3; + __IOM uint32_t SCNTH : 13; /*!< [28..16] Short circuit detection high continuous detection count */ + uint32_t : 3; + } DSSCTSR_b; + }; + + union + { + __IOM uint32_t DSODCR; /*!< (@ 0x00000024) Overcurrent Detect Control Register */ + + struct + { + __IOM uint32_t ODEL : 1; /*!< [0..0] Overcurrent lower limit detection enable bit */ + __IOM uint32_t ODEH : 1; /*!< [1..1] Overcurrent upper limit exceeded detection enable bit */ + uint32_t : 30; + } DSODCR_b; + }; + __IM uint32_t RESERVED[6]; + + union + { + __IOM uint32_t DSCSTRTR; /*!< (@ 0x00000040) Software Start Trigger Register */ + + struct + { + __IOM uint32_t STRTRG : 1; /*!< [0..0] Channel start trigger */ + uint32_t : 31; + } DSCSTRTR_b; + }; + + union + { + __IOM uint32_t DSCSTPTR; /*!< (@ 0x00000044) Software Stop Trigger Register */ + + struct + { + __IOM uint32_t STPTRG : 1; /*!< [0..0] Channel stop trigger */ + uint32_t : 31; + } DSCSTPTR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IM uint32_t DSCDR; /*!< (@ 0x00000050) Current Data Register */ + + struct + { + __IM uint32_t ADDR : 16; /*!< [15..0] Current data */ + uint32_t : 16; + } DSCDR_b; + }; + + union + { + __IM uint32_t DSCCDRA; /*!< (@ 0x00000054) Capture Current Data Register A */ + + struct + { + __IM uint32_t CDRA : 16; /*!< [15..0] Capture current data A */ + uint32_t : 16; + } DSCCDRA_b; + }; + + union + { + __IM uint32_t DSCCDRB; /*!< (@ 0x00000058) Capture Current Data Register B */ + + struct + { + __IM uint32_t CDRB : 16; /*!< [15..0] Capture current data B */ + uint32_t : 16; + } DSCCDRB_b; + }; + + union + { + __IM uint32_t DSOCDR; /*!< (@ 0x0000005C) Overcurrent Data Register */ + + struct + { + __IM uint32_t ODR : 16; /*!< [15..0] Overcurrent data */ + uint32_t : 16; + } DSOCDR_b; + }; + + union + { + __IM uint32_t DSCOCDR; /*!< (@ 0x00000060) Capture Overcurrent Data Register */ + + struct + { + __IM uint32_t CODR : 16; /*!< [15..0] Capture Overcurrent data when overcurrent detected */ + uint32_t : 16; + } DSCOCDR_b; + }; + __IM uint32_t RESERVED2[7]; + + union + { + __IM uint32_t DSCSR; /*!< (@ 0x00000080) Status Register */ + + struct + { + __IM uint32_t DUF : 1; /*!< [0..0] Channel n data update flag */ + __IM uint32_t OCFL : 1; /*!< [1..1] Channel n overcurrent lower limit detection flag */ + __IM uint32_t OCFH : 1; /*!< [2..2] Channel n overcurrent upper limit exceeded flag */ + __IM uint32_t SCF : 1; /*!< [3..3] Channel n short circuit detection flag */ + uint32_t : 12; + __IM uint32_t CHSTATE : 1; /*!< [16..16] Channel n state */ + uint32_t : 15; + } DSCSR_b; + }; + + union + { + __IOM uint32_t DSCSCR; /*!< (@ 0x00000084) Status Clear Register */ + + struct + { + __IOM uint32_t CLRDUF : 1; /*!< [0..0] Channel n data update flag clear */ + __IOM uint32_t CLROCFL : 1; /*!< [1..1] Channel n overcurrent lower limit detection flag clear */ + __IOM uint32_t CLROCFH : 1; /*!< [2..2] Channel n overcurrent upper limit exceeded flag clear */ + __IOM uint32_t CLRSCF : 1; /*!< [3..3] Channel n short circuit detection flag clear */ + uint32_t : 28; + } DSCSCR_b; + }; + __IM uint32_t RESERVED3[2]; +} R_DSMIF0_CH_Type; /*!< Size = 144 (0x90) */ + +/** @} */ /* End of group Device_Peripheral_clusters */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_GPT7 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief General PWM Timer 7 (R_GPT7) + */ + +typedef struct /*!< (@ 0x80000000) R_GPT7 Structure */ +{ + union + { + __IOM uint32_t GTWP; /*!< (@ 0x00000000) General PWM Timer Write-Protection Register */ + + struct + { + __IOM uint32_t WP : 1; /*!< [0..0] Register Write Disabled */ + __IOM uint32_t STRWP : 1; /*!< [1..1] GTSTR.CSTRT Bit Write Disabled */ + __IOM uint32_t STPWP : 1; /*!< [2..2] GTSTP.CSTOP Bit Write Disabled */ + __IOM uint32_t CLRWP : 1; /*!< [3..3] GTCLR.CCLR Bit Write Disabled */ + __IOM uint32_t CMNWP : 1; /*!< [4..4] Common Register Write Disabled */ + uint32_t : 3; + __OM uint32_t PRKEY : 8; /*!< [15..8] GTWP Key Code */ + uint32_t : 16; + } GTWP_b; + }; + + union + { + __IOM uint32_t GTSTR; /*!< (@ 0x00000004) General PWM Timer Software Start Register */ + + struct + { + __IOM uint32_t CSTRT0 : 1; /*!< [0..0] Channel 0 Count Start */ + __IOM uint32_t CSTRT1 : 1; /*!< [1..1] Channel 1 Count Start */ + __IOM uint32_t CSTRT2 : 1; /*!< [2..2] Channel 2 Count Start */ + __IOM uint32_t CSTRT3 : 1; /*!< [3..3] Channel 3 Count Start */ + __IOM uint32_t CSTRT4 : 1; /*!< [4..4] Channel 4 Count Start */ + __IOM uint32_t CSTRT5 : 1; /*!< [5..5] Channel 5 Count Start */ + __IOM uint32_t CSTRT6 : 1; /*!< [6..6] Channel 6 Count Start */ + uint32_t : 25; + } GTSTR_b; + }; + + union + { + __IOM uint32_t GTSTP; /*!< (@ 0x00000008) General PWM Timer Software Stop Register */ + + struct + { + __IOM uint32_t CSTOP0 : 1; /*!< [0..0] Channel 0 Count Stop */ + __IOM uint32_t CSTOP1 : 1; /*!< [1..1] Channel 1 Count Stop */ + __IOM uint32_t CSTOP2 : 1; /*!< [2..2] Channel 2 Count Stop */ + __IOM uint32_t CSTOP3 : 1; /*!< [3..3] Channel 3 Count Stop */ + __IOM uint32_t CSTOP4 : 1; /*!< [4..4] Channel 4 Count Stop */ + __IOM uint32_t CSTOP5 : 1; /*!< [5..5] Channel 5 Count Stop */ + __IOM uint32_t CSTOP6 : 1; /*!< [6..6] Channel 6 Count Stop */ + uint32_t : 25; + } GTSTP_b; + }; + + union + { + __OM uint32_t GTCLR; /*!< (@ 0x0000000C) General PWM Timer Software Clear Register */ + + struct + { + __OM uint32_t CCLR0 : 1; /*!< [0..0] Channel 0 Count Clear */ + __OM uint32_t CCLR1 : 1; /*!< [1..1] Channel 1 Count Clear */ + __OM uint32_t CCLR2 : 1; /*!< [2..2] Channel 2 Count Clear */ + __OM uint32_t CCLR3 : 1; /*!< [3..3] Channel 3 Count Clear */ + __OM uint32_t CCLR4 : 1; /*!< [4..4] Channel 4 Count Clear */ + __OM uint32_t CCLR5 : 1; /*!< [5..5] Channel 5 Count Clear */ + __OM uint32_t CCLR6 : 1; /*!< [6..6] Channel 6 Count Clear */ + uint32_t : 25; + } GTCLR_b; + }; + + union + { + __IOM uint32_t GTSSR; /*!< (@ 0x00000010) General PWM Timer Start Source Select Register */ + + struct + { + __IOM uint32_t SSGTRGAFR : 2; /*!< [1..0] SSGTRGAFR */ + __IOM uint32_t SSGTRGBFR : 2; /*!< [3..2] SSGTRGBFR */ + __IOM uint32_t SSGTRGCFR : 2; /*!< [5..4] SSGTRGCFR */ + __IOM uint32_t SSGTRGDFR : 2; /*!< [7..6] SSGTRGDFR */ + __IOM uint32_t SSCARBHL : 2; /*!< [9..8] SSCARBHL */ + __IOM uint32_t SSCAFBHL : 2; /*!< [11..10] SSCAFBHL */ + __IOM uint32_t SSCBRAHL : 2; /*!< [13..12] SSCBRAHL */ + __IOM uint32_t SSCBFAHL : 2; /*!< [15..14] SSCBFAHL */ + __IOM uint32_t SSELCA : 1; /*!< [16..16] SSELCA */ + __IOM uint32_t SSELCB : 1; /*!< [17..17] SSELCB */ + __IOM uint32_t SSELCC : 1; /*!< [18..18] SSELCC */ + __IOM uint32_t SSELCD : 1; /*!< [19..19] SSELCD */ + __IOM uint32_t SSELCE : 1; /*!< [20..20] SSELCE */ + __IOM uint32_t SSELCF : 1; /*!< [21..21] SSELCF */ + __IOM uint32_t SSELCG : 1; /*!< [22..22] SSELCG */ + __IOM uint32_t SSELCH : 1; /*!< [23..23] SSELCH */ + uint32_t : 7; + __IOM uint32_t CSTRT : 1; /*!< [31..31] Software Source Count Start Enable */ + } GTSSR_b; + }; + + union + { + __IOM uint32_t GTPSR; /*!< (@ 0x00000014) General PWM Timer Stop Source Select Register */ + + struct + { + __IOM uint32_t PSGTRGAFR : 2; /*!< [1..0] PSGTRGAFR */ + __IOM uint32_t PSGTRGBFR : 2; /*!< [3..2] PSGTRGBFR */ + __IOM uint32_t PSGTRGCFR : 2; /*!< [5..4] PSGTRGCFR */ + __IOM uint32_t PSGTRGDFR : 2; /*!< [7..6] PSGTRGDFR */ + __IOM uint32_t PSCARBHL : 2; /*!< [9..8] PSCARBHL */ + __IOM uint32_t PSCAFBHL : 2; /*!< [11..10] PSCAFBHL */ + __IOM uint32_t PSCBRAHL : 2; /*!< [13..12] PSCBRAHL */ + __IOM uint32_t PSCBFAHL : 2; /*!< [15..14] PSCBFAHL */ + __IOM uint32_t PSELCA : 1; /*!< [16..16] PSELCA */ + __IOM uint32_t PSELCB : 1; /*!< [17..17] PSELCB */ + __IOM uint32_t PSELCC : 1; /*!< [18..18] PSELCC */ + __IOM uint32_t PSELCD : 1; /*!< [19..19] PSELCD */ + __IOM uint32_t PSELCE : 1; /*!< [20..20] PSELCE */ + __IOM uint32_t PSELCF : 1; /*!< [21..21] PSELCF */ + __IOM uint32_t PSELCG : 1; /*!< [22..22] PSELCG */ + __IOM uint32_t PSELCH : 1; /*!< [23..23] PSELCH */ + uint32_t : 7; + __IOM uint32_t CSTOP : 1; /*!< [31..31] CSTOP */ + } GTPSR_b; + }; + + union + { + __IOM uint32_t GTCSR; /*!< (@ 0x00000018) General PWM Timer Clear Source Select Register */ + + struct + { + __IOM uint32_t CSGTRGAFR : 2; /*!< [1..0] CSGTRGAFR */ + __IOM uint32_t CSGTRGBFR : 2; /*!< [3..2] CSGTRGBFR */ + __IOM uint32_t CSGTRGCFR : 2; /*!< [5..4] CSGTRGCFR */ + __IOM uint32_t CSGTRGDFR : 2; /*!< [7..6] CSGTRGDFR */ + __IOM uint32_t CSCARBHL : 2; /*!< [9..8] CSCARBHL */ + __IOM uint32_t CSCAFBHL : 2; /*!< [11..10] CSCAFBHL */ + __IOM uint32_t CSCBRAHL : 2; /*!< [13..12] CSCBRAHL */ + __IOM uint32_t CSCBFAHL : 2; /*!< [15..14] CSCBFAHL */ + __IOM uint32_t CSELCA : 1; /*!< [16..16] CSELCA */ + __IOM uint32_t CSELCB : 1; /*!< [17..17] CSELCB */ + __IOM uint32_t CSELCC : 1; /*!< [18..18] CSELCC */ + __IOM uint32_t CSELCD : 1; /*!< [19..19] CSELCD */ + __IOM uint32_t CSELCE : 1; /*!< [20..20] CSELCE */ + __IOM uint32_t CSELCF : 1; /*!< [21..21] CSELCF */ + __IOM uint32_t CSELCG : 1; /*!< [22..22] CSELCG */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] CSELCH */ + uint32_t : 7; + __IOM uint32_t CCLR : 1; /*!< [31..31] CCLR */ + } GTCSR_b; + }; + + union + { + __IOM uint32_t GTUPSR; /*!< (@ 0x0000001C) General PWM Timer Count-Up Source Select Register */ + + struct + { + __IOM uint32_t USGTRGAFR : 2; /*!< [1..0] USGTRGAFR */ + __IOM uint32_t USGTRGBFR : 2; /*!< [3..2] USGTRGBFR */ + __IOM uint32_t USGTRGCFR : 2; /*!< [5..4] USGTRGCFR */ + __IOM uint32_t USGTRGDFR : 2; /*!< [7..6] USGTRGDFR */ + __IOM uint32_t USCARBHL : 2; /*!< [9..8] USCARBHL */ + __IOM uint32_t USCAFBHL : 2; /*!< [11..10] USCAFBHL */ + __IOM uint32_t USCBRAHL : 2; /*!< [13..12] USCBRAHL */ + __IOM uint32_t USCBFAHL : 2; /*!< [15..14] USCBFAHL */ + __IOM uint32_t USELCA : 1; /*!< [16..16] USELCA */ + __IOM uint32_t USELCB : 1; /*!< [17..17] USELCB */ + __IOM uint32_t USELCC : 1; /*!< [18..18] USELCC */ + __IOM uint32_t USELCD : 1; /*!< [19..19] USELCD */ + __IOM uint32_t USELCE : 1; /*!< [20..20] USELCE */ + __IOM uint32_t USELCF : 1; /*!< [21..21] USELCF */ + __IOM uint32_t USELCG : 1; /*!< [22..22] USELCG */ + __IOM uint32_t USELCH : 1; /*!< [23..23] USELCH */ + uint32_t : 8; + } GTUPSR_b; + }; + + union + { + __IOM uint32_t GTDNSR; /*!< (@ 0x00000020) General PWM Timer Count-Down Source Select Register */ + + struct + { + __IOM uint32_t DSGTRGAFR : 2; /*!< [1..0] DSGTRGAFR */ + __IOM uint32_t DSGTRGBFR : 2; /*!< [3..2] DSGTRGBFR */ + __IOM uint32_t DSGTRGCFR : 2; /*!< [5..4] DSGTRGCFR */ + __IOM uint32_t DSGTRGDFR : 2; /*!< [7..6] DSGTRGDFR */ + __IOM uint32_t DSCARBHL : 2; /*!< [9..8] DSCARBHL */ + __IOM uint32_t DSCAFBHL : 2; /*!< [11..10] DSCAFBHL */ + __IOM uint32_t DSCBRAHL : 2; /*!< [13..12] DSCBRAHL */ + __IOM uint32_t DSCBFAHL : 2; /*!< [15..14] DSCBFAHL */ + __IOM uint32_t DSELCA : 1; /*!< [16..16] DSELCA */ + __IOM uint32_t DSELCB : 1; /*!< [17..17] DSELCB */ + __IOM uint32_t DSELCC : 1; /*!< [18..18] DSELCC */ + __IOM uint32_t DSELCD : 1; /*!< [19..19] DSELCD */ + __IOM uint32_t DSELCE : 1; /*!< [20..20] DSELCE */ + __IOM uint32_t DSELCF : 1; /*!< [21..21] DSELCF */ + __IOM uint32_t DSELCG : 1; /*!< [22..22] DSELCG */ + __IOM uint32_t DSELCH : 1; /*!< [23..23] DSELCH */ + uint32_t : 8; + } GTDNSR_b; + }; + + union + { + __IOM uint32_t GTICASR; /*!< (@ 0x00000024) General PWM Timer Input Capture Source Select + * Register A */ + + struct + { + __IOM uint32_t ASGTRGAFR : 2; /*!< [1..0] ASGTRGAFR */ + __IOM uint32_t ASGTRGBFR : 2; /*!< [3..2] ASGTRGBFR */ + __IOM uint32_t ASGTRGCFR : 2; /*!< [5..4] ASGTRGCFR */ + __IOM uint32_t ASGTRGDFR : 2; /*!< [7..6] ASGTRGDFR */ + __IOM uint32_t ASCARBHL : 2; /*!< [9..8] ASCARBHL */ + __IOM uint32_t ASCAFBHL : 2; /*!< [11..10] ASCAFBHL */ + __IOM uint32_t ASCBRAHL : 2; /*!< [13..12] ASCBRAHL */ + __IOM uint32_t ASCBFAHL : 2; /*!< [15..14] ASCBFAHL */ + __IOM uint32_t ASELCA : 1; /*!< [16..16] ASELCA */ + __IOM uint32_t ASELCB : 1; /*!< [17..17] ASELCB */ + __IOM uint32_t ASELCC : 1; /*!< [18..18] ASELCC */ + __IOM uint32_t ASELCD : 1; /*!< [19..19] ASELCD */ + __IOM uint32_t ASELCE : 1; /*!< [20..20] ASELCE */ + __IOM uint32_t ASELCF : 1; /*!< [21..21] ASELCF */ + __IOM uint32_t ASELCG : 1; /*!< [22..22] ASELCG */ + __IOM uint32_t ASELCH : 1; /*!< [23..23] ASELCH */ + uint32_t : 8; + } GTICASR_b; + }; + + union + { + __IOM uint32_t GTICBSR; /*!< (@ 0x00000028) General PWM Timer Input Capture Source Select + * Register B */ + + struct + { + __IOM uint32_t BSGTRGAFR : 2; /*!< [1..0] BSGTRGAFR */ + __IOM uint32_t BSGTRGBFR : 2; /*!< [3..2] BSGTRGBFR */ + __IOM uint32_t BSGTRGCFR : 2; /*!< [5..4] BSGTRGCFR */ + __IOM uint32_t BSGTRGDFR : 2; /*!< [7..6] BSGTRGDFR */ + __IOM uint32_t BSCARBHL : 2; /*!< [9..8] BSCARBHL */ + __IOM uint32_t BSCAFBHL : 2; /*!< [11..10] BSCAFBHL */ + __IOM uint32_t BSCBRAHL : 2; /*!< [13..12] BSCBRAHL */ + __IOM uint32_t BSCBFAHL : 2; /*!< [15..14] BSCBFAHL */ + __IOM uint32_t BSELCA : 1; /*!< [16..16] BSELCA */ + __IOM uint32_t BSELCB : 1; /*!< [17..17] BSELCB */ + __IOM uint32_t BSELCC : 1; /*!< [18..18] BSELCC */ + __IOM uint32_t BSELCD : 1; /*!< [19..19] BSELCD */ + __IOM uint32_t BSELCE : 1; /*!< [20..20] BSELCE */ + __IOM uint32_t BSELCF : 1; /*!< [21..21] BSELCF */ + __IOM uint32_t BSELCG : 1; /*!< [22..22] BSELCG */ + __IOM uint32_t BSELCH : 1; /*!< [23..23] BSELCH */ + uint32_t : 8; + } GTICBSR_b; + }; + + union + { + __IOM uint32_t GTCR; /*!< (@ 0x0000002C) General PWM Timer Control Register */ + + struct + { + __IOM uint32_t CST : 1; /*!< [0..0] Count Start */ + uint32_t : 7; + __IOM uint32_t ICDS : 1; /*!< [8..8] Input Capture Operation Select at Count Stop */ + uint32_t : 7; + __IOM uint32_t MD : 3; /*!< [18..16] Mode Select */ + uint32_t : 4; + __IOM uint32_t TPCS : 4; /*!< [26..23] Timer Prescaler Select */ + uint32_t : 2; + __IOM uint32_t SWMD : 3; /*!< [31..29] Switch Mode Select */ + } GTCR_b; + }; + + union + { + __IOM uint32_t GTUDDTYC; /*!< (@ 0x00000030) General PWM Timer Count Direction and Duty Setting + * Register */ + + struct + { + __IOM uint32_t UD : 1; /*!< [0..0] Count Direction Setting */ + __IOM uint32_t UDF : 1; /*!< [1..1] Forcible Count Direction Setting */ + uint32_t : 14; + __IOM uint32_t OADTY : 2; /*!< [17..16] GTIOCnA Pin Output Duty Setting */ + __IOM uint32_t OADTYF : 1; /*!< [18..18] GTIOCnA Pin Output Duty Forced Setting */ + __IOM uint32_t OADTYR : 1; /*!< [19..19] Output after Release of GTIOCnA Pin Output 0%/100% + * Duty Cycle Settings */ + uint32_t : 4; + __IOM uint32_t OBDTY : 2; /*!< [25..24] GTIOCnB Pin Output Duty Setting */ + __IOM uint32_t OBDTYF : 1; /*!< [26..26] GTIOCnB Pin Output Duty Forced Setting */ + __IOM uint32_t OBDTYR : 1; /*!< [27..27] Output after Release of GTIOCnB Pin Output 0%/100% + * Duty Cycle Settings */ + uint32_t : 4; + } GTUDDTYC_b; + }; + + union + { + __IOM uint32_t GTIOR; /*!< (@ 0x00000034) General PWM Timer I/O Control Register */ + + struct + { + __IOM uint32_t GTIOA : 5; /*!< [4..0] GTIOCnA Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OADFLT : 1; /*!< [6..6] GTIOCnA Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OAHLD : 1; /*!< [7..7] GTIOCnA Pin Output Retention at the Start/Stop Count */ + __IOM uint32_t OAE : 1; /*!< [8..8] GTIOCnA Pin Output Enable */ + __IOM uint32_t OADF : 2; /*!< [10..9] GTIOCnA Pin Negate Value Setting */ + uint32_t : 2; + __IOM uint32_t NFAEN : 1; /*!< [13..13] GTIOCnA Pin Input Noise Filter Enable */ + __IOM uint32_t NFCSA : 2; /*!< [15..14] GTIOCnA Pin Input Noise Filter Sampling Clock Select */ + __IOM uint32_t GTIOB : 5; /*!< [20..16] GTIOCnB Pin Function Select */ + uint32_t : 1; + __IOM uint32_t OBDFLT : 1; /*!< [22..22] GTIOCnB Pin Output Value Setting at the Count Stop */ + __IOM uint32_t OBHLD : 1; /*!< [23..23] GTIOCnB Pin Output Retention at the Start/Stop Count */ + __IOM uint32_t OBE : 1; /*!< [24..24] GTIOCnB Pin Output Enable */ + __IOM uint32_t OBDF : 2; /*!< [26..25] GTIOCnB Pin Negate Value Setting */ + uint32_t : 2; + __IOM uint32_t NFBEN : 1; /*!< [29..29] GTIOCnB Pin Input Noise Filter Enable */ + __IOM uint32_t NFCSB : 2; /*!< [31..30] GTIOCnB Pin Input Noise Filter Sampling Clock Select */ + } GTIOR_b; + }; + + union + { + __IOM uint32_t GTINTAD; /*!< (@ 0x00000038) General PWM Timer Interrupt Output Setting Register */ + + struct + { + __IOM uint32_t GTINTA : 1; /*!< [0..0] GTINTA */ + __IOM uint32_t GTINTB : 1; /*!< [1..1] GTINTB */ + __IOM uint32_t GTINTC : 1; /*!< [2..2] GTINTC */ + __IOM uint32_t GTINTD : 1; /*!< [3..3] GTINTD */ + __IOM uint32_t GTINTE : 1; /*!< [4..4] GTINTE */ + __IOM uint32_t GTINTF : 1; /*!< [5..5] GTINTF */ + __IOM uint32_t GTINTPR : 2; /*!< [7..6] GTINTPR */ + uint32_t : 8; + __IOM uint32_t ADTRAUEN : 1; /*!< [16..16] ADTRAUEN */ + __IOM uint32_t ADTRADEN : 1; /*!< [17..17] ADTRADEN */ + __IOM uint32_t ADTRBUEN : 1; /*!< [18..18] ADTRBUEN */ + __IOM uint32_t ADTRBDEN : 1; /*!< [19..19] ADTRBDEN */ + uint32_t : 4; + __IOM uint32_t GRP : 2; /*!< [25..24] Select the group to detect disabling of output (dead-time + * error or simultaneous driving of outputs to the high or + * low level) to POEG and to request of disabling of output + * from POEG. */ + uint32_t : 2; + __IOM uint32_t GRPDTE : 1; /*!< [28..28] GRPDTE */ + __IOM uint32_t GRPABH : 1; /*!< [29..29] (GTIOCnA pin and GTIOCnB output) */ + __IOM uint32_t GRPABL : 1; /*!< [30..30] (GTIOCnA pin and GTIOCnB output) */ + uint32_t : 1; + } GTINTAD_b; + }; + + union + { + __IOM uint32_t GTST; /*!< (@ 0x0000003C) General PWM Timer Status Register */ + + struct + { + uint32_t : 8; + __IM uint32_t ITCNT : 3; /*!< [10..8] GPTn_OVF/GPTn_UDF Interrupt Skipping Count Counter */ + uint32_t : 4; + __IM uint32_t TUCF : 1; /*!< [15..15] Count Direction Flag */ + __IOM uint32_t ADTRAUF : 1; /*!< [16..16] GTADTRA Register Compare Match (Up-Counting) A/D Converter + * Start Request Flag */ + __IOM uint32_t ADTRADF : 1; /*!< [17..17] GTADTRA Register Compare Match (Down-Counting) A/D + * Converter Start Request Flag */ + __IOM uint32_t ADTRBUF : 1; /*!< [18..18] GTADTRB Register Compare Match (Up-Counting) A/D Converter + * Start Request Flag */ + __IOM uint32_t ADTRBDF : 1; /*!< [19..19] GTADTRB Register Compare Match (Down-Counting) A/D + * Converter Start Request Flag */ + uint32_t : 4; + __IM uint32_t ODF : 1; /*!< [24..24] Output Stop Request Flag */ + uint32_t : 3; + __IM uint32_t DTEF : 1; /*!< [28..28] Dead Time Error Flag */ + __IM uint32_t OABHF : 1; /*!< [29..29] Simultaneous High Output Flag */ + __IM uint32_t OABLF : 1; /*!< [30..30] Simultaneous Low Output Flag */ + uint32_t : 1; + } GTST_b; + }; + + union + { + __IOM uint32_t GTBER; /*!< (@ 0x00000040) General PWM Timer Buffer Enable Register */ + + struct + { + __IOM uint32_t BD0 : 1; /*!< [0..0] GTCCRA/GTCCRB Registers Buffer Operation Disable */ + __IOM uint32_t BD1 : 1; /*!< [1..1] GTPR Register Buffer Operation Disable */ + __IOM uint32_t BD2 : 1; /*!< [2..2] GTADTRA/GTADTRB Registers Buffer Operation Disable */ + __IOM uint32_t BD3 : 1; /*!< [3..3] GTDVU/GTDVD Registers Buffer Operation Disable */ + uint32_t : 4; + __IOM uint32_t DBRTECA : 1; /*!< [8..8] GTCCRA Register Double Buffer Repeat Operation Enable */ + uint32_t : 1; + __IOM uint32_t DBRTECB : 1; /*!< [10..10] GTCCRB Register Double Buffer Repeat Operation Enable */ + uint32_t : 5; + __IOM uint32_t CCRA : 2; /*!< [17..16] GTCCRA Register Buffer Operation */ + __IOM uint32_t CCRB : 2; /*!< [19..18] GTCCRB Register Buffer Operation */ + __IOM uint32_t PR : 2; /*!< [21..20] GTPR Register Buffer Operation */ + __IOM uint32_t CCRSWT : 1; /*!< [22..22] GTCCRA and GTCCRB Registers Forcible Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTA : 2; /*!< [25..24] GTADTRA Register Buffer Transfer Timing Select */ + __IOM uint32_t ADTDA : 1; /*!< [26..26] GTADTRA Register Double Buffer Operation */ + uint32_t : 1; + __IOM uint32_t ADTTB : 2; /*!< [29..28] GTADTRB Register Buffer Transfer Timing Select */ + __IOM uint32_t ADTDB : 1; /*!< [30..30] GTADTRB Register Double Buffer Operation */ + uint32_t : 1; + } GTBER_b; + }; + + union + { + __IOM uint32_t GTITC; /*!< (@ 0x00000044) General PWM Timer Interrupt and A/D Converter + * Start Request Skipping Setting Register */ + + struct + { + __IOM uint32_t ITLA : 1; /*!< [0..0] ITLA */ + __IOM uint32_t ITLB : 1; /*!< [1..1] ITLB */ + __IOM uint32_t ITLC : 1; /*!< [2..2] ITLC */ + __IOM uint32_t ITLD : 1; /*!< [3..3] ITLD */ + __IOM uint32_t ITLE : 1; /*!< [4..4] ITLE */ + __IOM uint32_t ITLF : 1; /*!< [5..5] ITLF */ + __IOM uint32_t IVTC : 2; /*!< [7..6] IVTC */ + __IOM uint32_t IVTT : 3; /*!< [10..8] IVTT */ + uint32_t : 1; + __IOM uint32_t ADTAL : 1; /*!< [12..12] ADTAL */ + uint32_t : 1; + __IOM uint32_t ADTBL : 1; /*!< [14..14] ADTBL */ + uint32_t : 17; + } GTITC_b; + }; + __IOM uint32_t GTCNT; /*!< (@ 0x00000048) General PWM Timer Counter */ + __IOM uint32_t GTCCR[6]; /*!< (@ 0x0000004C) General PWM Timer Compare Capture Register m + * (m = A to F) */ + __IOM uint32_t GTPR; /*!< (@ 0x00000064) General PWM Timer Cycle Setting Register */ + __IOM uint32_t GTPBR; /*!< (@ 0x00000068) General PWM Timer Cycle Setting Buffer Register */ + __IOM uint32_t GTPDBR; /*!< (@ 0x0000006C) General PWM Timer Cycle Setting Double-Buffer + * Register */ + __IOM uint32_t GTADTRA; /*!< (@ 0x00000070) A/D Converter Start Request Timing Register A + * (m = A, B) */ + __IOM uint32_t GTADTBRA; /*!< (@ 0x00000074) A/D Converter Start Request Timing Buffer Register + * A (m = A, B) */ + __IOM uint32_t GTADTDBRA; /*!< (@ 0x00000078) A/D Converter Start Request Timing Double-Buffer + * Register A */ + __IOM uint32_t GTADTRB; /*!< (@ 0x0000007C) A/D Converter Start Request Timing Register B + * (m = A, B) */ + __IOM uint32_t GTADTBRB; /*!< (@ 0x00000080) A/D Converter Start Request Timing Buffer Register + * B (m = A, B) */ + __IOM uint32_t GTADTDBRB; /*!< (@ 0x00000084) A/D Converter Start Request Timing Double-Buffer + * Register B */ + + union + { + __IOM uint32_t GTDTCR; /*!< (@ 0x00000088) General PWM Timer Dead Time Control Register */ + + struct + { + __IOM uint32_t TDE : 1; /*!< [0..0] Negative-Phase Waveform Setting */ + uint32_t : 3; + __IOM uint32_t TDBUE : 1; /*!< [4..4] GTDVU Register Buffer Operation Enable */ + __IOM uint32_t TDBDE : 1; /*!< [5..5] GTDVD Register Buffer Operation Enable */ + uint32_t : 2; + __IOM uint32_t TDFER : 1; /*!< [8..8] GTDVD Register Setting */ + uint32_t : 23; + } GTDTCR_b; + }; + __IOM uint32_t GTDVU; /*!< (@ 0x0000008C) General PWM Timer Dead Time Value Register U + * (m = U, D) */ + __IOM uint32_t GTDVD; /*!< (@ 0x00000090) General PWM Timer Dead Time Value Register D + * (m = U, D) */ + __IOM uint32_t GTDBU; /*!< (@ 0x00000094) General PWM Timer Dead Time Value Buffer Register + * U (m = U, D) */ + __IOM uint32_t GTDBD; /*!< (@ 0x00000098) General PWM Timer Dead Time Value Buffer Register + * D (m = U, D) */ + + union + { + __IM uint32_t GTSOS; /*!< (@ 0x0000009C) General PWM Timer Output Protection Function + * Status Register */ + + struct + { + __IM uint32_t SOS : 2; /*!< [1..0] Output Protection Function Status */ + uint32_t : 30; + } GTSOS_b; + }; + + union + { + __IOM uint32_t GTSOTR; /*!< (@ 0x000000A0) General PWM Timer Output Protection Function + * Temporary Release Register */ + + struct + { + __IOM uint32_t SOTR : 1; /*!< [0..0] Output Protection Function Temporary Release */ + uint32_t : 31; + } GTSOTR_b; + }; + + union + { + __IOM uint32_t GTADSMR; /*!< (@ 0x000000A4) General PWM Timer A/D Conversion Start Request + * Signal Monitoring Register */ + + struct + { + __IOM uint32_t ADSMS0 : 2; /*!< [1..0] A/D Conversion Start Request Signal Monitor 0 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN0 : 1; /*!< [8..8] A/D Conversion Start Request Signal Monitor 0 Output + * Enabling */ + uint32_t : 7; + __IOM uint32_t ADSMS1 : 2; /*!< [17..16] A/D Conversion Start Request Signal Monitor 1 Selection */ + uint32_t : 6; + __IOM uint32_t ADSMEN1 : 1; /*!< [24..24] A/D Conversion Start Request Signal Monitor 1 Output + * Enabling */ + uint32_t : 7; + } GTADSMR_b; + }; + + union + { + __IOM uint32_t GTEITC; /*!< (@ 0x000000A8) General PWM Timer Extended Interrupt Skipping + * Counter Control Register */ + + struct + { + __IOM uint32_t EIVTC1 : 2; /*!< [1..0] Extended Interrupt Skipping Counter 1 Count Source Select */ + uint32_t : 2; + __IOM uint32_t EIVTT1 : 4; /*!< [7..4] Extended Interrupt Skipping 1 Skipping Count Setting */ + uint32_t : 4; + __IM uint32_t EITCNT1 : 4; /*!< [15..12] Extended Interrupt Skipping Counter 1 */ + __IOM uint32_t EIVTC2 : 2; /*!< [17..16] Extended Interrupt Skipping Counter 2 Count Source + * Select */ + uint32_t : 2; + __IOM uint32_t EIVTT2 : 4; /*!< [23..20] Extended Interrupt Skipping 2 Skipping Count Setting */ + __IOM uint32_t EITCNT2IV : 4; /*!< [27..24] Extended Interrupt Skipping Counter 2 Initial Value */ + __IM uint32_t EITCNT2 : 4; /*!< [31..28] Extended Interrupt Skipping Counter 2 */ + } GTEITC_b; + }; + + union + { + __IOM uint32_t GTEITLI1; /*!< (@ 0x000000AC) General PWM Timer Extended Interrupt Skipping + * Setting Register 1 */ + + struct + { + __IOM uint32_t EITLA : 3; /*!< [2..0] GTCCRA Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLB : 3; /*!< [6..4] GTCCRB Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLC : 3; /*!< [10..8] GTCCRC Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLD : 3; /*!< [14..12] GTCCRD Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLE : 3; /*!< [18..16] GTCCRE Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLF : 3; /*!< [22..20] GTCCRF Register Compare Match / Input Capture Interrupt + * Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLV : 3; /*!< [26..24] Overflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + __IOM uint32_t EITLU : 3; /*!< [30..28] Underflow Interrupt Extended Skipping Function Select */ + uint32_t : 1; + } GTEITLI1_b; + }; + + union + { + __IOM uint32_t GTEITLI2; /*!< (@ 0x000000B0) General PWM Timer Extended Interrupt Skipping + * Setting Register 2 */ + + struct + { + __IOM uint32_t EADTAL : 3; /*!< [2..0] GTADTRA A/D Converter Start Request Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EADTBL : 3; /*!< [6..4] GTADTRB A/D Converter Start Request Extended Skipping + * Function Select */ + uint32_t : 25; + } GTEITLI2_b; + }; + + union + { + __IOM uint32_t GTEITLB; /*!< (@ 0x000000B4) General PWM Timer Extended Buffer Transfer Skipping + * Setting Register */ + + struct + { + __IOM uint32_t EBTLCA : 3; /*!< [2..0] GTCCRA Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLCB : 3; /*!< [6..4] GTCCRB Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLPR : 3; /*!< [10..8] GTPR Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 5; + __IOM uint32_t EBTLADA : 3; /*!< [18..16] GTADTRA Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLADB : 3; /*!< [22..20] GTADTRB Register Buffer Transfer Extended Skipping + * Function Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVU : 3; /*!< [26..24] GTDVU Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + __IOM uint32_t EBTLDVD : 3; /*!< [30..28] GTDVD Register Buffer Transfer Extended Skipping Function + * Select */ + uint32_t : 1; + } GTEITLB_b; + }; + __IM uint32_t RESERVED[6]; + + union + { + __IOM uint32_t GTSECSR; /*!< (@ 0x000000D0) General PWM Timer Operation Enable Bit Simultaneous + * Control Channel Select Register */ + + struct + { + __IOM uint32_t SECSEL0 : 1; /*!< [0..0] Channel 0 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL1 : 1; /*!< [1..1] Channel 1 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL2 : 1; /*!< [2..2] Channel 2 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL3 : 1; /*!< [3..3] Channel 3 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL4 : 1; /*!< [4..4] Channel 4 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL5 : 1; /*!< [5..5] Channel 5 Operation Enable Bit Simultaneous Control Channel + * Select */ + __IOM uint32_t SECSEL6 : 1; /*!< [6..6] Channel 6 Operation Enable Bit Simultaneous Control Channel + * Select */ + uint32_t : 25; + } GTSECSR_b; + }; + + union + { + __IOM uint32_t GTSECR; /*!< (@ 0x000000D4) General PWM Timer Operation Enable Bit Simultaneous + * Control Register */ + + struct + { + __IOM uint32_t SBDCE : 1; /*!< [0..0] GTCCR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDPE : 1; /*!< [1..1] GTPR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDAE : 1; /*!< [2..2] GTADTR Register Buffer Operation Simultaneous Enable */ + __IOM uint32_t SBDDE : 1; /*!< [3..3] GTDV Register Buffer Operation Simultaneous Enable */ + uint32_t : 4; + __IOM uint32_t SBDCD : 1; /*!< [8..8] GTCCR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDPD : 1; /*!< [9..9] GTPR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDAD : 1; /*!< [10..10] GTADTR Register Buffer Operation Simultaneous Disable */ + __IOM uint32_t SBDDD : 1; /*!< [11..11] GTDV Register Buffer Operation Simultaneous Disable */ + uint32_t : 20; + } GTSECR_b; + }; + + union + { + __IOM uint32_t GTSWSR; /*!< (@ 0x000000D8) General PWM Timer Switch Source Select Register */ + + struct + { + __IOM uint32_t WSGTRGA : 2; /*!< [1..0] GTETRGA Signal Edge Select to Switch Counter (GTETRGSA + * Signal for SAFTY) */ + __IOM uint32_t WSGTRGB : 2; /*!< [3..2] GTETRGB Signal Edge Select to Switch Counter (GTETRGSB + * Signal for SAFTY) */ + __IOM uint32_t WSGTRGC : 2; /*!< [5..4] GTETRGC Signal Edge Select to Switch Counter (GTETRGSC + * Signal for SAFTY) */ + __IOM uint32_t WSGTRGD : 2; /*!< [7..6] GTETRGD Signal Edge Select to Switch Counter (GTETRGSD + * Signal for SAFTY) */ + uint32_t : 8; + __IOM uint32_t WSELCA : 1; /*!< [16..16] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCB : 1; /*!< [17..17] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCC : 1; /*!< [18..18] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCD : 1; /*!< [19..19] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCE : 1; /*!< [20..20] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCF : 1; /*!< [21..21] Event Source Counter Switch Enable */ + __IOM uint32_t WSELCG : 1; /*!< [22..22] Event Source Counter Switch Enable */ + __IOM uint32_t CSELCH : 1; /*!< [23..23] Event Source Counter Switch Enable */ + uint32_t : 8; + } GTSWSR_b; + }; + __IOM uint32_t GTSWOS; /*!< (@ 0x000000DC) General PWM Timer Switch Offset Setting Register */ +} R_GPT0_Type; /*!< Size = 224 (0xe0) */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Communication Interface 0 (R_SCI0) + */ + +typedef struct /*!< (@ 0x80001000) R_SCI0 Structure */ +{ + union + { + __IM uint32_t RDR; /*!< (@ 0x00000000) Receive Data Register */ + + struct + { + __IM uint32_t RDAT : 9; /*!< [8..0] Serial receive data */ + __IM uint32_t MPB : 1; /*!< [9..9] Multi-processor flag */ + __IM uint32_t DR : 1; /*!< [10..10] Receive data ready flag */ + __IM uint32_t FPER : 1; /*!< [11..11] FIFO parity error flag */ + __IM uint32_t FFER : 1; /*!< [12..12] FIFO framing error flag */ + uint32_t : 11; + __IM uint32_t ORER : 1; /*!< [24..24] Overrun Error flag */ + uint32_t : 2; + __IM uint32_t PER : 1; /*!< [27..27] Parity error flag */ + __IM uint32_t FER : 1; /*!< [28..28] Framing error flag */ + uint32_t : 3; + } RDR_b; + }; + + union + { + __IOM uint32_t TDR; /*!< (@ 0x00000004) Transmit Data Register */ + + struct + { + __IOM uint32_t TDAT : 9; /*!< [8..0] Serial transmit data */ + __IOM uint32_t MPBT : 1; /*!< [9..9] Multi-processor transfer bit flag */ + uint32_t : 22; + } TDR_b; + }; + + union + { + __IOM uint32_t CCR0; /*!< (@ 0x00000008) Common Control Register 0 */ + + struct + { + __IOM uint32_t RE : 1; /*!< [0..0] Receive Enable */ + uint32_t : 3; + __IOM uint32_t TE : 1; /*!< [4..4] Transmit Enable */ + uint32_t : 3; + __IOM uint32_t MPIE : 1; /*!< [8..8] Multi-Processor Interrupt Enable */ + __IOM uint32_t DCME : 1; /*!< [9..9] Data Compare Match Enable */ + __IOM uint32_t IDSEL : 1; /*!< [10..10] ID frame select */ + uint32_t : 5; + __IOM uint32_t RIE : 1; /*!< [16..16] Receive Interrupt Enable */ + uint32_t : 3; + __IOM uint32_t TIE : 1; /*!< [20..20] Transmit Interrupt Enable */ + __IOM uint32_t TEIE : 1; /*!< [21..21] Transmit End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SSE : 1; /*!< [24..24] SSn# Pin Function Enable */ + uint32_t : 7; + } CCR0_b; + }; + + union + { + __IOM uint32_t CCR1; /*!< (@ 0x0000000C) Common Control Register 1 */ + + struct + { + __IOM uint32_t CTSE : 1; /*!< [0..0] CTS Enable */ + __IOM uint32_t CTSPEN : 1; /*!< [1..1] CTS external pin Enable */ + uint32_t : 2; + __IOM uint32_t SPB2DT : 1; /*!< [4..4] Serial port break data select */ + __IOM uint32_t SPB2IO : 1; /*!< [5..5] Serial port break I/O */ + uint32_t : 2; + __IOM uint32_t PE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t PM : 1; /*!< [9..9] Parity Mode */ + uint32_t : 2; + __IOM uint32_t TINV : 1; /*!< [12..12] TXD invert */ + __IOM uint32_t RINV : 1; /*!< [13..13] RXD invert */ + uint32_t : 2; + __IOM uint32_t SPLP : 1; /*!< [16..16] Loopback Control */ + uint32_t : 3; + __IOM uint32_t SHARPS : 1; /*!< [20..20] Half-duplex communication select */ + uint32_t : 3; + __IOM uint32_t NFCS : 3; /*!< [26..24] Noise Filter Clock Select */ + uint32_t : 1; + __IOM uint32_t NFEN : 1; /*!< [28..28] Digital Noise Filter Function Enable */ + uint32_t : 3; + } CCR1_b; + }; + + union + { + __IOM uint32_t CCR2; /*!< (@ 0x00000010) Common Control Register 2 */ + + struct + { + __IOM uint32_t BCP : 3; /*!< [2..0] Base Clock Pulse */ + uint32_t : 1; + __IOM uint32_t BGDM : 1; /*!< [4..4] Baud Rate Generator Double-Speed Mode Select */ + __IOM uint32_t ABCS : 1; /*!< [5..5] Asynchronous Mode Base Clock Select */ + __IOM uint32_t ABCSE : 1; /*!< [6..6] Asynchronous Mode Extended Base Clock Select */ + uint32_t : 1; + __IOM uint32_t BRR : 8; /*!< [15..8] Bit rate setting */ + __IOM uint32_t BRME : 1; /*!< [16..16] BRME */ + uint32_t : 3; + __IOM uint32_t CKS : 2; /*!< [21..20] Clock Select */ + uint32_t : 2; + __IOM uint32_t MDDR : 8; /*!< [31..24] Modulation Duty setting */ + } CCR2_b; + }; + + union + { + __IOM uint32_t CCR3; /*!< (@ 0x00000014) Common Control Register 3 */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] Clock Phase Select */ + __IOM uint32_t CPOL : 1; /*!< [1..1] Clock Polarity Select */ + uint32_t : 5; + __IOM uint32_t BPEN : 1; /*!< [7..7] Synchronizer bypass enable */ + __IOM uint32_t CHR : 2; /*!< [9..8] Character Length */ + uint32_t : 2; + __IOM uint32_t LSBF : 1; /*!< [12..12] LSB First select */ + __IOM uint32_t SINV : 1; /*!< [13..13] Transmitted/Received Data Invert */ + __IOM uint32_t STP : 1; /*!< [14..14] Stop Bit Length */ + __IOM uint32_t RXDESEL : 1; /*!< [15..15] Asynchronous Start Bit Edge Detection Select */ + __IOM uint32_t MOD : 3; /*!< [18..16] Communication mode select */ + __IOM uint32_t MP : 1; /*!< [19..19] Multi-Processor Mode */ + __IOM uint32_t FM : 1; /*!< [20..20] FIFO Mode select */ + __IOM uint32_t DEN : 1; /*!< [21..21] Driver enable */ + uint32_t : 2; + __IOM uint32_t CKE : 2; /*!< [25..24] Clock enable */ + uint32_t : 2; + __IOM uint32_t GM : 1; /*!< [28..28] GSM Mode */ + __IOM uint32_t BLK : 1; /*!< [29..29] Block Transfer Mode */ + uint32_t : 2; + } CCR3_b; + }; + + union + { + __IOM uint32_t CCR4; /*!< (@ 0x00000018) Common Control Register 4 */ + + struct + { + __IOM uint32_t CMPD : 9; /*!< [8..0] Compare Match Data */ + uint32_t : 7; + __IOM uint32_t ASEN : 1; /*!< [16..16] Adjust receive sampling timing enable */ + __IOM uint32_t ATEN : 1; /*!< [17..17] Adjust transmit timing enable */ + uint32_t : 6; + __IOM uint32_t AST : 3; /*!< [26..24] Adjustment value for receive Sampling Timing */ + __IOM uint32_t AJD : 1; /*!< [27..27] Adjustment Direction for receive sampling timing */ + __IOM uint32_t ATT : 3; /*!< [30..28] Adjustment value for Transmit timing */ + __IOM uint32_t AET : 1; /*!< [31..31] Adjustment edge for transmit timing */ + } CCR4_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t ICR; /*!< (@ 0x00000020) Simple I2C Control Register */ + + struct + { + __IOM uint32_t IICDL : 5; /*!< [4..0] SDA Delay Output Select */ + uint32_t : 3; + __IOM uint32_t IICINTM : 1; /*!< [8..8] IICINTM */ + __IOM uint32_t IICCSC : 1; /*!< [9..9] IICCSC */ + uint32_t : 3; + __IOM uint32_t IICACKT : 1; /*!< [13..13] IICACKT */ + uint32_t : 2; + __IOM uint32_t IICSTAREQ : 1; /*!< [16..16] IICSTAREQ */ + __IOM uint32_t IICRSTAREQ : 1; /*!< [17..17] IICRSTAREQ */ + __IOM uint32_t IICSTPREQ : 1; /*!< [18..18] IICSTPREQ */ + uint32_t : 1; + __IOM uint32_t IICSDAS : 2; /*!< [21..20] IICSDAS */ + __IOM uint32_t IICSCLS : 2; /*!< [23..22] IICSCLS */ + uint32_t : 8; + } ICR_b; + }; + + union + { + __IOM uint32_t FCR; /*!< (@ 0x00000024) FIFO Control Register */ + + struct + { + __IOM uint32_t DRES : 1; /*!< [0..0] Receive data ready error select */ + uint32_t : 7; + __IOM uint32_t TTRG : 5; /*!< [12..8] Transmit FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t TFRST : 1; /*!< [15..15] Transmit FIFO Data Register Reset */ + __IOM uint32_t RTRG : 5; /*!< [20..16] Receive FIFO data trigger number */ + uint32_t : 2; + __OM uint32_t RFRST : 1; /*!< [23..23] Receive FIFO Data Register Reset */ + __IOM uint32_t RSTRG : 5; /*!< [28..24] RTS# Output Active Trigger Number Select */ + uint32_t : 3; + } FCR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t DCR; /*!< (@ 0x00000030) Driver Control Register */ + + struct + { + __IOM uint32_t DEPOL : 1; /*!< [0..0] Driver effective polarity select */ + uint32_t : 7; + __IOM uint32_t DEAST : 5; /*!< [12..8] Driver Assertion Time */ + uint32_t : 3; + __IOM uint32_t DENGT : 5; /*!< [20..16] Driver negate time */ + uint32_t : 11; + } DCR_b; + }; + __IM uint32_t RESERVED2[5]; + + union + { + __IM uint32_t CSR; /*!< (@ 0x00000048) Common Status Register */ + + struct + { + uint32_t : 4; + __IM uint32_t ERS : 1; /*!< [4..4] Error Signal Status Flag */ + uint32_t : 10; + __IM uint32_t RXDMON : 1; /*!< [15..15] Serial input data monitor */ + __IM uint32_t DCMF : 1; /*!< [16..16] Data Compare Match Flag */ + __IM uint32_t DPER : 1; /*!< [17..17] Data Compare Match Parity Error Flag */ + __IM uint32_t DFER : 1; /*!< [18..18] Data Compare Match Framing Error Flag */ + uint32_t : 5; + __IM uint32_t ORER : 1; /*!< [24..24] ORER */ + uint32_t : 1; + __IM uint32_t MFF : 1; /*!< [26..26] Mode Fault Error Flag */ + __IM uint32_t PER : 1; /*!< [27..27] PER */ + __IM uint32_t FER : 1; /*!< [28..28] FER */ + __IM uint32_t TDRE : 1; /*!< [29..29] Transmit Data Empty Flag */ + __IM uint32_t TEND : 1; /*!< [30..30] TEND */ + __IM uint32_t RDRF : 1; /*!< [31..31] RDRF */ + } CSR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x0000004C) Simple I2C Status Register */ + + struct + { + __IM uint32_t IICACKR : 1; /*!< [0..0] ACK Reception Data Flag */ + uint32_t : 2; + __IM uint32_t IICSTIF : 1; /*!< [3..3] Issuing of Start, Restart, or Stop Condition Completed + * Flag */ + uint32_t : 28; + } ISR_b; + }; + + union + { + __IM uint32_t FRSR; /*!< (@ 0x00000050) FIFO Receive Status Register */ + + struct + { + __IM uint32_t DR : 1; /*!< [0..0] DR */ + uint32_t : 7; + __IM uint32_t R : 6; /*!< [13..8] Receive FIFO Data Count */ + uint32_t : 2; + __IM uint32_t PNUM : 6; /*!< [21..16] Parity Error Count */ + uint32_t : 2; + __IM uint32_t FNUM : 6; /*!< [29..24] Framing Error Count */ + uint32_t : 2; + } FRSR_b; + }; + + union + { + __IM uint32_t FTSR; /*!< (@ 0x00000054) FIFO Transmit Status Register */ + + struct + { + __IM uint32_t T : 6; /*!< [5..0] Transmit FIFO Data Count */ + uint32_t : 26; + } FTSR_b; + }; + __IM uint32_t RESERVED3[4]; + + union + { + __OM uint32_t CFCLR; /*!< (@ 0x00000068) Common Flag Clear Register */ + + struct + { + uint32_t : 4; + __OM uint32_t ERSC : 1; /*!< [4..4] ERSC */ + uint32_t : 11; + __OM uint32_t DCMFC : 1; /*!< [16..16] DCMFC */ + __OM uint32_t DPERC : 1; /*!< [17..17] DPERC */ + __OM uint32_t DFERC : 1; /*!< [18..18] DFERC */ + uint32_t : 5; + __OM uint32_t ORERC : 1; /*!< [24..24] ORERC */ + uint32_t : 1; + __OM uint32_t MFFC : 1; /*!< [26..26] MFFC */ + __OM uint32_t PERC : 1; /*!< [27..27] PERC */ + __OM uint32_t FERC : 1; /*!< [28..28] FERC */ + __OM uint32_t TDREC : 1; /*!< [29..29] TDREC */ + uint32_t : 1; + __OM uint32_t RDRFC : 1; /*!< [31..31] RDRFC */ + } CFCLR_b; + }; + + union + { + __OM uint32_t ICFCLR; /*!< (@ 0x0000006C) Simple I2C Flag Clear Register */ + + struct + { + uint32_t : 3; + __OM uint32_t IICSTIFC : 1; /*!< [3..3] IICSTIFC */ + uint32_t : 28; + } ICFCLR_b; + }; + + union + { + __OM uint32_t FFCLR; /*!< (@ 0x00000070) FIFO Flag Clear Register */ + + struct + { + __OM uint32_t DRC : 1; /*!< [0..0] DRC */ + uint32_t : 31; + } FFCLR_b; + }; +} R_SCI0_Type; /*!< Size = 116 (0x74) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Peripheral Interface 0 (R_SPI0) + */ + +typedef struct /*!< (@ 0x80003000) R_SPI0 Structure */ +{ + union + { + union + { + __IOM uint32_t SPDR; /*!< (@ 0x00000000) SPI Data Register */ + + struct + { + __IOM uint32_t SPD : 32; /*!< [31..0] The SPI data register (SPDR) is used to store SPI's + * transmit data and receive data. Transmit buffers and receive + * buffers independently function. */ + } SPDR_b; + }; + __IOM uint16_t SPDR_HA; /*!< (@ 0x00000000) SPI Data Register */ + __IOM uint8_t SPDR_BY; /*!< (@ 0x00000000) SPI Data Register */ + }; + + union + { + __IOM uint8_t SPCKD; /*!< (@ 0x00000004) SPI Clock Delay Register */ + + struct + { + __IOM uint8_t SCKDL : 3; /*!< [2..0] RSPCK Delay Setting */ + uint8_t : 5; + } SPCKD_b; + }; + + union + { + __IOM uint8_t SSLND; /*!< (@ 0x00000005) SPI Slave Select Negation Delay Register */ + + struct + { + __IOM uint8_t SLNDL : 3; /*!< [2..0] SSL Negation Delay Bits */ + uint8_t : 5; + } SSLND_b; + }; + + union + { + __IOM uint8_t SPND; /*!< (@ 0x00000006) SPI Next-Access Delay Register */ + + struct + { + __IOM uint8_t SPNDL : 3; /*!< [2..0] SPI Next-Access Delay Bits */ + uint8_t : 5; + } SPND_b; + }; + + union + { + __IOM uint8_t MRCKD; /*!< (@ 0x00000007) SPI ClocK Digital control Register for Master + * Receive */ + + struct + { + __IOM uint8_t ARST : 3; /*!< [2..0] Receive Sampling Timing Adjustment Bits */ + uint8_t : 5; + } MRCKD_b; + }; + + union + { + __IOM uint32_t SPCR; /*!< (@ 0x00000008) SPI Control Register */ + + struct + { + __IOM uint32_t SPE : 1; /*!< [0..0] SPI Function Enable */ + uint32_t : 6; + __IOM uint32_t SPSCKSEL : 1; /*!< [7..7] SPI Master Receive Clock Select */ + __IOM uint32_t SPPE : 1; /*!< [8..8] Parity Enable */ + __IOM uint32_t SPOE : 1; /*!< [9..9] Parity Mode */ + uint32_t : 1; + __IOM uint32_t PTE : 1; /*!< [11..11] Parity Self-Diagnosis Enable */ + __IOM uint32_t SCKASE : 1; /*!< [12..12] RSPCK Auto-Stop Function Enable */ + __IOM uint32_t BFDS : 1; /*!< [13..13] Between Burst Transfer Frames Delay Select */ + __IOM uint32_t MODFEN : 1; /*!< [14..14] Mode Fault Error Detection Enable */ + uint32_t : 1; + __IOM uint32_t SPEIE : 1; /*!< [16..16] SPI Error Interrupt Enable */ + __IOM uint32_t SPRIE : 1; /*!< [17..17] SPI Receive Buffer Full Interrupt Enable */ + __IOM uint32_t SPIIE : 1; /*!< [18..18] SPI Idle Interrupt Enable */ + __IOM uint32_t SPDRES : 1; /*!< [19..19] SPI Receive Data Ready Error Select */ + __IOM uint32_t SPTIE : 1; /*!< [20..20] SPI Transmit Buffer Empty Interrupt Enable */ + __IOM uint32_t CENDIE : 1; /*!< [21..21] SPI Communication End Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t SPMS : 1; /*!< [24..24] SPI Function Enable */ + __IOM uint32_t SPFRF : 1; /*!< [25..25] SPI Frame Format Select */ + uint32_t : 2; + __IOM uint32_t TXMD : 2; /*!< [29..28] Communication Mode Select */ + __IOM uint32_t MSTR : 1; /*!< [30..30] SPI Master/Slave Mode Select */ + __IOM uint32_t BPEN : 1; /*!< [31..31] Synchronization Circuit Bypass Enable */ + } SPCR_b; + }; + + union + { + __IOM uint8_t SPCRRM; /*!< (@ 0x0000000C) SPI Control Register for Master Receive only */ + + struct + { + __IOM uint8_t RMFM : 5; /*!< [4..0] Frame processing count setting in Master Receive only */ + uint8_t : 1; + __OM uint8_t RMEDTG : 1; /*!< [6..6] Reading value is always 0. */ + __OM uint8_t RMSTTG : 1; /*!< [7..7] Reading value is always 0. */ + } SPCRRM_b; + }; + + union + { + __IOM uint8_t SPDRCR; /*!< (@ 0x0000000D) SPI Control Register for Received Data Ready + * Detection */ + + struct + { + __IOM uint8_t SPDRC : 8; /*!< [7..0] SPDRC */ + } SPDRCR_b; + }; + + union + { + __IOM uint8_t SPPCR; /*!< (@ 0x0000000E) SPI Pin Control Register */ + + struct + { + __IOM uint8_t SPLP : 1; /*!< [0..0] SPI Loopback */ + __IOM uint8_t SPLP2 : 1; /*!< [1..1] SPI Loopback 2 */ + __IOM uint8_t SPOM : 1; /*!< [2..2] SPI Output Pin Mode */ + uint8_t : 1; + __IOM uint8_t MOIFV : 1; /*!< [4..4] MOSI Idle Fixed Value */ + __IOM uint8_t MOIFE : 1; /*!< [5..5] MOSI Idle Value Fixing Enable */ + uint8_t : 2; + } SPPCR_b; + }; + + union + { + __IOM uint8_t SPCR2; /*!< (@ 0x0000000F) SPI Control Register 2 */ + + struct + { + __IOM uint8_t SPSCKDL : 3; /*!< [2..0] SPI Master Receive Clock Analog Delay */ + uint8_t : 5; + } SPCR2_b; + }; + + union + { + __IOM uint8_t SSLP; /*!< (@ 0x00000010) SPI Slave Select Polarity Register */ + + struct + { + __IOM uint8_t SSL0P : 1; /*!< [0..0] SSL0 Signal Polarity Setting */ + __IOM uint8_t SSL1P : 1; /*!< [1..1] SSL1 Signal Polarity Setting */ + __IOM uint8_t SSL2P : 1; /*!< [2..2] SSL2 Signal Polarity Setting */ + __IOM uint8_t SSL3P : 1; /*!< [3..3] SSL3 Signal Polarity Setting */ + uint8_t : 4; + } SSLP_b; + }; + + union + { + __IOM uint8_t SPBR; /*!< (@ 0x00000011) SPI Bit Rate Register */ + + struct + { + __IOM uint8_t SPR : 8; /*!< [7..0] The SPBR register is used to set the bit rate in master + * mode. If SPBR is modified while SPCR.MSTR = 1 and SPCR.SPE + * = 1, subsequent operation is not guaranteed. */ + } SPBR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t SPSCR; /*!< (@ 0x00000013) SPI Sequence Control Register */ + + struct + { + __IOM uint8_t SPSLN : 3; /*!< [2..0] SPI Sequence Length Specification */ + uint8_t : 5; + } SPSCR_b; + }; + + union + { + __IOM uint32_t SPCMD[8]; /*!< (@ 0x00000014) SPI Command Register [0..7] (m = 0 to 7) */ + + struct + { + __IOM uint32_t CPHA : 1; /*!< [0..0] RSPCK Phase */ + __IOM uint32_t CPOL : 1; /*!< [1..1] RSPCK Polarity */ + __IOM uint32_t BRDV : 2; /*!< [3..2] Bit Rate Division */ + uint32_t : 3; + __IOM uint32_t SSLKP : 1; /*!< [7..7] SSL Signal Level Hold */ + uint32_t : 4; + __IOM uint32_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint32_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint32_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint32_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + __IOM uint32_t SPB : 5; /*!< [20..16] SPI Data Length */ + uint32_t : 3; + __IOM uint32_t SSLA : 2; /*!< [25..24] SSL Signal Assertion */ + uint32_t : 6; + } SPCMD_b[8]; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint16_t SPDCR; /*!< (@ 0x00000040) SPI Data Control Register */ + + struct + { + __IOM uint16_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint16_t SLSEL : 2; /*!< [2..1] SSL Pin Output Select */ + __IOM uint16_t SPRDTD : 1; /*!< [3..3] SPI Receive Data or Transmit Data Selection */ + __IOM uint16_t SINV : 1; /*!< [4..4] Serial data invert */ + uint16_t : 3; + __IOM uint16_t SPFC : 2; /*!< [9..8] Frame Count */ + uint16_t : 6; + } SPDCR_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPDCR2; /*!< (@ 0x00000044) SPI Data Control Register 2 */ + + struct + { + __IOM uint16_t RTRG : 2; /*!< [1..0] Receive FIFO threshold setting */ + uint16_t : 6; + __IOM uint16_t TTRG : 2; /*!< [9..8] Transmission FIFO threshold setting */ + uint16_t : 6; + } SPDCR2_b; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[2]; + __IM uint8_t RESERVED5; + + union + { + __IM uint8_t SPSSR; /*!< (@ 0x00000051) SPI Sequence Status Register */ + + struct + { + __IM uint8_t SPCP : 3; /*!< [2..0] SPI Command Pointer */ + uint8_t : 1; + __IM uint8_t SPECM : 3; /*!< [6..4] SPI Error Command */ + uint8_t : 1; + } SPSSR_b; + }; + + union + { + __IM uint16_t SPSR; /*!< (@ 0x00000052) SPI Status Register */ + + struct + { + uint16_t : 7; + __IM uint16_t SPDRF : 1; /*!< [7..7] SPI Receive Data Ready Flag */ + __IM uint16_t OVRF : 1; /*!< [8..8] Overrun Error Flag */ + __IM uint16_t IDLNF : 1; /*!< [9..9] SPI Idle Flag */ + __IM uint16_t MODF : 1; /*!< [10..10] Mode Fault Error Flag */ + __IM uint16_t PERF : 1; /*!< [11..11] Parity Error Flag */ + __IM uint16_t UDRF : 1; /*!< [12..12] Underrun Error Flag */ + __IM uint16_t SPTEF : 1; /*!< [13..13] SPI Transmit Buffer Empty Flag */ + __IM uint16_t CENDF : 1; /*!< [14..14] Communication End Flag */ + __IM uint16_t SPRF : 1; /*!< [15..15] SPI Receive Buffer Full Flag */ + } SPSR_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IM uint8_t SPTFSR; /*!< (@ 0x00000058) SPI Transfer FIFO Status Register */ + + struct + { + __IM uint8_t TFDN : 3; /*!< [2..0] Transmit FIFO data empty stage number */ + uint8_t : 5; + } SPTFSR_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IM uint8_t SPRFSR; /*!< (@ 0x0000005C) SPI Receive FIFO Status Register */ + + struct + { + __IM uint8_t RFDN : 3; /*!< [2..0] Receive FIFO data store stage number */ + uint8_t : 5; + } SPRFSR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + + union + { + __IM uint32_t SPPSR; /*!< (@ 0x00000060) SPI Poling Register */ + + struct + { + __IM uint32_t SPEPS : 1; /*!< [0..0] SPI Polling Status */ + uint32_t : 31; + } SPPSR_b; + }; + __IM uint32_t RESERVED11; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t SPSRC; /*!< (@ 0x0000006A) SPI Status Clear Register */ + + struct + { + uint16_t : 7; + __OM uint16_t SPDRFC : 1; /*!< [7..7] SPI Receive Data Ready Flag Clear */ + __OM uint16_t OVRFC : 1; /*!< [8..8] Overrun Error Flag Clear */ + uint16_t : 1; + __OM uint16_t MODFC : 1; /*!< [10..10] Mode Fault Error Flag Clear */ + __OM uint16_t PERFC : 1; /*!< [11..11] Parity Error Flag Clear */ + __OM uint16_t UDRFC : 1; /*!< [12..12] Underrun Error Flag Clear */ + __OM uint16_t SPTEFC : 1; /*!< [13..13] SPI Transmit Buffer Empty Flag Clear */ + __OM uint16_t CENDFC : 1; /*!< [14..14] Communication End Flag Clear */ + __OM uint16_t SPRFC : 1; /*!< [15..15] SPI Receive Buffer Full Flag Clear */ + } SPSRC_b; + }; + + union + { + __OM uint8_t SPFCR; /*!< (@ 0x0000006C) SPI FIFO Clear Register */ + + struct + { + __OM uint8_t SPFRST : 1; /*!< [0..0] SPI FIFO clear */ + uint8_t : 7; + } SPFCR_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; +} R_SPI0_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CRC Unit 0 (R_CRC0) + */ + +typedef struct /*!< (@ 0x80004000) R_CRC0 Structure */ +{ + union + { + __IOM uint8_t CRCCR0; /*!< (@ 0x00000000) CRC Control Register 0 */ + + struct + { + __IOM uint8_t GPS : 3; /*!< [2..0] CRC Generating Polynomial Switching */ + uint8_t : 3; + __IOM uint8_t LMS : 1; /*!< [6..6] CRC Calculation Switching */ + __OM uint8_t DORCLR : 1; /*!< [7..7] CRCDOR Register Clear */ + } CRCCR0_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + + union + { + __IOM uint32_t CRCDIR; /*!< (@ 0x00000004) CRC Data Input Register */ + __IOM uint8_t CRCDIR_BY; /*!< (@ 0x00000004) CRC Data Input Register */ + }; + + union + { + __IOM uint32_t CRCDOR; /*!< (@ 0x00000008) CRC Data Output Register */ + __IOM uint16_t CRCDOR_HA; /*!< (@ 0x00000008) CRC Data Output Register */ + __IOM uint8_t CRCDOR_BY; /*!< (@ 0x00000008) CRC Data Output Register */ + }; +} R_CRC0_Type; /*!< Size = 12 (0xc) */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/** + * @brief CAN-FD (R_CANFD) + */ + +typedef struct /*!< (@ 0x80020000) R_CANFD Structure */ +{ + __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) CANFD Channel [0..1] Registers */ + __IM uint32_t RESERVED[24]; + + union + { + __IM uint32_t CFDGIPV; /*!< (@ 0x00000080) Global IP Version Register */ + + struct + { + __IM uint32_t IPV : 8; /*!< [7..0] IP Version */ + __IM uint32_t IPT : 2; /*!< [9..8] IP Type */ + uint32_t : 6; + __IM uint32_t PSI : 14; /*!< [29..16] Parameter Status Information */ + uint32_t : 2; + } CFDGIPV_b; + }; + + union + { + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ + + struct + { + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD Message Payload Overflow Configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; + }; + + union + { + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ + + struct + { + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC Check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message Lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD Message Payload Overflow Flag Interrupt Enable */ + __IOM uint32_t QOWEIE : 1; /*!< [12..12] TXQ Message Overwrite Error Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message Lost Error Interrupt Enable */ + __IOM uint32_t MOWEIE : 1; /*!< [15..15] Message Lost Error Interrupt Enable */ + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + uint32_t : 15; + } CFDGCTR_b; + }; + + union + { + __IM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ + + struct + { + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialization */ + uint32_t : 28; + } CFDGSTS_b; + }; + + union + { + __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ + + struct + { + __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ + __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ + __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ + __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD Message Payload Overflow Flag */ + __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message Overwrite Error Status */ + uint32_t : 1; + __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ + __IM uint32_t MOWES : 1; /*!< [7..7] Message Overwrite Error Status */ + uint32_t : 8; + __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ + __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ + uint32_t : 14; + } CFDGERFL_b; + }; + + union + { + __IM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ + + struct + { + __IM uint32_t TS : 16; /*!< [15..0] Timestamp value */ + uint32_t : 16; + } CFDGTSC_b; + }; + + union + { + __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ + + struct + { + __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ + uint32_t : 4; + __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ + uint32_t : 23; + } CFDGAFLECTR_b; + }; + + union + { + __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register + * 0 */ + + struct + { + __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ + uint32_t : 7; + __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ + uint32_t : 7; + } CFDGAFLCFG0_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ + + struct + { + __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ + __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ + uint32_t : 21; + } CFDRMNB_b; + }; + + union + { + __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ + + struct + { + __IOM uint32_t RMNS : 32; /*!< [31..0] RX Message Buffer New Data Status */ + } CFDRMND0_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration/Control Register [0..7] */ + + struct + { + __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ + __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size Configuration */ + uint32_t : 1; + __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ + uint32_t : 1; + __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ + __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ + __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full Interrupt Enable */ + uint32_t : 15; + } CFDRFCC_b[8]; + }; + + union + { + __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Register [0..7] */ + + struct + { + __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ + __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ + __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ + __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ + uint32_t : 4; + __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ + __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ + uint32_t : 15; + } CFDRFSTS_b[8]; + }; + + union + { + __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Register [0..7] */ + + struct + { + __IOM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ + uint32_t : 24; + } CFDRFPCTR_b[8]; + }; + + union + { + __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration/Control Register [0..5] */ + + struct + { + __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ + __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ + __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data Size Configuration */ + uint32_t : 1; + __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ + __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ + __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ + __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ + __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ + __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ + __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ + __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ + } CFDCFCC_b[6]; + }; + __IM uint32_t RESERVED3[18]; + + union + { + __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration/Control Enhancement + * Register [0..5] */ + + struct + { + __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full Interrupt Enable */ + __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ + __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO Message Overwrite Mode */ + uint32_t : 7; + __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ + uint32_t : 15; + } CFDCFCCE_b[6]; + }; + __IM uint32_t RESERVED4[18]; + + union + { + __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Register [0..5] */ + + struct + { + __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ + __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ + __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ + __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ + __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ + uint32_t : 3; + __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ + __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ + __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ + __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ + uint32_t : 5; + __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO Message Overwrite */ + uint32_t : 7; + } CFDCFSTS_b[6]; + }; + __IM uint32_t RESERVED5[18]; + + union + { + __OM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Register [0..5] */ + + struct + { + __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ + uint32_t : 24; + } CFDCFPCTR_b[6]; + }; + __IM uint32_t RESERVED6[18]; + + union + { + __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ + + struct + { + __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIFO Empty Status */ + __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIFO Empty Status */ + uint32_t : 18; + } CFDFESTS_b; + }; + + union + { + __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ + + struct + { + __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIFO Full Status */ + __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIFO Full Status */ + uint32_t : 18; + } CFDFFSTS_b; + }; + + union + { + __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ + + struct + { + __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Message Lost Status */ + __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Message Lost Status */ + uint32_t : 18; + } CFDFMSTS_b; + }; + + union + { + __IM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ + + struct + { + __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ + uint32_t : 8; + __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ + uint32_t : 8; + } CFDRFISTS_b; + }; + + union + { + __IM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFRISTS_b; + }; + + union + { + __IM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ + + struct + { + __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO One Frame RX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFRISTS_b; + }; + + union + { + __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status + * Register */ + + struct + { + __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO One Frame TX Interrupt Flag Status */ + uint32_t : 26; + } CFDCFOFTISTS_b; + }; + + union + { + __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Overwrite Status Register */ + + struct + { + __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO Massage Overwrite Status */ + uint32_t : 26; + } CFDCFMOWSTS_b; + }; + + union + { + __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ + + struct + { + __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC Level Full Status */ + __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC Level Full Status */ + uint32_t : 18; + } CFDFFFSTS_b; + }; + __IM uint32_t RESERVED7[2]; + + union + { + __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Register [0..127] */ + + struct + { + __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ + __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission Abort Request */ + __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ + uint8_t : 5; + } CFDTMC_b[128]; + }; + __IM uint32_t RESERVED8[288]; + + union + { + __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Register [0..127] */ + + struct + { + __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ + __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ + __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ + __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission Abort Request Mirrored */ + uint8_t : 3; + } CFDTMSTS_b[128]; + }; + __IM uint32_t RESERVED9[288]; + + union + { + __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status + * Register [0..3] */ + + struct + { + __IM uint32_t TMTRSTS : 16; /*!< [15..0] TX Message Buffer Transmission Request Status */ + uint32_t : 16; + } CFDTMTRSTS_b[4]; + }; + __IM uint32_t RESERVED10[36]; + + union + { + __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request + * Status Register [0..3] */ + + struct + { + __IM uint32_t TMTARSTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Request Status */ + uint32_t : 16; + } CFDTMTARSTS_b[4]; + }; + __IM uint32_t RESERVED11[36]; + + union + { + __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status + * Register [0..3] */ + + struct + { + __IM uint32_t TMTCSTS : 16; /*!< [15..0] TX Message Buffer Transmission Completion Status */ + uint32_t : 16; + } CFDTMTCSTS_b[4]; + }; + __IM uint32_t RESERVED12[36]; + + union + { + __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register + * [0..3] */ + + struct + { + __IM uint32_t TMTASTS : 16; /*!< [15..0] TX Message Buffer Transmission Abort Status */ + uint32_t : 16; + } CFDTMTASTS_b[4]; + }; + __IM uint32_t RESERVED13[36]; + + union + { + __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Transmission Interrupt Enable + * Register [0..3] */ + + struct + { + __IOM uint32_t TMIE : 16; /*!< [15..0] TX Message Buffer Interrupt Enable */ + uint32_t : 16; + } CFDTMIEC_b[4]; + }; + __IM uint32_t RESERVED14[40]; + + union + { + __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration/Control Register 0[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC0_b[2]; + }; + __IM uint32_t RESERVED15[6]; + + union + { + __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Register 0[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS0_b[2]; + }; + __IM uint32_t RESERVED16[6]; + + union + { + __OM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Register 0[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR0_b[2]; + }; + __IM uint32_t RESERVED17[6]; + + union + { + __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration/Control Register 1[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC1_b[2]; + }; + __IM uint32_t RESERVED18[6]; + + union + { + __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Register 1[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS1_b[2]; + }; + __IM uint32_t RESERVED19[6]; + + union + { + __OM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Register 1[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR1_b[2]; + }; + __IM uint32_t RESERVED20[6]; + + union + { + __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration/Control Register 2[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 3; + __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ + __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC2_b[2]; + }; + __IM uint32_t RESERVED21[6]; + + union + { + __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Register 2[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 2; + __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ + __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS2_b[2]; + }; + __IM uint32_t RESERVED22[6]; + + union + { + __OM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Register 2[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR2_b[2]; + }; + __IM uint32_t RESERVED23[6]; + + union + { + __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration/Control Register 3[0..1] */ + + struct + { + __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ + uint32_t : 1; + __IOM uint32_t TXQOWE : 1; /*!< [2..2] TX Queue Overwrite Mode Enable */ + uint32_t : 2; + __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ + uint32_t : 1; + __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ + __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ + uint32_t : 5; + __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ + uint32_t : 13; + } CFDTXQCC3_b[2]; + }; + __IM uint32_t RESERVED24[6]; + + union + { + __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Register 3[0..1] */ + + struct + { + __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ + __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ + __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ + uint32_t : 5; + __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ + uint32_t : 4; + __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ + uint32_t : 1; + __IOM uint32_t TXQMOW : 1; /*!< [20..20] TXQ Message Overwrite */ + uint32_t : 11; + } CFDTXQSTS3_b[2]; + }; + __IM uint32_t RESERVED25[6]; + + union + { + __OM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Register 3[0..1] */ + + struct + { + __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ + uint32_t : 24; + } CFDTXQPCTR3_b[2]; + }; + __IM uint32_t RESERVED26[6]; + + union + { + __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ + + struct + { + __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ Empty Status */ + uint32_t : 24; + } CFDTXQESTS_b; + }; + + union + { + __IM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status Flag for Channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status Flag for Channel 1 */ + uint32_t : 25; + } CFDTXQFISTS_b; + }; + + union + { + __IM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ + + struct + { + __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ Message Lost Status Flag for Channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ Message Lost Status Flag for Channel 1 */ + uint32_t : 25; + } CFDTXQMSTS_b; + }; + __IM uint32_t RESERVED27; + + union + { + __IM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for Channel 0 */ + __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for Channel 1 */ + uint32_t : 24; + } CFDTXQISTS_b; + }; + + union + { + __IM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for Channel 0 */ + __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for Channel 1 */ + uint32_t : 24; + } CFDTXQOFTISTS_b; + }; + + union + { + __IM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ + + struct + { + __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag for Channel 0 */ + uint32_t : 1; + __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag for Channel 1 */ + uint32_t : 25; + } CFDTXQOFRISTS_b; + }; + + union + { + __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ + + struct + { + __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for Channel 0 */ + __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for Channel 1 */ + uint32_t : 24; + } CFDTXQFSTS_b; + }; + __IM uint32_t RESERVED28[24]; + + union + { + __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration/Control Register + * [0..1] */ + + struct + { + __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ + uint32_t : 7; + __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ + __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ + __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ + __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated Gateway Enable */ + uint32_t : 20; + } CFDTHLCC_b[2]; + }; + __IM uint32_t RESERVED29[6]; + + union + { + __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register [0..1] */ + + struct + { + __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ + __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ + __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ + __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ + uint32_t : 4; + __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ + uint32_t : 18; + } CFDTHLSTS_b[2]; + }; + __IM uint32_t RESERVED30[6]; + + union + { + __OM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Register [0..1] */ + + struct + { + __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ + uint32_t : 24; + } CFDTHLPCTR_b[2]; + }; + __IM uint32_t RESERVED31[46]; + + union + { + __IM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ + + struct + { + __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ + __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ + __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ + __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ + __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ + __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel + * 0 */ + __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel + * 0 */ + uint32_t : 1; + __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ + __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ + __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ + __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ + __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ + __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel + * 1 */ + __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel + * 1 */ + uint32_t : 17; + } CFDGTINTSTS0_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ + + struct + { + __IOM uint32_t C0ICBCE : 1; /*!< [0..0] Channel 0 Internal CAN Bus Communication Test Mode Enable */ + __IOM uint32_t C1ICBCE : 1; /*!< [1..1] Channel 1 Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 14; + __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ + uint32_t : 6; + } CFDGTSTCFG_b; + }; + + union + { + __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ + + struct + { + __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ + uint32_t : 1; + __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ + uint32_t : 29; + } CFDGTSTCTR_b; + }; + __IM uint32_t RESERVED33; + + union + { + __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration Register */ + + struct + { + __IOM uint32_t RPED : 1; /*!< [0..0] RES Bit Protocol Exception Disable */ + uint32_t : 7; + __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp Capture Configuration */ + uint32_t : 22; + } CFDGFDCFG_b; + }; + __IM uint32_t RESERVED34; + + union + { + __OM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ + + struct + { + __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ + uint32_t : 16; + } CFDGLOCKK_b; + }; + __IM uint32_t RESERVED35[4]; + + union + { + __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ + + struct + { + __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RX FIFO 0 */ + __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RX FIFO 1 */ + __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RX FIFO 2 */ + __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RX FIFO 3 */ + __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RX FIFO 4 */ + __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RX FIFO 5 */ + __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RX FIFO 6 */ + __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RX FIFO 7 */ + __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of Channel 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of Channel 1 */ + uint32_t : 22; + } CFDCDTCT_b; + }; + + union + { + __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ + + struct + { + __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ + __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ + __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ + __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ + __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ + __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ + __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ + __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ + __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of Channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of Channel + * 1 */ + uint32_t : 22; + } CFDCDTSTS_b; + }; + __IM uint32_t RESERVED36[2]; + + union + { + __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ + + struct + { + __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of Channel 0 */ + __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of Channel 1 */ + uint32_t : 6; + __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of Channel 0 */ + __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of Channel 1 */ + uint32_t : 6; + __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of Channel + * 0 */ + __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of Channel + * 1 */ + uint32_t : 14; + } CFDCDTTCT_b; + }; + + union + { + __IM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ + + struct + { + __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of Channel 0 */ + __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of Channel 1 */ + uint32_t : 6; + __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of Channel 0 */ + __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of Channel 1 */ + uint32_t : 6; + __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status for Common FIFO 2 of Channel + * 0 */ + __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status for Common FIFO 2 of Channel + * 1 */ + uint32_t : 14; + } CFDCDTTSTS_b; + }; + __IM uint32_t RESERVED37[2]; + + union + { + __IM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register [0..1] */ + + struct + { + __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 1; + __IM uint32_t BQFIF : 2; /*!< [5..4] Borrowed TXQ Full Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 2; + __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 1; + __IM uint32_t BQOFRIF : 2; /*!< [13..12] Borrowed TXQ One Frame RX Interrupt Flag Channel n + * (n = 0, 1) */ + uint32_t : 2; + __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n (n = 0, 1) */ + uint32_t : 5; + __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC Level Full Interrupt Flag Channel n + * (n = 0, 1) */ + uint32_t : 1; + __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n (n + * = 0, 1) */ + uint32_t : 1; + } CFDGRINTSTS_b[2]; + }; + __IM uint32_t RESERVED38[10]; + + union + { + __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global Reset Control Register */ + + struct + { + __IOM uint32_t SRST : 1; /*!< [0..0] Software Reset */ + uint32_t : 7; + __OM uint32_t KEY : 8; /*!< [15..8] Key Code */ + uint32_t : 16; + } CFDGRSTC_b; + }; + + union + { + __IOM uint32_t CFDGFCMC; /*!< (@ 0x00001384) Global Flexible CAN Mode Configuration Register */ + + struct + { + __IOM uint32_t FLXC0 : 1; /*!< [0..0] Flexible CAN Mode between Channel 0 and Channel 1 */ + uint32_t : 31; + } CFDGFCMC_b; + }; + __IM uint32_t RESERVED39; + + union + { + __IOM uint32_t CFDGFTBAC; /*!< (@ 0x0000138C) Global Flexible Transmission Buffer Assignment + * Configuration Register */ + + struct + { + __IOM uint32_t FLXMB0 : 4; /*!< [3..0] Flexible Transmission Buffer Assignment between Channel + * 0 and Channel 1 */ + uint32_t : 28; + } CFDGFTBAC_b; + }; + __IM uint32_t RESERVED40[28]; + __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ + __IM uint32_t RESERVED41[240]; + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED42[448]; + __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED43[3072]; + __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ + __IM uint32_t RESERVED44[1600]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ + __IM uint32_t RESERVED45[252]; + + union + { + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Register [0..63] */ + + struct + { + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + } CFDRPGACC_b[64]; + }; + __IM uint32_t RESERVED46[7872]; + __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Registers */ +} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ + +/* =========================================================================================================================== */ +/* ================ R_CMT ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Compare Match Timer Control (R_CMT) + */ + +typedef struct /*!< (@ 0x80040000) R_CMT Structure */ +{ + __IOM R_CMT_UNT_Type UNT[3]; /*!< (@ 0x00000000) 3 Timer Start Register Units */ +} R_CMT_Type; /*!< Size = 3072 (0xc00) */ + +/* =========================================================================================================================== */ +/* ================ R_CMTW0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Compare Match Timer W (R_CMTW0) + */ + +typedef struct /*!< (@ 0x80041000) R_CMTW0 Structure */ +{ + union + { + __IOM uint16_t CMWSTR; /*!< (@ 0x00000000) Timer Start Register */ + + struct + { + __IOM uint16_t STR : 1; /*!< [0..0] Counter Start */ + uint16_t : 15; + } CMWSTR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CMWCR; /*!< (@ 0x00000004) Timer Control Register */ + + struct + { + __IOM uint16_t CKS : 2; /*!< [1..0] Clock Select */ + uint16_t : 1; + __IOM uint16_t CMWIE : 1; /*!< [3..3] Compare Match Interrupt Enable */ + __IOM uint16_t IC0IE : 1; /*!< [4..4] Input Capture 0 Interrupt Enable */ + __IOM uint16_t IC1IE : 1; /*!< [5..5] Input Capture 1 Interrupt Enable */ + __IOM uint16_t OC0IE : 1; /*!< [6..6] Output Compare 0 Interrupt Enable */ + __IOM uint16_t OC1IE : 1; /*!< [7..7] Output Compare 1 Interrupt Enable */ + uint16_t : 1; + __IOM uint16_t CMS : 1; /*!< [9..9] Timer Counter Size */ + uint16_t : 3; + __IOM uint16_t CCLR : 3; /*!< [15..13] Counter Clear */ + } CMWCR_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t CMWIOR; /*!< (@ 0x00000008) Timer I/O Control Register */ + + struct + { + __IOM uint16_t IC0 : 2; /*!< [1..0] Input Capture Control 0 */ + __IOM uint16_t IC1 : 2; /*!< [3..2] Input Capture Control 1 */ + __IOM uint16_t IC0E : 1; /*!< [4..4] Input Capture Enable 0 */ + __IOM uint16_t IC1E : 1; /*!< [5..5] Input Capture Enable 1 */ + uint16_t : 2; + __IOM uint16_t OC0 : 2; /*!< [9..8] Output Compare Control 0 */ + __IOM uint16_t OC1 : 2; /*!< [11..10] Output Compare Control 1 */ + __IOM uint16_t OC0E : 1; /*!< [12..12] Compare Match Enable 0 */ + __IOM uint16_t OC1E : 1; /*!< [13..13] Compare Match Enable 1 */ + uint16_t : 1; + __IOM uint16_t CMWE : 1; /*!< [15..15] Compare Match Enable */ + } CMWIOR_b; + }; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3; + __IOM uint32_t CMWCNT; /*!< (@ 0x00000010) Timer Counter */ + __IOM uint32_t CMWCOR; /*!< (@ 0x00000014) Compare Match Constant Register */ + __IM uint32_t CMWICR0; /*!< (@ 0x00000018) Input Capture Registers */ + __IM uint32_t CMWICR1; /*!< (@ 0x0000001C) Input Capture Registers */ + __IOM uint32_t CMWOCR0; /*!< (@ 0x00000020) Output Compare Registers */ + __IOM uint32_t CMWOCR1; /*!< (@ 0x00000024) Output Compare Registers */ +} R_CMTW0_Type; /*!< Size = 40 (0x28) */ + +/* =========================================================================================================================== */ +/* ================ R_WDT0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Watchdog Timer 0 (R_WDT0) + */ + +typedef struct /*!< (@ 0x80042000) R_WDT0 Structure */ +{ + __IOM uint8_t WDTRR; /*!< (@ 0x00000000) WDT Refresh Register */ + __IM uint8_t RESERVED; + + union + { + __IOM uint16_t WDTCR; /*!< (@ 0x00000002) WDT Control Register */ + + struct + { + __IOM uint16_t TOPS : 2; /*!< [1..0] Timeout Period Selection */ + uint16_t : 2; + __IOM uint16_t CKS : 4; /*!< [7..4] Clock Division Ratio Selection */ + __IOM uint16_t RPES : 2; /*!< [9..8] Window End Position Selection */ + uint16_t : 2; + __IOM uint16_t RPSS : 2; /*!< [13..12] Window Start Position Selection */ + uint16_t : 2; + } WDTCR_b; + }; + + union + { + __IOM uint16_t WDTSR; /*!< (@ 0x00000004) WDT Status Register */ + + struct + { + __IM uint16_t CNTVAL : 14; /*!< [13..0] Down-Counter Value */ + __IOM uint16_t UNDFF : 1; /*!< [14..14] Underflow Flag */ + __IOM uint16_t REFEF : 1; /*!< [15..15] Refresh Error Flag */ + } WDTSR_b; + }; + + union + { + __IOM uint8_t WDTRCR; /*!< (@ 0x00000006) WDT Reset Control Register */ + + struct + { + uint8_t : 7; + __IOM uint8_t RSTIRQS : 1; /*!< [7..7] Reset Interrupt Request Selection */ + } WDTRCR_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_WDT0_Type; /*!< Size = 10 (0xa) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I2C Bus Interface 0 (R_IIC0) + */ + +typedef struct /*!< (@ 0x80043000) R_IIC0 Structure */ +{ + union + { + __IOM uint8_t ICCR1; /*!< (@ 0x00000000) I2C Bus Control Register 1 */ + + struct + { + __IM uint8_t SDAI : 1; /*!< [0..0] SDA Line Monitor */ + __IM uint8_t SCLI : 1; /*!< [1..1] SCL Line Monitor */ + __IOM uint8_t SDAO : 1; /*!< [2..2] SDA Output Control/Monitor */ + __IOM uint8_t SCLO : 1; /*!< [3..3] SCL Output Control/Monitor */ + __OM uint8_t SOWP : 1; /*!< [4..4] SCLO/SDAO Write Protect */ + __IOM uint8_t CLO : 1; /*!< [5..5] Extra SCL Clock Cycle Output */ + __IOM uint8_t IICRST : 1; /*!< [6..6] IIC-Bus Interface Internal Reset */ + __IOM uint8_t ICE : 1; /*!< [7..7] IIC-Bus Interface Enable */ + } ICCR1_b; + }; + + union + { + __IOM uint8_t ICCR2; /*!< (@ 0x00000001) I2C Bus Control Register 2 */ + + struct + { + uint8_t : 1; + __IOM uint8_t ST : 1; /*!< [1..1] Start Condition Issuance Request */ + __IOM uint8_t RS : 1; /*!< [2..2] Restart Condition Issuance Request */ + __IOM uint8_t SP : 1; /*!< [3..3] Stop Condition Issuance Request */ + uint8_t : 1; + __IOM uint8_t TRS : 1; /*!< [5..5] Transmit/Receive Mode */ + __IOM uint8_t MST : 1; /*!< [6..6] Master/Slave Mode */ + __IM uint8_t BBSY : 1; /*!< [7..7] Bus Busy Detection Flag */ + } ICCR2_b; + }; + + union + { + __IOM uint8_t ICMR1; /*!< (@ 0x00000002) I2C Bus Mode Register 1 */ + + struct + { + __IOM uint8_t BC : 3; /*!< [2..0] Bit Counter */ + __OM uint8_t BCWP : 1; /*!< [3..3] BC Write Protect */ + __IOM uint8_t CKS : 3; /*!< [6..4] Internal Reference Clock Select */ + __IOM uint8_t MTWP : 1; /*!< [7..7] MST/TRS Write Protect */ + } ICMR1_b; + }; + + union + { + __IOM uint8_t ICMR2; /*!< (@ 0x00000003) I2C Bus Mode Register 2 */ + + struct + { + __IOM uint8_t TMOS : 1; /*!< [0..0] Timeout Detection Time Select */ + __IOM uint8_t TMOL : 1; /*!< [1..1] Timeout L Count Control */ + __IOM uint8_t TMOH : 1; /*!< [2..2] Timeout H Count Control */ + uint8_t : 1; + __IOM uint8_t SDDL : 3; /*!< [6..4] SDA Output Delay Counter */ + __IOM uint8_t DLCS : 1; /*!< [7..7] SDA Output Delay Clock Source Select */ + } ICMR2_b; + }; + + union + { + __IOM uint8_t ICMR3; /*!< (@ 0x00000004) I2C Bus Mode Register 3 */ + + struct + { + __IOM uint8_t NF : 2; /*!< [1..0] Noise Filter Stage Select */ + __IM uint8_t ACKBR : 1; /*!< [2..2] Receive Acknowledge */ + __IOM uint8_t ACKBT : 1; /*!< [3..3] Transmit Acknowledge */ + __IOM uint8_t ACKWP : 1; /*!< [4..4] ACKBT Write Protect */ + __IOM uint8_t RDRFS : 1; /*!< [5..5] RDRF Flag Set Timing Select */ + __IOM uint8_t WAIT : 1; /*!< [6..6] WAIT */ + __IOM uint8_t SMBS : 1; /*!< [7..7] SMBus/IIC-Bus Select */ + } ICMR3_b; + }; + + union + { + __IOM uint8_t ICFER; /*!< (@ 0x00000005) I2C Bus Function Enable Register */ + + struct + { + __IOM uint8_t TMOE : 1; /*!< [0..0] Timeout Function Enable */ + __IOM uint8_t MALE : 1; /*!< [1..1] Master Arbitration-Lost Detection Enable */ + __IOM uint8_t NALE : 1; /*!< [2..2] NACK Transmission Arbitration-Lost Detection Enable */ + __IOM uint8_t SALE : 1; /*!< [3..3] Slave Arbitration-Lost Detection Enable */ + __IOM uint8_t NACKE : 1; /*!< [4..4] NACK Reception Transfer Suspension Enable */ + __IOM uint8_t NFE : 1; /*!< [5..5] Digital Noise Filter Circuit Enable */ + __IOM uint8_t SCLE : 1; /*!< [6..6] SCL Synchronous Circuit Enable */ + uint8_t : 1; + } ICFER_b; + }; + + union + { + __IOM uint8_t ICSER; /*!< (@ 0x00000006) I2C Bus Status Enable Register */ + + struct + { + __IOM uint8_t SAR0E : 1; /*!< [0..0] Slave Address Register 0 Enable */ + __IOM uint8_t SAR1E : 1; /*!< [1..1] Slave Address Register 1 Enable */ + __IOM uint8_t SAR2E : 1; /*!< [2..2] Slave Address Register 2 Enable */ + __IOM uint8_t GCAE : 1; /*!< [3..3] General Call Address Enable */ + uint8_t : 1; + __IOM uint8_t DIDE : 1; /*!< [5..5] Device ID Address Detection Enable */ + uint8_t : 1; + __IOM uint8_t HOAE : 1; /*!< [7..7] Host Address Enable */ + } ICSER_b; + }; + + union + { + __IOM uint8_t ICIER; /*!< (@ 0x00000007) I2C Bus Interrupt Enable Register */ + + struct + { + __IOM uint8_t TMOIE : 1; /*!< [0..0] Timeout Interrupt Request Enable */ + __IOM uint8_t ALIE : 1; /*!< [1..1] Arbitration-Lost Interrupt Request Enable */ + __IOM uint8_t STIE : 1; /*!< [2..2] Start Condition Detection Interrupt Request Enable */ + __IOM uint8_t SPIE : 1; /*!< [3..3] Stop Condition Detection Interrupt Request Enable */ + __IOM uint8_t NAKIE : 1; /*!< [4..4] NACK Reception Interrupt Request Enable */ + __IOM uint8_t RIE : 1; /*!< [5..5] Receive Data Full Interrupt Request Enable */ + __IOM uint8_t TEIE : 1; /*!< [6..6] Transmit End Interrupt Request Enable */ + __IOM uint8_t TIE : 1; /*!< [7..7] Transmit Data Empty Interrupt Request Enable */ + } ICIER_b; + }; + + union + { + __IOM uint8_t ICSR1; /*!< (@ 0x00000008) I2C Bus Status Register 1 */ + + struct + { + __IOM uint8_t AAS0 : 1; /*!< [0..0] Slave Address 0 Detection Flag */ + __IOM uint8_t AAS1 : 1; /*!< [1..1] Slave Address 1 Detection Flag */ + __IOM uint8_t AAS2 : 1; /*!< [2..2] Slave Address 2 Detection Flag */ + __IOM uint8_t GCA : 1; /*!< [3..3] General Call Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t DID : 1; /*!< [5..5] Device ID Address Detection Flag */ + uint8_t : 1; + __IOM uint8_t HOA : 1; /*!< [7..7] Host Address Detection Flag */ + } ICSR1_b; + }; + + union + { + __IOM uint8_t ICSR2; /*!< (@ 0x00000009) I2C Bus Status Register 2 */ + + struct + { + __IOM uint8_t TMOF : 1; /*!< [0..0] Timeout Detection Flag */ + __IOM uint8_t AL : 1; /*!< [1..1] Arbitration-Lost Flag */ + __IOM uint8_t START : 1; /*!< [2..2] Start Condition Detection Flag */ + __IOM uint8_t STOP : 1; /*!< [3..3] Stop Condition Detection Flag */ + __IOM uint8_t NACKF : 1; /*!< [4..4] NACK Detection Flag */ + __IOM uint8_t RDRF : 1; /*!< [5..5] Receive Data Full Flag */ + __IOM uint8_t TEND : 1; /*!< [6..6] Transmit End Flag */ + __IM uint8_t TDRE : 1; /*!< [7..7] Transmit Data Empty Flag */ + } ICSR2_b; + }; + __IOM R_IIC0_SAR_Type SAR[3]; /*!< (@ 0x0000000A) Slave Address Registers */ + + union + { + __IOM uint8_t ICBRL; /*!< (@ 0x00000010) I2C Bus Bit Rate Low-Level Register */ + + struct + { + __IOM uint8_t BRL : 5; /*!< [4..0] Bit Rate Low-Level Period */ + uint8_t : 3; + } ICBRL_b; + }; + + union + { + __IOM uint8_t ICBRH; /*!< (@ 0x00000011) I2C Bus Bit Rate High-Level Register */ + + struct + { + __IOM uint8_t BRH : 5; /*!< [4..0] Bit Rate High-Level Period */ + uint8_t : 3; + } ICBRH_b; + }; + __IOM uint8_t ICDRT; /*!< (@ 0x00000012) I2C Bus Transmit Data Register */ + __IM uint8_t ICDRR; /*!< (@ 0x00000013) I2C Bus Receive Data Register */ +} R_IIC0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Data Operation Circuit (R_DOC) + */ + +typedef struct /*!< (@ 0x80044000) R_DOC Structure */ +{ + union + { + __IOM uint8_t DOCR; /*!< (@ 0x00000000) DOC Control Register */ + + struct + { + __IOM uint8_t OMS : 2; /*!< [1..0] Operating Mode Select */ + __IOM uint8_t DCSEL : 1; /*!< [2..2] Detection Condition Select */ + uint8_t : 1; + __IOM uint8_t DOPCIE : 1; /*!< [4..4] Data Operation Circuit Interrupt Enable */ + __IM uint8_t DOPCF : 1; /*!< [5..5] Data Operation Circuit Flag */ + __OM uint8_t DOPCFCL : 1; /*!< [6..6] DOPCF Flag Clear */ + uint8_t : 1; + } DOCR_b; + }; + __IM uint8_t RESERVED; + __IOM uint16_t DODIR; /*!< (@ 0x00000002) DOC Data Input Register */ + __IOM uint16_t DODSR; /*!< (@ 0x00000004) DOC Data Setting Register */ +} R_DOC_Type; /*!< Size = 6 (0x6) */ + +/* =========================================================================================================================== */ +/* ================ R_ADC121 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief 12-Bit A/D converter (R_ADC121) + */ + +typedef struct /*!< (@ 0x80045000) R_ADC121 Structure */ +{ + union + { + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ + + struct + { + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel Select */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + uint16_t : 2; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D conversion Start */ + } ADCSR_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t ADANSA0; /*!< (@ 0x00000004) A/D Channel Select Register A0 */ + + struct + { + __IOM uint16_t ANSA0 : 8; /*!< [7..0] A/D conversion Analog input Channel Select */ + uint16_t : 8; + } ADANSA0_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t ADADS0; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Function + * Channel Select Register 0 */ + + struct + { + __IOM uint16_t ADS0 : 8; /*!< [7..0] A/D-Converted Value Addition/Average Channel Select */ + uint16_t : 8; + } ADADS0_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ + + struct + { + __IOM uint8_t ADC : 3; /*!< [2..0] Addition Count Select */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable */ + } ADADC_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ + + struct + { + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 2; + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 9; + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group B */ + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger Select */ + uint16_t : 2; + } ADSTRGR_b; + }; + __IM uint16_t RESERVED4; + + union + { + __IOM uint16_t ADANSB0; /*!< (@ 0x00000014) A/D Channel Select Register B0 */ + + struct + { + __IOM uint16_t ANSB0 : 8; /*!< [7..0] A/D Conversion Analog Input Channel Select */ + uint16_t : 8; + } ADANSB0_b; + }; + __IM uint16_t RESERVED5; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t DBLDR : 16; /*!< [15..0] The result of A/D conversion in response to the second + * trigger in double trigger mode. */ + } ADDBLDR_b; + }; + __IM uint16_t RESERVED6[3]; + + union + { + __IM uint16_t ADDR[8]; /*!< (@ 0x00000020) A/D Data Register n (n = 0 to 3 for unit 0, n + * = 0 to 7 for unit1) */ + + struct + { + __IM uint16_t DR : 16; /*!< [15..0] The result of A/D conversion (n: Number of channel) */ + } ADDR_b[8]; + }; + __IM uint16_t RESERVED7[27]; + + union + { + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Control Register */ + + struct + { + __IOM uint16_t SSTSH : 8; /*!< [7..0] Sample and hold period setting */ + __IOM uint16_t SHANS : 3; /*!< [10..8] Sample and hold use or bypass select for ch0-2 */ + uint16_t : 5; + } ADSHCR_b; + }; + __IM uint16_t RESERVED8[10]; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t ADELCCR; /*!< (@ 0x0000007D) A/D Event Link Control Register */ + + struct + { + __IOM uint8_t ELCC : 2; /*!< [1..0] Event link control bits */ + __IOM uint8_t GCELC : 1; /*!< [2..2] Event control bit for Group C */ + uint8_t : 5; + } ADELCCR_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ + + struct + { + __IOM uint16_t PGS : 1; /*!< [0..0] Group Priority Control Setting */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting */ + uint16_t : 12; + __IOM uint16_t LGRRS : 1; /*!< [14..14] Restart Channel Select */ + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start */ + } ADGSPCR_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplication Register A */ + + struct + { + __IM uint16_t DBLDRA : 16; /*!< [15..0] The result of A/D conversion during extended operation + * in double trigger mode */ + } ADDBLDRA_b; + }; + + union + { + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplication Register B */ + + struct + { + __IM uint16_t DBLDRB : 16; /*!< [15..0] The result of A/D conversion during extended operation + * in double trigger mode */ + } ADDBLDRB_b; + }; + __IM uint16_t RESERVED12[2]; + + union + { + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitoring + * Register */ + + struct + { + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitor */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparing result monitor for window A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparing result monitor for window B */ + uint8_t : 2; + } ADWINMON_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ + + struct + { + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B combination condition setting */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Window B operation permission */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Window A operation permission */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare window B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function enable */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare window A Interrupt Enable */ + } ADCMPCR_b; + }; + __IM uint16_t RESERVED15; + + union + { + __IOM uint16_t ADCMPANSR0; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register 0 */ + + struct + { + __IOM uint16_t CMPCHA0 : 8; /*!< [7..0] Window A Channel Select */ + uint16_t : 8; + } ADCMPANSR0_b; + }; + __IM uint16_t RESERVED16; + + union + { + __IOM uint16_t ADCMPLR0; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register 0 */ + + struct + { + __IOM uint16_t CMPLCHA0 : 8; /*!< [7..0] Window A comparison condition for target channel (ch0-7) + * setting */ + uint16_t : 8; + } ADCMPLR0_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Comparison Function Window A Lower Level + * Setting Register */ + + struct + { + __IOM uint16_t CMPLLA : 16; /*!< [15..0] Reference data setting when using the compare function + * window A */ + } ADCMPDR0_b; + }; + + union + { + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) AD Comparison Function Window A Upper Level Setting + * Register */ + + struct + { + __IOM uint16_t CMPULA : 16; /*!< [15..0] Reference data setting when using the compare function + * window A */ + } ADCMPDR1_b; + }; + + union + { + __IOM uint16_t ADCMPSR0; /*!< (@ 0x000000A0) A/D Comparison Function Window A Channel Status + * Register 0 */ + + struct + { + __IOM uint16_t CMPSTCHA0 : 8; /*!< [7..0] Window A Status Flag */ + uint16_t : 8; + } ADCMPSR0_b; + }; + __IM uint16_t RESERVED18[2]; + + union + { + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Select + * Register */ + + struct + { + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Window B Channel Select */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Window B Comparison Condition Setting */ + } ADCMPBNSR_b; + }; + __IM uint8_t RESERVED19; + + union + { + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t CMPLLB : 16; /*!< [15..0] Reference lower data setting when using the compare + * function window B */ + } ADWINLLB_b; + }; + + union + { + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ + + struct + { + __IOM uint16_t CMPULB : 16; /*!< [15..0] Reference upper data setting when using the compare + * function window B */ + } ADWINULB_b; + }; + + union + { + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ + + struct + { + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Window B Flag */ + uint8_t : 7; + } ADCMPBSR_b; + }; + __IM uint8_t RESERVED20; + __IM uint16_t RESERVED21[19]; + + union + { + __IOM uint16_t ADANSC0; /*!< (@ 0x000000D4) A/D Channel Select Register C0 */ + + struct + { + __IOM uint16_t ANSC0 : 8; /*!< [7..0] A/D-Converted Channel Select for Group C in Group Scan + * Mode */ + uint16_t : 8; + } ADANSC0_b; + }; + __IM uint16_t RESERVED22; + __IM uint8_t RESERVED23; + + union + { + __IOM uint8_t ADGCTRGR; /*!< (@ 0x000000D9) A/D Group C Trigger Select Register */ + + struct + { + __IOM uint8_t TRSC : 6; /*!< [5..0] Group C A/D Conversion Start Trigger Select */ + __IOM uint8_t GCADIE : 1; /*!< [6..6] Group C Scan Completion Interrupt Enable */ + __IOM uint8_t GRCE : 1; /*!< [7..7] Group C A/D Conversion Enable */ + } ADGCTRGR_b; + }; + __IM uint16_t RESERVED24[3]; + + union + { + __IOM uint8_t ADSSTR[8]; /*!< (@ 0x000000E0) A/D Sampling State Register n (n = 0 to 3 for + * unit 0, n = 0 to 7 for unit1) */ + + struct + { + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting */ + } ADSSTR_b[8]; + }; +} R_ADC121_Type; /*!< Size = 232 (0xe8) */ + +/* =========================================================================================================================== */ +/* ================ R_TSU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Temperature Sensor Unit (R_TSU) + */ + +typedef struct /*!< (@ 0x80046000) R_TSU Structure */ +{ + union + { + __IOM uint32_t TSUSM; /*!< (@ 0x00000000) Sensor Mode Register */ + + struct + { + __IOM uint32_t TSEN : 1; /*!< [0..0] Temperature Sensor Enable */ + __IOM uint32_t ADCEN : 1; /*!< [1..1] ADC Enable */ + uint32_t : 30; + } TSUSM_b; + }; + + union + { + __IOM uint32_t TSUST; /*!< (@ 0x00000004) Sensor Trigger Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] A/D Conversion Control */ + uint32_t : 31; + } TSUST_b; + }; + + union + { + __IOM uint32_t TSUSCS; /*!< (@ 0x00000008) Sensor Configuration Setting Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t CKDIV : 1; /*!< [3..3] Divider Value for PCLKL */ + uint32_t : 28; + } TSUSCS_b; + }; + + union + { + __IM uint32_t TSUSAD; /*!< (@ 0x0000000C) Sensor ADC Data Register */ + + struct + { + __IM uint32_t DOUT : 12; /*!< [11..0] Temperature Sensor Data Output */ + uint32_t : 20; + } TSUSAD_b; + }; + + union + { + __IM uint32_t TSUSS; /*!< (@ 0x00000010) Sensor Status Register */ + + struct + { + __IM uint32_t CONV : 1; /*!< [0..0] A/D Conversion Status */ + uint32_t : 31; + } TSUSS_b; + }; +} R_TSU_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG1 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPT Port Output Enable 1 (R_POEG1) + */ + +typedef struct /*!< (@ 0x80047000) R_POEG1 Structure */ +{ + union + { + __IOM uint32_t POEG1GA; /*!< (@ 0x00000000) POEG1 Group A Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GA_b; + }; + __IM uint32_t RESERVED[255]; + + union + { + __IOM uint32_t POEG1GB; /*!< (@ 0x00000400) POEG1 Group B Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GB_b; + }; + __IM uint32_t RESERVED1[255]; + + union + { + __IOM uint32_t POEG1GC; /*!< (@ 0x00000800) POEG1 Group C Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GC_b; + }; + __IM uint32_t RESERVED2[255]; + + union + { + __IOM uint32_t POEG1GD; /*!< (@ 0x00000C00) POEG1 Group D Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG1GD_b; + }; +} R_POEG1_Type; /*!< Size = 3076 (0xc04) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMA Controller 0 (R_DMAC0) + */ + +typedef struct /*!< (@ 0x80080000) R_DMAC0 Structure */ +{ + __IOM R_DMAC0_GRP_Type GRP[1]; /*!< (@ 0x00000000) 8 channel Registers */ +} R_DMAC0_Type; /*!< Size = 804 (0x324) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU_NS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller in Non Safety Domain (R_ICU_NS) + */ + +typedef struct /*!< (@ 0x80090000) R_ICU_NS Structure */ +{ + union + { + __OM uint32_t NS_SWINT; /*!< (@ 0x00000000) Software Interrupt Register */ + + struct + { + __OM uint32_t IC0 : 1; /*!< [0..0] Software Interrupt register */ + __OM uint32_t IC1 : 1; /*!< [1..1] Software Interrupt register */ + __OM uint32_t IC2 : 1; /*!< [2..2] Software Interrupt register */ + __OM uint32_t IC3 : 1; /*!< [3..3] Software Interrupt register */ + __OM uint32_t IC4 : 1; /*!< [4..4] Software Interrupt register */ + __OM uint32_t IC5 : 1; /*!< [5..5] Software Interrupt register */ + uint32_t : 26; + } NS_SWINT_b; + }; + + union + { + __IOM uint32_t NS_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register */ + + struct + { + __IOM uint32_t FLT0 : 1; /*!< [0..0] Noise filter enable for IRQ0 */ + __IOM uint32_t FLT1 : 1; /*!< [1..1] Noise filter enable for IRQ1 */ + __IOM uint32_t FLT2 : 1; /*!< [2..2] Noise filter enable for IRQ2 */ + __IOM uint32_t FLT3 : 1; /*!< [3..3] Noise filter enable for IRQ3 */ + __IOM uint32_t FLT4 : 1; /*!< [4..4] Noise filter enable for IRQ4 */ + __IOM uint32_t FLT5 : 1; /*!< [5..5] Noise filter enable for IRQ5 */ + __IOM uint32_t FLT6 : 1; /*!< [6..6] Noise filter enable for IRQ6 */ + __IOM uint32_t FLT7 : 1; /*!< [7..7] Noise filter enable for IRQ7 */ + __IOM uint32_t FLT8 : 1; /*!< [8..8] Noise filter enable for IRQ8 */ + __IOM uint32_t FLT9 : 1; /*!< [9..9] Noise filter enable for IRQ9 */ + __IOM uint32_t FLT10 : 1; /*!< [10..10] Noise filter enable for IRQ10 */ + __IOM uint32_t FLT11 : 1; /*!< [11..11] Noise filter enable for IRQ11 */ + __IOM uint32_t FLT12 : 1; /*!< [12..12] Noise filter enable for IRQ12 */ + __IOM uint32_t FLT13 : 1; /*!< [13..13] Noise filter enable for IRQ13 */ + __IOM uint32_t FLTDRQ : 1; /*!< [14..14] Noise filter enable for External DMA request (DREQ) */ + uint32_t : 17; + } NS_PORTNF_FLTSEL_b; + }; + + union + { + __IOM uint32_t NS_PORTNF_CLKSEL; /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register */ + + struct + { + __IOM uint32_t CKSEL0 : 2; /*!< [1..0] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL1 : 2; /*!< [3..2] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL2 : 2; /*!< [5..4] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL3 : 2; /*!< [7..6] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL4 : 2; /*!< [9..8] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL5 : 2; /*!< [11..10] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL6 : 2; /*!< [13..12] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL7 : 2; /*!< [15..14] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL8 : 2; /*!< [17..16] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL9 : 2; /*!< [19..18] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL10 : 2; /*!< [21..20] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL11 : 2; /*!< [23..22] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL12 : 2; /*!< [25..24] Noise filter sampling clock selector */ + __IOM uint32_t CKSEL13 : 2; /*!< [27..26] Noise filter sampling clock selector */ + __IOM uint32_t CKSELDREQ : 2; /*!< [29..28] Noise filter sampling clock selector */ + uint32_t : 2; + } NS_PORTNF_CLKSEL_b; + }; + + union + { + __IOM uint32_t NS_PORTNF_MD; /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register */ + + struct + { + __IOM uint32_t MD0 : 2; /*!< [1..0] Select detection mode for IRQ0 */ + __IOM uint32_t MD1 : 2; /*!< [3..2] Select detection mode for IRQ1 */ + __IOM uint32_t MD2 : 2; /*!< [5..4] Select detection mode for IRQ2 */ + __IOM uint32_t MD3 : 2; /*!< [7..6] Select detection mode for IRQ3 */ + __IOM uint32_t MD4 : 2; /*!< [9..8] Select detection mode for IRQ4 */ + __IOM uint32_t MD5 : 2; /*!< [11..10] Select detection mode for IRQ5 */ + __IOM uint32_t MD6 : 2; /*!< [13..12] Select detection mode for IRQ6 */ + __IOM uint32_t MD7 : 2; /*!< [15..14] Select detection mode for IRQ7 */ + __IOM uint32_t MD8 : 2; /*!< [17..16] Select detection mode for IRQ8 */ + __IOM uint32_t MD9 : 2; /*!< [19..18] Select detection mode for IRQ9 */ + __IOM uint32_t MD10 : 2; /*!< [21..20] Select detection mode for IRQ10 */ + __IOM uint32_t MD11 : 2; /*!< [23..22] Select detection mode for IRQ11 */ + __IOM uint32_t MD12 : 2; /*!< [25..24] Select detection mode for IRQ12 */ + __IOM uint32_t MD13 : 2; /*!< [27..26] Select detection mode for IRQ13 */ + __IOM uint32_t MDDRQ : 2; /*!< [29..28] Select detection mode for DREQ of DMAC */ + uint32_t : 2; + } NS_PORTNF_MD_b; + }; +} R_ICU_NS_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Evnet Link Controller (R_ELC) + */ + +typedef struct /*!< (@ 0x80090010) R_ELC Structure */ +{ + union + { + __IOM uint32_t ELC_SSEL[19]; /*!< (@ 0x00000000) ELC Event Source Select Register [0..18] */ + + struct + { + __IOM uint32_t ELC_SEL0 : 10; /*!< [9..0] Set the number for ELC event source to be linked to the + * ELC destination. */ + __IOM uint32_t ELC_SEL1 : 10; /*!< [19..10] Set the number for ELC event source to be linked to + * the ELC destination. */ + __IOM uint32_t ELC_SEL2 : 10; /*!< [29..20] Set the number for ELC event source to be linked to + * the ELC destination. */ + uint32_t : 2; + } ELC_SSEL_b[19]; + }; +} R_ELC_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/** + * @brief DMAC Configuration (R_DMA) + */ + +typedef struct /*!< (@ 0x80090060) R_DMA Structure */ +{ + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t DMAC0_RSSEL[3]; /*!< (@ 0x0000000C) DMAC Unit 0 Resource Select Register [0..2] */ + + struct + { + __IOM uint32_t REQ_SELA : 9; /*!< [8..0] DMA Resource Select for Channel n */ + uint32_t : 1; + __IOM uint32_t REQ_SELB : 9; /*!< [18..10] DMA Resource Select for Channel n + 1 */ + uint32_t : 1; + __IOM uint32_t REQ_SELC : 9; /*!< [28..20] DMA Resource Select for Channel n + 2 */ + uint32_t : 3; + } DMAC0_RSSEL_b[3]; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DMAC1_RSSEL[3]; /*!< (@ 0x00000024) DMAC Unit 1 Resource Select Register [0..2] */ + + struct + { + __IOM uint32_t REQ_SELA : 9; /*!< [8..0] DMA Resource Select for Channel n */ + uint32_t : 1; + __IOM uint32_t REQ_SELB : 9; /*!< [18..10] DMA Resource Select for Channel n + 1 */ + uint32_t : 1; + __IOM uint32_t REQ_SELC : 9; /*!< [28..20] DMA Resource Select for Channel n + 2 */ + uint32_t : 3; + } DMAC1_RSSEL_b[3]; + }; +} R_DMA_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT_NSR ================ */ +/* =========================================================================================================================== */ + +/** + * @brief I/O Ports (Non safety region) (R_PORT_NSR) + */ + +typedef struct /*!< (@ 0x800A0000) R_PORT_NSR Structure */ +{ + union + { + __IOM uint8_t P[25]; /*!< (@ 0x00000000) Port [0..24] Register */ + + struct + { + __IOM uint8_t POUT_0 : 1; /*!< [0..0] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_1 : 1; /*!< [1..1] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_2 : 1; /*!< [2..2] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_3 : 1; /*!< [3..3] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_4 : 1; /*!< [4..4] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_5 : 1; /*!< [5..5] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_6 : 1; /*!< [6..6] Pm_n Output Data Store (n: bit position) */ + __IOM uint8_t POUT_7 : 1; /*!< [7..7] Pm_n Output Data Store (n: bit position) */ + } P_b[25]; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[121]; + + union + { + __IOM uint16_t PM[25]; /*!< (@ 0x00000200) Port 0 Mode Register */ + + struct + { + __IOM uint16_t PM0 : 2; /*!< [1..0] Pm_0 I/O Select */ + __IOM uint16_t PM1 : 2; /*!< [3..2] Pm_1 I/O Select */ + __IOM uint16_t PM2 : 2; /*!< [5..4] Pm_2 I/O Select */ + __IOM uint16_t PM3 : 2; /*!< [7..6] Pm_3 I/O Select */ + __IOM uint16_t PM4 : 2; /*!< [9..8] Pm_4 I/O Select */ + __IOM uint16_t PM5 : 2; /*!< [11..10] Pm_5 I/O Select */ + __IOM uint16_t PM6 : 2; /*!< [13..12] Pm_6 I/O Select */ + __IOM uint16_t PM7 : 2; /*!< [15..14] Pm_7 I/O Select */ + } PM_b[25]; + }; + __IM uint16_t RESERVED3; + __IM uint32_t RESERVED4[115]; + + union + { + __IOM uint8_t PMC[25]; /*!< (@ 0x00000400) Port [0..24] Mode Control Register */ + + struct + { + __IOM uint8_t PMC0 : 1; /*!< [0..0] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC1 : 1; /*!< [1..1] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC2 : 1; /*!< [2..2] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC3 : 1; /*!< [3..3] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC4 : 1; /*!< [4..4] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC5 : 1; /*!< [5..5] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC6 : 1; /*!< [6..6] Pm_n Pin Mode Control (n: bit position) */ + __IOM uint8_t PMC7 : 1; /*!< [7..7] Pm_n Pin Mode Control (n: bit position) */ + } PMC_b[25]; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[121]; + + union + { + __IOM uint32_t PFC[25]; /*!< (@ 0x00000600) Port [0..24] Function Control Register */ + + struct + { + __IOM uint32_t PFC0 : 4; /*!< [3..0] Pm_0 Pin function Select */ + __IOM uint32_t PFC1 : 4; /*!< [7..4] Pm_1 Pin function Select */ + __IOM uint32_t PFC2 : 4; /*!< [11..8] Pm_2 Pin function Select */ + __IOM uint32_t PFC3 : 4; /*!< [15..12] Pm_3 Pin function Select */ + __IOM uint32_t PFC4 : 4; /*!< [19..16] Pm_4 Pin function Select */ + __IOM uint32_t PFC5 : 4; /*!< [23..20] Pm_5 Pin function Select */ + __IOM uint32_t PFC6 : 4; /*!< [27..24] Pm_6 Pin function Select */ + __IOM uint32_t PFC7 : 4; /*!< [31..28] Pm_7 Pin function Select */ + } PFC_b[25]; + }; + __IM uint32_t RESERVED8[103]; + + union + { + __IM uint8_t PIN[25]; /*!< (@ 0x00000800) Port [0..24] Input Register */ + + struct + { + __IM uint8_t PIN0 : 1; /*!< [0..0] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN1 : 1; /*!< [1..1] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN2 : 1; /*!< [2..2] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN3 : 1; /*!< [3..3] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN4 : 1; /*!< [4..4] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN5 : 1; /*!< [5..5] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN6 : 1; /*!< [6..6] Pm_n Pin Input (n: bit position) */ + __IM uint8_t PIN7 : 1; /*!< [7..7] Pm_n Pin Input (n: bit position) */ + } PIN_b[25]; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; + __IM uint32_t RESERVED11[121]; + __IOM R_PORT_DRCTL_Type DRCTL[25]; /*!< (@ 0x00000A00) I/O Buffer [0..24] Function Switching Register */ + __IM uint32_t RESERVED12[206]; + + union + { + __IOM uint8_t ELC_PGR[2]; /*!< (@ 0x00000E00) ELC Port Group Setting Register [0..1] */ + + struct + { + __IOM uint8_t PG0 : 1; /*!< [0..0] Port Group Setting */ + __IOM uint8_t PG1 : 1; /*!< [1..1] Port Group Setting */ + __IOM uint8_t PG2 : 1; /*!< [2..2] Port Group Setting */ + __IOM uint8_t PG3 : 1; /*!< [3..3] Port Group Setting */ + __IOM uint8_t PG4 : 1; /*!< [4..4] Port Group Setting */ + __IOM uint8_t PG5 : 1; /*!< [5..5] Port Group Setting */ + __IOM uint8_t PG6 : 1; /*!< [6..6] Port Group Setting */ + __IOM uint8_t PG7 : 1; /*!< [7..7] Port Group Setting */ + } ELC_PGR_b[2]; + }; + + union + { + __IOM uint8_t ELC_PGC[2]; /*!< (@ 0x00000E02) ELC Port Group Control Register [0..1] */ + + struct + { + __IOM uint8_t PGCI : 2; /*!< [1..0] Event Output Edge Select */ + __IOM uint8_t PGCOVE : 1; /*!< [2..2] PDBF Overwrite */ + uint8_t : 1; + __IOM uint8_t PGCO : 3; /*!< [6..4] Port Group Operation Select */ + uint8_t : 1; + } ELC_PGC_b[2]; + }; + __IOM R_PORT_NSR_ELC_PDBF_Type ELC_PDBF[2]; /*!< (@ 0x00000E04) ELC Port Buffer Register [0..1] */ + + union + { + __IOM uint8_t ELC_PEL[4]; /*!< (@ 0x00000E0C) ELC Port Setting Register [0..3] */ + + struct + { + __IOM uint8_t PSB : 3; /*!< [2..0] Bit Number Specification */ + __IOM uint8_t PSP : 2; /*!< [4..3] Port Number Specification */ + __IOM uint8_t PSM : 2; /*!< [6..5] Event Link Specification */ + uint8_t : 1; + } ELC_PEL_b[4]; + }; + + union + { + __IOM uint8_t ELC_DPTC; /*!< (@ 0x00000E10) ELC Edge Detection Control Register */ + + struct + { + __IOM uint8_t PTC0 : 1; /*!< [0..0] Single Input Port n Edge Detection */ + __IOM uint8_t PTC1 : 1; /*!< [1..1] Single Input Port n Edge Detection */ + __IOM uint8_t PTC2 : 1; /*!< [2..2] Single Input Port n Edge Detection */ + __IOM uint8_t PTC3 : 1; /*!< [3..3] Single Input Port n Edge Detection */ + uint8_t : 4; + } ELC_DPTC_b; + }; + + union + { + __IOM uint8_t ELC_ELSR2; /*!< (@ 0x00000E11) ELC Port Event Control Register */ + + struct + { + uint8_t : 2; + __IOM uint8_t PEG1 : 1; /*!< [2..2] ELC Port Buffer Register (ELC_PDBFn) write access control. + * When set to 1, writing to the ELC_PDBFn register via Internal + * peripheral bus is disabled, preventing overwriting. */ + __IOM uint8_t PEG2 : 1; /*!< [3..3] ELC Port Buffer Register (ELC_PDBFn) write access control. + * When set to 1, writing to the ELC_PDBFn register via Internal + * peripheral bus is disabled, preventing overwriting. */ + __IOM uint8_t PES0 : 1; /*!< [4..4] Single Port n Event Link Function Enable */ + __IOM uint8_t PES1 : 1; /*!< [5..5] Single Port n Event Link Function Enable */ + __IOM uint8_t PES2 : 1; /*!< [6..6] Single Port n Event Link Function Enable */ + __IOM uint8_t PES3 : 1; /*!< [7..7] Single Port n Event Link Function Enable */ + } ELC_ELSR2_b; + }; + __IM uint16_t RESERVED13; +} R_PORT_COMMON_Type; /*!< Size = 3604 (0xe14) */ + +/* =========================================================================================================================== */ +/* ================ R_GMAC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet MAC (R_GMAC) + */ + +typedef struct /*!< (@ 0x80100000) R_GMAC Structure */ +{ + union + { + __IOM uint32_t MAC_Configuration; /*!< (@ 0x00000000) MAC Configuration Register */ + + struct + { + __IOM uint32_t PRELEN : 2; /*!< [1..0] Preamble Length for Transmit Frames */ + __IOM uint32_t RE : 1; /*!< [2..2] Receiver Enable */ + __IOM uint32_t TE : 1; /*!< [3..3] Transmitter Enable */ + __IOM uint32_t DC : 1; /*!< [4..4] Deferral Check */ + __IOM uint32_t BL : 2; /*!< [6..5] Back-Off Limit */ + __IOM uint32_t ACS : 1; /*!< [7..7] Automatic Pad or CRC Stripping */ + uint32_t : 1; + __IOM uint32_t DR : 1; /*!< [9..9] Disable Retry */ + __IOM uint32_t IPC : 1; /*!< [10..10] Checksum Offload */ + __IOM uint32_t DM : 1; /*!< [11..11] Duplex Mode */ + __IOM uint32_t LM : 1; /*!< [12..12] Loopback Mode */ + __IOM uint32_t DO : 1; /*!< [13..13] Disable Receive Own */ + __IOM uint32_t FES : 1; /*!< [14..14] Speed */ + __IOM uint32_t PS : 1; /*!< [15..15] Port Select */ + __IOM uint32_t DCRS : 1; /*!< [16..16] Disable Carrier Sense During Transmission */ + __IOM uint32_t IFG : 3; /*!< [19..17] Inter-Frame Gap */ + __IOM uint32_t JE : 1; /*!< [20..20] Jumbo Frame Enable */ + __IOM uint32_t BE : 1; /*!< [21..21] Frame Burst Enable */ + __IOM uint32_t JD : 1; /*!< [22..22] Jabber Disable */ + __IOM uint32_t WD : 1; /*!< [23..23] Watchdog Disable */ + uint32_t : 1; + __IOM uint32_t CST : 1; /*!< [25..25] CRC Stripping for Type Frames */ + uint32_t : 1; + __IOM uint32_t TWOKPE : 1; /*!< [27..27] IEEE 802.3 as Support for 2 K Packets */ + uint32_t : 4; + } MAC_Configuration_b; + }; + + union + { + __IOM uint32_t MAC_Frame_Filter; /*!< (@ 0x00000004) MAC Frame Filter Register */ + + struct + { + __IOM uint32_t PR : 1; /*!< [0..0] Promiscuous Mode */ + __IOM uint32_t HUC : 1; /*!< [1..1] Hash Unicast */ + __IOM uint32_t HMC : 1; /*!< [2..2] Hash Multicast */ + __IOM uint32_t DAIF : 1; /*!< [3..3] DA Inverse Filtering */ + __IOM uint32_t PM : 1; /*!< [4..4] Pass All Multicast */ + __IOM uint32_t DBF : 1; /*!< [5..5] Disable Broadcast Frames */ + __IOM uint32_t PCF : 2; /*!< [7..6] Pass Control Frames */ + __IOM uint32_t SAIF : 1; /*!< [8..8] SA Inverse Filtering */ + __IOM uint32_t SAF : 1; /*!< [9..9] Source Address Filter Enable */ + __IOM uint32_t HPF : 1; /*!< [10..10] Hash or Perfect Filter */ + uint32_t : 5; + __IOM uint32_t VTFE : 1; /*!< [16..16] VLAN Tag Filter Enable */ + uint32_t : 14; + __IOM uint32_t RA : 1; /*!< [31..31] Receive All */ + } MAC_Frame_Filter_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t GMII_Address; /*!< (@ 0x00000010) GMII Address Register */ + + struct + { + __IOM uint32_t GB : 1; /*!< [0..0] GMII Busy */ + __IOM uint32_t GW : 1; /*!< [1..1] GMII Write */ + __IOM uint32_t CR : 4; /*!< [5..2] CSR Clock Range */ + __IOM uint32_t GR : 5; /*!< [10..6] GMII Register */ + __IOM uint32_t PA : 5; /*!< [15..11] Physical Layer Address */ + uint32_t : 16; + } GMII_Address_b; + }; + + union + { + __IOM uint32_t GMII_Data; /*!< (@ 0x00000014) GMII Data Register */ + + struct + { + __IOM uint32_t GD : 16; /*!< [15..0] GMII Data */ + uint32_t : 16; + } GMII_Data_b; + }; + + union + { + __IOM uint32_t Flow_Control; /*!< (@ 0x00000018) Flow Control Register */ + + struct + { + __IOM uint32_t FCA_BPA : 1; /*!< [0..0] Flow Control Busy or Backpressure Activate */ + __IOM uint32_t TFE : 1; /*!< [1..1] Transmit Flow Control Enable */ + __IOM uint32_t RFE : 1; /*!< [2..2] Receive Flow Control Enable */ + __IOM uint32_t UP : 1; /*!< [3..3] Unicast Pause Frame Detect */ + __IOM uint32_t PLT : 2; /*!< [5..4] Pause Low Threshold */ + uint32_t : 1; + __IOM uint32_t DZPQ : 1; /*!< [7..7] Disable Zero-Quanta Pause */ + uint32_t : 8; + __IOM uint32_t PT : 16; /*!< [31..16] Pause Time */ + } Flow_Control_b; + }; + + union + { + __IOM uint32_t VLAN_Tag; /*!< (@ 0x0000001C) VLAN Tag Register */ + + struct + { + __IOM uint32_t VL : 16; /*!< [15..0] VLAN Tag Identifier for Receive Frames */ + __IOM uint32_t ETV : 1; /*!< [16..16] Enable 12-Bit VLAN Tag Comparison */ + __IOM uint32_t VTIM : 1; /*!< [17..17] VLAN Tag Inverse Match Enable */ + __IOM uint32_t ESVL : 1; /*!< [18..18] Enable S-VLAN */ + __IOM uint32_t VTHM : 1; /*!< [19..19] VLAN Tag Hash Table Match Enable */ + uint32_t : 12; + } VLAN_Tag_b; + }; + + union + { + __IM uint32_t Version; /*!< (@ 0x00000020) Version Register */ + + struct + { + __IM uint32_t VER : 16; /*!< [15..0] Version (GMAC: 0x3037) */ + uint32_t : 16; + } Version_b; + }; + + union + { + __IM uint32_t Debug; /*!< (@ 0x00000024) Debug Register */ + + struct + { + __IM uint32_t RPESTS : 1; /*!< [0..0] GMAC GMII or MII Receive Protocol Engine Status */ + __IM uint32_t RFCFCSTS : 2; /*!< [2..1] GMAC Receive Frame Controller FIFO Status */ + uint32_t : 1; + __IM uint32_t RWCSTS : 1; /*!< [4..4] MTL RX FIFO Write Controller Active Status */ + __IM uint32_t RRCSTS : 2; /*!< [6..5] MTL RX FIFO Read Controller State */ + uint32_t : 1; + __IM uint32_t RXFSTS : 2; /*!< [9..8] MTL RX FIFO Fill-level Status */ + uint32_t : 6; + __IM uint32_t TPESTS : 1; /*!< [16..16] GMAC GMII or MII Transmit Protocol Engine Status */ + __IM uint32_t TFCSTS : 2; /*!< [18..17] GMAC Transmit Frame Controller Status */ + __IM uint32_t TXPAUSED : 1; /*!< [19..19] GMAC transmitter in PAUSE */ + __IM uint32_t TRCSTS : 2; /*!< [21..20] MTL TX FIFO Read Controller Status */ + __IM uint32_t TWCSTS : 1; /*!< [22..22] MTL TX FIFO Write Controller Active Status */ + uint32_t : 1; + __IM uint32_t TXFSTS : 1; /*!< [24..24] MTL TX FIFO Not Empty Status */ + __IM uint32_t TXSTSFSTS : 1; /*!< [25..25] MTL TX Status FIFO Full Status */ + uint32_t : 6; + } Debug_b; + }; + + union + { + __IOM uint32_t Remote_Wake_Up_Frame_Filter; /*!< (@ 0x00000028) Remote Wake-Up Frame Filter Register */ + + struct + { + __IOM uint32_t WKUPFRMFTR : 32; /*!< [31..0] Remote Wake-Up Frame Filter */ + } Remote_Wake_Up_Frame_Filter_b; + }; + + union + { + __IOM uint32_t PMT_Control_Status; /*!< (@ 0x0000002C) PMT Control and Status Register */ + + struct + { + __IOM uint32_t PWRDWN : 1; /*!< [0..0] Power Down */ + __IOM uint32_t MGKPKTEN : 1; /*!< [1..1] Magic Packet Enable */ + __IOM uint32_t RWKPKTEN : 1; /*!< [2..2] Wake-Up Frame Enable */ + uint32_t : 2; + __IM uint32_t MGKPRCVD : 1; /*!< [5..5] Magic Packet Received */ + __IM uint32_t RWKPRCVD : 1; /*!< [6..6] Wake-Up Frame Received */ + uint32_t : 2; + __IOM uint32_t GLBLUCAST : 1; /*!< [9..9] Global Unicast */ + uint32_t : 14; + __IM uint32_t RWKPTR : 3; /*!< [26..24] Remote Wake-Up FIFO Pointer */ + uint32_t : 4; + __IOM uint32_t RWKFILTRST : 1; /*!< [31..31] Wake-Up Frame Filter Register Pointer Reset */ + } PMT_Control_Status_b; + }; + + union + { + __IOM uint32_t LPI_Control_Status; /*!< (@ 0x00000030) LPI Control and Status Register */ + + struct + { + __IM uint32_t TLPIEN : 1; /*!< [0..0] Transmit LPI Entry */ + __IM uint32_t TLPIEX : 1; /*!< [1..1] Transmit LPI Exit */ + __IM uint32_t RLPIEN : 1; /*!< [2..2] Receive LPI Entry */ + __IM uint32_t RLPIEX : 1; /*!< [3..3] Receive LPI Exit */ + uint32_t : 4; + __IM uint32_t TLPIST : 1; /*!< [8..8] Transmit LPI State */ + __IM uint32_t RLPIST : 1; /*!< [9..9] Receive LPI State */ + uint32_t : 6; + __IOM uint32_t LPIEN : 1; /*!< [16..16] LPI Enable */ + __IOM uint32_t PLS : 1; /*!< [17..17] PHY Link Status */ + uint32_t : 1; + __IOM uint32_t LPITXA : 1; /*!< [19..19] LPI TX Automate */ + uint32_t : 12; + } LPI_Control_Status_b; + }; + + union + { + __IOM uint32_t LPI_Timers_Control; /*!< (@ 0x00000034) LPI Timers Control Register */ + + struct + { + __IOM uint32_t TWT : 16; /*!< [15..0] LPI TW Timer */ + __IOM uint32_t LST : 10; /*!< [25..16] LPI LS Timer */ + uint32_t : 6; + } LPI_Timers_Control_b; + }; + + union + { + __IM uint32_t Interrupt_Status; /*!< (@ 0x00000038) Interrupt Status Register */ + + struct + { + uint32_t : 3; + __IM uint32_t PMTIS : 1; /*!< [3..3] PMT Interrupt Status */ + __IM uint32_t MMCIS : 1; /*!< [4..4] MMC Interrupt Status */ + __IM uint32_t MMCRXIS : 1; /*!< [5..5] MMC Receive Interrupt Status */ + __IM uint32_t MMCTXIS : 1; /*!< [6..6] MMC Transmit Interrupt Status */ + __IM uint32_t MMCRXIPIS : 1; /*!< [7..7] MMC Receive Checksum Offload Interrupt Status */ + uint32_t : 1; + __IM uint32_t TSIS : 1; /*!< [9..9] Timestamp Interrupt Status */ + __IM uint32_t LPIIS : 1; /*!< [10..10] LPI Interrupt Status */ + uint32_t : 21; + } Interrupt_Status_b; + }; + + union + { + __IOM uint32_t Interrupt_Mask; /*!< (@ 0x0000003C) Interrupt Mask Register */ + + struct + { + uint32_t : 3; + __IOM uint32_t PMTIM : 1; /*!< [3..3] PMT Interrupt Mask */ + uint32_t : 5; + __IOM uint32_t TSIM : 1; /*!< [9..9] Timestamp Interrupt Mask */ + __IOM uint32_t LPIIM : 1; /*!< [10..10] LPI Interrupt Mask */ + uint32_t : 21; + } Interrupt_Mask_b; + }; + + union + { + __IOM uint32_t MAR0_H; /*!< (@ 0x00000040) MAC Address 0 High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address0[47:32] */ + uint32_t : 15; + __IM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR0_H_b; + }; + + union + { + __IOM uint32_t MAR0_L; /*!< (@ 0x00000044) MAC Address 0 Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address0[31:0] */ + } MAR0_L_b; + }; + + union + { + __IOM uint32_t MAR1_H; /*!< (@ 0x00000048) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR1_H_b; + }; + + union + { + __IOM uint32_t MAR1_L; /*!< (@ 0x0000004C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR1_L_b; + }; + + union + { + __IOM uint32_t MAR2_H; /*!< (@ 0x00000050) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR2_H_b; + }; + + union + { + __IOM uint32_t MAR2_L; /*!< (@ 0x00000054) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR2_L_b; + }; + + union + { + __IOM uint32_t MAR3_H; /*!< (@ 0x00000058) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR3_H_b; + }; + + union + { + __IOM uint32_t MAR3_L; /*!< (@ 0x0000005C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR3_L_b; + }; + + union + { + __IOM uint32_t MAR4_H; /*!< (@ 0x00000060) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR4_H_b; + }; + + union + { + __IOM uint32_t MAR4_L; /*!< (@ 0x00000064) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR4_L_b; + }; + + union + { + __IOM uint32_t MAR5_H; /*!< (@ 0x00000068) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR5_H_b; + }; + + union + { + __IOM uint32_t MAR5_L; /*!< (@ 0x0000006C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR5_L_b; + }; + + union + { + __IOM uint32_t MAR6_H; /*!< (@ 0x00000070) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR6_H_b; + }; + + union + { + __IOM uint32_t MAR6_L; /*!< (@ 0x00000074) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR6_L_b; + }; + + union + { + __IOM uint32_t MAR7_H; /*!< (@ 0x00000078) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR7_H_b; + }; + + union + { + __IOM uint32_t MAR7_L; /*!< (@ 0x0000007C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR7_L_b; + }; + + union + { + __IOM uint32_t MAR8_H; /*!< (@ 0x00000080) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR8_H_b; + }; + + union + { + __IOM uint32_t MAR8_L; /*!< (@ 0x00000084) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR8_L_b; + }; + + union + { + __IOM uint32_t MAR9_H; /*!< (@ 0x00000088) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR9_H_b; + }; + + union + { + __IOM uint32_t MAR9_L; /*!< (@ 0x0000008C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR9_L_b; + }; + + union + { + __IOM uint32_t MAR10_H; /*!< (@ 0x00000090) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR10_H_b; + }; + + union + { + __IOM uint32_t MAR10_L; /*!< (@ 0x00000094) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR10_L_b; + }; + + union + { + __IOM uint32_t MAR11_H; /*!< (@ 0x00000098) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR11_H_b; + }; + + union + { + __IOM uint32_t MAR11_L; /*!< (@ 0x0000009C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR11_L_b; + }; + + union + { + __IOM uint32_t MAR12_H; /*!< (@ 0x000000A0) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR12_H_b; + }; + + union + { + __IOM uint32_t MAR12_L; /*!< (@ 0x000000A4) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR12_L_b; + }; + + union + { + __IOM uint32_t MAR13_H; /*!< (@ 0x000000A8) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR13_H_b; + }; + + union + { + __IOM uint32_t MAR13_L; /*!< (@ 0x000000AC) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR13_L_b; + }; + + union + { + __IOM uint32_t MAR14_H; /*!< (@ 0x000000B0) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR14_H_b; + }; + + union + { + __IOM uint32_t MAR14_L; /*!< (@ 0x000000B4) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR14_L_b; + }; + + union + { + __IOM uint32_t MAR15_H; /*!< (@ 0x000000B8) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR15_H_b; + }; + + union + { + __IOM uint32_t MAR15_L; /*!< (@ 0x000000BC) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR15_L_b; + }; + __IM uint32_t RESERVED1[7]; + + union + { + __IOM uint32_t WDog_Timeout; /*!< (@ 0x000000DC) Watchdog Timeout Register */ + + struct + { + __IOM uint32_t WTO : 14; /*!< [13..0] Watchdog Timeout */ + uint32_t : 2; + __IOM uint32_t PWE : 1; /*!< [16..16] Programmable Watchdog Enable */ + uint32_t : 15; + } WDog_Timeout_b; + }; + __IM uint32_t RESERVED2[8]; + + union + { + __IOM uint32_t MMC_Control; /*!< (@ 0x00000100) MMC Control Register */ + + struct + { + __IOM uint32_t CNTRST : 1; /*!< [0..0] Counters Reset */ + __IOM uint32_t CNTSTOPRO : 1; /*!< [1..1] Counters Stop Rollover */ + __IOM uint32_t RSTONRD : 1; /*!< [2..2] Reset on Read */ + __IOM uint32_t CNTFREEZ : 1; /*!< [3..3] MMC Counter Freeze */ + __IOM uint32_t CNTPRST : 1; /*!< [4..4] Counters Preset */ + __IOM uint32_t CNTPRSTLVL : 1; /*!< [5..5] Full-Half Preset */ + uint32_t : 2; + __IOM uint32_t UCDBC : 1; /*!< [8..8] Update MMC Counters for Dropped Broadcast Frames */ + uint32_t : 23; + } MMC_Control_b; + }; + + union + { + __IM uint32_t MMC_Receive_Interrupt; /*!< (@ 0x00000104) MMC Receive Interrupt Register */ + + struct + { + __IM uint32_t RXGBFRMIS : 1; /*!< [0..0] MMC Receive Good Bad Frame Counter Interrupt Status */ + __IM uint32_t RXGBOCTIS : 1; /*!< [1..1] MMC Receive Good Bad Octet Counter Interrupt Status */ + __IM uint32_t RXGOCTIS : 1; /*!< [2..2] MMC Receive Good Octet Counter Interrupt Status */ + __IM uint32_t RXBCGFIS : 1; /*!< [3..3] MMC Receive Broadcast Good Frame Counter Interrupt Status */ + __IM uint32_t RXMCGFIS : 1; /*!< [4..4] MMC Receive Multicast Good Frame Counter Interrupt Status */ + __IM uint32_t RXCRCERFIS : 1; /*!< [5..5] MMC Receive CRC Error Frame Counter Interrupt Status */ + __IM uint32_t RXALGNERFIS : 1; /*!< [6..6] MMC Receive Alignment Error Frame Counter Interrupt Status */ + __IM uint32_t RXRUNTFIS : 1; /*!< [7..7] MMC Receive Runt Frame Counter Interrupt Status */ + __IM uint32_t RXJABERFIS : 1; /*!< [8..8] MMC Receive Jabber Error Frame Counter Interrupt Status */ + __IM uint32_t RXUSIZEGFIS : 1; /*!< [9..9] MMC Receive Undersize Good Frame Counter Interrupt Status */ + __IM uint32_t RXOSIZEGFIS : 1; /*!< [10..10] MMC Receive Oversize Good Frame Counter Interrupt Status */ + __IM uint32_t RX64OCTGBFIS : 1; /*!< [11..11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t RX65T127OCTGBFIS : 1; /*!< [12..12] MMC Receive 65 to 127 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX128T255OCTGBFIS : 1; /*!< [13..13] MMC Receive 128 to 255 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX256T511OCTGBFIS : 1; /*!< [14..14] MMC Receive 256 to 511 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX512T1023OCTGBFIS : 1; /*!< [15..15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RX1024TMAXOCTGBFIS : 1; /*!< [16..16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t RXUCGFIS : 1; /*!< [17..17] MMC Receive Unicast Good Frame Counter Interrupt Status */ + __IM uint32_t RXLENERFIS : 1; /*!< [18..18] MMC Receive Length Error Frame Counter Interrupt Status */ + __IM uint32_t RXORANGEFIS : 1; /*!< [19..19] MMC Receive Out Of Range Error Frame Counter Interrupt + * Status */ + __IM uint32_t RXPAUSFIS : 1; /*!< [20..20] MMC Receive Pause Frame Counter Interrupt Status */ + __IM uint32_t RXFOVFIS : 1; /*!< [21..21] MMC Receive FIFO Overflow Frame Counter Interrupt Status */ + __IM uint32_t RXVLANGBFIS : 1; /*!< [22..22] MMC Receive VLAN Good Bad Frame Counter Interrupt Status */ + __IM uint32_t RXWDOGFIS : 1; /*!< [23..23] MMC Receive Watchdog Error Frame Counter Interrupt + * Status */ + __IM uint32_t RXRCVERRFIS : 1; /*!< [24..24] MMC Receive Error Frame Counter Interrupt Status */ + __IM uint32_t RXCTRLFIS : 1; /*!< [25..25] MMC Receive Control Frame Counter Interrupt Status */ + uint32_t : 6; + } MMC_Receive_Interrupt_b; + }; + + union + { + __IM uint32_t MMC_Transmit_Interrupt; /*!< (@ 0x00000108) MMC Transmit Interrupt Register */ + + struct + { + __IM uint32_t TXGBOCTIS : 1; /*!< [0..0] MMC Transmit Good Bad Octet Counter Interrupt Status */ + __IM uint32_t TXGBFRMIS : 1; /*!< [1..1] MMC Transmit Good Bad Frame Counter Interrupt Status */ + __IM uint32_t TXBCGFIS : 1; /*!< [2..2] MMC Transmit Broadcast Good Frame Counter Interrupt Status */ + __IM uint32_t TXMCGFIS : 1; /*!< [3..3] MMC Transmit Multicast Good Frame Counter Interrupt Status */ + __IM uint32_t TX64OCTGBFIS : 1; /*!< [4..4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TX65T127OCTGBFIS : 1; /*!< [5..5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TX128T255OCTGBFIS : 1; /*!< [6..6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TX256T511OCTGBFIS : 1; /*!< [7..7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TX512T1023OCTGBFIS : 1; /*!< [8..8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TX1024TMAXOCTGBFIS : 1; /*!< [9..9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Status */ + __IM uint32_t TXUCGBFIS : 1; /*!< [10..10] MMC Transmit Unicast Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TXMCGBFIS : 1; /*!< [11..11] MMC Transmit Multicast Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TXBCGBFIS : 1; /*!< [12..12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt + * Status */ + __IM uint32_t TXUFLOWERFIS : 1; /*!< [13..13] MMC Transmit Underflow Error Frame Counter Interrupt + * Status */ + __IM uint32_t TXSCOLGFIS : 1; /*!< [14..14] MMC Transmit Single Collision Good Frame Counter Interrupt + * Status */ + __IM uint32_t TXMCOLGFIS : 1; /*!< [15..15] MMC Transmit Multiple Collision Good Frame Counter + * Interrupt Status */ + __IM uint32_t TXDEFFIS : 1; /*!< [16..16] MMC Transmit Deferred Frame Counter Interrupt Status */ + __IM uint32_t TXLATCOLFIS : 1; /*!< [17..17] MMC Transmit Late Collision Frame Counter Interrupt + * Status */ + __IM uint32_t TXEXCOLFIS : 1; /*!< [18..18] MMC Transmit Excessive Collision Frame Counter Interrupt + * Status */ + __IM uint32_t TXCARERFIS : 1; /*!< [19..19] MMC Transmit Carrier Error Frame Counter Interrupt + * Status */ + __IM uint32_t TXGOCTIS : 1; /*!< [20..20] MMC Transmit Good Octet Counter Interrupt Status */ + __IM uint32_t TXGFRMIS : 1; /*!< [21..21] MMC Transmit Good Frame Counter Interrupt Status */ + __IM uint32_t TXEXDEFFIS : 1; /*!< [22..22] MMC Transmit Excessive Deferral Frame Counter Interrupt + * Status */ + __IM uint32_t TXPAUSFIS : 1; /*!< [23..23] MMC Transmit Pause Frame Counter Interrupt Status */ + __IM uint32_t TXVLANGFIS : 1; /*!< [24..24] MMC Transmit VLAN Good Frame Counter Interrupt Status */ + __IM uint32_t TXOSIZEGFIS : 1; /*!< [25..25] MMC Transmit Oversize Good Frame Counter Interrupt + * Status */ + uint32_t : 6; + } MMC_Transmit_Interrupt_b; + }; + + union + { + __IOM uint32_t MMC_Receive_Interrupt_Mask; /*!< (@ 0x0000010C) MMC Receive Interrupt Mask Register */ + + struct + { + __IOM uint32_t RXGBFRMIM : 1; /*!< [0..0] MMC Receive Good Bad Frame Counter Interrupt Mask */ + __IOM uint32_t RXGBOCTIM : 1; /*!< [1..1] MMC Receive Good Bad Octet Counter Interrupt Mask */ + __IOM uint32_t RXGOCTIM : 1; /*!< [2..2] MMC Receive Good Octet Counter Interrupt Mask */ + __IOM uint32_t RXBCGFIM : 1; /*!< [3..3] MMC Receive Broadcast Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXMCGFIM : 1; /*!< [4..4] MMC Receive Multicast Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXCRCERFIM : 1; /*!< [5..5] MMC Receive CRC Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXALGNERFIM : 1; /*!< [6..6] MMC Receive Alignment Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXRUNTFIM : 1; /*!< [7..7] MMC Receive Runt Frame Counter Interrupt Mask */ + __IOM uint32_t RXJABERFIM : 1; /*!< [8..8] MMC Receive Jabber Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXUSIZEGFIM : 1; /*!< [9..9] MMC Receive Undersize Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXOSIZEGFIM : 1; /*!< [10..10] MMC Receive Oversize Good Frame Counter Interrupt Mask */ + __IOM uint32_t RX64OCTGBFIM : 1; /*!< [11..11] MMC Receive 64 Octet Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t RX65T127OCTGBFIM : 1; /*!< [12..12] MMC Receive 65 to 127 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX128T255OCTGBFIM : 1; /*!< [13..13] MMC Receive 128 to 255 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX256T511OCTGBFIM : 1; /*!< [14..14] MMC Receive 256 to 511 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX512T1023OCTGBFIM : 1; /*!< [15..15] MMC Receive 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RX1024TMAXOCTGBFIM : 1; /*!< [16..16] MMC Receive 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t RXUCGFIM : 1; /*!< [17..17] MMC Receive Unicast Good Frame Counter Interrupt Mask */ + __IOM uint32_t RXLENERFIM : 1; /*!< [18..18] MMC Receive Length Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXORANGEFIM : 1; /*!< [19..19] MMC Receive Out Of Range Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t RXPAUSFIM : 1; /*!< [20..20] MMC Receive Pause Frame Counter Interrupt Mask */ + __IOM uint32_t RXFOVFIM : 1; /*!< [21..21] MMC Receive FIFO Overflow Frame Counter Interrupt Mask */ + __IOM uint32_t RXVLANGBFIM : 1; /*!< [22..22] MMC Receive VLAN Good Bad Frame Counter Interrupt Mask */ + __IOM uint32_t RXWDOGFIM : 1; /*!< [23..23] MMC Receive Watchdog Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t RXRCVERRFIM : 1; /*!< [24..24] MMC Receive Error Frame Counter Interrupt Mask */ + __IOM uint32_t RXCTRLFIM : 1; /*!< [25..25] MMC Receive Control Frame Counter Interrupt Mask */ + uint32_t : 6; + } MMC_Receive_Interrupt_Mask_b; + }; + + union + { + __IOM uint32_t MMC_Transmit_Interrupt_Mask; /*!< (@ 0x00000110) MMC Transmit Interrupt Mask Register */ + + struct + { + __IOM uint32_t TXGBOCTIM : 1; /*!< [0..0] MMC Transmit Good Bad Octet Counter Interrupt Mask */ + __IOM uint32_t TXGBFRMIM : 1; /*!< [1..1] MMC Transmit Good Bad Frame Counter Interrupt Mask */ + __IOM uint32_t TXBCGFIM : 1; /*!< [2..2] MMC Transmit Broadcast Good Frame Counter Interrupt Mask */ + __IOM uint32_t TXMCGFIM : 1; /*!< [3..3] MMC Transmit Multicast Good Frame Counter Interrupt Mask */ + __IOM uint32_t TX64OCTGBFIM : 1; /*!< [4..4] MMC Transmit 64 Octet Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TX65T127OCTGBFIM : 1; /*!< [5..5] MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TX128T255OCTGBFIM : 1; /*!< [6..6] MMC Transmit 128 to 255 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TX256T511OCTGBFIM : 1; /*!< [7..7] MMC Transmit 256 to 511 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TX512T1023OCTGBFIM : 1; /*!< [8..8] MMC Transmit 512 to 1023 Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TX1024TMAXOCTGBFIM : 1; /*!< [9..9] MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter + * Interrupt Mask */ + __IOM uint32_t TXUCGBFIM : 1; /*!< [10..10] MMC Transmit Unicast Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXMCGBFIM : 1; /*!< [11..11] MMC Transmit Multicast Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXBCGBFIM : 1; /*!< [12..12] MMC Transmit Broadcast Good Bad Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXUFLOWERFIM : 1; /*!< [13..13] MMC Transmit Underflow Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXSCOLGFIM : 1; /*!< [14..14] MMC Transmit Single Collision Good Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXMCOLGFIM : 1; /*!< [15..15] MMC Transmit Multiple Collision Good Frame Counter + * Interrupt Mask */ + __IOM uint32_t TXDEFFIM : 1; /*!< [16..16] MMC Transmit Deferred Frame Counter Interrupt Mask */ + __IOM uint32_t TXLATCOLFIM : 1; /*!< [17..17] MMC Transmit Late Collision Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXEXCOLFIM : 1; /*!< [18..18] MMC Transmit Excessive Collision Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXCARERFIM : 1; /*!< [19..19] MMC Transmit Carrier Error Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXGOCTIM : 1; /*!< [20..20] MMC Transmit Good Octet Counter Interrupt Mask */ + __IOM uint32_t TXGFRMIM : 1; /*!< [21..21] MMC Transmit Good Frame Counter Interrupt Mask */ + __IOM uint32_t TXEXDEFFIM : 1; /*!< [22..22] MMC Transmit Excessive Deferral Frame Counter Interrupt + * Mask */ + __IOM uint32_t TXPAUSFIM : 1; /*!< [23..23] MMC Transmit Pause Frame Counter Interrupt Mask */ + __IOM uint32_t TXVLANGFIM : 1; /*!< [24..24] MMC Transmit VLAN Good Frame Counter Interrupt Mask */ + __IOM uint32_t TXOSIZEGFIM : 1; /*!< [25..25] MMC Transmit Oversize Good Frame Counter Interrupt + * Mask */ + uint32_t : 6; + } MMC_Transmit_Interrupt_Mask_b; + }; + + union + { + __IM uint32_t Tx_Octet_Count_Good_Bad; /*!< (@ 0x00000114) Transmit Octet Count for Good and Bad Frames */ + + struct + { + __IM uint32_t TXOCTGB : 32; /*!< [31..0] This field indicates the number of bytes transmitted + * in good and bad frames exclusive of preamble and retried + * bytes. */ + } Tx_Octet_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Frame_Count_Good_Bad; /*!< (@ 0x00000118) Transmit Frame Count for Good and Bad Frames */ + + struct + { + __IM uint32_t TXFRMGB : 32; /*!< [31..0] This field indicates the number of good and bad frames + * transmitted, exclusive of retried frames. */ + } Tx_Frame_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Broadcast_Frames_Good; /*!< (@ 0x0000011C) Transmit Frame Count for Good Broadcast Frames */ + + struct + { + __IM uint32_t TXBCASTG : 32; /*!< [31..0] This field indicates the number of transmitted good + * broadcast frames. */ + } Tx_Broadcast_Frames_Good_b; + }; + + union + { + __IM uint32_t Tx_Multicast_Frames_Good; /*!< (@ 0x00000120) Transmit Frame Count for Good Multicast Frames */ + + struct + { + __IM uint32_t TXMCASTG : 32; /*!< [31..0] This field indicates the number of transmitted good + * multicast frames. */ + } Tx_Multicast_Frames_Good_b; + }; + + union + { + __IM uint32_t Tx_64Octets_Frames_Good_Bad; /*!< (@ 0x00000124) Transmit Octet Count for Good and Bad 64 Byte + * Frames */ + + struct + { + __IM uint32_t TX64OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length of 64 bytes, exclusive of preamble + * and retried frames. */ + } Tx_64Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_65To127Octets_Frames_Good_Bad; /*!< (@ 0x00000128) Transmit Octet Count for Good and Bad 65 to 127 + * Bytes Frames */ + + struct + { + __IM uint32_t TX65_127OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 65 and 127 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_65To127Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_128To255Octets_Frames_Good_Bad; /*!< (@ 0x0000012C) Transmit Octet Count for Good and Bad 128 to + * 255 Bytes Frames */ + + struct + { + __IM uint32_t TX128_255OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 128 and 255 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_128To255Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_256To511Octets_Frames_Good_Bad; /*!< (@ 0x00000130) Transmit Octet Count for Good and Bad 256 to + * 511 Bytes Frames */ + + struct + { + __IM uint32_t TX256_511OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 256 and 511 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_256To511Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_512To1023Octets_Frames_Good_Bad; /*!< (@ 0x00000134) Transmit Octet Count for Good and Bad 512 to + * 1023 Bytes Frames */ + + struct + { + __IM uint32_t TX512_1023OCTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad frames with length between 512 and 1,023 (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_512To1023Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_1024ToMaxOctets_Frames_Good_Bad; /*!< (@ 0x00000138) Transmit Octet Count for Good and Bad 1024 to + * Maxsize Bytes Frames */ + + struct + { + __IM uint32_t TX1024_MAXOCTGB : 32; /*!< [31..0] This field indicates the number of good and bad frames + * transmitted with length between 1,024 and maxsize (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Tx_1024ToMaxOctets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Unicast_Frames_Good_Bad; /*!< (@ 0x0000013C) Transmit Frame Count for Good and Bad Unicast + * Frames */ + + struct + { + __IM uint32_t TXUCASTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad unicast frames. */ + } Tx_Unicast_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Multicast_Frames_Good_Bad; /*!< (@ 0x00000140) Transmit Frame Count for Good and Bad Multicast + * Frames */ + + struct + { + __IM uint32_t TXMCASTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad multicast frames. */ + } Tx_Multicast_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Broadcast_Frames_Good_Bad; /*!< (@ 0x00000144) Transmit Frame Count for Good and Bad Broadcast + * Frames */ + + struct + { + __IM uint32_t TXBCASTGB : 32; /*!< [31..0] This field indicates the number of transmitted good + * and bad broadcast frames. */ + } Tx_Broadcast_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Tx_Underflow_Error_Frames; /*!< (@ 0x00000148) Transmit Frame Count for Underflow Error Frames */ + + struct + { + __IM uint32_t TXUNDRFLW : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of frame underflow error. */ + uint32_t : 16; + } Tx_Underflow_Error_Frames_b; + }; + + union + { + __IM uint32_t Tx_Single_Collision_Good_Frames; /*!< (@ 0x0000014C) Transmit Frame Count for Frames Transmitted after + * Single Collision */ + + struct + { + __IM uint32_t TXSNGLCOLG : 16; /*!< [15..0] This field indicates the number of successfully transmitted + * frames after a single collision in the half-duplex mode. */ + uint32_t : 16; + } Tx_Single_Collision_Good_Frames_b; + }; + + union + { + __IM uint32_t Tx_Multiple_Collision_Good_Frames; /*!< (@ 0x00000150) Transmit Frame Count for Frames Transmitted after + * Multiple Collision */ + + struct + { + __IM uint32_t TXMULTCOLG : 16; /*!< [15..0] This field indicates the number of successfully transmitted + * frames after multiple collisions in the half-duplex mode. */ + uint32_t : 16; + } Tx_Multiple_Collision_Good_Frames_b; + }; + + union + { + __IM uint32_t Tx_Deferred_Frames; /*!< (@ 0x00000154) Transmit Frame Count for Deferred Frames */ + + struct + { + __IM uint32_t TXDEFRD : 16; /*!< [15..0] This field indicates the number of successfully transmitted + * frames after a deferral in the half-duplex mode. */ + uint32_t : 16; + } Tx_Deferred_Frames_b; + }; + + union + { + __IM uint32_t Tx_Late_Collision_Frames; /*!< (@ 0x00000158) Transmit Frame Count for Late Collision Error + * Frames */ + + struct + { + __IM uint32_t TXLATECOL : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of late collision error. */ + uint32_t : 16; + } Tx_Late_Collision_Frames_b; + }; + + union + { + __IM uint32_t Tx_Excessive_Collision_Frames; /*!< (@ 0x0000015C) Transmit Frame Count for Excessive Collision + * Error Frames */ + + struct + { + __IM uint32_t TXEXSCOL : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of excessive (16) collision error. */ + uint32_t : 16; + } Tx_Excessive_Collision_Frames_b; + }; + + union + { + __IM uint32_t Tx_Carrier_Error_Frames; /*!< (@ 0x00000160) Transmit Frame Count for Carrier Sense Error + * Frames */ + + struct + { + __IM uint32_t TXCARR : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of carrier sense error (no carrier or loss of carrier). */ + uint32_t : 16; + } Tx_Carrier_Error_Frames_b; + }; + + union + { + __IM uint32_t Tx_Octet_Count_Good; /*!< (@ 0x00000164) Transmit Octet Count for Good Frames */ + + struct + { + __IM uint32_t TXOCTG : 32; /*!< [31..0] TXOCTG */ + } Tx_Octet_Count_Good_b; + }; + + union + { + __IM uint32_t Tx_Frame_Count_Good; /*!< (@ 0x00000168) Transmit Frame Count for Good Frames */ + + struct + { + __IM uint32_t TXFRMG : 32; /*!< [31..0] This field indicates the number of transmitted good + * frames, exclusive of preamble. */ + } Tx_Frame_Count_Good_b; + }; + + union + { + __IM uint32_t Tx_Excessive_Deferral_Error; /*!< (@ 0x0000016C) Transmit Frame Count for Excessive Deferral Error + * Frames */ + + struct + { + __IM uint32_t TXEXSDEF : 16; /*!< [15..0] This field indicates the number of frames aborted because + * of excessive deferral error, that is, frames deferred for + * more than two max sized frame times. */ + uint32_t : 16; + } Tx_Excessive_Deferral_Error_b; + }; + + union + { + __IM uint32_t Tx_Pause_Frames; /*!< (@ 0x00000170) Transmit Frame Count for Good PAUSE Frames */ + + struct + { + __IM uint32_t TXPAUSE : 16; /*!< [15..0] This field indicates the number of transmitted good + * PAUSE frames. */ + uint32_t : 16; + } Tx_Pause_Frames_b; + }; + + union + { + __IM uint32_t Tx_VLAN_Frames_Good; /*!< (@ 0x00000174) Transmit Frame Count for Good VLAN Frames */ + + struct + { + __IM uint32_t TXVLANG : 32; /*!< [31..0] This register maintains the number of transmitted good + * VLAN frames, exclusive of retried frames. */ + } Tx_VLAN_Frames_Good_b; + }; + + union + { + __IM uint32_t Tx_OSize_Frames_Good; /*!< (@ 0x00000178) Transmit Frame Count for Good Oversize Frames */ + + struct + { + __IM uint32_t TXOSIZG : 16; /*!< [15..0] This field indicates the number of frames transmitted + * without errors and with length greater than the maxsize + * (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes + * if enabled in bit [27] of MAC Configuration Register (MAC_Configuration)) + */ + uint32_t : 16; + } Tx_OSize_Frames_Good_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IM uint32_t Rx_Frames_Count_Good_Bad; /*!< (@ 0x00000180) Receive Frame Count for Good and Bad Frames */ + + struct + { + __IM uint32_t RXFRMGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames. */ + } Rx_Frames_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Octet_Count_Good_Bad; /*!< (@ 0x00000184) Receive Octet Count for Good and Bad Frames */ + + struct + { + __IM uint32_t RXOCTGB : 32; /*!< [31..0] This field indicates the number of bytes received, exclusive + * of preamble, in good and bad frames. */ + } Rx_Octet_Count_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Octet_Count_Good; /*!< (@ 0x00000188) Receive Octet Count for Good Frames */ + + struct + { + __IM uint32_t RXOCTG : 32; /*!< [31..0] This field indicates the number of bytes received, exclusive + * of preamble, only in good frames. */ + } Rx_Octet_Count_Good_b; + }; + + union + { + __IM uint32_t Rx_Broadcast_Frames_Good; /*!< (@ 0x0000018C) Receive Frame Count for Good Broadcast Frames */ + + struct + { + __IM uint32_t RXBCASTG : 32; /*!< [31..0] This field indicates the number of received good broadcast + * frames. */ + } Rx_Broadcast_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_Multicast_Frames_Good; /*!< (@ 0x00000190) Receive Frame Count for Good Multicast Frames */ + + struct + { + __IM uint32_t RXMCASTG : 32; /*!< [31..0] This field indicates the number of received good multicast + * frames. */ + } Rx_Multicast_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_CRC_Error_Frames; /*!< (@ 0x00000194) Receive Frame Count for CRC Error Frames */ + + struct + { + __IM uint32_t RXCRCERR : 16; /*!< [15..0] This field indicates the number of frames received with + * CRC error. */ + uint32_t : 16; + } Rx_CRC_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Alignment_Error_Frames; /*!< (@ 0x00000198) Receive Frame Count for Alignment Error Frames */ + + struct + { + __IM uint32_t RXALGNERR : 16; /*!< [15..0] This field indicates the number of frames received with + * alignment (dribble) error. This field is valid only in + * the 10 or 100 Mbps mode. */ + uint32_t : 16; + } Rx_Alignment_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Runt_Error_Frames; /*!< (@ 0x0000019C) Receive Frame Count for Runt Error Frames */ + + struct + { + __IM uint32_t RXRUNTERR : 16; /*!< [15..0] This field indicates the number of frames received with + * runt error (< 64 bytes and CRC error). */ + uint32_t : 16; + } Rx_Runt_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Jabber_Error_Frames; /*!< (@ 0x000001A0) Receive Frame Count for Jabber Error Frames */ + + struct + { + __IM uint32_t RXJABERR : 16; /*!< [15..0] This field indicates the number of giant frames received + * with length (including CRC) greater than 1,518 bytes (1,522 + * bytes for VLAN tagged) and with CRC error. If Jumbo Frame + * mode is enabled, then frames of length greater than 9,018 + * bytes (9,022 for VLAN tagged) are considered as giant frames. */ + uint32_t : 16; + } Rx_Jabber_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Undersize_Frames_Good; /*!< (@ 0x000001A4) Receive Frame Count for Undersize Frames */ + + struct + { + __IM uint32_t RXUNDERSZG : 16; /*!< [15..0] This field indicates the number of frames received with + * length less than 64 bytes and without errors. */ + uint32_t : 16; + } Rx_Undersize_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_Oversize_Frames_Good; /*!< (@ 0x000001A8) Receive Frame Count for Oversize Frames */ + + struct + { + __IM uint32_t RXOVERSZG : 16; /*!< [15..0] This field indicates the number of frames received without + * errors, with length greater than the maxsize (1,518 or + * 1,522 for VLAN tagged frames; 2,000 bytes if enabled in + * bit [27] of MAC Configuration Register (MAC_Configuration)). */ + uint32_t : 16; + } Rx_Oversize_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_64Octets_Frames_Good_Bad; /*!< (@ 0x000001AC) Receive Frame Count for Good and Bad 64 Byte + * Frames */ + + struct + { + __IM uint32_t RX64OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length 64 bytes, exclusive of preamble. */ + } Rx_64Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_65To127Octets_Frames_Good_Bad; /*!< (@ 0x000001B0) Receive Frame Count for Good and Bad 65 to 127 + * Bytes Frames */ + + struct + { + __IM uint32_t RX65_127OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames received with length between 65 and 127 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_65To127Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_128To255Octets_Frames_Good_Bad; /*!< (@ 0x000001B4) Receive Frame Count for Good and Bad 128 to 255 + * Bytes Frames */ + + struct + { + __IM uint32_t RX128_255OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 128 and 255 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_128To255Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_256To511Octets_Frames_Good_Bad; /*!< (@ 0x000001B8) Receive Frame Count for Good and Bad 256 to 511 + * Bytes Frames */ + + struct + { + __IM uint32_t RX256_511OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 256 and 511 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_256To511Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_512To1023Octets_Frames_Good_Bad; /*!< (@ 0x000001BC) Receive Frame Count for Good and Bad 512 to 1,023 + * Bytes Frames */ + + struct + { + __IM uint32_t RX512_1023OCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 512 and 1,023 (inclusive) + * bytes, exclusive of preamble. */ + } Rx_512To1023Octets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_1024ToMaxOctets_Frames_Good_Bad; /*!< (@ 0x000001C0) Receive Frame Count for Good and Bad 1,024 to + * Maxsize Bytes Frames */ + + struct + { + __IM uint32_t RX1024_MAXOCTGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad frames with length between 1,024 and maxsize (inclusive) + * bytes, exclusive of preamble and retried frames. */ + } Rx_1024ToMaxOctets_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Unicast_Frames_Good; /*!< (@ 0x000001C4) Receive Frame Count for Good Unicast Frames */ + + struct + { + __IM uint32_t RXUCASTG : 32; /*!< [31..0] This field indicates the number of received good unicast + * frames. */ + } Rx_Unicast_Frames_Good_b; + }; + + union + { + __IM uint32_t Rx_Length_Error_Frames; /*!< (@ 0x000001C8) Receive Frame Count for Length Error Frames */ + + struct + { + __IM uint32_t RXLENERR : 16; /*!< [15..0] RXLENERR */ + uint32_t : 16; + } Rx_Length_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Out_Of_Range_Type_Frames; /*!< (@ 0x000001CC) Receive Frame Count for Out of Range Frames */ + + struct + { + __IM uint32_t RXOUTOFRNG : 16; /*!< [15..0] This field indicates the number of received frames with + * length field not equal to the valid frame size (greater + * than 1,500 but less than 1,536). */ + uint32_t : 16; + } Rx_Out_Of_Range_Type_Frames_b; + }; + + union + { + __IM uint32_t Rx_Pause_Frames; /*!< (@ 0x000001D0) Receive Frame Count for PAUSE Frames */ + + struct + { + __IM uint32_t RXPAUSEFRM : 16; /*!< [15..0] This field indicates the number of received good and + * valid PAUSE frames. */ + uint32_t : 16; + } Rx_Pause_Frames_b; + }; + + union + { + __IM uint32_t Rx_FIFO_Overflow_Frames; /*!< (@ 0x000001D4) Receive Frame Count for FIFO Overflow Frames */ + + struct + { + __IM uint32_t RXFIFOOVFL : 16; /*!< [15..0] This field indicates the number of received frames missed + * because of FIFO overflow. */ + uint32_t : 16; + } Rx_FIFO_Overflow_Frames_b; + }; + + union + { + __IM uint32_t Rx_VLAN_Frames_Good_Bad; /*!< (@ 0x000001D8) Receive Frame Count for Good and Bad VLAN Frames */ + + struct + { + __IM uint32_t RXVLANFRGB : 32; /*!< [31..0] This field indicates the number of received good and + * bad VLAN frames. */ + } Rx_VLAN_Frames_Good_Bad_b; + }; + + union + { + __IM uint32_t Rx_Watchdog_Error_Frames; /*!< (@ 0x000001DC) Receive Frame Count for Watchdog Error Frames */ + + struct + { + __IM uint32_t RXWDGERR : 16; /*!< [15..0] This field indicates the number of frames received with + * error because of the watchdog timeout error (frames with + * more than 2,048 bytes or value programmed in Watchdog Timeout + * Register (WDog_Timeout)). */ + uint32_t : 16; + } Rx_Watchdog_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Receive_Error_Frames; /*!< (@ 0x000001E0) Receive Frame Count for Receive Error Frames */ + + struct + { + __IM uint32_t RXRCVERR : 16; /*!< [15..0] This field indicates the number of frames received with + * error because of the GMII/MII RXER error or Frame Extension + * error on GMII. */ + uint32_t : 16; + } Rx_Receive_Error_Frames_b; + }; + + union + { + __IM uint32_t Rx_Control_Frames_Good; /*!< (@ 0x000001E4) Receive Frame Count for Good Control Frames */ + + struct + { + __IM uint32_t RXCTRLG : 32; /*!< [31..0] This field indicates the number of good control frames + * received. */ + } Rx_Control_Frames_Good_b; + }; + __IM uint32_t RESERVED4[134]; + + union + { + __IOM uint32_t GMACTRGSEL; /*!< (@ 0x00000400) GMAC PTP Trigger Select Register */ + + struct + { + __IOM uint32_t TRGSEL : 2; /*!< [1..0] Select PTP Timestamp Trigger for GMAC IP */ + uint32_t : 30; + } GMACTRGSEL_b; + }; + __IM uint32_t RESERVED5[63]; + + union + { + __IOM uint32_t HASH_TABLE_REG[8]; /*!< (@ 0x00000500) Hash Table Register [0..7] (n = 0 to 7) */ + + struct + { + __IOM uint32_t HT : 32; /*!< [31..0] This field contains the nth 32 bits [31:0] of the Hash + * table. */ + } HASH_TABLE_REG_b[8]; + }; + __IM uint32_t RESERVED6[26]; + + union + { + __IOM uint32_t VLAN_Hash_Table_Reg; /*!< (@ 0x00000588) VLAN Hash Table Register */ + + struct + { + __IOM uint32_t VLHT : 16; /*!< [15..0] VLAN Hash Table */ + uint32_t : 16; + } VLAN_Hash_Table_Reg_b; + }; + __IM uint32_t RESERVED7[93]; + + union + { + __IOM uint32_t Timestamp_Control; /*!< (@ 0x00000700) Timestamp Control Register */ + + struct + { + __IOM uint32_t TSENA : 1; /*!< [0..0] Timestamp Enable */ + uint32_t : 7; + __IOM uint32_t TSENALL : 1; /*!< [8..8] Enable Timestamp for all Frames */ + __IOM uint32_t TSCTRLSSR : 1; /*!< [9..9] Timestamp Digital or Binary Rollover Control */ + __IOM uint32_t TSVER2ENA : 1; /*!< [10..10] Enable PTP packet Processing for Version 2 Format */ + __IOM uint32_t TSIPENA : 1; /*!< [11..11] Enable Processing of PTP over Ethernet Frames */ + __IOM uint32_t TSIPV6ENA : 1; /*!< [12..12] Enable Processing of PTP Frames Sent Over IPv6 UDP */ + __IOM uint32_t TSIPV4ENA : 1; /*!< [13..13] Enable Processing of PTP Frames Sent over IPv4 UDP */ + __IOM uint32_t TSEVNTENA : 1; /*!< [14..14] Enable Timestamp Snapshot for Event Messages */ + __IOM uint32_t TSMSTRENA : 1; /*!< [15..15] Enable Snapshot for Messages Relevant to Master */ + __IOM uint32_t SNAPTYPSEL : 2; /*!< [17..16] Select PTP packets for Taking Snapshots */ + __IOM uint32_t TSENMACADDR : 1; /*!< [18..18] Enable MAC address for PTP Frame Filtering */ + uint32_t : 5; + __IOM uint32_t ATSFC : 1; /*!< [24..24] Auxiliary Snapshot FIFO Clear */ + __IOM uint32_t ATSEN0 : 1; /*!< [25..25] Auxiliary Snapshot 0 Enable */ + __IOM uint32_t ATSEN1 : 1; /*!< [26..26] Auxiliary Snapshot 1 Enable */ + uint32_t : 5; + } Timestamp_Control_b; + }; + __IM uint32_t RESERVED8[9]; + + union + { + __IM uint32_t Timestamp_Status; /*!< (@ 0x00000728) Timestamp Status Register */ + + struct + { + uint32_t : 2; + __IM uint32_t AUXTSTRIG : 1; /*!< [2..2] Auxiliary Timestamp Trigger Snapshot */ + uint32_t : 13; + __IM uint32_t ATSSTN : 4; /*!< [19..16] Auxiliary Timestamp Snapshot Trigger Identifier */ + uint32_t : 4; + __IM uint32_t ATSSTM : 1; /*!< [24..24] Auxiliary Timestamp Snapshot Trigger Missed */ + __IM uint32_t ATSNS : 5; /*!< [29..25] Number of Auxiliary Timestamp Snapshots */ + uint32_t : 2; + } Timestamp_Status_b; + }; + __IM uint32_t RESERVED9; + + union + { + __IM uint32_t Auxiliary_Timestamp_Nanoseconds; /*!< (@ 0x00000730) Auxiliary Timestamp - Nanoseconds Register */ + + struct + { + __IM uint32_t AUXTSLO : 31; /*!< [30..0] Contains the lower 32 bits (nanoseconds field) of the + * auxiliary timestamp. */ + uint32_t : 1; + } Auxiliary_Timestamp_Nanoseconds_b; + }; + + union + { + __IM uint32_t Auxiliary_Timestamp_Seconds; /*!< (@ 0x00000734) Auxiliary Timestamp - Seconds Register */ + + struct + { + __IM uint32_t AUXTSHI : 32; /*!< [31..0] Contains the upper 32 bits (Seconds field) of the auxiliary + * timestamp. */ + } Auxiliary_Timestamp_Seconds_b; + }; + __IM uint32_t RESERVED10[50]; + + union + { + __IOM uint32_t MAR16_H; /*!< (@ 0x00000800) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR16_H_b; + }; + + union + { + __IOM uint32_t MAR16_L; /*!< (@ 0x00000804) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR16_L_b; + }; + + union + { + __IOM uint32_t MAR17_H; /*!< (@ 0x00000808) MAC ADDRESS High Register */ + + struct + { + __IOM uint32_t ADDRHI : 16; /*!< [15..0] MAC Address n[47:32] */ + uint32_t : 8; + __IOM uint32_t MBC : 6; /*!< [29..24] Mask Byte Control */ + __IOM uint32_t SA : 1; /*!< [30..30] Source Address */ + __IOM uint32_t AE : 1; /*!< [31..31] Address Enable */ + } MAR17_H_b; + }; + + union + { + __IOM uint32_t MAR17_L; /*!< (@ 0x0000080C) MAC ADDRESS Low Register */ + + struct + { + __IOM uint32_t ADDRLO : 32; /*!< [31..0] MAC Address n[31:0] */ + } MAR17_L_b; + }; + __IM uint32_t RESERVED11[508]; + + union + { + __IOM uint32_t Bus_Mode; /*!< (@ 0x00001000) Bus Mode Register */ + + struct + { + __IOM uint32_t SWR : 1; /*!< [0..0] Software Reset */ + __IM uint32_t DA : 1; /*!< [1..1] DMA Arbitration Scheme */ + __IOM uint32_t DSL : 5; /*!< [6..2] Descriptor Skip Length */ + __IOM uint32_t ATDS : 1; /*!< [7..7] Enhanced Descriptor Size */ + __IOM uint32_t PBL : 6; /*!< [13..8] Programmable Burst Length */ + __IM uint32_t PR : 2; /*!< [15..14] Priority Ratio */ + __IOM uint32_t FB : 1; /*!< [16..16] Fixed Burst */ + __IOM uint32_t RPBL : 6; /*!< [22..17] RX DMA PBL */ + __IOM uint32_t USP : 1; /*!< [23..23] Use Separate PBL */ + __IOM uint32_t PBLx8 : 1; /*!< [24..24] PBLx8 Mode */ + __IOM uint32_t AAL : 1; /*!< [25..25] Address Aligned Beats */ + __IM uint32_t MB : 1; /*!< [26..26] Mixed Burst */ + __IM uint32_t TXPR : 1; /*!< [27..27] Transmit Priority */ + __IM uint32_t PRWG : 2; /*!< [29..28] Channel Priority Weights */ + uint32_t : 1; + __IM uint32_t RIB : 1; /*!< [31..31] Rebuild INCRx Burst */ + } Bus_Mode_b; + }; + + union + { + __IOM uint32_t Transmit_Poll_Demand; /*!< (@ 0x00001004) Transmit Poll Demand Register */ + + struct + { + __IOM uint32_t TPD : 32; /*!< [31..0] Transmit Poll Demand */ + } Transmit_Poll_Demand_b; + }; + + union + { + __IOM uint32_t Receive_Poll_Demand; /*!< (@ 0x00001008) Receive Poll Demand Register */ + + struct + { + __IOM uint32_t RPD : 32; /*!< [31..0] Receive Poll Demand */ + } Receive_Poll_Demand_b; + }; + + union + { + __IOM uint32_t Receive_Descriptor_List_Address; /*!< (@ 0x0000100C) Receive Descriptor List Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t RDESLA_32bit : 30; /*!< [31..2] Start of Receive List */ + } Receive_Descriptor_List_Address_b; + }; + + union + { + __IOM uint32_t Transmit_Descriptor_List_Address; /*!< (@ 0x00001010) Transmit Descriptor List Address Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t TDESLA_32bit : 30; /*!< [31..2] Start of Transmit List */ + } Transmit_Descriptor_List_Address_b; + }; + + union + { + __IOM uint32_t Status; /*!< (@ 0x00001014) Status Register */ + + struct + { + __IOM uint32_t TI : 1; /*!< [0..0] Transmit Interrupt */ + __IOM uint32_t TPS : 1; /*!< [1..1] Transmit Process Stopped */ + __IOM uint32_t TU : 1; /*!< [2..2] Transmit Buffer Unavailable */ + __IOM uint32_t TJT : 1; /*!< [3..3] Transmit Jabber Timeout */ + __IOM uint32_t OVF : 1; /*!< [4..4] Receive Overflow */ + __IOM uint32_t UNF : 1; /*!< [5..5] Transmit Underflow */ + __IOM uint32_t RI : 1; /*!< [6..6] Receive Interrupt */ + __IOM uint32_t RU : 1; /*!< [7..7] Receive Buffer Unavailable */ + __IOM uint32_t RPS : 1; /*!< [8..8] Receive Process Stopped */ + __IOM uint32_t RWT : 1; /*!< [9..9] Receive Watchdog Timeout */ + __IOM uint32_t ETI : 1; /*!< [10..10] Early Transmit Interrupt */ + uint32_t : 2; + __IOM uint32_t FBI : 1; /*!< [13..13] Fatal Bus Error Interrupt */ + __IOM uint32_t ERI : 1; /*!< [14..14] Early Receive Interrupt */ + __IOM uint32_t AIS : 1; /*!< [15..15] Abnormal Interrupt Summary */ + __IOM uint32_t NIS : 1; /*!< [16..16] Normal Interrupt Summary */ + __IM uint32_t RS : 3; /*!< [19..17] Received Process State */ + __IM uint32_t TS : 3; /*!< [22..20] Transmit Process State */ + __IM uint32_t EB : 3; /*!< [25..23] Error Bits */ + uint32_t : 1; + __IM uint32_t GMI : 1; /*!< [27..27] GMAC MMC Interrupt */ + __IM uint32_t GPI : 1; /*!< [28..28] GMAC PMT Interrupt */ + __IM uint32_t TTI : 1; /*!< [29..29] Timestamp Trigger Interrupt */ + __IM uint32_t GLPII : 1; /*!< [30..30] GMAC LPI Interrupt */ + uint32_t : 1; + } Status_b; + }; + + union + { + __IOM uint32_t Operation_Mode; /*!< (@ 0x00001018) Operation Mode Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t SR : 1; /*!< [1..1] Start or Stop Receive */ + __IOM uint32_t OSF : 1; /*!< [2..2] Operate on Second Frame */ + __IOM uint32_t RTC : 2; /*!< [4..3] Receive Threshold Control */ + __IOM uint32_t DGF : 1; /*!< [5..5] Drop Giant Frames */ + __IOM uint32_t FUF : 1; /*!< [6..6] Forward Undersized Good Frames */ + __IOM uint32_t FEF : 1; /*!< [7..7] Forward Error Frames */ + __IOM uint32_t EFC : 1; /*!< [8..8] Enable HW Flow Control */ + __IOM uint32_t RFA : 2; /*!< [10..9] Threshold for Activating Flow Control (in half-duplex + * and full-duplex) */ + __IOM uint32_t RFD : 2; /*!< [12..11] Threshold for Deactivating Flow Control (in half-duplex + * and full-duplex) */ + __IOM uint32_t ST : 1; /*!< [13..13] Start or Stop Transmission Command */ + __IOM uint32_t TTC : 3; /*!< [16..14] Transmit Threshold Control */ + uint32_t : 3; + __IOM uint32_t FTF : 1; /*!< [20..20] Flush Transmit FIFO */ + __IOM uint32_t TSF : 1; /*!< [21..21] Transmit Store and Forward */ + uint32_t : 3; + __IOM uint32_t RSF : 1; /*!< [25..25] Receive Store and Forward */ + __IOM uint32_t DT : 1; /*!< [26..26] Disable Dropping of TCP/IP Checksum Error Frames */ + uint32_t : 5; + } Operation_Mode_b; + }; + + union + { + __IOM uint32_t Interrupt_Enable; /*!< (@ 0x0000101C) Interrupt Enable Register */ + + struct + { + __IOM uint32_t TIE : 1; /*!< [0..0] Transmit Interrupt Enable */ + __IOM uint32_t TSE : 1; /*!< [1..1] Transmit Stopped Enable */ + __IOM uint32_t TUE : 1; /*!< [2..2] Transmit Buffer Unavailable Enable */ + __IOM uint32_t TJE : 1; /*!< [3..3] Transmit Jabber Timeout Enable */ + __IOM uint32_t OVE : 1; /*!< [4..4] Overflow Interrupt Enable */ + __IOM uint32_t UNE : 1; /*!< [5..5] Underflow Interrupt Enable */ + __IOM uint32_t RIE : 1; /*!< [6..6] Receive Interrupt Enable */ + __IOM uint32_t RUE : 1; /*!< [7..7] Receive Buffer Unavailable Enable */ + __IOM uint32_t RSE : 1; /*!< [8..8] Receive Stopped Enable */ + __IOM uint32_t RWE : 1; /*!< [9..9] Receive Watchdog Timeout Enable */ + __IOM uint32_t ETE : 1; /*!< [10..10] Early Transmit Interrupt Enable */ + uint32_t : 2; + __IOM uint32_t FBE : 1; /*!< [13..13] Fatal Bus Error Enable */ + __IOM uint32_t ERE : 1; /*!< [14..14] Early Receive Interrupt Enable */ + __IOM uint32_t AIE : 1; /*!< [15..15] Abnormal Interrupt Summary Enable */ + __IOM uint32_t NIE : 1; /*!< [16..16] Normal Interrupt Summary Enable */ + uint32_t : 15; + } Interrupt_Enable_b; + }; + + union + { + __IM uint32_t Missed_Frame_And_Buffer_Overflow_Counter; /*!< (@ 0x00001020) Missed Frame and Buffer Overflow Counter Register */ + + struct + { + __IM uint32_t MISFRMCNT : 16; /*!< [15..0] Missed Frame Counter */ + __IM uint32_t MISCNTOVF : 1; /*!< [16..16] Overflow Bit for Missed Frame Counter */ + __IM uint32_t OVFFRMCNT : 11; /*!< [27..17] Overflow Frame Counter */ + __IM uint32_t OVFCNTOVF : 1; /*!< [28..28] Overflow Bit for FIFO Overflow Counter */ + uint32_t : 3; + } Missed_Frame_And_Buffer_Overflow_Counter_b; + }; + + union + { + __IOM uint32_t Receive_Interrupt_Watchdog_Timer; /*!< (@ 0x00001024) Receive Interrupt Watchdog Timer Register */ + + struct + { + __IOM uint32_t RIWT : 8; /*!< [7..0] RI Watchdog Timer Count */ + uint32_t : 24; + } Receive_Interrupt_Watchdog_Timer_b; + }; + + union + { + __IOM uint32_t AXI_Bus_Mode; /*!< (@ 0x00001028) AXI Bus Mode Register */ + + struct + { + __IM uint32_t UNDEF : 1; /*!< [0..0] AXI Undefined Burst Length */ + __IOM uint32_t BLEN4 : 1; /*!< [1..1] AXI Burst Length 4 */ + __IOM uint32_t BLEN8 : 1; /*!< [2..2] AXI Burst Length 8 */ + __IOM uint32_t BLEN16 : 1; /*!< [3..3] AXI Burst Length 16 */ + uint32_t : 8; + __IM uint32_t AXI_AAL : 1; /*!< [12..12] Address-Aligned Beats */ + __IOM uint32_t ONEKBBE : 1; /*!< [13..13] 1 KB Boundary Crossing Enable for the GMAC-AXI Master */ + uint32_t : 2; + __IOM uint32_t RD_OSR_LMT : 2; /*!< [17..16] AXI Maximum Read OutStanding Request Limit */ + uint32_t : 2; + __IOM uint32_t WR_OSR_LMT : 2; /*!< [21..20] AXI Maximum Write OutStanding Request Limit */ + uint32_t : 8; + __IOM uint32_t LPI_XIT_FRM : 1; /*!< [30..30] Unlock on Magic Packet or Remote Wake-Up Frame */ + __IOM uint32_t EN_LPI : 1; /*!< [31..31] Enable Low Power Interface (LPI) */ + } AXI_Bus_Mode_b; + }; + + union + { + __IM uint32_t AXI_Status; /*!< (@ 0x0000102C) AXI Status Register */ + + struct + { + __IM uint32_t AXWHSTS : 1; /*!< [0..0] AXI Master Write Channel */ + __IM uint32_t AXIRDSTS : 1; /*!< [1..1] AXI Master Read Channel Status */ + uint32_t : 30; + } AXI_Status_b; + }; + __IM uint32_t RESERVED12[6]; + + union + { + __IM uint32_t Current_Host_Transmit_Descriptor; /*!< (@ 0x00001048) Current Host Transmit Descriptor Register */ + + struct + { + __IM uint32_t CURTDESAPTR : 32; /*!< [31..0] Host Transmit Descriptor Address Pointer */ + } Current_Host_Transmit_Descriptor_b; + }; + + union + { + __IM uint32_t Current_Host_Receive_Descriptor; /*!< (@ 0x0000104C) Current Host Receive Descriptor Register */ + + struct + { + __IM uint32_t CURRDESAPTR : 32; /*!< [31..0] Host Receive Descriptor Address Pointer */ + } Current_Host_Receive_Descriptor_b; + }; + + union + { + __IM uint32_t Current_Host_Transmit_Buffer_Address; /*!< (@ 0x00001050) Current Host Transmit Buffer Address Register */ + + struct + { + __IM uint32_t CURTBUFAPTR : 32; /*!< [31..0] Host Transmit Buffer Address Pointer */ + } Current_Host_Transmit_Buffer_Address_b; + }; + + union + { + __IM uint32_t Current_Host_Receive_Buffer_Address; /*!< (@ 0x00001054) Current Host Receive Buffer Address Register */ + + struct + { + __IM uint32_t CURRBUFAPTR : 32; /*!< [31..0] Host Receive Buffer Address Pointer */ + } Current_Host_Receive_Buffer_Address_b; + }; + + union + { + __IM uint32_t HW_Feature; /*!< (@ 0x00001058) HW Feature Register */ + + struct + { + __IM uint32_t MIISEL : 1; /*!< [0..0] 10 or 100 Mbps support */ + __IM uint32_t GMIISEL : 1; /*!< [1..1] 1000 Mbps support */ + __IM uint32_t HDSEL : 1; /*!< [2..2] Half-Duplex support */ + __IM uint32_t EXTHASHEN : 1; /*!< [3..3] Expanded DA Hash Filter */ + __IM uint32_t HASHSEL : 1; /*!< [4..4] HASH Filter */ + __IM uint32_t ADDMACADRSEL : 1; /*!< [5..5] Multiple MAC Address Registers */ + uint32_t : 1; + __IM uint32_t L3L4FLTREN : 1; /*!< [7..7] Layer 3 and Layer 4 Filter Feature */ + __IM uint32_t SMASEL : 1; /*!< [8..8] SMA (MDIO) Interface */ + __IM uint32_t RWKSEL : 1; /*!< [9..9] PMT Remote wakeup */ + __IM uint32_t MGKSEL : 1; /*!< [10..10] PMT Magic Packet */ + __IM uint32_t MMCSEL : 1; /*!< [11..11] RMON Module */ + __IM uint32_t TSVER1SEL : 1; /*!< [12..12] Only IEEE 1588-2002 Timestamp */ + __IM uint32_t TSVER2SEL : 1; /*!< [13..13] IEEE 1588-2008 Advanced Timestamp */ + __IM uint32_t EEESEL : 1; /*!< [14..14] Energy Efficient Ethernet */ + __IM uint32_t AVSEL : 1; /*!< [15..15] AV Feature */ + __IM uint32_t TXCOESEL : 1; /*!< [16..16] Checksum Offload in TX */ + __IM uint32_t RXTYP1COE : 1; /*!< [17..17] IP Checksum Offload (Type 1) in RX */ + __IM uint32_t RXTYP2COE : 1; /*!< [18..18] IP Checksum Offload (Type 2) in RX */ + __IM uint32_t RXFIFOSIZE : 1; /*!< [19..19] RX FIFO > 2,048 Bytes */ + __IM uint32_t RXCHCNT : 2; /*!< [21..20] Number of additional RX channels */ + __IM uint32_t TXCHCNT : 2; /*!< [23..22] Number of additional TX channels */ + __IM uint32_t ENHDESSEL : 1; /*!< [24..24] Enhanced Descriptor */ + __IM uint32_t INTTSEN : 1; /*!< [25..25] Timestamping with Internal System Time */ + __IM uint32_t FLEXIPPSEN : 1; /*!< [26..26] Flexible Pulse-Per-Second Output (GMAC: 0) */ + __IM uint32_t SAVLANINS : 1; /*!< [27..27] Source Address or VLAN Insertion */ + __IM uint32_t ACTPHYIF : 3; /*!< [30..28] Active or Selected PHY interface */ + uint32_t : 1; + } HW_Feature_b; + }; +} R_GMAC_Type; /*!< Size = 4188 (0x105c) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Subsystem (R_ETHSS) + */ + +typedef struct /*!< (@ 0x80110000) R_ETHSS Structure */ +{ + __IOM uint32_t PRCMD; /*!< (@ 0x00000000) Ethernet Protect Register */ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t MODCTRL; /*!< (@ 0x00000008) Mode Control Register */ + + struct + { + __IOM uint32_t SW_MODE : 3; /*!< [2..0] Media I/F connectionSW_MODE[2:0]Media I/FPort 0Port 1Port + * 2000bETHSW Port 0ETHSW Port 1ETHSW Port 2001bESC Port 0ESC + * Port 1GMAC Port010bESC Port 0ESC Port 1ETHSW Port 2011bESC + * Port 0ESC Port 1ESC Port 2100bETHSW Port 0ESC Port 1ESC + * Port 2101bETHSW Port 0ESC Port 1ETHSW Port 2110b-ETHSW + * Port 1ETHSW Port 0111b-ESC Port 1ESC Port 0 */ + uint32_t : 29; + } MODCTRL_b; + }; + + union + { + __IOM uint32_t PTPMCTRL; /*!< (@ 0x0000000C) PTP Mode Control Register */ + + struct + { + __IOM uint32_t PTP_MODE : 1; /*!< [0..0] Select the unit number of PTP Timer for GMAC and Pulse + * Generator (unit 0 - 3) */ + uint32_t : 15; + __IOM uint32_t PTP_PLS_RSTn : 1; /*!< [16..16] Reset control for Pulse Generator (unit 0 - 3) */ + uint32_t : 15; + } PTPMCTRL_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IOM uint32_t PHYLNK; /*!< (@ 0x00000014) Ethernet PHY Link Mode Register */ + + struct + { + __IOM uint32_t SWLINK : 3; /*!< [2..0] Specify the active level of the ETHSW_PHYLINKn signal + * using the Ethernet switch interface */ + uint32_t : 1; + __IOM uint32_t CATLNK : 3; /*!< [6..4] Specify the active level of the ESC_PHYLINKn signal using + * the EtherCAT interface */ + uint32_t : 25; + } PHYLNK_b; + }; + __IM uint32_t RESERVED2[58]; + + union + { + __IOM uint32_t CONVCTRL[3]; /*!< (@ 0x00000100) RGMII/RMII Converter [0..2] Control Register */ + + struct + { + __IOM uint32_t CONV_MODE : 5; /*!< [4..0] Converter operation mode */ + uint32_t : 3; + __IOM uint32_t FULLD : 1; /*!< [8..8] FULLD */ + __IOM uint32_t RMII_RX_ER_EN : 1; /*!< [9..9] RMII_RX_ER_EN */ + __IOM uint32_t RMII_CRS_MODE : 1; /*!< [10..10] RMII_CRS_MODE */ + uint32_t : 1; + __IM uint32_t RGMII_LINK : 1; /*!< [12..12] RGMII_LINK */ + __IM uint32_t RGMII_DUPLEX : 1; /*!< [13..13] RGMII_DUPLEX */ + __IM uint32_t RGMII_SPEED : 2; /*!< [15..14] RGMII_SPEED */ + uint32_t : 16; + } CONVCTRL_b[3]; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IOM uint32_t CONVRST; /*!< (@ 0x00000114) RGMII/RMII Converter Reset Control Register */ + + struct + { + __IOM uint32_t PHYIR : 3; /*!< [2..0] PHYIR */ + uint32_t : 29; + } CONVRST_b; + }; + __IM uint32_t RESERVED4[123]; + + union + { + __IOM uint32_t SWCTRL; /*!< (@ 0x00000304) Switch Core Control Register */ + + struct + { + __IOM uint32_t SET10 : 3; /*!< [2..0] Port control to select use of 10 Mbps. Bit 0 = port 0, + * bit 1 = port 1, bit 2 = port 2. */ + uint32_t : 1; + __IOM uint32_t SET1000 : 3; /*!< [6..4] Port control to select use of 1000 Mbps. Bit 0 = port + * 0, bit 1 = port 1, bit 2 = port 2. */ + uint32_t : 9; + __IOM uint32_t STRAP_SX_ENB : 1; /*!< [16..16] Initialize switch after reset (set during module reset + * of ETHSW) */ + __IOM uint32_t STRAP_HUB_ENB : 1; /*!< [17..17] Initialize switch port 0 and 1 (set during module reset + * of ETHSW) */ + uint32_t : 14; + } SWCTRL_b; + }; + + union + { + __IOM uint32_t SWDUPC; /*!< (@ 0x00000308) Switch Core Duplex Mode Register */ + + struct + { + __IOM uint32_t PHY_DUPLEX : 3; /*!< [2..0] Configure the MAC of each port for full-duplex or half-duplex + * operation. Bit 0 = port 0, bit 1 = port 1, bit 2 = port + * 2. */ + uint32_t : 29; + } SWDUPC_b; + }; + __IM uint32_t RESERVED5[573]; + + union + { + __IOM uint32_t CDCR; /*!< (@ 0x00000C00) RGMII Clock Delay Control Register */ + + struct + { + __IOM uint32_t RXDLYEN : 1; /*!< [0..0] Enable delay for ETH2_RXCLK */ + __IOM uint32_t TXDLYEN : 1; /*!< [1..1] Enable delay for ETH2_TXCLK */ + __IOM uint32_t OSCCLKEN : 1; /*!< [2..2] Enable Oscillation mode for calibration */ + __IOM uint32_t CLKINEN : 1; /*!< [3..3] Enable Phase shift mode for normal operation */ + uint32_t : 28; + } CDCR_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IM uint32_t RXFCNT; /*!< (@ 0x00000C10) RGMII RX OSC Frequency Measurement Counter Register */ + + struct + { + __IM uint32_t RXFCNT : 16; /*!< [15..0] Oscillation frequency measurement counter for ETH2_RXCLK + * delay */ + uint32_t : 16; + } RXFCNT_b; + }; + + union + { + __IM uint32_t TXFCNT; /*!< (@ 0x00000C14) RGMII TX OSC Frequency Measurement Counter Register */ + + struct + { + __IM uint32_t TXFCNT : 16; /*!< [15..0] Oscillation frequency measurement counter for ETH2_TXCLK + * delay */ + uint32_t : 16; + } TXFCNT_b; + }; + + union + { + __IOM uint32_t RXTAPSEL; /*!< (@ 0x00000C18) RGMII RX TAP Selection Register */ + + struct + { + __IOM uint32_t RXTAPSEL : 7; /*!< [6..0] TAP selection for ETH2_RXCLK delay (number of taps for + * 90 degree phase shift) */ + uint32_t : 25; + } RXTAPSEL_b; + }; + + union + { + __IOM uint32_t TXTAPSEL; /*!< (@ 0x00000C1C) RGMII TX TAP Selection Register */ + + struct + { + __IOM uint32_t TXTAPSEL : 7; /*!< [6..0] TAP selection for ETH2_TXCLK delay (Number of taps for + * 90 degree phase shift) */ + uint32_t : 25; + } TXTAPSEL_b; + }; + + union + { + __IOM uint32_t MIIMCR; /*!< (@ 0x00000C20) MII Mode Control Register */ + + struct + { + __IOM uint32_t MIIM2MEN : 1; /*!< [0..0] Enable MAC-to-MAC MII Mode */ + uint32_t : 31; + } MIIMCR_b; + }; +} R_ETHSS_Type; /*!< Size = 3108 (0xc24) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC_INI ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Initial Configuration 1 for EtherCAT Slave Controller (R_ESC_INI) + */ + +typedef struct /*!< (@ 0x80110200) R_ESC_INI Structure */ +{ + union + { + __IOM uint32_t ECATOFFADR; /*!< (@ 0x00000000) EtherCAT PHY Offset Address Setting Register */ + + struct + { + __IOM uint32_t OADD : 5; /*!< [4..0] PHY Offset Address Setting */ + uint32_t : 27; + } ECATOFFADR_b; + }; + + union + { + __IOM uint32_t ECATOPMOD; /*!< (@ 0x00000004) EtherCAT Operation Mode Register */ + + struct + { + __IOM uint32_t EEPROMSIZE : 1; /*!< [0..0] EEPROM Memory Size Specification */ + uint32_t : 31; + } ECATOPMOD_b; + }; + + union + { + __IOM uint32_t ECATDBGC; /*!< (@ 0x00000008) EtherCAT Debug Control Register */ + + struct + { + __IOM uint32_t TXSFT0 : 2; /*!< [1..0] Set the delay time for ETH0_TXEN and ETH0_TXDn of the + * EtherCAT */ + __IOM uint32_t TXSFT1 : 2; /*!< [3..2] Set the delay time for ETH1_TXEN and ETH1_TXDn of the + * EtherCAT */ + __IOM uint32_t TXSFT2 : 2; /*!< [5..4] Set the delay time for ETH2_TXEN and ETH2_TXDn of the + * EtherCAT */ + uint32_t : 26; + } ECATDBGC_b; + }; + + union + { + __IOM uint32_t ECATTRGSEL; /*!< (@ 0x0000000C) EtherCAT DC Latch Trigger Select Register */ + + struct + { + __IOM uint32_t TRGSEL0 : 1; /*!< [0..0] Select DC Latch Trigger 0 for ESC */ + __IOM uint32_t TRGSEL1 : 1; /*!< [1..1] Select DC Latch Trigger 1 for ESC */ + uint32_t : 30; + } ECATTRGSEL_b; + }; +} R_ESC_INI_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSW_PTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Switch for PTP (R_ETHSW_PTP) + */ + +typedef struct /*!< (@ 0x80110400) R_ETHSW_PTP Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SWPTPOUTSEL; /*!< (@ 0x00000004) ETHSW_PTPOUT Select Register */ + + struct + { + __IOM uint32_t IOSEL0 : 1; /*!< [0..0] Select the source of the ETHSW_PTPOUT0 output signal */ + __IOM uint32_t IOSEL1 : 1; /*!< [1..1] Select the source of the ETHSW_PTPOUT1 output signal */ + __IOM uint32_t IOSEL2 : 1; /*!< [2..2] Select the source of the ETHSW_PTPOUT2 output signal */ + __IOM uint32_t IOSEL3 : 1; /*!< [3..3] Select the source of the ETHSW_PTPOUT3 output signal */ + __IOM uint32_t EVTSEL0 : 1; /*!< [4..4] Select the source of the ETHSW_PTPOUT0 event for GIC, + * DMAC, and ELC */ + __IOM uint32_t EVTSEL1 : 1; /*!< [5..5] Select the source of the ETHSW_PTPOUT1 event for GIC, + * DMAC, and ELC */ + __IOM uint32_t EVTSEL2 : 1; /*!< [6..6] Select the source of the ETHSW_PTPOUT2 event for GIC, + * DMAC, and ELC */ + __IOM uint32_t EVTSEL3 : 1; /*!< [7..7] Select the source of the ETHSW_PTPOUT3 event for GIC, + * DMAC, and ELC */ + uint32_t : 24; + } SWPTPOUTSEL_b; + }; + __IM uint32_t RESERVED1[254]; + __IOM R_ETHSW_PTP_SWTM_Type SWTM[4]; /*!< (@ 0x00000400) Ethernet Switch Timer output pins 0-3 Registers */ +} R_ETHSW_PTP_Type; /*!< Size = 2048 (0x800) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSW ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Ethernet Switch (R_ETHSW) + */ + +typedef struct /*!< (@ 0x80120000) R_ETHSW Structure */ +{ + union + { + __IM uint32_t REVISION; /*!< (@ 0x00000000) Switch Core Version Register */ + + struct + { + __IM uint32_t REV : 32; /*!< [31..0] Revision */ + } REVISION_b; + }; + + union + { + __IOM uint32_t SCRATCH; /*!< (@ 0x00000004) Scratch Register */ + + struct + { + __IOM uint32_t SCRATCH : 32; /*!< [31..0] The Scratch Register provides a memory location to test + * the register access. */ + } SCRATCH_b; + }; + + union + { + __IOM uint32_t PORT_ENA; /*!< (@ 0x00000008) Port Enable Register */ + + struct + { + __IOM uint32_t TXENA : 4; /*!< [3..0] Transmit Enable Mask */ + uint32_t : 12; + __IOM uint32_t RXENA : 4; /*!< [19..16] Receive Enable Mask */ + uint32_t : 12; + } PORT_ENA_b; + }; + + union + { + __IOM uint32_t UCAST_DEFAULT_MASK0; /*!< (@ 0x0000000C) Unicast Default Mask Register 0 */ + + struct + { + __IOM uint32_t UCASTDM : 4; /*!< [3..0] Default Unicast Resolution */ + uint32_t : 28; + } UCAST_DEFAULT_MASK0_b; + }; + + union + { + __IOM uint32_t VLAN_VERIFY; /*!< (@ 0x00000010) Verify VLAN Domain Register */ + + struct + { + __IOM uint32_t VLANVERI : 4; /*!< [3..0] Verify VLAN Domain */ + uint32_t : 12; + __IOM uint32_t VLANDISC : 4; /*!< [19..16] Discard Unknown */ + uint32_t : 12; + } VLAN_VERIFY_b; + }; + + union + { + __IOM uint32_t BCAST_DEFAULT_MASK0; /*!< (@ 0x00000014) Broadcast Default Mask Register 0 */ + + struct + { + __IOM uint32_t BCASTDM : 4; /*!< [3..0] Default Broadcast Resolution */ + uint32_t : 28; + } BCAST_DEFAULT_MASK0_b; + }; + + union + { + __IOM uint32_t MCAST_DEFAULT_MASK0; /*!< (@ 0x00000018) Multicast Default Mask Register 0 */ + + struct + { + __IOM uint32_t MCASTDM : 4; /*!< [3..0] Default Multicast Resolution */ + uint32_t : 28; + } MCAST_DEFAULT_MASK0_b; + }; + + union + { + __IOM uint32_t INPUT_LEARN_BLOCK; /*!< (@ 0x0000001C) Input Learning Block Register */ + + struct + { + __IOM uint32_t BLOCKEN : 4; /*!< [3..0] Blocking Enable */ + uint32_t : 12; + __IOM uint32_t LEARNDIS : 4; /*!< [19..16] Learning Disable */ + uint32_t : 12; + } INPUT_LEARN_BLOCK_b; + }; + + union + { + __IOM uint32_t MGMT_CONFIG; /*!< (@ 0x00000020) Management Configuration Register */ + + struct + { + __IOM uint32_t PORT : 4; /*!< [3..0] The Port number of the port that should act as a management + * port. Keep the initial value. */ + uint32_t : 1; + __IOM uint32_t MSG_TRANS : 1; /*!< [5..5] Set (latched) when a BPDU message is transmitted from + * the management port to any output port. This bit can be + * used for handshaking to indicate that the port mask bits + * are used and can now be changed again by setting it to + * 0. */ + __IOM uint32_t ENABLE : 1; /*!< [6..6] If set, all Bridge Protocol Frames (BPDU) are forwarded + * exclusively to the management port specified in bits [3:0]. */ + __IOM uint32_t DISCARD : 1; /*!< [7..7] If set, BPDU frames are discarded always. */ + __IOM uint32_t MGMT_EN : 1; /*!< [8..8] If set, BPDU frames received at the management port are + * forwarded to the ports given in the portmask given in this + * register, bypassing the normal forwarding decisions (except + * forced forwarding). */ + __IOM uint32_t MGMT_DISC : 1; /*!< [9..9] This bit is the same as DISCARD (bit 7) but for the management + * port. */ + uint32_t : 3; + __IOM uint32_t PRIORITY : 3; /*!< [15..13] Priority to use for transmitted BPDU frames if non-zero. */ + __IOM uint32_t PORTMASK : 4; /*!< [19..16] Portmask for transmission of management frames. When + * the management port transmits a frame to the switch, it + * is forwarded to all ports in this portmask (bit 16 = port + * 0, bit 17 = port 1, ..., bit 19 = port 3). */ + uint32_t : 12; + } MGMT_CONFIG_b; + }; + + union + { + __IOM uint32_t MODE_CONFIG; /*!< (@ 0x00000024) Mode Configuration Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t CUT_THRU_EN : 4; /*!< [11..8] Port Cut through Support Enable */ + uint32_t : 19; + __IOM uint32_t STATSRESET : 1; /*!< [31..31] Reset Statistics Counters Command. */ + } MODE_CONFIG_b; + }; + + union + { + __IOM uint32_t VLAN_IN_MODE; /*!< (@ 0x00000028) VLAN Input Manipulation Mode Register */ + + struct + { + __IOM uint32_t P0VLANINMD : 2; /*!< [1..0] Port 0 Define Behavior of VLAN Input Manipulation Function */ + __IOM uint32_t P1VLANINMD : 2; /*!< [3..2] Port 1 Define Behavior of VLAN Input Manipulation Function */ + __IOM uint32_t P2VLANINMD : 2; /*!< [5..4] Port 2 Define Behavior of VLAN Input Manipulation Function */ + __IOM uint32_t P3VLANINMD : 2; /*!< [7..6] Port3 Define Behavior of VLAN Input Manipulation Function */ + uint32_t : 24; + } VLAN_IN_MODE_b; + }; + + union + { + __IOM uint32_t VLAN_OUT_MODE; /*!< (@ 0x0000002C) VLAN Output Manipulation Mode Register */ + + struct + { + __IOM uint32_t P0VLANOUTMD : 2; /*!< [1..0] Port 0 Define Behavior of VLAN Output Manipulation Function */ + __IOM uint32_t P1VLANOUTMD : 2; /*!< [3..2] Port 1 Define Behavior of VLAN Output Manipulation Function */ + __IOM uint32_t P2VLANOUTMD : 2; /*!< [5..4] Port 2 Define Behavior of VLAN Output Manipulation Function */ + __IOM uint32_t P3VLANOUTMD : 2; /*!< [7..6] Port 3 Define Behavior of VLAN Output Manipulation Function */ + uint32_t : 24; + } VLAN_OUT_MODE_b; + }; + + union + { + __IOM uint32_t VLAN_IN_MODE_ENA; /*!< (@ 0x00000030) VLAN Input Mode Enable Register */ + + struct + { + __IOM uint32_t VLANINMDEN : 4; /*!< [3..0] Enable the input processing according to the VLAN_IN_MODE + * for a port (1 bit per port). */ + uint32_t : 28; + } VLAN_IN_MODE_ENA_b; + }; + + union + { + __IOM uint32_t VLAN_TAG_ID; /*!< (@ 0x00000034) VLAN Tag ID Register */ + + struct + { + __IOM uint32_t VLANTAGID : 16; /*!< [15..0] The VLAN type field (TPID) value to expect to identify + * a VLAN tagged frame. */ + uint32_t : 16; + } VLAN_TAG_ID_b; + }; + + union + { + __IOM uint32_t BCAST_STORM_LIMIT; /*!< (@ 0x00000038) Broadcast Storm Protection Register */ + + struct + { + __IOM uint32_t TMOUT : 16; /*!< [15..0] Timeout in steps of 65535 switch operating clock cycles. */ + __IOM uint32_t BCASTLIMIT : 16; /*!< [31..16] Number of broadcast frames (-1) that can be accepted + * on a port during a timeout period. If more are received, + * they are discarded. The counter is implemented per port + * independently. However, the limit is used for all ports. */ + } BCAST_STORM_LIMIT_b; + }; + + union + { + __IOM uint32_t MCAST_STORM_LIMIT; /*!< (@ 0x0000003C) Multicast Storm Protection Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t MCASTLIMIT : 16; /*!< [31..16] Number of multicast frames (-1) that can be accepted + * on a port during a timeout period. If more are received, + * they are discarded. The counter is implemented per port + * independently. However, the limit is used for all ports. */ + } MCAST_STORM_LIMIT_b; + }; + + union + { + __IOM uint32_t MIRROR_CONTROL; /*!< (@ 0x00000040) Port Mirroring Configuration Register */ + + struct + { + __IOM uint32_t PORT : 2; /*!< [1..0] The port number of the port that acts as the mirror port + * and receives all mirrored frames. Valid setting range is + * 0 to 3. */ + uint32_t : 2; + __IOM uint32_t MIRROR_EN : 1; /*!< [4..4] MIRROR_EN */ + __IOM uint32_t ING_MAP_EN : 1; /*!< [5..5] If set, the ingress map is enabled (MIRROR_ING_MAP). */ + __IOM uint32_t EG_MAP_EN : 1; /*!< [6..6] If set, the egress map is enabled (MIRROR_EG_MAP). */ + __IOM uint32_t ING_SA_MATCH : 1; /*!< [7..7] If set, only frames received on an ingress port with + * a source address matching the value programmed in MIRROR_ISRC + * registers are mirrored. Other frames are not mirrored. */ + __IOM uint32_t ING_DA_MATCH : 1; /*!< [8..8] If set, only frames received on an ingress port with + * a destination address matching the value programmed in + * MIRROR_IDST registers are mirrored. Other frames are not + * mirrored. */ + __IOM uint32_t EG_SA_MATCH : 1; /*!< [9..9] If set, only frames transmitted on an egress port with + * a source address matching the value programmed in MIRROR_ESRC + * registers are mirrored. Other frames are not mirrored. */ + __IOM uint32_t EG_DA_MATCH : 1; /*!< [10..10] If set, only frames transmitted on an egress port with + * a destination address matching the value programmed in + * MIRROR_EDST registers are mirrored. Other frames are not + * mirrored. */ + uint32_t : 21; + } MIRROR_CONTROL_b; + }; + + union + { + __IOM uint32_t MIRROR_EG_MAP; /*!< (@ 0x00000044) Port Mirroring Egress Port Definition Register */ + + struct + { + __IOM uint32_t EMAP : 4; /*!< [3..0] Port Mirroring Egress Port Definitions */ + uint32_t : 28; + } MIRROR_EG_MAP_b; + }; + + union + { + __IOM uint32_t MIRROR_ING_MAP; /*!< (@ 0x00000048) Port Mirroring Ingress Port Definition Register */ + + struct + { + __IOM uint32_t IMAP : 4; /*!< [3..0] Port Mirroring Ingress Port Definitions */ + uint32_t : 28; + } MIRROR_ING_MAP_b; + }; + + union + { + __IOM uint32_t MIRROR_ISRC_0; /*!< (@ 0x0000004C) Ingress Source MAC Address for Mirror Filtering + * Register 0 */ + + struct + { + __IOM uint32_t ISRC : 32; /*!< [31..0] Ingress Source MAC Address for Mirror Filtering */ + } MIRROR_ISRC_0_b; + }; + + union + { + __IOM uint32_t MIRROR_ISRC_1; /*!< (@ 0x00000050) Ingress Source MAC Address for Mirror Filtering + * Register 1 */ + + struct + { + __IOM uint32_t ISRC : 16; /*!< [15..0] Ingress Source MAC Address for Mirror Filtering */ + uint32_t : 16; + } MIRROR_ISRC_1_b; + }; + + union + { + __IOM uint32_t MIRROR_IDST_0; /*!< (@ 0x00000054) Ingress Destination MAC Address for Mirror Filtering + * Register 0 */ + + struct + { + __IOM uint32_t IDST : 32; /*!< [31..0] Ingress Destination MAC Address for Mirror Filtering */ + } MIRROR_IDST_0_b; + }; + + union + { + __IOM uint32_t MIRROR_IDST_1; /*!< (@ 0x00000058) Ingress Destination MAC Address for Mirror Filtering + * Register 1 */ + + struct + { + __IOM uint32_t IDST : 16; /*!< [15..0] Ingress Destination MAC Address for Mirror Filtering */ + uint32_t : 16; + } MIRROR_IDST_1_b; + }; + + union + { + __IOM uint32_t MIRROR_ESRC_0; /*!< (@ 0x0000005C) Egress Source MAC Address for Mirror Filtering + * Register 0 */ + + struct + { + __IOM uint32_t ESRC : 32; /*!< [31..0] Egress Source MAC Address for Mirror Filtering */ + } MIRROR_ESRC_0_b; + }; + + union + { + __IOM uint32_t MIRROR_ESRC_1; /*!< (@ 0x00000060) Egress Source MAC Address for Mirror Filtering + * Register 1 */ + + struct + { + __IOM uint32_t ESRC : 16; /*!< [15..0] Egress Source MAC Address for Mirror Filtering */ + uint32_t : 16; + } MIRROR_ESRC_1_b; + }; + + union + { + __IOM uint32_t MIRROR_EDST_0; /*!< (@ 0x00000064) Egress Destination MAC Address for Mirror Filtering + * Register 0 */ + + struct + { + __IOM uint32_t EDST : 32; /*!< [31..0] Egress Destination MAC Address for Mirror Filtering */ + } MIRROR_EDST_0_b; + }; + + union + { + __IOM uint32_t MIRROR_EDST_1; /*!< (@ 0x00000068) Egress Destination MAC Address for Mirror Filtering + * Register 1 */ + + struct + { + __IOM uint32_t EDST : 16; /*!< [15..0] Egress Destination MAC Address for Mirror Filtering */ + uint32_t : 16; + } MIRROR_EDST_1_b; + }; + + union + { + __IOM uint32_t MIRROR_CNT; /*!< (@ 0x0000006C) Mirror Filtering Count Value Register */ + + struct + { + __IOM uint32_t CNT : 8; /*!< [7..0] Count Value for Mirror Filtering */ + uint32_t : 24; + } MIRROR_CNT_b; + }; + + union + { + __IOM uint32_t UCAST_DEFAULT_MASK1; /*!< (@ 0x00000070) Unicast Default Mask Register 1 */ + + struct + { + __IOM uint32_t UCASTDM1 : 4; /*!< [3..0] Default Unicast Resolution Mask 1 */ + uint32_t : 28; + } UCAST_DEFAULT_MASK1_b; + }; + + union + { + __IOM uint32_t BCAST_DEFAULT_MASK1; /*!< (@ 0x00000074) Broadcast Default Mask Register 1 */ + + struct + { + __IOM uint32_t BCASTDM1 : 4; /*!< [3..0] Default Broadcast Resolution Mask 1 */ + uint32_t : 28; + } BCAST_DEFAULT_MASK1_b; + }; + + union + { + __IOM uint32_t MCAST_DEFAULT_MASK1; /*!< (@ 0x00000078) Multicast Default Mask Register 1 */ + + struct + { + __IOM uint32_t MCASTDM1 : 4; /*!< [3..0] Default Multicast Resolution Mask 1 */ + uint32_t : 28; + } MCAST_DEFAULT_MASK1_b; + }; + + union + { + __IOM uint32_t PORT_XCAST_MASK_SEL; /*!< (@ 0x0000007C) Port Mask Select Register */ + + struct + { + __IOM uint32_t MSEL : 4; /*!< [3..0] Mask Select */ + uint32_t : 28; + } PORT_XCAST_MASK_SEL_b; + }; + __IM uint32_t RESERVED[2]; + + union + { + __IOM uint32_t QMGR_ST_MINCELLS; /*!< (@ 0x00000088) Minimum Memory Cell Statistics Register */ + + struct + { + __IOM uint32_t STMINCELLS : 11; /*!< [10..0] Minimum Free Cell Indication */ + uint32_t : 21; + } QMGR_ST_MINCELLS_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t QMGR_RED_MIN4; /*!< (@ 0x00000094) RED Minimum Threshold Register */ + + struct + { + __IOM uint32_t CFGRED_MINTH4 : 32; /*!< [31..0] Random Early Detection (RED) Minimum Threshold for Queues + * 0 to 3 */ + } QMGR_RED_MIN4_b; + }; + + union + { + __IOM uint32_t QMGR_RED_MAX4; /*!< (@ 0x00000098) RED Maximum Threshold Register */ + + struct + { + __IOM uint32_t CFGRED_MAXTH4 : 32; /*!< [31..0] Random Early Detection (RED) Maximum Threshold for Queues + * 0 to 3 */ + } QMGR_RED_MAX4_b; + }; + + union + { + __IOM uint32_t QMGR_RED_CONFIG; /*!< (@ 0x0000009C) RED Configuration Register */ + + struct + { + __IOM uint32_t QUEUE_RED_EN : 4; /*!< [3..0] Enable Random Early Detection (RED) (when this bit is + * 1) or Tail Drop (when this bit is 0) congestion management + * for a queue. */ + uint32_t : 4; + __IOM uint32_t GACTIVITY_EN : 1; /*!< [8..8] Enable Averaging on Global Switch Activity (when this + * bit is 1) or on port local activity (when this bit is 0) + * only. */ + uint32_t : 23; + } QMGR_RED_CONFIG_b; + }; + + union + { + __IM uint32_t IMC_STATUS; /*!< (@ 0x000000A0) Input Memory Controller Status Register */ + + struct + { + __IM uint32_t CELLS_AVAILABLE : 24; /*!< [23..0] Total number of memory cells (128-byte units) available + * in the shared memory (real time). */ + __IM uint32_t CF_ERR : 1; /*!< [24..24] Cell Factory Empty Error */ + __IM uint32_t DE_ERR : 1; /*!< [25..25] Deallocation Error */ + __IM uint32_t DE_INIT : 1; /*!< [26..26] Asserts during Memory Initialization (deallocation + * module) */ + __IM uint32_t MEM_FULL : 1; /*!< [27..27] Latched Indication that Memory is or was Full */ + uint32_t : 4; + } IMC_STATUS_b; + }; + + union + { + __IM uint32_t IMC_ERR_FULL; /*!< (@ 0x000000A4) Input Port Memory Full and Truncation Indicator + * Register */ + + struct + { + __IM uint32_t IPC_ERR_FULL : 4; /*!< [3..0] Memory was full at start of a frame reception. */ + uint32_t : 12; + __IM uint32_t IPC_ERR_TRUNC : 4; /*!< [19..16] Memory became full while a frame was received and was + * partly written into memory. */ + uint32_t : 12; + } IMC_ERR_FULL_b; + }; + + union + { + __IM uint32_t IMC_ERR_IFACE; /*!< (@ 0x000000A8) Input Port Memory Error Indicator Register */ + + struct + { + __IM uint32_t IPC_ERR_IFACE : 4; /*!< [3..0] Error indication on memory input (receive from MAC) that + * a frame has been truncated and discarded. */ + uint32_t : 12; + __IM uint32_t WBUF_OVF : 4; /*!< [19..16] Error indicating an overflow in the input write buffer + * to the memory controller (a small decoupling FIFO at every + * MAC RX). */ + uint32_t : 12; + } IMC_ERR_IFACE_b; + }; + + union + { + __IM uint32_t IMC_ERR_QOFLOW; /*!< (@ 0x000000AC) Output Port Queue Overflow Indicator Register */ + + struct + { + __IM uint32_t OP_ERR : 4; /*!< [3..0] A frame cannot be stored in an output queue of the port + * as the queue FIFO overflowed (write occurred into full + * fifo). The frame is ignored but stays stored in memory. + * This should not occur during normal operation. This is + * a fatal error as the memory allocated by that frame is + * not freed, and resulting in memory leakage. */ + uint32_t : 28; + } IMC_ERR_QOFLOW_b; + }; + + union + { + __IOM uint32_t IMC_CONFIG; /*!< (@ 0x000000B0) Input Memory Controller Configuration Register */ + + struct + { + __IOM uint32_t WFQ_EN : 1; /*!< [0..0] Enable weighted fair queuing (when this bit is 1) or + * strict priority (when this bit is 0, default) output queue + * scheduling. */ + __IOM uint32_t RSV_ENA : 1; /*!< [1..1] Enable Memory Reservations to Operate */ + __IOM uint32_t SPEED_HIPRI_THR : 3; /*!< [4..2] High-Priority Speed Threshold */ + __IOM uint32_t CTFL_EMPTY_MD : 1; /*!< [5..5] When this bit is set to 0, a frame received in Cut-Through + * mode that cannot allocate an entry in the CTFL is forwarded + * as store and forward. */ + uint32_t : 26; + } IMC_CONFIG_b; + }; + + union + { + __IM uint32_t IMC_ERR_ALLOC; /*!< (@ 0x000000B4) Input Port Error Indicator Register */ + + struct + { + __IM uint32_t DISC_FULL : 4; /*!< [3..0] Per port discard indication due to memory pool going + * empty. Per port indication that one of the queues was full + * and a frame was discarded. */ + uint32_t : 12; + __IM uint32_t DISC_LATE : 4; /*!< [19..16] Per port discard indication due to lateness in the + * priority resolution. The priority resolution can be delayed + * by the pattern matchers. If it arrives too late (after + * approximately 100 bytes into the frame), the frame is discarded. */ + uint32_t : 12; + } IMC_ERR_ALLOC_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t GPARSER0; /*!< (@ 0x000000C0) [n + 1]th Parser of 1st Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask will be compared with the data in the frame. + * All bits having a 0 will be 0 for the compare, however + * this requires the compare value to have those bits also + * set to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes where to find the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type/length field of the frame, that + * is, 0 = first byte of type/length field) or the payload + * following an IP header (see IPDATA). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicate that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field found within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represent the byte at + * the given offset and MASK_VAL2[7:0] represent the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields. For example, setting a compare + * value of 0x0800 and offset 0 matches IP frames. No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value. + * When set, the parser reports a match if the byte at given + * offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER0_b; + }; + + union + { + __IOM uint32_t GPARSER1; /*!< (@ 0x000000C4) [n + 1]th Parser of 1st Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask will be compared with the data in the frame. + * All bits having a 0 will be 0 for the compare, however + * this requires the compare value to have those bits also + * set to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes where to find the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type/length field of the frame, that + * is, 0 = first byte of type/length field) or the payload + * following an IP header (see IPDATA). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicate that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field found within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represent the byte at + * the given offset and MASK_VAL2[7:0] represent the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields. For example, setting a compare + * value of 0x0800 and offset 0 matches IP frames. No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value. + * When set, the parser reports a match if the byte at given + * offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER1_b; + }; + + union + { + __IOM uint32_t GPARSER2; /*!< (@ 0x000000C8) [n + 1]th Parser of 1st Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask will be compared with the data in the frame. + * All bits having a 0 will be 0 for the compare, however + * this requires the compare value to have those bits also + * set to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes where to find the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type/length field of the frame, that + * is, 0 = first byte of type/length field) or the payload + * following an IP header (see IPDATA). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicate that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field found within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represent the byte at + * the given offset and MASK_VAL2[7:0] represent the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields. For example, setting a compare + * value of 0x0800 and offset 0 matches IP frames. No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value. + * When set, the parser reports a match if the byte at given + * offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER2_b; + }; + + union + { + __IOM uint32_t GPARSER3; /*!< (@ 0x000000CC) [n + 1]th Parser of 1st Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask will be compared with the data in the frame. + * All bits having a 0 will be 0 for the compare, however + * this requires the compare value to have those bits also + * set to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes where to find the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type/length field of the frame, that + * is, 0 = first byte of type/length field) or the payload + * following an IP header (see IPDATA). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicate that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field found within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represent the byte at + * the given offset and MASK_VAL2[7:0] represent the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields. For example, setting a compare + * value of 0x0800 and offset 0 matches IP frames. No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use the MASK_VAL2[7:0] bits as a 2nd compare value. + * When set, the parser reports a match if the byte at given + * offset matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER3_b; + }; + + union + { + __IOM uint32_t GARITH0; /*!< (@ 0x000000D0) Snoop Configuration for Arithmetic [n + 1]th + * Stage of 1st Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH0_b; + }; + + union + { + __IOM uint32_t GARITH1; /*!< (@ 0x000000D4) Snoop Configuration for Arithmetic [n + 1]th + * Stage of 1st Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH1_b; + }; + + union + { + __IOM uint32_t GARITH2; /*!< (@ 0x000000D8) Snoop Configuration for Arithmetic [n + 1]th + * Stage of 1st Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH2_b; + }; + + union + { + __IOM uint32_t GARITH3; /*!< (@ 0x000000DC) Snoop Configuration for Arithmetic [n + 1]th + * Stage of 1st Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH3_b; + }; + + union + { + __IOM uint32_t GPARSER4; /*!< (@ 0x000000E0) [n - 3]th Parser of 2nd Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask are compared with the data in the frame. All + * bits having a 0 will be 0 for the compare, however this + * requires the compare value to have those bits also set + * to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes to locate the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type or length field of the frame, for + * example 0 = first byte of type/length field) or the payload + * following an IP header (see bit 26). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicates that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field located within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. If the bit is set, but the frame is not + * an IPv4/v6 frame the parser reports a no match and does + * not continue to inspect the frame. When cleared, the offset + * is used normally on all frames. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represents the byte + * at the given offset and MASK_VAL2[7:0] represents the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields, (for example setting a compare + * value of 0x0800 and offset 0 matches IP frames). No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When + * set, the parser reports a match if the byte at given offset + * matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER4_b; + }; + + union + { + __IOM uint32_t GPARSER5; /*!< (@ 0x000000E4) [n - 3]th Parser of 2nd Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask are compared with the data in the frame. All + * bits having a 0 will be 0 for the compare, however this + * requires the compare value to have those bits also set + * to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes to locate the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type or length field of the frame, for + * example 0 = first byte of type/length field) or the payload + * following an IP header (see bit 26). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicates that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field located within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. If the bit is set, but the frame is not + * an IPv4/v6 frame the parser reports a no match and does + * not continue to inspect the frame. When cleared, the offset + * is used normally on all frames. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represents the byte + * at the given offset and MASK_VAL2[7:0] represents the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields, (for example setting a compare + * value of 0x0800 and offset 0 matches IP frames). No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When + * set, the parser reports a match if the byte at given offset + * matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER5_b; + }; + + union + { + __IOM uint32_t GPARSER6; /*!< (@ 0x000000E8) [n - 3]th Parser of 2nd Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask are compared with the data in the frame. All + * bits having a 0 will be 0 for the compare, however this + * requires the compare value to have those bits also set + * to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes to locate the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type or length field of the frame, for + * example 0 = first byte of type/length field) or the payload + * following an IP header (see bit 26). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicates that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field located within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. If the bit is set, but the frame is not + * an IPv4/v6 frame the parser reports a no match and does + * not continue to inspect the frame. When cleared, the offset + * is used normally on all frames. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represents the byte + * at the given offset and MASK_VAL2[7:0] represents the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields, (for example setting a compare + * value of 0x0800 and offset 0 matches IP frames). No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When + * set, the parser reports a match if the byte at given offset + * matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER6_b; + }; + + union + { + __IOM uint32_t GPARSER7; /*!< (@ 0x000000EC) [n - 3]th Parser of 2nd Block */ + + struct + { + __IOM uint32_t MASK_VAL2 : 8; /*!< [7..0] Mask for single byte compares or 2nd compare value (if + * bit 30 = 1) or least significant bits of a 16-bit compare + * value (if bit 28 = 1). When used as a mask (bit 28, 30 + * = 0, 0), the data from the frame is ANDed with this mask, + * then compared to the compare value. All bits having a 1 + * in the mask are compared with the data in the frame. All + * bits having a 0 will be 0 for the compare, however this + * requires the compare value to have those bits also set + * to 0. */ + __IOM uint32_t COMPARE_VAL : 8; /*!< [15..8] The value to compare the frame data with at the given + * offset. */ + __IOM uint32_t OFFSET : 6; /*!< [21..16] An offset in bytes to locate the data for comparison + * within the frame. The offset value starts at 0 to indicate + * the very first byte after offset start. The offset start + * can be either the type or length field of the frame, for + * example 0 = first byte of type/length field) or the payload + * following an IP header (see bit 26). Valid values range + * from 0 to 60. */ + uint32_t : 1; + __IOM uint32_t OFFSET_DA : 1; /*!< [23..23] When set, the offset starts counting from the first + * byte of the MAC destination address. */ + __IOM uint32_t VALID : 1; /*!< [24..24] Indicates that this entry is valid (when this bit is + * 1) and should be used. When this bit is 0, the parser result + * always indicates "no match" and none of the other bits + * are relevant. */ + __IOM uint32_t SKIPVLAN : 1; /*!< [25..25] When set, any optional VLAN tags found in the frame + * are skipped and the parser starts operating at the first + * byte following any VLAN tags. When cleared, the parser + * starts with the first byte following the source MAC address. */ + __IOM uint32_t IPDATA : 1; /*!< [26..26] When set, the offset starts with the first byte following + * an IP header if an IP frame is processed. The following + * fields are skipped: */ + __IOM uint32_t IPPROTOCOL : 1; /*!< [27..27] When set, the compare value is compared with the protocol + * field located within the IP header for both IPv4 and IPv6 + * frames. It implicitly acts as SKIPVLAN = 1 skipping any + * VLAN tags if present. The offset setting has no meaning + * and is ignored. If the bit is set, but the frame is not + * an IPv4/v6 frame the parser reports a no match and does + * not continue to inspect the frame. When cleared, the offset + * is used normally on all frames. */ + __IOM uint32_t CMP16 : 1; /*!< [28..28] When set, MASK_VAL2[7:0] is used as a value to perform + * a 16-bit compare. COMPARE_VAL[7:0] represents the byte + * at the given offset and MASK_VAL2[7:0] represents the byte + * following at offset + 1 which matches the network byte + * order for 16-bit fields, (for example setting a compare + * value of 0x0800 and offset 0 matches IP frames). No mask + * is available in this mode. */ + __IOM uint32_t OFFSET_PLUS2 : 1; /*!< [29..29] Repeats the comparison at offset + 2, if the comparison + * at offset failed. */ + __IOM uint32_t CMP_MASK_OR : 1; /*!< [30..30] Use MASK_VAL2[7:0] as a second compare value. When + * set, the parser reports a match if the byte at given offset + * matches COMPARE_VAL[7:0] or MASK_VAL2[7:0]. */ + uint32_t : 1; + } GPARSER7_b; + }; + + union + { + __IOM uint32_t GARITH4; /*!< (@ 0x000000F0) Snoop Configuration for Arithmetic [n - 3]th + * Stage of 2nd Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH4_b; + }; + + union + { + __IOM uint32_t GARITH5; /*!< (@ 0x000000F4) Snoop Configuration for Arithmetic [n - 3]th + * Stage of 2nd Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH5_b; + }; + + union + { + __IOM uint32_t GARITH6; /*!< (@ 0x000000F8) Snoop Configuration for Arithmetic [n - 3]th + * Stage of 2nd Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH6_b; + }; + + union + { + __IOM uint32_t GARITH7; /*!< (@ 0x000000FC) Snoop Configuration for Arithmetic [n - 3]th + * Stage of 2nd Block */ + + struct + { + __IOM uint32_t NOT_INP : 4; /*!< [3..0] Not Input */ + uint32_t : 4; + __IOM uint32_t SEL_MATCH : 4; /*!< [11..8] Select Match */ + __IOM uint32_t SEL_ARITH0 : 1; /*!< [12..12] Select Arithmetic Stage 0 */ + __IOM uint32_t SEL_ARITH1 : 1; /*!< [13..13] Select Arithmetic Stage 1 */ + __IOM uint32_t SEL_ARITH2 : 1; /*!< [14..14] Select Arithmetic Stage 2 */ + uint32_t : 1; + __IOM uint32_t OP : 1; /*!< [16..16] Operation */ + __IOM uint32_t RESULT_INV : 1; /*!< [17..17] Result Invert */ + uint32_t : 2; + __IOM uint32_t SNP_MD : 2; /*!< [21..20] Snoop Mode */ + uint32_t : 10; + } GARITH7_b; + }; + + union + { + __IOM uint32_t VLAN_PRIORITY[4]; /*!< (@ 0x00000100) VLAN Priority Register [0..3] */ + + struct + { + __IOM uint32_t PRIORITY0 : 3; /*!< [2..0] Priority 0 Setting */ + __IOM uint32_t PRIORITY1 : 3; /*!< [5..3] Priority 1 Setting */ + __IOM uint32_t PRIORITY2 : 3; /*!< [8..6] Priority 2 Setting */ + __IOM uint32_t PRIORITY3 : 3; /*!< [11..9] Priority 3 Setting */ + __IOM uint32_t PRIORITY4 : 3; /*!< [14..12] Priority 4 Setting */ + __IOM uint32_t PRIORITY5 : 3; /*!< [17..15] Priority 5 Setting */ + __IOM uint32_t PRIORITY6 : 3; /*!< [20..18] Priority 6 Setting */ + __IOM uint32_t PRIORITY7 : 3; /*!< [23..21] Priority 7 Setting */ + uint32_t : 8; + } VLAN_PRIORITY_b[4]; + }; + __IM uint32_t RESERVED3[12]; + + union + { + __IOM uint32_t IP_PRIORITY[4]; /*!< (@ 0x00000140) IP Priority Register [0..3] */ + + struct + { + __IOM uint32_t ADDRESS : 8; /*!< [7..0] COS Table Address Specifying */ + __IOM uint32_t IPV6SELECT : 1; /*!< [8..8] IPv6 COS Table Selection */ + __IOM uint32_t PRIORITY : 3; /*!< [11..9] COS Table Priority */ + uint32_t : 19; + __IOM uint32_t READ : 1; /*!< [31..31] COS Table Operation Switching */ + } IP_PRIORITY_b[4]; + }; + __IM uint32_t RESERVED4[12]; + + union + { + __IOM uint32_t PRIORITY_CFG[4]; /*!< (@ 0x00000180) Priority Configuration Register [0..3] */ + + struct + { + __IOM uint32_t VLANEN : 1; /*!< [0..0] VLAN Priority Enable */ + __IOM uint32_t IPEN : 1; /*!< [1..1] IP Priority Enable */ + __IOM uint32_t MACEN : 1; /*!< [2..2] MAC Based Priority Enable */ + __IOM uint32_t TYPE_EN : 1; /*!< [3..3] TYPE Based Priority Enable */ + __IOM uint32_t DEFAULTPRI : 3; /*!< [6..4] Default Priority Enable Setting */ + __IOM uint32_t PCP_REMAP_DIS : 1; /*!< [7..7] Disables PCP remapping when set to 1. */ + __IOM uint32_t PCP_REMAP : 24; /*!< [31..8] PCP Remapping function */ + } PRIORITY_CFG_b[4]; + }; + __IM uint32_t RESERVED5[10]; + + union + { + __IOM uint32_t PRIORITY_TYPE1; /*!< (@ 0x000001B8) Priority Type Register 1 */ + + struct + { + __IOM uint32_t TYPEVAL : 16; /*!< [15..0] Type Priority */ + __IOM uint32_t VALID : 1; /*!< [16..16] If set indicates, this register contains valid data. */ + __IOM uint32_t PRIORITY : 3; /*!< [19..17] The priority value to use if a match occurs. */ + uint32_t : 12; + } PRIORITY_TYPE1_b; + }; + + union + { + __IOM uint32_t PRIORITY_TYPE2; /*!< (@ 0x000001BC) Priority Type Register 2 */ + + struct + { + __IOM uint32_t TYPEVAL : 16; /*!< [15..0] Type Priority */ + __IOM uint32_t VALID : 1; /*!< [16..16] If set indicates, this register contains valid data. */ + __IOM uint32_t PRIORITY : 3; /*!< [19..17] The priority value to use if a match occurs. */ + uint32_t : 12; + } PRIORITY_TYPE2_b; + }; + __IOM R_ETHSW_MGMT_ADDR_Type MGMT_ADDR[4]; /*!< (@ 0x000001C0) MAC Address [0..3] for Bridge Protocol Frame + * Register */ + + union + { + __IOM uint32_t SRCFLT_ENA; /*!< (@ 0x000001E0) MAC Source Address Filtering Enable Register */ + + struct + { + __IOM uint32_t SRCENA : 3; /*!< [2..0] Per-Source Port Enable */ + uint32_t : 13; + __IOM uint32_t DSTENA : 4; /*!< [19..16] Per-Destination Port Enable */ + uint32_t : 12; + } SRCFLT_ENA_b; + }; + + union + { + __IOM uint32_t SRCFLT_CONTROL; /*!< (@ 0x000001E4) MAC Source Address Filtering Control Register */ + + struct + { + __IOM uint32_t MGMT_FWD : 1; /*!< [0..0] Management Forward Enable */ + __IOM uint32_t WATCHDOG_ENA : 1; /*!< [1..1] When set to 1, a watchdog is enabled. */ + uint32_t : 14; + __IOM uint32_t WATCHDOG_TIME : 16; /*!< [31..16] Defines the watchdog expire time in milliseconds. The + * default is 2000 milliseconds. */ + } SRCFLT_CONTROL_b; + }; + + union + { + __IOM uint32_t SRCFLT_MACADDR_LO; /*!< (@ 0x000001E8) Lower MAC Filtering Address Register */ + + struct + { + __IOM uint32_t SRCFLT_MACADDR : 32; /*!< [31..0] MAC address to use in source filtering */ + } SRCFLT_MACADDR_LO_b; + }; + + union + { + __IOM uint32_t SRCFLT_MACADDR_HI; /*!< (@ 0x000001EC) Higher MAC Filtering Address Register */ + + struct + { + __IOM uint32_t SRCFLT_MACADDR : 16; /*!< [15..0] MAC address to use in source filtering */ + __IOM uint32_t MASK : 16; /*!< [31..16] The mask to apply to the last 16 bits of the MAC address */ + } SRCFLT_MACADDR_HI_b; + }; + __IM uint32_t RESERVED6[3]; + + union + { + __IOM uint32_t PHY_FILTER_CFG; /*!< (@ 0x000001FC) Debounce Filter Configuration Register */ + + struct + { + __IOM uint32_t FILTER_DURATION : 9; /*!< [8..0] This is the amount of time to wait after the last phy_link + * (ETHSW_PHYLINKn: n = port) transition from 0 to 1 to acknowledge + * the link-up condition. */ + uint32_t : 7; + __IOM uint32_t FLT_EN : 3; /*!< [18..16] Per-port Enable Mask */ + uint32_t : 13; + } PHY_FILTER_CFG_b; + }; + + union + { + __IOM uint32_t SYSTEM_TAGINFO[4]; /*!< (@ 0x00000200) One VLAN ID Field [0..3] for VLAN Input Manipulation */ + + struct + { + __IOM uint32_t SYSVLANINFO : 16; /*!< [15..0] System VLAN Info (prio/cfi/vid) for Port n */ + uint32_t : 16; + } SYSTEM_TAGINFO_b[4]; + }; + __IM uint32_t RESERVED7[12]; + + union + { + __IOM uint32_t AUTH_PORT[4]; /*!< (@ 0x00000240) Port [0..3] Authentication Control and Configuration */ + + struct + { + __IOM uint32_t AUTH : 1; /*!< [0..0] Authorized */ + __IOM uint32_t CTRL_BOTH : 1; /*!< [1..1] Controlled Both */ + __IOM uint32_t EAPOL_EN : 1; /*!< [2..2] EAPOL Enable */ + __IOM uint32_t GUEST_EN : 1; /*!< [3..3] Guest Enable */ + __IOM uint32_t BPDU_EN : 1; /*!< [4..4] BPDU Enable */ + __IOM uint32_t EAPOL_UC_EN : 1; /*!< [5..5] EAPOL Unicast Enable */ + uint32_t : 5; + __IOM uint32_t ACHG_UNAUTH : 1; /*!< [11..11] Automatic Port Change to Unauthorized */ + __IOM uint32_t EAPOL_PNUM : 4; /*!< [15..12] EAPOL Port Number */ + __IOM uint32_t GUEST_MASK : 4; /*!< [19..16] Destination port mask with all ports that are allowed + * to receive non-EAPOL frames from this port while it is + * unauthorized and guest (GUEST_EN) is enabled. */ + uint32_t : 12; + } AUTH_PORT_b[4]; + }; + __IM uint32_t RESERVED8[12]; + + union + { + __IOM uint32_t VLAN_RES_TABLE[32]; /*!< (@ 0x00000280) 32 VLAN Domain Entries */ + + struct + { + __IOM uint32_t PORTMASK : 4; /*!< [3..0] When this bit is set to 1, it defines a port as a member + * of the VLAN. When bit [28] or bit [29] is set, the tagged + * bit mask is read/written instead of port mask. */ + __IOM uint32_t VLANID : 12; /*!< [15..4] The 12-bit VLAN identifier (VLAN ID) of the entry. */ + uint32_t : 12; + __IOM uint32_t RD_TAGMSK : 1; /*!< [28..28] Read TAG Mask */ + __IOM uint32_t WT_TAGMSK : 1; /*!< [29..29] Write TAG Mask */ + __IOM uint32_t WT_PRTMSK : 1; /*!< [30..30] Write Port Mask */ + uint32_t : 1; + } VLAN_RES_TABLE_b[32]; + }; + + union + { + __IM uint32_t TOTAL_DISC; /*!< (@ 0x00000300) Discarded Frame Total Number Register */ + + struct + { + __IM uint32_t TOTAL_DISC : 32; /*!< [31..0] Total number of incoming frames accepted by MAC RX but + * discarded in the switch */ + } TOTAL_DISC_b; + }; + + union + { + __IM uint32_t TOTAL_BYT_DISC; /*!< (@ 0x00000304) Discarded Frame Total Bytes Register */ + + struct + { + __IM uint32_t TOTAL_BYT_DISC : 32; /*!< [31..0] Sum of bytes of frames counted in TOTAL_DISC */ + } TOTAL_BYT_DISC_b; + }; + + union + { + __IM uint32_t TOTAL_FRM; /*!< (@ 0x00000308) Processed Frame Total Number Register */ + + struct + { + __IM uint32_t TOTAL_FRM : 32; /*!< [31..0] Total number of incoming frames processed by the switch */ + } TOTAL_FRM_b; + }; + + union + { + __IM uint32_t TOTAL_BYT_FRM; /*!< (@ 0x0000030C) Processed Frame Total Bytes Register */ + + struct + { + __IM uint32_t TOTAL_BYT_FRM : 32; /*!< [31..0] Sum of bytes of frames counted in TOTAL_FRM */ + } TOTAL_BYT_FRM_b; + }; + __IM uint32_t RESERVED9[12]; + + union + { + __IOM uint32_t IALK_CONTROL; /*!< (@ 0x00000340) IA Lookup Function Enable Register */ + + struct + { + __IOM uint32_t IA_LKUP_ENA : 4; /*!< [3..0] Per-port Enable to the IA Lookup Table */ + uint32_t : 12; + __IOM uint32_t CT_ENA : 4; /*!< [19..16] Per-port Cut-Through Mode Enable */ + uint32_t : 12; + } IALK_CONTROL_b; + }; + + union + { + __IOM uint32_t IALK_OUI; /*!< (@ 0x00000344) IA Frames MAC Address OUI Register */ + + struct + { + __IOM uint32_t IALK_OUI : 24; /*!< [23..0] IA Frames MAC Address OUI */ + uint32_t : 8; + } IALK_OUI_b; + }; + + union + { + __IOM uint32_t IALK_ID_MIN; /*!< (@ 0x00000348) Minimum Value ID MAC Address Register */ + + struct + { + __IOM uint32_t IALK_ID_MIN : 24; /*!< [23..0] Minimum value for the 24-bit ID in the MAC address */ + uint32_t : 8; + } IALK_ID_MIN_b; + }; + + union + { + __IOM uint32_t IALK_ID_MAX; /*!< (@ 0x0000034C) Maximum Value ID MAC Address Register */ + + struct + { + __IOM uint32_t IALK_ID_MAX : 24; /*!< [23..0] Maximum value for the 24-bit ID in the MAC address */ + uint32_t : 8; + } IALK_ID_MAX_b; + }; + + union + { + __IOM uint32_t IALK_ID_SUB; /*!< (@ 0x00000350) Offset Value ID MAC Address Register */ + + struct + { + __IOM uint32_t IALK_ID_SUB : 24; /*!< [23..0] Offset value to subtract from the 24-bit ID in the MAC + * address */ + uint32_t : 8; + } IALK_ID_SUB_b; + }; + + union + { + __IOM uint32_t IALK_ID_CONFIG; /*!< (@ 0x00000354) Configures Lookup Response Unknown IDs Register */ + + struct + { + __IOM uint32_t INVLD_ID_FLOOD : 1; /*!< [0..0] Setting this bit to 1 causes the IA table to return a + * found response for frames whose ID lies outside the ID + * range defined by [IA_LK_MAX:IA_LK_MIN] using INVLD_ID_FLOOD_MASK[3:0] + * bits. */ + __IOM uint32_t INVLD_ID_LRN_ENA : 1; /*!< [1..1] Setting this bit to 1 allows automatic learning into + * the L2 FDB for frames with unknown IDs. When 0, learning + * is inhibited. This bit is only valid when INVLD_ID_FLOOD + * bit is set to 1. */ + uint32_t : 2; + __IOM uint32_t INVLD_ID_PRIO : 3; /*!< [6..4] Priority to use for found responses of an invalid ID. + * This bit is only valid when INVLD_ID_FLOOD bit is set to + * 1. */ + __IOM uint32_t INVLD_ID_PRIO_VLD : 1; /*!< [7..7] Indicates if the priority in INVLD_ID_PRIO is valid. + * This bit is valid only when INVLD_ID_FLOOD bit is set to + * 1. */ + uint32_t : 8; + __IOM uint32_t INVLD_ID_FLOOD_MASK : 4; /*!< [19..16] Forwarding mask used for frames whose ID is invalid. + * This bit is only valid when INVLD_ID_FLOOD bit is set to + * 1. Setting this mask to 0 causes the frame to be dropped. */ + uint32_t : 12; + } IALK_ID_CONFIG_b; + }; + + union + { + __IOM uint32_t IALK_VLAN_CONFIG; /*!< (@ 0x00000358) Configure Lookup Response Unknown VLAN Register */ + + struct + { + __IOM uint32_t UNKWN_VLAN_FLOOD : 1; /*!< [0..0] When this bit is set to 1, a frame matching the OUI and + * with a valid ID but having a VLAN ID not matching any of + * the enabled values in IALK_VLANIDn causes the IA table + * to return a found response using the forwarding mask in + * UNKWN_VLAN_FLOOD_MASK[3:0]. */ + __IOM uint32_t UNKWN_VLAN_LRN_ENA : 1; /*!< [1..1] Setting this bit to 1 allows automatic learning into + * the L2 FDB for frames with unknown VLANs. When 0, learning + * is inhibited. This bit is only valid when UNKWN_VLAN_FLOOD + * bit is set to 1. */ + uint32_t : 2; + __IOM uint32_t UNKWN_VLAN_PRIO : 3; /*!< [6..4] Priority to use for found responses for an unknown VLAN. + * This bit is only valid when UNKWN_VLAN_FLOOD bit is set + * to 1. */ + __IOM uint32_t UNKWN_VLAN_PRIO_VLD : 1; /*!< [7..7] Indicates if the priority in UNKWN_VLAN_PRIO[2:0] is + * valid. This bit is only valid when UNKWN_VLAN_FLOOD bit + * is set to 1. */ + __IOM uint32_t VLANS_ENABLED : 3; /*!< [10..8] Configures the logical geometry of the IA table by specifying + * the number of distinct VLAN IDs enabled. When set to 0, + * no VLANs are supported and the VLAN ID for the frames is + * ignored. */ + uint32_t : 5; + __IOM uint32_t UNKWN_VLAN_FLOOD_MASK : 4; /*!< [19..16] Forwarding mask used for frames with an unknown VLAN + * ID. */ + uint32_t : 12; + } IALK_VLAN_CONFIG_b; + }; + + union + { + __IOM uint32_t IALK_TBL_ADDR; /*!< (@ 0x0000035C) IA Lookup Database Address Register */ + + struct + { + __IOM uint32_t ADDR : 13; /*!< [12..0] Defines the address to write to or read from the IA + * Lookup table */ + uint32_t : 15; + __IOM uint32_t AINC : 4; /*!< [31..28] Auto-Increment Control */ + } IALK_TBL_ADDR_b; + }; + + union + { + __IOM uint32_t IALK_TBL_DATA; /*!< (@ 0x00000360) IA Lookup Database Data Register */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Indicates whether the entry indicated by ADDR is valid + * or not. */ + __IOM uint32_t FWD_MASK : 4; /*!< [4..1] Forwarding mask used for lookups that hit the entry and + * when VALID is set to 1. */ + uint32_t : 27; + } IALK_TBL_DATA_b; + }; + __IM uint32_t RESERVED10[7]; + + union + { + __IOM uint32_t IALK_VLANID[4]; /*!< (@ 0x00000380) IA Lookup VLANIDn Register */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] Configure the VLAN ID to be used for VLAN n (n: IALK_VLAN_CONFIG.VLANS + * ENABLED). This bit is only valid when VLANID_ENA bit is + * set to 1. A value of 0 matches any VLAN ID. */ + __IOM uint32_t VLANID_ENA : 1; /*!< [12..12] Enables this VLAN ID. When set to 1, the VLAN ID of + * the frame is compared against VLANID[11:0]. */ + __IOM uint32_t VLANID_LRN_ENA : 1; /*!< [13..13] Configures whether automatic learning in the L2 FDB + * is allowed for frames matching VLAN ID. This also includes + * frames that match the VLAN ID and that the entry in the + * IA table is invalid. */ + uint32_t : 2; + __IOM uint32_t VLANID_FLOOD_MASK : 4; /*!< [19..16] Flooding mask to be used for frames matching this VLAN + * ID but with an invalid entry in the IA table. */ + uint32_t : 8; + __IOM uint32_t VLANID_PRIO : 3; /*!< [30..28] Priority to use for found responses. */ + __IOM uint32_t VLANID_PRIO_VLD : 1; /*!< [31..31] Indicates if the priority in VLANID_PRIO[2:0] is valid. */ + } IALK_VLANID_b[4]; + }; + __IM uint32_t RESERVED11[12]; + + union + { + __IM uint32_t IMC_QLEVEL_P[4]; /*!< (@ 0x000003C0) Port [0..3] Queued Frame Count Register */ + + struct + { + __IM uint32_t QUEUE0 : 4; /*!< [3..0] A 4-bit value per queue indicating the number of frames + * stored in queue 0 */ + __IM uint32_t QUEUE1 : 4; /*!< [7..4] A 4-bit value per queue indicating the number of frames + * stored in queue 1 */ + __IM uint32_t QUEUE2 : 4; /*!< [11..8] A 4-bit value per queue indicating the number of frames + * stored in queue 2 */ + __IM uint32_t QUEUE3 : 4; /*!< [15..12] A 4-bit value per queue indicating the number of frames + * stored in queue 3 */ + __IM uint32_t QUEUE4 : 4; /*!< [19..16] A 4-bit value per queue indicating the number of frames + * stored in queue 4 */ + __IM uint32_t QUEUE5 : 4; /*!< [23..20] A 4-bit value per queue indicating the number of frames + * stored in queue 5 */ + __IM uint32_t QUEUE6 : 4; /*!< [27..24] A 4-bit value per queue indicating the number of frames + * stored in queue 6 */ + __IM uint32_t QUEUE7 : 4; /*!< [31..28] A 4-bit value per queue indicating the number of frames + * stored in queue 7 */ + } IMC_QLEVEL_P_b[4]; + }; + __IM uint32_t RESERVED12[12]; + + union + { + __IOM uint32_t LK_CTRL; /*!< (@ 0x00000400) Learning/Lookup Function Global Configuration + * Register */ + + struct + { + __IOM uint32_t LKUP_EN : 1; /*!< [0..0] Lookup Controller Enable */ + __IOM uint32_t LEARN_EN : 1; /*!< [1..1] Learning Enable */ + __IOM uint32_t AGING_EN : 1; /*!< [2..2] Aging Enable */ + __IOM uint32_t ALW_MGRT : 1; /*!< [3..3] Allow Migration */ + __IOM uint32_t DISC_UNK_DEST : 1; /*!< [4..4] Discard Unknown Destination */ + uint32_t : 1; + __IOM uint32_t CLRTBL : 1; /*!< [6..6] Clear Table */ + __IOM uint32_t IND_VLAN : 1; /*!< [7..7] Enable Independent VLAN Learning */ + uint32_t : 8; + __IOM uint32_t DISC_UNK_SRC : 4; /*!< [19..16] Discard Unknown Source */ + uint32_t : 12; + } LK_CTRL_b; + }; + + union + { + __IOM uint32_t LK_STATUS; /*!< (@ 0x00000404) Status Bits and Table Overflow Counter Register */ + + struct + { + __IM uint32_t AGEADDR : 16; /*!< [15..0] Address the aging process will inspect when the aging + * timer expires next time. */ + __IOM uint32_t OVRF : 14; /*!< [29..16] Counts number of table overflows that occurred (a new + * address was learned but the table had no storage and an + * older entry was deleted). The counter is cleared by writing + * into the register and having bit 16 set to 1. */ + uint32_t : 1; + __IOM uint32_t LRNEVNT : 1; /*!< [31..31] Learn Event */ + } LK_STATUS_b; + }; + + union + { + __IOM uint32_t LK_ADDR_CTRL; /*!< (@ 0x00000408) Address Table Transaction Control and Read/Write + * Address */ + + struct + { + __IOM uint32_t ADDR_MSK : 12; /*!< [11..0] Memory address for read and write transactions. This + * is the address of a 69-bit entry. For the DEL_PORT bit, + * a port mask can be provided in these bits instead of the + * address. Bit 0 represents port 0, bit 1 port 1, and so + * on. */ + uint32_t : 10; + __IOM uint32_t CLR_DYNAMIC : 1; /*!< [22..22] When set to 1, scans the complete table for valid dynamic + * entries and deletes them (writes entry with all 0s). This + * bit is cleared when the function has completed. */ + __IOM uint32_t CLR_STATIC : 1; /*!< [23..23] When set to 1, scans the complete table for valid static + * entries and deletes them (writes entry with all 0s). This + * bit is cleared when the function has completed. */ + __IOM uint32_t GETLASTNEW : 1; /*!< [24..24] When set to 1, retrieves the last source address that + * was not found in the table and places it into LK_DATA_LO/HI/HI2. + * The valid bit of the entry (bit LK_DATA_HI[16]) indicates + * if the address is new (when valid bit is 1) or not (when + * valid bit is 0) since the command was last issued. */ + __IOM uint32_t WRITE : 1; /*!< [25..25] When set to 1, perform a single write transaction. */ + __IOM uint32_t READ : 1; /*!< [26..26] When set to 1, perform a single read transaction. */ + __IOM uint32_t WAIT_COMP : 1; /*!< [27..27] When set to 1, instructs to stall the processor bus + * until the transaction is completed. This allows performing + * of consecutive writes into this register with varying commands + * without the need for polling the BUSY bit. */ + __IM uint32_t LOOKUP : 1; /*!< [28..28] When set to 1, perform a lookup of the MAC address + * given in LK_DATA_LO/HI/HI2. */ + __IOM uint32_t CLEAR : 1; /*!< [29..29] When set to 1, writes all 0s to the entry selected + * by the given address set in ADDR_MSK[11:0]. If this bit + * is set together with the LOOKUP bit, first a lookup is + * performed and if the lookup succeeds, the entry is then + * deleted. The registers LK_DATA_LO/HI/HI2 are also cleared. + * The memory address in this register is set from the lookup + * result. If the lookup failed, the clear command is ignored + * and memory address is arbitrary. */ + __IOM uint32_t DEL_PORT : 1; /*!< [30..30] When set to 1, scans the complete table for valid dynamic + * entries that contain the given ports in their destination + * port mask and deletes the ports or the complete entry. + * The port mask is provided in the ADDR_MSK[3:0] when writing + * this register (1 bit per port, bit 0 = port 0, bit 1 = + * port 1, and so on). */ + __IM uint32_t BUSY : 1; /*!< [31..31] Transaction Busy Indication */ + } LK_ADDR_CTRL_b; + }; + + union + { + __IOM uint32_t LK_DATA_LO; /*!< (@ 0x0000040C) Lower 32-Bit Data of Lookup Memory Entry */ + + struct + { + __IOM uint32_t MEMDATA : 32; /*!< [31..0] Memory Data [31:0] */ + } LK_DATA_LO_b; + }; + + union + { + __IOM uint32_t LK_DATA_HI; /*!< (@ 0x00000410) Higher 25-Bit Data of Lookup Memory Entry */ + + struct + { + __IOM uint32_t MEMDATA : 25; /*!< [24..0] Memory Data [56:32] */ + uint32_t : 7; + } LK_DATA_HI_b; + }; + + union + { + __IOM uint32_t LK_DATA_HI2; /*!< (@ 0x00000414) Higher2 12-Bit Data of Lookup Memory Entry */ + + struct + { + uint32_t : 8; + __IOM uint32_t MEMDATA : 12; /*!< [19..8] Memory Data [68:57] */ + uint32_t : 12; + } LK_DATA_HI2_b; + }; + + union + { + __IOM uint32_t LK_LEARNCOUNT; /*!< (@ 0x00000418) Learned Address Count Register */ + + struct + { + __IOM uint32_t LEARNCOUNT : 13; /*!< [12..0] Number of Learned Addresses */ + uint32_t : 17; + __IOM uint32_t WRITE_MD : 2; /*!< [31..30] These bits define how the LEARNCOUNT value is modified + * when writing into the register: */ + } LK_LEARNCOUNT_b; + }; + + union + { + __IOM uint32_t LK_AGETIME; /*!< (@ 0x0000041C) Period of the Aging Timer */ + + struct + { + __IOM uint32_t AGETIME : 24; /*!< [23..0] 24-bit Timer Value */ + uint32_t : 8; + } LK_AGETIME_b; + }; + __IM uint32_t RESERVED13[24]; + + union + { + __IOM uint32_t MGMT_TAG_CONFIG; /*!< (@ 0x00000480) Management Tag Configuration Register */ + + struct + { + __IOM uint32_t ENABLE : 1; /*!< [0..0] Enable Management Tag Insertion Module */ + __IOM uint32_t AL_FRAMES : 1; /*!< [1..1] Enable Tag Insertion for All Frames */ + uint32_t : 2; + __IOM uint32_t TYPE1_EN : 1; /*!< [4..4] When set, frames with a Type field that match the value + * in PRIORITY_TYPE1.TYPEVAL[15:0] have management tag inserted. + * This is in addition to BPDU frames which always have tag + * inserted. */ + __IOM uint32_t TYPE2_EN : 1; /*!< [5..5] When set, frames with a Type field that match the value + * in PRIORITY_TYPE2.TYPEVAL[15:0] have management tag inserted. + * This is in addition to BPDU frames which always have tag + * inserted. */ + uint32_t : 10; + __IOM uint32_t TAGFIELD : 16; /*!< [31..16] The value of the tag that is found in the first Type/Length + * field of the frame to identify that the control information + * is present within a frame. For example, [31:24] = first + * octet, [23:16] = 2nd octet. */ + } MGMT_TAG_CONFIG_b; + }; + __IM uint32_t RESERVED14[32]; + + union + { + __IOM uint32_t TSM_CONFIG; /*!< (@ 0x00000504) Timestamping Control Module Configuration Register */ + + struct + { + __IOM uint32_t IRQ_EN : 1; /*!< [0..0] Final Interrupt enable */ + __IOM uint32_t IRQ_TEST : 1; /*!< [1..1] Software controlled interrupt for testing purposes */ + __IOM uint32_t IRQ_TSFIFO_OVR : 1; /*!< [2..2] Trigger interrupt enable for Transmit Timestamp Capture + * Overflow event */ + uint32_t : 1; + __IOM uint32_t IRQ_EVT_OFFSET : 2; /*!< [5..4] Per-timer Trigger interrupt enable for the timer offset + * event */ + uint32_t : 2; + __IOM uint32_t IRQ_EVT_PERIOD : 2; /*!< [9..8] Per-timer Trigger interrupt enable for the timer periodical + * event */ + uint32_t : 2; + __IOM uint32_t IRQ_ATIME_OVER : 2; /*!< [13..12] Per-timer Trigger interrupt enable for the timer wrap + * (reached its maximum) */ + uint32_t : 2; + __IOM uint32_t IRQ_TX_EN : 4; /*!< [19..16] Per Port Transmit Timestamp Capture Interrupt Enable */ + uint32_t : 12; + } TSM_CONFIG_b; + }; + + union + { + __IOM uint32_t TSM_IRQ_STAT_ACK; /*!< (@ 0x00000508) Interrupt Status/Acknowledge Register */ + + struct + { + __IM uint32_t IRQ_STAT : 1; /*!< [0..0] Interrupt Pending Status */ + __IOM uint32_t IRQ_TEST : 1; /*!< [1..1] Test Interrupt Pending Status */ + __IM uint32_t IRQ_TSFIFO_OVR : 1; /*!< [2..2] Transmit Timestamp Capture Overflow Interrupt Pending + * Status */ + uint32_t : 1; + __IOM uint32_t IRQ_EVT_OFFSET : 2; /*!< [5..4] Per-timer Offset Interrupt Pending Status */ + uint32_t : 2; + __IOM uint32_t IRQ_EVT_PERIOD : 2; /*!< [9..8] Per-timer Periodical Interrupt Pending Status */ + uint32_t : 2; + __IOM uint32_t IRQ_ATIME_OVER : 2; /*!< [13..12] Per-timer Overflow Interrupt Pending Status */ + uint32_t : 2; + __IOM uint32_t IRQ_TX : 4; /*!< [19..16] Per Port Transmit Timestamp Capture Interrupt */ + uint32_t : 12; + } TSM_IRQ_STAT_ACK_b; + }; + + union + { + __IOM uint32_t PTP_DOMAIN; /*!< (@ 0x0000050C) Domain Number of PTP Frame */ + + struct + { + __IOM uint32_t DOMAIN0 : 8; /*!< [7..0] DomainNumber to Match Against for Timer 0 */ + __IOM uint32_t DOMAIN1 : 8; /*!< [15..8] DomainNumber to Match Against for Timer 1 */ + uint32_t : 16; + } PTP_DOMAIN_b; + }; + __IM uint32_t RESERVED15[12]; + + union + { + __IOM uint32_t PEERDELAY_P0_T0; /*!< (@ 0x00000540) Port 0 Peer Delay Value for Timer 0 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 0 */ + uint32_t : 2; + } PEERDELAY_P0_T0_b; + }; + + union + { + __IOM uint32_t PEERDELAY_P0_T1; /*!< (@ 0x00000544) Port 0 Peer Delay Value for Timer 1 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 1 */ + uint32_t : 2; + } PEERDELAY_P0_T1_b; + }; + __IM uint32_t RESERVED16[2]; + + union + { + __IOM uint32_t PEERDELAY_P1_T0; /*!< (@ 0x00000550) Port 1 Peer Delay Value for Timer 0 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 0 */ + uint32_t : 2; + } PEERDELAY_P1_T0_b; + }; + + union + { + __IOM uint32_t PEERDELAY_P1_T1; /*!< (@ 0x00000554) Port 1 Peer Delay Value for Timer 1 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 1 */ + uint32_t : 2; + } PEERDELAY_P1_T1_b; + }; + __IM uint32_t RESERVED17[2]; + + union + { + __IOM uint32_t PEERDELAY_P2_T0; /*!< (@ 0x00000560) Port 2 Peer Delay Value for Timer 0 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 0 */ + uint32_t : 2; + } PEERDELAY_P2_T0_b; + }; + + union + { + __IOM uint32_t PEERDELAY_P2_T1; /*!< (@ 0x00000564) Port 2 Peer Delay Value for Timer 1 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 1 */ + uint32_t : 2; + } PEERDELAY_P2_T1_b; + }; + __IM uint32_t RESERVED18[2]; + + union + { + __IOM uint32_t PEERDELAY_P3_T0; /*!< (@ 0x00000570) Port 3 Peer Delay Value for Timer 0 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 0 */ + uint32_t : 2; + } PEERDELAY_P3_T0_b; + }; + + union + { + __IOM uint32_t PEERDELAY_P3_T1; /*!< (@ 0x00000574) Port 3 Peer Delay Value for Timer 1 (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t PEERDELAY : 30; /*!< [29..0] Peer Delay Value Determined at the Port n for Timer + * 1 */ + uint32_t : 2; + } PEERDELAY_P3_T1_b; + }; + __IM uint32_t RESERVED19[18]; + + union + { + __IOM uint32_t TS_FIFO_STATUS; /*!< (@ 0x000005C0) Transmit Timestamp FIFO Status Register */ + + struct + { + __IM uint32_t FF_VALID : 4; /*!< [3..0] Per-port indication that a valid timestamp is available + * in the corresponding FIFO of the port */ + uint32_t : 12; + __IOM uint32_t FF_OVR : 4; /*!< [19..16] Per-port indication that a timestamp cannot be written + * to the FIFO because of the FIFO being full. */ + uint32_t : 12; + } TS_FIFO_STATUS_b; + }; + + union + { + __IOM uint32_t TS_FIFO_READ_CTRL; /*!< (@ 0x000005C4) Transmit Timestamp FIFO Read Control Register */ + + struct + { + __IOM uint32_t PORT_NUM : 2; /*!< [1..0] Port Number to Read from */ + uint32_t : 2; + __IM uint32_t TS_VALID : 1; /*!< [4..4] When reading from this register, this bit is 1 if the + * FIFO indicated by PORT_NUM contained valid data. */ + uint32_t : 1; + __IM uint32_t TS_SEL : 1; /*!< [6..6] When TS_VALID is 1, TS_SEL indicates the timer used for + * the read timestamp. */ + uint32_t : 1; + __IM uint32_t TS_ID : 7; /*!< [14..8] When TS_VALID is 1, TS_ID indicates the ID specified + * by the application through the management tag control information, + * if present. */ + uint32_t : 17; + } TS_FIFO_READ_CTRL_b; + }; + + union + { + __IM uint32_t TS_FIFO_READ_TIMESTAMP; /*!< (@ 0x000005C8) 32-bit Timestamp Value Read from FIFO */ + + struct + { + __IM uint32_t TIMESTAMP : 32; /*!< [31..0] 32-bit timestamp value read from the FIFO */ + } TS_FIFO_READ_TIMESTAMP_b; + }; + __IM uint32_t RESERVED20[13]; + + union + { + __IOM uint32_t INT_CONFIG; /*!< (@ 0x00000600) Interrupt Enable Configuration Register */ + + struct + { + __IOM uint32_t IRQ_EN : 1; /*!< [0..0] Interrupt Global Enable */ + __IOM uint32_t MDIO1 : 1; /*!< [1..1] Enable Interrupt on Transaction Complete from MDIO Controller */ + uint32_t : 1; + __IOM uint32_t LK_NEW_SRC : 1; /*!< [3..3] Enable Interrupt for New Source Address */ + __IOM uint32_t IRQ_TEST : 1; /*!< [4..4] When set, an interrupt is triggered immediately. Can + * be used to cause a software controlled interrupt for testing + * purposes. */ + __IOM uint32_t DLR_INT : 1; /*!< [5..5] Enable Interrupt for DLR */ + __IOM uint32_t PRP_INT : 1; /*!< [6..6] Enable Interrupt for PRP */ + __IOM uint32_t HUB_INT : 1; /*!< [7..7] Enable Interrupt for HUB */ + __IOM uint32_t IRQ_LINK : 3; /*!< [10..8] Per Line Port Phy Link Change Interrupt Enable */ + uint32_t : 5; + __IOM uint32_t IRQ_MAC_EEE : 3; /*!< [18..16] Per Line Port MAC interrupt */ + uint32_t : 8; + __IOM uint32_t EFP_INT : 1; /*!< [27..27] Enable Interrupt for Extended Frame Parser */ + __IOM uint32_t SRCFLT_WD_INT : 1; /*!< [28..28] MAC Address Source Filtering Watchdog */ + __IOM uint32_t TSM_INT : 1; /*!< [29..29] Enable Interrupt for TSM (Timer, Timestamping) */ + __IOM uint32_t TDMA_INT : 1; /*!< [30..30] Enable Interrupt for TDMA scheduler */ + __IOM uint32_t PATTERN_INT : 1; /*!< [31..31] Enable Interrupt for RX Pattern Matcher */ + } INT_CONFIG_b; + }; + + union + { + __IOM uint32_t INT_STAT_ACK; /*!< (@ 0x00000604) Interrupt Status/ACK Register */ + + struct + { + __IM uint32_t IRQ_PEND : 1; /*!< [0..0] Interrupt Pending Status */ + __IOM uint32_t MDIO1 : 1; /*!< [1..1] Latched Interrupt Status for MDIO1 */ + uint32_t : 1; + __IOM uint32_t LK_NEW_SRC : 1; /*!< [3..3] Latched Interrupt Status for LK_NEW_SRC */ + __IM uint32_t IRQ_TEST : 1; /*!< [4..4] Interrupt Status for IRQ_TEST */ + __IM uint32_t DLR_INT : 1; /*!< [5..5] Interrupt Pending Status from DLR Module */ + __IM uint32_t PRP_INT : 1; /*!< [6..6] Interrupt Pending Status from PRP Module */ + __IM uint32_t HUB_INT : 1; /*!< [7..7] Interrupt Pending Status from Hub Module */ + __IOM uint32_t IRQ_LINK : 3; /*!< [10..8] Interrupt Pending per Line Port Phy Link Change Interrupt */ + uint32_t : 5; + __IOM uint32_t IRQ_MAC_EEE : 3; /*!< [18..16] Interrupt Pending Status per Line Port MAC Interrupt */ + uint32_t : 8; + __IOM uint32_t EFP_INT : 1; /*!< [27..27] Interrupt from Extended Frame Parser */ + __IOM uint32_t SRCFLT_WD_INT : 1; /*!< [28..28] Interrupt Pending Status for MAC Source Filtering Watchdog */ + __IM uint32_t TSM_INT : 1; /*!< [29..29] Interrupt Pending Interrupt Indication from TSM (Timestamping) + * module */ + __IM uint32_t TDMA_INT : 1; /*!< [30..30] Interrupt Pending Status from TDMA Scheduler */ + __IM uint32_t PATTERN_INT : 1; /*!< [31..31] Interrupt Pending Status from RX Pattern Matcher Module */ + } INT_STAT_ACK_b; + }; + __IM uint32_t RESERVED21[30]; + + union + { + __IOM uint32_t ATIME_CTRL0; /*!< (@ 0x00000680) Timer 0 Control Register (n = 0, 1) */ + + struct + { + __IOM uint32_t ENABLE : 1; /*!< [0..0] ENABLE */ + __IOM uint32_t ONE_SHOT : 1; /*!< [1..1] Avoid timer wrap around. If set, the timer stops at maximum. + * An overflow interrupt (TSM_CONFIG.IRQ_ATIME_OVER) occurs + * (if enabled) when the maximum is reached. */ + __IOM uint32_t EVT_OFFSET_ENA : 1; /*!< [2..2] Enable Offset Event */ + uint32_t : 1; + __IOM uint32_t EVT_PERIOD_ENA : 1; /*!< [4..4] Enable Periodical Event */ + __IOM uint32_t EVT_PERIOD_RST : 1; /*!< [5..5] Reset Timer on Periodical Event */ + uint32_t : 3; + __IOM uint32_t RESTART : 1; /*!< [9..9] Resets the Timer to Zero (Command Bit) */ + uint32_t : 1; + __IOM uint32_t CAPTURE : 1; /*!< [11..11] Capture Time Value (Command Bit) */ + __IOM uint32_t CAPTURE_ALL : 1; /*!< [12..12] Capture All Timers Value (Command Bit) */ + uint32_t : 19; + } ATIME_CTRL0_b; + }; + + union + { + __IOM uint32_t ATIME0; /*!< (@ 0x00000684) Timer 0 Count Register (n = 0, 1) */ + + struct + { + __IOM uint32_t TIMER_VAL : 32; /*!< [31..0] Timer Value */ + } ATIME0_b; + }; + + union + { + __IOM uint32_t ATIME_OFFSET0; /*!< (@ 0x00000688) Timer 0 Offset Register (n = 0, 1) */ + + struct + { + __IOM uint32_t OFFSET : 32; /*!< [31..0] Value used for performing offset corrections without + * changing the drift correction */ + } ATIME_OFFSET0_b; + }; + + union + { + __IOM uint32_t ATIME_EVT_PERIOD0; /*!< (@ 0x0000068C) Timer 0 Periodic Event Register (n = 0, 1) */ + + struct + { + __IOM uint32_t PERIOD : 32; /*!< [31..0] Value for generating periodic events */ + } ATIME_EVT_PERIOD0_b; + }; + + union + { + __IOM uint32_t ATIME_CORR0; /*!< (@ 0x00000690) Timer 0 Correction Period Register (n = 0, 1) */ + + struct + { + __IOM uint32_t CORR_PERIOD : 31; /*!< [30..0] Correction Period */ + uint32_t : 1; + } ATIME_CORR0_b; + }; + + union + { + __IOM uint32_t ATIME_INC0; /*!< (@ 0x00000694) Timer 0 Increment Register (n = 0, 1) */ + + struct + { + __IOM uint32_t CLK_PERIOD : 7; /*!< [6..0] Clock Period of the Timestamping Clock (125 MHz) in nanoseconds */ + uint32_t : 1; + __IOM uint32_t CORR_INC : 7; /*!< [14..8] Correction Increment Value */ + uint32_t : 1; + __IOM uint32_t OFFS_CORR_INC : 7; /*!< [22..16] Offset Correction Increment Value */ + uint32_t : 9; + } ATIME_INC0_b; + }; + + union + { + __IOM uint32_t ATIME_SEC0; /*!< (@ 0x00000698) Timer 0 Seconds Time Register (n = 0, 1) */ + + struct + { + __IOM uint32_t SEC_TIME : 32; /*!< [31..0] Seconds Time Value */ + } ATIME_SEC0_b; + }; + + union + { + __IOM uint32_t ATIME_OFFS_CORR0; /*!< (@ 0x0000069C) Timer 0 Offset Correction Counter Register (n + * = 0, 1) */ + + struct + { + __IOM uint32_t OFFS_CORR_CNT : 32; /*!< [31..0] Offset Correction Counter */ + } ATIME_OFFS_CORR0_b; + }; + + union + { + __IOM uint32_t ATIME_CTRL1; /*!< (@ 0x000006A0) Timer 1 Control Register (n = 0, 1) */ + + struct + { + __IOM uint32_t ENABLE : 1; /*!< [0..0] ENABLE */ + __IOM uint32_t ONE_SHOT : 1; /*!< [1..1] Avoid timer wrap around. If set, the timer stops at maximum. + * An overflow interrupt (TSM_CONFIG.IRQ_ATIME_OVER) occurs + * (if enabled) when the maximum is reached. */ + __IOM uint32_t EVT_OFFSET_ENA : 1; /*!< [2..2] Enable Offset Event */ + uint32_t : 1; + __IOM uint32_t EVT_PERIOD_ENA : 1; /*!< [4..4] Enable Periodical Event */ + __IOM uint32_t EVT_PERIOD_RST : 1; /*!< [5..5] Reset Timer on Periodical Event */ + uint32_t : 3; + __IOM uint32_t RESTART : 1; /*!< [9..9] Resets the Timer to Zero (Command Bit) */ + uint32_t : 1; + __IOM uint32_t CAPTURE : 1; /*!< [11..11] Capture Time Value (Command Bit) */ + __IOM uint32_t CAPTURE_ALL : 1; /*!< [12..12] Capture All Timers Value (Command Bit) */ + uint32_t : 19; + } ATIME_CTRL1_b; + }; + + union + { + __IOM uint32_t ATIME1; /*!< (@ 0x000006A4) Timer 1 Count Register (n = 0, 1) */ + + struct + { + __IOM uint32_t TIMER_VAL : 32; /*!< [31..0] Timer Value */ + } ATIME1_b; + }; + + union + { + __IOM uint32_t ATIME_OFFSET1; /*!< (@ 0x000006A8) Timer 1 Offset Register (n = 0, 1) */ + + struct + { + __IOM uint32_t OFFSET : 32; /*!< [31..0] Value used for performing offset corrections without + * changing the drift correction */ + } ATIME_OFFSET1_b; + }; + + union + { + __IOM uint32_t ATIME_EVT_PERIOD1; /*!< (@ 0x000006AC) Timer 1 Periodic Event Register (n = 0, 1) */ + + struct + { + __IOM uint32_t PERIOD : 32; /*!< [31..0] Value for generating periodic events */ + } ATIME_EVT_PERIOD1_b; + }; + + union + { + __IOM uint32_t ATIME_CORR1; /*!< (@ 0x000006B0) Timer 1 Correction Period Register (n = 0, 1) */ + + struct + { + __IOM uint32_t CORR_PERIOD : 31; /*!< [30..0] Correction Period */ + uint32_t : 1; + } ATIME_CORR1_b; + }; + + union + { + __IOM uint32_t ATIME_INC1; /*!< (@ 0x000006B4) Timer 1 Increment Register (n = 0, 1) */ + + struct + { + __IOM uint32_t CLK_PERIOD : 7; /*!< [6..0] Clock Period of the Timestamping Clock (125 MHz) in nanoseconds */ + uint32_t : 1; + __IOM uint32_t CORR_INC : 7; /*!< [14..8] Correction Increment Value */ + uint32_t : 1; + __IOM uint32_t OFFS_CORR_INC : 7; /*!< [22..16] Offset Correction Increment Value */ + uint32_t : 9; + } ATIME_INC1_b; + }; + + union + { + __IOM uint32_t ATIME_SEC1; /*!< (@ 0x000006B8) Timer 1 Seconds Time Register (n = 0, 1) */ + + struct + { + __IOM uint32_t SEC_TIME : 32; /*!< [31..0] Seconds Time Value */ + } ATIME_SEC1_b; + }; + + union + { + __IOM uint32_t ATIME_OFFS_CORR1; /*!< (@ 0x000006BC) Timer 1 Offset Correction Counter Register (n + * = 0, 1) */ + + struct + { + __IOM uint32_t OFFS_CORR_CNT : 32; /*!< [31..0] Offset Correction Counter */ + } ATIME_OFFS_CORR1_b; + }; + __IM uint32_t RESERVED22[16]; + + union + { + __IOM uint32_t MDIO_CFG_STATUS; /*!< (@ 0x00000700) MDIO Configuration and Status Register */ + + struct + { + __IM uint32_t BUSY : 1; /*!< [0..0] MDIO Busy */ + __IM uint32_t READERR : 1; /*!< [1..1] MDIO Read Error */ + __IOM uint32_t HOLD : 3; /*!< [4..2] MDIO Hold Time Setting */ + __IOM uint32_t DISPREAM : 1; /*!< [5..5] Disable Preamble */ + uint32_t : 1; + __IOM uint32_t CLKDIV : 9; /*!< [15..7] MDIO Clock Divisor */ + uint32_t : 16; + } MDIO_CFG_STATUS_b; + }; + + union + { + __IOM uint32_t MDIO_COMMAND; /*!< (@ 0x00000704) MDIO PHY Command Register */ + + struct + { + __IOM uint32_t REGADDR : 5; /*!< [4..0] Register Address */ + __IOM uint32_t PHYADDR : 5; /*!< [9..5] PHY Address */ + uint32_t : 5; + __IOM uint32_t TRANINIT : 1; /*!< [15..15] If set to 1, a read transaction is initiated. */ + uint32_t : 16; + } MDIO_COMMAND_b; + }; + + union + { + __IOM uint32_t MDIO_DATA; /*!< (@ 0x00000708) MDIO Data Register */ + + struct + { + __IOM uint32_t MDIO_DATA : 16; /*!< [15..0] MDIO_DATA */ + uint32_t : 16; + } MDIO_DATA_b; + }; + __IM uint32_t RESERVED23[61]; + + union + { + __IM uint32_t REV_P0; /*!< (@ 0x00000800) Port 0 MAC Core Revision (n = 0 to 3) */ + + struct + { + __IM uint32_t REV : 32; /*!< [31..0] MAC Core Revision */ + } REV_P0_b; + }; + __IM uint32_t RESERVED24; + + union + { + __IOM uint32_t COMMAND_CONFIG_P0; /*!< (@ 0x00000808) Port 0 Command Configuration Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t TX_ENA : 1; /*!< [0..0] Enable/Disable MAC Transmit Path */ + __IOM uint32_t RX_ENA : 1; /*!< [1..1] Enable/Disable MAC Receive Path */ + __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from + * the IMC until the current frame is completed. This can + * cause the IPG between frames to be more than the value + * in TX_IPG_LENGTH. */ + __IOM uint32_t ETH_SPEED : 1; /*!< [3..3] Operation Mode Definition */ + __IM uint32_t PROMIS_EN : 1; /*!< [4..4] Enable/Disable MAC Promiscuous Operation */ + __IM uint32_t PAD_EN : 1; /*!< [5..5] Enable/Disable Frame Padding Remove on Receive */ + uint32_t : 1; + __IM uint32_t PAUSE_FWD : 1; /*!< [7..7] Terminate/Forward Pause Frames */ + __IOM uint32_t PAUSE_IGNORE : 1; /*!< [8..8] Ignore Pause Frame Quanta */ + __IM uint32_t TX_ADDR_INS : 1; /*!< [9..9] Non writable bit, fixed to 0 always. */ + __IOM uint32_t HD_ENA : 1; /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or + * full-duplex only (set to 0). */ + __IOM uint32_t TX_CRC_APPEND : 1; /*!< [11..11] Enable CRC Append on Transmit */ + uint32_t : 1; + __IOM uint32_t SW_RESET : 1; /*!< [13..13] Self Clearing Reset Command Bit */ + uint32_t : 9; + __IOM uint32_t CNTL_FRM_ENA : 1; /*!< [23..23] MAC Control Frame Enable */ + __IOM uint32_t NO_LGTH_CHK : 1; /*!< [24..24] Payload Length Check Disable */ + __IOM uint32_t ENA_10 : 1; /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn + * register. */ + __IOM uint32_t EFPI_SELECT : 1; /*!< [26..26] EFPI_SELECT */ + __IOM uint32_t TX_TRUNCATE : 1; /*!< [27..27] TX_TRUNCATE */ + uint32_t : 2; + __IOM uint32_t TIMER_SEL : 1; /*!< [30..30] Selects the default timer to use for timestamping operations + * on transmit and on receive. The value is used when not + * overridden by the PTP auto-response function, pattern matchers + * or force forwarding information in a management tag. */ + uint32_t : 1; + } COMMAND_CONFIG_P0_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_0_P0; /*!< (@ 0x0000080C) Port 0 MAC Address Register 0 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First + * byte is bits [7:0]. The MAC address is used on locally + * generated frames such as pause frames, peer-delay response. */ + } MAC_ADDR_0_P0_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_1_P0; /*!< (@ 0x00000810) Port 0 MAC Address Register 1 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits + * [7:0] is the 5th byte and bits [15:8] is the 6th byte. */ + uint32_t : 16; + } MAC_ADDR_1_P0_b; + }; + + union + { + __IOM uint32_t FRM_LENGTH_P0; /*!< (@ 0x00000814) Port 0 Maximum Frame Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length */ + uint32_t : 18; + } FRM_LENGTH_P0_b; + }; + + union + { + __IM uint32_t PAUSE_QUANT_P0; /*!< (@ 0x00000818) Port 0 MAC Pause Quanta (n = 0 to 3) */ + + struct + { + __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta */ + uint32_t : 16; + } PAUSE_QUANT_P0_b; + }; + + union + { + __IOM uint32_t MAC_LINK_QTRIG_P0; /*!< (@ 0x0000081C) Port 0 Trigger Event Configuration Register (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port Bit Mask */ + uint32_t : 12; + __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame + * is transmitted from the ports indicated by PORT_MASK. A + * single frame is transmitted per indicated port in PORT_MASK + * among the queues indicated by QUEUE_MASK. */ + uint32_t : 4; + __IOM uint32_t TRIGGERED : 1; /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether + * a frame was transmitted. When MODE is set to 0, TRIGGERED + * is always 0. This flag clears when the register is written. */ + __IOM uint32_t DLR_MODE : 1; /*!< [29..29] When set to 0, the DLR state machine is ignored. When + * set to 1, the Link Queue Trigger occurs only if the DLR + * state machine is in the NORMAL or FAULT state. */ + __IOM uint32_t MODE : 1; /*!< [30..30] When set to 0, only a single Link_Status frame is generated. + * This is to prevent sending multiple frames due to link + * flapping. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature. + * When the link status (phy_link) transitions from 1 -> + * 0, a trigger event is generated to the memory controller + * for the ports and queues indicated in PORT_MASK and QUEUE_MASK. */ + } MAC_LINK_QTRIG_P0_b; + }; + __IM uint32_t RESERVED25[4]; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY1_P0; /*!< (@ 0x00000830) Port 0 PTP Clock Identity 1 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0] */ + __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1] */ + __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2] */ + __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3] */ + } PTPCLOCKIDENTITY1_P0_b; + }; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY2_P0; /*!< (@ 0x00000834) Port 0 PTP Clock Identity 2 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4] */ + __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5] */ + __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6] */ + __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7] */ + } PTPCLOCKIDENTITY2_P0_b; + }; + + union + { + __IOM uint32_t PTPAUTORESPONSE_P0; /*!< (@ 0x00000838) Port 0 PTP Auto Response Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t ARSP_EN : 1; /*!< [0..0] Auto Response Enable */ + __IOM uint32_t D_TIMER : 1; /*!< [1..1] Default timer to use for auto-response generation */ + uint32_t : 14; + __IOM uint32_t PORTNUM1 : 8; /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb) */ + __IOM uint32_t PORTNUM0 : 8; /*!< [31..24] 28, portIdentity.PortNumber[0] (msb) */ + } PTPAUTORESPONSE_P0_b; + }; + __IM uint32_t RESERVED26; + + union + { + __IOM uint32_t STATUS_P0; /*!< (@ 0x00000840) Port 0 Status Register */ + + struct + { + __IM uint32_t PHYSPEED : 2; /*!< [1..0] Currently Active PHY Interface Speed */ + __IM uint32_t PHYLINK : 1; /*!< [2..2] Link status from PHY interface */ + __IM uint32_t PHYDUPLEX : 1; /*!< [3..3] Duplex status from PHY interface */ + __IOM uint32_t TX_UNDFLW : 1; /*!< [4..4] Indicates that the transmit MAC underflow. This shall + * never occur during normal operation. */ + __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed + * to complete in time before the next frame was received + * at the port. This should never occur under normal operation. + * The cause could be from IPG violations in the received + * frames. */ + __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according + * to clause 30.14.1.2 of the 802.3br specification */ + uint32_t : 23; + } STATUS_P0_b; + }; + + union + { + __IOM uint32_t TX_IPG_LENGTH_P0; /*!< (@ 0x00000844) Port 0 Transmit IPG Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values + * are in the range of 8 to 31. */ + uint32_t : 11; + __IOM uint32_t MINRTC3GAP : 5; /*!< [20..16] MINRTC3GAP */ + uint32_t : 11; + } TX_IPG_LENGTH_P0_b; + }; + + union + { + __IOM uint32_t EEE_CTL_STAT_P0; /*!< (@ 0x00000848) Port 0 MAC EEE Functions Control and Status (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_AUTO : 1; /*!< [0..0] EEE Automatic Mode of Operation */ + __IOM uint32_t LPI_REQ : 1; /*!< [1..1] Request LPI Transmission when MAC Becomes Idle */ + __IOM uint32_t LPI_TXHOLD : 1; /*!< [2..2] MAC Transmission Hold */ + uint32_t : 5; + __IM uint32_t ST_LPI_REQ : 1; /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC */ + __IM uint32_t ST_LPI_TXHOLD : 1; /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC */ + __IM uint32_t ST_TXBUSY : 1; /*!< [10..10] Status (real time) if the MAC is currently transmitting. */ + __IM uint32_t ST_TXAVAIL : 1; /*!< [11..11] Status (real time) if the MAC transmit FIFO has data + * available for transmission. */ + __IM uint32_t ST_LPI_IND : 1; /*!< [12..12] Status (real time) of Received LPI */ + uint32_t : 3; + __IM uint32_t STLH_LPI_REQ : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC */ + __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the + * MAC */ + __IM uint32_t STLH_TXBUSY : 1; /*!< [18..18] Status (latched high) if the MAC is/was Transmitting */ + uint32_t : 1; + __IM uint32_t STLH_LPI_IND : 1; /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND) */ + uint32_t : 11; + } EEE_CTL_STAT_P0_b; + }; + + union + { + __IOM uint32_t EEE_IDLE_TIME_P0; /*!< (@ 0x0000084C) Port 0 EEE Idle Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission + * of LPI begins. A 32-bit value in steps of 32 switch operating + * clock cycles. A value of 0 disables the timer. The value + * must be set to 1 less count. */ + } EEE_IDLE_TIME_P0_b; + }; + + union + { + __IOM uint32_t EEE_TWSYS_TIME_P0; /*!< (@ 0x00000850) Port 0 EEE Wake Up Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed + * to begin transmitting the first frame again. A 32-bit value + * in steps of switch operating clock cycles. A value of 0 + * disables the timer. The value must be set to 1 less count. */ + } EEE_TWSYS_TIME_P0_b; + }; + + union + { + __IOM uint32_t IDLE_SLOPE_P0; /*!< (@ 0x00000854) Port 0 MAC Traffic Shaper Bandwidth Control */ + + struct + { + __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control */ + uint32_t : 21; + } IDLE_SLOPE_P0_b; + }; + + union + { + __IOM uint32_t CT_DELAY_P0; /*!< (@ 0x00000858) Port 0 Cut-Through Delay Indication Register */ + + struct + { + __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency + * of the MII PHY interface) */ + uint32_t : 23; + } CT_DELAY_P0_b; + }; + + union + { + __IOM uint32_t BR_CONTROL_P0; /*!< (@ 0x0000085C) Port 0 802.3br Frame Configuration Register */ + + struct + { + __IOM uint32_t PREEMPT_ENA : 1; /*!< [0..0] When set to 1, enables 802.3br Frame Preemption. */ + __IOM uint32_t VERIFY_DIS : 1; /*!< [1..1] When set to 1, disables the verify process required for + * preemption operation. */ + __IOM uint32_t RESPONSE_DIS : 1; /*!< [2..2] When set to 1 prevents the MAC from responding to "verify" + * frames. */ + uint32_t : 1; + __IOM uint32_t ADDFRAGSIZE : 2; /*!< [5..4] Minimum fragment size in increments of 64 bytes. */ + uint32_t : 2; + __IOM uint32_t TX_VERIFY_TIME : 7; /*!< [14..8] Preemption verification timeout in milliseconds. */ + uint32_t : 1; + __IOM uint32_t RX_STRICT_PRE : 1; /*!< [16..16] When set to 1, the preamble is checked so all bytes + * except the SFD are 0x55. When set to 0, only the last 2 + * bytes of the preamble are checked (SFD/SMD and FRAG_COUNT). + * It is recommended to set this bit to 1 to comply with the + * 802.3br specification. This bit must be set to 0 if only + * non-802.3br traffic is expected (for example, normal Ethernet + * traffic) and if custom preamble is used. */ + __IOM uint32_t RX_BR_SMD_DIS : 1; /*!< [17..17] When set to 1, the receiver does not decode the 802.3br + * SMDs and assumes all frames are express frames. This bit + * must be set to 0 for correct operation with 802.3br, and + * can be set to 1 when 802.3br is not enabled to avoid false + * detection of SMDs. */ + __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE + * frames is enabled. When set to 1, the frame contents and + * frame length checks are also performed on these frames. + * The mCRC is always checked regardless of the value of this + * register. This bit must be set to 0 to be compliant with + * the functionality described in IEEE 802.3br. */ + __IOM uint32_t TX_MCRC_INV : 1; /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for transmitted frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + __IOM uint32_t RX_MCRC_INV : 1; /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for received frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + uint32_t : 11; + } BR_CONTROL_P0_b; + }; + __IM uint32_t RESERVED27[2]; + + union + { + __IM uint32_t AFRAMESTRANSMITTEDOK_P0; /*!< (@ 0x00000868) Port 0 MAC Transmitted Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Transmitted, including pause. */ + } AFRAMESTRANSMITTEDOK_P0_b; + }; + + union + { + __IM uint32_t AFRAMESRECEIVEDOK_P0; /*!< (@ 0x0000086C) Port 0 MAC Received Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Received, including pause. */ + } AFRAMESRECEIVEDOK_P0_b; + }; + + union + { + __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P0; /*!< (@ 0x00000870) Port 0 MAC FCS Error Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t FCSERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Length but CRC error. */ + } AFRAMECHECKSEQUENCEERRORS_P0_b; + }; + + union + { + __IM uint32_t AALIGNMENTERRORS_P0; /*!< (@ 0x00000874) Port 0 MAC Alignment Error Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number + * of Nibbles (MII) Received. */ + } AALIGNMENTERRORS_P0_b; + }; + + union + { + __IM uint32_t AOCTETSTRANSMITTEDOK_P0; /*!< (@ 0x00000878) Port 0 MAC Transmitted Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Transmitted. */ + } AOCTETSTRANSMITTEDOK_P0_b; + }; + + union + { + __IM uint32_t AOCTETSRECEIVEDOK_P0; /*!< (@ 0x0000087C) Port 0 MAC Received Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Received. */ + } AOCTETSRECEIVEDOK_P0_b; + }; + + union + { + __IM uint32_t ATXPAUSEMACCTRLFRAMES_P0; /*!< (@ 0x00000880) Port 0 MAC Transmitted Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Transmitted. */ + } ATXPAUSEMACCTRLFRAMES_P0_b; + }; + + union + { + __IM uint32_t ARXPAUSEMACCTRLFRAMES_P0; /*!< (@ 0x00000884) Port 0 MAC Received Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Received. */ + } ARXPAUSEMACCTRLFRAMES_P0_b; + }; + + union + { + __IM uint32_t IFINERRORS_P0; /*!< (@ 0x00000888) Port 0 MAC Input Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error + * During Reception such as CRC, Length, PHY Error, RX FIFO + * Overflow. */ + } IFINERRORS_P0_b; + }; + + union + { + __IM uint32_t IFOUTERRORS_P0; /*!< (@ 0x0000088C) Port 0 MAC Output Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame + * Transmitted with PHY error. */ + } IFOUTERRORS_P0_b; + }; + + union + { + __IM uint32_t IFINUCASTPKTS_P0; /*!< (@ 0x00000890) Port 0 MAC Received Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Received. */ + } IFINUCASTPKTS_P0_b; + }; + + union + { + __IM uint32_t IFINMULTICASTPKTS_P0; /*!< (@ 0x00000894) Port 0 MAC Received Multicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Received. */ + } IFINMULTICASTPKTS_P0_b; + }; + + union + { + __IM uint32_t IFINBROADCASTPKTS_P0; /*!< (@ 0x00000898) Port 0 MAC Received Broadcast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Received. */ + } IFINBROADCASTPKTS_P0_b; + }; + + union + { + __IM uint32_t IFOUTDISCARDS_P0; /*!< (@ 0x0000089C) Port 0 MAC Discarded Outbound Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable */ + } IFOUTDISCARDS_P0_b; + }; + + union + { + __IM uint32_t IFOUTUCASTPKTS_P0; /*!< (@ 0x000008A0) Port 0 MAC Transmitted Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Transmitted. */ + } IFOUTUCASTPKTS_P0_b; + }; + + union + { + __IM uint32_t IFOUTMULTICASTPKTS_P0; /*!< (@ 0x000008A4) Port 0 MAC Transmitted Multicast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Transmitted. */ + } IFOUTMULTICASTPKTS_P0_b; + }; + + union + { + __IM uint32_t IFOUTBROADCASTPKTS_P0; /*!< (@ 0x000008A8) Port 0 MAC Transmitted Broadcast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Transmitted. */ + } IFOUTBROADCASTPKTS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSDROPEVENTS_P0; /*!< (@ 0x000008AC) Port 0 MAC Dropped Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t DROPCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO + * Full at frame start. */ + } ETHERSTATSDROPEVENTS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSOCTETS_P0; /*!< (@ 0x000008B0) Port 0 MAC All Frame Octets Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLOCTETS : 32; /*!< [31..0] ALLOCTETS */ + } ETHERSTATSOCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS_P0; /*!< (@ 0x000008B4) Port 0 MAC All Frame Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT */ + } ETHERSTATSPKTS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P0; /*!< (@ 0x000008B8) Port 0 MAC Too Short Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t TOOSHRTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Good CRC. */ + } ETHERSTATSUNDERSIZEPKTS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSOVERSIZEPKTS_P0; /*!< (@ 0x000008BC) Port 0 MAC Too Long Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t TOOLONGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Good CRC. */ + } ETHERSTATSOVERSIZEPKTS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS64OCTETS_P0; /*!< (@ 0x000008C0) Port 0 MAC 64 Octets Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT64 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 64 bytes). */ + } ETHERSTATSPKTS64OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P0; /*!< (@ 0x000008C4) Port 0 MAC 65 to 127 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT65T127 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 65 to 127 bytes). */ + } ETHERSTATSPKTS65TO127OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P0; /*!< (@ 0x000008C8) Port 0 MAC 128 to 255 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT128T255 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 128 to 255 bytes). */ + } ETHERSTATSPKTS128TO255OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P0; /*!< (@ 0x000008CC) Port 0 MAC 256 to 511 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT256T511 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 256 to 511 bytes). */ + } ETHERSTATSPKTS256TO511OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P0; /*!< (@ 0x000008D0) Port 0 MAC 512 to 1023 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT512T1023 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 512 to 1023 bytes). */ + } ETHERSTATSPKTS512TO1023OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P0; /*!< (@ 0x000008D4) Port 0 MAC 1024 to 1518 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1024T1518 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 1024 to 1518 bytes). */ + } ETHERSTATSPKTS1024TO1518OCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P0; /*!< (@ 0x000008D8) Port 0 MAC Over 1519 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1519TX : 32; /*!< [31..0] PORT n, this field indicates the number of MAC all Frames, + * Good and Bad (Packet Size: over 1519 bytes). */ + } ETHERSTATSPKTS1519TOXOCTETS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSJABBERS_P0; /*!< (@ 0x000008DC) Port 0 MAC Jabbers Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Bad CRC. */ + } ETHERSTATSJABBERS_P0_b; + }; + + union + { + __IM uint32_t ETHERSTATSFRAGMENTS_P0; /*!< (@ 0x000008E0) Port 0 MAC Fragment Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t FRAGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Bad CRC. */ + } ETHERSTATSFRAGMENTS_P0_b; + }; + __IM uint32_t RESERVED28; + + union + { + __IM uint32_t VLANRECEIVEDOK_P0; /*!< (@ 0x000008E8) Port 0 MAC Received VLAN Tagged Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Received. */ + } VLANRECEIVEDOK_P0_b; + }; + __IM uint32_t RESERVED29[2]; + + union + { + __IM uint32_t VLANTRANSMITTEDOK_P0; /*!< (@ 0x000008F4) Port 0 MAC Transmitted VLAN Tagged Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Transmitted. */ + } VLANTRANSMITTEDOK_P0_b; + }; + + union + { + __IM uint32_t FRAMESRETRANSMITTED_P0; /*!< (@ 0x000008F8) Port 0 MAC Retransmitted Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RETXCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Transmitted + * Frames that experienced a collision and were retransmitted. */ + } FRAMESRETRANSMITTED_P0_b; + }; + __IM uint32_t RESERVED30; + + union + { + __IM uint32_t STATS_HIWORD_P0; /*!< (@ 0x00000900) Port 0 MAC Statistics Counter High Word Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics + * Counter Last Read */ + } STATS_HIWORD_P0_b; + }; + + union + { + __IOM uint32_t STATS_CTRL_P0; /*!< (@ 0x00000904) Port 0 MAC Statistics Control Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t CLRALL : 1; /*!< [0..0] Self Clearing Counter Initialize Command */ + __IM uint32_t CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication */ + uint32_t : 30; + } STATS_CTRL_P0_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUELO_P0; /*!< (@ 0x00000908) Port 0 MAC Statistics Clear Value Lower Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUELO_P0_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUEHI_P0; /*!< (@ 0x0000090C) Port 0 MAC Statistics Clear Value Higher Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUEHI_P0_b; + }; + + union + { + __IM uint32_t ADEFERRED_P0; /*!< (@ 0x00000910) Port 0 MAC Deferred Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted + * without collision but was deferred at begin. */ + } ADEFERRED_P0_b; + }; + + union + { + __IM uint32_t AMULTIPLECOLLISIONS_P0; /*!< (@ 0x00000914) Port 0 MAC Multiple Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after multiple collisions. */ + } AMULTIPLECOLLISIONS_P0_b; + }; + + union + { + __IM uint32_t ASINGLECOLLISIONS_P0; /*!< (@ 0x00000918) Port 0 MAC Single Collision Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after single collision. */ + } ASINGLECOLLISIONS_P0_b; + }; + + union + { + __IM uint32_t ALATECOLLISIONS_P0; /*!< (@ 0x0000091C) Port 0 MAC Late Collision Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late + * Collision. Frame was aborted and not retransmitted. */ + } ALATECOLLISIONS_P0_b; + }; + + union + { + __IM uint32_t AEXCESSIVECOLLISIONS_P0; /*!< (@ 0x00000920) Port 0 MAC Excessive Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t EXCCOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frames Discarded + * due to 16 consecutive collisions. */ + } AEXCESSIVECOLLISIONS_P0_b; + }; + + union + { + __IM uint32_t ACARRIERSENSEERRORS_P0; /*!< (@ 0x00000924) Port 0 MAC Carrier Sense Error Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t CSERRCOUNT : 32; /*!< [31..0] PORT n, increments during Transmission without Collisions + * the PHY Carrier Sense Signal (RX_CRS) dropped or never + * asserted. */ + } ACARRIERSENSEERRORS_P0_b; + }; + __IM uint32_t RESERVED31[182]; + + union + { + __IM uint32_t REV_P1; /*!< (@ 0x00000C00) Port 1 MAC Core Revision (n = 0 to 3) */ + + struct + { + __IM uint32_t REV : 32; /*!< [31..0] MAC Core Revision */ + } REV_P1_b; + }; + __IM uint32_t RESERVED32; + + union + { + __IOM uint32_t COMMAND_CONFIG_P1; /*!< (@ 0x00000C08) Port 1 Command Configuration Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t TX_ENA : 1; /*!< [0..0] Enable/Disable MAC Transmit Path */ + __IOM uint32_t RX_ENA : 1; /*!< [1..1] Enable/Disable MAC Receive Path */ + __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from + * the IMC until the current frame is completed. This can + * cause the IPG between frames to be more than the value + * in TX_IPG_LENGTH. */ + __IOM uint32_t ETH_SPEED : 1; /*!< [3..3] Operation Mode Definition */ + __IM uint32_t PROMIS_EN : 1; /*!< [4..4] Enable/Disable MAC Promiscuous Operation */ + __IM uint32_t PAD_EN : 1; /*!< [5..5] Enable/Disable Frame Padding Remove on Receive */ + uint32_t : 1; + __IM uint32_t PAUSE_FWD : 1; /*!< [7..7] Terminate/Forward Pause Frames */ + __IOM uint32_t PAUSE_IGNORE : 1; /*!< [8..8] Ignore Pause Frame Quanta */ + __IM uint32_t TX_ADDR_INS : 1; /*!< [9..9] Non writable bit, fixed to 0 always. */ + __IOM uint32_t HD_ENA : 1; /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or + * full-duplex only (set to 0). */ + __IOM uint32_t TX_CRC_APPEND : 1; /*!< [11..11] Enable CRC Append on Transmit */ + uint32_t : 1; + __IOM uint32_t SW_RESET : 1; /*!< [13..13] Self Clearing Reset Command Bit */ + uint32_t : 9; + __IOM uint32_t CNTL_FRM_ENA : 1; /*!< [23..23] MAC Control Frame Enable */ + __IOM uint32_t NO_LGTH_CHK : 1; /*!< [24..24] Payload Length Check Disable */ + __IOM uint32_t ENA_10 : 1; /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn + * register. */ + __IOM uint32_t EFPI_SELECT : 1; /*!< [26..26] EFPI_SELECT */ + __IOM uint32_t TX_TRUNCATE : 1; /*!< [27..27] TX_TRUNCATE */ + uint32_t : 2; + __IOM uint32_t TIMER_SEL : 1; /*!< [30..30] Selects the default timer to use for timestamping operations + * on transmit and on receive. The value is used when not + * overridden by the PTP auto-response function, pattern matchers + * or force forwarding information in a management tag. */ + uint32_t : 1; + } COMMAND_CONFIG_P1_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_0_P1; /*!< (@ 0x00000C0C) Port 1 MAC Address Register 0 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First + * byte is bits [7:0]. The MAC address is used on locally + * generated frames such as pause frames, peer-delay response. */ + } MAC_ADDR_0_P1_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_1_P1; /*!< (@ 0x00000C10) Port 1 MAC Address Register 1 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits + * [7:0] is the 5th byte and bits [15:8] is the 6th byte. */ + uint32_t : 16; + } MAC_ADDR_1_P1_b; + }; + + union + { + __IOM uint32_t FRM_LENGTH_P1; /*!< (@ 0x00000C14) Port 1 Maximum Frame Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length */ + uint32_t : 18; + } FRM_LENGTH_P1_b; + }; + + union + { + __IM uint32_t PAUSE_QUANT_P1; /*!< (@ 0x00000C18) Port 1 MAC Pause Quanta (n = 0 to 3) */ + + struct + { + __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta */ + uint32_t : 16; + } PAUSE_QUANT_P1_b; + }; + + union + { + __IOM uint32_t MAC_LINK_QTRIG_P1; /*!< (@ 0x00000C1C) Port 1 Trigger Event Configuration Register (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port Bit Mask */ + uint32_t : 12; + __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame + * is transmitted from the ports indicated by PORT_MASK. A + * single frame is transmitted per indicated port in PORT_MASK + * among the queues indicated by QUEUE_MASK. */ + uint32_t : 4; + __IOM uint32_t TRIGGERED : 1; /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether + * a frame was transmitted. When MODE is set to 0, TRIGGERED + * is always 0. This flag clears when the register is written. */ + __IOM uint32_t DLR_MODE : 1; /*!< [29..29] When set to 0, the DLR state machine is ignored. When + * set to 1, the Link Queue Trigger occurs only if the DLR + * state machine is in the NORMAL or FAULT state. */ + __IOM uint32_t MODE : 1; /*!< [30..30] When set to 0, only a single Link_Status frame is generated. + * This is to prevent sending multiple frames due to link + * flapping. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature. + * When the link status (phy_link) transitions from 1 -> + * 0, a trigger event is generated to the memory controller + * for the ports and queues indicated in PORT_MASK and QUEUE_MASK. */ + } MAC_LINK_QTRIG_P1_b; + }; + __IM uint32_t RESERVED33[4]; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY1_P1; /*!< (@ 0x00000C30) Port 1 PTP Clock Identity 1 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0] */ + __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1] */ + __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2] */ + __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3] */ + } PTPCLOCKIDENTITY1_P1_b; + }; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY2_P1; /*!< (@ 0x00000C34) Port 1 PTP Clock Identity 2 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4] */ + __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5] */ + __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6] */ + __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7] */ + } PTPCLOCKIDENTITY2_P1_b; + }; + + union + { + __IOM uint32_t PTPAUTORESPONSE_P1; /*!< (@ 0x00000C38) Port 1 PTP Auto Response Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t ARSP_EN : 1; /*!< [0..0] Auto Response Enable */ + __IOM uint32_t D_TIMER : 1; /*!< [1..1] Default timer to use for auto-response generation */ + uint32_t : 14; + __IOM uint32_t PORTNUM1 : 8; /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb) */ + __IOM uint32_t PORTNUM0 : 8; /*!< [31..24] 28, portIdentity.PortNumber[0] (msb) */ + } PTPAUTORESPONSE_P1_b; + }; + __IM uint32_t RESERVED34; + + union + { + __IOM uint32_t STATUS_P1; /*!< (@ 0x00000C40) Port 1 Status Register */ + + struct + { + __IM uint32_t PHYSPEED : 2; /*!< [1..0] Currently Active PHY Interface Speed */ + __IM uint32_t PHYLINK : 1; /*!< [2..2] Link status from PHY interface */ + __IM uint32_t PHYDUPLEX : 1; /*!< [3..3] Duplex status from PHY interface */ + __IOM uint32_t TX_UNDFLW : 1; /*!< [4..4] Indicates that the transmit MAC underflow. This shall + * never occur during normal operation. */ + __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed + * to complete in time before the next frame was received + * at the port. This should never occur under normal operation. + * The cause could be from IPG violations in the received + * frames. */ + __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according + * to clause 30.14.1.2 of the 802.3br specification */ + uint32_t : 23; + } STATUS_P1_b; + }; + + union + { + __IOM uint32_t TX_IPG_LENGTH_P1; /*!< (@ 0x00000C44) Port 1 Transmit IPG Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values + * are in the range of 8 to 31. */ + uint32_t : 11; + __IOM uint32_t MINRTC3GAP : 5; /*!< [20..16] MINRTC3GAP */ + uint32_t : 11; + } TX_IPG_LENGTH_P1_b; + }; + + union + { + __IOM uint32_t EEE_CTL_STAT_P1; /*!< (@ 0x00000C48) Port 1 MAC EEE Functions Control and Status (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_AUTO : 1; /*!< [0..0] EEE Automatic Mode of Operation */ + __IOM uint32_t LPI_REQ : 1; /*!< [1..1] Request LPI Transmission when MAC Becomes Idle */ + __IOM uint32_t LPI_TXHOLD : 1; /*!< [2..2] MAC Transmission Hold */ + uint32_t : 5; + __IM uint32_t ST_LPI_REQ : 1; /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC */ + __IM uint32_t ST_LPI_TXHOLD : 1; /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC */ + __IM uint32_t ST_TXBUSY : 1; /*!< [10..10] Status (real time) if the MAC is currently transmitting. */ + __IM uint32_t ST_TXAVAIL : 1; /*!< [11..11] Status (real time) if the MAC transmit FIFO has data + * available for transmission. */ + __IM uint32_t ST_LPI_IND : 1; /*!< [12..12] Status (real time) of Received LPI */ + uint32_t : 3; + __IM uint32_t STLH_LPI_REQ : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC */ + __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the + * MAC */ + __IM uint32_t STLH_TXBUSY : 1; /*!< [18..18] Status (latched high) if the MAC is/was Transmitting */ + uint32_t : 1; + __IM uint32_t STLH_LPI_IND : 1; /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND) */ + uint32_t : 11; + } EEE_CTL_STAT_P1_b; + }; + + union + { + __IOM uint32_t EEE_IDLE_TIME_P1; /*!< (@ 0x00000C4C) Port 1 EEE Idle Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission + * of LPI begins. A 32-bit value in steps of 32 switch operating + * clock cycles. A value of 0 disables the timer. The value + * must be set to 1 less count. */ + } EEE_IDLE_TIME_P1_b; + }; + + union + { + __IOM uint32_t EEE_TWSYS_TIME_P1; /*!< (@ 0x00000C50) Port 1 EEE Wake Up Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed + * to begin transmitting the first frame again. A 32-bit value + * in steps of switch operating clock cycles. A value of 0 + * disables the timer. The value must be set to 1 less count. */ + } EEE_TWSYS_TIME_P1_b; + }; + + union + { + __IOM uint32_t IDLE_SLOPE_P1; /*!< (@ 0x00000C54) Port 1 MAC Traffic Shaper Bandwidth Control */ + + struct + { + __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control */ + uint32_t : 21; + } IDLE_SLOPE_P1_b; + }; + + union + { + __IOM uint32_t CT_DELAY_P1; /*!< (@ 0x00000C58) Port 1 Cut-Through Delay Indication Register */ + + struct + { + __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency + * of the MII PHY interface) */ + uint32_t : 23; + } CT_DELAY_P1_b; + }; + + union + { + __IOM uint32_t BR_CONTROL_P1; /*!< (@ 0x00000C5C) Port 1 802.3br Frame Configuration Register */ + + struct + { + __IOM uint32_t PREEMPT_ENA : 1; /*!< [0..0] When set to 1, enables 802.3br Frame Preemption. */ + __IOM uint32_t VERIFY_DIS : 1; /*!< [1..1] When set to 1, disables the verify process required for + * preemption operation. */ + __IOM uint32_t RESPONSE_DIS : 1; /*!< [2..2] When set to 1 prevents the MAC from responding to "verify" + * frames. */ + uint32_t : 1; + __IOM uint32_t ADDFRAGSIZE : 2; /*!< [5..4] Minimum fragment size in increments of 64 bytes. */ + uint32_t : 2; + __IOM uint32_t TX_VERIFY_TIME : 7; /*!< [14..8] Preemption verification timeout in milliseconds. */ + uint32_t : 1; + __IOM uint32_t RX_STRICT_PRE : 1; /*!< [16..16] When set to 1, the preamble is checked so all bytes + * except the SFD are 0x55. When set to 0, only the last 2 + * bytes of the preamble are checked (SFD/SMD and FRAG_COUNT). + * It is recommended to set this bit to 1 to comply with the + * 802.3br specification. This bit must be set to 0 if only + * non-802.3br traffic is expected (for example, normal Ethernet + * traffic) and if custom preamble is used. */ + __IOM uint32_t RX_BR_SMD_DIS : 1; /*!< [17..17] When set to 1, the receiver does not decode the 802.3br + * SMDs and assumes all frames are express frames. This bit + * must be set to 0 for correct operation with 802.3br, and + * can be set to 1 when 802.3br is not enabled to avoid false + * detection of SMDs. */ + __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE + * frames is enabled. When set to 1, the frame contents and + * frame length checks are also performed on these frames. + * The mCRC is always checked regardless of the value of this + * register. This bit must be set to 0 to be compliant with + * the functionality described in IEEE 802.3br. */ + __IOM uint32_t TX_MCRC_INV : 1; /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for transmitted frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + __IOM uint32_t RX_MCRC_INV : 1; /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for received frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + uint32_t : 11; + } BR_CONTROL_P1_b; + }; + __IM uint32_t RESERVED35[2]; + + union + { + __IM uint32_t AFRAMESTRANSMITTEDOK_P1; /*!< (@ 0x00000C68) Port 1 MAC Transmitted Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Transmitted, including pause. */ + } AFRAMESTRANSMITTEDOK_P1_b; + }; + + union + { + __IM uint32_t AFRAMESRECEIVEDOK_P1; /*!< (@ 0x00000C6C) Port 1 MAC Received Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Received, including pause. */ + } AFRAMESRECEIVEDOK_P1_b; + }; + + union + { + __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P1; /*!< (@ 0x00000C70) Port 1 MAC FCS Error Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t FCSERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Length but CRC error. */ + } AFRAMECHECKSEQUENCEERRORS_P1_b; + }; + + union + { + __IM uint32_t AALIGNMENTERRORS_P1; /*!< (@ 0x00000C74) Port 1 MAC Alignment Error Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number + * of Nibbles (MII) Received. */ + } AALIGNMENTERRORS_P1_b; + }; + + union + { + __IM uint32_t AOCTETSTRANSMITTEDOK_P1; /*!< (@ 0x00000C78) Port 1 MAC Transmitted Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Transmitted. */ + } AOCTETSTRANSMITTEDOK_P1_b; + }; + + union + { + __IM uint32_t AOCTETSRECEIVEDOK_P1; /*!< (@ 0x00000C7C) Port 1 MAC Received Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Received. */ + } AOCTETSRECEIVEDOK_P1_b; + }; + + union + { + __IM uint32_t ATXPAUSEMACCTRLFRAMES_P1; /*!< (@ 0x00000C80) Port 1 MAC Transmitted Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Transmitted. */ + } ATXPAUSEMACCTRLFRAMES_P1_b; + }; + + union + { + __IM uint32_t ARXPAUSEMACCTRLFRAMES_P1; /*!< (@ 0x00000C84) Port 1 MAC Received Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Received. */ + } ARXPAUSEMACCTRLFRAMES_P1_b; + }; + + union + { + __IM uint32_t IFINERRORS_P1; /*!< (@ 0x00000C88) Port 1 MAC Input Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error + * During Reception such as CRC, Length, PHY Error, RX FIFO + * Overflow. */ + } IFINERRORS_P1_b; + }; + + union + { + __IM uint32_t IFOUTERRORS_P1; /*!< (@ 0x00000C8C) Port 1 MAC Output Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame + * Transmitted with PHY error. */ + } IFOUTERRORS_P1_b; + }; + + union + { + __IM uint32_t IFINUCASTPKTS_P1; /*!< (@ 0x00000C90) Port 1 MAC Received Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Received. */ + } IFINUCASTPKTS_P1_b; + }; + + union + { + __IM uint32_t IFINMULTICASTPKTS_P1; /*!< (@ 0x00000C94) Port 1 MAC Received Multicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Received. */ + } IFINMULTICASTPKTS_P1_b; + }; + + union + { + __IM uint32_t IFINBROADCASTPKTS_P1; /*!< (@ 0x00000C98) Port 1 MAC Received Broadcast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Received. */ + } IFINBROADCASTPKTS_P1_b; + }; + + union + { + __IM uint32_t IFOUTDISCARDS_P1; /*!< (@ 0x00000C9C) Port 1 MAC Discarded Outbound Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable */ + } IFOUTDISCARDS_P1_b; + }; + + union + { + __IM uint32_t IFOUTUCASTPKTS_P1; /*!< (@ 0x00000CA0) Port 1 MAC Transmitted Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Transmitted. */ + } IFOUTUCASTPKTS_P1_b; + }; + + union + { + __IM uint32_t IFOUTMULTICASTPKTS_P1; /*!< (@ 0x00000CA4) Port 1 MAC Transmitted Multicast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Transmitted. */ + } IFOUTMULTICASTPKTS_P1_b; + }; + + union + { + __IM uint32_t IFOUTBROADCASTPKTS_P1; /*!< (@ 0x00000CA8) Port 1 MAC Transmitted Broadcast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Transmitted. */ + } IFOUTBROADCASTPKTS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSDROPEVENTS_P1; /*!< (@ 0x00000CAC) Port 1 MAC Dropped Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t DROPCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO + * Full at frame start. */ + } ETHERSTATSDROPEVENTS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSOCTETS_P1; /*!< (@ 0x00000CB0) Port 1 MAC All Frame Octets Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLOCTETS : 32; /*!< [31..0] ALLOCTETS */ + } ETHERSTATSOCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS_P1; /*!< (@ 0x00000CB4) Port 1 MAC All Frame Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT */ + } ETHERSTATSPKTS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P1; /*!< (@ 0x00000CB8) Port 1 MAC Too Short Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t TOOSHRTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Good CRC. */ + } ETHERSTATSUNDERSIZEPKTS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSOVERSIZEPKTS_P1; /*!< (@ 0x00000CBC) Port 1 MAC Too Long Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t TOOLONGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Good CRC. */ + } ETHERSTATSOVERSIZEPKTS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS64OCTETS_P1; /*!< (@ 0x00000CC0) Port 1 MAC 64 Octets Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT64 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 64 bytes). */ + } ETHERSTATSPKTS64OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P1; /*!< (@ 0x00000CC4) Port 1 MAC 65 to 127 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT65T127 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 65 to 127 bytes). */ + } ETHERSTATSPKTS65TO127OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P1; /*!< (@ 0x00000CC8) Port 1 MAC 128 to 255 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT128T255 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 128 to 255 bytes). */ + } ETHERSTATSPKTS128TO255OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P1; /*!< (@ 0x00000CCC) Port 1 MAC 256 to 511 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT256T511 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 256 to 511 bytes). */ + } ETHERSTATSPKTS256TO511OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P1; /*!< (@ 0x00000CD0) Port 1 MAC 512 to 1023 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT512T1023 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 512 to 1023 bytes). */ + } ETHERSTATSPKTS512TO1023OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P1; /*!< (@ 0x00000CD4) Port 1 MAC 1024 to 1518 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1024T1518 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 1024 to 1518 bytes). */ + } ETHERSTATSPKTS1024TO1518OCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P1; /*!< (@ 0x00000CD8) Port 1 MAC Over 1519 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1519TX : 32; /*!< [31..0] PORT n, this field indicates the number of MAC all Frames, + * Good and Bad (Packet Size: over 1519 bytes). */ + } ETHERSTATSPKTS1519TOXOCTETS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSJABBERS_P1; /*!< (@ 0x00000CDC) Port 1 MAC Jabbers Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Bad CRC. */ + } ETHERSTATSJABBERS_P1_b; + }; + + union + { + __IM uint32_t ETHERSTATSFRAGMENTS_P1; /*!< (@ 0x00000CE0) Port 1 MAC Fragment Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t FRAGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Bad CRC. */ + } ETHERSTATSFRAGMENTS_P1_b; + }; + __IM uint32_t RESERVED36; + + union + { + __IM uint32_t VLANRECEIVEDOK_P1; /*!< (@ 0x00000CE8) Port 1 MAC Received VLAN Tagged Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Received. */ + } VLANRECEIVEDOK_P1_b; + }; + __IM uint32_t RESERVED37[2]; + + union + { + __IM uint32_t VLANTRANSMITTEDOK_P1; /*!< (@ 0x00000CF4) Port 1 MAC Transmitted VLAN Tagged Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Transmitted. */ + } VLANTRANSMITTEDOK_P1_b; + }; + + union + { + __IM uint32_t FRAMESRETRANSMITTED_P1; /*!< (@ 0x00000CF8) Port 1 MAC Retransmitted Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RETXCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Transmitted + * Frames that experienced a collision and were retransmitted. */ + } FRAMESRETRANSMITTED_P1_b; + }; + __IM uint32_t RESERVED38; + + union + { + __IM uint32_t STATS_HIWORD_P1; /*!< (@ 0x00000D00) Port 1 MAC Statistics Counter High Word Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics + * Counter Last Read */ + } STATS_HIWORD_P1_b; + }; + + union + { + __IOM uint32_t STATS_CTRL_P1; /*!< (@ 0x00000D04) Port 1 MAC Statistics Control Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t CLRALL : 1; /*!< [0..0] Self Clearing Counter Initialize Command */ + __IM uint32_t CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication */ + uint32_t : 30; + } STATS_CTRL_P1_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUELO_P1; /*!< (@ 0x00000D08) Port 1 MAC Statistics Clear Value Lower Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUELO_P1_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUEHI_P1; /*!< (@ 0x00000D0C) Port 1 MAC Statistics Clear Value Higher Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUEHI_P1_b; + }; + + union + { + __IM uint32_t ADEFERRED_P1; /*!< (@ 0x00000D10) Port 1 MAC Deferred Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted + * without collision but was deferred at begin. */ + } ADEFERRED_P1_b; + }; + + union + { + __IM uint32_t AMULTIPLECOLLISIONS_P1; /*!< (@ 0x00000D14) Port 1 MAC Multiple Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after multiple collisions. */ + } AMULTIPLECOLLISIONS_P1_b; + }; + + union + { + __IM uint32_t ASINGLECOLLISIONS_P1; /*!< (@ 0x00000D18) Port 1 MAC Single Collision Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after single collision. */ + } ASINGLECOLLISIONS_P1_b; + }; + + union + { + __IM uint32_t ALATECOLLISIONS_P1; /*!< (@ 0x00000D1C) Port 1 MAC Late Collision Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late + * Collision. Frame was aborted and not retransmitted. */ + } ALATECOLLISIONS_P1_b; + }; + + union + { + __IM uint32_t AEXCESSIVECOLLISIONS_P1; /*!< (@ 0x00000D20) Port 1 MAC Excessive Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t EXCCOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frames Discarded + * due to 16 consecutive collisions. */ + } AEXCESSIVECOLLISIONS_P1_b; + }; + + union + { + __IM uint32_t ACARRIERSENSEERRORS_P1; /*!< (@ 0x00000D24) Port 1 MAC Carrier Sense Error Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t CSERRCOUNT : 32; /*!< [31..0] PORT n, increments during Transmission without Collisions + * the PHY Carrier Sense Signal (RX_CRS) dropped or never + * asserted. */ + } ACARRIERSENSEERRORS_P1_b; + }; + __IM uint32_t RESERVED39[182]; + + union + { + __IM uint32_t REV_P2; /*!< (@ 0x00001000) Port 2 MAC Core Revision (n = 0 to 3) */ + + struct + { + __IM uint32_t REV : 32; /*!< [31..0] MAC Core Revision */ + } REV_P2_b; + }; + __IM uint32_t RESERVED40; + + union + { + __IOM uint32_t COMMAND_CONFIG_P2; /*!< (@ 0x00001008) Port 2 Command Configuration Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t TX_ENA : 1; /*!< [0..0] Enable/Disable MAC Transmit Path */ + __IOM uint32_t RX_ENA : 1; /*!< [1..1] Enable/Disable MAC Receive Path */ + __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from + * the IMC until the current frame is completed. This can + * cause the IPG between frames to be more than the value + * in TX_IPG_LENGTH. */ + __IOM uint32_t ETH_SPEED : 1; /*!< [3..3] Operation Mode Definition */ + __IM uint32_t PROMIS_EN : 1; /*!< [4..4] Enable/Disable MAC Promiscuous Operation */ + __IM uint32_t PAD_EN : 1; /*!< [5..5] Enable/Disable Frame Padding Remove on Receive */ + uint32_t : 1; + __IM uint32_t PAUSE_FWD : 1; /*!< [7..7] Terminate/Forward Pause Frames */ + __IOM uint32_t PAUSE_IGNORE : 1; /*!< [8..8] Ignore Pause Frame Quanta */ + __IM uint32_t TX_ADDR_INS : 1; /*!< [9..9] Non writable bit, fixed to 0 always. */ + __IOM uint32_t HD_ENA : 1; /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or + * full-duplex only (set to 0). */ + __IOM uint32_t TX_CRC_APPEND : 1; /*!< [11..11] Enable CRC Append on Transmit */ + uint32_t : 1; + __IOM uint32_t SW_RESET : 1; /*!< [13..13] Self Clearing Reset Command Bit */ + uint32_t : 9; + __IOM uint32_t CNTL_FRM_ENA : 1; /*!< [23..23] MAC Control Frame Enable */ + __IOM uint32_t NO_LGTH_CHK : 1; /*!< [24..24] Payload Length Check Disable */ + __IOM uint32_t ENA_10 : 1; /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn + * register. */ + __IOM uint32_t EFPI_SELECT : 1; /*!< [26..26] EFPI_SELECT */ + __IOM uint32_t TX_TRUNCATE : 1; /*!< [27..27] TX_TRUNCATE */ + uint32_t : 2; + __IOM uint32_t TIMER_SEL : 1; /*!< [30..30] Selects the default timer to use for timestamping operations + * on transmit and on receive. The value is used when not + * overridden by the PTP auto-response function, pattern matchers + * or force forwarding information in a management tag. */ + uint32_t : 1; + } COMMAND_CONFIG_P2_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_0_P2; /*!< (@ 0x0000100C) Port 2 MAC Address Register 0 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 32; /*!< [31..0] The first 4 bytes of the MAC address of the port. First + * byte is bits [7:0]. The MAC address is used on locally + * generated frames such as pause frames, peer-delay response. */ + } MAC_ADDR_0_P2_b; + }; + + union + { + __IOM uint32_t MAC_ADDR_1_P2; /*!< (@ 0x00001010) Port 2 MAC Address Register 1 (n = 0 to 2) */ + + struct + { + __IOM uint32_t MAC_ADDR : 16; /*!< [15..0] The last 2 bytes of the MAC address of the port. Bits + * [7:0] is the 5th byte and bits [15:8] is the 6th byte. */ + uint32_t : 16; + } MAC_ADDR_1_P2_b; + }; + + union + { + __IOM uint32_t FRM_LENGTH_P2; /*!< (@ 0x00001014) Port 2 Maximum Frame Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length */ + uint32_t : 18; + } FRM_LENGTH_P2_b; + }; + + union + { + __IM uint32_t PAUSE_QUANT_P2; /*!< (@ 0x00001018) Port 2 MAC Pause Quanta (n = 0 to 3) */ + + struct + { + __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta */ + uint32_t : 16; + } PAUSE_QUANT_P2_b; + }; + + union + { + __IOM uint32_t MAC_LINK_QTRIG_P2; /*!< (@ 0x0000101C) Port 2 Trigger Event Configuration Register (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port Bit Mask */ + uint32_t : 12; + __IOM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame + * is transmitted from the ports indicated by PORT_MASK. A + * single frame is transmitted per indicated port in PORT_MASK + * among the queues indicated by QUEUE_MASK. */ + uint32_t : 4; + __IOM uint32_t TRIGGERED : 1; /*!< [28..28] When MODE is set to 1, TRIGGERED indicates whether + * a frame was transmitted. When MODE is set to 0, TRIGGERED + * is always 0. This flag clears when the register is written. */ + __IOM uint32_t DLR_MODE : 1; /*!< [29..29] When set to 0, the DLR state machine is ignored. When + * set to 1, the Link Queue Trigger occurs only if the DLR + * state machine is in the NORMAL or FAULT state. */ + __IOM uint32_t MODE : 1; /*!< [30..30] When set to 0, only a single Link_Status frame is generated. + * This is to prevent sending multiple frames due to link + * flapping. */ + __IOM uint32_t ENABLE : 1; /*!< [31..31] Write to 1 to enable the Link Queue Trigger feature. + * When the link status (phy_link) transitions from 1 -> + * 0, a trigger event is generated to the memory controller + * for the ports and queues indicated in PORT_MASK and QUEUE_MASK. */ + } MAC_LINK_QTRIG_P2_b; + }; + __IM uint32_t RESERVED41[4]; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY1_P2; /*!< (@ 0x00001030) Port 2 PTP Clock Identity 1 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY0 : 8; /*!< [7..0] 20, portIdentity.ClockIdentity[0] */ + __IOM uint32_t CLK_IDENTITY1 : 8; /*!< [15..8] 21, portIdentity.ClockIdentity[1] */ + __IOM uint32_t CLK_IDENTITY2 : 8; /*!< [23..16] 22, portIdentity.ClockIdentity[2] */ + __IOM uint32_t CLK_IDENTITY3 : 8; /*!< [31..24] 23, portIdentity.ClockIdentity[3] */ + } PTPCLOCKIDENTITY1_P2_b; + }; + + union + { + __IOM uint32_t PTPCLOCKIDENTITY2_P2; /*!< (@ 0x00001034) Port 2 PTP Clock Identity 2 Register (n = 0 to + * 2) */ + + struct + { + __IOM uint32_t CLK_IDENTITY4 : 8; /*!< [7..0] 24, portIdentity.ClockIdentity[4] */ + __IOM uint32_t CLK_IDENTITY5 : 8; /*!< [15..8] 25, portIdentity.ClockIdentity[5] */ + __IOM uint32_t CLK_IDENTITY6 : 8; /*!< [23..16] 26, portIdentity.ClockIdentity[6] */ + __IOM uint32_t CLK_IDENTITY7 : 8; /*!< [31..24] 27, portIdentity.ClockIdentity[7] */ + } PTPCLOCKIDENTITY2_P2_b; + }; + + union + { + __IOM uint32_t PTPAUTORESPONSE_P2; /*!< (@ 0x00001038) Port 2 PTP Auto Response Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t ARSP_EN : 1; /*!< [0..0] Auto Response Enable */ + __IOM uint32_t D_TIMER : 1; /*!< [1..1] Default timer to use for auto-response generation */ + uint32_t : 14; + __IOM uint32_t PORTNUM1 : 8; /*!< [23..16] 29, portIdentity.PortNumber[1] (lsb) */ + __IOM uint32_t PORTNUM0 : 8; /*!< [31..24] 28, portIdentity.PortNumber[0] (msb) */ + } PTPAUTORESPONSE_P2_b; + }; + __IM uint32_t RESERVED42; + + union + { + __IOM uint32_t STATUS_P2; /*!< (@ 0x00001040) Port 2 Status Register */ + + struct + { + __IM uint32_t PHYSPEED : 2; /*!< [1..0] Currently Active PHY Interface Speed */ + __IM uint32_t PHYLINK : 1; /*!< [2..2] Link status from PHY interface */ + __IM uint32_t PHYDUPLEX : 1; /*!< [3..3] Duplex status from PHY interface */ + __IOM uint32_t TX_UNDFLW : 1; /*!< [4..4] Indicates that the transmit MAC underflow. This shall + * never occur during normal operation. */ + __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed + * to complete in time before the next frame was received + * at the port. This should never occur under normal operation. + * The cause could be from IPG violations in the received + * frames. */ + __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according + * to clause 30.14.1.2 of the 802.3br specification */ + uint32_t : 23; + } STATUS_P2_b; + }; + + union + { + __IOM uint32_t TX_IPG_LENGTH_P2; /*!< (@ 0x00001044) Port 2 Transmit IPG Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values + * are in the range of 8 to 31. */ + uint32_t : 11; + __IOM uint32_t MINRTC3GAP : 5; /*!< [20..16] MINRTC3GAP */ + uint32_t : 11; + } TX_IPG_LENGTH_P2_b; + }; + + union + { + __IOM uint32_t EEE_CTL_STAT_P2; /*!< (@ 0x00001048) Port 2 MAC EEE Functions Control and Status (n + * = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_AUTO : 1; /*!< [0..0] EEE Automatic Mode of Operation */ + __IOM uint32_t LPI_REQ : 1; /*!< [1..1] Request LPI Transmission when MAC Becomes Idle */ + __IOM uint32_t LPI_TXHOLD : 1; /*!< [2..2] MAC Transmission Hold */ + uint32_t : 5; + __IM uint32_t ST_LPI_REQ : 1; /*!< [8..8] Status (real time) of Internal LPI_REQ to the MAC */ + __IM uint32_t ST_LPI_TXHOLD : 1; /*!< [9..9] Status (real time) of Internal LPI_TXHOLD to the MAC */ + __IM uint32_t ST_TXBUSY : 1; /*!< [10..10] Status (real time) if the MAC is currently transmitting. */ + __IM uint32_t ST_TXAVAIL : 1; /*!< [11..11] Status (real time) if the MAC transmit FIFO has data + * available for transmission. */ + __IM uint32_t ST_LPI_IND : 1; /*!< [12..12] Status (real time) of Received LPI */ + uint32_t : 3; + __IM uint32_t STLH_LPI_REQ : 1; /*!< [16..16] Status (latched high) of Internal LPI_REQ to the MAC */ + __IM uint32_t STLH_LPI_TXHOLD : 1; /*!< [17..17] Status (latched high) of Internal LPI_TXHOLD to the + * MAC */ + __IM uint32_t STLH_TXBUSY : 1; /*!< [18..18] Status (latched high) if the MAC is/was Transmitting */ + uint32_t : 1; + __IM uint32_t STLH_LPI_IND : 1; /*!< [20..20] Status (latched high) of Received LPI (ST_LPI_IND) */ + uint32_t : 11; + } EEE_CTL_STAT_P2_b; + }; + + union + { + __IOM uint32_t EEE_IDLE_TIME_P2; /*!< (@ 0x0000104C) Port 2 EEE Idle Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_IDLE_TIME : 32; /*!< [31..0] Time (-1) the transmitter must be idle before transmission + * of LPI begins. A 32-bit value in steps of 32 switch operating + * clock cycles. A value of 0 disables the timer. The value + * must be set to 1 less count. */ + } EEE_IDLE_TIME_P2_b; + }; + + union + { + __IOM uint32_t EEE_TWSYS_TIME_P2; /*!< (@ 0x00001050) Port 2 EEE Wake Up Time Register (n = 0 to 2) */ + + struct + { + __IOM uint32_t EEE_WKUP_TIME : 32; /*!< [31..0] Time (-1) after PHY wakeup until the MAC is allowed + * to begin transmitting the first frame again. A 32-bit value + * in steps of switch operating clock cycles. A value of 0 + * disables the timer. The value must be set to 1 less count. */ + } EEE_TWSYS_TIME_P2_b; + }; + + union + { + __IOM uint32_t IDLE_SLOPE_P2; /*!< (@ 0x00001054) Port 2 MAC Traffic Shaper Bandwidth Control */ + + struct + { + __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control */ + uint32_t : 21; + } IDLE_SLOPE_P2_b; + }; + + union + { + __IOM uint32_t CT_DELAY_P2; /*!< (@ 0x00001058) Port 2 Cut-Through Delay Indication Register */ + + struct + { + __IOM uint32_t CT_DELAY : 9; /*!< [8..0] Delay Value in 400 ns / 40 ns / 8 ns increments (frequency + * of the MII PHY interface) */ + uint32_t : 23; + } CT_DELAY_P2_b; + }; + + union + { + __IOM uint32_t BR_CONTROL_P2; /*!< (@ 0x0000105C) Port 2 802.3br Frame Configuration Register */ + + struct + { + __IOM uint32_t PREEMPT_ENA : 1; /*!< [0..0] When set to 1, enables 802.3br Frame Preemption. */ + __IOM uint32_t VERIFY_DIS : 1; /*!< [1..1] When set to 1, disables the verify process required for + * preemption operation. */ + __IOM uint32_t RESPONSE_DIS : 1; /*!< [2..2] When set to 1 prevents the MAC from responding to "verify" + * frames. */ + uint32_t : 1; + __IOM uint32_t ADDFRAGSIZE : 2; /*!< [5..4] Minimum fragment size in increments of 64 bytes. */ + uint32_t : 2; + __IOM uint32_t TX_VERIFY_TIME : 7; /*!< [14..8] Preemption verification timeout in milliseconds. */ + uint32_t : 1; + __IOM uint32_t RX_STRICT_PRE : 1; /*!< [16..16] When set to 1, the preamble is checked so all bytes + * except the SFD are 0x55. When set to 0, only the last 2 + * bytes of the preamble are checked (SFD/SMD and FRAG_COUNT). + * It is recommended to set this bit to 1 to comply with the + * 802.3br specification. This bit must be set to 0 if only + * non-802.3br traffic is expected (for example, normal Ethernet + * traffic) and if custom preamble is used. */ + __IOM uint32_t RX_BR_SMD_DIS : 1; /*!< [17..17] When set to 1, the receiver does not decode the 802.3br + * SMDs and assumes all frames are express frames. This bit + * must be set to 0 for correct operation with 802.3br, and + * can be set to 1 when 802.3br is not enabled to avoid false + * detection of SMDs. */ + __IOM uint32_t RX_STRICT_BR_CTL : 1; /*!< [18..18] When set to 1, strict checking of VERIFY and RESPONSE + * frames is enabled. When set to 1, the frame contents and + * frame length checks are also performed on these frames. + * The mCRC is always checked regardless of the value of this + * register. This bit must be set to 0 to be compliant with + * the functionality described in IEEE 802.3br. */ + __IOM uint32_t TX_MCRC_INV : 1; /*!< [19..19] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for transmitted frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + __IOM uint32_t RX_MCRC_INV : 1; /*!< [20..20] When set to 1, the 32-bit XOR mask used to calculate + * the mCRC for received frames is inverted. This bit must + * always be written to 0 and only used for debugging. */ + uint32_t : 11; + } BR_CONTROL_P2_b; + }; + __IM uint32_t RESERVED43[2]; + + union + { + __IM uint32_t AFRAMESTRANSMITTEDOK_P2; /*!< (@ 0x00001068) Port 2 MAC Transmitted Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Transmitted, including pause. */ + } AFRAMESTRANSMITTEDOK_P2_b; + }; + + union + { + __IM uint32_t AFRAMESRECEIVEDOK_P2; /*!< (@ 0x0000106C) Port 2 MAC Received Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Received, including pause. */ + } AFRAMESRECEIVEDOK_P2_b; + }; + + union + { + __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P2; /*!< (@ 0x00001070) Port 2 MAC FCS Error Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t FCSERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Length but CRC error. */ + } AFRAMECHECKSEQUENCEERRORS_P2_b; + }; + + union + { + __IM uint32_t AALIGNMENTERRORS_P2; /*!< (@ 0x00001074) Port 2 MAC Alignment Error Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number + * of Nibbles (MII) Received. */ + } AALIGNMENTERRORS_P2_b; + }; + + union + { + __IM uint32_t AOCTETSTRANSMITTEDOK_P2; /*!< (@ 0x00001078) Port 2 MAC Transmitted Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Transmitted. */ + } AOCTETSTRANSMITTEDOK_P2_b; + }; + + union + { + __IM uint32_t AOCTETSRECEIVEDOK_P2; /*!< (@ 0x0000107C) Port 2 MAC Received Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Received. */ + } AOCTETSRECEIVEDOK_P2_b; + }; + + union + { + __IM uint32_t ATXPAUSEMACCTRLFRAMES_P2; /*!< (@ 0x00001080) Port 2 MAC Transmitted Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Transmitted. */ + } ATXPAUSEMACCTRLFRAMES_P2_b; + }; + + union + { + __IM uint32_t ARXPAUSEMACCTRLFRAMES_P2; /*!< (@ 0x00001084) Port 2 MAC Received Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Received. */ + } ARXPAUSEMACCTRLFRAMES_P2_b; + }; + + union + { + __IM uint32_t IFINERRORS_P2; /*!< (@ 0x00001088) Port 2 MAC Input Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error + * During Reception such as CRC, Length, PHY Error, RX FIFO + * Overflow. */ + } IFINERRORS_P2_b; + }; + + union + { + __IM uint32_t IFOUTERRORS_P2; /*!< (@ 0x0000108C) Port 2 MAC Output Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame + * Transmitted with PHY error. */ + } IFOUTERRORS_P2_b; + }; + + union + { + __IM uint32_t IFINUCASTPKTS_P2; /*!< (@ 0x00001090) Port 2 MAC Received Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Received. */ + } IFINUCASTPKTS_P2_b; + }; + + union + { + __IM uint32_t IFINMULTICASTPKTS_P2; /*!< (@ 0x00001094) Port 2 MAC Received Multicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Received. */ + } IFINMULTICASTPKTS_P2_b; + }; + + union + { + __IM uint32_t IFINBROADCASTPKTS_P2; /*!< (@ 0x00001098) Port 2 MAC Received Broadcast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Received. */ + } IFINBROADCASTPKTS_P2_b; + }; + + union + { + __IM uint32_t IFOUTDISCARDS_P2; /*!< (@ 0x0000109C) Port 2 MAC Discarded Outbound Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable */ + } IFOUTDISCARDS_P2_b; + }; + + union + { + __IM uint32_t IFOUTUCASTPKTS_P2; /*!< (@ 0x000010A0) Port 2 MAC Transmitted Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Transmitted. */ + } IFOUTUCASTPKTS_P2_b; + }; + + union + { + __IM uint32_t IFOUTMULTICASTPKTS_P2; /*!< (@ 0x000010A4) Port 2 MAC Transmitted Multicast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Transmitted. */ + } IFOUTMULTICASTPKTS_P2_b; + }; + + union + { + __IM uint32_t IFOUTBROADCASTPKTS_P2; /*!< (@ 0x000010A8) Port 2 MAC Transmitted Broadcast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Transmitted. */ + } IFOUTBROADCASTPKTS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSDROPEVENTS_P2; /*!< (@ 0x000010AC) Port 2 MAC Dropped Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t DROPCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO + * Full at frame start. */ + } ETHERSTATSDROPEVENTS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSOCTETS_P2; /*!< (@ 0x000010B0) Port 2 MAC All Frame Octets Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLOCTETS : 32; /*!< [31..0] ALLOCTETS */ + } ETHERSTATSOCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS_P2; /*!< (@ 0x000010B4) Port 2 MAC All Frame Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT */ + } ETHERSTATSPKTS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P2; /*!< (@ 0x000010B8) Port 2 MAC Too Short Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t TOOSHRTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Good CRC. */ + } ETHERSTATSUNDERSIZEPKTS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSOVERSIZEPKTS_P2; /*!< (@ 0x000010BC) Port 2 MAC Too Long Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t TOOLONGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Good CRC. */ + } ETHERSTATSOVERSIZEPKTS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS64OCTETS_P2; /*!< (@ 0x000010C0) Port 2 MAC 64 Octets Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT64 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 64 bytes). */ + } ETHERSTATSPKTS64OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P2; /*!< (@ 0x000010C4) Port 2 MAC 65 to 127 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT65T127 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 65 to 127 bytes). */ + } ETHERSTATSPKTS65TO127OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P2; /*!< (@ 0x000010C8) Port 2 MAC 128 to 255 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT128T255 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 128 to 255 bytes). */ + } ETHERSTATSPKTS128TO255OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P2; /*!< (@ 0x000010CC) Port 2 MAC 256 to 511 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT256T511 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 256 to 511 bytes). */ + } ETHERSTATSPKTS256TO511OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P2; /*!< (@ 0x000010D0) Port 2 MAC 512 to 1023 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT512T1023 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 512 to 1023 bytes). */ + } ETHERSTATSPKTS512TO1023OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P2; /*!< (@ 0x000010D4) Port 2 MAC 1024 to 1518 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1024T1518 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 1024 to 1518 bytes). */ + } ETHERSTATSPKTS1024TO1518OCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P2; /*!< (@ 0x000010D8) Port 2 MAC Over 1519 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1519TX : 32; /*!< [31..0] PORT n, this field indicates the number of MAC all Frames, + * Good and Bad (Packet Size: over 1519 bytes). */ + } ETHERSTATSPKTS1519TOXOCTETS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSJABBERS_P2; /*!< (@ 0x000010DC) Port 2 MAC Jabbers Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Bad CRC. */ + } ETHERSTATSJABBERS_P2_b; + }; + + union + { + __IM uint32_t ETHERSTATSFRAGMENTS_P2; /*!< (@ 0x000010E0) Port 2 MAC Fragment Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t FRAGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Bad CRC. */ + } ETHERSTATSFRAGMENTS_P2_b; + }; + __IM uint32_t RESERVED44; + + union + { + __IM uint32_t VLANRECEIVEDOK_P2; /*!< (@ 0x000010E8) Port 2 MAC Received VLAN Tagged Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Received. */ + } VLANRECEIVEDOK_P2_b; + }; + __IM uint32_t RESERVED45[2]; + + union + { + __IM uint32_t VLANTRANSMITTEDOK_P2; /*!< (@ 0x000010F4) Port 2 MAC Transmitted VLAN Tagged Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Transmitted. */ + } VLANTRANSMITTEDOK_P2_b; + }; + + union + { + __IM uint32_t FRAMESRETRANSMITTED_P2; /*!< (@ 0x000010F8) Port 2 MAC Retransmitted Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RETXCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Transmitted + * Frames that experienced a collision and were retransmitted. */ + } FRAMESRETRANSMITTED_P2_b; + }; + __IM uint32_t RESERVED46; + + union + { + __IM uint32_t STATS_HIWORD_P2; /*!< (@ 0x00001100) Port 2 MAC Statistics Counter High Word Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics + * Counter Last Read */ + } STATS_HIWORD_P2_b; + }; + + union + { + __IOM uint32_t STATS_CTRL_P2; /*!< (@ 0x00001104) Port 2 MAC Statistics Control Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t CLRALL : 1; /*!< [0..0] Self Clearing Counter Initialize Command */ + __IM uint32_t CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication */ + uint32_t : 30; + } STATS_CTRL_P2_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUELO_P2; /*!< (@ 0x00001108) Port 2 MAC Statistics Clear Value Lower Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUELO_P2_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUEHI_P2; /*!< (@ 0x0000110C) Port 2 MAC Statistics Clear Value Higher Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUEHI_P2_b; + }; + + union + { + __IM uint32_t ADEFERRED_P2; /*!< (@ 0x00001110) Port 2 MAC Deferred Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted + * without collision but was deferred at begin. */ + } ADEFERRED_P2_b; + }; + + union + { + __IM uint32_t AMULTIPLECOLLISIONS_P2; /*!< (@ 0x00001114) Port 2 MAC Multiple Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after multiple collisions. */ + } AMULTIPLECOLLISIONS_P2_b; + }; + + union + { + __IM uint32_t ASINGLECOLLISIONS_P2; /*!< (@ 0x00001118) Port 2 MAC Single Collision Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after single collision. */ + } ASINGLECOLLISIONS_P2_b; + }; + + union + { + __IM uint32_t ALATECOLLISIONS_P2; /*!< (@ 0x0000111C) Port 2 MAC Late Collision Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late + * Collision. Frame was aborted and not retransmitted. */ + } ALATECOLLISIONS_P2_b; + }; + + union + { + __IM uint32_t AEXCESSIVECOLLISIONS_P2; /*!< (@ 0x00001120) Port 2 MAC Excessive Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t EXCCOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frames Discarded + * due to 16 consecutive collisions. */ + } AEXCESSIVECOLLISIONS_P2_b; + }; + + union + { + __IM uint32_t ACARRIERSENSEERRORS_P2; /*!< (@ 0x00001124) Port 2 MAC Carrier Sense Error Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t CSERRCOUNT : 32; /*!< [31..0] PORT n, increments during Transmission without Collisions + * the PHY Carrier Sense Signal (RX_CRS) dropped or never + * asserted. */ + } ACARRIERSENSEERRORS_P2_b; + }; + __IM uint32_t RESERVED47[182]; + + union + { + __IM uint32_t REV_P3; /*!< (@ 0x00001400) Port 3 MAC Core Revision (n = 0 to 3) */ + + struct + { + __IM uint32_t REV : 32; /*!< [31..0] MAC Core Revision */ + } REV_P3_b; + }; + __IM uint32_t RESERVED48; + + union + { + __IOM uint32_t COMMAND_CONFIG_P3; /*!< (@ 0x00001408) Port 3 Command Configuration Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t TX_ENA : 1; /*!< [0..0] Enable/Disable MAC Transmit Path */ + __IOM uint32_t RX_ENA : 1; /*!< [1..1] Enable/Disable MAC Receive Path */ + __IOM uint32_t TDMA_PREBUF_DIS : 1; /*!< [2..2] When set to 1, the MAC does not request a new frame from + * the IMC until the current frame is completed. This can + * cause the IPG between frames to be more than the value + * in TX_IPG_LENGTH. */ + __IOM uint32_t ETH_SPEED : 1; /*!< [3..3] Operation Mode Definition */ + __IM uint32_t PROMIS_EN : 1; /*!< [4..4] Enable/Disable MAC Promiscuous Operation */ + __IM uint32_t PAD_EN : 1; /*!< [5..5] Enable/Disable Frame Padding Remove on Receive */ + uint32_t : 1; + __IM uint32_t PAUSE_FWD : 1; /*!< [7..7] Terminate/Forward Pause Frames */ + __IOM uint32_t PAUSE_IGNORE : 1; /*!< [8..8] Ignore Pause Frame Quanta */ + __IM uint32_t TX_ADDR_INS : 1; /*!< [9..9] Non writable bit, fixed to 0 always. */ + __IOM uint32_t HD_ENA : 1; /*!< [10..10] Enable auto full/half-duplex operation (set to 1) or + * full-duplex only (set to 0). */ + __IOM uint32_t TX_CRC_APPEND : 1; /*!< [11..11] Enable CRC Append on Transmit */ + uint32_t : 1; + __IOM uint32_t SW_RESET : 1; /*!< [13..13] Self Clearing Reset Command Bit */ + uint32_t : 9; + __IOM uint32_t CNTL_FRM_ENA : 1; /*!< [23..23] MAC Control Frame Enable */ + __IOM uint32_t NO_LGTH_CHK : 1; /*!< [24..24] Payload Length Check Disable */ + __IOM uint32_t ENA_10 : 1; /*!< [25..25] This bit has no effect except PHYSPEED bit of STATUS_Pn + * register. */ + __IOM uint32_t EFPI_SELECT : 1; /*!< [26..26] EFPI_SELECT */ + __IOM uint32_t TX_TRUNCATE : 1; /*!< [27..27] TX_TRUNCATE */ + uint32_t : 2; + __IOM uint32_t TIMER_SEL : 1; /*!< [30..30] Selects the default timer to use for timestamping operations + * on transmit and on receive. The value is used when not + * overridden by the PTP auto-response function, pattern matchers + * or force forwarding information in a management tag. */ + uint32_t : 1; + } COMMAND_CONFIG_P3_b; + }; + __IM uint32_t RESERVED49[2]; + + union + { + __IOM uint32_t FRM_LENGTH_P3; /*!< (@ 0x00001414) Port 3 Maximum Frame Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t FRM_LENGTH : 14; /*!< [13..0] Maximum Frame Length */ + uint32_t : 18; + } FRM_LENGTH_P3_b; + }; + + union + { + __IM uint32_t PAUSE_QUANT_P3; /*!< (@ 0x00001418) Port 3 MAC Pause Quanta (n = 0 to 3) */ + + struct + { + __IM uint32_t PAUSE_QUANT : 16; /*!< [15..0] Pause Quanta */ + uint32_t : 16; + } PAUSE_QUANT_P3_b; + }; + __IM uint32_t RESERVED50[9]; + + union + { + __IOM uint32_t STATUS_P3; /*!< (@ 0x00001440) Port 3 Status Register */ + + struct + { + __IM uint32_t PHYSPEED : 2; /*!< [1..0] Currently Active PHY Interface Speed */ + __IM uint32_t PHYLINK : 1; /*!< [2..2] Link status from PHY interface */ + __IM uint32_t PHYDUPLEX : 1; /*!< [3..3] Duplex status from PHY interface */ + __IOM uint32_t TX_UNDFLW : 1; /*!< [4..4] Indicates that the transmit MAC underflow. This shall + * never occur during normal operation. */ + __IOM uint32_t LK_DST_ERR : 1; /*!< [5..5] Indicates that the L2 destination lookup process failed + * to complete in time before the next frame was received + * at the port. This should never occur under normal operation. + * The cause could be from IPG violations in the received + * frames. */ + __IM uint32_t BR_VERIF_ST : 3; /*!< [8..6] Indicates the current status of the verification according + * to clause 30.14.1.2 of the 802.3br specification */ + uint32_t : 23; + } STATUS_P3_b; + }; + + union + { + __IOM uint32_t TX_IPG_LENGTH_P3; /*!< (@ 0x00001444) Port 3 Transmit IPG Length Register (n = 0 to + * 3) */ + + struct + { + __IOM uint32_t TX_IPG_LENGTH : 5; /*!< [4..0] Define transmit interpacket gap in octets. Allowed values + * are in the range of 8 to 31. */ + uint32_t : 11; + __IOM uint32_t MINRTC3GAP : 5; /*!< [20..16] MINRTC3GAP */ + uint32_t : 11; + } TX_IPG_LENGTH_P3_b; + }; + __IM uint32_t RESERVED51[3]; + + union + { + __IOM uint32_t IDLE_SLOPE_P3; /*!< (@ 0x00001454) Port 3 MAC Traffic Shaper Bandwidth Control */ + + struct + { + __IOM uint32_t IDLE_SLOPE : 11; /*!< [10..0] Traffic Shaper Bandwidth Control */ + uint32_t : 21; + } IDLE_SLOPE_P3_b; + }; + __IM uint32_t RESERVED52[4]; + + union + { + __IM uint32_t AFRAMESTRANSMITTEDOK_P3; /*!< (@ 0x00001468) Port 3 MAC Transmitted Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Transmitted, including pause. */ + } AFRAMESTRANSMITTEDOK_P3_b; + }; + + union + { + __IM uint32_t AFRAMESRECEIVEDOK_P3; /*!< (@ 0x0000146C) Port 3 MAC Received Valid Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Received, including pause. */ + } AFRAMESRECEIVEDOK_P3_b; + }; + + union + { + __IM uint32_t AFRAMECHECKSEQUENCEERRORS_P3; /*!< (@ 0x00001470) Port 3 MAC FCS Error Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t FCSERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Length but CRC error. */ + } AFRAMECHECKSEQUENCEERRORS_P3_b; + }; + + union + { + __IM uint32_t AALIGNMENTERRORS_P3; /*!< (@ 0x00001474) Port 3 MAC Alignment Error Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t ALGNERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Odd Number + * of Nibbles (MII) Received. */ + } AALIGNMENTERRORS_P3_b; + }; + + union + { + __IM uint32_t AOCTETSTRANSMITTEDOK_P3; /*!< (@ 0x00001478) Port 3 MAC Transmitted Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Transmitted. */ + } AOCTETSTRANSMITTEDOK_P3_b; + }; + + union + { + __IM uint32_t AOCTETSRECEIVEDOK_P3; /*!< (@ 0x0000147C) Port 3 MAC Received Valid Frame Octets Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVALIDOCTETS : 32; /*!< [31..0] PORT n, this field indicates the octets (the payload + * only) of MAC Valid Received. */ + } AOCTETSRECEIVEDOK_P3_b; + }; + + union + { + __IM uint32_t ATXPAUSEMACCTRLFRAMES_P3; /*!< (@ 0x00001480) Port 3 MAC Transmitted Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Transmitted. */ + } ATXPAUSEMACCTRLFRAMES_P3_b; + }; + + union + { + __IM uint32_t ARXPAUSEMACCTRLFRAMES_P3; /*!< (@ 0x00001484) Port 3 MAC Received Pause Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXPAUSECOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Valid + * Pause Received. */ + } ARXPAUSEMACCTRLFRAMES_P3_b; + }; + + union + { + __IM uint32_t IFINERRORS_P3; /*!< (@ 0x00001488) Port 3 MAC Input Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t INERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Any Error + * During Reception such as CRC, Length, PHY Error, RX FIFO + * Overflow. */ + } IFINERRORS_P3_b; + }; + + union + { + __IM uint32_t IFOUTERRORS_P3; /*!< (@ 0x0000148C) Port 3 MAC Output Error Count Register (n = 0 + * to 3) */ + + struct + { + __IM uint32_t OUTERRCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Frame + * Transmitted with PHY error. */ + } IFOUTERRORS_P3_b; + }; + + union + { + __IM uint32_t IFINUCASTPKTS_P3; /*!< (@ 0x00001490) Port 3 MAC Received Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Received. */ + } IFINUCASTPKTS_P3_b; + }; + + union + { + __IM uint32_t IFINMULTICASTPKTS_P3; /*!< (@ 0x00001494) Port 3 MAC Received Multicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Received. */ + } IFINMULTICASTPKTS_P3_b; + }; + + union + { + __IM uint32_t IFINBROADCASTPKTS_P3; /*!< (@ 0x00001498) Port 3 MAC Received Broadcast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Received. */ + } IFINBROADCASTPKTS_P3_b; + }; + + union + { + __IM uint32_t IFOUTDISCARDS_P3; /*!< (@ 0x0000149C) Port 3 MAC Discarded Outbound Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t DISCOBCOUNT : 32; /*!< [31..0] Not Applicable */ + } IFOUTDISCARDS_P3_b; + }; + + union + { + __IM uint32_t IFOUTUCASTPKTS_P3; /*!< (@ 0x000014A0) Port 3 MAC Transmitted Unicast Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t TXUCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Unicast + * Frame Valid Transmitted. */ + } IFOUTUCASTPKTS_P3_b; + }; + + union + { + __IM uint32_t IFOUTMULTICASTPKTS_P3; /*!< (@ 0x000014A4) Port 3 MAC Transmitted Multicast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXMCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Multicast + * Frame Valid Transmitted. */ + } IFOUTMULTICASTPKTS_P3_b; + }; + + union + { + __IM uint32_t IFOUTBROADCASTPKTS_P3; /*!< (@ 0x000014A8) Port 3 MAC Transmitted Broadcast Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXBCASTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC Broadcast + * Frame Valid Transmitted. */ + } IFOUTBROADCASTPKTS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSDROPEVENTS_P3; /*!< (@ 0x000014AC) Port 3 MAC Dropped Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t DROPCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC RX FIFO + * Full at frame start. */ + } ETHERSTATSDROPEVENTS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSOCTETS_P3; /*!< (@ 0x000014B0) Port 3 MAC All Frame Octets Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLOCTETS : 32; /*!< [31..0] ALLOCTETS */ + } ETHERSTATSOCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS_P3; /*!< (@ 0x000014B4) Port 3 MAC All Frame Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t ALLCOUNT : 32; /*!< [31..0] ALLCOUNT */ + } ETHERSTATSPKTS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSUNDERSIZEPKTS_P3; /*!< (@ 0x000014B8) Port 3 MAC Too Short Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t TOOSHRTCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Good CRC. */ + } ETHERSTATSUNDERSIZEPKTS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSOVERSIZEPKTS_P3; /*!< (@ 0x000014BC) Port 3 MAC Too Long Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t TOOLONGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Good CRC. */ + } ETHERSTATSOVERSIZEPKTS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS64OCTETS_P3; /*!< (@ 0x000014C0) Port 3 MAC 64 Octets Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT64 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 64 bytes). */ + } ETHERSTATSPKTS64OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS65TO127OCTETS_P3; /*!< (@ 0x000014C4) Port 3 MAC 65 to 127 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT65T127 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 65 to 127 bytes). */ + } ETHERSTATSPKTS65TO127OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS128TO255OCTETS_P3; /*!< (@ 0x000014C8) Port 3 MAC 128 to 255 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT128T255 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 128 to 255 bytes). */ + } ETHERSTATSPKTS128TO255OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS256TO511OCTETS_P3; /*!< (@ 0x000014CC) Port 3 MAC 256 to 511 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT256T511 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 256 to 511 bytes). */ + } ETHERSTATSPKTS256TO511OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS512TO1023OCTETS_P3; /*!< (@ 0x000014D0) Port 3 MAC 512 to 1023 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT512T1023 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 512 to 1023 bytes). */ + } ETHERSTATSPKTS512TO1023OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1024TO1518OCTETS_P3; /*!< (@ 0x000014D4) Port 3 MAC 1024 to 1518 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1024T1518 : 32; /*!< [31..0] PORT n, this field indicates the number of MAC All Frames, + * Good and Bad (Packet Size: 1024 to 1518 bytes). */ + } ETHERSTATSPKTS1024TO1518OCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSPKTS1519TOXOCTETS_P3; /*!< (@ 0x000014D8) Port 3 MAC Over 1519 Octets Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t OCTCNT1519TX : 32; /*!< [31..0] PORT n, this field indicates the number of MAC all Frames, + * Good and Bad (Packet Size: over 1519 bytes). */ + } ETHERSTATSPKTS1519TOXOCTETS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSJABBERS_P3; /*!< (@ 0x000014DC) Port 3 MAC Jabbers Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t JABBERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Long, + * Bad CRC. */ + } ETHERSTATSJABBERS_P3_b; + }; + + union + { + __IM uint32_t ETHERSTATSFRAGMENTS_P3; /*!< (@ 0x000014E0) Port 3 MAC Fragment Frame Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t FRAGCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of MAC too Short, + * Bad CRC. */ + } ETHERSTATSFRAGMENTS_P3_b; + }; + __IM uint32_t RESERVED53; + + union + { + __IM uint32_t VLANRECEIVEDOK_P3; /*!< (@ 0x000014E8) Port 3 MAC Received VLAN Tagged Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Received. */ + } VLANRECEIVEDOK_P3_b; + }; + __IM uint32_t RESERVED54[2]; + + union + { + __IM uint32_t VLANTRANSMITTEDOK_P3; /*!< (@ 0x000014F4) Port 3 MAC Transmitted VLAN Tagged Frame Count + * Register (n = 0 to 3) */ + + struct + { + __IM uint32_t TXVLANTAGCNT : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frames + * with VLAN Tag Transmitted. */ + } VLANTRANSMITTEDOK_P3_b; + }; + + union + { + __IM uint32_t FRAMESRETRANSMITTED_P3; /*!< (@ 0x000014F8) Port 3 MAC Retransmitted Frame Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t RETXCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Transmitted + * Frames that experienced a collision and were retransmitted. */ + } FRAMESRETRANSMITTED_P3_b; + }; + __IM uint32_t RESERVED55; + + union + { + __IM uint32_t STATS_HIWORD_P3; /*!< (@ 0x00001500) Port 3 MAC Statistics Counter High Word Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t STATS_HIWORD : 32; /*!< [31..0] The latched upper 32-bit of the 64 bits MAC Statistics + * Counter Last Read */ + } STATS_HIWORD_P3_b; + }; + + union + { + __IOM uint32_t STATS_CTRL_P3; /*!< (@ 0x00001504) Port 3 MAC Statistics Control Register (n = 0 + * to 3) */ + + struct + { + __IOM uint32_t CLRALL : 1; /*!< [0..0] Self Clearing Counter Initialize Command */ + __IM uint32_t CLRBUSY : 1; /*!< [1..1] Clear in Progress Indication */ + uint32_t : 30; + } STATS_CTRL_P3_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUELO_P3; /*!< (@ 0x00001508) Port 3 MAC Statistics Clear Value Lower Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUELO : 32; /*!< [31..0] PORT n, lower 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUELO_P3_b; + }; + + union + { + __IOM uint32_t STATS_CLEAR_VALUEHI_P3; /*!< (@ 0x0000150C) Port 3 MAC Statistics Clear Value Higher Register + * (n = 0 to 3) */ + + struct + { + __IOM uint32_t STATS_CLEAR_VALUEHI : 32; /*!< [31..0] PORT n, upper 32-bit of 64 bits value loaded into all + * counters when clearing all counters with STATS_CTRL_Pn.CLRALL + * command for test purposes. These bits should be set to + * 0 normally. */ + } STATS_CLEAR_VALUEHI_P3_b; + }; + + union + { + __IM uint32_t ADEFERRED_P3; /*!< (@ 0x00001510) Port 3 MAC Deferred Count Register (n = 0 to + * 3) */ + + struct + { + __IM uint32_t DEFERCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frame Transmitted + * without collision but was deferred at begin. */ + } ADEFERRED_P3_b; + }; + + union + { + __IM uint32_t AMULTIPLECOLLISIONS_P3; /*!< (@ 0x00001514) Port 3 MAC Multiple Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTMLTCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after multiple collisions. */ + } AMULTIPLECOLLISIONS_P3_b; + }; + + union + { + __IM uint32_t ASINGLECOLLISIONS_P3; /*!< (@ 0x00001518) Port 3 MAC Single Collision Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t COUNTAFTSNGLCOLL : 32; /*!< [31..0] PORT n, this field indicates the number of Good Frame + * Transmit after single collision. */ + } ASINGLECOLLISIONS_P3_b; + }; + + union + { + __IM uint32_t ALATECOLLISIONS_P3; /*!< (@ 0x0000151C) Port 3 MAC Late Collision Count Register (n = + * 0 to 3) */ + + struct + { + __IM uint32_t LATECOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of too Late + * Collision. Frame was aborted and not retransmitted. */ + } ALATECOLLISIONS_P3_b; + }; + + union + { + __IM uint32_t AEXCESSIVECOLLISIONS_P3; /*!< (@ 0x00001520) Port 3 MAC Excessive Collision Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t EXCCOLLCOUNT : 32; /*!< [31..0] PORT n, this field indicates the number of Frames Discarded + * due to 16 consecutive collisions. */ + } AEXCESSIVECOLLISIONS_P3_b; + }; + + union + { + __IM uint32_t ACARRIERSENSEERRORS_P3; /*!< (@ 0x00001524) Port 3 MAC Carrier Sense Error Count Register + * (n = 0 to 3) */ + + struct + { + __IM uint32_t CSERRCOUNT : 32; /*!< [31..0] PORT n, increments during Transmission without Collisions + * the PHY Carrier Sense Signal (RX_CRS) dropped or never + * asserted. */ + } ACARRIERSENSEERRORS_P3_b; + }; + __IM uint32_t RESERVED56[694]; + + union + { + __IOM uint32_t P0_QSTMACU0; /*!< (@ 0x00002000) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P0_QSTMACU0_b; + }; + + union + { + __IOM uint32_t P0_QSTMACD0; /*!< (@ 0x00002004) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P0_QSTMACD0_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMU0; /*!< (@ 0x00002008) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P0_QSTMAMU0_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMD0; /*!< (@ 0x0000200C) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P0_QSTMAMD0_b; + }; + + union + { + __IOM uint32_t P0_QSFTVL0; /*!< (@ 0x00002010) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P0_QSFTVL0_b; + }; + + union + { + __IOM uint32_t P0_QSFTVLM0; /*!< (@ 0x00002014) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P0_QSFTVLM0_b; + }; + + union + { + __IOM uint32_t P0_QSFTBL0; /*!< (@ 0x00002018) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P0_QSFTBL0_b; + }; + + union + { + __IM uint32_t P0_QSMFC0; /*!< (@ 0x0000201C) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P0_QSMFC0_b; + }; + + union + { + __IM uint32_t P0_QMSPPC0; /*!< (@ 0x00002020) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P0_QMSPPC0_b; + }; + + union + { + __IM uint32_t P0_QMSRPC0; /*!< (@ 0x00002024) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P0_QMSRPC0_b; + }; + + union + { + __IOM uint32_t P0_QSTMACU1; /*!< (@ 0x00002028) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P0_QSTMACU1_b; + }; + + union + { + __IOM uint32_t P0_QSTMACD1; /*!< (@ 0x0000202C) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P0_QSTMACD1_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMU1; /*!< (@ 0x00002030) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P0_QSTMAMU1_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMD1; /*!< (@ 0x00002034) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P0_QSTMAMD1_b; + }; + + union + { + __IOM uint32_t P0_QSFTVL1; /*!< (@ 0x00002038) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P0_QSFTVL1_b; + }; + + union + { + __IOM uint32_t P0_QSFTVLM1; /*!< (@ 0x0000203C) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P0_QSFTVLM1_b; + }; + + union + { + __IOM uint32_t P0_QSFTBL1; /*!< (@ 0x00002040) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P0_QSFTBL1_b; + }; + + union + { + __IM uint32_t P0_QSMFC1; /*!< (@ 0x00002044) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P0_QSMFC1_b; + }; + + union + { + __IM uint32_t P0_QMSPPC1; /*!< (@ 0x00002048) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P0_QMSPPC1_b; + }; + + union + { + __IM uint32_t P0_QMSRPC1; /*!< (@ 0x0000204C) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P0_QMSRPC1_b; + }; + + union + { + __IOM uint32_t P0_QSTMACU2; /*!< (@ 0x00002050) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P0_QSTMACU2_b; + }; + + union + { + __IOM uint32_t P0_QSTMACD2; /*!< (@ 0x00002054) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P0_QSTMACD2_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMU2; /*!< (@ 0x00002058) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P0_QSTMAMU2_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMD2; /*!< (@ 0x0000205C) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P0_QSTMAMD2_b; + }; + + union + { + __IOM uint32_t P0_QSFTVL2; /*!< (@ 0x00002060) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P0_QSFTVL2_b; + }; + + union + { + __IOM uint32_t P0_QSFTVLM2; /*!< (@ 0x00002064) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P0_QSFTVLM2_b; + }; + + union + { + __IOM uint32_t P0_QSFTBL2; /*!< (@ 0x00002068) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P0_QSFTBL2_b; + }; + + union + { + __IM uint32_t P0_QSMFC2; /*!< (@ 0x0000206C) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P0_QSMFC2_b; + }; + + union + { + __IM uint32_t P0_QMSPPC2; /*!< (@ 0x00002070) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P0_QMSPPC2_b; + }; + + union + { + __IM uint32_t P0_QMSRPC2; /*!< (@ 0x00002074) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P0_QMSRPC2_b; + }; + + union + { + __IOM uint32_t P0_QSTMACU3; /*!< (@ 0x00002078) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P0_QSTMACU3_b; + }; + + union + { + __IOM uint32_t P0_QSTMACD3; /*!< (@ 0x0000207C) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P0_QSTMACD3_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMU3; /*!< (@ 0x00002080) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P0_QSTMAMU3_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMD3; /*!< (@ 0x00002084) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P0_QSTMAMD3_b; + }; + + union + { + __IOM uint32_t P0_QSFTVL3; /*!< (@ 0x00002088) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P0_QSFTVL3_b; + }; + + union + { + __IOM uint32_t P0_QSFTVLM3; /*!< (@ 0x0000208C) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P0_QSFTVLM3_b; + }; + + union + { + __IOM uint32_t P0_QSFTBL3; /*!< (@ 0x00002090) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P0_QSFTBL3_b; + }; + + union + { + __IM uint32_t P0_QSMFC3; /*!< (@ 0x00002094) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P0_QSMFC3_b; + }; + + union + { + __IM uint32_t P0_QMSPPC3; /*!< (@ 0x00002098) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P0_QMSPPC3_b; + }; + + union + { + __IM uint32_t P0_QMSRPC3; /*!< (@ 0x0000209C) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P0_QMSRPC3_b; + }; + + union + { + __IOM uint32_t P0_QSTMACU4; /*!< (@ 0x000020A0) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P0_QSTMACU4_b; + }; + + union + { + __IOM uint32_t P0_QSTMACD4; /*!< (@ 0x000020A4) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P0_QSTMACD4_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMU4; /*!< (@ 0x000020A8) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P0_QSTMAMU4_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMD4; /*!< (@ 0x000020AC) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P0_QSTMAMD4_b; + }; + + union + { + __IOM uint32_t P0_QSFTVL4; /*!< (@ 0x000020B0) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P0_QSFTVL4_b; + }; + + union + { + __IOM uint32_t P0_QSFTVLM4; /*!< (@ 0x000020B4) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P0_QSFTVLM4_b; + }; + + union + { + __IOM uint32_t P0_QSFTBL4; /*!< (@ 0x000020B8) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P0_QSFTBL4_b; + }; + + union + { + __IM uint32_t P0_QSMFC4; /*!< (@ 0x000020BC) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P0_QSMFC4_b; + }; + + union + { + __IM uint32_t P0_QMSPPC4; /*!< (@ 0x000020C0) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P0_QMSPPC4_b; + }; + + union + { + __IM uint32_t P0_QMSRPC4; /*!< (@ 0x000020C4) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P0_QMSRPC4_b; + }; + + union + { + __IOM uint32_t P0_QSTMACU5; /*!< (@ 0x000020C8) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P0_QSTMACU5_b; + }; + + union + { + __IOM uint32_t P0_QSTMACD5; /*!< (@ 0x000020CC) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P0_QSTMACD5_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMU5; /*!< (@ 0x000020D0) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P0_QSTMAMU5_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMD5; /*!< (@ 0x000020D4) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P0_QSTMAMD5_b; + }; + + union + { + __IOM uint32_t P0_QSFTVL5; /*!< (@ 0x000020D8) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P0_QSFTVL5_b; + }; + + union + { + __IOM uint32_t P0_QSFTVLM5; /*!< (@ 0x000020DC) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P0_QSFTVLM5_b; + }; + + union + { + __IOM uint32_t P0_QSFTBL5; /*!< (@ 0x000020E0) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P0_QSFTBL5_b; + }; + + union + { + __IM uint32_t P0_QSMFC5; /*!< (@ 0x000020E4) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P0_QSMFC5_b; + }; + + union + { + __IM uint32_t P0_QMSPPC5; /*!< (@ 0x000020E8) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P0_QMSPPC5_b; + }; + + union + { + __IM uint32_t P0_QMSRPC5; /*!< (@ 0x000020EC) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P0_QMSRPC5_b; + }; + + union + { + __IOM uint32_t P0_QSTMACU6; /*!< (@ 0x000020F0) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P0_QSTMACU6_b; + }; + + union + { + __IOM uint32_t P0_QSTMACD6; /*!< (@ 0x000020F4) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P0_QSTMACD6_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMU6; /*!< (@ 0x000020F8) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P0_QSTMAMU6_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMD6; /*!< (@ 0x000020FC) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P0_QSTMAMD6_b; + }; + + union + { + __IOM uint32_t P0_QSFTVL6; /*!< (@ 0x00002100) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P0_QSFTVL6_b; + }; + + union + { + __IOM uint32_t P0_QSFTVLM6; /*!< (@ 0x00002104) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P0_QSFTVLM6_b; + }; + + union + { + __IOM uint32_t P0_QSFTBL6; /*!< (@ 0x00002108) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P0_QSFTBL6_b; + }; + + union + { + __IM uint32_t P0_QSMFC6; /*!< (@ 0x0000210C) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P0_QSMFC6_b; + }; + + union + { + __IM uint32_t P0_QMSPPC6; /*!< (@ 0x00002110) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P0_QMSPPC6_b; + }; + + union + { + __IM uint32_t P0_QMSRPC6; /*!< (@ 0x00002114) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P0_QMSRPC6_b; + }; + + union + { + __IOM uint32_t P0_QSTMACU7; /*!< (@ 0x00002118) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P0_QSTMACU7_b; + }; + + union + { + __IOM uint32_t P0_QSTMACD7; /*!< (@ 0x0000211C) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P0_QSTMACD7_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMU7; /*!< (@ 0x00002120) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P0_QSTMAMU7_b; + }; + + union + { + __IOM uint32_t P0_QSTMAMD7; /*!< (@ 0x00002124) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P0_QSTMAMD7_b; + }; + + union + { + __IOM uint32_t P0_QSFTVL7; /*!< (@ 0x00002128) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P0_QSFTVL7_b; + }; + + union + { + __IOM uint32_t P0_QSFTVLM7; /*!< (@ 0x0000212C) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P0_QSFTVLM7_b; + }; + + union + { + __IOM uint32_t P0_QSFTBL7; /*!< (@ 0x00002130) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P0_QSFTBL7_b; + }; + + union + { + __IM uint32_t P0_QSMFC7; /*!< (@ 0x00002134) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P0_QSMFC7_b; + }; + + union + { + __IM uint32_t P0_QMSPPC7; /*!< (@ 0x00002138) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P0_QMSPPC7_b; + }; + + union + { + __IM uint32_t P0_QMSRPC7; /*!< (@ 0x0000213C) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P0_QMSRPC7_b; + }; + __IM uint32_t RESERVED57[42]; + + union + { + __IOM uint32_t P0_QSEIS; /*!< (@ 0x000021E8) Qci Stream Filter Error Interrupt Status (SDU + * Oversize) */ + + struct + { + __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s] */ + uint32_t : 24; + } P0_QSEIS_b; + }; + + union + { + __IOM uint32_t P0_QSEIE; /*!< (@ 0x000021EC) Qci Stream Filter Error Interrupt Enable */ + + struct + { + __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s] */ + uint32_t : 24; + } P0_QSEIE_b; + }; + + union + { + __OM uint32_t P0_QSEID; /*!< (@ 0x000021F0) Qci Stream Filter Error Interrupt Disable */ + + struct + { + __OM uint32_t QSMOID : 8; /*!< [7..0] MSDU oversize frames Interrupt Disable[s] */ + uint32_t : 24; + } P0_QSEID_b; + }; + __IM uint32_t RESERVED58[3]; + + union + { + __IOM uint32_t P0_QGMOD; /*!< (@ 0x00002200) Qci Gate Mode Register */ + + struct + { + __IOM uint32_t QGMOD : 8; /*!< [7..0] Flow gate mode[g] */ + uint32_t : 24; + } P0_QGMOD_b; + }; + + union + { + __IM uint32_t P0_QGPPC; /*!< (@ 0x00002204) Qci Gate (All) Passed Packet Count Port 0 */ + + struct + { + __IM uint32_t QGPPC : 16; /*!< [15..0] Qci gate passed packet count */ + uint32_t : 16; + } P0_QGPPC_b; + }; + + union + { + __IM uint32_t P0_QGDPC0; /*!< (@ 0x00002208) Qci Gate 0 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P0_QGDPC0_b; + }; + __IM uint32_t RESERVED59; + + union + { + __IM uint32_t P0_QGDPC1; /*!< (@ 0x00002210) Qci Gate 1 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P0_QGDPC1_b; + }; + __IM uint32_t RESERVED60; + + union + { + __IM uint32_t P0_QGDPC2; /*!< (@ 0x00002218) Qci Gate 2 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P0_QGDPC2_b; + }; + __IM uint32_t RESERVED61; + + union + { + __IM uint32_t P0_QGDPC3; /*!< (@ 0x00002220) Qci Gate 3 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P0_QGDPC3_b; + }; + __IM uint32_t RESERVED62; + + union + { + __IM uint32_t P0_QGDPC4; /*!< (@ 0x00002228) Qci Gate 4 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P0_QGDPC4_b; + }; + __IM uint32_t RESERVED63; + + union + { + __IM uint32_t P0_QGDPC5; /*!< (@ 0x00002230) Qci Gate 5 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P0_QGDPC5_b; + }; + __IM uint32_t RESERVED64; + + union + { + __IM uint32_t P0_QGDPC6; /*!< (@ 0x00002238) Qci Gate 6 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P0_QGDPC6_b; + }; + __IM uint32_t RESERVED65; + + union + { + __IM uint32_t P0_QGDPC7; /*!< (@ 0x00002240) Qci Gate 7 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P0_QGDPC7_b; + }; + + union + { + __IOM uint32_t P0_QGEIS; /*!< (@ 0x00002244) Qci Gate Error Interrupt Status */ + + struct + { + __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g] */ + uint32_t : 24; + } P0_QGEIS_b; + }; + + union + { + __IOM uint32_t P0_QGEIE; /*!< (@ 0x00002248) Qci Gate Error Interrupt Enable */ + + struct + { + __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g] */ + uint32_t : 24; + } P0_QGEIE_b; + }; + + union + { + __OM uint32_t P0_QGEID; /*!< (@ 0x0000224C) Qci Gate Error Interrupt Disable */ + + struct + { + __OM uint32_t QGMOID : 8; /*!< [7..0] Gating error Interrupt Disable[g] */ + uint32_t : 24; + } P0_QGEID_b; + }; + + union + { + __IOM uint32_t P0_QMDESC0; /*!< (@ 0x00002250) Qci Port n Flow Meter 0 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P0_QMDESC0_b; + }; + + union + { + __IOM uint32_t P0_QMCBSC0; /*!< (@ 0x00002254) Qci Meter CBS Configuration Port n, Meter 0 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P0_QMCBSC0_b; + }; + + union + { + __IOM uint32_t P0_QMCIRC0; /*!< (@ 0x00002258) Qci Meter CIR Configuration n 0 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P0_QMCIRC0_b; + }; + + union + { + __IM uint32_t P0_QMGPC0; /*!< (@ 0x0000225C) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P0_QMGPC0_b; + }; + + union + { + __IM uint32_t P0_QMRPC0; /*!< (@ 0x00002260) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P0_QMRPC0_b; + }; + + union + { + __IOM uint32_t P0_QMDESC1; /*!< (@ 0x00002264) Qci Port n Flow Meter 1 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P0_QMDESC1_b; + }; + + union + { + __IOM uint32_t P0_QMCBSC1; /*!< (@ 0x00002268) Qci Meter CBS Configuration Port n, Meter 1 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P0_QMCBSC1_b; + }; + + union + { + __IOM uint32_t P0_QMCIRC1; /*!< (@ 0x0000226C) Qci Meter CIR Configuration n 1 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P0_QMCIRC1_b; + }; + + union + { + __IM uint32_t P0_QMGPC1; /*!< (@ 0x00002270) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P0_QMGPC1_b; + }; + + union + { + __IM uint32_t P0_QMRPC1; /*!< (@ 0x00002274) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P0_QMRPC1_b; + }; + + union + { + __IOM uint32_t P0_QMDESC2; /*!< (@ 0x00002278) Qci Port n Flow Meter 2 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P0_QMDESC2_b; + }; + + union + { + __IOM uint32_t P0_QMCBSC2; /*!< (@ 0x0000227C) Qci Meter CBS Configuration Port n, Meter 2 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P0_QMCBSC2_b; + }; + + union + { + __IOM uint32_t P0_QMCIRC2; /*!< (@ 0x00002280) Qci Meter CIR Configuration n 2 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P0_QMCIRC2_b; + }; + + union + { + __IM uint32_t P0_QMGPC2; /*!< (@ 0x00002284) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P0_QMGPC2_b; + }; + + union + { + __IM uint32_t P0_QMRPC2; /*!< (@ 0x00002288) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P0_QMRPC2_b; + }; + + union + { + __IOM uint32_t P0_QMDESC3; /*!< (@ 0x0000228C) Qci Port n Flow Meter 3 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P0_QMDESC3_b; + }; + + union + { + __IOM uint32_t P0_QMCBSC3; /*!< (@ 0x00002290) Qci Meter CBS Configuration Port n, Meter 3 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P0_QMCBSC3_b; + }; + + union + { + __IOM uint32_t P0_QMCIRC3; /*!< (@ 0x00002294) Qci Meter CIR Configuration n 3 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P0_QMCIRC3_b; + }; + + union + { + __IM uint32_t P0_QMGPC3; /*!< (@ 0x00002298) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P0_QMGPC3_b; + }; + + union + { + __IM uint32_t P0_QMRPC3; /*!< (@ 0x0000229C) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P0_QMRPC3_b; + }; + + union + { + __IOM uint32_t P0_QMDESC4; /*!< (@ 0x000022A0) Qci Port n Flow Meter 4 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P0_QMDESC4_b; + }; + + union + { + __IOM uint32_t P0_QMCBSC4; /*!< (@ 0x000022A4) Qci Meter CBS Configuration Port n, Meter 4 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P0_QMCBSC4_b; + }; + + union + { + __IOM uint32_t P0_QMCIRC4; /*!< (@ 0x000022A8) Qci Meter CIR Configuration n 4 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P0_QMCIRC4_b; + }; + + union + { + __IM uint32_t P0_QMGPC4; /*!< (@ 0x000022AC) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P0_QMGPC4_b; + }; + + union + { + __IM uint32_t P0_QMRPC4; /*!< (@ 0x000022B0) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P0_QMRPC4_b; + }; + + union + { + __IOM uint32_t P0_QMDESC5; /*!< (@ 0x000022B4) Qci Port n Flow Meter 5 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P0_QMDESC5_b; + }; + + union + { + __IOM uint32_t P0_QMCBSC5; /*!< (@ 0x000022B8) Qci Meter CBS Configuration Port n, Meter 5 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P0_QMCBSC5_b; + }; + + union + { + __IOM uint32_t P0_QMCIRC5; /*!< (@ 0x000022BC) Qci Meter CIR Configuration n 5 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P0_QMCIRC5_b; + }; + + union + { + __IM uint32_t P0_QMGPC5; /*!< (@ 0x000022C0) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P0_QMGPC5_b; + }; + + union + { + __IM uint32_t P0_QMRPC5; /*!< (@ 0x000022C4) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P0_QMRPC5_b; + }; + + union + { + __IOM uint32_t P0_QMDESC6; /*!< (@ 0x000022C8) Qci Port n Flow Meter 6 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P0_QMDESC6_b; + }; + + union + { + __IOM uint32_t P0_QMCBSC6; /*!< (@ 0x000022CC) Qci Meter CBS Configuration Port n, Meter 6 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P0_QMCBSC6_b; + }; + + union + { + __IOM uint32_t P0_QMCIRC6; /*!< (@ 0x000022D0) Qci Meter CIR Configuration n 6 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P0_QMCIRC6_b; + }; + + union + { + __IM uint32_t P0_QMGPC6; /*!< (@ 0x000022D4) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P0_QMGPC6_b; + }; + + union + { + __IM uint32_t P0_QMRPC6; /*!< (@ 0x000022D8) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P0_QMRPC6_b; + }; + + union + { + __IOM uint32_t P0_QMDESC7; /*!< (@ 0x000022DC) Qci Port n Flow Meter 7 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P0_QMDESC7_b; + }; + + union + { + __IOM uint32_t P0_QMCBSC7; /*!< (@ 0x000022E0) Qci Meter CBS Configuration Port n, Meter 7 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P0_QMCBSC7_b; + }; + + union + { + __IOM uint32_t P0_QMCIRC7; /*!< (@ 0x000022E4) Qci Meter CIR Configuration n 7 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P0_QMCIRC7_b; + }; + + union + { + __IM uint32_t P0_QMGPC7; /*!< (@ 0x000022E8) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P0_QMGPC7_b; + }; + + union + { + __IM uint32_t P0_QMRPC7; /*!< (@ 0x000022EC) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P0_QMRPC7_b; + }; + + union + { + __IOM uint32_t P0_QMEC; /*!< (@ 0x000022F0) Qci Meter Enable Configuration */ + + struct + { + __IOM uint32_t ME : 8; /*!< [7..0] Enable meter[m] */ + uint32_t : 24; + } P0_QMEC_b; + }; + + union + { + __IOM uint32_t P0_QMEIS; /*!< (@ 0x000022F4) Qci Meter Error Interrupt Status */ + + struct + { + __IOM uint32_t QRFIS : 8; /*!< [7..0] Red frames Interrupt status[m] */ + uint32_t : 24; + } P0_QMEIS_b; + }; + + union + { + __IOM uint32_t P0_QMEIE; /*!< (@ 0x000022F8) Qci Meter Error Interrupt Enable */ + + struct + { + __IOM uint32_t QRFIE : 8; /*!< [7..0] Red frames Interrupt Enable[m] */ + uint32_t : 24; + } P0_QMEIE_b; + }; + + union + { + __OM uint32_t P0_QMEID; /*!< (@ 0x000022FC) Qci Meter Error Interrupt Disable */ + + struct + { + __OM uint32_t QRFID : 8; /*!< [7..0] Red frames Interrupt Disable[m] */ + uint32_t : 24; + } P0_QMEID_b; + }; + + union + { + __IOM uint32_t P0_PCP_REMAP; /*!< (@ 0x00002300) Port 0 VLAN Priority Code Point (PCP) Remap */ + + struct + { + __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0 */ + __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1 */ + __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2 */ + __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3 */ + __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4 */ + __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5 */ + __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6 */ + __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7 */ + uint32_t : 8; + } P0_PCP_REMAP_b; + }; + + union + { + __IOM uint32_t P0_VLAN_TAG; /*!< (@ 0x00002304) Port 0 VLAN TAG Information for Priority Regeneration */ + + struct + { + __IOM uint32_t VID : 12; /*!< [11..0] VID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TPID : 16; /*!< [31..16] TPID */ + } P0_VLAN_TAG_b; + }; + + union + { + __IOM uint32_t P0_VLAN_MODE; /*!< (@ 0x00002308) Port 0 VLAN Mode */ + + struct + { + __IOM uint32_t VITM : 2; /*!< [1..0] VLAN input tagging mode */ + __IOM uint32_t VICM : 2; /*!< [3..2] VLAN input verification mode */ + uint32_t : 28; + } P0_VLAN_MODE_b; + }; + + union + { + __IM uint32_t P0_VIC_DROP_CNT; /*!< (@ 0x0000230C) Port 0 VLAN Ingress Check Drop Frame Counter */ + + struct + { + __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count */ + uint32_t : 16; + } P0_VIC_DROP_CNT_b; + }; + __IM uint32_t RESERVED66[6]; + + union + { + __IM uint32_t P0_LOOKUP_HIT_CNT; /*!< (@ 0x00002328) Port 0 DST Address Lookup Hit Counter */ + + struct + { + __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count */ + uint32_t : 8; + } P0_LOOKUP_HIT_CNT_b; + }; + + union + { + __IOM uint32_t P0_ERROR_STATUS; /*!< (@ 0x0000232C) Port 0 Frame Parser Runtime Error Status */ + + struct + { + __IOM uint32_t SOPERR : 1; /*!< [0..0] SOP error detected in frame parser */ + __IOM uint32_t PUNDSZ : 1; /*!< [1..1] Preemptable frame under size error detected in frame + * parser */ + __IOM uint32_t POVRSZ : 1; /*!< [2..2] Preemptable frame over size error detected in frame parser */ + __IOM uint32_t EUNDSZ : 1; /*!< [3..3] Express frame under size error detected in frame parser */ + __IOM uint32_t EOVRSZ : 1; /*!< [4..4] Express frame over size error detected in frame parser */ + uint32_t : 27; + } P0_ERROR_STATUS_b; + }; + + union + { + __IOM uint32_t P0_ERROR_MASK; /*!< (@ 0x00002330) Port 0 Frame Parser Runtime Error Mask */ + + struct + { + __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error) */ + __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error) */ + __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error) */ + __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error) */ + __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error) */ + uint32_t : 27; + } P0_ERROR_MASK_b; + }; + __IM uint32_t RESERVED67[35]; + + union + { + __IM uint32_t CHANNEL_STATE; /*!< (@ 0x000023C0) Enable/Disable State of Ingress Channels */ + + struct + { + __IM uint32_t CH0ACT : 1; /*!< [0..0] CH0ACT */ + __IM uint32_t CH1ACT : 1; /*!< [1..1] CH1ACT */ + __IM uint32_t CH2ACT : 1; /*!< [2..2] CH2ACT */ + uint32_t : 29; + } CHANNEL_STATE_b; + }; + + union + { + __OM uint32_t CHANNEL_ENABLE; /*!< (@ 0x000023C4) Enable Operation of Channel */ + + struct + { + __OM uint32_t CH0ENA : 1; /*!< [0..0] CH0ENA */ + __OM uint32_t CH1ENA : 1; /*!< [1..1] CH1ENA */ + __OM uint32_t CH2ENA : 1; /*!< [2..2] CH2ENA */ + uint32_t : 29; + } CHANNEL_ENABLE_b; + }; + + union + { + __OM uint32_t CHANNEL_DISABLE; /*!< (@ 0x000023C8) Disable and Reset Operation of Channel */ + + struct + { + __OM uint32_t CH0DIS : 1; /*!< [0..0] CH0DIS */ + __OM uint32_t CH1DIS : 1; /*!< [1..1] CH1DIS */ + __OM uint32_t CH2DIS : 1; /*!< [2..2] CH2DIS */ + uint32_t : 29; + } CHANNEL_DISABLE_b; + }; + + union + { + __IOM uint32_t ASI_MEM_WDATA[4]; /*!< (@ 0x000023CC) Memory Write Data Word [0..3] */ + + struct + { + __IOM uint32_t WDATA : 32; /*!< [31..0] Destination MAC address regeneration write data */ + } ASI_MEM_WDATA_b[4]; + }; + + union + { + __IOM uint32_t ASI_MEM_ADDR; /*!< (@ 0x000023DC) Memory Address and R/W Control */ + + struct + { + __IOM uint32_t ADDR : 7; /*!< [6..0] Memory access address */ + __IOM uint32_t MEM_WEN : 1; /*!< [7..7] MEM_WEN */ + __IOM uint32_t MEM_REQ : 3; /*!< [10..8] Memory access request */ + uint32_t : 21; + } ASI_MEM_ADDR_b; + }; + + union + { + __IM uint32_t ASI_MEM_RDATA[4]; /*!< (@ 0x000023E0) Memory Read Data Word [0..3] */ + + struct + { + __IM uint32_t RDATA : 32; /*!< [31..0] Destination MAC address regeneration read data */ + } ASI_MEM_RDATA_b[4]; + }; + __IM uint32_t RESERVED68[4]; + + union + { + __IOM uint32_t P1_QSTMACU0; /*!< (@ 0x00002400) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P1_QSTMACU0_b; + }; + + union + { + __IOM uint32_t P1_QSTMACD0; /*!< (@ 0x00002404) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P1_QSTMACD0_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMU0; /*!< (@ 0x00002408) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P1_QSTMAMU0_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMD0; /*!< (@ 0x0000240C) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P1_QSTMAMD0_b; + }; + + union + { + __IOM uint32_t P1_QSFTVL0; /*!< (@ 0x00002410) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P1_QSFTVL0_b; + }; + + union + { + __IOM uint32_t P1_QSFTVLM0; /*!< (@ 0x00002414) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P1_QSFTVLM0_b; + }; + + union + { + __IOM uint32_t P1_QSFTBL0; /*!< (@ 0x00002418) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P1_QSFTBL0_b; + }; + + union + { + __IM uint32_t P1_QSMFC0; /*!< (@ 0x0000241C) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P1_QSMFC0_b; + }; + + union + { + __IM uint32_t P1_QMSPPC0; /*!< (@ 0x00002420) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P1_QMSPPC0_b; + }; + + union + { + __IM uint32_t P1_QMSRPC0; /*!< (@ 0x00002424) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P1_QMSRPC0_b; + }; + + union + { + __IOM uint32_t P1_QSTMACU1; /*!< (@ 0x00002428) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P1_QSTMACU1_b; + }; + + union + { + __IOM uint32_t P1_QSTMACD1; /*!< (@ 0x0000242C) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P1_QSTMACD1_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMU1; /*!< (@ 0x00002430) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P1_QSTMAMU1_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMD1; /*!< (@ 0x00002434) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P1_QSTMAMD1_b; + }; + + union + { + __IOM uint32_t P1_QSFTVL1; /*!< (@ 0x00002438) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P1_QSFTVL1_b; + }; + + union + { + __IOM uint32_t P1_QSFTVLM1; /*!< (@ 0x0000243C) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P1_QSFTVLM1_b; + }; + + union + { + __IOM uint32_t P1_QSFTBL1; /*!< (@ 0x00002440) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P1_QSFTBL1_b; + }; + + union + { + __IM uint32_t P1_QSMFC1; /*!< (@ 0x00002444) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P1_QSMFC1_b; + }; + + union + { + __IM uint32_t P1_QMSPPC1; /*!< (@ 0x00002448) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P1_QMSPPC1_b; + }; + + union + { + __IM uint32_t P1_QMSRPC1; /*!< (@ 0x0000244C) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P1_QMSRPC1_b; + }; + + union + { + __IOM uint32_t P1_QSTMACU2; /*!< (@ 0x00002450) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P1_QSTMACU2_b; + }; + + union + { + __IOM uint32_t P1_QSTMACD2; /*!< (@ 0x00002454) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P1_QSTMACD2_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMU2; /*!< (@ 0x00002458) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P1_QSTMAMU2_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMD2; /*!< (@ 0x0000245C) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P1_QSTMAMD2_b; + }; + + union + { + __IOM uint32_t P1_QSFTVL2; /*!< (@ 0x00002460) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P1_QSFTVL2_b; + }; + + union + { + __IOM uint32_t P1_QSFTVLM2; /*!< (@ 0x00002464) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P1_QSFTVLM2_b; + }; + + union + { + __IOM uint32_t P1_QSFTBL2; /*!< (@ 0x00002468) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P1_QSFTBL2_b; + }; + + union + { + __IM uint32_t P1_QSMFC2; /*!< (@ 0x0000246C) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P1_QSMFC2_b; + }; + + union + { + __IM uint32_t P1_QMSPPC2; /*!< (@ 0x00002470) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P1_QMSPPC2_b; + }; + + union + { + __IM uint32_t P1_QMSRPC2; /*!< (@ 0x00002474) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P1_QMSRPC2_b; + }; + + union + { + __IOM uint32_t P1_QSTMACU3; /*!< (@ 0x00002478) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P1_QSTMACU3_b; + }; + + union + { + __IOM uint32_t P1_QSTMACD3; /*!< (@ 0x0000247C) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P1_QSTMACD3_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMU3; /*!< (@ 0x00002480) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P1_QSTMAMU3_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMD3; /*!< (@ 0x00002484) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P1_QSTMAMD3_b; + }; + + union + { + __IOM uint32_t P1_QSFTVL3; /*!< (@ 0x00002488) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P1_QSFTVL3_b; + }; + + union + { + __IOM uint32_t P1_QSFTVLM3; /*!< (@ 0x0000248C) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P1_QSFTVLM3_b; + }; + + union + { + __IOM uint32_t P1_QSFTBL3; /*!< (@ 0x00002490) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P1_QSFTBL3_b; + }; + + union + { + __IM uint32_t P1_QSMFC3; /*!< (@ 0x00002494) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P1_QSMFC3_b; + }; + + union + { + __IM uint32_t P1_QMSPPC3; /*!< (@ 0x00002498) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P1_QMSPPC3_b; + }; + + union + { + __IM uint32_t P1_QMSRPC3; /*!< (@ 0x0000249C) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P1_QMSRPC3_b; + }; + + union + { + __IOM uint32_t P1_QSTMACU4; /*!< (@ 0x000024A0) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P1_QSTMACU4_b; + }; + + union + { + __IOM uint32_t P1_QSTMACD4; /*!< (@ 0x000024A4) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P1_QSTMACD4_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMU4; /*!< (@ 0x000024A8) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P1_QSTMAMU4_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMD4; /*!< (@ 0x000024AC) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P1_QSTMAMD4_b; + }; + + union + { + __IOM uint32_t P1_QSFTVL4; /*!< (@ 0x000024B0) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P1_QSFTVL4_b; + }; + + union + { + __IOM uint32_t P1_QSFTVLM4; /*!< (@ 0x000024B4) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P1_QSFTVLM4_b; + }; + + union + { + __IOM uint32_t P1_QSFTBL4; /*!< (@ 0x000024B8) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P1_QSFTBL4_b; + }; + + union + { + __IM uint32_t P1_QSMFC4; /*!< (@ 0x000024BC) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P1_QSMFC4_b; + }; + + union + { + __IM uint32_t P1_QMSPPC4; /*!< (@ 0x000024C0) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P1_QMSPPC4_b; + }; + + union + { + __IM uint32_t P1_QMSRPC4; /*!< (@ 0x000024C4) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P1_QMSRPC4_b; + }; + + union + { + __IOM uint32_t P1_QSTMACU5; /*!< (@ 0x000024C8) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P1_QSTMACU5_b; + }; + + union + { + __IOM uint32_t P1_QSTMACD5; /*!< (@ 0x000024CC) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P1_QSTMACD5_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMU5; /*!< (@ 0x000024D0) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P1_QSTMAMU5_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMD5; /*!< (@ 0x000024D4) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P1_QSTMAMD5_b; + }; + + union + { + __IOM uint32_t P1_QSFTVL5; /*!< (@ 0x000024D8) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P1_QSFTVL5_b; + }; + + union + { + __IOM uint32_t P1_QSFTVLM5; /*!< (@ 0x000024DC) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P1_QSFTVLM5_b; + }; + + union + { + __IOM uint32_t P1_QSFTBL5; /*!< (@ 0x000024E0) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P1_QSFTBL5_b; + }; + + union + { + __IM uint32_t P1_QSMFC5; /*!< (@ 0x000024E4) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P1_QSMFC5_b; + }; + + union + { + __IM uint32_t P1_QMSPPC5; /*!< (@ 0x000024E8) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P1_QMSPPC5_b; + }; + + union + { + __IM uint32_t P1_QMSRPC5; /*!< (@ 0x000024EC) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P1_QMSRPC5_b; + }; + + union + { + __IOM uint32_t P1_QSTMACU6; /*!< (@ 0x000024F0) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P1_QSTMACU6_b; + }; + + union + { + __IOM uint32_t P1_QSTMACD6; /*!< (@ 0x000024F4) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P1_QSTMACD6_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMU6; /*!< (@ 0x000024F8) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P1_QSTMAMU6_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMD6; /*!< (@ 0x000024FC) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P1_QSTMAMD6_b; + }; + + union + { + __IOM uint32_t P1_QSFTVL6; /*!< (@ 0x00002500) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P1_QSFTVL6_b; + }; + + union + { + __IOM uint32_t P1_QSFTVLM6; /*!< (@ 0x00002504) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P1_QSFTVLM6_b; + }; + + union + { + __IOM uint32_t P1_QSFTBL6; /*!< (@ 0x00002508) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P1_QSFTBL6_b; + }; + + union + { + __IM uint32_t P1_QSMFC6; /*!< (@ 0x0000250C) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P1_QSMFC6_b; + }; + + union + { + __IM uint32_t P1_QMSPPC6; /*!< (@ 0x00002510) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P1_QMSPPC6_b; + }; + + union + { + __IM uint32_t P1_QMSRPC6; /*!< (@ 0x00002514) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P1_QMSRPC6_b; + }; + + union + { + __IOM uint32_t P1_QSTMACU7; /*!< (@ 0x00002518) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P1_QSTMACU7_b; + }; + + union + { + __IOM uint32_t P1_QSTMACD7; /*!< (@ 0x0000251C) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P1_QSTMACD7_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMU7; /*!< (@ 0x00002520) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P1_QSTMAMU7_b; + }; + + union + { + __IOM uint32_t P1_QSTMAMD7; /*!< (@ 0x00002524) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P1_QSTMAMD7_b; + }; + + union + { + __IOM uint32_t P1_QSFTVL7; /*!< (@ 0x00002528) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P1_QSFTVL7_b; + }; + + union + { + __IOM uint32_t P1_QSFTVLM7; /*!< (@ 0x0000252C) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P1_QSFTVLM7_b; + }; + + union + { + __IOM uint32_t P1_QSFTBL7; /*!< (@ 0x00002530) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P1_QSFTBL7_b; + }; + + union + { + __IM uint32_t P1_QSMFC7; /*!< (@ 0x00002534) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P1_QSMFC7_b; + }; + + union + { + __IM uint32_t P1_QMSPPC7; /*!< (@ 0x00002538) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P1_QMSPPC7_b; + }; + + union + { + __IM uint32_t P1_QMSRPC7; /*!< (@ 0x0000253C) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P1_QMSRPC7_b; + }; + __IM uint32_t RESERVED69[42]; + + union + { + __IOM uint32_t P1_QSEIS; /*!< (@ 0x000025E8) Qci Stream Filter Error Interrupt Status (SDU + * Oversize) */ + + struct + { + __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s] */ + uint32_t : 24; + } P1_QSEIS_b; + }; + + union + { + __IOM uint32_t P1_QSEIE; /*!< (@ 0x000025EC) Qci Stream Filter Error Interrupt Enable */ + + struct + { + __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s] */ + uint32_t : 24; + } P1_QSEIE_b; + }; + + union + { + __OM uint32_t P1_QSEID; /*!< (@ 0x000025F0) Qci Stream Filter Error Interrupt Disable */ + + struct + { + __OM uint32_t QSMOID : 8; /*!< [7..0] MSDU oversize frames Interrupt Disable[s] */ + uint32_t : 24; + } P1_QSEID_b; + }; + __IM uint32_t RESERVED70[3]; + + union + { + __IOM uint32_t P1_QGMOD; /*!< (@ 0x00002600) Qci Gate Mode Register */ + + struct + { + __IOM uint32_t QGMOD : 8; /*!< [7..0] Flow gate mode[g] */ + uint32_t : 24; + } P1_QGMOD_b; + }; + + union + { + __IM uint32_t P1_QGPPC; /*!< (@ 0x00002604) Qci Gate (All) Passed Packet Count Port 1 */ + + struct + { + __IM uint32_t QGPPC : 16; /*!< [15..0] Qci gate passed packet count */ + uint32_t : 16; + } P1_QGPPC_b; + }; + + union + { + __IM uint32_t P1_QGDPC0; /*!< (@ 0x00002608) Qci Gate 0 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P1_QGDPC0_b; + }; + __IM uint32_t RESERVED71; + + union + { + __IM uint32_t P1_QGDPC1; /*!< (@ 0x00002610) Qci Gate 1 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P1_QGDPC1_b; + }; + __IM uint32_t RESERVED72; + + union + { + __IM uint32_t P1_QGDPC2; /*!< (@ 0x00002618) Qci Gate 2 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P1_QGDPC2_b; + }; + __IM uint32_t RESERVED73; + + union + { + __IM uint32_t P1_QGDPC3; /*!< (@ 0x00002620) Qci Gate 3 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P1_QGDPC3_b; + }; + __IM uint32_t RESERVED74; + + union + { + __IM uint32_t P1_QGDPC4; /*!< (@ 0x00002628) Qci Gate 4 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P1_QGDPC4_b; + }; + __IM uint32_t RESERVED75; + + union + { + __IM uint32_t P1_QGDPC5; /*!< (@ 0x00002630) Qci Gate 5 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P1_QGDPC5_b; + }; + __IM uint32_t RESERVED76; + + union + { + __IM uint32_t P1_QGDPC6; /*!< (@ 0x00002638) Qci Gate 6 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P1_QGDPC6_b; + }; + __IM uint32_t RESERVED77; + + union + { + __IM uint32_t P1_QGDPC7; /*!< (@ 0x00002640) Qci Gate 7 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P1_QGDPC7_b; + }; + + union + { + __IOM uint32_t P1_QGEIS; /*!< (@ 0x00002644) Qci Gate Error Interrupt Status */ + + struct + { + __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g] */ + uint32_t : 24; + } P1_QGEIS_b; + }; + + union + { + __IOM uint32_t P1_QGEIE; /*!< (@ 0x00002648) Qci Gate Error Interrupt Enable */ + + struct + { + __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g] */ + uint32_t : 24; + } P1_QGEIE_b; + }; + + union + { + __OM uint32_t P1_QGEID; /*!< (@ 0x0000264C) Qci Gate Error Interrupt Disable */ + + struct + { + __OM uint32_t QGMOID : 8; /*!< [7..0] Gating error Interrupt Disable[g] */ + uint32_t : 24; + } P1_QGEID_b; + }; + + union + { + __IOM uint32_t P1_QMDESC0; /*!< (@ 0x00002650) Qci Port n Flow Meter 0 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P1_QMDESC0_b; + }; + + union + { + __IOM uint32_t P1_QMCBSC0; /*!< (@ 0x00002654) Qci Meter CBS Configuration Port n, Meter 0 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P1_QMCBSC0_b; + }; + + union + { + __IOM uint32_t P1_QMCIRC0; /*!< (@ 0x00002658) Qci Meter CIR Configuration n 0 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P1_QMCIRC0_b; + }; + + union + { + __IM uint32_t P1_QMGPC0; /*!< (@ 0x0000265C) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P1_QMGPC0_b; + }; + + union + { + __IM uint32_t P1_QMRPC0; /*!< (@ 0x00002660) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P1_QMRPC0_b; + }; + + union + { + __IOM uint32_t P1_QMDESC1; /*!< (@ 0x00002664) Qci Port n Flow Meter 1 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P1_QMDESC1_b; + }; + + union + { + __IOM uint32_t P1_QMCBSC1; /*!< (@ 0x00002668) Qci Meter CBS Configuration Port n, Meter 1 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P1_QMCBSC1_b; + }; + + union + { + __IOM uint32_t P1_QMCIRC1; /*!< (@ 0x0000266C) Qci Meter CIR Configuration n 1 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P1_QMCIRC1_b; + }; + + union + { + __IM uint32_t P1_QMGPC1; /*!< (@ 0x00002670) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P1_QMGPC1_b; + }; + + union + { + __IM uint32_t P1_QMRPC1; /*!< (@ 0x00002674) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P1_QMRPC1_b; + }; + + union + { + __IOM uint32_t P1_QMDESC2; /*!< (@ 0x00002678) Qci Port n Flow Meter 2 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P1_QMDESC2_b; + }; + + union + { + __IOM uint32_t P1_QMCBSC2; /*!< (@ 0x0000267C) Qci Meter CBS Configuration Port n, Meter 2 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P1_QMCBSC2_b; + }; + + union + { + __IOM uint32_t P1_QMCIRC2; /*!< (@ 0x00002680) Qci Meter CIR Configuration n 2 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P1_QMCIRC2_b; + }; + + union + { + __IM uint32_t P1_QMGPC2; /*!< (@ 0x00002684) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P1_QMGPC2_b; + }; + + union + { + __IM uint32_t P1_QMRPC2; /*!< (@ 0x00002688) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P1_QMRPC2_b; + }; + + union + { + __IOM uint32_t P1_QMDESC3; /*!< (@ 0x0000268C) Qci Port n Flow Meter 3 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P1_QMDESC3_b; + }; + + union + { + __IOM uint32_t P1_QMCBSC3; /*!< (@ 0x00002690) Qci Meter CBS Configuration Port n, Meter 3 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P1_QMCBSC3_b; + }; + + union + { + __IOM uint32_t P1_QMCIRC3; /*!< (@ 0x00002694) Qci Meter CIR Configuration n 3 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P1_QMCIRC3_b; + }; + + union + { + __IM uint32_t P1_QMGPC3; /*!< (@ 0x00002698) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P1_QMGPC3_b; + }; + + union + { + __IM uint32_t P1_QMRPC3; /*!< (@ 0x0000269C) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P1_QMRPC3_b; + }; + + union + { + __IOM uint32_t P1_QMDESC4; /*!< (@ 0x000026A0) Qci Port n Flow Meter 4 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P1_QMDESC4_b; + }; + + union + { + __IOM uint32_t P1_QMCBSC4; /*!< (@ 0x000026A4) Qci Meter CBS Configuration Port n, Meter 4 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P1_QMCBSC4_b; + }; + + union + { + __IOM uint32_t P1_QMCIRC4; /*!< (@ 0x000026A8) Qci Meter CIR Configuration n 4 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P1_QMCIRC4_b; + }; + + union + { + __IM uint32_t P1_QMGPC4; /*!< (@ 0x000026AC) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P1_QMGPC4_b; + }; + + union + { + __IM uint32_t P1_QMRPC4; /*!< (@ 0x000026B0) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P1_QMRPC4_b; + }; + + union + { + __IOM uint32_t P1_QMDESC5; /*!< (@ 0x000026B4) Qci Port n Flow Meter 5 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P1_QMDESC5_b; + }; + + union + { + __IOM uint32_t P1_QMCBSC5; /*!< (@ 0x000026B8) Qci Meter CBS Configuration Port n, Meter 5 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P1_QMCBSC5_b; + }; + + union + { + __IOM uint32_t P1_QMCIRC5; /*!< (@ 0x000026BC) Qci Meter CIR Configuration n 5 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P1_QMCIRC5_b; + }; + + union + { + __IM uint32_t P1_QMGPC5; /*!< (@ 0x000026C0) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P1_QMGPC5_b; + }; + + union + { + __IM uint32_t P1_QMRPC5; /*!< (@ 0x000026C4) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P1_QMRPC5_b; + }; + + union + { + __IOM uint32_t P1_QMDESC6; /*!< (@ 0x000026C8) Qci Port n Flow Meter 6 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P1_QMDESC6_b; + }; + + union + { + __IOM uint32_t P1_QMCBSC6; /*!< (@ 0x000026CC) Qci Meter CBS Configuration Port n, Meter 6 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P1_QMCBSC6_b; + }; + + union + { + __IOM uint32_t P1_QMCIRC6; /*!< (@ 0x000026D0) Qci Meter CIR Configuration n 6 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P1_QMCIRC6_b; + }; + + union + { + __IM uint32_t P1_QMGPC6; /*!< (@ 0x000026D4) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P1_QMGPC6_b; + }; + + union + { + __IM uint32_t P1_QMRPC6; /*!< (@ 0x000026D8) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P1_QMRPC6_b; + }; + + union + { + __IOM uint32_t P1_QMDESC7; /*!< (@ 0x000026DC) Qci Port n Flow Meter 7 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P1_QMDESC7_b; + }; + + union + { + __IOM uint32_t P1_QMCBSC7; /*!< (@ 0x000026E0) Qci Meter CBS Configuration Port n, Meter 7 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P1_QMCBSC7_b; + }; + + union + { + __IOM uint32_t P1_QMCIRC7; /*!< (@ 0x000026E4) Qci Meter CIR Configuration n 7 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P1_QMCIRC7_b; + }; + + union + { + __IM uint32_t P1_QMGPC7; /*!< (@ 0x000026E8) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P1_QMGPC7_b; + }; + + union + { + __IM uint32_t P1_QMRPC7; /*!< (@ 0x000026EC) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P1_QMRPC7_b; + }; + + union + { + __IOM uint32_t P1_QMEC; /*!< (@ 0x000026F0) Qci Meter Enable Configuration */ + + struct + { + __IOM uint32_t ME : 8; /*!< [7..0] Enable meter[m] */ + uint32_t : 24; + } P1_QMEC_b; + }; + + union + { + __IOM uint32_t P1_QMEIS; /*!< (@ 0x000026F4) Qci Meter Error Interrupt Status */ + + struct + { + __IOM uint32_t QRFIS : 8; /*!< [7..0] Red frames Interrupt status[m] */ + uint32_t : 24; + } P1_QMEIS_b; + }; + + union + { + __IOM uint32_t P1_QMEIE; /*!< (@ 0x000026F8) Qci Meter Error Interrupt Enable */ + + struct + { + __IOM uint32_t QRFIE : 8; /*!< [7..0] Red frames Interrupt Enable[m] */ + uint32_t : 24; + } P1_QMEIE_b; + }; + + union + { + __OM uint32_t P1_QMEID; /*!< (@ 0x000026FC) Qci Meter Error Interrupt Disable */ + + struct + { + __OM uint32_t QRFID : 8; /*!< [7..0] Red frames Interrupt Disable[m] */ + uint32_t : 24; + } P1_QMEID_b; + }; + + union + { + __IOM uint32_t P1_PCP_REMAP; /*!< (@ 0x00002700) Port 1 VLAN Priority Code Point (PCP) Remap */ + + struct + { + __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0 */ + __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1 */ + __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2 */ + __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3 */ + __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4 */ + __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5 */ + __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6 */ + __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7 */ + uint32_t : 8; + } P1_PCP_REMAP_b; + }; + + union + { + __IOM uint32_t P1_VLAN_TAG; /*!< (@ 0x00002704) Port 1 VLAN TAG Information for Priority Regeneration */ + + struct + { + __IOM uint32_t VID : 12; /*!< [11..0] VID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TPID : 16; /*!< [31..16] TPID */ + } P1_VLAN_TAG_b; + }; + + union + { + __IOM uint32_t P1_VLAN_MODE; /*!< (@ 0x00002708) Port 1 VLAN Mode */ + + struct + { + __IOM uint32_t VITM : 2; /*!< [1..0] VLAN input tagging mode */ + __IOM uint32_t VICM : 2; /*!< [3..2] VLAN input verification mode */ + uint32_t : 28; + } P1_VLAN_MODE_b; + }; + + union + { + __IM uint32_t P1_VIC_DROP_CNT; /*!< (@ 0x0000270C) Port 1 VLAN Ingress Check Drop Frame Counter */ + + struct + { + __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count */ + uint32_t : 16; + } P1_VIC_DROP_CNT_b; + }; + __IM uint32_t RESERVED78[6]; + + union + { + __IM uint32_t P1_LOOKUP_HIT_CNT; /*!< (@ 0x00002728) Port 1 DST Address Lookup Hit Counter */ + + struct + { + __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count */ + uint32_t : 8; + } P1_LOOKUP_HIT_CNT_b; + }; + + union + { + __IOM uint32_t P1_ERROR_STATUS; /*!< (@ 0x0000272C) Port 1 Frame Parser Runtime Error Status */ + + struct + { + __IOM uint32_t SOPERR : 1; /*!< [0..0] SOP error detected in frame parser */ + __IOM uint32_t PUNDSZ : 1; /*!< [1..1] Preemptable frame under size error detected in frame + * parser */ + __IOM uint32_t POVRSZ : 1; /*!< [2..2] Preemptable frame over size error detected in frame parser */ + __IOM uint32_t EUNDSZ : 1; /*!< [3..3] Express frame under size error detected in frame parser */ + __IOM uint32_t EOVRSZ : 1; /*!< [4..4] Express frame over size error detected in frame parser */ + uint32_t : 27; + } P1_ERROR_STATUS_b; + }; + + union + { + __IOM uint32_t P1_ERROR_MASK; /*!< (@ 0x00002730) Port 1 Frame Parser Runtime Error Mask */ + + struct + { + __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error) */ + __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error) */ + __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error) */ + __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error) */ + __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error) */ + uint32_t : 27; + } P1_ERROR_MASK_b; + }; + __IM uint32_t RESERVED79[51]; + + union + { + __IOM uint32_t P2_QSTMACU0; /*!< (@ 0x00002800) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P2_QSTMACU0_b; + }; + + union + { + __IOM uint32_t P2_QSTMACD0; /*!< (@ 0x00002804) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P2_QSTMACD0_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMU0; /*!< (@ 0x00002808) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P2_QSTMAMU0_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMD0; /*!< (@ 0x0000280C) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P2_QSTMAMD0_b; + }; + + union + { + __IOM uint32_t P2_QSFTVL0; /*!< (@ 0x00002810) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P2_QSFTVL0_b; + }; + + union + { + __IOM uint32_t P2_QSFTVLM0; /*!< (@ 0x00002814) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P2_QSFTVLM0_b; + }; + + union + { + __IOM uint32_t P2_QSFTBL0; /*!< (@ 0x00002818) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P2_QSFTBL0_b; + }; + + union + { + __IM uint32_t P2_QSMFC0; /*!< (@ 0x0000281C) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P2_QSMFC0_b; + }; + + union + { + __IM uint32_t P2_QMSPPC0; /*!< (@ 0x00002820) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P2_QMSPPC0_b; + }; + + union + { + __IM uint32_t P2_QMSRPC0; /*!< (@ 0x00002824) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P2_QMSRPC0_b; + }; + + union + { + __IOM uint32_t P2_QSTMACU1; /*!< (@ 0x00002828) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P2_QSTMACU1_b; + }; + + union + { + __IOM uint32_t P2_QSTMACD1; /*!< (@ 0x0000282C) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P2_QSTMACD1_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMU1; /*!< (@ 0x00002830) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P2_QSTMAMU1_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMD1; /*!< (@ 0x00002834) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P2_QSTMAMD1_b; + }; + + union + { + __IOM uint32_t P2_QSFTVL1; /*!< (@ 0x00002838) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P2_QSFTVL1_b; + }; + + union + { + __IOM uint32_t P2_QSFTVLM1; /*!< (@ 0x0000283C) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P2_QSFTVLM1_b; + }; + + union + { + __IOM uint32_t P2_QSFTBL1; /*!< (@ 0x00002840) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P2_QSFTBL1_b; + }; + + union + { + __IM uint32_t P2_QSMFC1; /*!< (@ 0x00002844) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P2_QSMFC1_b; + }; + + union + { + __IM uint32_t P2_QMSPPC1; /*!< (@ 0x00002848) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P2_QMSPPC1_b; + }; + + union + { + __IM uint32_t P2_QMSRPC1; /*!< (@ 0x0000284C) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P2_QMSRPC1_b; + }; + + union + { + __IOM uint32_t P2_QSTMACU2; /*!< (@ 0x00002850) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P2_QSTMACU2_b; + }; + + union + { + __IOM uint32_t P2_QSTMACD2; /*!< (@ 0x00002854) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P2_QSTMACD2_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMU2; /*!< (@ 0x00002858) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P2_QSTMAMU2_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMD2; /*!< (@ 0x0000285C) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P2_QSTMAMD2_b; + }; + + union + { + __IOM uint32_t P2_QSFTVL2; /*!< (@ 0x00002860) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P2_QSFTVL2_b; + }; + + union + { + __IOM uint32_t P2_QSFTVLM2; /*!< (@ 0x00002864) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P2_QSFTVLM2_b; + }; + + union + { + __IOM uint32_t P2_QSFTBL2; /*!< (@ 0x00002868) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P2_QSFTBL2_b; + }; + + union + { + __IM uint32_t P2_QSMFC2; /*!< (@ 0x0000286C) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P2_QSMFC2_b; + }; + + union + { + __IM uint32_t P2_QMSPPC2; /*!< (@ 0x00002870) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P2_QMSPPC2_b; + }; + + union + { + __IM uint32_t P2_QMSRPC2; /*!< (@ 0x00002874) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P2_QMSRPC2_b; + }; + + union + { + __IOM uint32_t P2_QSTMACU3; /*!< (@ 0x00002878) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P2_QSTMACU3_b; + }; + + union + { + __IOM uint32_t P2_QSTMACD3; /*!< (@ 0x0000287C) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P2_QSTMACD3_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMU3; /*!< (@ 0x00002880) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P2_QSTMAMU3_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMD3; /*!< (@ 0x00002884) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P2_QSTMAMD3_b; + }; + + union + { + __IOM uint32_t P2_QSFTVL3; /*!< (@ 0x00002888) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P2_QSFTVL3_b; + }; + + union + { + __IOM uint32_t P2_QSFTVLM3; /*!< (@ 0x0000288C) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P2_QSFTVLM3_b; + }; + + union + { + __IOM uint32_t P2_QSFTBL3; /*!< (@ 0x00002890) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P2_QSFTBL3_b; + }; + + union + { + __IM uint32_t P2_QSMFC3; /*!< (@ 0x00002894) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P2_QSMFC3_b; + }; + + union + { + __IM uint32_t P2_QMSPPC3; /*!< (@ 0x00002898) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P2_QMSPPC3_b; + }; + + union + { + __IM uint32_t P2_QMSRPC3; /*!< (@ 0x0000289C) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P2_QMSRPC3_b; + }; + + union + { + __IOM uint32_t P2_QSTMACU4; /*!< (@ 0x000028A0) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P2_QSTMACU4_b; + }; + + union + { + __IOM uint32_t P2_QSTMACD4; /*!< (@ 0x000028A4) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P2_QSTMACD4_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMU4; /*!< (@ 0x000028A8) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P2_QSTMAMU4_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMD4; /*!< (@ 0x000028AC) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P2_QSTMAMD4_b; + }; + + union + { + __IOM uint32_t P2_QSFTVL4; /*!< (@ 0x000028B0) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P2_QSFTVL4_b; + }; + + union + { + __IOM uint32_t P2_QSFTVLM4; /*!< (@ 0x000028B4) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P2_QSFTVLM4_b; + }; + + union + { + __IOM uint32_t P2_QSFTBL4; /*!< (@ 0x000028B8) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P2_QSFTBL4_b; + }; + + union + { + __IM uint32_t P2_QSMFC4; /*!< (@ 0x000028BC) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P2_QSMFC4_b; + }; + + union + { + __IM uint32_t P2_QMSPPC4; /*!< (@ 0x000028C0) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P2_QMSPPC4_b; + }; + + union + { + __IM uint32_t P2_QMSRPC4; /*!< (@ 0x000028C4) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P2_QMSRPC4_b; + }; + + union + { + __IOM uint32_t P2_QSTMACU5; /*!< (@ 0x000028C8) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P2_QSTMACU5_b; + }; + + union + { + __IOM uint32_t P2_QSTMACD5; /*!< (@ 0x000028CC) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P2_QSTMACD5_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMU5; /*!< (@ 0x000028D0) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P2_QSTMAMU5_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMD5; /*!< (@ 0x000028D4) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P2_QSTMAMD5_b; + }; + + union + { + __IOM uint32_t P2_QSFTVL5; /*!< (@ 0x000028D8) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P2_QSFTVL5_b; + }; + + union + { + __IOM uint32_t P2_QSFTVLM5; /*!< (@ 0x000028DC) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P2_QSFTVLM5_b; + }; + + union + { + __IOM uint32_t P2_QSFTBL5; /*!< (@ 0x000028E0) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P2_QSFTBL5_b; + }; + + union + { + __IM uint32_t P2_QSMFC5; /*!< (@ 0x000028E4) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P2_QSMFC5_b; + }; + + union + { + __IM uint32_t P2_QMSPPC5; /*!< (@ 0x000028E8) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P2_QMSPPC5_b; + }; + + union + { + __IM uint32_t P2_QMSRPC5; /*!< (@ 0x000028EC) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P2_QMSRPC5_b; + }; + + union + { + __IOM uint32_t P2_QSTMACU6; /*!< (@ 0x000028F0) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P2_QSTMACU6_b; + }; + + union + { + __IOM uint32_t P2_QSTMACD6; /*!< (@ 0x000028F4) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P2_QSTMACD6_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMU6; /*!< (@ 0x000028F8) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P2_QSTMAMU6_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMD6; /*!< (@ 0x000028FC) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P2_QSTMAMD6_b; + }; + + union + { + __IOM uint32_t P2_QSFTVL6; /*!< (@ 0x00002900) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P2_QSFTVL6_b; + }; + + union + { + __IOM uint32_t P2_QSFTVLM6; /*!< (@ 0x00002904) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P2_QSFTVLM6_b; + }; + + union + { + __IOM uint32_t P2_QSFTBL6; /*!< (@ 0x00002908) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P2_QSFTBL6_b; + }; + + union + { + __IM uint32_t P2_QSMFC6; /*!< (@ 0x0000290C) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P2_QSMFC6_b; + }; + + union + { + __IM uint32_t P2_QMSPPC6; /*!< (@ 0x00002910) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P2_QMSPPC6_b; + }; + + union + { + __IM uint32_t P2_QMSRPC6; /*!< (@ 0x00002914) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P2_QMSRPC6_b; + }; + + union + { + __IOM uint32_t P2_QSTMACU7; /*!< (@ 0x00002918) Qci Stream Filter Table MAC Address Upper Part */ + + struct + { + __IOM uint32_t MACA : 16; /*!< [15..0] Qci stream filter table MAC address[47:32] */ + __IOM uint32_t DASA : 1; /*!< [16..16] MAC address (MACA) select */ + uint32_t : 15; + } P2_QSTMACU7_b; + }; + + union + { + __IOM uint32_t P2_QSTMACD7; /*!< (@ 0x0000291C) Qci Stream Filter Table MAC Address Downer Part */ + + struct + { + __IOM uint32_t MACA : 32; /*!< [31..0] Qci stream filter table MAC address[31:0] */ + } P2_QSTMACD7_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMU7; /*!< (@ 0x00002920) Qci Stream Filter Table MAC Address Mask Upper + * Part */ + + struct + { + __IOM uint32_t MACAM : 16; /*!< [15..0] Qci stream filter table MAC address bit mask[47:32] */ + uint32_t : 16; + } P2_QSTMAMU7_b; + }; + + union + { + __IOM uint32_t P2_QSTMAMD7; /*!< (@ 0x00002924) Qci Stream Filter Table MAC Address Mask Downer + * Part */ + + struct + { + __IOM uint32_t MACAM : 32; /*!< [31..0] Qci stream filter table MAC address bit mask[31:0] */ + } P2_QSTMAMD7_b; + }; + + union + { + __IOM uint32_t P2_QSFTVL7; /*!< (@ 0x00002928) Qci Stream Filter Table VLAN */ + + struct + { + __IOM uint32_t VLANID : 12; /*!< [11..0] VLANID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TAGMD : 2; /*!< [17..16] TAGMD */ + uint32_t : 14; + } P2_QSFTVL7_b; + }; + + union + { + __IOM uint32_t P2_QSFTVLM7; /*!< (@ 0x0000292C) Qci Stream Filter Table VLAN Mask */ + + struct + { + __IOM uint32_t VLANIDM : 12; /*!< [11..0] Qci stream filter table VLAN ID[11:0] bit mask */ + __IOM uint32_t DEIM : 1; /*!< [12..12] DEIM */ + __IOM uint32_t PCPM : 3; /*!< [15..13] Qci stream filter table VLAN PCP[2:0] bit mask */ + uint32_t : 16; + } P2_QSFTVLM7_b; + }; + + union + { + __IOM uint32_t P2_QSFTBL7; /*!< (@ 0x00002930) Qci Stream Filter Table SDU/Gate/Meter ID */ + + struct + { + __IOM uint32_t QSTE : 1; /*!< [0..0] QSTE */ + uint32_t : 3; + __IOM uint32_t GAID : 3; /*!< [6..4] GAID */ + __IOM uint32_t GAIDV : 1; /*!< [7..7] GAIDV */ + __IOM uint32_t MEID : 3; /*!< [10..8] MEID */ + uint32_t : 1; + __IOM uint32_t MEIDV : 1; /*!< [12..12] MEIDV */ + uint32_t : 3; + __IOM uint32_t MSDU : 11; /*!< [26..16] Qci stream filter table max SDU size */ + __IOM uint32_t MSDUE : 1; /*!< [27..27] MSDUE */ + __IOM uint32_t QSMSM : 1; /*!< [28..28] Qci stream MSDU mode */ + uint32_t : 3; + } P2_QSFTBL7_b; + }; + + union + { + __IM uint32_t P2_QSMFC7; /*!< (@ 0x00002934) Qci Stream Match Packet Count */ + + struct + { + __IM uint32_t QSMFC : 16; /*!< [15..0] Qci stream match packet count */ + uint32_t : 16; + } P2_QSMFC7_b; + }; + + union + { + __IM uint32_t P2_QMSPPC7; /*!< (@ 0x00002938) Qci MSDU Passed Packet Count */ + + struct + { + __IM uint32_t QMSPPC : 16; /*!< [15..0] Qci msdu passed packet count */ + uint32_t : 16; + } P2_QMSPPC7_b; + }; + + union + { + __IM uint32_t P2_QMSRPC7; /*!< (@ 0x0000293C) Qci MSDU Reject Packet Count */ + + struct + { + __IM uint32_t QMSRPC : 16; /*!< [15..0] Qci MSDU rejected packet count */ + uint32_t : 16; + } P2_QMSRPC7_b; + }; + __IM uint32_t RESERVED80[42]; + + union + { + __IOM uint32_t P2_QSEIS; /*!< (@ 0x000029E8) Qci Stream Filter Error Interrupt Status (SDU + * Oversize) */ + + struct + { + __IOM uint32_t QSMOIS : 8; /*!< [7..0] MSDU oversize frames Interrupt status[s] */ + uint32_t : 24; + } P2_QSEIS_b; + }; + + union + { + __IOM uint32_t P2_QSEIE; /*!< (@ 0x000029EC) Qci Stream Filter Error Interrupt Enable */ + + struct + { + __IOM uint32_t QSMOIE : 8; /*!< [7..0] MSDU oversize frames Interrupt Enable[s] */ + uint32_t : 24; + } P2_QSEIE_b; + }; + + union + { + __OM uint32_t P2_QSEID; /*!< (@ 0x000029F0) Qci Stream Filter Error Interrupt Disable */ + + struct + { + __OM uint32_t QSMOID : 8; /*!< [7..0] MSDU oversize frames Interrupt Disable[s] */ + uint32_t : 24; + } P2_QSEID_b; + }; + __IM uint32_t RESERVED81[3]; + + union + { + __IOM uint32_t P2_QGMOD; /*!< (@ 0x00002A00) Qci Gate Mode Register */ + + struct + { + __IOM uint32_t QGMOD : 8; /*!< [7..0] Flow gate mode[g] */ + uint32_t : 24; + } P2_QGMOD_b; + }; + + union + { + __IM uint32_t P2_QGPPC; /*!< (@ 0x00002A04) Qci Gate (All) Passed Packet Count Port 2 */ + + struct + { + __IM uint32_t QGPPC : 16; /*!< [15..0] Qci gate passed packet count */ + uint32_t : 16; + } P2_QGPPC_b; + }; + + union + { + __IM uint32_t P2_QGDPC0; /*!< (@ 0x00002A08) Qci Gate 0 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P2_QGDPC0_b; + }; + __IM uint32_t RESERVED82; + + union + { + __IM uint32_t P2_QGDPC1; /*!< (@ 0x00002A10) Qci Gate 1 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P2_QGDPC1_b; + }; + __IM uint32_t RESERVED83; + + union + { + __IM uint32_t P2_QGDPC2; /*!< (@ 0x00002A18) Qci Gate 2 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P2_QGDPC2_b; + }; + __IM uint32_t RESERVED84; + + union + { + __IM uint32_t P2_QGDPC3; /*!< (@ 0x00002A20) Qci Gate 3 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P2_QGDPC3_b; + }; + __IM uint32_t RESERVED85; + + union + { + __IM uint32_t P2_QGDPC4; /*!< (@ 0x00002A28) Qci Gate 4 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P2_QGDPC4_b; + }; + __IM uint32_t RESERVED86; + + union + { + __IM uint32_t P2_QGDPC5; /*!< (@ 0x00002A30) Qci Gate 5 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P2_QGDPC5_b; + }; + __IM uint32_t RESERVED87; + + union + { + __IM uint32_t P2_QGDPC6; /*!< (@ 0x00002A38) Qci Gate 6 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P2_QGDPC6_b; + }; + __IM uint32_t RESERVED88; + + union + { + __IM uint32_t P2_QGDPC7; /*!< (@ 0x00002A40) Qci Gate 7 Dropped Packet Count Port n */ + + struct + { + __IM uint32_t QGDPC : 16; /*!< [15..0] Qci gate dropped packet count */ + uint32_t : 16; + } P2_QGDPC7_b; + }; + + union + { + __IOM uint32_t P2_QGEIS; /*!< (@ 0x00002A44) Qci Gate Error Interrupt Status */ + + struct + { + __IOM uint32_t QGMOIS : 8; /*!< [7..0] Gating error Interrupt status[g] */ + uint32_t : 24; + } P2_QGEIS_b; + }; + + union + { + __IOM uint32_t P2_QGEIE; /*!< (@ 0x00002A48) Qci Gate Error Interrupt Enable */ + + struct + { + __IOM uint32_t QGMOIE : 8; /*!< [7..0] Gating error Interrupt Enable[g] */ + uint32_t : 24; + } P2_QGEIE_b; + }; + + union + { + __OM uint32_t P2_QGEID; /*!< (@ 0x00002A4C) Qci Gate Error Interrupt Disable */ + + struct + { + __OM uint32_t QGMOID : 8; /*!< [7..0] Gating error Interrupt Disable[g] */ + uint32_t : 24; + } P2_QGEID_b; + }; + + union + { + __IOM uint32_t P2_QMDESC0; /*!< (@ 0x00002A50) Qci Port n Flow Meter 0 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P2_QMDESC0_b; + }; + + union + { + __IOM uint32_t P2_QMCBSC0; /*!< (@ 0x00002A54) Qci Meter CBS Configuration Port n, Meter 0 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P2_QMCBSC0_b; + }; + + union + { + __IOM uint32_t P2_QMCIRC0; /*!< (@ 0x00002A58) Qci Meter CIR Configuration n 0 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P2_QMCIRC0_b; + }; + + union + { + __IM uint32_t P2_QMGPC0; /*!< (@ 0x00002A5C) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P2_QMGPC0_b; + }; + + union + { + __IM uint32_t P2_QMRPC0; /*!< (@ 0x00002A60) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P2_QMRPC0_b; + }; + + union + { + __IOM uint32_t P2_QMDESC1; /*!< (@ 0x00002A64) Qci Port n Flow Meter 1 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P2_QMDESC1_b; + }; + + union + { + __IOM uint32_t P2_QMCBSC1; /*!< (@ 0x00002A68) Qci Meter CBS Configuration Port n, Meter 1 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P2_QMCBSC1_b; + }; + + union + { + __IOM uint32_t P2_QMCIRC1; /*!< (@ 0x00002A6C) Qci Meter CIR Configuration n 1 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P2_QMCIRC1_b; + }; + + union + { + __IM uint32_t P2_QMGPC1; /*!< (@ 0x00002A70) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P2_QMGPC1_b; + }; + + union + { + __IM uint32_t P2_QMRPC1; /*!< (@ 0x00002A74) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P2_QMRPC1_b; + }; + + union + { + __IOM uint32_t P2_QMDESC2; /*!< (@ 0x00002A78) Qci Port n Flow Meter 2 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P2_QMDESC2_b; + }; + + union + { + __IOM uint32_t P2_QMCBSC2; /*!< (@ 0x00002A7C) Qci Meter CBS Configuration Port n, Meter 2 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P2_QMCBSC2_b; + }; + + union + { + __IOM uint32_t P2_QMCIRC2; /*!< (@ 0x00002A80) Qci Meter CIR Configuration n 2 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P2_QMCIRC2_b; + }; + + union + { + __IM uint32_t P2_QMGPC2; /*!< (@ 0x00002A84) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P2_QMGPC2_b; + }; + + union + { + __IM uint32_t P2_QMRPC2; /*!< (@ 0x00002A88) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P2_QMRPC2_b; + }; + + union + { + __IOM uint32_t P2_QMDESC3; /*!< (@ 0x00002A8C) Qci Port n Flow Meter 3 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P2_QMDESC3_b; + }; + + union + { + __IOM uint32_t P2_QMCBSC3; /*!< (@ 0x00002A90) Qci Meter CBS Configuration Port n, Meter 3 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P2_QMCBSC3_b; + }; + + union + { + __IOM uint32_t P2_QMCIRC3; /*!< (@ 0x00002A94) Qci Meter CIR Configuration n 3 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P2_QMCIRC3_b; + }; + + union + { + __IM uint32_t P2_QMGPC3; /*!< (@ 0x00002A98) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P2_QMGPC3_b; + }; + + union + { + __IM uint32_t P2_QMRPC3; /*!< (@ 0x00002A9C) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P2_QMRPC3_b; + }; + + union + { + __IOM uint32_t P2_QMDESC4; /*!< (@ 0x00002AA0) Qci Port n Flow Meter 4 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P2_QMDESC4_b; + }; + + union + { + __IOM uint32_t P2_QMCBSC4; /*!< (@ 0x00002AA4) Qci Meter CBS Configuration Port n, Meter 4 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P2_QMCBSC4_b; + }; + + union + { + __IOM uint32_t P2_QMCIRC4; /*!< (@ 0x00002AA8) Qci Meter CIR Configuration n 4 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P2_QMCIRC4_b; + }; + + union + { + __IM uint32_t P2_QMGPC4; /*!< (@ 0x00002AAC) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P2_QMGPC4_b; + }; + + union + { + __IM uint32_t P2_QMRPC4; /*!< (@ 0x00002AB0) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P2_QMRPC4_b; + }; + + union + { + __IOM uint32_t P2_QMDESC5; /*!< (@ 0x00002AB4) Qci Port n Flow Meter 5 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P2_QMDESC5_b; + }; + + union + { + __IOM uint32_t P2_QMCBSC5; /*!< (@ 0x00002AB8) Qci Meter CBS Configuration Port n, Meter 5 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P2_QMCBSC5_b; + }; + + union + { + __IOM uint32_t P2_QMCIRC5; /*!< (@ 0x00002ABC) Qci Meter CIR Configuration n 5 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P2_QMCIRC5_b; + }; + + union + { + __IM uint32_t P2_QMGPC5; /*!< (@ 0x00002AC0) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P2_QMGPC5_b; + }; + + union + { + __IM uint32_t P2_QMRPC5; /*!< (@ 0x00002AC4) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P2_QMRPC5_b; + }; + + union + { + __IOM uint32_t P2_QMDESC6; /*!< (@ 0x00002AC8) Qci Port n Flow Meter 6 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P2_QMDESC6_b; + }; + + union + { + __IOM uint32_t P2_QMCBSC6; /*!< (@ 0x00002ACC) Qci Meter CBS Configuration Port n, Meter 6 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P2_QMCBSC6_b; + }; + + union + { + __IOM uint32_t P2_QMCIRC6; /*!< (@ 0x00002AD0) Qci Meter CIR Configuration n 6 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P2_QMCIRC6_b; + }; + + union + { + __IM uint32_t P2_QMGPC6; /*!< (@ 0x00002AD4) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P2_QMGPC6_b; + }; + + union + { + __IM uint32_t P2_QMRPC6; /*!< (@ 0x00002AD8) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P2_QMRPC6_b; + }; + + union + { + __IOM uint32_t P2_QMDESC7; /*!< (@ 0x00002ADC) Qci Port n Flow Meter 7 Descriptor Register */ + + struct + { + __IOM uint32_t RFD : 1; /*!< [0..0] Red frame drop */ + __IOM uint32_t MM : 1; /*!< [1..1] Flow meter mode */ + __IOM uint32_t CF : 1; /*!< [2..2] Coupling flag */ + uint32_t : 29; + } P2_QMDESC7_b; + }; + + union + { + __IOM uint32_t P2_QMCBSC7; /*!< (@ 0x00002AE0) Qci Meter CBS Configuration Port n, Meter 7 */ + + struct + { + __IOM uint32_t CBS : 18; /*!< [17..0] CBS (Committed Burst Size) */ + uint32_t : 14; + } P2_QMCBSC7_b; + }; + + union + { + __IOM uint32_t P2_QMCIRC7; /*!< (@ 0x00002AE4) Qci Meter CIR Configuration n 7 */ + + struct + { + __IOM uint32_t CIR : 17; /*!< [16..0] CIR (Committed Information Rate) */ + uint32_t : 15; + } P2_QMCIRC7_b; + }; + + union + { + __IM uint32_t P2_QMGPC7; /*!< (@ 0x00002AE8) Qci Meter Green Packet Count */ + + struct + { + __IM uint32_t QMGPC : 16; /*!< [15..0] Qci meter green packet count */ + uint32_t : 16; + } P2_QMGPC7_b; + }; + + union + { + __IM uint32_t P2_QMRPC7; /*!< (@ 0x00002AEC) Qci Meter Red Packet Count */ + + struct + { + __IM uint32_t QMRPC : 16; /*!< [15..0] Qci meter red packet count */ + uint32_t : 16; + } P2_QMRPC7_b; + }; + + union + { + __IOM uint32_t P2_QMEC; /*!< (@ 0x00002AF0) Qci Meter Enable Configuration */ + + struct + { + __IOM uint32_t ME : 8; /*!< [7..0] Enable meter[m] */ + uint32_t : 24; + } P2_QMEC_b; + }; + + union + { + __IOM uint32_t P2_QMEIS; /*!< (@ 0x00002AF4) Qci Meter Error Interrupt Status */ + + struct + { + __IOM uint32_t QRFIS : 8; /*!< [7..0] Red frames Interrupt status[m] */ + uint32_t : 24; + } P2_QMEIS_b; + }; + + union + { + __IOM uint32_t P2_QMEIE; /*!< (@ 0x00002AF8) Qci Meter Error Interrupt Enable */ + + struct + { + __IOM uint32_t QRFIE : 8; /*!< [7..0] Red frames Interrupt Enable[m] */ + uint32_t : 24; + } P2_QMEIE_b; + }; + + union + { + __OM uint32_t P2_QMEID; /*!< (@ 0x00002AFC) Qci Meter Error Interrupt Disable */ + + struct + { + __OM uint32_t QRFID : 8; /*!< [7..0] Red frames Interrupt Disable[m] */ + uint32_t : 24; + } P2_QMEID_b; + }; + + union + { + __IOM uint32_t P2_PCP_REMAP; /*!< (@ 0x00002B00) Port 2 VLAN Priority Code Point (PCP) Remap */ + + struct + { + __IOM uint32_t PCP_REMAP0 : 3; /*!< [2..0] PCP_REMAP0 */ + __IOM uint32_t PCP_REMAP1 : 3; /*!< [5..3] PCP_REMAP1 */ + __IOM uint32_t PCP_REMAP2 : 3; /*!< [8..6] PCP_REMAP2 */ + __IOM uint32_t PCP_REMAP3 : 3; /*!< [11..9] PCP_REMAP3 */ + __IOM uint32_t PCP_REMAP4 : 3; /*!< [14..12] PCP_REMAP4 */ + __IOM uint32_t PCP_REMAP5 : 3; /*!< [17..15] PCP_REMAP5 */ + __IOM uint32_t PCP_REMAP6 : 3; /*!< [20..18] PCP_REMAP6 */ + __IOM uint32_t PCP_REMAP7 : 3; /*!< [23..21] PCP_REMAP7 */ + uint32_t : 8; + } P2_PCP_REMAP_b; + }; + + union + { + __IOM uint32_t P2_VLAN_TAG; /*!< (@ 0x00002B04) Port 2 VLAN TAG Information for Priority Regeneration */ + + struct + { + __IOM uint32_t VID : 12; /*!< [11..0] VID */ + __IOM uint32_t DEI : 1; /*!< [12..12] DEI */ + __IOM uint32_t PCP : 3; /*!< [15..13] PCP */ + __IOM uint32_t TPID : 16; /*!< [31..16] TPID */ + } P2_VLAN_TAG_b; + }; + + union + { + __IOM uint32_t P2_VLAN_MODE; /*!< (@ 0x00002B08) Port 2 VLAN Mode */ + + struct + { + __IOM uint32_t VITM : 2; /*!< [1..0] VLAN input tagging mode */ + __IOM uint32_t VICM : 2; /*!< [3..2] VLAN input verification mode */ + uint32_t : 28; + } P2_VLAN_MODE_b; + }; + + union + { + __IM uint32_t P2_VIC_DROP_CNT; /*!< (@ 0x00002B0C) Port 2 VLAN Ingress Check Drop Frame Counter */ + + struct + { + __IM uint32_t VIC_DROP_CNT : 16; /*!< [15..0] Port n VLAN ingress check drop frame count */ + uint32_t : 16; + } P2_VIC_DROP_CNT_b; + }; + __IM uint32_t RESERVED89[6]; + + union + { + __IM uint32_t P2_LOOKUP_HIT_CNT; /*!< (@ 0x00002B28) Port 2 DST Address Lookup Hit Counter */ + + struct + { + __IM uint32_t LOOKUP_HIT_CNT : 24; /*!< [23..0] Port n Lookup hit count */ + uint32_t : 8; + } P2_LOOKUP_HIT_CNT_b; + }; + + union + { + __IOM uint32_t P2_ERROR_STATUS; /*!< (@ 0x00002B2C) Port 2 Frame Parser Runtime Error Status */ + + struct + { + __IOM uint32_t SOPERR : 1; /*!< [0..0] SOP error detected in frame parser */ + __IOM uint32_t PUNDSZ : 1; /*!< [1..1] Preemptable frame under size error detected in frame + * parser */ + __IOM uint32_t POVRSZ : 1; /*!< [2..2] Preemptable frame over size error detected in frame parser */ + __IOM uint32_t EUNDSZ : 1; /*!< [3..3] Express frame under size error detected in frame parser */ + __IOM uint32_t EOVRSZ : 1; /*!< [4..4] Express frame over size error detected in frame parser */ + uint32_t : 27; + } P2_ERROR_STATUS_b; + }; + + union + { + __IOM uint32_t P2_ERROR_MASK; /*!< (@ 0x00002B30) Port 2 Frame Parser Runtime Error Mask */ + + struct + { + __IOM uint32_t MSOPERR : 1; /*!< [0..0] Error mask of SOPERR (SOP error) */ + __IOM uint32_t MPUNDSZ : 1; /*!< [1..1] Error mask of PUNDSZ (Preemptable frame under size error) */ + __IOM uint32_t MPOVRSZ : 1; /*!< [2..2] Error mask of POVRSZ (Preemptable frame over size error) */ + __IOM uint32_t MEUNDSZ : 1; /*!< [3..3] Error mask of EUNDSZ (Express frame under size error) */ + __IOM uint32_t MEOVRSZ : 1; /*!< [4..4] Error mask of EOVRSZ (Express frame over size error) */ + uint32_t : 27; + } P2_ERROR_MASK_b; + }; + __IM uint32_t RESERVED90[564]; + + union + { + __IM uint32_t STATN_STATUS; /*!< (@ 0x00003404) Statistics Status Register */ + + struct + { + __IM uint32_t BUSY : 1; /*!< [0..0] Statistics module is busy */ + uint32_t : 31; + } STATN_STATUS_b; + }; + + union + { + __IOM uint32_t STATN_CONFIG; /*!< (@ 0x00003408) Statistics Configure Register */ + + struct + { + uint32_t : 1; + __IOM uint32_t CLEAR_ON_READ : 1; /*!< [1..1] When set to 1, a read to a counter resets it to 0. When + * set to 0 (default), counters are not affected by read. */ + uint32_t : 29; + __IOM uint32_t RESET : 1; /*!< [31..31] When set to 1, all internal functions are aborted and + * return to a stable state (flushes prescalers). It also + * triggers a clear of all counter memory (all ports are cleared) + * by setting STATN_CONTROL.CMD_CLEAR with all mask bits. + * Capture memory is not reset. */ + } STATN_CONFIG_b; + }; + + union + { + __IOM uint32_t STATN_CONTROL; /*!< (@ 0x0000340C) Statistics Control Register */ + + struct + { + __IOM uint32_t CHANMASK : 4; /*!< [3..0] One bit per port. Bit 0 = port 0, bit 1 = port 1, and + * so on. */ + uint32_t : 25; + __IOM uint32_t CLEAR_PRE : 1; /*!< [29..29] Clear the internal pre-scaler counters of ports when + * a clear occurs. This bit can be used together with the + * CMD_CLEAR command to clear the internal pre-scaler counters + * of the ports. */ + uint32_t : 1; + __IOM uint32_t CMD_CLEAR : 1; /*!< [31..31] Clear Channel Counters Command */ + } STATN_CONTROL_b; + }; + + union + { + __IOM uint32_t STATN_CLEARVALUE_LO; /*!< (@ 0x00003410) Statistics Clear Value Lower Register */ + + struct + { + __IOM uint32_t STATN_CLEARVALUE_LO : 32; /*!< [31..0] 32-bit value written into statistics memory when a clear + * command (STATN_CONTROL.CMD_CLEAR) is triggered (see ), + * or when a clear-after-read is used. */ + } STATN_CLEARVALUE_LO_b; + }; + __IM uint32_t RESERVED91[21]; + + union + { + __IM uint32_t ODISC0; /*!< (@ 0x00003468) Port 0 Discarded Outgoing Frame Count Register */ + + struct + { + __IM uint32_t ODISC : 32; /*!< [31..0] Port n outgoing frames discarded due to output queue + * congestion. */ + } ODISC0_b; + }; + + union + { + __IM uint32_t IDISC_VLAN0; /*!< (@ 0x0000346C) Port 0 Discarded Incoming VLAN Tagged Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching + * or missing VLAN ID while VLAN verification was enabled. */ + } IDISC_VLAN0_b; + }; + + union + { + __IM uint32_t IDISC_UNTAGGED0; /*!< (@ 0x00003470) Port 0 Discarded Incoming VLAN Untagged Frame + * Count Register */ + + struct + { + __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN + * tag. */ + } IDISC_UNTAGGED0_b; + }; + + union + { + __IM uint32_t IDISC_BLOCKED0; /*!< (@ 0x00003474) Port 0 Discarded Incoming Blocked Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as + * the port is configured in blocking mode. */ + } IDISC_BLOCKED0_b; + }; + + union + { + __IM uint32_t IDISC_ANY0; /*!< (@ 0x00003478) Port 0 Discarded Any Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes + * IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED. */ + } IDISC_ANY0_b; + }; + + union + { + __IM uint32_t IDISC_SRCFLT0; /*!< (@ 0x0000347C) Port 0 Discarded Address Source Count Register */ + + struct + { + __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded + * due to the MAC address source filter. */ + } IDISC_SRCFLT0_b; + }; + + union + { + __IM uint32_t TX_HOLD_REQ_CNT0; /*!< (@ 0x00003480) Port 0 TX Hold Request Count Register */ + + struct + { + __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT */ + } TX_HOLD_REQ_CNT0_b; + }; + + union + { + __IM uint32_t TX_FRAG_CNT0; /*!< (@ 0x00003484) Port 0 TX for Preemption Count Register */ + + struct + { + __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted + * due to preemption. */ + } TX_FRAG_CNT0_b; + }; + + union + { + __IM uint32_t RX_FRAG_CNT0; /*!< (@ 0x00003488) Port 0 RX Continuation Count Register */ + + struct + { + __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received. */ + } RX_FRAG_CNT0_b; + }; + + union + { + __IM uint32_t RX_ASSY_OK_CNT0; /*!< (@ 0x0000348C) Port 0 RX Preempted Frame Success Count Register */ + + struct + { + __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully + * assembled. */ + } RX_ASSY_OK_CNT0_b; + }; + + union + { + __IM uint32_t RX_ASSY_ERR_CNT0; /*!< (@ 0x00003490) Port 0 RX Preempted Frame Incorrect Count Register */ + + struct + { + __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly + * assembled. */ + uint32_t : 16; + } RX_ASSY_ERR_CNT0_b; + }; + + union + { + __IM uint32_t RX_SMD_ERR_CNT0; /*!< (@ 0x00003494) Port 0 RX SMD Frame Count Register */ + + struct + { + __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received + * and no assembly is in progress. */ + uint32_t : 16; + } RX_SMD_ERR_CNT0_b; + }; + + union + { + __IM uint32_t TX_VERIFY_OK_CNT0; /*!< (@ 0x00003498) Port 0 TX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted. */ + uint32_t : 24; + } TX_VERIFY_OK_CNT0_b; + }; + + union + { + __IM uint32_t TX_RESPONSE_OK_CNT0; /*!< (@ 0x0000349C) Port 0 TX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted. */ + uint32_t : 24; + } TX_RESPONSE_OK_CNT0_b; + }; + + union + { + __IM uint32_t RX_VERIFY_OK_CNT0; /*!< (@ 0x000034A0) Port 0 RX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_OK_CNT0_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_OK_CNT0; /*!< (@ 0x000034A4) Port 0 RX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_OK_CNT0_b; + }; + + union + { + __IM uint32_t RX_VERIFY_BAD_CNT0; /*!< (@ 0x000034A8) Port 0 RX Error VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_BAD_CNT0_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_BAD_CNT0; /*!< (@ 0x000034AC) Port 0 RX Error RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_BAD_CNT0_b; + }; + + union + { + __IM uint32_t ODISC1; /*!< (@ 0x000034B0) Port 1 Discarded Outgoing Frame Count Register */ + + struct + { + __IM uint32_t ODISC : 32; /*!< [31..0] Port n outgoing frames discarded due to output queue + * congestion. */ + } ODISC1_b; + }; + + union + { + __IM uint32_t IDISC_VLAN1; /*!< (@ 0x000034B4) Port 1 Discarded Incoming VLAN Tagged Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching + * or missing VLAN ID while VLAN verification was enabled. */ + } IDISC_VLAN1_b; + }; + + union + { + __IM uint32_t IDISC_UNTAGGED1; /*!< (@ 0x000034B8) Port 1 Discarded Incoming VLAN Untagged Frame + * Count Register */ + + struct + { + __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN + * tag. */ + } IDISC_UNTAGGED1_b; + }; + + union + { + __IM uint32_t IDISC_BLOCKED1; /*!< (@ 0x000034BC) Port 1 Discarded Incoming Blocked Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as + * the port is configured in blocking mode. */ + } IDISC_BLOCKED1_b; + }; + + union + { + __IM uint32_t IDISC_ANY1; /*!< (@ 0x000034C0) Port 1 Discarded Any Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes + * IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED. */ + } IDISC_ANY1_b; + }; + + union + { + __IM uint32_t IDISC_SRCFLT1; /*!< (@ 0x000034C4) Port 1 Discarded Address Source Count Register */ + + struct + { + __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded + * due to the MAC address source filter. */ + } IDISC_SRCFLT1_b; + }; + + union + { + __IM uint32_t TX_HOLD_REQ_CNT1; /*!< (@ 0x000034C8) Port 1 TX Hold Request Count Register */ + + struct + { + __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT */ + } TX_HOLD_REQ_CNT1_b; + }; + + union + { + __IM uint32_t TX_FRAG_CNT1; /*!< (@ 0x000034CC) Port 1 TX for Preemption Count Register */ + + struct + { + __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted + * due to preemption. */ + } TX_FRAG_CNT1_b; + }; + + union + { + __IM uint32_t RX_FRAG_CNT1; /*!< (@ 0x000034D0) Port 1 RX Continuation Count Register */ + + struct + { + __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received. */ + } RX_FRAG_CNT1_b; + }; + + union + { + __IM uint32_t RX_ASSY_OK_CNT1; /*!< (@ 0x000034D4) Port 1 RX Preempted Frame Success Count Register */ + + struct + { + __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully + * assembled. */ + } RX_ASSY_OK_CNT1_b; + }; + + union + { + __IM uint32_t RX_ASSY_ERR_CNT1; /*!< (@ 0x000034D8) Port 1 RX Preempted Frame Incorrect Count Register */ + + struct + { + __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly + * assembled. */ + uint32_t : 16; + } RX_ASSY_ERR_CNT1_b; + }; + + union + { + __IM uint32_t RX_SMD_ERR_CNT1; /*!< (@ 0x000034DC) Port 1 RX SMD Frame Count Register */ + + struct + { + __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received + * and no assembly is in progress. */ + uint32_t : 16; + } RX_SMD_ERR_CNT1_b; + }; + + union + { + __IM uint32_t TX_VERIFY_OK_CNT1; /*!< (@ 0x000034E0) Port 1 TX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted. */ + uint32_t : 24; + } TX_VERIFY_OK_CNT1_b; + }; + + union + { + __IM uint32_t TX_RESPONSE_OK_CNT1; /*!< (@ 0x000034E4) Port 1 TX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted. */ + uint32_t : 24; + } TX_RESPONSE_OK_CNT1_b; + }; + + union + { + __IM uint32_t RX_VERIFY_OK_CNT1; /*!< (@ 0x000034E8) Port 1 RX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_OK_CNT1_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_OK_CNT1; /*!< (@ 0x000034EC) Port 1 RX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_OK_CNT1_b; + }; + + union + { + __IM uint32_t RX_VERIFY_BAD_CNT1; /*!< (@ 0x000034F0) Port 1 RX Error VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_BAD_CNT1_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_BAD_CNT1; /*!< (@ 0x000034F4) Port 1 RX Error RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_BAD_CNT1_b; + }; + + union + { + __IM uint32_t ODISC2; /*!< (@ 0x000034F8) Port 2 Discarded Outgoing Frame Count Register */ + + struct + { + __IM uint32_t ODISC : 32; /*!< [31..0] Port n outgoing frames discarded due to output queue + * congestion. */ + } ODISC2_b; + }; + + union + { + __IM uint32_t IDISC_VLAN2; /*!< (@ 0x000034FC) Port 2 Discarded Incoming VLAN Tagged Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching + * or missing VLAN ID while VLAN verification was enabled. */ + } IDISC_VLAN2_b; + }; + + union + { + __IM uint32_t IDISC_UNTAGGED2; /*!< (@ 0x00003500) Port 2 Discarded Incoming VLAN Untagged Frame + * Count Register */ + + struct + { + __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN + * tag. */ + } IDISC_UNTAGGED2_b; + }; + + union + { + __IM uint32_t IDISC_BLOCKED2; /*!< (@ 0x00003504) Port 2 Discarded Incoming Blocked Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as + * the port is configured in blocking mode. */ + } IDISC_BLOCKED2_b; + }; + + union + { + __IM uint32_t IDISC_ANY2; /*!< (@ 0x00003508) Port 2 Discarded Any Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes + * IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED. */ + } IDISC_ANY2_b; + }; + + union + { + __IM uint32_t IDISC_SRCFLT2; /*!< (@ 0x0000350C) Port 2 Discarded Address Source Count Register */ + + struct + { + __IM uint32_t IDISC_SRCFLT : 32; /*!< [31..0] Port n counts the number of incoming frames discarded + * due to the MAC address source filter. */ + } IDISC_SRCFLT2_b; + }; + + union + { + __IM uint32_t TX_HOLD_REQ_CNT2; /*!< (@ 0x00003510) Port 2 TX Hold Request Count Register */ + + struct + { + __IM uint32_t TX_HOLD_REQ_CNT : 32; /*!< [31..0] TX_HOLD_REQ_CNT */ + } TX_HOLD_REQ_CNT2_b; + }; + + union + { + __IM uint32_t TX_FRAG_CNT2; /*!< (@ 0x00003514) Port 2 TX for Preemption Count Register */ + + struct + { + __IM uint32_t TX_FRAG_CNT : 32; /*!< [31..0] Port n increments when an additional mPacket is transmitted + * due to preemption. */ + } TX_FRAG_CNT2_b; + }; + + union + { + __IM uint32_t RX_FRAG_CNT2; /*!< (@ 0x00003518) Port 2 RX Continuation Count Register */ + + struct + { + __IM uint32_t RX_FRAG_CNT : 32; /*!< [31..0] Port n increments for every continuation mPacket received. */ + } RX_FRAG_CNT2_b; + }; + + union + { + __IM uint32_t RX_ASSY_OK_CNT2; /*!< (@ 0x0000351C) Port 2 RX Preempted Frame Success Count Register */ + + struct + { + __IM uint32_t RX_ASSY_OK_CNT : 32; /*!< [31..0] Port n increments when a preempted frame is successfully + * assembled. */ + } RX_ASSY_OK_CNT2_b; + }; + + union + { + __IM uint32_t RX_ASSY_ERR_CNT2; /*!< (@ 0x00003520) Port 2 RX Preempted Frame Incorrect Count Register */ + + struct + { + __IM uint32_t RX_ASSY_ERR_CNT : 16; /*!< [15..0] Port n increments when a preempted frame is incorrectly + * assembled. */ + uint32_t : 16; + } RX_ASSY_ERR_CNT2_b; + }; + + union + { + __IM uint32_t RX_SMD_ERR_CNT2; /*!< (@ 0x00003524) Port 2 RX SMD Frame Count Register */ + + struct + { + __IM uint32_t RX_SMD_ERR_CNT : 16; /*!< [15..0] Port n increments when a frame with an SMD-Cx is received + * and no assembly is in progress. */ + uint32_t : 16; + } RX_SMD_ERR_CNT2_b; + }; + + union + { + __IM uint32_t TX_VERIFY_OK_CNT2; /*!< (@ 0x00003528) Port 2 TX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t TX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every VERIFY frame transmitted. */ + uint32_t : 24; + } TX_VERIFY_OK_CNT2_b; + }; + + union + { + __IM uint32_t TX_RESPONSE_OK_CNT2; /*!< (@ 0x0000352C) Port 2 TX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t TX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every RESPONSE frame transmitted. */ + uint32_t : 24; + } TX_RESPONSE_OK_CNT2_b; + }; + + union + { + __IM uint32_t RX_VERIFY_OK_CNT2; /*!< (@ 0x00003530) Port 2 RX VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_OK_CNT : 8; /*!< [7..0] Port n increments for every valid VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_OK_CNT2_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_OK_CNT2; /*!< (@ 0x00003534) Port 2 RX RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_OK_CNT : 8; /*!< [7..0] Port n increments for every valid RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_OK_CNT2_b; + }; + + union + { + __IM uint32_t RX_VERIFY_BAD_CNT2; /*!< (@ 0x00003538) Port 2 RX Error VERIFY Frame Count Register */ + + struct + { + __IM uint32_t RX_VERIFY_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored VERIFY frame received. */ + uint32_t : 24; + } RX_VERIFY_BAD_CNT2_b; + }; + + union + { + __IM uint32_t RX_RESPONSE_BAD_CNT2; /*!< (@ 0x0000353C) Port 2 RX Error RESPONSE Frame Count Register */ + + struct + { + __IM uint32_t RX_RESPONSE_BAD_CNT : 8; /*!< [7..0] Port n increments for every errored RESPONSE frame received. */ + uint32_t : 24; + } RX_RESPONSE_BAD_CNT2_b; + }; + + union + { + __IM uint32_t ODISC3; /*!< (@ 0x00003540) Port 3 Discarded Outgoing Frame Count Register */ + + struct + { + __IM uint32_t ODISC : 32; /*!< [31..0] Port n outgoing frames discarded due to output queue + * congestion. */ + } ODISC3_b; + }; + + union + { + __IM uint32_t IDISC_VLAN3; /*!< (@ 0x00003544) Port 3 Discarded Incoming VLAN Tagged Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_VLAN : 32; /*!< [31..0] Port n incoming frames discarded due to mismatching + * or missing VLAN ID while VLAN verification was enabled. */ + } IDISC_VLAN3_b; + }; + + union + { + __IM uint32_t IDISC_UNTAGGED3; /*!< (@ 0x00003548) Port 3 Discarded Incoming VLAN Untagged Frame + * Count Register */ + + struct + { + __IM uint32_t IDISC_UNTAGGED : 32; /*!< [31..0] Port n incoming frames discarded due to missing VLAN + * tag. */ + } IDISC_UNTAGGED3_b; + }; + + union + { + __IM uint32_t IDISC_BLOCKED3; /*!< (@ 0x0000354C) Port 3 Discarded Incoming Blocked Frame Count + * Register */ + + struct + { + __IM uint32_t IDISC_BLOCKED : 32; /*!< [31..0] Port n incoming frames discarded (after learning) as + * the port is configured in blocking mode. */ + } IDISC_BLOCKED3_b; + }; + + union + { + __IM uint32_t IDISC_ANY3; /*!< (@ 0x00003550) Port 3 Discarded Any Frame Count Register (n + * = 0 to 3) */ + + struct + { + __IM uint32_t IDISC_ANY : 32; /*!< [31..0] Port n total incoming frames discarded. This includes + * IDISC_VLAN, IDSIC_UNTAGGED, IDISC_SRCFLT, and IDISC_BLOCKED. */ + } IDISC_ANY3_b; + }; + __IM uint32_t RESERVED92[363]; + + union + { + __IOM uint32_t MMCTL_OUT_CT; /*!< (@ 0x00003B00) Cut-Through Register */ + + struct + { + __IOM uint32_t CT_OVR_ENA : 3; /*!< [2..0] Per-port bit mask to enable overriding the Cut-Through + * (CT) behavior of the output ports with CT_OVR. When set + * to 0, the frames are transmitted CT if the CT flag of the + * frame context is set. */ + uint32_t : 13; + __IOM uint32_t CT_OVR : 3; /*!< [18..16] 1 bit per-port value to set the Cut Through behavior + * of the output ports. When set to 0, all frames are sent + * as Store & Forward (SF) frames. When set to 1, frames with + * the CT flag set in the frame context are started as soon + * as the frame context information is available. */ + uint32_t : 13; + } MMCTL_OUT_CT_b; + }; + + union + { + __IOM uint32_t MMCTL_CTFL_P0_3_ENA; /*!< (@ 0x00003B04) Cut-Through Frame Length Enable Register */ + + struct + { + __IOM uint32_t CTFL_P0_ENA : 8; /*!< [7..0] Port 0 bit mask of n bits, where n is the number of queues + * per port indicating whether the CTFL is used for Cut-Through + * (CT) frames. When set to 1, a CT frame requires a CTFL + * entry to be written as a CT frame in the output memory. */ + __IOM uint32_t CTFL_P1_ENA : 8; /*!< [15..8] Port 1 bit mask of n bits, where n is the number of + * queues per port indicating whether the CTFL is used for + * Cut-Through (CT) frames. When set to 1, a CT frame requires + * a CTFL entry to be written as a CT frame in the output + * memory. */ + __IOM uint32_t CTFL_P2_ENA : 8; /*!< [23..16] Port 2 bit mask of n bits, where n is the number of + * queues per port indicating whether the CTFL is used for + * Cut-Through (CT) frames. When set to 1, a CT frame requires + * a CTFL entry to be written as a CT frame in the output + * memory. */ + uint32_t : 8; + } MMCTL_CTFL_P0_3_ENA_b; + }; + __IM uint32_t RESERVED93[6]; + + union + { + __IOM uint32_t MMCTL_YELLOW_BYTE_LENGTH_P[3]; /*!< (@ 0x00003B20) Port [0..2] Yellow Period Byte Length Register */ + + struct + { + uint32_t : 2; + __IOM uint32_t YELLOW_LEN : 14; /*!< [15..2] Length in bytes of the YELLOW period for port n. Determines + * whether a frame can be transmitted before the YELLOW period + * expires. The value is programmed in increments of 4 bytes + * excluding the MAC overhead (IPG, Preamble and FCS if appended) + * of the frame. */ + __IOM uint32_t YLEN_EN : 1; /*!< [16..16] When set to 1, enables transmission when OUT_CT_ENA + * is low only if the frame length is less than YELLOW_LEN. + * If cleared, YELLOW_LEN is ignored and frames are always + * transmitted in SF mode when OUT_CT_ENA is 0. */ + uint32_t : 15; + } MMCTL_YELLOW_BYTE_LENGTH_P_b[3]; + }; + __IM uint32_t RESERVED94[5]; + + union + { + __IOM uint32_t MMCTL_POOL0_CTR; /*!< (@ 0x00003B40) Memory Pool Counter (n = 0 to 1) */ + + struct + { + __IOM uint32_t CELLS : 10; /*!< [9..0] Memory pool configuration for pool n. Configures, in + * cells, the size of each memory pool. */ + uint32_t : 6; + __IM uint32_t USED : 10; /*!< [25..16] Reports the current available number of used cells + * for this memory pool. The used number of free cells can + * be calculated as CELLS - USED. */ + uint32_t : 6; + } MMCTL_POOL0_CTR_b; + }; + + union + { + __IOM uint32_t MMCTL_POOL1_CTR; /*!< (@ 0x00003B44) Memory Pool Counter (n = 0 to 1) */ + + struct + { + __IOM uint32_t CELLS : 10; /*!< [9..0] Memory pool configuration for pool n. Configures, in + * cells, the size of each memory pool. */ + uint32_t : 6; + __IM uint32_t USED : 10; /*!< [25..16] Reports the current available number of used cells + * for this memory pool. The used number of free cells can + * be calculated as CELLS - USED. */ + uint32_t : 6; + } MMCTL_POOL1_CTR_b; + }; + __IM uint32_t RESERVED95[6]; + + union + { + __IOM uint32_t MMCTL_POOL_GLOBAL; /*!< (@ 0x00003B60) Memory Pool Configuration Register */ + + struct + { + __IOM uint32_t CELLS : 10; /*!< [9..0] Memory pool configuration for the global pool. Configures, + * in cells, the size of the global shared pool. */ + uint32_t : 6; + __IM uint32_t USED : 10; /*!< [25..16] Reports the current number of used cells for the global + * shared pool. The used number of free cells can be calculated + * as CELLS - USED. */ + uint32_t : 6; + } MMCTL_POOL_GLOBAL_b; + }; + + union + { + __IM uint32_t MMCTL_POOL_STATUS; /*!< (@ 0x00003B64) Memory Pool Status Register */ + + struct + { + __IM uint32_t QUEUE_FULL : 8; /*!< [7..0] Per-queue pool full indication. Indicates for each queue + * whether all the blocks in the corresponding pool and global + * pool are allocated. */ + uint32_t : 24; + } MMCTL_POOL_STATUS_b; + }; + + union + { + __IOM uint32_t MMCTL_POOL_QMAP; /*!< (@ 0x00003B68) Queue MAP Register */ + + struct + { + __IOM uint32_t Q0_MAP : 1; /*!< [0..0] Queue 0 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q0_ENA : 1; /*!< [3..3] Queue 0 Memory Pool Enabled */ + __IOM uint32_t Q1_MAP : 1; /*!< [4..4] Queue 1 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q1_ENA : 1; /*!< [7..7] Queue 1 Memory Pool Enabled */ + __IOM uint32_t Q2_MAP : 1; /*!< [8..8] Queue 2 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q2_ENA : 1; /*!< [11..11] Queue 2 Memory Pool Enabled */ + __IOM uint32_t Q3_MAP : 1; /*!< [12..12] Queue 3 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q3_ENA : 1; /*!< [15..15] Queue 3 Memory Pool Enabled */ + __IOM uint32_t Q4_MAP : 1; /*!< [16..16] Queue 4 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q4_ENA : 1; /*!< [19..19] Queue 4 Memory Pool Enabled */ + __IOM uint32_t Q5_MAP : 1; /*!< [20..20] Queue 5 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q5_ENA : 1; /*!< [23..23] Queue 5 Memory Pool Enabled */ + __IOM uint32_t Q6_MAP : 1; /*!< [24..24] Queue 6 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q6_ENA : 1; /*!< [27..27] Queue 6 Memory Pool Enabled */ + __IOM uint32_t Q7_MAP : 1; /*!< [28..28] Queue 7 Memory Pool */ + uint32_t : 2; + __IOM uint32_t Q7_ENA : 1; /*!< [31..31] Queue 7 Memory Pool Enabled */ + } MMCTL_POOL_QMAP_b; + }; + + union + { + __OM uint32_t MMCTL_QGATE; /*!< (@ 0x00003B6C) Queue Gate State Register */ + + struct + { + __OM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port bit mask. When set to 1 for a port, the queue + * gate state is changed for that port as indicated by QUEUE_GATE. */ + uint32_t : 12; + __OM uint32_t QUEUE_GATE : 16; /*!< [31..16] 2-bit per queue indicating the action to be performed + * on each queue of the ports indicated by PORT_MASK. */ + } MMCTL_QGATE_b; + }; + + union + { + __OM uint32_t MMCTL_QTRIG; /*!< (@ 0x00003B70) Queue Trigger Register */ + + struct + { + __OM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port bit mask. When set to 1 for a port, a frame + * is triggered from the closed queues indicated by QUEUE_TRIG. */ + uint32_t : 12; + __OM uint32_t QUEUE_TRIG : 8; /*!< [23..16] 1-bit per queue indicating from which queues a frame + * is to be transmitted from the ports indicated by PORT_MASK. + * When set to 1, a single frame is transmitted per indicated + * port in PORT_MASK among the queues indicated by QUEUE_TRIG. */ + uint32_t : 8; + } MMCTL_QTRIG_b; + }; + + union + { + __OM uint32_t MMCTL_QFLUSH; /*!< (@ 0x00003B74) Flush Event Select Register */ + + struct + { + __OM uint32_t PORT_MASK : 4; /*!< [3..0] Per-port bit mask. When set to 1 for a port, the queue + * flush status is changed for that port for the queues indicated + * in QUEUE_MASK. */ + uint32_t : 12; + __OM uint32_t QUEUE_MASK : 8; /*!< [23..16] 1 bit per queue indicating for which queues of the + * ports indicated by PORT_MASK the flush state is changed + * as indicated in ACTION. */ + __OM uint32_t ACTION : 2; /*!< [25..24] Selects the flush state for the queues indicated by + * QUEUE_MASK in the ports indicated by PORT_MASK. Possible + * actions are: */ + uint32_t : 6; + } MMCTL_QFLUSH_b; + }; + + union + { + __IM uint32_t MMCTL_QCLOSED_STATUS_P0_3; /*!< (@ 0x00003B78) Queue Closed Status Register */ + + struct + { + __IM uint32_t P0_STATUS : 8; /*!< [7..0] Per-queue closed status of Port 0 (1-bit per queue). + * A 0 indicates that the queue is open (enabled), and a 1 + * indicates that the queue is closed (disabled). */ + __IM uint32_t P1_STATUS : 8; /*!< [15..8] Per-queue closed status of Port 1 (1-bit per queue). + * A 0 indicates that the queue is open (enabled), and a 1 + * indicates that the queue is closed (disabled). */ + __IM uint32_t P2_STATUS : 8; /*!< [23..16] Per-queue closed status of Port 2 (1-bit per queue). + * A 0 indicates that the queue is open (enabled), and a 1 + * indicates that the queue is closed (disabled). */ + uint32_t : 8; + } MMCTL_QCLOSED_STATUS_P0_3_b; + }; + __IM uint32_t RESERVED96; + + union + { + __IOM uint32_t MMCTL_1FRAME_MODE_P[3]; /*!< (@ 0x00003B80) Port [0..2] 1-Frame Mode Configuration Register */ + + struct + { + __IOM uint32_t Q_1FRAME_ENA : 8; /*!< [7..0] 1 bit per queue. Setting a bit to 1 enables the 1-frame + * mode for that queue for port n. In this mode, only one + * frame is allowed in the queue. If a new frame is received, + * the old frame is discarded. */ + uint32_t : 8; + __IOM uint32_t Q_BUF_ENA : 8; /*!< [23..16] 1 bit per queue. Setting a bit to 1 enables the buffer + * mode behavior for that queue for port n. This mode requires + * also that Q_1FRAME_ENA is set to 1. */ + uint32_t : 8; + } MMCTL_1FRAME_MODE_P_b[3]; + }; + __IM uint32_t RESERVED97[5]; + + union + { + __IM uint32_t MMCTL_P0_3_QUEUE_STATUS; /*!< (@ 0x00003BA0) Queue Status Indicator */ + + struct + { + __IM uint32_t P0_Q_STATUS : 8; /*!< [7..0] Port 0 Per-Queue Bit Indication */ + __IM uint32_t P1_Q_STATUS : 8; /*!< [15..8] Port 1 Per-Queue Bit Indication */ + __IM uint32_t P2_Q_STATUS : 8; /*!< [23..16] Port 2 Per-Queue Bit Indication */ + uint32_t : 8; + } MMCTL_P0_3_QUEUE_STATUS_b; + }; + __IM uint32_t RESERVED98; + + union + { + __IM uint32_t MMCTL_P0_3_FLUSH_STATUS; /*!< (@ 0x00003BA8) Queue Flush Status Indicator */ + + struct + { + __IM uint32_t P0_F_STATUS : 8; /*!< [7..0] Port 0 per-Queue Bit Indication on whether the queue + * is flushing frames (read 1) or not (read 0). */ + __IM uint32_t P1_F_STATUS : 8; /*!< [15..8] Port 1 per-Queue Bit Indication on whether the queue + * is flushing frames (read 1) or not (read 0). */ + __IM uint32_t P2_F_STATUS : 8; /*!< [23..16] Port 2 per-Queue Bit Indication on whether the queue + * is flushing frames (read 1) or not (read 0). */ + uint32_t : 8; + } MMCTL_P0_3_FLUSH_STATUS_b; + }; + __IM uint32_t RESERVED99; + + union + { + __IOM uint32_t MMCTL_DLY_QTRIGGER_CTRL; /*!< (@ 0x00003BB0) Delayed Queue Trigger Control Register */ + + struct + { + __IOM uint32_t DELAY_TIME : 30; /*!< [29..0] 30-bit time in nanoseconds indicates the time after + * the trigger request from the pattern matchers to generate + * the event. */ + __IOM uint32_t TIMER_SEL : 1; /*!< [30..30] Select the source timer to use for calculating the + * time. */ + uint32_t : 1; + } MMCTL_DLY_QTRIGGER_CTRL_b; + }; + + union + { + __IOM uint32_t MMCTL_PREEMPT_QUEUES; /*!< (@ 0x00003BB4) Preemptable Queues Configures Register */ + + struct + { + __IOM uint32_t PREEMPT_ENA : 8; /*!< [7..0] Per-queue enable bit to configure which queues are used + * for preemptable traffic. Set to 1 the corresponding bit + * to configure a queue to be preemptable. */ + __IOM uint32_t PREEMPT_ON_QCLOSE : 8; /*!< [15..8] Per-queue configuration bit to enable preempting a frame + * when the queue goes from OPEN to CLOSED. When the corresponding + * bit is set to 1 and the queue is configured as preemptable + * in PREEMPT_ENA, a queue close event causes the current + * frame to be preempted, if preemption is operational. */ + uint32_t : 16; + } MMCTL_PREEMPT_QUEUES_b; + }; + + union + { + __IOM uint32_t MMCTL_HOLD_CONTROL; /*!< (@ 0x00003BB8) Request Preemption Register */ + + struct + { + __IOM uint32_t Q_HOLD_REQ_FORCE : 3; /*!< [2..0] A per-port bit that forces a preempt request using MM_CTL.request + * (hold_req). When this bit is set to 1, it overrides other + * sources of hold request, including the TDMA controller. */ + uint32_t : 13; + __IOM uint32_t Q_HOLD_REQ_RELEASE : 3; /*!< [18..16] A per-port bit that forces a release of preemption + * request using MM_CTL.request (hold_req). When this bit + * is set to 1, it overrides other sources of hold request, + * including the TDMA controller and Q_HOLD_REQ_FORCE[2:0]. */ + uint32_t : 13; + } MMCTL_HOLD_CONTROL_b; + }; + + union + { + __IM uint32_t MMCTL_PREEMPT_STATUS; /*!< (@ 0x00003BBC) Preemption State Register */ + + struct + { + __IM uint32_t PREEMPT_STATE : 3; /*!< [2..0] A per-port bit that indicates if a port is in a preempted + * state. This is a real-time indication meant for debugging. */ + uint32_t : 13; + __IM uint32_t HOLD_REQ_STATE : 3; /*!< [18..16] A per-port bit that indicates if a port is preempted + * using MM_CTL.request (hold_req). This is a real-time indication + * meant for debugging. */ + uint32_t : 13; + } MMCTL_PREEMPT_STATUS_b; + }; + + union + { + __IOM uint32_t MMCTL_CQF_CTRL_P[4]; /*!< (@ 0x00003BC0) Port [0..3] Cyclic Queuing and Forwarding Control + * Register */ + + struct + { + __IOM uint32_t PRIO_ENABLE0 : 8; /*!< [7..0] A per-queue enable to select which ingress priorities + * are queued in the two CQF queues. */ + __IOM uint32_t QUEUE_SEL0 : 3; /*!< [10..8] Select which two physical queues are used for CQF. The + * queues used are QUEUE_SEL0 and QUEUE_SEL0 + 1. Frames are + * written into QUEUE_SEL0 when the gate control selected + * with GATE_SEL0 is 0, and into QUEUE_SEL0 + 1 when the gate + * control is 1. */ + __IOM uint32_t GATE_SEL0 : 3; /*!< [13..11] Select which gate control signal is used for selecting + * the output queue (these signals are the same as the ETHSW_TDMAOUT + * pins). */ + __IOM uint32_t USE_SOP0 : 1; /*!< [14..14] When set to 1, the CFQ queue is determined when the + * SOP is received at the frame writer in the memory controller. + * When set to 0, the queue is determined when the EOP is + * received at the frame writer. */ + __IOM uint32_t REF_SEL0 : 1; /*!< [15..15] Select whether the gate control signal used for the + * CQF group is based on the egress port when set to 0, or + * the ingress port when set to 1. */ + uint32_t : 16; + } MMCTL_CQF_CTRL_P_b[4]; + }; + __IM uint32_t RESERVED100[4]; + + union + { + __IM uint32_t MMCTL_P0_3_QCLOSED_NONEMPTY; /*!< (@ 0x00003BE0) Port Queue Status Register */ + + struct + { + __IM uint32_t P0_Q_STATUS : 8; /*!< [7..0] Port 0 per-queue bit indication on whether the queue + * transitioned from open to closed state while frames were + * still queued. */ + __IM uint32_t P1_Q_STATUS : 8; /*!< [15..8] Port 1 per-queue bit indication on whether the queue + * transitioned from open to closed state while frames were + * still queued. */ + __IM uint32_t P2_Q_STATUS : 8; /*!< [23..16] Port 2 per-queue bit indication on whether the queue + * transitioned from open to closed state while frames were + * still queued. */ + __IM uint32_t P3_Q_STATUS : 8; /*!< [31..24] Port 3 per-queue bit indication on whether the queue + * transitioned from open to closed state while frames were + * still queued. */ + } MMCTL_P0_3_QCLOSED_NONEMPTY_b; + }; + __IM uint32_t RESERVED101; + + union + { + __IOM uint32_t MMCTL_PREEMPT_EXTRA; /*!< (@ 0x00003BE8) Frame Preemption Extra Configuration Register */ + + struct + { + __IOM uint32_t MIN_PFRM_ADJ : 4; /*!< [3..0] Adjust the minimum mPacket length, in increments of 4 + * bytes. */ + __IOM uint32_t LAST_PFRM_ADJ : 4; /*!< [7..4] Adjust the preemptable threshold when reaching the end + * of the frame, in increments of 4 bytes. Incrementing this + * value increments the length of the last mPacket. */ + uint32_t : 24; + } MMCTL_PREEMPT_EXTRA_b; + }; + __IM uint32_t RESERVED102[5]; + + union + { + __IOM uint32_t DLR_CONTROL; /*!< (@ 0x00003C00) DLR Control Register */ + + struct + { + __IOM uint32_t ENABLE : 1; /*!< [0..0] Enable DLR extension module. When set, the DLR module + * becomes active. When DLR is enabled, the LOOP_FILTER_ENA + * must also be enabled for proper DLR operation. */ + __IOM uint32_t AUTOFLUSH : 1; /*!< [1..1] Enable automatic flushing of unicast entries in address + * table if ring reconfiguration occurs (see also DLR interrupt + * IRQ_flush_macaddr_ena in DLR_IRQ_CONTROL). */ + __IOM uint32_t LOOP_FILTER_ENA : 1; /*!< [2..2] Enable the loop filter function. When set to 1, the ingress + * loop filter is enabled. This can be enabled regardless + * of the DLR ENABLE state, allowing the loop filter function + * to operate when DLR is not used. */ + uint32_t : 1; + __IOM uint32_t IGNORE_INVTM : 1; /*!< [4..4] Enable ignore beacon frames with invalid timeout timer. + * When enabled (set to 1) frames with timeout timer value + * not within a range of 200 microseconds to 500 milliseconds + * are ignored and parameters are not locally stored or considered + * for state transitions. The invalid timeout timer value + * is always stored within the DLR_INV_TMOUT register irrespective + * of the value of this bit. Ignored frames are forwarded + * normally. */ + uint32_t : 3; + __IOM uint32_t US_TIME : 12; /*!< [19..8] Number of clock cycles required for 1 microsecond for + * the switch operating clock. This LSI operates at 200 MHz, + * therefore this register must be set to 0xC8. The value + * after reset must be changed. */ + uint32_t : 12; + } DLR_CONTROL_b; + }; + + union + { + __IM uint32_t DLR_STATUS; /*!< (@ 0x00003C04) DLR Status Register */ + + struct + { + __IM uint32_t LastBcnRcvPort : 2; /*!< [1..0] Last Beacon Receive Port */ + uint32_t : 6; + __IM uint32_t NODE_STATE : 8; /*!< [15..8] Local Node Current State */ + __IM uint32_t LINK_STATUS : 2; /*!< [17..16] Link Status */ + uint32_t : 6; + __IM uint32_t TOPOLOGY : 8; /*!< [31..24] Current Network Topology */ + } DLR_STATUS_b; + }; + + union + { + __IOM uint32_t DLR_ETH_TYP; /*!< (@ 0x00003C08) DLR Ethernet Type Register */ + + struct + { + __IOM uint32_t DLR_ETH_TYP : 16; /*!< [15..0] Ethernet type to compare for DLR frame detection (initial + * value is 0x80E1) */ + uint32_t : 16; + } DLR_ETH_TYP_b; + }; + + union + { + __IOM uint32_t DLR_IRQ_CONTROL; /*!< (@ 0x00003C0C) DLR Interrupt Control Register */ + + struct + { + __IOM uint32_t IRQ_state_chng_ena : 1; /*!< [0..0] Enable Interrupt for State Change */ + __IOM uint32_t IRQ_flush_macaddr_ena : 1; /*!< [1..1] Enable Flush Local MAC Address Table Interrupt. */ + __IOM uint32_t IRQ_stop_nbchk0_ena : 1; /*!< [2..2] Enable Stop Request Neighbor Check Timeout Timer Interrupt + * for Port 0. */ + __IOM uint32_t IRQ_stop_nbchk1_ena : 1; /*!< [3..3] Enable Stop Request Neighbor Check Timeout Timer Interrupt + * for Port 1. */ + __IOM uint32_t IRQ_bec_tmr0_exp_ena : 1; /*!< [4..4] IRQ_bec_tmr0_exp_ena */ + __IOM uint32_t IRQ_bec_tmr1_exp_ena : 1; /*!< [5..5] Enable Interrupt on Beacon Timeout Timer Expire for Port + * 1. */ + __IOM uint32_t IRQ_supr_chng_ena : 1; /*!< [6..6] Enable Interrupt on Ring Supervisor Change. */ + __IOM uint32_t IRQ_link_chng0_ena : 1; /*!< [7..7] Enable Link Status Change Interrupt Event for Port 0. */ + __IOM uint32_t IRQ_link_chng1_ena : 1; /*!< [8..8] Enable Link Status Change Interrupt Event for Port 1. */ + __IOM uint32_t IRQ_sup_ignord_ena : 1; /*!< [9..9] Enable interrupt on beacon frame detection from a supervisor + * with lower precedence than the current ring supervisor + * or lower numeric value for MAC address when precedence + * is same. */ + __IOM uint32_t IRQ_ip_addr_chng_ena : 1; /*!< [10..10] Enable interrupt on IP address change detection within + * beacon frame from ring supervisor. */ + __IOM uint32_t IRQ_invalid_tmr_ena : 1; /*!< [11..11] Enable interrupt on invalid range for beacon timeout + * timer value detection. */ + __IOM uint32_t IRQ_bec_rcv0_ena : 1; /*!< [12..12] Enable interrupt on beacon frame detection on port + * 0. */ + __IOM uint32_t IRQ_bec_rcv1_ena : 1; /*!< [13..13] Enable interrupt on beacon frame detection on port + * 1. */ + __IOM uint32_t IRQ_frm_dscrd0 : 1; /*!< [14..14] Enable interrupt on frame discard due to source address + * match with the local address on port 0. */ + __IOM uint32_t IRQ_frm_dscrd1 : 1; /*!< [15..15] Enable Interrupt on Frame discard due to source address + * match with the local address on port 1. */ + uint32_t : 13; + __IOM uint32_t low_int_en : 1; /*!< [29..29] Enable active-low interrupt. Asserted to use active-low + * interrupt signal instead of active-high interrupt signal. */ + __OM uint32_t atomic_OR : 1; /*!< [30..30] When set during a register-write, the enable bits are + * ORed into the current setting of the register. By writing + * this bit at the same time, only the target bit can be set + * to 1. */ + __OM uint32_t atomic_AND : 1; /*!< [31..31] When set during a register-write, the enable bits are + * ANDed with the current setting of the register. By writing + * this bit at the same time, only the target bit can be set + * to 0. */ + } DLR_IRQ_CONTROL_b; + }; + + union + { + __IOM uint32_t DLR_IRQ_STAT_ACK; /*!< (@ 0x00003C10) DLR Interrupt Status/ACK Register */ + + struct + { + __IOM uint32_t state_chng_IRQ_pending : 1; /*!< [0..0] Latched State Change Event */ + __IOM uint32_t flush_IRQ_pending : 1; /*!< [1..1] Latched Flush Event for MAC Address Learning Table */ + __IOM uint32_t nbchk0_IRQ_pending : 1; /*!< [2..2] Stop Request Event for Neighbor Check Timeout Timer for + * Port 0 */ + __IOM uint32_t nbchk1_IRQ_pending : 1; /*!< [3..3] Stop Request Event for Neighbor Check Timeout Timer for + * Port 1 */ + __IOM uint32_t bec_tmr0_IRQ_pending : 1; /*!< [4..4] Beacon Timeout Timer Expire Event for Port 0 */ + __IOM uint32_t bec_tmr1_IRQ_pending : 1; /*!< [5..5] Beacon Timeout Timer Expire Event for Port 1 */ + __IOM uint32_t supr_chng_IRQ_pending : 1; /*!< [6..6] Latched Supervisor Change Event */ + __IOM uint32_t Link0_IRQ_pending : 1; /*!< [7..7] Latched Link Status Change Event for Port 0 */ + __IOM uint32_t Link1_IRQ_pending : 1; /*!< [8..8] Latched Link Status Change Event for Port 1 */ + __IOM uint32_t sup_ignord_IRQ_pending : 1; /*!< [9..9] Latched Event for Beacon Frame Detection from Ignored + * Supervisor */ + __IOM uint32_t ip_chng_IRQ_pending : 1; /*!< [10..10] Latched IP Address Change Event */ + __IOM uint32_t invalid_tmr_IRQ_pending : 1; /*!< [11..11] Latched Event on Invalid Beacon Timeout Timer Value + * Detection Within Beacon Frame on Port 0 or Port 1 */ + __IOM uint32_t bec_rcv0_IRQ_pending : 1; /*!< [12..12] Latched Event on Beacon Frame Detection on Port 0 */ + __IOM uint32_t bec_rcv1_IRQ_pending : 1; /*!< [13..13] Latched Event on Beacon Frame Detection on Port 1 */ + __IOM uint32_t frm_dscrd0_IRQ_pending : 1; /*!< [14..14] Latched Event on Frame Discard Due to Source Address + * Match with the Local Address on Port 0 (Loop Filter) */ + __IOM uint32_t frm_dscrd1_IRQ_pending : 1; /*!< [15..15] Latched Event on Frame Discard Due to Source Address + * Match with the Local Address on Port 1 (Loop Filter) */ + uint32_t : 16; + } DLR_IRQ_STAT_ACK_b; + }; + + union + { + __IOM uint32_t DLR_LOC_MAClo; /*!< (@ 0x00003C14) DLR Local MAC Address Low Register */ + + struct + { + __IOM uint32_t LOC_MAC : 32; /*!< [31..0] First 4 octets of the Local MAC address for loop filter */ + } DLR_LOC_MAClo_b; + }; + + union + { + __IOM uint32_t DLR_LOC_MAChi; /*!< (@ 0x00003C18) DLR Local MAC Address High Register */ + + struct + { + __IOM uint32_t LOC_MAC : 16; /*!< [15..0] Last 2 octets of local MAC address for loop filter */ + uint32_t : 16; + } DLR_LOC_MAChi_b; + }; + __IM uint32_t RESERVED103; + + union + { + __IM uint32_t DLR_SUPR_MAClo; /*!< (@ 0x00003C20) DLR Supervisor MAC Address Low Register */ + + struct + { + __IM uint32_t SUPR_MAC : 32; /*!< [31..0] First 4 octets of the active ring supervisor of the + * MAC address extracted from the Source Address field of + * the beacon frame. */ + } DLR_SUPR_MAClo_b; + }; + + union + { + __IM uint32_t DLR_SUPR_MAChi; /*!< (@ 0x00003C24) DLR Supervisor MAC Address High Register */ + + struct + { + __IM uint32_t SUPR_MAC : 16; /*!< [15..0] Last 2 octets of the active ring supervisor of the MAC + * address extracted from the Source Address field of the + * beacon frame. */ + __IM uint32_t PRECE : 8; /*!< [23..16] Precedence value of the ring supervisor extracted from + * the Supervisor precedence field of the beacon frame. */ + uint32_t : 8; + } DLR_SUPR_MAChi_b; + }; + + union + { + __IM uint32_t DLR_STATE_VLAN; /*!< (@ 0x00003C28) DLR Ring Status/VLAN Register */ + + struct + { + __IM uint32_t RINGSTAT : 8; /*!< [7..0] DLR ring state extracted from the Ring State field of + * the beacon frame. */ + __IM uint32_t VLANVALID : 1; /*!< [8..8] VLAN Valid */ + uint32_t : 7; + __IM uint32_t VLANINFO : 16; /*!< [31..16] IEEE 802.1Q VLAN Tag control field extracted from the + * VLAN info field of the beacon frame. */ + } DLR_STATE_VLAN_b; + }; + + union + { + __IM uint32_t DLR_BEC_TMOUT; /*!< (@ 0x00003C2C) DLR Beacon Timeout Register */ + + struct + { + __IM uint32_t BEC_TMOUT : 32; /*!< [31..0] Beacon timeout timer value extracted from the Beacon + * Timeout in microseconds field of the beacon frame. */ + } DLR_BEC_TMOUT_b; + }; + + union + { + __IM uint32_t DLR_BEC_INTRVL; /*!< (@ 0x00003C30) DLR Beacon Interval Register */ + + struct + { + __IM uint32_t BEC_INTRVL : 32; /*!< [31..0] Beacon interval extracted from the Beacon Interval field + * of the beacon frame */ + } DLR_BEC_INTRVL_b; + }; + + union + { + __IM uint32_t DLR_SUPR_IPADR; /*!< (@ 0x00003C34) DLR Supervisor IP Address Register */ + + struct + { + __IM uint32_t SUPR_IPADR : 32; /*!< [31..0] IP address of the ring supervisor extracted from the + * Source IP address field of the beacon frame. A value of + * 0x0 can be received when supervisor has no IP address. */ + } DLR_SUPR_IPADR_b; + }; + + union + { + __IM uint32_t DLR_ETH_STYP_VER; /*!< (@ 0x00003C38) DLR Sub Type/Protocol Version Register */ + + struct + { + __IM uint32_t SUBTYPE : 8; /*!< [7..0] DLR Ring Ether Sub Type extracted from the Ring Sub Type + * field of the beacon frame. */ + __IM uint32_t PROTVER : 8; /*!< [15..8] DLR Ring Protocol Version extracted from the Ring Protocol + * Version field of the beacon frame. */ + __IM uint32_t SPORT : 8; /*!< [23..16] Source port extracted from the Source Port field of + * the beacon frame. */ + uint32_t : 8; + } DLR_ETH_STYP_VER_b; + }; + + union + { + __IM uint32_t DLR_INV_TMOUT; /*!< (@ 0x00003C3C) DLR Beacon Timeout Timer Register */ + + struct + { + __IM uint32_t INV_TMOUT : 32; /*!< [31..0] Last out of range Beacon timeout timer value extracted + * from beacon frame on any of the port. */ + } DLR_INV_TMOUT_b; + }; + + union + { + __IM uint32_t DLR_SEQ_ID; /*!< (@ 0x00003C40) DLR Sequence ID Register */ + + struct + { + __IM uint32_t SEQ_ID : 32; /*!< [31..0] Sequence ID of the last beacon frame extracted from + * the Sequence ID field of the beacon frame on port 0 or + * port 1. Sequence ID of the ignored frames is not stored. */ + } DLR_SEQ_ID_b; + }; + __IM uint32_t RESERVED104[5]; + + union + { + __IOM uint32_t DLR_DSTlo; /*!< (@ 0x00003C58) DLR Beacon Destination Address Low Register */ + + struct + { + __IOM uint32_t DLR_DST : 32; /*!< [31..0] First 4 octets of the beacon frame destination multicast + * address (01-21-6C-00-00-01). */ + } DLR_DSTlo_b; + }; + + union + { + __IOM uint32_t DLR_DSThi; /*!< (@ 0x00003C5C) DLR Beacon Destination Address High Register */ + + struct + { + __IOM uint32_t DLR_DST : 16; /*!< [15..0] Last 2 octets of the beacon frame destination multicast + * address (01-21-6C-00-00-01). */ + uint32_t : 16; + } DLR_DSThi_b; + }; + + union + { + __IM uint32_t DLR_RX_STAT0; /*!< (@ 0x00003C60) DLR Received Frame Statistic Register 0 */ + + struct + { + __IM uint32_t RX_STAT0 : 32; /*!< [31..0] Number of Beacon Frames Received on Port 0 */ + } DLR_RX_STAT0_b; + }; + + union + { + __IM uint32_t DLR_RX_ERR_STAT0; /*!< (@ 0x00003C64) DLR Received Frame Error Statistic Register 0 */ + + struct + { + __IM uint32_t RX_ERR_STAT0 : 32; /*!< [31..0] Number of Beacon Frames Received with CRC Error on Port + * 0 */ + } DLR_RX_ERR_STAT0_b; + }; + __IM uint32_t RESERVED105; + + union + { + __IOM uint32_t DLR_RX_LF_STAT0; /*!< (@ 0x00003C6C) DLR Received Frame Loop Filter Statistic Register + * 0 */ + + struct + { + __IOM uint32_t RX_LF_STAT0 : 8; /*!< [7..0] Number of discarded frames in port 0 due to loop filtering + * when LOOP_FILTER_ENA is set to 1. Saturates at 255. */ + uint32_t : 24; + } DLR_RX_LF_STAT0_b; + }; + + union + { + __IM uint32_t DLR_RX_STAT1; /*!< (@ 0x00003C70) DLR Received Frame Statistic Register 1 */ + + struct + { + __IM uint32_t RX_STAT1 : 32; /*!< [31..0] Number of Beacon Frames Received on Port 1 */ + } DLR_RX_STAT1_b; + }; + + union + { + __IM uint32_t DLR_RX_ERR_STAT1; /*!< (@ 0x00003C74) DLR Received Frame Error Statistic Register 1 */ + + struct + { + __IM uint32_t RX_ERR_STAT1 : 32; /*!< [31..0] Number of Beacon Frames Received with CRC Error on Port + * 1 */ + } DLR_RX_ERR_STAT1_b; + }; + __IM uint32_t RESERVED106; + + union + { + __IOM uint32_t DLR_RX_LF_STAT1; /*!< (@ 0x00003C7C) DLR Received Frame Loop Filter Statistic Register + * 1 */ + + struct + { + __IOM uint32_t RX_LF_STAT1 : 8; /*!< [7..0] Number of discarded frames in port 1 due to loop filtering + * when LOOP_FILTER_ENA is set to 1. Saturates at 255. */ + uint32_t : 24; + } DLR_RX_LF_STAT1_b; + }; + __IM uint32_t RESERVED107[32]; + + union + { + __IOM uint32_t PRP_CONFIG; /*!< (@ 0x00003D00) PRP Configuration Register */ + + struct + { + __IOM uint32_t PRP_ENA : 1; /*!< [0..0] Enable PRP Operation */ + __IOM uint32_t RX_DUP_ACCEPT : 1; /*!< [1..1] Enable Duplicate Accept Mode of Operation at Receive */ + __IOM uint32_t RX_REMOVE_RCT : 1; /*!< [2..2] Allow PRP Port RX to Remove the RCT */ + __IOM uint32_t TX_RCT_MODE : 2; /*!< [4..3] Control Appending the RCT to Transmitted Frames on the + * Redundant Ports */ + __IOM uint32_t TX_RCT_BROADCAST : 1; /*!< [5..5] Should be 1 normally. */ + __IOM uint32_t TX_RCT_MULTICAST : 1; /*!< [6..6] Should be 1 normally. */ + __IOM uint32_t TX_RCT_UNKNOWN : 1; /*!< [7..7] Should be 1 normally. */ + __IOM uint32_t TX_RCT_1588 : 1; /*!< [8..8] Setting this bit affects IEEE 1588 frames that are forwarded + * through the switch (for example, when used as RedBox) to + * both PRP_GROUP ports. Locally generated IEEE 1588 frames + * (peer-delay request/response) are not affected by this + * setting. */ + __IOM uint32_t RCT_LEN_CHK_DIS : 1; /*!< [9..9] When set to 1, disables the RCT length field checking + * against the actual frame length. */ + uint32_t : 6; + __IOM uint32_t PRP_AGE_ENA : 1; /*!< [16..16] Enable History Memory Aging Timer */ + uint32_t : 15; + } PRP_CONFIG_b; + }; + + union + { + __IOM uint32_t PRP_GROUP; /*!< (@ 0x00003D04) PRP Port Group Register */ + + struct + { + __IOM uint32_t PRP_GROUP : 3; /*!< [2..0] Defines which two ports should be treated as redundant + * ports for PRP. */ + uint32_t : 13; + __IOM uint32_t LANB_MASK : 3; /*!< [18..16] Defines which of the ports is considered the LAN B + * port. */ + uint32_t : 13; + } PRP_GROUP_b; + }; + + union + { + __IOM uint32_t PRP_SUFFIX; /*!< (@ 0x00003D08) PRP RCT Suffix */ + + struct + { + __IOM uint32_t PRP_SUFFIX : 16; /*!< [15..0] The Redundancy Control Trailer (RCT) suffix (initial + * value is 0x88FB) */ + uint32_t : 16; + } PRP_SUFFIX_b; + }; + + union + { + __IOM uint32_t PRP_LANID; /*!< (@ 0x00003D0C) PRP LAN Identifier */ + + struct + { + __IOM uint32_t LANAID : 4; /*!< [3..0] LAN A Identifier */ + __IOM uint32_t LANBID : 4; /*!< [7..4] LAN B Identifier */ + uint32_t : 24; + } PRP_LANID_b; + }; + + union + { + __IOM uint32_t DUP_W; /*!< (@ 0x00003D10) PRP Max Duplicate Detection Window Size */ + + struct + { + __IOM uint32_t DUP_W : 8; /*!< [7..0] Maximum Duplicate Detect Window Size */ + uint32_t : 24; + } DUP_W_b; + }; + + union + { + __IOM uint32_t PRP_AGETIME; /*!< (@ 0x00003D14) PRP Aging Time Define Register */ + + struct + { + __IOM uint32_t PRP_AGETIME : 24; /*!< [23..0] Timeout in steps of 32 switch operating clock cycles + * to control aging of duplicate history data. */ + uint32_t : 8; + } PRP_AGETIME_b; + }; + + union + { + __IOM uint32_t PRP_IRQ_CONTROL; /*!< (@ 0x00003D18) PRP Interrupt Control Register */ + + struct + { + __IOM uint32_t MEMTOOLATE : 1; /*!< [0..0] Enable Interrupt for Memory Error Indications. */ + __IOM uint32_t WRONGLAN : 1; /*!< [1..1] Enable interrupt for frames received at a redundant port + * with an invalid LAN identifier in its redundancy trailer. */ + __IOM uint32_t OUTOFSEQ : 1; /*!< [2..2] Enable interrupt for frames received and accepted but + * have an unexpected sequence number. */ + __IOM uint32_t SEQMISSING : 1; /*!< [3..3] Enable interrupt for frames received and accepted that + * caused the history to skip a sequence number that was never + * received (for example, a missing sequence number is being + * ignored and is now treated as a candidate for dropping). */ + uint32_t : 28; + } PRP_IRQ_CONTROL_b; + }; + + union + { + __IOM uint32_t PRP_IRQ_STAT_ACK; /*!< (@ 0x00003D1C) PRP Interrupt Status/ACK Register */ + + struct + { + __IOM uint32_t MEMTOOLATE : 1; /*!< [0..0] Interrupt Pending Indication */ + __IOM uint32_t WRONGLAN : 1; /*!< [1..1] This bit functions the same as MEMTOOLATE bit. */ + __IOM uint32_t OUTOFSEQ : 1; /*!< [2..2] This bit functions the same as MEMTOOLATE bit. */ + __IOM uint32_t SEQMISSING : 1; /*!< [3..3] This bit functions the same as MEMTOOLATE bit. */ + uint32_t : 28; + } PRP_IRQ_STAT_ACK_b; + }; + + union + { + __IOM uint32_t RM_ADDR_CTRL; /*!< (@ 0x00003D20) PRP History Memory Transactions Control Register */ + + struct + { + __IOM uint32_t address : 12; /*!< [11..0] Memory Address for Read and Write Transactions */ + uint32_t : 10; + __IOM uint32_t CLEAR_DYNAMIC : 1; /*!< [22..22] When set to 1, scan the complete table for valid dynamic + * history entries and deletes them (writes entry with all + * 0s). */ + __IOM uint32_t CLEAR_MEMORY : 1; /*!< [23..23] When set to 1, write all memory locations with 0. */ + uint32_t : 1; + __IOM uint32_t WRITE : 1; /*!< [25..25] When set to 1, perform a Single Write Transaction. */ + __IOM uint32_t READ : 1; /*!< [26..26] When set to 1, perform Single Read Transaction. */ + uint32_t : 2; + __IOM uint32_t CLEAR : 1; /*!< [29..29] When set to 1, write all 0s to the entry selected by + * the given address. */ + uint32_t : 1; + __IM uint32_t BUSY : 1; /*!< [31..31] Transaction Busy Indication */ + } RM_ADDR_CTRL_b; + }; + + union + { + __IOM uint32_t RM_DATA; /*!< (@ 0x00003D24) PRP Memory Data Register */ + + struct + { + __IOM uint32_t RM_DATA : 32; /*!< [31..0] Memory data register for read/write transactions controlled + * by RM_ADDR_CTRL. */ + } RM_DATA_b; + }; + + union + { + __IOM uint32_t RM_DATA_HI; /*!< (@ 0x00003D28) PRP Memory Data Higher Register */ + + struct + { + __IOM uint32_t RM_DATA_HI : 32; /*!< [31..0] A Second Data Register */ + } RM_DATA_HI_b; + }; + + union + { + __IM uint32_t RM_STATUS; /*!< (@ 0x00003D2C) PRP Memory Controller Status Indication */ + + struct + { + __IM uint32_t ageaddress : 12; /*!< [11..0] Address of an entry which the aging process inspects + * when the aging timer expires next time. */ + uint32_t : 20; + } RM_STATUS_b; + }; + + union + { + __IOM uint32_t TxSeqTooLate; /*!< (@ 0x00003D30) PRP Frame Transmission Retrieval of Failed Sequence */ + + struct + { + __IOM uint32_t TxSeqTooLate : 4; /*!< [3..0] Retrieval of a Sequence Number Failed */ + uint32_t : 28; + } TxSeqTooLate_b; + }; + + union + { + __IM uint32_t CntErrWrongLanA; /*!< (@ 0x00003D34) PRP Wrong ID LAN-A Count Register */ + + struct + { + __IM uint32_t CntErrWrongLanA : 32; /*!< [31..0] Valid frames received on LAN A which have an RCT (valid + * length + suffix) but LAN ID is not matching LAN A. */ + } CntErrWrongLanA_b; + }; + + union + { + __IM uint32_t CntErrWrongLanB; /*!< (@ 0x00003D38) PRP Wrong ID LAN-B Count Register */ + + struct + { + __IM uint32_t CntErrWrongLanB : 32; /*!< [31..0] Valid frames received on LAN B which have an RCT (valid + * length + suffix) but LAN ID is not matching LAN B. */ + } CntErrWrongLanB_b; + }; + + union + { + __IM uint32_t CntDupLanA; /*!< (@ 0x00003D3C) PRP Duplicate LAN-A Count Register */ + + struct + { + __IM uint32_t CntDupLanA : 32; /*!< [31..0] Valid frames received on LAN A that were dropped by + * duplicate detection. */ + } CntDupLanA_b; + }; + + union + { + __IM uint32_t CntDupLanB; /*!< (@ 0x00003D40) PRP Duplicate LAN-B Count Register */ + + struct + { + __IM uint32_t CntDupLanB : 32; /*!< [31..0] Valid frames received on LAN B that were dropped by + * duplicate detection. */ + } CntDupLanB_b; + }; + + union + { + __IM uint32_t CntOutOfSeqLowA; /*!< (@ 0x00003D44) PRP Sequence Error Low LAN-A Count Register */ + + struct + { + __IM uint32_t CntOutOfSeqLowA : 32; /*!< [31..0] Valid and accepted frames received on LAN A with a sequence + * number less than last window (DUP_W). */ + } CntOutOfSeqLowA_b; + }; + + union + { + __IM uint32_t CntOutOfSeqLowB; /*!< (@ 0x00003D48) PRP Sequence Error Low LAN-B Count Register */ + + struct + { + __IM uint32_t CntOutOfSeqLowB : 32; /*!< [31..0] Valid and accepted frames received on LAN B with a sequence + * number less than last window (DUP_W). */ + } CntOutOfSeqLowB_b; + }; + + union + { + __IM uint32_t CntOutOfSeqA; /*!< (@ 0x00003D4C) PRP Sequence Error LAN-A Count Register */ + + struct + { + __IM uint32_t CntOutOfSeqA : 32; /*!< [31..0] Valid and accepted frames received on LAN A with an + * unexpected sequence number. */ + } CntOutOfSeqA_b; + }; + + union + { + __IM uint32_t CntOutOfSeqB; /*!< (@ 0x00003D50) PRP Sequence Error LAN-B Count Register */ + + struct + { + __IM uint32_t CntOutOfSeqB : 32; /*!< [31..0] Valid and accepted frames received on LAN B with an + * unexpected sequence number. */ + } CntOutOfSeqB_b; + }; + + union + { + __IM uint32_t CntAcceptA; /*!< (@ 0x00003D54) PRP Valid Frame LAN-A Count Register */ + + struct + { + __IM uint32_t CntAcceptA : 32; /*!< [31..0] Valid frames received on LAN A which had a valid sequence + * number in the expected range. */ + } CntAcceptA_b; + }; + + union + { + __IM uint32_t CntAcceptB; /*!< (@ 0x00003D58) PRP Valid Frame LAN-B Count Register */ + + struct + { + __IM uint32_t CntAcceptB : 32; /*!< [31..0] Valid frames received on LAN B which had a valid sequence + * number in the expected range. */ + } CntAcceptB_b; + }; + + union + { + __IM uint32_t CntMissing; /*!< (@ 0x00003D5C) PRP Drop History Adjustment Count */ + + struct + { + __IM uint32_t CntMissing : 32; /*!< [31..0] Indicates adjustment of the drop history as a frame + * was received with a sequence number of expected + history + + 1. This occurs if the same frame was dropped in both + + LAN segments (one sequence number is missing) and the history + + is now extended beyond that sequence number (causing it + + to be treated as drop allowed). */ + } CntMissing_b; + }; + __IM uint32_t RESERVED108[40]; + + union + { + __IOM uint32_t HUB_CONFIG; /*!< (@ 0x00003E00) HUB Configuration Register */ + + struct + { + __IOM uint32_t HUB_ENA : 1; /*!< [0..0] Enable Integrated HUB Operation */ + __IOM uint32_t RETRANSMIT_ENA : 1; /*!< [1..1] Enable Hub Retransmit Capability */ + __IOM uint32_t TRIGGER_MODE : 1; /*!< [2..2] Enable Single Frame Trigger Mode */ + __IOM uint32_t HUB_ISOLATE : 1; /*!< [3..3] Isolate all hub ports from the other ports of the switch + * and allow communication with management port only. It is + * then up to the application of the management port to implement + * some bridging functionality to other ports as required. */ + __IOM uint32_t TIMER_SEL : 1; /*!< [4..4] Select the timer to use for timed triggers */ + uint32_t : 1; + __IOM uint32_t IPG_WAIT : 3; /*!< [8..6] IPG_WAIT */ + __IOM uint32_t CRS_GEN : 1; /*!< [9..9] CRS_GEN */ + __IOM uint32_t PRMB_GEN_DIS : 1; /*!< [10..10] PRMB_GEN_DIS */ + __IOM uint32_t JAM_WAIT_IDLE : 1; /*!< [11..11] JAM_WAIT_IDLE */ + uint32_t : 20; + } HUB_CONFIG_b; + }; + + union + { + __IOM uint32_t HUB_GROUP; /*!< (@ 0x00003E04) HUB Port Group Register */ + + struct + { + __IOM uint32_t HUB_GROUP : 3; /*!< [2..0] Define all ports that should be combined to a Hub Group. */ + uint32_t : 29; + } HUB_GROUP_b; + }; + + union + { + __IOM uint32_t HUB_DEFPORT; /*!< (@ 0x00003E08) HUB Default Port Selection Register */ + + struct + { + __IOM uint32_t HUB_DEFPORT : 3; /*!< [2..0] The default port within the Hub Group where all traffic + * from a port outside the group is forwarded to port (bit + * 0 = port 0, bit 1 = port 1, and bit 2 = port 2). If a frame + * should be forwarded to any of the hub ports, the frame + * is sent to this port only. The copy function of the hub + * copies it to all PHY interfaces of the group eventually. */ + uint32_t : 29; + } HUB_DEFPORT_b; + }; + + union + { + __IOM uint32_t HUB_TRIGGER_IMMEDIATE; /*!< (@ 0x00003E0C) HUB Transmission Trigger Immediate Register */ + + struct + { + __IOM uint32_t HUB_TRIGGER_IMMEDIATE : 3; /*!< [2..0] Trigger immediate transmission of a single frame from + * given port within the hub group (bit 0 = port 0, bit 1 + * = port 1, and bit 2 = port 2). */ + uint32_t : 29; + } HUB_TRIGGER_IMMEDIATE_b; + }; + + union + { + __IOM uint32_t HUB_TRIGGER_AT; /*!< (@ 0x00003E10) HUB Transmission Trigger At Register */ + + struct + { + __IOM uint32_t HUB_TRIGGER_AT : 3; /*!< [2..0] Trigger Transmission of a Single Frame at a Specific + * Time (bit 0 = port 0, bit 1 = port 1, and bit 2 = port + * 2). */ + uint32_t : 29; + } HUB_TRIGGER_AT_b; + }; + + union + { + __IOM uint32_t HUB_TTIME; /*!< (@ 0x00003E14) HUB Transmission Time Define Register */ + + struct + { + __IOM uint32_t HUB_TTIME : 32; /*!< [31..0] Define the Time Value when a Trigger Should Occur */ + } HUB_TTIME_b; + }; + + union + { + __IOM uint32_t HUB_IRQ_CONTROL; /*!< (@ 0x00003E18) HUB Interrupt Control Register */ + + struct + { + __IOM uint32_t RX_TRIGGER : 3; /*!< [2..0] Enable Interrupt on Receive Pattern Match Trigger Function */ + __IOM uint32_t CHANGE_DET : 1; /*!< [3..3] Enable interrupt for hub TX state machine port state + * change request detection */ + __IOM uint32_t TRIGGER_IMMEDIATE : 1; /*!< [4..4] Enable interrupt when hub transmit started after writing + * the HUB_TRIGGER_IMMEDIATE register */ + __IOM uint32_t TRIGGER_TIMER : 1; /*!< [5..5] Enable interrupt when hub transmit started after writing + * the HUB_TRIGGER_TIME register and the timeout value is + * reached (register HUB_TTIME). */ + uint32_t : 26; + } HUB_IRQ_CONTROL_b; + }; + + union + { + __IOM uint32_t HUB_IRQ_STAT_ACK; /*!< (@ 0x00003E1C) HUB Interrupt Status/ACK Register */ + + struct + { + __IOM uint32_t RX_TRIGGER : 3; /*!< [2..0] Interrupt Pending Indication */ + __IOM uint32_t CHANGE_DET : 1; /*!< [3..3] This bit functions the same as RX_TRIGGER bit. */ + __IOM uint32_t TRIGGER_IMMEDIATE : 1; /*!< [4..4] This bit functions the same as RX_TRIGGER bit. */ + __IOM uint32_t TRIGGER_TIMER : 1; /*!< [5..5] This bit functions the same as RX_TRIGGER bit. */ + uint32_t : 26; + } HUB_IRQ_STAT_ACK_b; + }; + + union + { + __IM uint32_t HUB_STATUS; /*!< (@ 0x00003E20) HUB Status Register */ + + struct + { + __IM uint32_t PORTS_ACTIVE : 3; /*!< [2..0] When this bit is 1, it shows the currently active ports + * of the Hub group which are allowed for transmit. */ + uint32_t : 6; + __IM uint32_t TX_ACTIVE : 1; /*!< [9..9] When this bit is 1, the hub global transmit state machine + * has successfully entered Hub mode and is now controlling + * the hub group. */ + __IM uint32_t TX_BUSY : 1; /*!< [10..10] When this bit is 1, the local device currently transmits + * data to all ports within the hub group. */ + __IM uint32_t Speed_OK : 1; /*!< [11..11] When this bit is 1, it indicates that the port speed + * of all group ports match. */ + __IM uint32_t TX_Change_Pending : 1; /*!< [12..12] Indicate a pending change request in the hub transmitter + * that is unsolved and cause the hub to stop operation (no + * longer performing any transmissions). */ + uint32_t : 19; + } HUB_STATUS_b; + }; + + union + { + __IM uint32_t HUB_OPORT_STATUS; /*!< (@ 0x00003E24) HUB Output Port Status Register */ + + struct + { + __IM uint32_t HUB_OPORT_STATUS : 3; /*!< [2..0] Per Output Port Data Available Status */ + uint32_t : 29; + } HUB_OPORT_STATUS_b; + }; + __IM uint32_t RESERVED109[22]; + + union + { + __IOM uint32_t TDMA_CONFIG; /*!< (@ 0x00003E80) TDMA Configuration Register */ + + struct + { + __IOM uint32_t TDMA_ENA : 1; /*!< [0..0] Enable TDMA Scheduler */ + __IM uint32_t WAIT_START : 1; /*!< [1..1] Status bit which is set as long as the scheduler is enabled + * but has not yet reached the time given in register TDMA_START. */ + __IOM uint32_t TIMER_SEL : 1; /*!< [2..2] Select which timer to use as the time source for the + * scheduler */ + uint32_t : 1; + __IM uint32_t RED_PERIOD : 1; /*!< [4..4] Read only bit indicating the current period for Profinet */ + __IOM uint32_t RED_OVRD_ENA : 1; /*!< [5..5] Enables overriding the RED period status, regardless + * of the indication by the TCV. */ + __IOM uint32_t RED_OVRD : 1; /*!< [6..6] Override Value for the RED Period */ + __OM uint32_t IN_CT_WREN : 1; /*!< [7..7] IN_CT_WREN */ + __OM uint32_t OUT_CT_WREN : 1; /*!< [8..8] Enable writing the OUT_CT_ENA control to the egress ports. */ + __OM uint32_t HOLD_REQ_CLR : 1; /*!< [9..9] Writing 1 to this register clears the state of TDMA hold + * request. */ + uint32_t : 2; + __IM uint32_t TIMER_SEL_ACTIVE : 1; /*!< [12..12] Return the current timer being used for the TDMA Scheduler */ + uint32_t : 3; + __IOM uint32_t IN_CT_ENA : 4; /*!< [19..16] On read, return the current status of the ingress Cut-Through + * enable indicated by the TDMA scheduler. On write, override + * the ingress Cut-Through enable if IN_CT_WREN is also 1. */ + uint32_t : 4; + __IOM uint32_t OUT_CT_ENA : 4; /*!< [27..24] On read, return the current status of the egress Cut-Through + * enable indicated by the TDMA scheduler. On write, override + * the egress Cut-Through enable if OUT_CT_WREN is also 1. */ + uint32_t : 4; + } TDMA_CONFIG_b; + }; + + union + { + __IOM uint32_t TDMA_ENA_CTRL; /*!< (@ 0x00003E84) TDMA Scheduling Enable Control Register */ + + struct + { + __IOM uint32_t PORT_ENA : 4; /*!< [3..0] Set to 1 to indicate that a port is operating in TDMA + * mode. When set to 1 for a port, the port does not prefetch + * another frame until the current frame in progress is done + * and if TDMA_PREBUF_DIS in COMMAND_CONFIG is set to 1. This + * helps adding precision to the queue gating operations indicated + * by the TDMA at the expense of loss of line rate. */ + uint32_t : 12; + __IOM uint32_t QGATE_DIS : 8; /*!< [23..16] One bit per output queue. When a bit is set to 1, the + * TDMA scheduler gating commands do not affect the queue + * even if the queue mask in the TCV control data is set to + * 1. */ + __IOM uint32_t QTRIG_DIS : 8; /*!< [31..24] One bit per output queue. When a bit is set to 1, the + * TDMA scheduler triggering commands do not affect the queue + * even if the queue mask in the TCV control data is set to + * 1. */ + } TDMA_ENA_CTRL_b; + }; + + union + { + __IOM uint32_t TDMA_START; /*!< (@ 0x00003E88) TDMA Start Time Set Register */ + + struct + { + __IOM uint32_t TDMA_START : 32; /*!< [31..0] Set the start time for the very first cycle after system + * initialization has completed. The value is compared with + * the system time (selected in TDMA_CONFIG.TIMER_SEL) and + * when it is reached (crossed), the scheduler begins with + * its first cycle. The 2nd cycle is then at TDMA_START + + * TDMA_CYCLE. */ + } TDMA_START_b; + }; + + union + { + __IOM uint32_t TDMA_MODULO; /*!< (@ 0x00003E8C) TDMA System Timer Modulo */ + + struct + { + __IOM uint32_t TDMA_MODULO : 32; /*!< [31..0] The System Timer Modulo */ + } TDMA_MODULO_b; + }; + + union + { + __IOM uint32_t TDMA_CYCLE; /*!< (@ 0x00003E90) TDMA Periodic Cycle Set Register */ + + struct + { + __IOM uint32_t TDMA_CYCLE : 32; /*!< [31..0] The periodic cycle time for the scheduler given in system + * timer time. */ + } TDMA_CYCLE_b; + }; + + union + { + __IOM uint32_t TCV_SEQ_ADDR; /*!< (@ 0x00003E94) TCV Sequence Address Register */ + + struct + { + __IOM uint32_t TCV_S_ADDR : 12; /*!< [11..0] Address to write to or read from in the TCV sequence + * table. */ + uint32_t : 19; + __IOM uint32_t ADDR_AINC : 1; /*!< [31..31] When set to 1, read and write operations performed + * using TCV_SEQ_CTRL causes the address in TCV_S_ADDR to + * auto-increment after the operation. */ + } TCV_SEQ_ADDR_b; + }; + + union + { + __IOM uint32_t TCV_SEQ_CTRL; /*!< (@ 0x00003E98) TCV Sequence Table Control Register */ + + struct + { + __IOM uint32_t START : 1; /*!< [0..0] Indicate this TCV must be executed after the next cycle + * start */ + __IOM uint32_t INT : 1; /*!< [1..1] Indicates this TCV generates an interrupt to the CPU + * when activated */ + __IOM uint32_t TCV_D_IDX : 9; /*!< [10..2] Index to the TCV Data Entry */ + uint32_t : 11; + __IOM uint32_t GPIO : 8; /*!< [29..22] Generic bits that control the output pins ETHSW_TDMAOUTn + * (n = 0 to 7) */ + uint32_t : 1; + __IOM uint32_t READ_MODE : 1; /*!< [31..31] When set to 1, a read operation is performed instead + * of writing to the TCV sequence table. The read data (START, + * INT, TCV_D_IDX[8:0], and GPIO) can be obtained by reading + * this register afterwards. On read, this field always returns + * 0. */ + } TCV_SEQ_CTRL_b; + }; + + union + { + __IOM uint32_t TCV_SEQ_LAST; /*!< (@ 0x00003E9C) TCV Sequence Last Entry */ + + struct + { + __IOM uint32_t LAST : 12; /*!< [11..0] Defines the last entry to read from the TCV sequence + * table when the TDMA scheduler is operating. */ + uint32_t : 4; + __IM uint32_t ACTIVE : 12; /*!< [27..16] Return the active TCV sequence entry. */ + uint32_t : 4; + } TCV_SEQ_LAST_b; + }; + + union + { + __IOM uint32_t TCV_D_ADDR; /*!< (@ 0x00003EA0) TCV Data Address Register */ + + struct + { + __IOM uint32_t ADDR : 9; /*!< [8..0] Address to read from/write to in the TCV data table */ + uint32_t : 22; + __IOM uint32_t AINC_WR_ENA : 1; /*!< [31..31] Auto-Increment Enable */ + } TCV_D_ADDR_b; + }; + + union + { + __IOM uint32_t TCV_D_OFFSET; /*!< (@ 0x00003EA4) TCV Data Offset Register */ + + struct + { + __IOM uint32_t TCV_D_OFFSET : 32; /*!< [31..0] 32-bit time offset for the TCV data entry indicated + * by TCV_D_ADDR. When accessing the table, TCV_D_OFFSET must + * be read or written before TCV_D_CTRL. */ + } TCV_D_OFFSET_b; + }; + + union + { + __IOM uint32_t TCV_D_CTRL; /*!< (@ 0x00003EA8) TCV Data Control Register */ + + struct + { + __IOM uint32_t INC_CTR0 : 1; /*!< [0..0] Increment Control for Counter 0 */ + __IOM uint32_t INC_CTR1 : 1; /*!< [1..1] Increment Control for Counter 1 */ + __IOM uint32_t RED_PERIOD : 1; /*!< [2..2] Period Color Control (for Profinet IRT) */ + __IOM uint32_t OUT_CT_ENA : 1; /*!< [3..3] Output Cut-Through Enable */ + __IOM uint32_t IN_CT_ENA : 1; /*!< [4..4] Input Cut-Through Enable */ + __IOM uint32_t TRIGGER_MODE : 1; /*!< [5..5] Trigger mode enable when set to 1. GATE_MODE must be + * 0, otherwise, GATE_MODE has precedence. */ + __IOM uint32_t GATE_MODE : 1; /*!< [6..6] Gate mode enable when set to 1. */ + __IOM uint32_t HOLD_REQ : 1; /*!< [7..7] Preemption hold request. Generates a hold request to + * ports enabled in PMASK. */ + __IOM uint32_t QGATE : 8; /*!< [15..8] Bits mask, one per output queue */ + __IOM uint32_t PMASK : 4; /*!< [19..16] Bits mask, one per output port */ + uint32_t : 12; + } TCV_D_CTRL_b; + }; + + union + { + __IOM uint32_t TDMA_CTR0; /*!< (@ 0x00003EAC) TDMA Counter 0 */ + + struct + { + __IOM uint32_t TDMA_CTR0 : 32; /*!< [31..0] 32-bit counter that is incremented when the TCV field + * INC_CTR0 is set to 1. */ + } TDMA_CTR0_b; + }; + + union + { + __IOM uint32_t TDMA_CTR1; /*!< (@ 0x00003EB0) TDMA Counter 1 */ + + struct + { + __IOM uint32_t VALUE : 8; /*!< [7..0] Current Counter Value */ + __OM uint32_t WRITE_ENA : 1; /*!< [8..8] Write Enable for VALUE */ + uint32_t : 7; + __IOM uint32_t MAX : 8; /*!< [23..16] Counter Maximum Value */ + __IOM uint32_t INT_VALUE : 8; /*!< [31..24] Interrupt Value */ + } TDMA_CTR1_b; + }; + + union + { + __IOM uint32_t TDMA_TCV_START; /*!< (@ 0x00003EB4) TDMA TCV Sequence Entry Start */ + + struct + { + __IOM uint32_t TDMA_TCV_START : 12; /*!< [11..0] Define the TCV_SEQ entry to start from. */ + uint32_t : 20; + } TDMA_TCV_START_b; + }; + + union + { + __IM uint32_t TIME_LOAD_NEXT; /*!< (@ 0x00003EB8) TDMA Calculated Next Loading Time */ + + struct + { + __IM uint32_t TIME_LOAD_NEXT : 32; /*!< [31..0] Status giving the calculated time the scheduler loads + * into its internal compare register after the current running + * slot end is reached (not the end of the current slot). */ + } TIME_LOAD_NEXT_b; + }; + + union + { + __IOM uint32_t TDMA_IRQ_CONTROL; /*!< (@ 0x00003EBC) TDMA IRQ Control Register */ + + struct + { + __IOM uint32_t TCV_INT_EN : 1; /*!< [0..0] Enable Interrupts Generated by the TCV */ + uint32_t : 12; + __IOM uint32_t CTR1_INT_EN : 1; /*!< [13..13] Enable Interrupts Generated from Counter 1 */ + uint32_t : 18; + } TDMA_IRQ_CONTROL_b; + }; + + union + { + __IOM uint32_t TDMA_IRQ_STAT_ACK; /*!< (@ 0x00003EC0) TDMA IRQ Status/ACK Register */ + + struct + { + __IOM uint32_t TCV_ACK : 1; /*!< [0..0] TCV Execution Event */ + uint32_t : 12; + __IOM uint32_t CTR1_ACK : 1; /*!< [13..13] Counter 1 Event */ + uint32_t : 18; + } TDMA_IRQ_STAT_ACK_b; + }; + + union + { + __IOM uint32_t TDMA_GPIO; /*!< (@ 0x00003EC4) TDMA GPIO Register */ + + struct + { + __IM uint32_t GPIO_STATUS : 8; /*!< [7..0] Status of the GPIO Output Pins */ + uint32_t : 8; + __IOM uint32_t GPIO_MODE : 16; /*!< [31..16] 2 bits per GPIO pin to configure its operating mode */ + } TDMA_GPIO_b; + }; + __IM uint32_t RESERVED110[14]; + + union + { + __IOM uint32_t RXMATCH_CONFIG[4]; /*!< (@ 0x00003F00) RX Pattern Matcher Configuration for Port [0..3] */ + + struct + { + __IOM uint32_t PATTERN_EN : 12; /*!< [11..0] Enable Patterns on the Port (RX) */ + uint32_t : 20; + } RXMATCH_CONFIG_b[4]; + }; + __IM uint32_t RESERVED111[12]; + + union + { + __IOM uint32_t PATTERN_CTRL[12]; /*!< (@ 0x00003F40) RX Pattern Matcher Function Control for Pattern + * [0..11] */ + + struct + { + __IOM uint32_t MATCH_NOT : 1; /*!< [0..0] When set, a match is reported and the functions of this + * control are executed if the pattern does not match. */ + __IOM uint32_t MGMTFWD : 1; /*!< [1..1] When set, the frame is forwarded to the management port + * only (suppressing destination address lookup). */ + __IOM uint32_t DISCARD : 1; /*!< [2..2] When set, the frame is discarded. */ + __IOM uint32_t SET_PRIO : 1; /*!< [3..3] Set frame priority, overriding normal classification. */ + __IOM uint32_t MODE : 2; /*!< [5..4] Selects the operating mode */ + __IOM uint32_t TIMER_SEL_OVR : 1; /*!< [6..6] Overrides the default timer to use by timestamp operations + * when set to 1, using instead the value in TIMER_SEL. */ + __IOM uint32_t FORCE_FORWARD : 1; /*!< [7..7] When set, the frame is forwarded to the ports indicated + * in PORTMASK, ignoring the result from L2 lookups. */ + __IOM uint32_t HUBTRIGGER : 1; /*!< [8..8] When set, the port defined in the PORTMASK setting is + * allowed for transmitting one frame. */ + __IOM uint32_t MATCH_RED : 1; /*!< [9..9] Enable the pattern matcher only when the TDMA indicates + * that this is the RED period. */ + __IOM uint32_t MATCH_NOT_RED : 1; /*!< [10..10] Enable the pattern matcher only when the TDMA indicates + * that this is not the RED period. */ + __IOM uint32_t VLAN_SKIP : 1; /*!< [11..11] When set to 1, for operating modes 1, 2, and 3. The + * first Length/Type after the MAC source address is compared + * against 0x8100. If it matches, a VLAN tag is assumed and + * 4 bytes are skipped. */ + __IOM uint32_t PRIORITY : 3; /*!< [14..12] Priority of the frame used when SET_PRIO is set. The + * priority is used to forward the frame into the corresponding + * output queue of a port. */ + __IOM uint32_t LEARNING_DIS : 1; /*!< [15..15] When set to 1, the hardware learning function is not + * executed. */ + __IOM uint32_t PORTMASK : 4; /*!< [19..16] A port mask used depending on the control bits (for + * example, HUBTRIGGER). */ + uint32_t : 2; + __IOM uint32_t IMC_TRIGGER : 1; /*!< [22..22] When set, the ports defined in the PORTMASK setting + * are allowed for transmitting one frame from the queues + * indicated by QUEUESEL. The trigger request is sent to the + * integrated memory controller. */ + __IOM uint32_t IMC_TRIGGER_DLY : 1; /*!< [23..23] When set, the ports defined in the PORTMASK setting + * are allowed for transmitting one frame from the queues + * indicated by QUEUESEL. The trigger request is sent to the + * integrated memory controller and the event is delayed by + * the value programmed in MMCTL_DLY_QTRIGGER_CTRL. */ + __IOM uint32_t SWAP_BYTES : 1; /*!< [24..24] Applicable only for operating modes 1, 2, and 3. When + * set to 1, the byte order is swapped from the order received + * by the frame. When set to 0, the first byte received by + * the frame is set into position 0 for comparison. When set + * to 1, the first byte received is set into position 3 (for + * mode 1) or position 2 (for mode 2 and 3) for comparison. */ + __IOM uint32_t MATCH_LT : 1; /*!< [25..25] For operating modes 1, 2, and 3. When set to 1, the + * Length/Type field in the frame after the MAC source address + * is compared against the value in length_type in the compare + * register. If VLAN_SKIP is set and the frame has a VLAN + * tag with Length/Type of 0x8100 then the comparison is performed + * in the Length/Type following the VLAN tag. */ + __IOM uint32_t TIMER_SEL : 1; /*!< [26..26] Override value to use when TIMER_SEL_OVR is set to + * 1 for selecting the timer for this frame. */ + uint32_t : 1; + __IOM uint32_t QUEUESEL : 4; /*!< [31..28] A queue selector for the HUBTRIGGER function. Selects + * the queue to trigger a frame, or sets from 0x8 to 0xF to + * select one among all queues. */ + } PATTERN_CTRL_b[12]; + }; + __IM uint32_t RESERVED112[4]; + + union + { + __IOM uint32_t PATTERN_IRQ_CONTROL; /*!< (@ 0x00003F80) RX Pattern Matcher Interrupt Control Register */ + + struct + { + __IOM uint32_t MATCHINT : 12; /*!< [11..0] Enable Interrupt on Receive Pattern Match */ + uint32_t : 4; + __IOM uint32_t ERROR_INT : 4; /*!< [19..16] Enable Interrupt on Internal Pattern Matcher Error */ + uint32_t : 12; + } PATTERN_IRQ_CONTROL_b; + }; + + union + { + __IOM uint32_t PATTERN_IRQ_STAT_ACK; /*!< (@ 0x00003F84) RX Pattern Matcher Interrupt Status/ACK Register */ + + struct + { + __IOM uint32_t MATCHINT : 12; /*!< [11..0] Interrupt pending indication for the corresponding pattern + * match events (see ). */ + uint32_t : 4; + __IOM uint32_t ERROR_INT : 4; /*!< [19..16] Interrupt pending indication for a pattern matcher + * error, per port. */ + uint32_t : 12; + } PATTERN_IRQ_STAT_ACK_b; + }; + + union + { + __IOM uint32_t PTRN_VLANID; /*!< (@ 0x00003F88) Custom VLAN ID Register */ + + struct + { + __IOM uint32_t PTRN_VLANID : 16; /*!< [15..0] Custom VLAN ID to use. The default VLAN ID 0x8100 is + * always considered by the hardware. This value can be changed + * to detect other VLANs like 0x8808. */ + uint32_t : 16; + } PTRN_VLANID_b; + }; + + union + { + __IOM uint32_t PATTERN_SEL; /*!< (@ 0x00003F8C) RX Pattern Number Selection Register */ + + struct + { + __IOM uint32_t PATTERN_SEL : 4; /*!< [3..0] Define the pattern number which is selected for read/write + * through the PTRN_CMP_* and PTRN_MSK_* registers. */ + uint32_t : 28; + } PATTERN_SEL_b; + }; + __IM uint32_t RESERVED113[12]; + + union + { + __IOM uint32_t PTRN_CMP_30; /*!< (@ 0x00003FC0) Pattern Compare Value Bytes 3 .. 0 */ + + struct + { + __IOM uint32_t PTRN_CMP_30 : 32; /*!< [31..0] Pattern Compare Value Bytes 3 .. 0 */ + } PTRN_CMP_30_b; + }; + + union + { + __IOM uint32_t PTRN_CMP_74; /*!< (@ 0x00003FC4) Pattern Compare Value Bytes 7 .. 4 */ + + struct + { + __IOM uint32_t PTRN_CMP_74 : 32; /*!< [31..0] Pattern Compare Value Bytes 7 .. 4 */ + } PTRN_CMP_74_b; + }; + + union + { + __IOM uint32_t PTRN_CMP_118; /*!< (@ 0x00003FC8) Pattern Compare Value Bytes 11 .. 8 */ + + struct + { + __IOM uint32_t PTRN_CMP_118 : 32; /*!< [31..0] Pattern Compare Value Bytes 11 .. 8 */ + } PTRN_CMP_118_b; + }; + __IM uint32_t RESERVED114; + + union + { + __IOM uint32_t PTRN_MSK_30; /*!< (@ 0x00003FD0) Pattern Mask for Bytes 3 .. 0 */ + + struct + { + __IOM uint32_t PTRN_MSK_30 : 32; /*!< [31..0] PTRN_MSK_30 */ + } PTRN_MSK_30_b; + }; + + union + { + __IOM uint32_t PTRN_MSK_74; /*!< (@ 0x00003FD4) Pattern Mask for Bytes 7 .. 4 */ + + struct + { + __IOM uint32_t PTRN_MSK_74 : 32; /*!< [31..0] PTRN_MSK_74 */ + } PTRN_MSK_74_b; + }; + + union + { + __IOM uint32_t PTRN_MSK_118; /*!< (@ 0x00003FD8) Pattern Mask for Bytes 11 .. 8 */ + + struct + { + __IOM uint32_t PTRN_MSK_118 : 32; /*!< [31..0] PTRN_MSK_118 */ + } PTRN_MSK_118_b; + }; +} R_ETHSW_Type; /*!< Size = 16348 (0x3fdc) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief EtherCAT Slave Controller (R_ESC) + */ + +typedef struct /*!< (@ 0x80130000) R_ESC Structure */ +{ + union + { + __IM uint8_t TYPE; /*!< (@ 0x00000000) Type Register */ + + struct + { + __IM uint8_t TYPE : 8; /*!< [7..0] Type of the EtherCAT slave controller */ + } TYPE_b; + }; + + union + { + __IM uint8_t REVISION; /*!< (@ 0x00000001) Revision Register */ + + struct + { + __IM uint8_t REV : 8; /*!< [7..0] Revision of the EtherCAT slave controller */ + } REVISION_b; + }; + + union + { + __IM uint8_t BUILD; /*!< (@ 0x00000002) Build Register */ + + struct + { + __IM uint8_t BUILD : 8; /*!< [7..0] Build number of the EtherCAT slave controller */ + } BUILD_b; + }; + __IM uint8_t RESERVED; + + union + { + __IM uint8_t FMMU_NUM; /*!< (@ 0x00000004) FMMU Supported Register */ + + struct + { + __IM uint8_t NUMFMMU : 8; /*!< [7..0] Number of FMMU channels supported in the EtherCAT slave + * controller */ + } FMMU_NUM_b; + }; + + union + { + __IM uint8_t SYNC_MANAGER; /*!< (@ 0x00000005) SyncManager Supported Register */ + + struct + { + __IM uint8_t NUMSYNC : 8; /*!< [7..0] Number of SyncManager channels supported in the EtherCAT + * slave controller */ + } SYNC_MANAGER_b; + }; + + union + { + __IM uint8_t RAM_SIZE; /*!< (@ 0x00000006) RAM Size Register */ + + struct + { + __IM uint8_t RAMSIZE : 8; /*!< [7..0] Process data RAM size supported in the EtherCAT slave + * controller (unit: KB) */ + } RAM_SIZE_b; + }; + + union + { + __IM uint8_t PORT_DESC; /*!< (@ 0x00000007) Port Descriptor Register */ + + struct + { + __IM uint8_t P0 : 2; /*!< [1..0] Port 0 configuration */ + __IM uint8_t P1 : 2; /*!< [3..2] Port 1 configuration */ + __IM uint8_t P2 : 2; /*!< [5..4] Port 2 configuration */ + __IM uint8_t P3 : 2; /*!< [7..6] Port 3 configuration */ + } PORT_DESC_b; + }; + + union + { + __IM uint16_t FEATURE; /*!< (@ 0x00000008) ESC Features Supported Register */ + + struct + { + __IM uint16_t FMMU : 1; /*!< [0..0] FMMU Operation */ + uint16_t : 1; + __IM uint16_t DC : 1; /*!< [2..2] Distributed Clock */ + __IM uint16_t DCWID : 1; /*!< [3..3] Distributed Clock Width */ + uint16_t : 2; + __IM uint16_t LINKDECMII : 1; /*!< [6..6] Enhanced Link Detection in MII */ + __IM uint16_t FCS : 1; /*!< [7..7] Separate handling of FCS errors */ + __IM uint16_t DCSYNC : 1; /*!< [8..8] Enhanced DC SYNC activation */ + __IM uint16_t LRW : 1; /*!< [9..9] EtherCAT LRW command support */ + __IM uint16_t RWSUPP : 1; /*!< [10..10] EtherCAT read/write command support (BRW, APRW, FPRW) */ + __IM uint16_t FSCONFIG : 1; /*!< [11..11] Fixed FMMU/SyncManager configuration */ + uint16_t : 4; + } FEATURE_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2; + + union + { + __IM uint16_t STATION_ADR; /*!< (@ 0x00000010) Configured Station Address Register */ + + struct + { + __IM uint16_t NODADDR : 16; /*!< [15..0] Node Addressing Address Indication */ + } STATION_ADR_b; + }; + + union + { + __IOM uint16_t STATION_ALIAS; /*!< (@ 0x00000012) Configured Station Alias Register */ + + struct + { + __IOM uint16_t NODALIADDR : 16; /*!< [15..0] Alias Address Indication */ + } STATION_ALIAS_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IM uint8_t WR_REG_ENABLE; /*!< (@ 0x00000020) Write Register Enable Register */ + + struct + { + __IM uint8_t ENABLE : 1; /*!< [0..0] Register Write Protection Unlock */ + uint8_t : 7; + } WR_REG_ENABLE_b; + }; + + union + { + __IM uint8_t WR_REG_PROTECT; /*!< (@ 0x00000021) Write Register Protection Register */ + + struct + { + __IM uint8_t PROTECT : 1; /*!< [0..0] Register Write Protection Specification */ + uint8_t : 7; + } WR_REG_PROTECT_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[3]; + + union + { + __IM uint8_t ESC_WR_ENABLE; /*!< (@ 0x00000030) ESC Write Enable Register */ + + struct + { + __IM uint8_t ENABLE : 1; /*!< [0..0] Register/Memory Write Protection Unlock */ + uint8_t : 7; + } ESC_WR_ENABLE_b; + }; + + union + { + __IM uint8_t ESC_WR_PROTECT; /*!< (@ 0x00000031) ESC Write Protection Register */ + + struct + { + __IM uint8_t PROTECT : 1; /*!< [0..0] Register/Memory Write Protection Specification */ + uint8_t : 7; + } ESC_WR_PROTECT_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + union + { + __IM uint8_t ESC_RESET_ECAT_R; /*!< (@ 0x00000040) ESC Reset ECAT Register for read */ + + struct + { + __IM uint8_t RESET_ECAT : 2; /*!< [1..0] Reset Progress Status */ + uint8_t : 6; + } ESC_RESET_ECAT_R_b; + }; + + union + { + __IM uint8_t ESC_RESET_ECAT_W; /*!< (@ 0x00000040) ESC Reset ECAT Register for write */ + + struct + { + __IM uint8_t RESET_ECAT : 8; /*!< [7..0] Software Reset Setting */ + } ESC_RESET_ECAT_W_b; + }; + }; + + union + { + union + { + __IOM uint8_t ESC_RESET_PDI_R; /*!< (@ 0x00000041) ESC Reset PDI Register for read */ + + struct + { + __IOM uint8_t RESET_PDI : 2; /*!< [1..0] Reset Progress Status */ + uint8_t : 6; + } ESC_RESET_PDI_R_b; + }; + + union + { + __IOM uint8_t ESC_RESET_PDI_W; /*!< (@ 0x00000041) ESC Reset PDI Register for write */ + + struct + { + __IOM uint8_t RESET_PDI : 8; /*!< [7..0] Software Reset Setting */ + } ESC_RESET_PDI_W_b; + }; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[47]; + + union + { + __IM uint32_t ESC_DL_CONTROL; /*!< (@ 0x00000100) ESC DL Control Register */ + + struct + { + __IM uint32_t FWDRULE : 1; /*!< [0..0] Forwarding Rule */ + __IM uint32_t TEMPUSE : 1; /*!< [1..1] Temporary Use of Bits 15 to 8 Settings */ + uint32_t : 6; + __IM uint32_t LP0 : 2; /*!< [9..8] Loop Port 0 Configuration */ + __IM uint32_t LP1 : 2; /*!< [11..10] Loop Port 1 Configuration */ + __IM uint32_t LP2 : 2; /*!< [13..12] Loop Port 2 Configuration */ + __IM uint32_t LP3 : 2; /*!< [15..14] Loop Port 3 Configuration */ + __IM uint32_t RXFIFO : 3; /*!< [18..16] RX FIFO Size */ + uint32_t : 5; + __IM uint32_t STAALIAS : 1; /*!< [24..24] Station Alias Status */ + uint32_t : 7; + } ESC_DL_CONTROL_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IM uint16_t PHYSICAL_RW_OFFSET; /*!< (@ 0x00000108) Physical Read/Write Offset Register */ + + struct + { + __IM uint16_t RWOFFSET : 16; /*!< [15..0] Offset between Read and Write Addresses */ + } PHYSICAL_RW_OFFSET_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12; + + union + { + __IM uint16_t ESC_DL_STATUS; /*!< (@ 0x00000110) ESC DL Status Register */ + + struct + { + __IM uint16_t PDIOPE : 1; /*!< [0..0] PDI/EEPROM Load State Indication */ + __IM uint16_t PDIWDST : 1; /*!< [1..1] PDI Watchdog Timer Status */ + __IM uint16_t ENHLINKD : 1; /*!< [2..2] Enhanced Link Detection Indication */ + uint16_t : 1; + __IM uint16_t PHYP0 : 1; /*!< [4..4] Port 0 Link State Indication */ + __IM uint16_t PHYP1 : 1; /*!< [5..5] Port 1 Link State Indication */ + __IM uint16_t PHYP2 : 1; /*!< [6..6] Port 2 Link State Indication */ + __IM uint16_t PHYP3 : 1; /*!< [7..7] Port 3 Link State Indication */ + __IM uint16_t LP0 : 1; /*!< [8..8] Loop Port 0 State Indication */ + __IM uint16_t COMP0 : 1; /*!< [9..9] Port 0 Communication State Indication */ + __IM uint16_t LP1 : 1; /*!< [10..10] Loop Port 1 State Indication */ + __IM uint16_t COMP1 : 1; /*!< [11..11] Port 1 Communication State Indication */ + __IM uint16_t LP2 : 1; /*!< [12..12] Loop Port 2 State Indication */ + __IM uint16_t COMP2 : 1; /*!< [13..13] Port 2 Communication State Indication */ + __IM uint16_t LP3 : 1; /*!< [14..14] Loop Port 3 State Indication */ + __IM uint16_t COMP3 : 1; /*!< [15..15] Port 3 Communication State Indication */ + } ESC_DL_STATUS_b; + }; + __IM uint16_t RESERVED13; + __IM uint32_t RESERVED14[3]; + + union + { + __IM uint16_t AL_CONTROL; /*!< (@ 0x00000120) AL Control Register */ + + struct + { + __IM uint16_t INISTATE : 4; /*!< [3..0] Change the state transition of the device state machine. */ + __IM uint16_t ERRINDACK : 1; /*!< [4..4] Error Indication Acknowledge (Response) */ + __IM uint16_t DEVICEID : 1; /*!< [5..5] Device ID Request */ + uint16_t : 10; + } AL_CONTROL_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[3]; + + union + { + __IOM uint16_t AL_STATUS; /*!< (@ 0x00000130) AL Status Register */ + + struct + { + __IOM uint16_t ACTSTATE : 4; /*!< [3..0] State Machine State Indication */ + __IOM uint16_t ERR : 1; /*!< [4..4] Error State Indication */ + __IOM uint16_t DEVICEID : 1; /*!< [5..5] Device ID Load State Indication */ + uint16_t : 10; + } AL_STATUS_b; + }; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t AL_STATUS_CODE; /*!< (@ 0x00000134) AL Status Code Register */ + + struct + { + __IOM uint16_t STATUSCODE : 16; /*!< [15..0] AL status code */ + } AL_STATUS_CODE_b; + }; + __IM uint16_t RESERVED18; + + union + { + __IOM uint8_t RUN_LED_OVERRIDE; /*!< (@ 0x00000138) RUN LED Override Register */ + + struct + { + __IOM uint8_t LEDCODE : 4; /*!< [3..0] LED Code Indication (FSM state: Bits [3:0] of the AL + * Status register, AL_STATUS) */ + __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting */ + uint8_t : 3; + } RUN_LED_OVERRIDE_b; + }; + + union + { + __IOM uint8_t ERR_LED_OVERRIDE; /*!< (@ 0x00000139) ERR LED Override Register */ + + struct + { + __IOM uint8_t LEDCODE : 4; /*!< [3..0] LED Code Indication */ + __IOM uint8_t OVERRIDEEN : 1; /*!< [4..4] Override Setting */ + uint8_t : 3; + } ERR_LED_OVERRIDE_b; + }; + __IM uint16_t RESERVED19; + __IM uint32_t RESERVED20; + + union + { + __IM uint8_t PDI_CONTROL; /*!< (@ 0x00000140) PDI Control Register */ + + struct + { + __IM uint8_t PDI : 8; /*!< [7..0] Process Data Interface. In this LSI, the following value + * is indicated. */ + } PDI_CONTROL_b; + }; + + union + { + __IM uint8_t ESC_CONFIG; /*!< (@ 0x00000141) ESC Configuration Register */ + + struct + { + __IM uint8_t DEVEMU : 1; /*!< [0..0] Device emulation (control of AL status) */ + __IM uint8_t ENLALLP : 1; /*!< [1..1] Sets enhanced link detection for all ports */ + __IM uint8_t DCSYNC : 1; /*!< [2..2] Sets the SYNC output unit for distributed clocks (fixed + * to 1 in this LSI) */ + __IM uint8_t DCLATCH : 1; /*!< [3..3] Sets the latch input unit for distributed clocks */ + __IM uint8_t ENLP0 : 1; /*!< [4..4] Port 0 Enhanced Link Detection Setting */ + __IM uint8_t ENLP1 : 1; /*!< [5..5] Port 1 Enhanced Link Detection Setting */ + __IM uint8_t ENLP2 : 1; /*!< [6..6] Port 2 Enhanced Link Detection Setting */ + __IM uint8_t ENLP3 : 1; /*!< [7..7] Port 3 Enhanced Link Detection Setting */ + } ESC_CONFIG_b; + }; + __IM uint16_t RESERVED21; + __IM uint32_t RESERVED22[3]; + + union + { + __IM uint8_t PDI_CONFIG; /*!< (@ 0x00000150) PDI Configuration Register */ + + struct + { + __IM uint8_t ONCHIPBUSCLK : 5; /*!< [4..0] On-Chip Bus Clock Indication */ + __IM uint8_t ONCHIPBUS : 3; /*!< [7..5] On-Chip Bus Type Indication */ + } PDI_CONFIG_b; + }; + + union + { + __IM uint8_t SYNC_LATCH_CONFIG; /*!< (@ 0x00000151) SYNC/LATCH PDI Configuration Register */ + + struct + { + __IM uint8_t SYNC0OUT : 2; /*!< [1..0] SYNC0 Output Driver and Polarity Indication */ + __IM uint8_t SYNCLAT0 : 1; /*!< [2..2] SYNC0/LATCH0 Indication */ + __IM uint8_t SYNC0MAP : 1; /*!< [3..3] SYNC0 State Mapping Indication */ + __IM uint8_t SYNC1OUT : 2; /*!< [5..4] SYNC1 Output Driver and Polarity Indication */ + __IM uint8_t SYNCLAT1 : 1; /*!< [6..6] SYNC1/LATCH1 Indication */ + __IM uint8_t SYNC1MAP : 1; /*!< [7..7] SYNC1 State Mapping Indication */ + } SYNC_LATCH_CONFIG_b; + }; + + union + { + __IM uint16_t EXT_PDI_CONFIG; /*!< (@ 0x00000152) Extended PDI Configuration Register */ + + struct + { + __IM uint16_t DATABUSWID : 2; /*!< [1..0] PDI Data Bus Width Indication */ + uint16_t : 14; + } EXT_PDI_CONFIG_b; + }; + __IM uint32_t RESERVED23[43]; + + union + { + __IM uint16_t ECAT_EVENT_MASK; /*!< (@ 0x00000200) ECAT Event Mask Register */ + + struct + { + __IM uint16_t ECATEVMASK : 16; /*!< [15..0] Event Request Mask Setting */ + } ECAT_EVENT_MASK_b; + }; + __IM uint16_t RESERVED24; + + union + { + __IOM uint32_t AL_EVENT_MASK; /*!< (@ 0x00000204) AL Event Mask Register */ + + struct + { + __IOM uint32_t ALEVMASK : 32; /*!< [31..0] Event Request Mask Setting */ + } AL_EVENT_MASK_b; + }; + __IM uint32_t RESERVED25[2]; + + union + { + __IM uint16_t ECAT_EVENT_REQ; /*!< (@ 0x00000210) ECAT Event Request Register */ + + struct + { + __IM uint16_t DCLATCH : 1; /*!< [0..0] DC Latch Event State Indication */ + uint16_t : 1; + __IM uint16_t DLSTA : 1; /*!< [2..2] DL Status Event State Indication */ + __IM uint16_t ALSTA : 1; /*!< [3..3] AL Status Event State Indication */ + __IM uint16_t SMSTA0 : 1; /*!< [4..4] Mirror value of SyncManager 0 Status Indication */ + __IM uint16_t SMSTA1 : 1; /*!< [5..5] Mirror value of SyncManager 1 Status Indication */ + __IM uint16_t SMSTA2 : 1; /*!< [6..6] Mirror value of SyncManager 2 Status Indication */ + __IM uint16_t SMSTA3 : 1; /*!< [7..7] Mirror value of SyncManager 3 Status Indication */ + __IM uint16_t SMSTA4 : 1; /*!< [8..8] Mirror value of SyncManager 4 Status Indication */ + __IM uint16_t SMSTA5 : 1; /*!< [9..9] Mirror value of SyncManager 5 Status Indication */ + __IM uint16_t SMSTA6 : 1; /*!< [10..10] Mirror value of SyncManager 6 Status Indication */ + __IM uint16_t SMSTA7 : 1; /*!< [11..11] Mirror value of SyncManager 7 Status Indication */ + uint16_t : 4; + } ECAT_EVENT_REQ_b; + }; + __IM uint16_t RESERVED26; + __IM uint32_t RESERVED27[3]; + + union + { + __IM uint32_t AL_EVENT_REQ; /*!< (@ 0x00000220) AL Event Request Register */ + + struct + { + __IM uint32_t ALCTRL : 1; /*!< [0..0] AL Control Event State Indication */ + __IM uint32_t DCLATCH : 1; /*!< [1..1] DC Latch Event State Indication */ + __IM uint32_t DCSYNC0STA : 1; /*!< [2..2] DC SYNC0 State Indication */ + __IM uint32_t DCSYNC1STA : 1; /*!< [3..3] DC SYNC1 State Indication */ + __IM uint32_t SYNCACT : 1; /*!< [4..4] SyncManager Activation Indication */ + uint32_t : 1; + __IM uint32_t WDPD : 1; /*!< [6..6] Watchdog Process Data Indication */ + uint32_t : 1; + __IM uint32_t SMINT0 : 1; /*!< [8..8] SyncManager 0 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0805)) */ + __IM uint32_t SMINT1 : 1; /*!< [9..9] SyncManager 1 interrupt (bit 0 or 1 of the SyncManager + * status register (0x080D)) */ + __IM uint32_t SMINT2 : 1; /*!< [10..10] SyncManager 2 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0815)) */ + __IM uint32_t SMINT3 : 1; /*!< [11..11] SyncManager 3 interrupt (bit 0 or 1 of the SyncManager + * status register (0x081D)) */ + __IM uint32_t SMINT4 : 1; /*!< [12..12] SyncManager 4 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0825)) */ + __IM uint32_t SMINT5 : 1; /*!< [13..13] SyncManager 5 interrupt (bit 0 or 1 of the SyncManager + * status register (0x082D)) */ + __IM uint32_t SMINT6 : 1; /*!< [14..14] SyncManager 6 interrupt (bit 0 or 1 of the SyncManager + * status register (0x0835)) */ + __IM uint32_t SMINT7 : 1; /*!< [15..15] SyncManager 7 interrupt (bit 0 or 1 of the SyncManager + * status register (0x083D)) */ + uint32_t : 16; + } AL_EVENT_REQ_b; + }; + __IM uint32_t RESERVED28[55]; + + union + { + __IM uint16_t RX_ERR_COUNT[3]; /*!< (@ 0x00000300) RX Error Counter [0..2] Register (n = 0 to 2) */ + + struct + { + __IM uint16_t INVFRMCNT : 8; /*!< [7..0] Invalid Frame Counter Value Indication */ + __IM uint16_t RXERRCNT : 8; /*!< [15..8] RX Frame Error Counter Value Indication */ + } RX_ERR_COUNT_b[3]; + }; + __IM uint16_t RESERVED29; + + union + { + __IM uint8_t FWD_RX_ERR_COUNT[3]; /*!< (@ 0x00000308) Forwarded RX Error Counter [0..2] Register (n + * = 0 to 2) */ + + struct + { + __IM uint8_t FWDERRCNT : 8; /*!< [7..0] Forwarded Error Counter Value Indication */ + } FWD_RX_ERR_COUNT_b[3]; + }; + __IM uint8_t RESERVED30; + + union + { + __IM uint8_t ECAT_PROC_ERR_COUNT; /*!< (@ 0x0000030C) ECAT Processing Unit Error Counter Register */ + + struct + { + __IM uint8_t EPUERRCNT : 8; /*!< [7..0] Processing Unit Error Counter Value Indication */ + } ECAT_PROC_ERR_COUNT_b; + }; + + union + { + __IM uint8_t PDI_ERR_COUNT; /*!< (@ 0x0000030D) PDI Error Counter Register */ + + struct + { + __IM uint8_t PDIERRCNT : 8; /*!< [7..0] PDI Error Counter Value Indication */ + } PDI_ERR_COUNT_b; + }; + __IM uint16_t RESERVED31; + + union + { + __IM uint8_t LOST_LINK_COUNT[3]; /*!< (@ 0x00000310) Lost Link Counter [0..2] Register (n = 0 to 2) */ + + struct + { + __IM uint8_t LOSTLINKCNT : 8; /*!< [7..0] Lost Link Counter Value Indication */ + } LOST_LINK_COUNT_b[3]; + }; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[59]; + + union + { + __IM uint16_t WD_DIVIDE; /*!< (@ 0x00000400) Watchdog Divider Register */ + + struct + { + __IM uint16_t WDDIV : 16; /*!< [15..0] Watchdog Clock Frequency Divisor Setting */ + } WD_DIVIDE_b; + }; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; + + union + { + __IM uint16_t WDT_PDI; /*!< (@ 0x00000410) Watchdog Time PDI Register */ + + struct + { + __IM uint16_t WDTIMPDI : 16; /*!< [15..0] Watchdog Overflow Time Setting */ + } WDT_PDI_b; + }; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; + + union + { + __IM uint16_t WDT_DATA; /*!< (@ 0x00000420) Watchdog Time Process Data Register */ + + struct + { + __IM uint16_t WDTIMPD : 16; /*!< [15..0] Watchdog Overflow Time Setting */ + } WDT_DATA_b; + }; + __IM uint16_t RESERVED38; + __IM uint32_t RESERVED39[7]; + + union + { + __IM uint16_t WDS_DATA; /*!< (@ 0x00000440) Watchdog Status Process Data Register */ + + struct + { + __IM uint16_t WDSTAPD : 1; /*!< [0..0] Watchdog State Indication */ + uint16_t : 15; + } WDS_DATA_b; + }; + + union + { + __IM uint8_t WDC_DATA; /*!< (@ 0x00000442) Watchdog Counter Process Data Register */ + + struct + { + __IM uint8_t WDCNTPD : 8; /*!< [7..0] Watchdog Counter Value Indication */ + } WDC_DATA_b; + }; + + union + { + __IM uint8_t WDC_PDI; /*!< (@ 0x00000443) Watchdog Counter PDI Register */ + + struct + { + __IM uint8_t WDCNTPDI : 8; /*!< [7..0] Watchdog Counter Value Indication */ + } WDC_PDI_b; + }; + __IM uint32_t RESERVED40[47]; + + union + { + __IM uint8_t EEP_CONF; /*!< (@ 0x00000500) EEPROM Configuration Register */ + + struct + { + __IM uint8_t CTRLPDI : 1; /*!< [0..0] PDI EEPROM Control */ + __IM uint8_t FORCEECAT : 1; /*!< [1..1] EEPROM Access Right Change */ + uint8_t : 6; + } EEP_CONF_b; + }; + + union + { + __IOM uint8_t EEP_STATE; /*!< (@ 0x00000501) EEPROM PDI Access State Register */ + + struct + { + __IOM uint8_t PDIACCESS : 1; /*!< [0..0] EEPROM Access Right Setting */ + uint8_t : 7; + } EEP_STATE_b; + }; + + union + { + __IOM uint16_t EEP_CONT_STAT; /*!< (@ 0x00000502) EEPROM Control/Status Register */ + + struct + { + __IM uint16_t ECATWREN : 1; /*!< [0..0] ECAT Write Enable */ + uint16_t : 5; + __IM uint16_t READBYTE : 1; /*!< [6..6] EEPROM Read Byte Indication */ + __IM uint16_t PROMSIZE : 1; /*!< [7..7] EEPROM Algorithm Indication */ + __IOM uint16_t COMMAND : 3; /*!< [10..8] Command */ + __IM uint16_t CKSUMERR : 1; /*!< [11..11] Checksum Error Indication */ + __IM uint16_t LOADSTA : 1; /*!< [12..12] EEPROM Loading Status Indication */ + __IM uint16_t ACKCMDERR : 1; /*!< [13..13] Acknowledge/Command Error Indication */ + __IM uint16_t WRENERR : 1; /*!< [14..14] Write Enable Error Indication */ + __IM uint16_t BUSY : 1; /*!< [15..15] EEPROM Interface State Indication */ + } EEP_CONT_STAT_b; + }; + + union + { + __IOM uint32_t EEP_ADR; /*!< (@ 0x00000504) EEPROM Address Register */ + + struct + { + __IOM uint32_t ADDRESS : 32; /*!< [31..0] EEPROM Address Setting */ + } EEP_ADR_b; + }; + + union + { + __IOM uint32_t EEP_DATA; /*!< (@ 0x00000508) EEPROM Data Register */ + + struct + { + __IOM uint32_t LODATA : 16; /*!< [15..0] Data to be written to the EEPROM or data read from the + * EEPROM (lower 2 bytes) */ + __IM uint32_t HIDATA : 16; /*!< [31..16] Data read from the EEPROM (upper 2 bytes) */ + } EEP_DATA_b; + }; + __IM uint32_t RESERVED41; + + union + { + __IOM uint16_t MII_CONT_STAT; /*!< (@ 0x00000510) MII Management Control/Status Register */ + + struct + { + __IM uint16_t WREN : 1; /*!< [0..0] Write Enable */ + __IM uint16_t PDICTRL : 1; /*!< [1..1] PDI Control Indication */ + __IM uint16_t MILINK : 1; /*!< [2..2] MI Link Detection */ + __IM uint16_t PHYOFFSET : 5; /*!< [7..3] PHY Address Offset Indication */ + __IOM uint16_t COMMAND : 2; /*!< [9..8] Command */ + uint16_t : 3; + __IOM uint16_t READERR : 1; /*!< [13..13] Read Error Indication */ + __IM uint16_t CMDERR : 1; /*!< [14..14] Command Error Indication */ + __IM uint16_t BUSY : 1; /*!< [15..15] MII Management State Indication */ + } MII_CONT_STAT_b; + }; + + union + { + __IOM uint8_t PHY_ADR; /*!< (@ 0x00000512) PHY Address Register */ + + struct + { + __IOM uint8_t PHYADDR : 5; /*!< [4..0] PHY Address Setting */ + uint8_t : 3; + } PHY_ADR_b; + }; + + union + { + __IOM uint8_t PHY_REG_ADR; /*!< (@ 0x00000513) PHY Register Address Register */ + + struct + { + __IOM uint8_t PHYREGADDR : 5; /*!< [4..0] Address of PHY register */ + uint8_t : 3; + } PHY_REG_ADR_b; + }; + + union + { + __IOM uint16_t PHY_DATA; /*!< (@ 0x00000514) PHY Data Register */ + + struct + { + __IOM uint16_t PHYREGDATA : 16; /*!< [15..0] PHY Register Data Indication/Setting */ + } PHY_DATA_b; + }; + + union + { + __IM uint8_t MII_ECAT_ACS_STAT; /*!< (@ 0x00000516) MII Management ECAT Access State Register */ + + struct + { + __IM uint8_t ACSMII : 1; /*!< [0..0] MII Management Interface Access Right Setting */ + uint8_t : 7; + } MII_ECAT_ACS_STAT_b; + }; + + union + { + __IOM uint8_t MII_PDI_ACS_STAT; /*!< (@ 0x00000517) MII Management PDI Access State Register */ + + struct + { + __IOM uint8_t ACSMII : 1; /*!< [0..0] Right of access to the MII management interface */ + __IM uint8_t FORPDI : 1; /*!< [1..1] Forced change of access by the PDI (forced change of + * bit 0) */ + uint8_t : 6; + } MII_PDI_ACS_STAT_b; + }; + __IM uint32_t RESERVED42[58]; + __IOM R_ESC_FMMU_Type FMMU[8]; /*!< (@ 0x00000600) FMMU [0..7] Registers (n = 0 to 7) */ + __IM uint32_t RESERVED43[96]; + __IOM R_ESC_SM_Type SM[8]; /*!< (@ 0x00000800) SyncManager [0..7] Registers (n = 0 to 7) */ + __IM uint32_t RESERVED44[48]; + + union + { + __IM uint32_t DC_RCV_TIME_PORT[3]; /*!< (@ 0x00000900) Receive Time Port [0..2] Register */ + + struct + { + __IM uint32_t RCVTIME0 : 32; /*!< [31..0] Receive Time Indication/Latch */ + } DC_RCV_TIME_PORT_b[3]; + }; + __IM uint32_t RESERVED45; + __IM uint32_t DC_SYS_TIME_L; /*!< (@ 0x00000910) System Time Register L */ + __IM uint32_t DC_SYS_TIME_H; /*!< (@ 0x00000914) System Time Register H */ + __IM uint32_t DC_RCV_TIME_UNIT_L; /*!< (@ 0x00000918) Receive Time ECAT Processing Unit Register L */ + __IM uint32_t DC_RCV_TIME_UNIT_H; /*!< (@ 0x0000091C) Receive Time ECAT Processing Unit Register H */ + __IM uint32_t DC_SYS_TIME_OFFSET_L; /*!< (@ 0x00000920) System Time Offset Register L */ + __IM uint32_t DC_SYS_TIME_OFFSET_H; /*!< (@ 0x00000924) System Time Offset Register H */ + + union + { + __IM uint32_t DC_SYS_TIME_DELAY; /*!< (@ 0x00000928) System Time Delay Register */ + + struct + { + __IM uint32_t SYSTIMDLY : 32; /*!< [31..0] Propagation Delay Indication */ + } DC_SYS_TIME_DELAY_b; + }; + + union + { + __IM uint32_t DC_SYS_TIME_DIFF; /*!< (@ 0x0000092C) System Time Difference Register */ + + struct + { + __IM uint32_t DIFF : 31; /*!< [30..0] System Time Mean Difference Indication */ + __IM uint32_t LCP : 1; /*!< [31..31] System Time Greater/Less Indication */ + } DC_SYS_TIME_DIFF_b; + }; + + union + { + __IM uint16_t DC_SPEED_COUNT_START; /*!< (@ 0x00000930) Speed Counter Start Register */ + + struct + { + __IM uint16_t SPDCNTSTRT : 15; /*!< [14..0] Drift Correction Bandwidth Setting */ + uint16_t : 1; + } DC_SPEED_COUNT_START_b; + }; + + union + { + __IM uint16_t DC_SPEED_COUNT_DIFF; /*!< (@ 0x00000932) Speed Counter Difference Register */ + + struct + { + __IM uint16_t SPDCNTDIFF : 16; /*!< [15..0] Clock Period Deviation Indication */ + } DC_SPEED_COUNT_DIFF_b; + }; + + union + { + __IM uint8_t DC_SYS_TIME_DIFF_FIL_DEPTH; /*!< (@ 0x00000934) System Time Difference Filter Depth Register */ + + struct + { + __IM uint8_t SYSTIMDEP : 4; /*!< [3..0] Filter Depth Setting */ + uint8_t : 4; + } DC_SYS_TIME_DIFF_FIL_DEPTH_b; + }; + + union + { + __IM uint8_t DC_SPEED_COUNT_FIL_DEPTH; /*!< (@ 0x00000935) Speed Counter Filter Depth Register */ + + struct + { + __IM uint8_t CLKPERDEP : 4; /*!< [3..0] Filter Depth Setting */ + uint8_t : 4; + } DC_SPEED_COUNT_FIL_DEPTH_b; + }; + __IM uint16_t RESERVED46; + __IM uint32_t RESERVED47[18]; + + union + { + __IM uint8_t DC_CYC_CONT; /*!< (@ 0x00000980) Cyclic Unit Control Register */ + + struct + { + __IM uint8_t SYNCOUT : 1; /*!< [0..0] SYNC Output Unit Control Setting */ + uint8_t : 3; + __IM uint8_t LATCH0 : 1; /*!< [4..4] Latch Input Unit 0 Control Setting */ + __IM uint8_t LATCH1 : 1; /*!< [5..5] Latch Input Unit 1 Control Setting */ + uint8_t : 2; + } DC_CYC_CONT_b; + }; + + union + { + __IOM uint8_t DC_ACT; /*!< (@ 0x00000981) Activation Register */ + + struct + { + __IOM uint8_t SYNCACT : 1; /*!< [0..0] Sync Output Unit Activation */ + __IOM uint8_t SYNC0 : 1; /*!< [1..1] SYNC0 Output Setting */ + __IOM uint8_t SYNC1 : 1; /*!< [2..2] SYNC1 Output Setting */ + __IOM uint8_t AUTOACT : 1; /*!< [3..3] SYNC Output Unit Activation */ + __IOM uint8_t EXTSTARTTIME : 1; /*!< [4..4] Start Time Cyclic Operation Extension */ + __IOM uint8_t STARTTIME : 1; /*!< [5..5] Start Time Plausibility */ + __IOM uint8_t NEARFUTURE : 1; /*!< [6..6] Near Future Range Setting */ + __IOM uint8_t DBGPULSE : 1; /*!< [7..7] Debug Pulse Setting */ + } DC_ACT_b; + }; + + union + { + __IM uint16_t DC_PULSE_LEN; /*!< (@ 0x00000982) SYNC Signal Pulse Length Register */ + + struct + { + __IM uint16_t PULSELEN : 16; /*!< [15..0] SYNC Signal Pulse Length Indication */ + } DC_PULSE_LEN_b; + }; + + union + { + __IM uint8_t DC_ACT_STAT; /*!< (@ 0x00000984) Activation Status Register */ + + struct + { + __IM uint8_t SYNC0ACT : 1; /*!< [0..0] SYNC0 Status Indication */ + __IM uint8_t SYNC1ACT : 1; /*!< [1..1] SYNC1 Status Indication */ + __IM uint8_t STARTTIME : 1; /*!< [2..2] Plausibility Result Indication */ + uint8_t : 5; + } DC_ACT_STAT_b; + }; + __IM uint8_t RESERVED48; + __IM uint16_t RESERVED49; + __IM uint32_t RESERVED50; + __IM uint16_t RESERVED51; + + union + { + __IM uint8_t DC_SYNC0_STAT; /*!< (@ 0x0000098E) SYNC0 Status Register */ + + struct + { + __IM uint8_t SYNC0STA : 1; /*!< [0..0] SYNC0 State Indication */ + uint8_t : 7; + } DC_SYNC0_STAT_b; + }; + + union + { + __IM uint8_t DC_SYNC1_STAT; /*!< (@ 0x0000098F) SYNC1 Status Register */ + + struct + { + __IM uint8_t SYNC1STA : 1; /*!< [0..0] SYNC1 State Indication */ + uint8_t : 7; + } DC_SYNC1_STAT_b; + }; + __IOM uint32_t DC_CYC_START_TIME_L; /*!< (@ 0x00000990) Start Time Cyclic Operation/Next SYNC0 Pulse + * Register L */ + __IOM uint32_t DC_CYC_START_TIME_H; /*!< (@ 0x00000994) Start Time Cyclic Operation/Next SYNC0 Pulse + * Register H */ + __IM uint32_t DC_NEXT_SYNC1_PULSE_L; /*!< (@ 0x00000998) Next SYNC1 Pulse Register L */ + __IM uint32_t DC_NEXT_SYNC1_PULSE_H; /*!< (@ 0x0000099C) Next SYNC1 Pulse Register H */ + + union + { + __IOM uint32_t DC_SYNC0_CYC_TIME; /*!< (@ 0x000009A0) SYNC0 Cycle Time Register */ + + struct + { + __IOM uint32_t SYNC0CYC : 32; /*!< [31..0] Time Between Consecutive SYNC0 Pulses */ + } DC_SYNC0_CYC_TIME_b; + }; + + union + { + __IOM uint32_t DC_SYNC1_CYC_TIME; /*!< (@ 0x000009A4) SYNC1 Cycle Time Register */ + + struct + { + __IOM uint32_t SYNC1CYC : 32; /*!< [31..0] Time between SYNC1 and SYNC0 Pulses */ + } DC_SYNC1_CYC_TIME_b; + }; + + union + { + __IOM uint8_t DC_LATCH0_CONT; /*!< (@ 0x000009A8) Latch 0 Control Register */ + + struct + { + __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 0 Positive Edge Function Setting */ + __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 0 Negative Edge Function Setting */ + uint8_t : 6; + } DC_LATCH0_CONT_b; + }; + + union + { + __IOM uint8_t DC_LATCH1_CONT; /*!< (@ 0x000009A9) Latch 1 Control Register */ + + struct + { + __IOM uint8_t POSEDGE : 1; /*!< [0..0] Latch 1 Positive Edge Function Setting */ + __IOM uint8_t NEGEDGE : 1; /*!< [1..1] Latch 1 Negative Edge Function Setting */ + uint8_t : 6; + } DC_LATCH1_CONT_b; + }; + __IM uint16_t RESERVED52[2]; + + union + { + __IM uint8_t DC_LATCH0_STAT; /*!< (@ 0x000009AE) Latch 0 Status Register */ + + struct + { + __IM uint8_t EVENTPOS : 1; /*!< [0..0] Latch 0 Positive Edge Event Indication */ + __IM uint8_t EVENTNEG : 1; /*!< [1..1] Latch 0 Negative Edge Event Indication */ + __IM uint8_t PINSTATE : 1; /*!< [2..2] Latch 0 Input Pin State Indication */ + uint8_t : 5; + } DC_LATCH0_STAT_b; + }; + + union + { + __IM uint8_t DC_LATCH1_STAT; /*!< (@ 0x000009AF) Latch 1 Status Register */ + + struct + { + __IM uint8_t EVENTPOS : 1; /*!< [0..0] Latch 1 Positive Edge Event Indication */ + __IM uint8_t EVENTNEG : 1; /*!< [1..1] Latch 1 Negative Edge Event Indication */ + __IM uint8_t PINSTATE : 1; /*!< [2..2] Latch 1 Input Pin State Indication */ + uint8_t : 5; + } DC_LATCH1_STAT_b; + }; + __IM uint32_t DC_LATCH0_TIME_POS_L; /*!< (@ 0x000009B0) Latch 0 Time Positive Edge Register L */ + __IM uint32_t DC_LATCH0_TIME_POS_H; /*!< (@ 0x000009B4) Latch 0 Time Positive Edge Register H */ + __IM uint32_t DC_LATCH0_TIME_NEG_L; /*!< (@ 0x000009B8) Latch 0 Time Negative Edge Register L */ + __IM uint32_t DC_LATCH0_TIME_NEG_H; /*!< (@ 0x000009BC) Latch 0 Time Negative Edge Register H */ + __IM uint32_t DC_LATCH1_TIME_POS_L; /*!< (@ 0x000009C0) Latch 1 Time Positive Edge Register L */ + __IM uint32_t DC_LATCH1_TIME_POS_H; /*!< (@ 0x000009C4) Latch 1 Time Positive Edge Register H */ + __IM uint32_t DC_LATCH1_TIME_NEG_L; /*!< (@ 0x000009C8) Latch 1 Time Negative Edge Register L */ + __IM uint32_t DC_LATCH1_TIME_NEG_H; /*!< (@ 0x000009CC) Latch 1 Time Negative Edge Register H */ + __IM uint32_t RESERVED53[8]; + + union + { + __IM uint32_t DC_ECAT_CNG_EV_TIME; /*!< (@ 0x000009F0) Buffer Change Event Time Register */ + + struct + { + __IM uint32_t ECATCHANGE : 32; /*!< [31..0] Local Time Indication */ + } DC_ECAT_CNG_EV_TIME_b; + }; + __IM uint32_t RESERVED54; + + union + { + __IM uint32_t DC_PDI_START_EV_TIME; /*!< (@ 0x000009F8) PDI Buffer Start Event Time Register */ + + struct + { + __IM uint32_t PDISTART : 32; /*!< [31..0] Local Time Indication */ + } DC_PDI_START_EV_TIME_b; + }; + + union + { + __IM uint32_t DC_PDI_CNG_EV_TIME; /*!< (@ 0x000009FC) PDI Buffer Change Event Time Register */ + + struct + { + __IM uint32_t PDICHANGE : 32; /*!< [31..0] Local Time Indication */ + } DC_PDI_CNG_EV_TIME_b; + }; + __IM uint32_t RESERVED55[256]; + __IM uint32_t PRODUCT_ID_L; /*!< (@ 0x00000E00) Product ID Register L */ + __IM uint32_t PRODUCT_ID_H; /*!< (@ 0x00000E04) Product ID Register H */ + + union + { + __IM uint32_t VENDOR_ID_L; /*!< (@ 0x00000E08) Vendor ID Register L */ + + struct + { + __IM uint32_t VENDORID : 32; /*!< [31..0] Vendor ID Indication */ + } VENDOR_ID_L_b; + }; +} R_ESC_Type; /*!< Size = 3596 (0xe0c) */ + +/* =========================================================================================================================== */ +/* ================ R_USBHC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 HS Host Module (R_USBHC) + */ + +typedef struct /*!< (@ 0x80200000) R_USBHC Structure */ +{ + union + { + __IM uint32_t HCREVISION; /*!< (@ 0x00000000) HcRevision Register */ + + struct + { + __IM uint32_t REV : 8; /*!< [7..0] HCI revision */ + uint32_t : 24; + } HCREVISION_b; + }; + + union + { + __IOM uint32_t HCCONTROL; /*!< (@ 0x00000004) HcControl Register */ + + struct + { + __IOM uint32_t CBSR : 2; /*!< [1..0] Control/bulk transfer service ratio (ControlBulkServiceRatio) */ + __IOM uint32_t PLE : 1; /*!< [2..2] Periodic list setting (PeriodicListEnable) */ + __IOM uint32_t IE : 1; /*!< [3..3] Isochronous ED processing setting (IsochronousEnable) */ + __IOM uint32_t CLE : 1; /*!< [4..4] Control list processing setting (ControlListEnable) */ + __IOM uint32_t BLE : 1; /*!< [5..5] Bulk list processing setting (BulkListEnable) */ + __IOM uint32_t HCFS : 2; /*!< [7..6] Host logic operation status (Host Controller FunctionalState) */ + __IOM uint32_t IR : 1; /*!< [8..8] HcInterruptStatus interrupt path setting (InterruptRouting) */ + __IOM uint32_t RWC : 1; /*!< [9..9] Remote Wakeup support setting (RemoteWakeUpConnect) */ + __IOM uint32_t RWE : 1; /*!< [10..10] PME assertion control (RemoteWakeUpEnable) */ + uint32_t : 21; + } HCCONTROL_b; + }; + + union + { + __IOM uint32_t HCCOMMANDSTATUS; /*!< (@ 0x00000008) HcCommandStatus Register */ + + struct + { + __OM uint32_t HCR : 1; /*!< [0..0] Host logic software reset start (HostController Reset) */ + __IOM uint32_t CLF : 1; /*!< [1..1] Control list TD (ControlList Filled) */ + __IOM uint32_t BLF : 1; /*!< [2..2] Bulk list TD (BulkListFilled) */ + __OM uint32_t OCR : 1; /*!< [3..3] Host logic control right change (OwnershipChangeRequest) */ + uint32_t : 12; + __IM uint32_t SOC : 2; /*!< [17..16] Schedule overrun count (Scheduling OverrunCount) */ + uint32_t : 14; + } HCCOMMANDSTATUS_b; + }; + + union + { + __IOM uint32_t HCINTERRUPTSTATUS; /*!< (@ 0x0000000C) HcInterruptStatus Register */ + + struct + { + __IOM uint32_t SO : 1; /*!< [0..0] USB schedule overrun (Scheduling Overrun) */ + __IOM uint32_t WDH : 1; /*!< [1..1] Host logic HccaDoneHead update (Writeback Done Head) */ + __IOM uint32_t SF : 1; /*!< [2..2] HccaFrameNumber update (StartOfFrame) */ + __IOM uint32_t RD : 1; /*!< [3..3] Resume detection (Resume Detected) */ + __IOM uint32_t UE : 1; /*!< [4..4] USB non-related system error detection (Unrecoverable + * Error) */ + __IOM uint32_t FNO : 1; /*!< [5..5] FrameNumber bit MSB change (Frame Number Overflow) */ + __IOM uint32_t RHSC : 1; /*!< [6..6] HcRhStatus/HcRhPortStatus register status (RootHubStatus + * Change) */ + uint32_t : 23; + __IOM uint32_t OC : 1; /*!< [30..30] Host logic control right change (OwnershipChange) */ + uint32_t : 1; + } HCINTERRUPTSTATUS_b; + }; + + union + { + __IOM uint32_t HCINTERRUPTENABLE; /*!< (@ 0x00000010) HcInterruptEnable Register */ + + struct + { + __IOM uint32_t SOE : 1; /*!< [0..0] SO interrupt source enable (Scheduling OverrunEnable) */ + __IOM uint32_t WDHE : 1; /*!< [1..1] WDH interrupt source enable (WritebackDone HeadEnable) */ + __IOM uint32_t SFE : 1; /*!< [2..2] SF interrupt source enable (StartOfFrame) */ + __IOM uint32_t RDE : 1; /*!< [3..3] RD interrupt source enable (Resume DetectedEnable) */ + __IOM uint32_t UEE : 1; /*!< [4..4] UE interrupt source enable (Unrecoverable ErrorEnable) */ + __IOM uint32_t FNOE : 1; /*!< [5..5] FNO interrupt source enable (FrameNumber OverflowEnable) */ + __IOM uint32_t RHSCE : 1; /*!< [6..6] RHSC interrupt source enable (RootHubStatus ChangeEnable) */ + uint32_t : 23; + __IOM uint32_t OCE : 1; /*!< [30..30] OC interrupt source enable (OwnershipChangeEnable) */ + __IOM uint32_t MIE : 1; /*!< [31..31] Interrupt 8 source enable (MasterInterrupt Enable) */ + } HCINTERRUPTENABLE_b; + }; + + union + { + __IOM uint32_t HCINTERRUPTDISABLE; /*!< (@ 0x00000014) HcInterruptDisable Register */ + + struct + { + __IOM uint32_t SOD : 1; /*!< [0..0] SO interrupt source disable (Scheduling Overrun Disable) */ + __IOM uint32_t WDHD : 1; /*!< [1..1] WDH interrupt source disable (Writeback DoneHead Disable) */ + __IOM uint32_t SFD : 1; /*!< [2..2] SF interrupt source disable (StartOfFrame Disable) */ + __IOM uint32_t RDD : 1; /*!< [3..3] RD interrupt source disable (Resume Detected Disable) */ + __IOM uint32_t UED : 1; /*!< [4..4] UE interrupt source disable (Unrecoverable ErrorDisable) */ + __IOM uint32_t FNOD : 1; /*!< [5..5] FNO interrupt source disable (FrameNumberOverflow Disable) */ + __IOM uint32_t RHSCD : 1; /*!< [6..6] RHSC interrupt source disable (RootHub StatusChange Disable) */ + uint32_t : 23; + __IOM uint32_t OCD : 1; /*!< [30..30] OC interrupt source disable (OwnershipChangeDisable) */ + __IOM uint32_t MID : 1; /*!< [31..31] Interrupt 8 source disable (Master Interrupt Disable) */ + } HCINTERRUPTDISABLE_b; + }; + + union + { + __IOM uint32_t HCHCCA; /*!< (@ 0x00000018) HcHCCA Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t RAMBA : 24; /*!< [31..8] RAM base address setting */ + } HCHCCA_b; + }; + + union + { + __IM uint32_t HCPERIODCCURRENTIED; /*!< (@ 0x0000001C) HcPeriodicCurrentED Register */ + + struct + { + uint32_t : 4; + __IM uint32_t PCED : 28; /*!< [31..4] ED physical address (PeriodicCurrentED) */ + } HCPERIODCCURRENTIED_b; + }; + + union + { + __IOM uint32_t HCCONTROLHEADED; /*!< (@ 0x00000020) HcControlHeadED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t CHED : 28; /*!< [31..4] Start ED physical address (ControlHeadED) */ + } HCCONTROLHEADED_b; + }; + + union + { + __IOM uint32_t HCCONTROLCURRENTED; /*!< (@ 0x00000024) HcControlCurrentED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t CCED : 28; /*!< [31..4] ED physical address (ControlCurrentED) */ + } HCCONTROLCURRENTED_b; + }; + + union + { + __IOM uint32_t HCBULKHEADED; /*!< (@ 0x00000028) HcBulkHeadED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t BHED : 28; /*!< [31..4] Start ED physical address (BulkHeadED) */ + } HCBULKHEADED_b; + }; + + union + { + __IOM uint32_t HCBULKCURRENTED; /*!< (@ 0x0000002C) HcBulkCurrentED Register */ + + struct + { + uint32_t : 4; + __IOM uint32_t BCED : 28; /*!< [31..4] ED physical address (BulkCurrentED) */ + } HCBULKCURRENTED_b; + }; + + union + { + __IM uint32_t HCDONEHEAD; /*!< (@ 0x00000030) HcDoneHead Register */ + + struct + { + uint32_t : 4; + __IM uint32_t DH : 28; /*!< [31..4] HcDoneHead physical address (DoneHead) */ + } HCDONEHEAD_b; + }; + + union + { + __IOM uint32_t HCFMINTERVAL; /*!< (@ 0x00000034) HcFmInterval Register */ + + struct + { + __IOM uint32_t FI : 14; /*!< [13..0] Frame interval setting (FrameInterval) */ + uint32_t : 2; + __IOM uint32_t FSMPS : 15; /*!< [30..16] FS transfer packet maximum size setting (FSLagest DataPacket) */ + __IOM uint32_t FIT : 1; /*!< [31..31] Frame synchronization (FrameInterval Toggle) */ + } HCFMINTERVAL_b; + }; + + union + { + __IM uint32_t HCFNREMAINING; /*!< (@ 0x00000038) HcFmRemaining Register */ + + struct + { + __IM uint32_t FR : 14; /*!< [13..0] Down counter frame (FrameRemaining) */ + uint32_t : 17; + __IM uint32_t FRT : 1; /*!< [31..31] Frame synchronization (FrameRemainingToggle) */ + } HCFNREMAINING_b; + }; + + union + { + __IM uint32_t HCFMNUMBER; /*!< (@ 0x0000003C) HcFmNumber Register */ + + struct + { + __IM uint32_t FN : 16; /*!< [15..0] Elapsed frame number (FrameNumber) */ + uint32_t : 16; + } HCFMNUMBER_b; + }; + + union + { + __IOM uint32_t HCPERIODSTART; /*!< (@ 0x00000040) HcPeriodicStart Register */ + + struct + { + __IOM uint32_t PS : 14; /*!< [13..0] Periodic list processing start time (PeriodicStart) */ + uint32_t : 18; + } HCPERIODSTART_b; + }; + + union + { + __IOM uint32_t HCLSTHRESHOLD; /*!< (@ 0x00000044) HcLSThreshold Register */ + + struct + { + __IOM uint32_t LS : 12; /*!< [11..0] Transferrable threshold (LSThreshold) */ + uint32_t : 20; + } HCLSTHRESHOLD_b; + }; + + union + { + __IOM uint32_t HCRHDESCRIPTORA; /*!< (@ 0x00000048) HcRhDescriptorA Register */ + + struct + { + __IM uint32_t NDP : 8; /*!< [7..0] Downstream port number (NumberDownstreamPorts) */ + __IOM uint32_t PSM : 1; /*!< [8..8] Power switch control (PowerSwitchingMode) */ + __IOM uint32_t NPS : 1; /*!< [9..9] Power control (NoPower Switching) */ + __IM uint32_t DT : 1; /*!< [10..10] Device type (DeviceType) */ + __IOM uint32_t OCPM : 1; /*!< [11..11] Overcurrent state reporting (OverCurrentProtection + * Mode) */ + __IOM uint32_t NOCP : 1; /*!< [12..12] Overcurrent function support (NoOver Current Protection) */ + uint32_t : 11; + __IOM uint32_t POTPGT : 8; /*!< [31..24] Wait time (PowerOnToPowerGood Time) */ + } HCRHDESCRIPTORA_b; + }; + + union + { + __IOM uint32_t HCRHDESCRIPTORB; /*!< (@ 0x0000004C) HcRhDescriptorB Register */ + + struct + { + __IOM uint32_t DR : 16; /*!< [15..0] Device Removable */ + __IOM uint32_t PPCM : 16; /*!< [31..16] Port Power Control Mask */ + } HCRHDESCRIPTORB_b; + }; + + union + { + __IOM uint32_t HCRHSTATUS; /*!< (@ 0x00000050) HcRhStatus Register */ + + struct + { + __IOM uint32_t LPS : 1; /*!< [0..0] Local power status (LocalPowerStatus) */ + __IM uint32_t OCI : 1; /*!< [1..1] Overcurrent indicator (OverCurrent Indicator) */ + uint32_t : 13; + __IOM uint32_t DRWE : 1; /*!< [15..15] Device remote start enable (DeviceRemoteWakeupEnable) */ + __IOM uint32_t LPSC : 1; /*!< [16..16] Local power status change (LocalPowerStatusChange) */ + __IOM uint32_t OCIC : 1; /*!< [17..17] OCI bit change report (OverCurrent Indicate Change) */ + uint32_t : 13; + __OM uint32_t CRWE : 1; /*!< [31..31] DRWE bit clear (Clear Remote Wakeup Enable) */ + } HCRHSTATUS_b; + }; + + union + { + __IOM uint32_t HCRHPORTSTATUS1; /*!< (@ 0x00000054) HcRhPortStatus1 Register */ + + struct + { + __IOM uint32_t CCS : 1; /*!< [0..0] Connection status indication (CurrentConnectStatus) */ + __IOM uint32_t PES : 1; /*!< [1..1] Port enable status (PortEnableStatus) */ + __IOM uint32_t PSS : 1; /*!< [2..2] Suspend/Resume status (PortSuspendStatus) */ + __IM uint32_t POCI : 1; /*!< [3..3] Downstream port overcurrent detection (PortOverCurrentIndicator) */ + __IOM uint32_t PRS : 1; /*!< [4..4] Port reset status (PortResetStatus) */ + uint32_t : 3; + __IOM uint32_t PPS : 1; /*!< [8..8] Power status (PortPowerStatus) */ + __IOM uint32_t LSDA : 1; /*!< [9..9] Device speed (LowSpeedDeviceAttached) */ + uint32_t : 6; + __IOM uint32_t CSC : 1; /*!< [16..16] CCS bit status (ConnectStatus Change) */ + __IOM uint32_t PESC : 1; /*!< [17..17] PES bit status (PortEnable StatusChange) */ + __IOM uint32_t PSSC : 1; /*!< [18..18] RESUME sequence complete (PortSuspend StatusChange) */ + __IOM uint32_t OCIC : 1; /*!< [19..19] Overcurrent state detection (OverCurrent IndicateChange) */ + __IOM uint32_t PRSC : 1; /*!< [20..20] Port reset complete (PortReset StatusChange) */ + uint32_t : 11; + } HCRHPORTSTATUS1_b; + }; + __IM uint32_t RESERVED[42]; + + union + { + __IM uint32_t CAPL_VERSION; /*!< (@ 0x00000100) Capability Registers Length and EHCI Version + * Number Register */ + + struct + { + __IM uint32_t CRL : 8; /*!< [7..0] Capability Registers Length */ + uint32_t : 8; + __IM uint32_t HCIVN : 16; /*!< [31..16] EHCI Version Number */ + } CAPL_VERSION_b; + }; + + union + { + __IM uint32_t HCSPARAMS; /*!< (@ 0x00000104) Structural Parameters Register */ + + struct + { + __IM uint32_t N_PORTS : 4; /*!< [3..0] Number of downstream ports (Number of Ports) */ + __IM uint32_t PPC : 1; /*!< [4..4] Port power control (Port Power Control) */ + uint32_t : 2; + __IM uint32_t PTRR : 1; /*!< [7..7] Port routing rules */ + __IM uint32_t N_PCC : 4; /*!< [11..8] Number of ports (Number of Ports per Companion Controller) */ + __IM uint32_t N_CC : 4; /*!< [15..12] Number of OHCI host logic (Number of Companion Controller) */ + __IM uint32_t P_INDICATOR : 1; /*!< [16..16] Port indicator control support */ + uint32_t : 3; + __IM uint32_t DBGPTNUM : 4; /*!< [23..20] Debug port number */ + uint32_t : 8; + } HCSPARAMS_b; + }; + + union + { + __IM uint32_t HCCPARAMS; /*!< (@ 0x00000108) Capability Parameters Register */ + + struct + { + __IM uint32_t AC64 : 1; /*!< [0..0] Memory pointer selection */ + __IM uint32_t PFLF : 1; /*!< [1..1] Programming frame list flag */ + __IM uint32_t ASPC : 1; /*!< [2..2] Asynchronous schedule park support capability */ + uint32_t : 1; + __IM uint32_t IST : 4; /*!< [7..4] Isochronous data structure threshold */ + __IM uint32_t EECP : 8; /*!< [15..8] Offset address (EHCI Extend Capabilities Pointer) */ + __IM uint32_t HP : 1; /*!< [16..16] Hardware prefetch capability */ + __IM uint32_t LPMC : 1; /*!< [17..17] Link power management capability */ + __IM uint32_t PCEC : 1; /*!< [18..18] Per-port change event capability */ + __IM uint32_t PL32 : 1; /*!< [19..19] 32-frame periodic list capability */ + uint32_t : 12; + } HCCPARAMS_b; + }; + __IM uint32_t HCSP_PORTROUTE; /*!< (@ 0x0000010C) Companion Port Route Description Register */ + __IM uint32_t RESERVED1[4]; + + union + { + __IOM uint32_t USBCMD; /*!< (@ 0x00000120) USB Command Register */ + + struct + { + __IOM uint32_t RS : 1; /*!< [0..0] EHCI host logic run/stop (Run/Stop) */ + __IOM uint32_t HCRESET : 1; /*!< [1..1] Host logic initialization (Host Controller Reset) */ + __IOM uint32_t FLS : 2; /*!< [3..2] Frame list size */ + __IOM uint32_t PSE : 1; /*!< [4..4] Periodic schedule enable */ + __IOM uint32_t ASYNSE : 1; /*!< [5..5] Asynchronous schedule enable */ + __IOM uint32_t IAAD : 1; /*!< [6..6] Interrupt on Async Advance Doorbell */ + __IM uint32_t LHCR : 1; /*!< [7..7] Light host controller reset execution status */ + __IOM uint32_t ASPMC : 2; /*!< [9..8] Asynchronous schedule park mode count */ + uint32_t : 1; + __IOM uint32_t ASPME : 1; /*!< [11..11] Asynchronous schedule park mode enable */ + uint32_t : 3; + __IOM uint32_t PPCEE : 1; /*!< [15..15] Per-port change event enable */ + __IOM uint32_t ITC : 8; /*!< [23..16] Host logic interrupt generation maximum rate (Interrupt + * Threshold Control) */ + __IOM uint32_t HIRD : 4; /*!< [27..24] Host-Initiated Resume Duration (Minimum K-state drive + * time) */ + uint32_t : 4; + } USBCMD_b; + }; + + union + { + __IOM uint32_t USBSTS; /*!< (@ 0x00000124) USB Status Register */ + + struct + { + __IOM uint32_t USBINT : 1; /*!< [0..0] USB transfer complete (USB Interrupt) */ + __IOM uint32_t USBERRINT : 1; /*!< [1..1] USB transaction status (USB Error Interrupt) */ + __IOM uint32_t PTCGDET : 1; /*!< [2..2] Port state change detection */ + __IOM uint32_t FLROV : 1; /*!< [3..3] Frame list rollover */ + __IOM uint32_t HSYSE : 1; /*!< [4..4] Host system error */ + __IOM uint32_t IAAIS : 1; /*!< [5..5] Async advance interrupt status */ + uint32_t : 6; + __IM uint32_t EHCSTS : 1; /*!< [12..12] EHCI host logic status (HCHalted) */ + __IM uint32_t RECLAM : 1; /*!< [13..13] Empty asynchronous schedule detection (Reclamation) */ + __IM uint32_t PSCHSTS : 1; /*!< [14..14] Periodic schedule status */ + __IM uint32_t ASS : 1; /*!< [15..15] Asynchronous schedule status */ + __IOM uint32_t PTCGDETC : 16; /*!< [31..16] Port-n Change Detect */ + } USBSTS_b; + }; + + union + { + __IOM uint32_t USBINTR; /*!< (@ 0x00000128) USB Interrupt Enable Register */ + + struct + { + __IOM uint32_t USBIE : 1; /*!< [0..0] USB interrupt enable */ + __IOM uint32_t USBEIE : 1; /*!< [1..1] USB error interrupt enable */ + __IOM uint32_t PTCGIE : 1; /*!< [2..2] Port change interrupt enable */ + __IOM uint32_t FMLSTROE : 1; /*!< [3..3] Frame list rollover enable */ + __IOM uint32_t HSEE : 1; /*!< [4..4] Host system error enable */ + __IOM uint32_t INTAADVE : 1; /*!< [5..5] Interrupt on async advance enable */ + uint32_t : 10; + __IOM uint32_t PCGIE : 16; /*!< [31..16] Port-n Change Interrupt Enable */ + } USBINTR_b; + }; + + union + { + __IOM uint32_t FRINDEX; /*!< (@ 0x0000012C) USB Frame Index Register */ + + struct + { + __IOM uint32_t FRAMEINDEX : 14; /*!< [13..0] Frame index */ + uint32_t : 18; + } FRINDEX_b; + }; + __IM uint32_t CTRLDSSEGMENT; /*!< (@ 0x00000130) Control Data Structure Segment Register */ + + union + { + __IOM uint32_t PERIODICLISTBASE; /*!< (@ 0x00000134) Periodic Frame List Base Address Register */ + + struct + { + uint32_t : 12; + __IOM uint32_t PFLSA : 20; /*!< [31..12] Periodic frame list start address */ + } PERIODICLISTBASE_b; + }; + + union + { + __IOM uint32_t ASYNCLISTADDR; /*!< (@ 0x00000138) Next Asynchronous List Address Register */ + + struct + { + uint32_t : 5; + __IOM uint32_t LPL : 27; /*!< [31..5] Asynchronous Queue Head link pointer address (Link Pointer + * Low) */ + } ASYNCLISTADDR_b; + }; + __IM uint32_t RESERVED2[9]; + + union + { + __IOM uint32_t CONFIGFLAG; /*!< (@ 0x00000160) Configure Flag Register */ + + struct + { + __IOM uint32_t CF : 1; /*!< [0..0] Port routing control circuit configuration flag (Configure + * Flag) */ + uint32_t : 31; + } CONFIGFLAG_b; + }; + + union + { + __IOM uint32_t PORTSC1; /*!< (@ 0x00000164) Port 1 Status and Control Register */ + + struct + { + __IM uint32_t CCSTS : 1; /*!< [0..0] Port connection status */ + __IOM uint32_t CSC : 1; /*!< [1..1] Connect status change */ + __IOM uint32_t PTE : 1; /*!< [2..2] Port enable/disable status */ + __IOM uint32_t PTESC : 1; /*!< [3..3] Port enable/disable status change */ + __IM uint32_t OVCACT : 1; /*!< [4..4] Port overcurrent status */ + __IOM uint32_t OVCC : 1; /*!< [5..5] Over-current Change */ + __IOM uint32_t FRCPTRSM : 1; /*!< [6..6] Force Port Resume (Port resume detection flag) */ + __IOM uint32_t SUSPEND : 1; /*!< [7..7] Port suspend */ + __IOM uint32_t PTRST : 1; /*!< [8..8] Port reset status */ + __IOM uint32_t LPMCTL : 1; /*!< [9..9] LPM control */ + __IM uint32_t LINESTS : 2; /*!< [11..10] D+/D- logic level */ + __IOM uint32_t PP : 1; /*!< [12..12] Port Power Supply Control (Port Power) */ + __IOM uint32_t PTOWNR : 1; /*!< [13..13] Port ownership */ + __IM uint32_t PTINDCTL : 2; /*!< [15..14] As the host logic does not support the port indicator + * control function, these bits are set to 00b. */ + __IOM uint32_t PTTST : 4; /*!< [19..16] Pin test control */ + __IOM uint32_t WKCNNT_E : 1; /*!< [20..20] Device connection detection enable (Wake on Connect + * Enable) */ + __IOM uint32_t WKDSCNNT_E : 1; /*!< [21..21] Device disconnection detection enable (Wake on Disconnect + * Enable) */ + __IOM uint32_t WKOC_E : 1; /*!< [22..22] Overcurrent state detection enable (Wake on Over-current + * Enable) */ + __IOM uint32_t SUSPSTS : 2; /*!< [24..23] Suspend status */ + __IOM uint32_t DVADDR : 7; /*!< [31..25] USB device address */ + } PORTSC1_b; + }; + __IM uint32_t RESERVED3[38]; + + union + { + __IOM uint32_t INTENABLE; /*!< (@ 0x00000200) INT_ENABLE Register */ + + struct + { + __IOM uint32_t AHB_INTEN : 1; /*!< [0..0] AHB_INT bit control */ + __IOM uint32_t USBH_INTAEN : 1; /*!< [1..1] USBH_INTA bit control */ + __IOM uint32_t USBH_INTBEN : 1; /*!< [2..2] USBH_INTB bit control */ + __IOM uint32_t UCOM_INTEN : 1; /*!< [3..3] UCOM_INT bit control */ + __IOM uint32_t WAKEON_INTEN : 1; /*!< [4..4] WAKEON_INT bit control */ + uint32_t : 27; + } INTENABLE_b; + }; + + union + { + __IOM uint32_t INTSTATUS; /*!< (@ 0x00000204) INT_STATUS Register */ + + struct + { + __IOM uint32_t AHB_INT : 1; /*!< [0..0] AHB bus error indication */ + __IM uint32_t USBH_INTA : 1; /*!< [1..1] OHCI interrupt status */ + __IM uint32_t USBH_INTB : 1; /*!< [2..2] USBH_INTB EHCI interrupt status */ + __IM uint32_t UCOM_INT : 1; /*!< [3..3] UCOM register interrupt status */ + __IOM uint32_t WAKEON_INT : 1; /*!< [4..4] WAKEON interrupt status */ + uint32_t : 27; + } INTSTATUS_b; + }; + + union + { + __IOM uint32_t AHBBUSCTR; /*!< (@ 0x00000208) AHB_BUS_CTR Register */ + + struct + { + __IOM uint32_t MAX_BURST_LEN : 2; /*!< [1..0] Maximum burst length */ + uint32_t : 2; + __IOM uint32_t ALIGN_ADDRESS : 2; /*!< [5..4] Address boundary setting */ + uint32_t : 2; + __IOM uint32_t PROT_MODE : 1; /*!< [8..8] This bit selects the MHPROT[3:0] mode when the AHB master + * interface initiates a transfer. */ + uint32_t : 3; + __IOM uint32_t PROT_TYPE : 4; /*!< [15..12] These bits set MHPROT[3:0] when the AHB master interface + * initiates a transfer. */ + uint32_t : 16; + } AHBBUSCTR_b; + }; + + union + { + __IOM uint32_t USBCTR; /*!< (@ 0x0000020C) USBCTR Register */ + + struct + { + __OM uint32_t USBH_RST : 1; /*!< [0..0] Software reset for the core */ + __IOM uint32_t PLL_RST : 1; /*!< [1..1] Reset of USB PHY PLL */ + __IOM uint32_t DIRPD : 1; /*!< [2..2] Direct transition to power-down state */ + uint32_t : 29; + } USBCTR_b; + }; + __IM uint32_t RESERVED4[60]; + + union + { + __IM uint32_t REVID; /*!< (@ 0x00000300) Revision and Core ID Register */ + + struct + { + __IM uint32_t MINV : 8; /*!< [7..0] Minor Version */ + __IM uint32_t MAJV : 8; /*!< [15..8] Major Version */ + uint32_t : 8; + __IM uint32_t COREID : 8; /*!< [31..24] Core ID */ + } REVID_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t OCSLPTIMSET; /*!< (@ 0x00000310) Overcurrent Detection/Sleep Timer Setting Register */ + + struct + { + __IOM uint32_t TIMER_OC : 20; /*!< [19..0] Overcurrent Timer setting */ + __IOM uint32_t TIMER_SLEEP : 9; /*!< [28..20] Detection/Sleep Timer Setting */ + uint32_t : 3; + } OCSLPTIMSET_b; + }; + __IM uint32_t RESERVED6[315]; + + union + { + __IOM uint32_t COMMCTRL; /*!< (@ 0x00000800) Common Control Register */ + + struct + { + uint32_t : 31; + __IOM uint32_t PERI : 1; /*!< [31..31] USB mode setting */ + } COMMCTRL_b; + }; + + union + { + __IOM uint32_t OBINTSTA; /*!< (@ 0x00000804) OTG-BC Interrupt Status Register */ + + struct + { + __IOM uint32_t IDCHG_STA : 1; /*!< [0..0] USB_OTGID change status */ + __IOM uint32_t OCINT_STA : 1; /*!< [1..1] USB_OVRCUR assertion status */ + __IOM uint32_t VBSTACHG_STA : 1; /*!< [2..2] VBSTA[3:0] change status */ + __IOM uint32_t VBSTAINT_STA : 1; /*!< [3..3] VBUS voltage status interrupt */ + uint32_t : 12; + __IOM uint32_t DMMONCHG_STA : 1; /*!< [16..16] DMMON change status */ + __IOM uint32_t DPMONCHG_STA : 1; /*!< [17..17] DPMON change status */ + uint32_t : 14; + } OBINTSTA_b; + }; + + union + { + __IOM uint32_t OBINTEN; /*!< (@ 0x00000808) OTG-BC Interrupt Enable Register */ + + struct + { + __IOM uint32_t IDCHG_EN : 1; /*!< [0..0] IDCHG_STA Interrupt enable */ + __IOM uint32_t OCINT_EN : 1; /*!< [1..1] OCINT_STA interrupt enable */ + __IOM uint32_t VBSTACHG_EN : 1; /*!< [2..2] VBSTACHG_STA interrupt enable */ + __IOM uint32_t VBSTAINT_EN : 1; /*!< [3..3] VBSTAINT_STA interrupt enable */ + uint32_t : 12; + __IOM uint32_t DMMONCHG_EN : 1; /*!< [16..16] DMMONCHG_STA interrupt enable */ + __IOM uint32_t DPMONCHG_EN : 1; /*!< [17..17] DPMONCHG_STA interrupt enable */ + uint32_t : 14; + } OBINTEN_b; + }; + + union + { + __IOM uint32_t VBCTRL; /*!< (@ 0x0000080C) VBUS Control Register */ + + struct + { + __IOM uint32_t VBOUT : 1; /*!< [0..0] VBUS drive control (USB_VBUSEN pin) */ + __IOM uint32_t VBUSENSEL : 1; /*!< [1..1] USB_VBUSEN pin control */ + uint32_t : 2; + __IOM uint32_t VGPUO : 1; /*!< [4..4] USB_EXICEN pin control */ + uint32_t : 11; + __IOM uint32_t OCCLRIEN : 1; /*!< [16..16] USB_VBUSEN pin control at occurrence of overcurrent */ + __IOM uint32_t OCISEL : 1; /*!< [17..17] Overcurrent detection */ + uint32_t : 2; + __IOM uint32_t VBLVL : 4; /*!< [23..20] VBUS level detection */ + uint32_t : 4; + __IM uint32_t VBSTA : 4; /*!< [31..28] VBUS indication */ + } VBCTRL_b; + }; + + union + { + __IOM uint32_t LINECTRL1; /*!< (@ 0x00000810) Line Control Port 1 Register */ + + struct + { + __IM uint32_t IDMON : 1; /*!< [0..0] Indicates a value of USB_OTGID input pin. */ + uint32_t : 1; + __IM uint32_t DMMON : 1; /*!< [2..2] Indicates a value of USB bus DM. */ + __IM uint32_t DPMON : 1; /*!< [3..3] Indicates a value of USB bus DP. */ + uint32_t : 12; + __IOM uint32_t DM_RPD : 1; /*!< [16..16] Controls USB bus (DM) 15 kOhm pulldown resistor when + * DMPPD_EN = 1. */ + __IOM uint32_t DMRPD_EN : 1; /*!< [17..17] Enables DM_RPD to control USB bus (DM) 15 kOhm pulldown + * resistor. */ + __IOM uint32_t DP_RPD : 1; /*!< [18..18] Controls USB bus (DP) 15 kOhm pulldown resistor when + * DRPPD_EN = 1. */ + __IOM uint32_t DPRPD_EN : 1; /*!< [19..19] Enables DP_RPD to control USB bus (DP) 15 kOhm pulldown + * resistor. */ + uint32_t : 12; + } LINECTRL1_b; + }; +} R_USBHC_Type; /*!< Size = 2068 (0x814) */ + +/* =========================================================================================================================== */ +/* ================ R_USBF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief USB 2.0 Host and Function Module (R_USBF) + */ + +typedef struct /*!< (@ 0x80201000) R_USBF Structure */ +{ + union + { + __IOM uint16_t SYSCFG0; /*!< (@ 0x00000000) System Configuration Control Register 0 */ + + struct + { + __IOM uint16_t USBE : 1; /*!< [0..0] USB Block Operation Enable */ + uint16_t : 3; + __IOM uint16_t DPRPU : 1; /*!< [4..4] D+ Line Resistor Control */ + __IOM uint16_t DRPD : 1; /*!< [5..5] D+/D- Line Resistor Control */ + uint16_t : 1; + __IOM uint16_t HSE : 1; /*!< [7..7] High-Speed Operation Enable */ + __IOM uint16_t CNEN : 1; /*!< [8..8] Single-End Receiver Operation Enable */ + uint16_t : 7; + } SYSCFG0_b; + }; + + union + { + __IOM uint16_t SYSCFG1; /*!< (@ 0x00000002) System Configuration Control Register 1 */ + + struct + { + __IOM uint16_t BWAIT : 6; /*!< [5..0] CPU Bus Access Wait Specification */ + uint16_t : 2; + __IOM uint16_t AWAIT : 6; /*!< [13..8] AHB-DMA Bridge Bus Access Wait Specification */ + uint16_t : 2; + } SYSCFG1_b; + }; + + union + { + __IM uint16_t SYSSTS0; /*!< (@ 0x00000004) System Configuration Status Register */ + + struct + { + __IM uint16_t LNST : 2; /*!< [1..0] USB Data Line Status Monitor */ + uint16_t : 14; + } SYSSTS0_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t DVSTCTR0; /*!< (@ 0x00000008) Device State Control Register 0 */ + + struct + { + __IM uint16_t RHST : 3; /*!< [2..0] Reset Handshake */ + uint16_t : 5; + __IOM uint16_t WKUP : 1; /*!< [8..8] Wakeup Output */ + uint16_t : 7; + } DVSTCTR0_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t TESTMODE; /*!< (@ 0x0000000C) USB Test Mode Register */ + + struct + { + __IOM uint16_t UTST : 4; /*!< [3..0] Test Mode */ + uint16_t : 12; + } TESTMODE_b; + }; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3; + + union + { + union + { + __IOM uint32_t CFIFO; /*!< (@ 0x00000014) FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port */ + } CFIFO_b; + }; + + struct + { + union + { + __IOM uint16_t CFIFOL; /*!< (@ 0x00000014) FIFO Port Register */ + __IOM uint8_t CFIFOLL; /*!< (@ 0x00000014) FIFO Port Register */ + }; + + union + { + union + { + __IOM uint16_t CFIFOH; /*!< (@ 0x00000016) FIFO Port Register */ + + struct + { + __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port */ + } CFIFOH_b; + }; + + struct + { + __IM uint8_t RESERVED4; + + union + { + __IOM uint8_t CFIFOHH; /*!< (@ 0x00000017) FIFO Port Register */ + + struct + { + __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port */ + } CFIFOHH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D0FIFO; /*!< (@ 0x00000018) FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port */ + } D0FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D0FIFOL; /*!< (@ 0x00000018) FIFO Port Register */ + __IOM uint8_t D0FIFOLL; /*!< (@ 0x00000018) FIFO Port Register */ + }; + + union + { + union + { + __IOM uint16_t D0FIFOH; /*!< (@ 0x0000001A) FIFO Port Register */ + + struct + { + __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port */ + } D0FIFOH_b; + }; + + struct + { + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t D0FIFOHH; /*!< (@ 0x0000001B) FIFO Port Register */ + + struct + { + __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port */ + } D0FIFOHH_b; + }; + }; + }; + }; + }; + + union + { + union + { + __IOM uint32_t D1FIFO; /*!< (@ 0x0000001C) FIFO Port Register */ + + struct + { + __IOM uint32_t FIFOPORT : 32; /*!< [31..0] FIFO Port */ + } D1FIFO_b; + }; + + struct + { + union + { + __IOM uint16_t D1FIFOL; /*!< (@ 0x0000001C) FIFO Port Register */ + __IOM uint8_t D1FIFOLL; /*!< (@ 0x0000001C) FIFO Port Register */ + }; + + union + { + union + { + __IOM uint16_t D1FIFOH; /*!< (@ 0x0000001E) FIFO Port Register */ + + struct + { + __IOM uint16_t FIFOPORT : 16; /*!< [15..0] FIFO Port */ + } D1FIFOH_b; + }; + + struct + { + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t D1FIFOHH; /*!< (@ 0x0000001F) FIFO Port Register */ + + struct + { + __IOM uint8_t FIFOPORT : 8; /*!< [7..0] FIFO Port */ + } D1FIFOHH_b; + }; + }; + }; + }; + }; + + union + { + __IOM uint16_t CFIFOSEL; /*!< (@ 0x00000020) CFIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 1; + __IOM uint16_t ISEL : 1; /*!< [5..5] FIFO Port Access Direction when DCP is Selected */ + uint16_t : 2; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] CFIFO Port Access Bit Width */ + uint16_t : 2; + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } CFIFOSEL_b; + }; + + union + { + __IOM uint16_t CFIFOCTR; /*!< (@ 0x00000022) FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } CFIFOCTR_b; + }; + __IM uint32_t RESERVED7; + + union + { + __IOM uint16_t D0FIFOSEL; /*!< (@ 0x00000028) D0FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe + * Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D0FIFOSEL_b; + }; + + union + { + __IOM uint16_t D0FIFOCTR; /*!< (@ 0x0000002A) FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D0FIFOCTR_b; + }; + + union + { + __IOM uint16_t D1FIFOSEL; /*!< (@ 0x0000002C) D1FIFO Port Select Register */ + + struct + { + __IOM uint16_t CURPIPE : 4; /*!< [3..0] FIFO Port Access Pipe Specification */ + uint16_t : 4; + __IOM uint16_t BIGEND : 1; /*!< [8..8] FIFO Port Endian Control */ + uint16_t : 1; + __IOM uint16_t MBW : 2; /*!< [11..10] FIFO Port Access Bit Width */ + __IOM uint16_t DREQE : 1; /*!< [12..12] DMA Request Enable */ + __IOM uint16_t DCLRM : 1; /*!< [13..13] Auto Buffer Memory Clear Mode after Specified Pipe + * Data is Read */ + __IOM uint16_t REW : 1; /*!< [14..14] Buffer Pointer Rewind */ + __IOM uint16_t RCNT : 1; /*!< [15..15] Read Count Mode */ + } D1FIFOSEL_b; + }; + + union + { + __IOM uint16_t D1FIFOCTR; /*!< (@ 0x0000002E) FIFO Port Control Register */ + + struct + { + __IM uint16_t DTLN : 12; /*!< [11..0] Receive Data Length */ + uint16_t : 1; + __IM uint16_t FRDY : 1; /*!< [13..13] FIFO Port Ready */ + __IOM uint16_t BCLR : 1; /*!< [14..14] CPU Buffer Clear */ + __IOM uint16_t BVAL : 1; /*!< [15..15] Buffer Memory Valid Flag */ + } D1FIFOCTR_b; + }; + + union + { + __IOM uint16_t INTENB0; /*!< (@ 0x00000030) Interrupt Enable Register 0 */ + + struct + { + uint16_t : 8; + __IOM uint16_t BRDYE : 1; /*!< [8..8] Buffer Ready Interrupt Enable */ + __IOM uint16_t NRDYE : 1; /*!< [9..9] Buffer Not Ready Response Interrupt Enable */ + __IOM uint16_t BEMPE : 1; /*!< [10..10] Buffer Empty Interrupt Enable */ + __IOM uint16_t CTRE : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Enable */ + __IOM uint16_t DVSE : 1; /*!< [12..12] Device State Transition Interrupt Enable */ + __IOM uint16_t SOFE : 1; /*!< [13..13] Frame Number Update Interrupt Enable */ + __IOM uint16_t RSME : 1; /*!< [14..14] Resume Interrupt Enable */ + __IOM uint16_t VBSE : 1; /*!< [15..15] VBUS Interrupt Enable */ + } INTENB0_b; + }; + + union + { + __IOM uint16_t INTENB1; /*!< (@ 0x00000032) Interrupt Enable Register 1 */ + + struct + { + __IOM uint16_t PDDETINTE : 1; /*!< [0..0] PDDETINT Detection Interrupt Enable */ + uint16_t : 15; + } INTENB1_b; + }; + __IM uint16_t RESERVED8; + + union + { + __IOM uint16_t BRDYENB; /*!< (@ 0x00000036) BRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBRDYE : 10; /*!< [9..0] BRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BRDYENB_b; + }; + + union + { + __IOM uint16_t NRDYENB; /*!< (@ 0x00000038) NRDY Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPENRDYE : 10; /*!< [9..0] NRDY Interrupt Enable for Each Pipe */ + uint16_t : 6; + } NRDYENB_b; + }; + + union + { + __IOM uint16_t BEMPENB; /*!< (@ 0x0000003A) BEMP Interrupt Enable Register */ + + struct + { + __IOM uint16_t PIPEBEMPE : 10; /*!< [9..0] BEMP Interrupt Enable for Each Pipe */ + uint16_t : 6; + } BEMPENB_b; + }; + + union + { + __IOM uint16_t SOFCFG; /*!< (@ 0x0000003C) SOF Pin Configuration Register */ + + struct + { + uint16_t : 4; + __IM uint16_t EDGESTS : 1; /*!< [4..4] Interrupt Edge Processing Status */ + __IOM uint16_t INTL : 1; /*!< [5..5] Interrupt Output Sense Select */ + __IOM uint16_t BRDYM : 1; /*!< [6..6] PIPEBRDY Interrupt Status Clear Timing */ + uint16_t : 9; + } SOFCFG_b; + }; + __IM uint16_t RESERVED9; + + union + { + __IOM uint16_t INTSTS0; /*!< (@ 0x00000040) Interrupt Status Register 0 */ + + struct + { + __IM uint16_t CTSQ : 3; /*!< [2..0] Control Transfer Stage */ + __IOM uint16_t VALID : 1; /*!< [3..3] USB Request Reception */ + __IM uint16_t DVSQ : 3; /*!< [6..4] Device State */ + __IM uint16_t VBSTS : 1; /*!< [7..7] VBUS Input Status */ + __IM uint16_t BRDY : 1; /*!< [8..8] BRDY Interrupt Status */ + __IM uint16_t NRDY : 1; /*!< [9..9] NRDY Interrupt Status */ + __IM uint16_t BEMP : 1; /*!< [10..10] BEMP Interrupt Status */ + __IOM uint16_t CTRT : 1; /*!< [11..11] Control Transfer Stage Transition Interrupt Status */ + __IOM uint16_t DVST : 1; /*!< [12..12] Device State Transition Interrupt Status */ + __IOM uint16_t SOFR : 1; /*!< [13..13] Frame Number Update Interrupt Status */ + __IOM uint16_t RESM : 1; /*!< [14..14] Resume Interrupt Status */ + __IOM uint16_t VBINT : 1; /*!< [15..15] VBUS Change Detect Interrupt Status */ + } INTSTS0_b; + }; + + union + { + __IOM uint16_t INTSTS1; /*!< (@ 0x00000042) Interrupt Status Register 1 */ + + struct + { + __IOM uint16_t PDDETINT : 1; /*!< [0..0] PDDET Detection Interrupt Status */ + uint16_t : 15; + } INTSTS1_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t BRDYSTS; /*!< (@ 0x00000046) BRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBRDY : 10; /*!< [9..0] BRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } BRDYSTS_b; + }; + + union + { + __IOM uint16_t NRDYSTS; /*!< (@ 0x00000048) NRDY Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPENRDY : 10; /*!< [9..0] NRDY Interrupt Status for Each Pipe */ + uint16_t : 6; + } NRDYSTS_b; + }; + + union + { + __IOM uint16_t BEMPSTS; /*!< (@ 0x0000004A) BEMP Interrupt Status Register */ + + struct + { + __IOM uint16_t PIPEBEMP : 10; /*!< [9..0] BEMP Interrupt Status for Each Pipe */ + uint16_t : 6; + } BEMPSTS_b; + }; + + union + { + __IOM uint16_t FRMNUM; /*!< (@ 0x0000004C) Frame Number Register */ + + struct + { + __IM uint16_t FRNM : 11; /*!< [10..0] Frame Number */ + uint16_t : 3; + __IOM uint16_t CRCE : 1; /*!< [14..14] CRC Error Detection Status */ + __IOM uint16_t OVRN : 1; /*!< [15..15] Overrun/Underrun Detection Status */ + } FRMNUM_b; + }; + + union + { + __IM uint16_t UFRMNUM; /*!< (@ 0x0000004E) Frame Number Register */ + + struct + { + __IM uint16_t UFRNM : 3; /*!< [2..0] Microframe Number */ + uint16_t : 13; + } UFRMNUM_b; + }; + + union + { + __IM uint16_t USBADDR; /*!< (@ 0x00000050) USB Address Register */ + + struct + { + __IM uint16_t USBADDR : 7; /*!< [6..0] USB Address */ + uint16_t : 9; + } USBADDR_b; + }; + __IM uint16_t RESERVED11; + + union + { + __IM uint16_t USBREQ; /*!< (@ 0x00000054) USB Request Type Register */ + + struct + { + __IM uint16_t BMREQUESTTYPE : 8; /*!< [7..0] Request Type */ + __IM uint16_t BREQUEST : 8; /*!< [15..8] Request */ + } USBREQ_b; + }; + + union + { + __IM uint16_t USBVAL; /*!< (@ 0x00000056) USB Request Value Register */ + + struct + { + __IM uint16_t WVALUE : 16; /*!< [15..0] Value */ + } USBVAL_b; + }; + + union + { + __IM uint16_t USBINDX; /*!< (@ 0x00000058) USB Request Index Register */ + + struct + { + __IM uint16_t WINDEX : 16; /*!< [15..0] Index */ + } USBINDX_b; + }; + + union + { + __IM uint16_t USBLENG; /*!< (@ 0x0000005A) USB Request Length Register */ + + struct + { + __IM uint16_t WLENGTH : 16; /*!< [15..0] Length */ + } USBLENG_b; + }; + + union + { + __IOM uint16_t DCPCFG; /*!< (@ 0x0000005C) DCP Configuration Register */ + + struct + { + uint16_t : 7; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Disabling PIPE at the End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + uint16_t : 7; + } DCPCFG_b; + }; + + union + { + __IOM uint16_t DCPMAXP; /*!< (@ 0x0000005E) DCP Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 7; /*!< [6..0] Maximum Packet Size */ + uint16_t : 9; + } DCPMAXP_b; + }; + + union + { + __IOM uint16_t DCPCTR; /*!< (@ 0x00000060) DCP Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + __IOM uint16_t CCPL : 1; /*!< [2..2] Control Transfer End Enable */ + uint16_t : 2; + __IM uint16_t PBUSY : 1; /*!< [5..5] PIPE Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Sequence Toggle Bit Monitor */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + uint16_t : 6; + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } DCPCTR_b; + }; + __IM uint16_t RESERVED12; + + union + { + __IOM uint16_t PIPESEL; /*!< (@ 0x00000064) Pipe Window Select Register */ + + struct + { + __IOM uint16_t PIPESEL : 4; /*!< [3..0] Pipe Window Select */ + uint16_t : 12; + } PIPESEL_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t PIPECFG; /*!< (@ 0x00000068) Pipe Configuration Register */ + + struct + { + __IOM uint16_t EPNUM : 4; /*!< [3..0] Endpoint Number */ + __IOM uint16_t DIR : 1; /*!< [4..4] Transfer Direction */ + uint16_t : 2; + __IOM uint16_t SHTNAK : 1; /*!< [7..7] Pipe Disable at the End of Transfer */ + __IOM uint16_t CNTMD : 1; /*!< [8..8] Continuous Transfer Mode */ + __IOM uint16_t DBLB : 1; /*!< [9..9] Double Buffer Mode */ + __IOM uint16_t BFRE : 1; /*!< [10..10] BRDY Interrupt Operation Specification */ + uint16_t : 3; + __IOM uint16_t TYPE : 2; /*!< [15..14] Transfer Type */ + } PIPECFG_b; + }; + + union + { + __IOM uint16_t PIPEBUF; /*!< (@ 0x0000006A) Pipe Buffer Specification Register */ + + struct + { + __IOM uint16_t BUFNMB : 8; /*!< [7..0] Buffer number */ + uint16_t : 2; + __IOM uint16_t BUFSIZE : 5; /*!< [14..10] Buffer size */ + uint16_t : 1; + } PIPEBUF_b; + }; + + union + { + __IOM uint16_t PIPEMAXP; /*!< (@ 0x0000006C) Pipe Maximum Packet Size Register */ + + struct + { + __IOM uint16_t MXPS : 11; /*!< [10..0] Maximum Packet Size */ + uint16_t : 5; + } PIPEMAXP_b; + }; + + union + { + __IOM uint16_t PIPEPERI; /*!< (@ 0x0000006E) Pipe Timing Control Register */ + + struct + { + __IOM uint16_t IITV : 3; /*!< [2..0] Interval Error Detection Spacing */ + uint16_t : 9; + __IOM uint16_t IFIS : 1; /*!< [12..12] Isochronous IN Buffer Flush */ + uint16_t : 3; + } PIPEPERI_b; + }; + + union + { + __IOM uint16_t PIPE_CTR[9]; /*!< (@ 0x00000070) PIPE[0..8] Control Register */ + + struct + { + __IOM uint16_t PID : 2; /*!< [1..0] Response PID */ + uint16_t : 3; + __IM uint16_t PBUSY : 1; /*!< [5..5] PIPE Busy */ + __IM uint16_t SQMON : 1; /*!< [6..6] Toggle Bit Confirm */ + __IOM uint16_t SQSET : 1; /*!< [7..7] Toggle Bit Set */ + __IOM uint16_t SQCLR : 1; /*!< [8..8] Toggle Bit Clear */ + __IOM uint16_t ACLRM : 1; /*!< [9..9] Auto Buffer Clear Mode */ + __IOM uint16_t ATREPM : 1; /*!< [10..10] Auto Response Mode */ + uint16_t : 3; + __IM uint16_t INBUFM : 1; /*!< [14..14] Transfer Buffer Monitor */ + __IM uint16_t BSTS : 1; /*!< [15..15] Buffer Status */ + } PIPE_CTR_b[9]; + }; + __IM uint16_t RESERVED14; + __IM uint32_t RESERVED15[3]; + __IOM R_USBF_PIPE_TR_Type PIPE_TR[5]; /*!< (@ 0x00000090) PIPEn Transaction Counter Registers (n=1-5) */ + __IM uint32_t RESERVED16[23]; + __IM uint16_t RESERVED17; + + union + { + __IOM uint16_t LPSTS; /*!< (@ 0x00000102) Low Power Status Register */ + + struct + { + uint16_t : 14; + __IOM uint16_t SUSPM : 1; /*!< [14..14] UTMI SuspendM Control */ + uint16_t : 1; + } LPSTS_b; + }; + __IM uint32_t RESERVED18[191]; + __IOM R_USBF_CHa_Type CHa[2]; /*!< (@ 0x00000400) Next Register Set */ + __IM uint32_t RESERVED19[96]; + __IOM R_USBF_CHb_Type CHb[2]; /*!< (@ 0x00000600) Skip Register Set */ + __IM uint32_t RESERVED20[48]; + + union + { + __IOM uint32_t DCTRL; /*!< (@ 0x00000700) DMA Control Register */ + + struct + { + __IOM uint32_t PR : 1; /*!< [0..0] Priority */ + uint32_t : 15; + __IOM uint32_t LDPR : 4; /*!< [19..16] Link Descriptor PROT */ + uint32_t : 4; + __IOM uint32_t LWPR : 4; /*!< [27..24] Link WriteBack PROT */ + uint32_t : 4; + } DCTRL_b; + }; + + union + { + __IOM uint32_t DSCITVL; /*!< (@ 0x00000704) Descriptor Interval Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t DITVL : 8; /*!< [15..8] Descriptor Interval */ + uint32_t : 16; + } DSCITVL_b; + }; + __IM uint32_t RESERVED21[2]; + + union + { + __IM uint32_t DSTAT_EN; /*!< (@ 0x00000710) DMA Status EN Register */ + + struct + { + __IM uint32_t EN0 : 1; /*!< [0..0] Channel 0 EN */ + __IM uint32_t EN1 : 1; /*!< [1..1] Channel 1 EN */ + uint32_t : 30; + } DSTAT_EN_b; + }; + + union + { + __IM uint32_t DSTAT_ER; /*!< (@ 0x00000714) DMA Status ER Register */ + + struct + { + __IM uint32_t ER0 : 1; /*!< [0..0] Channel 0 ER */ + __IM uint32_t ER1 : 1; /*!< [1..1] Channel 1 ER */ + uint32_t : 30; + } DSTAT_ER_b; + }; + + union + { + __IM uint32_t DSTAT_END; /*!< (@ 0x00000718) DMA Status END Register */ + + struct + { + __IM uint32_t END0 : 1; /*!< [0..0] Channel 0 END */ + __IM uint32_t END1 : 1; /*!< [1..1] Channel 1 END */ + uint32_t : 30; + } DSTAT_END_b; + }; + + union + { + __IM uint32_t DSTAT_TC; /*!< (@ 0x0000071C) DMA Status TC Register */ + + struct + { + __IM uint32_t TC0 : 1; /*!< [0..0] Channel 0 TC */ + __IM uint32_t TC1 : 1; /*!< [1..1] Channel 1 TC */ + uint32_t : 30; + } DSTAT_TC_b; + }; + + union + { + __IM uint32_t DSTAT_SUS; /*!< (@ 0x00000720) DMA Status SUS Register */ + + struct + { + __IM uint32_t SUS0 : 1; /*!< [0..0] Channel 0 SUS */ + __IM uint32_t SUS1 : 1; /*!< [1..1] Channel 1 SUS */ + uint32_t : 30; + } DSTAT_SUS_b; + }; +} R_USBF_Type; /*!< Size = 1828 (0x724) */ + +/* =========================================================================================================================== */ +/* ================ R_BSC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus State Controller (R_BSC) + */ + +typedef struct /*!< (@ 0x80210000) R_BSC Structure */ +{ + union + { + __IOM uint32_t CMNCR; /*!< (@ 0x00000000) Common Control Register */ + + struct + { + uint32_t : 9; + __IOM uint32_t DPRTY : 2; /*!< [10..9] DMA Burst Transfer Priority */ + uint32_t : 13; + __IOM uint32_t AL : 1; /*!< [24..24] Acknowledge Level */ + uint32_t : 3; + __IOM uint32_t TL : 1; /*!< [28..28] Transfer End Level */ + uint32_t : 3; + } CMNCR_b; + }; + + union + { + __IOM uint32_t CSnBCR[6]; /*!< (@ 0x00000004) CS[0..5] Space Bus Control Register */ + + struct + { + uint32_t : 9; + __IOM uint32_t BSZ : 2; /*!< [10..9] Data Bus Width Specification */ + uint32_t : 1; + __IOM uint32_t TYPE : 3; /*!< [14..12] Memory Connected to a Space */ + uint32_t : 1; + __IOM uint32_t IWRRS : 3; /*!< [18..16] Idle State Insertion between Read-Read Cycles in the + * Same CS Space */ + __IOM uint32_t IWRRD : 3; /*!< [21..19] Idle State Insertion between Read-Read Cycles in Different + * CS Spaces */ + __IOM uint32_t IWRWS : 3; /*!< [24..22] Idle State Insertion between Read-Write Cycles in the + * Same CS Space */ + __IOM uint32_t IWRWD : 3; /*!< [27..25] Idle State Insertion between Read-Write Cycles in Different + * CS Spaces */ + __IOM uint32_t IWW : 3; /*!< [30..28] Idle Cycles between Write-Read Cycles and Write-Write + * Cycles */ + uint32_t : 1; + } CSnBCR_b[6]; + }; + __IM uint32_t RESERVED[3]; + + union + { + union + { + __IOM uint32_t CS0WCR_0; /*!< (@ 0x00000028) CS0 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection */ + + struct + { + __IOM uint32_t HW : 2; /*!< [1..0] Delay States from RD#, WEn# Negation to Address, CS0# + * Negation */ + uint32_t : 4; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Access Waits */ + __IOM uint32_t SW : 2; /*!< [12..11] Number of Delay Cycles from Address, CSn# Assertion + * to RD#, WEn# Assertion */ + uint32_t : 7; + __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select */ + uint32_t : 11; + } CS0WCR_0_b; + }; + + union + { + __IOM uint32_t CS0WCR_1; /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM + * with Clocked Asynchronous */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t W : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 5; + __IOM uint32_t BW : 2; /*!< [17..16] Number of Waits during Burst Access */ + uint32_t : 2; + __IOM uint32_t BST : 2; /*!< [21..20] Burst Count Specification */ + uint32_t : 10; + } CS0WCR_1_b; + }; + + union + { + __IOM uint32_t CS0WCR_2; /*!< (@ 0x00000028) CS0 Space Wait Control Register for Burst ROM + * with Clocked Synchronous */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t W : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 5; + __IOM uint32_t BW : 2; /*!< [17..16] Number of Burst Wait Cycles */ + uint32_t : 14; + } CS0WCR_2_b; + }; + }; + __IM uint32_t RESERVED1; + + union + { + union + { + __IOM uint32_t CS2WCR_0; /*!< (@ 0x00000030) CS2 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 9; + __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select */ + uint32_t : 11; + } CS2WCR_0_b; + }; + + union + { + __IOM uint32_t CS2WCR_1; /*!< (@ 0x00000030) CS2 Space Wait Control Register for SDRAM */ + + struct + { + uint32_t : 7; + __IOM uint32_t A2CL : 2; /*!< [8..7] CAS Latency for Area 2 */ + uint32_t : 23; + } CS2WCR_1_b; + }; + }; + + union + { + union + { + __IOM uint32_t CS3WCR_0; /*!< (@ 0x00000034) CS3 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection */ + + struct + { + uint32_t : 6; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Access Waits */ + uint32_t : 9; + __IOM uint32_t BAS : 1; /*!< [20..20] SRAM with Byte Selection Byte Access Select */ + uint32_t : 11; + } CS3WCR_0_b; + }; + + union + { + __IOM uint32_t CS3WCR_1; /*!< (@ 0x00000034) CS3 Space Wait Control Register for SDRAM */ + + struct + { + __IOM uint32_t WTRC : 2; /*!< [1..0] Number of Idle States from REF Command/Self-Refresh Release + * to ACTV/REF/MRS Command */ + uint32_t : 1; + __IOM uint32_t TRWL : 2; /*!< [4..3] Number of Auto-Precharge Startup Wait Cycles */ + uint32_t : 2; + __IOM uint32_t A3CL : 2; /*!< [8..7] CAS Latency for Area 3 */ + uint32_t : 1; + __IOM uint32_t WTRCD : 2; /*!< [11..10] Number of Waits between ACTV Command and READ(A)/WRIT(A) + * Command */ + uint32_t : 1; + __IOM uint32_t WTRP : 2; /*!< [14..13] Number of Auto-Precharge Completion Wait States */ + uint32_t : 17; + } CS3WCR_1_b; + }; + }; + __IM uint32_t RESERVED2; + + union + { + __IOM uint32_t CS5WCR; /*!< (@ 0x0000003C) CS5 Space Wait Control Register for Normal Space, + * SRAM with Byte Selection, and MPX-I/O */ + + struct + { + __IOM uint32_t HW : 2; /*!< [1..0] Delay Cycles from RD#, WEn# to Address, CS5# */ + uint32_t : 4; + __IOM uint32_t WM : 1; /*!< [6..6] External Wait Mask Specification */ + __IOM uint32_t WR : 4; /*!< [10..7] Number of Read Access Waits */ + __IOM uint32_t SW : 2; /*!< [12..11] Number of Delay Cycles from Address, CS5# Assertion + * to RD#, WEn# Assertion */ + uint32_t : 3; + __IOM uint32_t WW : 3; /*!< [18..16] Number of Write Access Waits */ + uint32_t : 1; + __IOM uint32_t MPXWSBAS : 1; /*!< [20..20] MPX-I/O Interface Address Cycle Wait and SRAM with + * Byte Selection Byte Access Select */ + __IOM uint32_t SZSEL : 1; /*!< [21..21] MPX-I/O Interface Bus Width Specification */ + uint32_t : 10; + } CS5WCR_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t SDCR; /*!< (@ 0x0000004C) SDRAM Control Register */ + + struct + { + __IOM uint32_t A3COL : 2; /*!< [1..0] Number of Bits of Column Address for Area 3 */ + uint32_t : 1; + __IOM uint32_t A3ROW : 2; /*!< [4..3] Number of Bits of Row Address for Area 3 */ + uint32_t : 3; + __IOM uint32_t BACTV : 1; /*!< [8..8] Bank Active Mode */ + __IOM uint32_t PDOWN : 1; /*!< [9..9] Power-Down Mode */ + __IOM uint32_t RMODE : 1; /*!< [10..10] Refresh Mode */ + __IOM uint32_t RFSH : 1; /*!< [11..11] Refresh Control */ + uint32_t : 1; + __IOM uint32_t DEEP : 1; /*!< [13..13] Deep Power-Down Mode */ + uint32_t : 2; + __IOM uint32_t A2COL : 2; /*!< [17..16] Number of Bits of Column Address for Area 2 */ + uint32_t : 1; + __IOM uint32_t A2ROW : 2; /*!< [20..19] Number of Bits of Row Address for Area 2 */ + uint32_t : 11; + } SDCR_b; + }; + __IOM uint32_t RTCSR; /*!< (@ 0x00000050) Refresh Timer Control/Status Register */ + __IOM uint32_t RTCNT; /*!< (@ 0x00000054) Refresh Timer Counter */ + __IOM uint32_t RTCOR; /*!< (@ 0x00000058) Refresh Time Constant Register */ + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t TOSCOR[6]; /*!< (@ 0x00000060) Timeout Cycle Constant Register [0..5] */ + + struct + { + __IOM uint32_t TOCNUM : 16; /*!< [15..0] Timeout Cycle Number */ + uint32_t : 16; + } TOSCOR_b[6]; + }; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint32_t TOSTR; /*!< (@ 0x00000080) Timeout Status Register */ + + struct + { + __IOM uint32_t CS0TOSTF : 1; /*!< [0..0] CS0 Space Timeout Status Flag */ + uint32_t : 1; + __IOM uint32_t CS2TOSTF : 1; /*!< [2..2] CS2 Space Timeout Status Flag */ + __IOM uint32_t CS3TOSTF : 1; /*!< [3..3] CS3 Space Timeout Status Flag */ + uint32_t : 1; + __IOM uint32_t CS5TOSTF : 1; /*!< [5..5] CS5 Space Timeout Status Flag */ + uint32_t : 26; + } TOSTR_b; + }; + + union + { + __IOM uint32_t TOENR; /*!< (@ 0x00000084) Timeout Enable Register */ + + struct + { + __IOM uint32_t CS0TOEN : 1; /*!< [0..0] CS0 Space Timeout Detection Enable */ + uint32_t : 1; + __IOM uint32_t CS2TOEN : 1; /*!< [2..2] CS2 Space Timeout Detection Enable */ + __IOM uint32_t CS3TOEN : 1; /*!< [3..3] CS3 Space Timeout Detection Enable */ + uint32_t : 1; + __IOM uint32_t CS5TOEN : 1; /*!< [5..5] CS5 Space Timeout Detection Enable */ + uint32_t : 26; + } TOENR_b; + }; +} R_BSC_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief xSPI (R_XSPI0) + */ + +typedef struct /*!< (@ 0x80220000) R_XSPI0 Structure */ +{ + union + { + __IOM uint32_t WRAPCFG; /*!< (@ 0x00000000) xSPI Wrapper Configuration Register */ + + struct + { + uint32_t : 8; + __IOM uint32_t DSSFTCS0 : 5; /*!< [12..8] DS shift for slave0 */ + uint32_t : 11; + __IOM uint32_t DSSFTCS1 : 5; /*!< [28..24] DS shift for slave1 */ + uint32_t : 3; + } WRAPCFG_b; + }; + + union + { + __IOM uint32_t COMCFG; /*!< (@ 0x00000004) xSPI Common Configuration Register */ + + struct + { + uint32_t : 16; + __IOM uint32_t OEASTEX : 1; /*!< [16..16] Output Enable Asserting extension */ + __IOM uint32_t OENEGEX : 1; /*!< [17..17] Output Enable Negating extension */ + uint32_t : 14; + } COMCFG_b; + }; + + union + { + __IOM uint32_t BMCFG; /*!< (@ 0x00000008) xSPI Bridge Map Configuration Register */ + + struct + { + __IOM uint32_t WRMD : 1; /*!< [0..0] AHB Write Response mode */ + uint32_t : 6; + __IOM uint32_t MWRCOMB : 1; /*!< [7..7] Memory Write Combination mode */ + __IOM uint32_t MWRSIZE : 8; /*!< [15..8] Memory Write Size */ + __IOM uint32_t PREEN : 1; /*!< [16..16] Prefetch enable */ + uint32_t : 15; + } BMCFG_b; + }; + __IM uint32_t RESERVED; + __IOM R_XSPI0_CSa_Type CSa[2]; /*!< (@ 0x00000010) xSPI Command Map Configuration Register [0..1] */ + __IM uint32_t RESERVED1[8]; + + union + { + __IOM uint32_t LIOCFGCS[2]; /*!< (@ 0x00000050) xSPI Link I/O Configuration Register CSn */ + + struct + { + __IOM uint32_t PRTMD : 10; /*!< [9..0] Protocol mode */ + __IOM uint32_t LATEMD : 1; /*!< [10..10] Latency mode */ + __IOM uint32_t WRMSKMD : 1; /*!< [11..11] Write mask mode */ + uint32_t : 4; + __IOM uint32_t CSMIN : 4; /*!< [19..16] CS minimum idle term */ + __IOM uint32_t CSASTEX : 1; /*!< [20..20] CS asserting extension */ + __IOM uint32_t CSNEGEX : 1; /*!< [21..21] CS negating extension */ + __IOM uint32_t SDRDRV : 1; /*!< [22..22] SDR driving timing */ + __IOM uint32_t SDRSMPMD : 1; /*!< [23..23] SDR Sampling mode */ + __IOM uint32_t SDRSMPSFT : 4; /*!< [27..24] SDR Sampling window shift */ + __IOM uint32_t DDRSMPEX : 4; /*!< [31..28] DDR sampling window extend */ + } LIOCFGCS_b[2]; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IOM uint32_t BMCTL0; /*!< (@ 0x00000060) xSPI Bridge Map Control Register 0 */ + + struct + { + __IOM uint32_t CS0ACC : 2; /*!< [1..0] AHB channel to slave0 memory area access enable */ + __IOM uint32_t CS1ACC : 2; /*!< [3..2] AHB channel to slave1 memory area access enable */ + uint32_t : 28; + } BMCTL0_b; + }; + + union + { + __OM uint32_t BMCTL1; /*!< (@ 0x00000064) xSPI Bridge Map Control Register 1 */ + + struct + { + uint32_t : 8; + __OM uint32_t MWRPUSH : 1; /*!< [8..8] Memory Write Data Push */ + uint32_t : 1; + __OM uint32_t PBUFCLR : 1; /*!< [10..10] Prefetch Buffer clear */ + uint32_t : 21; + } BMCTL1_b; + }; + + union + { + __IOM uint32_t CMCTL; /*!< (@ 0x00000068) xSPI Command Map Control Register */ + + struct + { + __IOM uint32_t XIPENCODE : 8; /*!< [7..0] XiP mode enter code */ + __IOM uint32_t XIPEXCODE : 8; /*!< [15..8] XiP mode exit code */ + __IOM uint32_t XIPEN : 1; /*!< [16..16] XiP mode enable */ + uint32_t : 15; + } CMCTL_b; + }; + + union + { + __IOM uint32_t CSSCTL; /*!< (@ 0x0000006C) xSPI CS Size Control Register */ + + struct + { + __IOM uint32_t CS0SIZE : 6; /*!< [5..0] CS0 (slave0) size */ + uint32_t : 2; + __IOM uint32_t CS1SIZE : 6; /*!< [13..8] CS1 (slave1) size */ + uint32_t : 18; + } CSSCTL_b; + }; + + union + { + __IOM uint32_t CDCTL0; /*!< (@ 0x00000070) xSPI Command Manual Control Register 0 */ + + struct + { + __IOM uint32_t TRREQ : 1; /*!< [0..0] Transaction request */ + __IOM uint32_t PERMD : 1; /*!< [1..1] Periodic mode */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t TRNUM : 2; /*!< [5..4] Transaction number */ + uint32_t : 10; + __IOM uint32_t PERITV : 5; /*!< [20..16] Periodic transaction interval */ + uint32_t : 3; + __IOM uint32_t PERREP : 4; /*!< [27..24] Periodic transaction repeat */ + uint32_t : 4; + } CDCTL0_b; + }; + + union + { + __IOM uint32_t CDCTL1; /*!< (@ 0x00000074) xSPI Command Manual Control Register 1 */ + + struct + { + __IOM uint32_t PEREXP : 32; /*!< [31..0] Periodic transaction expected value */ + } CDCTL1_b; + }; + + union + { + __IOM uint32_t CDCTL2; /*!< (@ 0x00000078) xSPI Command Manual Control Register 2 */ + + struct + { + __IOM uint32_t PERMSK : 32; /*!< [31..0] Periodic transaction masked value */ + } CDCTL2_b; + }; + __IM uint32_t RESERVED3; + __IOM R_XSPI0_BUF_Type BUF[4]; /*!< (@ 0x00000080) xSPI Command Manual Buf [0..3] */ + __IM uint32_t RESERVED4[16]; + + union + { + __IOM uint32_t LPCTL0; /*!< (@ 0x00000100) xSPI Link Pattern Control Register 0 */ + + struct + { + __IOM uint32_t PATREQ : 1; /*!< [0..0] Pattern request */ + uint32_t : 2; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t XDPIN : 2; /*!< [5..4] XiP Disable pattern pin */ + uint32_t : 10; + __IOM uint32_t XD1LEN : 5; /*!< [20..16] XiP Disable pattern 1st phase length */ + uint32_t : 2; + __IOM uint32_t XD1VAL : 1; /*!< [23..23] XiP Disable pattern 1st phase value */ + __IOM uint32_t XD2LEN : 5; /*!< [28..24] XiP Disable pattern 2nd phase length */ + uint32_t : 2; + __IOM uint32_t XD2VAL : 1; /*!< [31..31] XiP Disable pattern 2nd phase value */ + } LPCTL0_b; + }; + + union + { + __IOM uint32_t LPCTL1; /*!< (@ 0x00000104) xSPI Link Pattern Control Register 1 */ + + struct + { + __IOM uint32_t PATREQ : 2; /*!< [1..0] Pattern request */ + uint32_t : 1; + __IOM uint32_t CSSEL : 1; /*!< [3..3] Chip select */ + __IOM uint32_t RSTREP : 2; /*!< [5..4] Reset pattern repeat */ + uint32_t : 2; + __IOM uint32_t RSTWID : 3; /*!< [10..8] Reset pattern width */ + uint32_t : 1; + __IOM uint32_t RSTSU : 3; /*!< [14..12] Reset pattern data output setup time */ + uint32_t : 17; + } LPCTL1_b; + }; + + union + { + __IOM uint32_t LIOCTL; /*!< (@ 0x00000108) xSPI Link I/O Control Register */ + + struct + { + __IOM uint32_t WPCS0 : 1; /*!< [0..0] WP drive for slave0 */ + __IOM uint32_t WPCS1 : 1; /*!< [1..1] WP drive for slave1 */ + uint32_t : 14; + __IOM uint32_t RSTCS0 : 1; /*!< [16..16] Reset drive for slave0 */ + __IOM uint32_t RSTCS1 : 1; /*!< [17..17] Reset drive for slave1 */ + uint32_t : 14; + } LIOCTL_b; + }; + __IM uint32_t RESERVED5[9]; + __IOM R_XSPI0_CSb_Type CSb[2]; /*!< (@ 0x00000130) xSPI Command Calibration Control register [0..1] */ + __IM uint32_t RESERVED6[4]; + + union + { + __IM uint32_t VERSTT; /*!< (@ 0x00000180) xSPI Version Register */ + + struct + { + __IM uint32_t VER : 32; /*!< [31..0] Version */ + } VERSTT_b; + }; + + union + { + __IM uint32_t COMSTT; /*!< (@ 0x00000184) xSPI Common Status Register */ + + struct + { + __IM uint32_t MEMACC : 1; /*!< [0..0] Memory access ongoing */ + uint32_t : 3; + __IM uint32_t PBUFNE : 1; /*!< [4..4] Prefetch Buffer Not Empty */ + uint32_t : 1; + __IM uint32_t WRBUFNE : 1; /*!< [6..6] Write Buffer Not Empty */ + uint32_t : 9; + __IM uint32_t ECSCS0 : 1; /*!< [16..16] ECS monitor for slave0 */ + __IM uint32_t INTCS0 : 1; /*!< [17..17] INT monitor for slave0 */ + __IM uint32_t RSTOCS0 : 1; /*!< [18..18] RSTO monitor for slave0 */ + uint32_t : 1; + __IM uint32_t ECSCS1 : 1; /*!< [20..20] ECS monitor for slave1 */ + __IM uint32_t INTCS1 : 1; /*!< [21..21] INT monitor for slave1 */ + __IM uint32_t RSTOCS1 : 1; /*!< [22..22] RSTO monitor for slave1 */ + uint32_t : 9; + } COMSTT_b; + }; + + union + { + __IM uint32_t CASTTCS[2]; /*!< (@ 0x00000188) xSPI Calibration Status Register CSn */ + + struct + { + __IM uint32_t CASUC : 32; /*!< [31..0] Calibration Success */ + } CASTTCS_b[2]; + }; + + union + { + __IM uint32_t INTS; /*!< (@ 0x00000190) xSPI Interrupt Status Register */ + + struct + { + __IM uint32_t CMDCMP : 1; /*!< [0..0] Command Completed */ + __IM uint32_t PATCMP : 1; /*!< [1..1] Pattern Completed */ + __IM uint32_t INICMP : 1; /*!< [2..2] Initial Sequence Completed */ + __IM uint32_t PERTO : 1; /*!< [3..3] Periodic transaction timeout */ + __IM uint32_t DSTOCS0 : 1; /*!< [4..4] DS timeout for slave0 */ + __IM uint32_t DSTOCS1 : 1; /*!< [5..5] DS timeout for slave1 */ + uint32_t : 2; + __IM uint32_t ECSCS0 : 1; /*!< [8..8] ECC error detection for slave0 */ + __IM uint32_t ECSCS1 : 1; /*!< [9..9] ECC error detection for slave1 */ + uint32_t : 2; + __IM uint32_t INTCS0 : 1; /*!< [12..12] Interrupt detection for slave0 */ + __IM uint32_t INTCS1 : 1; /*!< [13..13] Interrupt detection for slave1 */ + uint32_t : 2; + __IM uint32_t BRGOF : 1; /*!< [16..16] Bridge Buffer overflow */ + uint32_t : 1; + __IM uint32_t BRGUF : 1; /*!< [18..18] Bridge Buffer underflow */ + uint32_t : 1; + __IM uint32_t BUSERR : 1; /*!< [20..20] AHB bus error */ + uint32_t : 7; + __IM uint32_t CAFAILCS0 : 1; /*!< [28..28] Calibration failed for slave0 */ + __IM uint32_t CAFAILCS1 : 1; /*!< [29..29] Calibration failed for slave1 */ + __IM uint32_t CASUCCS0 : 1; /*!< [30..30] Calibration success for slave0 */ + __IM uint32_t CASUCCS1 : 1; /*!< [31..31] Calibration success for slave1 */ + } INTS_b; + }; + + union + { + __OM uint32_t INTC; /*!< (@ 0x00000194) xSPI Interrupt Clear Register */ + + struct + { + __OM uint32_t CMDCMPC : 1; /*!< [0..0] Command Completed interrupt clear */ + __OM uint32_t PATCMPC : 1; /*!< [1..1] Pattern Completed interrupt clear */ + __OM uint32_t INICMPC : 1; /*!< [2..2] Initial Sequence Completed interrupt clear */ + __OM uint32_t PERTOC : 1; /*!< [3..3] Periodic transaction timeout interrupt clear */ + __OM uint32_t DSTOCS0C : 1; /*!< [4..4] DS timeout for slave0 interrupt clear */ + __OM uint32_t DSTOCS1C : 1; /*!< [5..5] DS timeout for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t ECSCS0C : 1; /*!< [8..8] ECC error detection for slave0 interrupt clear */ + __OM uint32_t ECSCS1C : 1; /*!< [9..9] ECC error detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t INTCS0C : 1; /*!< [12..12] Interrupt detection for slave0 interrupt clear */ + __OM uint32_t INTCS1C : 1; /*!< [13..13] Interrupt detection for slave1 interrupt clear */ + uint32_t : 2; + __OM uint32_t BRGOFC : 1; /*!< [16..16] Bridge Buffer overflow interrupt clear */ + uint32_t : 1; + __OM uint32_t BRGUFC : 1; /*!< [18..18] Bridge Buffer underflow interrupt clear */ + uint32_t : 1; + __OM uint32_t BUSERRC : 1; /*!< [20..20] AHB bus error interrupt clear */ + uint32_t : 7; + __OM uint32_t CAFAILCS0C : 1; /*!< [28..28] Calibration failed for slave0 interrupt clear */ + __OM uint32_t CAFAILCS1C : 1; /*!< [29..29] Calibration failed for slave1 interrupt clear */ + __OM uint32_t CASUCCS0C : 1; /*!< [30..30] Calibration success for slave0 interrupt clear */ + __OM uint32_t CASUCCS1C : 1; /*!< [31..31] Calibration success for slave1 interrupt clear */ + } INTC_b; + }; + + union + { + __IOM uint32_t INTE; /*!< (@ 0x00000198) xSPI Interrupt Enable Register */ + + struct + { + __IOM uint32_t CMDCMPE : 1; /*!< [0..0] Command Completed interrupt enable */ + __IOM uint32_t PATCMPE : 1; /*!< [1..1] Pattern Completed interrupt enable */ + __IOM uint32_t INICMPE : 1; /*!< [2..2] Initial Sequence Completed interrupt enable */ + __IOM uint32_t PERTOE : 1; /*!< [3..3] Periodic transaction timeout interrupt enable */ + __IOM uint32_t DSTOCS0E : 1; /*!< [4..4] DS timeout for slave0 interrupt enable */ + __IOM uint32_t DSTOCS1E : 1; /*!< [5..5] DS timeout for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t ECSCS0E : 1; /*!< [8..8] ECC error detection for slave0 interrupt enable */ + __IOM uint32_t ECSCS1E : 1; /*!< [9..9] ECC error detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t INTCS0E : 1; /*!< [12..12] Interrupt detection for slave0 interrupt enable */ + __IOM uint32_t INTCS1E : 1; /*!< [13..13] Interrupt detection for slave1 interrupt enable */ + uint32_t : 2; + __IOM uint32_t BRGOFE : 1; /*!< [16..16] Bridge Buffer overflow interrupt enable */ + uint32_t : 1; + __IOM uint32_t BRGUFE : 1; /*!< [18..18] Bridge Buffer underflow interrupt enable */ + uint32_t : 1; + __IOM uint32_t BUSERRE : 1; /*!< [20..20] AHB bus error interrupt enable */ + uint32_t : 7; + __IOM uint32_t CAFAILCS0E : 1; /*!< [28..28] Calibration failed for slave0 interrupt enable */ + __IOM uint32_t CAFAILCS1E : 1; /*!< [29..29] Calibration failed for slave1 interrupt enable */ + __IOM uint32_t CASUCCS0E : 1; /*!< [30..30] Calibration success for slave0 interrupt enable */ + __IOM uint32_t CASUCCS1E : 1; /*!< [31..31] Calibration success for slave1 interrupt enable */ + } INTE_b; + }; +} R_XSPI0_Type; /*!< Size = 412 (0x19c) */ + +/* =========================================================================================================================== */ +/* ================ R_MBXSEM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Mailbox and Semaphore (R_MBXSEM) + */ + +typedef struct /*!< (@ 0x80240000) R_MBXSEM Structure */ +{ + union + { + __IOM uint32_t SEM[8]; /*!< (@ 0x00000000) Semaphore Register [0..7] */ + + struct + { + __IOM uint32_t SEM : 1; /*!< [0..0] Semaphore bit */ + uint32_t : 31; + } SEM_b[8]; + }; + + union + { + __IOM uint32_t SEMRCEN; /*!< (@ 0x00000020) Semaphore Read Clear Enable Register */ + + struct + { + __IOM uint32_t SEMRCEN0 : 1; /*!< [0..0] SEMRCEN0 */ + __IOM uint32_t SEMRCEN1 : 1; /*!< [1..1] SEMRCEN1 */ + __IOM uint32_t SEMRCEN2 : 1; /*!< [2..2] SEMRCEN2 */ + __IOM uint32_t SEMRCEN3 : 1; /*!< [3..3] SEMRCEN3 */ + __IOM uint32_t SEMRCEN4 : 1; /*!< [4..4] SEMRCEN4 */ + __IOM uint32_t SEMRCEN5 : 1; /*!< [5..5] SEMRCEN5 */ + __IOM uint32_t SEMRCEN6 : 1; /*!< [6..6] SEMRCEN6 */ + __IOM uint32_t SEMRCEN7 : 1; /*!< [7..7] SEMRCEN7 */ + uint32_t : 24; + } SEMRCEN_b; + }; + __IM uint32_t RESERVED[7]; + + union + { + __IM uint32_t MBXH2C[4]; /*!< (@ 0x00000040) Host to CR52 Mailbox Register [0..3] */ + + struct + { + __IM uint32_t MBX : 32; /*!< [31..0] MBX */ + } MBXH2C_b[4]; + }; + + union + { + __IM uint32_t MBXISETH2C; /*!< (@ 0x00000050) Host to CR52 Mailbox Interrupt Set Register */ + + struct + { + __IM uint32_t MBX_INT0S : 1; /*!< [0..0] Generates or indicates MBX_INT0 interrupt of mailbox + * from external host CPU to internal Cortex-R52. */ + __IM uint32_t MBX_INT1S : 1; /*!< [1..1] Generates or indicates MBX_INT1 interrupt of mailbox + * from external host CPU to internal Cortex-R52. */ + __IM uint32_t MBX_INT2S : 1; /*!< [2..2] Generates or indicates MBX_INT2 interrupt of mailbox + * from external host CPU to internal Cortex-R52. */ + __IM uint32_t MBX_INT3S : 1; /*!< [3..3] Generates or indicates MBX_INT3 interrupt of mailbox + * from external host CPU to internal Cortex-R52. */ + uint32_t : 28; + } MBXISETH2C_b; + }; + + union + { + __IOM uint32_t MBXICLRH2C; /*!< (@ 0x00000054) Host to CR52 Mailbox Interrupt Clear Register */ + + struct + { + __IOM uint32_t MBX_INT0C : 1; /*!< [0..0] Clears or indicates MBX_INT0 interrupt of mailbox from + * external host CPU to internal Cortex-R52. */ + __IOM uint32_t MBX_INT1C : 1; /*!< [1..1] Clears or indicates MBX_INT1 interrupt of mailbox from + * external host CPU to internal Cortex-R52. */ + __IOM uint32_t MBX_INT2C : 1; /*!< [2..2] Clears or indicates MBX_INT2 interrupt of mailbox from + * external host CPU to internal Cortex-R52. */ + __IOM uint32_t MBX_INT3C : 1; /*!< [3..3] Clears or indicates MBX_INT3 interrupt of mailbox from + * external host CPU to internal Cortex-R52. */ + uint32_t : 28; + } MBXICLRH2C_b; + }; + __IM uint32_t RESERVED1[10]; + + union + { + __IOM uint32_t MBXC2H[4]; /*!< (@ 0x00000080) CR52 to Host Mailbox Register [0..3] */ + + struct + { + __IOM uint32_t MBX : 32; /*!< [31..0] MBX */ + } MBXC2H_b[4]; + }; + + union + { + __IOM uint32_t MBXISETC2H; /*!< (@ 0x00000090) CR52 to Host Mailbox Interrupt Set Register */ + + struct + { + __IOM uint32_t MBX_HINT0S : 1; /*!< [0..0] Generates or indicates MBX_HINT0 interrupt of mailbox + * from internal Cortex-R52 to external host CPU. */ + __IOM uint32_t MBX_HINT1S : 1; /*!< [1..1] Generates or indicates MBX_HINT1 interrupt of mailbox + * from internal Cortex-R52 to external host CPU. */ + __IOM uint32_t MBX_HINT2S : 1; /*!< [2..2] Generates or indicates MBX_HINT2 interrupt of mailbox + * from internal Cortex-R52 to external host CPU. */ + __IOM uint32_t MBX_HINT3S : 1; /*!< [3..3] Generates or indicates MBX_HINT3 interrupt of mailbox + * from internal Cortex-R52 to external host CPU. */ + uint32_t : 28; + } MBXISETC2H_b; + }; + + union + { + __IM uint32_t MBXICLRC2H; /*!< (@ 0x00000094) CR52 to Host Mailbox Interrupt Clear Register */ + + struct + { + __IM uint32_t MBX_HINT0C : 1; /*!< [0..0] Clears or indicates MBX_HINT0 interrupt of mailbox from + * internal Cortex-R52 to external host CPU. */ + __IM uint32_t MBX_HINT1C : 1; /*!< [1..1] Clears or indicates MBX_HINT1 interrupt of mailbox from + * internal Cortex-R52 to external host CPU. */ + __IM uint32_t MBX_HINT2C : 1; /*!< [2..2] Clears or indicates MBX_HINT2 interrupt of mailbox from + * internal Cortex-R52 to external host CPU. */ + __IM uint32_t MBX_HINT3C : 1; /*!< [3..3] Clears or indicates MBX_HINT3 interrupt of mailbox from + * internal Cortex-R52 to external host CPU. */ + uint32_t : 28; + } MBXICLRC2H_b; + }; +} R_MBXSEM_Type; /*!< Size = 152 (0x98) */ + +/* =========================================================================================================================== */ +/* ================ R_SHOSTIF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Host Interface (R_SHOSTIF) + */ + +typedef struct /*!< (@ 0x80241000) R_SHOSTIF Structure */ +{ + union + { + __IOM uint32_t CTRLR0; /*!< (@ 0x00000000) Control Register 0 */ + + struct + { + uint32_t : 8; + __IOM uint32_t SCPH : 1; /*!< [8..8] Serial Clock Phase */ + __IOM uint32_t SCPOL : 1; /*!< [9..9] Serial Clock Polarity */ + uint32_t : 22; + } CTRLR0_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t ENR; /*!< (@ 0x00000008) Enable Register */ + + struct + { + __IOM uint32_t ENABLE : 1; /*!< [0..0] SHOSTIF Enable */ + uint32_t : 31; + } ENR_b; + }; + __IM uint32_t RESERVED1[2]; + + union + { + __IOM uint32_t RXFBTR; /*!< (@ 0x00000014) Receive FIFO Burst Threshold Register */ + + struct + { + __IOM uint32_t RXFBTL : 6; /*!< [5..0] Receive FIFO Burst Threshold */ + uint32_t : 26; + } RXFBTR_b; + }; + + union + { + __IOM uint32_t TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register */ + + struct + { + __IOM uint32_t TFT : 6; /*!< [5..0] Transmit FIFO Threshold */ + uint32_t : 26; + } TXFTLR_b; + }; + + union + { + __IOM uint32_t RXFTLR; /*!< (@ 0x0000001C) Receive FIFO Threshold Level Register */ + + struct + { + __IOM uint32_t RFT : 6; /*!< [5..0] Receive FIFO Threshold */ + uint32_t : 26; + } RXFTLR_b; + }; + __IM uint32_t RESERVED2[2]; + + union + { + __IM uint32_t SR; /*!< (@ 0x00000028) Status Register */ + + struct + { + __IM uint32_t BUSY : 1; /*!< [0..0] Busy Flag */ + uint32_t : 31; + } SR_b; + }; + + union + { + __IOM uint32_t IMR; /*!< (@ 0x0000002C) Interrupt Mask Register */ + + struct + { + __IOM uint32_t TXEIM : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Mask */ + uint32_t : 2; + __IOM uint32_t RXOIM : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Mask */ + __IOM uint32_t RXFIM : 1; /*!< [4..4] Receive FIFO Full Interrupt Mask */ + uint32_t : 2; + __IOM uint32_t TXUIM : 1; /*!< [7..7] Transmit FIFO Underflow Mask */ + __IOM uint32_t AHBEM : 1; /*!< [8..8] AHB Error Interrupt Mask */ + __IOM uint32_t SPIMEM : 1; /*!< [9..9] SPI Master Error Interrupt Mask */ + uint32_t : 22; + } IMR_b; + }; + + union + { + __IM uint32_t ISR; /*!< (@ 0x00000030) Interrupt Status Register */ + + struct + { + __IM uint32_t TXEIS : 1; /*!< [0..0] Transmit FIFO Empty Interrupt Status */ + uint32_t : 2; + __IM uint32_t RXOIS : 1; /*!< [3..3] Receive FIFO Overflow Interrupt Status */ + __IM uint32_t RXFIS : 1; /*!< [4..4] Receive FIFO Full Interrupt Status */ + uint32_t : 2; + __IM uint32_t TXUIS : 1; /*!< [7..7] Transmit FIFO Underflow Status */ + __IM uint32_t AHBES : 1; /*!< [8..8] AHB Error Interrupt Status */ + __IM uint32_t SPIMES : 1; /*!< [9..9] SPI Master Error Interrupt Status */ + uint32_t : 22; + } ISR_b; + }; + + union + { + __IM uint32_t RISR; /*!< (@ 0x00000034) Raw Interrupt Status Register */ + + struct + { + __IM uint32_t TXEIR : 1; /*!< [0..0] Transmit FIFO Empty Raw Interrupt Status */ + uint32_t : 2; + __IM uint32_t RXOIR : 1; /*!< [3..3] Receive FIFO Overflow Raw Interrupt Status */ + __IM uint32_t RXFIR : 1; /*!< [4..4] Receive FIFO Full Raw Interrupt Status */ + uint32_t : 2; + __IM uint32_t TXUIR : 1; /*!< [7..7] Transmit FIFO Underflow Raw Interrupt Status */ + __IM uint32_t AHBER : 1; /*!< [8..8] AHB Error Raw Interrupt Status */ + __IM uint32_t SPIMER : 1; /*!< [9..9] SPI Master Error Raw Interrupt Status */ + uint32_t : 22; + } RISR_b; + }; + + union + { + __IM uint32_t TXUICR; /*!< (@ 0x00000038) Transmit FIFO Underflow Interrupt Clear Register */ + + struct + { + __IM uint32_t TXUICR : 1; /*!< [0..0] Clear Transmit FIFO Underflow Interrupt */ + uint32_t : 31; + } TXUICR_b; + }; + + union + { + __IM uint32_t RXOICR; /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt Clear Register */ + + struct + { + __IM uint32_t RXOICR : 1; /*!< [0..0] Clear Receive FIFO Overflow Interrupt */ + uint32_t : 31; + } RXOICR_b; + }; + + union + { + __IM uint32_t SPIMECR; /*!< (@ 0x00000040) SPI Master Interrupt Clear Register */ + + struct + { + __IM uint32_t SPIMECR : 1; /*!< [0..0] Clear SPI Master Error interrupt */ + uint32_t : 31; + } SPIMECR_b; + }; + + union + { + __IM uint32_t AHBECR; /*!< (@ 0x00000044) AHB Error Clear Register */ + + struct + { + __IM uint32_t AHBECR : 1; /*!< [0..0] Clear AHB Error Interrupt */ + uint32_t : 31; + } AHBECR_b; + }; + + union + { + __IM uint32_t ICR; /*!< (@ 0x00000048) Interrupt Clear Register */ + + struct + { + __IM uint32_t ICR : 1; /*!< [0..0] Clear Interrupts */ + uint32_t : 31; + } ICR_b; + }; +} R_SHOSTIF_Type; /*!< Size = 76 (0x4c) */ + +/* =========================================================================================================================== */ +/* ================ R_PHOSTIF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Parallel Host Interface (R_PHOSTIF) + */ + +typedef struct /*!< (@ 0x80242000) R_PHOSTIF Structure */ +{ + union + { + __IOM uint16_t HIFBCC; /*!< (@ 0x00000000) HOSTIF Bus Control Register */ + + struct + { + __IOM uint16_t RBUFON0 : 1; /*!< [0..0] RBUFON0 */ + __IOM uint16_t RBUFON1 : 1; /*!< [1..1] RBUFON1 */ + __IOM uint16_t RBUFON2 : 1; /*!< [2..2] RBUFON2 */ + __IOM uint16_t RBUFON3 : 1; /*!< [3..3] RBUFON3 */ + __IOM uint16_t RBUFON4 : 1; /*!< [4..4] RBUFON4 */ + __IOM uint16_t RBUFON5 : 1; /*!< [5..5] RBUFON5 */ + uint16_t : 2; + __IOM uint16_t RBUFONX : 1; /*!< [8..8] RBUFONX */ + uint16_t : 3; + __IOM uint16_t BSTON : 1; /*!< [12..12] BSTON */ + __IOM uint16_t WRPON : 1; /*!< [13..13] WRPON */ + uint16_t : 2; + } HIFBCC_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t HIFBTC; /*!< (@ 0x00000004) HOSTIF Timing Control Register */ + + struct + { + __IOM uint16_t WRSTD : 3; /*!< [2..0] Specifies the timing for detecting the start of write + * operation by the HWRSTB# signal. */ + uint16_t : 1; + __IOM uint16_t RDSTD : 2; /*!< [5..4] Specifies the timing for detecting the start of read + * operation by the HRD# signal. */ + uint16_t : 2; + __IOM uint16_t PASTD : 3; /*!< [10..8] PASTD */ + uint16_t : 1; + __IOM uint16_t RDDTS : 2; /*!< [13..12] RDDTS */ + uint16_t : 2; + } HIFBTC_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t HIFPRC; /*!< (@ 0x00000008) HOSTIF Page ROM Control Register */ + + struct + { + __IOM uint16_t PAGEON0 : 1; /*!< [0..0] PAGEON0 */ + __IOM uint16_t PAGEON1 : 1; /*!< [1..1] PAGEON1 */ + __IOM uint16_t PAGEON2 : 1; /*!< [2..2] PAGEON2 */ + __IOM uint16_t PAGEON3 : 1; /*!< [3..3] PAGEON3 */ + __IOM uint16_t PAGEON4 : 1; /*!< [4..4] PAGEON4 */ + __IOM uint16_t PAGEON5 : 1; /*!< [5..5] PAGEON5 */ + uint16_t : 2; + __IOM uint16_t PAGEONX : 1; /*!< [8..8] PAGEONX */ + uint16_t : 3; + __IOM uint16_t PAGESZ : 1; /*!< [12..12] PAGESZ */ + uint16_t : 3; + } HIFPRC_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t HIFIRC; /*!< (@ 0x0000000C) HOSTIF Interrupt Request Control Register */ + + struct + { + __IOM uint16_t ERRRSP : 1; /*!< [0..0] This bit is set to 1 on reception of an error response + * from internal slave modules. */ + uint16_t : 15; + } HIFIRC_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IM uint32_t HIFECR0; /*!< (@ 0x00000010) HOSTIF Error Source Register 0 */ + + struct + { + __IM uint32_t ERRADDR : 32; /*!< [31..0] ERRADDR */ + } HIFECR0_b; + }; + + union + { + __IM uint16_t HIFECR1; /*!< (@ 0x00000014) HOSTIF Error Source Register 1 */ + + struct + { + __IM uint16_t ERRSZ : 3; /*!< [2..0] ERRSZ */ + __IM uint16_t ERRWR : 1; /*!< [3..3] ERRWR */ + uint16_t : 12; + } HIFECR1_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint16_t HIFMON1; /*!< (@ 0x00000020) HOSTIF Monitor Register 1 */ + + struct + { + __IOM uint16_t HIFRDY : 1; /*!< [0..0] HIFRDY */ + __IM uint16_t BUSSEL : 1; /*!< [1..1] BUSSEL */ + uint16_t : 1; + __IM uint16_t HIFSYNC : 1; /*!< [3..3] HIFSYNC */ + uint16_t : 12; + } HIFMON1_b; + }; + __IM uint16_t RESERVED6; + + union + { + __IM uint16_t HIFMON2; /*!< (@ 0x00000024) HOSTIF Monitor Register 2 */ + + struct + { + __IM uint16_t HIFBCC : 1; /*!< [0..0] HIFBCC */ + __IM uint16_t HIFBTC : 1; /*!< [1..1] HIFBTC */ + __IM uint16_t HIFPRC : 1; /*!< [2..2] HIFPRC */ + __IM uint16_t HIFIRC : 1; /*!< [3..3] HIFIRC */ + __IM uint16_t HIFXAL : 1; /*!< [4..4] HIFXAL */ + __IM uint16_t HIFXAH : 1; /*!< [5..5] HIFXAH */ + uint16_t : 10; + } HIFMON2_b; + }; + __IM uint16_t RESERVED7; + + union + { + __IM uint16_t HIFMON3; /*!< (@ 0x00000028) HOSTIF Monitor Register 3 */ + + struct + { + __IM uint16_t HIFEXT0 : 1; /*!< [0..0] HIFEXT0 */ + __IM uint16_t HIFEXT1 : 1; /*!< [1..1] HIFEXT1 */ + uint16_t : 14; + } HIFMON3_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9; + + union + { + __IOM uint16_t HIFXAL; /*!< (@ 0x00000030) HOSTIF Specified Area Lower-limit Register */ + + struct + { + __IOM uint16_t XADDRL : 9; /*!< [8..0] Specifies the lower-limit address of the specified area + * to be set in the external bus address space. */ + uint16_t : 7; + } HIFXAL_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t HIFXAH; /*!< (@ 0x00000034) HOSTIF Specified Area Upper-limit Register */ + + struct + { + __IOM uint16_t XADDRH : 9; /*!< [8..0] Specifies the upper-limit address of the specified area + * to be set in the external bus address space. */ + uint16_t : 7; + } HIFXAH_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[18]; + + union + { + __IOM uint16_t HIFEXT0; /*!< (@ 0x00000080) HOSTIF Synchronous Burst Transfer Control Register + * 0 */ + + struct + { + __IOM uint16_t KESSBI : 1; /*!< [0..0] KESSBI */ + uint16_t : 1; + __IOM uint16_t KESDTI : 1; /*!< [2..2] KESDTI */ + __IOM uint16_t KESAVI : 1; /*!< [3..3] KESAVI */ + __IOM uint16_t KESDTO : 1; /*!< [4..4] KESDTO */ + __IOM uint16_t KESWTO : 1; /*!< [5..5] KESWTO */ + uint16_t : 3; + __IOM uint16_t CNDWEO : 1; /*!< [9..9] CNDWEO */ + uint16_t : 5; + __IOM uint16_t MODTRN : 1; /*!< [15..15] MODTRN */ + } HIFEXT0_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t HIFEXT1; /*!< (@ 0x00000084) HOSTIF Synchronous Burst Transfer Control Register + * 1 */ + + struct + { + __IOM uint16_t DLYWA : 4; /*!< [3..0] Minimum time from the last input of the Low level on + * the HBS# pin to the point where write data is received. + * (twc)DLYWA[3:0]CNDWEO = 0CNDWEO = 0HWRSTB# = 0HWRSTB# = + * 1HWRSTB# = 0HWRSTB# = 10x034450x134450x234450x344450x455550x566660x677770 + * 788880x899990x9101010100xA111111110xB121212120xC131313130xD141414140xE151 + * 15150xF16161616 */ + uint16_t : 4; + __IOM uint16_t DLYRA : 4; /*!< [11..8] Minimum time from the last input of the Low level on + * the HBS# pin to the point where read data can be acquired. + * (trc)DLYRA[3:0]CNDWEO = 0CNDWEO = 10x0450x1450x2550x3660x4770x5880x6990x7 + * 0100x811110x912120xA13130xB14140xC15150xD16160xE17170xF1818 */ + uint16_t : 4; + } HIFEXT1_b; + }; + __IM uint16_t RESERVED14; +} R_PHOSTIF_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_NS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System Control for Non-safety region (R_SYSC_NS) + */ + +typedef struct /*!< (@ 0x80280000) R_SYSC_NS Structure */ +{ + union + { + __IOM uint32_t SCKCR; /*!< (@ 0x00000000) System Clock Control Register */ + + struct + { + __IOM uint32_t FSELXSPI0 : 3; /*!< [2..0] Set the frequency of the clock provided to xSPI Unit + * 0 in combination with bit 6 (DIVSELXSPI0). The combination + * is shown below. */ + uint32_t : 3; + __IOM uint32_t DIVSELXSPI0 : 1; /*!< [6..6] Select the base clock to generate serial clock for xSPI + * Unit 0 */ + uint32_t : 1; + __IOM uint32_t FSELXSPI1 : 3; /*!< [10..8] Set the frequency of the clock provided to xSPI Unit + * 1 in combination with bit 14 (DIVSELXSPI1). */ + uint32_t : 3; + __IOM uint32_t DIVSELXSPI1 : 1; /*!< [14..14] Select the base clock to generate serial clock for + * xSPI Unit 1 */ + uint32_t : 1; + __IOM uint32_t CKIO : 3; /*!< [18..16] Set the frequency of the external bus clock (CKIO) + * and the clock supplied to BSC in combination with the DIVSELSUB + * in the SCKCR2 register. The combination is shown below. */ + uint32_t : 1; + __IOM uint32_t FSELCANFD : 1; /*!< [20..20] Select the frequency of the clock supplied to CANFD */ + __IOM uint32_t PHYSEL : 1; /*!< [21..21] Select the Ethernet PHY reference clock output (ETHn_REFCLK, + * n = 0 to 2) */ + __IOM uint32_t CLMASEL : 1; /*!< [22..22] Select alternative clock when main clock abnormal oscillation + * is detected in CLMA3 */ + uint32_t : 1; + __IOM uint32_t SPI0ASYNCSEL : 1; /*!< [24..24] Select clock frequency when asynchronous serial clock + * is selected in SPI0 */ + __IOM uint32_t SPI1ASYNCSEL : 1; /*!< [25..25] Select clock frequency when asynchronous serial clock + * is selected in SPI1 */ + __IOM uint32_t SPI2ASYNCSEL : 1; /*!< [26..26] Select clock frequency when asynchronous serial clock + * is selected in SPI2 */ + __IOM uint32_t SCI0ASYNCSEL : 1; /*!< [27..27] Select clock frequency when asynchronous serial clock + * is selected in SCI0 */ + __IOM uint32_t SCI1ASYNCSEL : 1; /*!< [28..28] Select clock frequency when asynchronous serial clock + * is selected in SCI1 */ + __IOM uint32_t SCI2ASYNCSEL : 1; /*!< [29..29] Select clock frequency when asynchronous serial clock + * is selected in SCI2 */ + __IOM uint32_t SCI3ASYNCSEL : 1; /*!< [30..30] Select clock frequency when asynchronous serial clock + * is selected in SCI3 */ + __IOM uint32_t SCI4ASYNCSEL : 1; /*!< [31..31] Select clock frequency when asynchronous serial clock + * is selected in SCI4 */ + } SCKCR_b; + }; + __IM uint32_t RESERVED[127]; + + union + { + __IOM uint32_t RSTSR0; /*!< (@ 0x00000200) Reset Status Register 0 */ + + struct + { + uint32_t : 1; + __IOM uint32_t TRF : 1; /*!< [1..1] RES# Pin Reset Detect Flag */ + __IOM uint32_t ERRF : 1; /*!< [2..2] Error Reset Detect Flag */ + __IOM uint32_t SWRSF : 1; /*!< [3..3] System Software Reset Detect Flag */ + __IOM uint32_t SWR0F : 1; /*!< [4..4] CPU0 Software Reset Detect Flag */ + uint32_t : 27; + } RSTSR0_b; + }; + __IM uint32_t RESERVED1[15]; + + union + { + __IOM uint32_t MRCTLA; /*!< (@ 0x00000240) Module Reset Control Register A */ + + struct + { + uint32_t : 4; + __IOM uint32_t MRCTLA04 : 1; /*!< [4..4] xSPI Unit 0 Reset Control */ + __IOM uint32_t MRCTLA05 : 1; /*!< [5..5] xSPI Unit 1 Reset Control */ + uint32_t : 26; + } MRCTLA_b; + }; + __IM uint32_t RESERVED2[3]; + + union + { + __IOM uint32_t MRCTLE; /*!< (@ 0x00000250) Module Reset Control Register E */ + + struct + { + __IOM uint32_t MRCTLE00 : 1; /*!< [0..0] GMAC (PCLKH clock domain) Reset Control */ + __IOM uint32_t MRCTLE01 : 1; /*!< [1..1] GMAC (PCLKM clock domain) Reset Control */ + __IOM uint32_t MRCTLE02 : 1; /*!< [2..2] ETHSW Reset Control */ + __IOM uint32_t MRCTLE03 : 1; /*!< [3..3] ESC (Bus clock domain) Reset Control */ + __IOM uint32_t MRCTLE04 : 1; /*!< [4..4] ESC (IP clock domain) Reset Control */ + __IOM uint32_t MRCTLE05 : 1; /*!< [5..5] Ethernet Subsystem Register Reset Control */ + __IOM uint32_t MRCTLE06 : 1; /*!< [6..6] MII Converter Reset Control */ + uint32_t : 25; + } MRCTLE_b; + }; + __IM uint32_t RESERVED3[43]; + + union + { + __IOM uint32_t MSTPCRA; /*!< (@ 0x00000300) Module Stop Control Register A */ + + struct + { + __IOM uint32_t MSTPCRA00 : 1; /*!< [0..0] BSC Module Stop */ + uint32_t : 3; + __IOM uint32_t MSTPCRA04 : 1; /*!< [4..4] xSPI Unit 0 Module Stop */ + __IOM uint32_t MSTPCRA05 : 1; /*!< [5..5] xSPI Unit 1 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRA08 : 1; /*!< [8..8] SCI Unit 0 Module Stop */ + __IOM uint32_t MSTPCRA09 : 1; /*!< [9..9] SCI Unit 1 Module Stop */ + __IOM uint32_t MSTPCRA10 : 1; /*!< [10..10] SCI Unit 2 Module Stop */ + __IOM uint32_t MSTPCRA11 : 1; /*!< [11..11] SCI Unit 3 Module Stop */ + __IOM uint32_t MSTPCRA12 : 1; /*!< [12..12] SCI Unit 4 Module Stop */ + uint32_t : 19; + } MSTPCRA_b; + }; + + union + { + __IOM uint32_t MSTPCRB; /*!< (@ 0x00000304) Module Stop Control Register B */ + + struct + { + __IOM uint32_t MSTPCRB00 : 1; /*!< [0..0] IIC Unit 0 Module Stop */ + __IOM uint32_t MSTPCRB01 : 1; /*!< [1..1] IIC Unit 1 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRB04 : 1; /*!< [4..4] SPI Unit 0 Module Stop */ + __IOM uint32_t MSTPCRB05 : 1; /*!< [5..5] SPI Unit 1 Module Stop */ + __IOM uint32_t MSTPCRB06 : 1; /*!< [6..6] SPI Unit 2 Module Stop */ + uint32_t : 25; + } MSTPCRB_b; + }; + + union + { + __IOM uint32_t MSTPCRC; /*!< (@ 0x00000308) Module Stop Control Register C */ + + struct + { + __IOM uint32_t MSTPCRC00 : 1; /*!< [0..0] MTU3 Module Stop */ + __IOM uint32_t MSTPCRC01 : 1; /*!< [1..1] GPT Unit 0 Module Stop */ + __IOM uint32_t MSTPCRC02 : 1; /*!< [2..2] GPT Unit 1 Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRC05 : 1; /*!< [5..5] TFU Module Stop */ + __IOM uint32_t MSTPCRC06 : 1; /*!< [6..6] ADC12 Unit 0 Module Stop */ + __IOM uint32_t MSTPCRC07 : 1; /*!< [7..7] ADC12 Unit 1 Module Stop */ + uint32_t : 24; + } MSTPCRC_b; + }; + + union + { + __IOM uint32_t MSTPCRD; /*!< (@ 0x0000030C) Module Stop Control Register D */ + + struct + { + __IOM uint32_t MSTPCRD00 : 1; /*!< [0..0] DSMIF Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD01 : 1; /*!< [1..1] DSMIF Unit 1 Module Stop */ + __IOM uint32_t MSTPCRD02 : 1; /*!< [2..2] CMT Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD03 : 1; /*!< [3..3] CMT Unit 1 Module Stop */ + __IOM uint32_t MSTPCRD04 : 1; /*!< [4..4] CMT Unit 2 Module Stop */ + __IOM uint32_t MSTPCRD05 : 1; /*!< [5..5] CMTW Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD06 : 1; /*!< [6..6] CMTW Unit 1 Module Stop */ + __IOM uint32_t MSTPCRD07 : 1; /*!< [7..7] TSU Module Stop */ + __IOM uint32_t MSTPCRD08 : 1; /*!< [8..8] DOC Module Stop */ + __IOM uint32_t MSTPCRD09 : 1; /*!< [9..9] CRC Unit 0 Module Stop */ + __IOM uint32_t MSTPCRD10 : 1; /*!< [10..10] CANFD Module Stop */ + __IOM uint32_t MSTPCRD11 : 1; /*!< [11..11] CKIO Module Stop */ + uint32_t : 20; + } MSTPCRD_b; + }; + + union + { + __IOM uint32_t MSTPCRE; /*!< (@ 0x00000310) Module Stop Control Register E */ + + struct + { + __IOM uint32_t MSTPCRE00 : 1; /*!< [0..0] GMAC Module Stop */ + __IOM uint32_t MSTPCRE01 : 1; /*!< [1..1] ETHSW Module Stop */ + __IOM uint32_t MSTPCRE02 : 1; /*!< [2..2] ESC Module Stop */ + __IOM uint32_t MSTPCRE03 : 1; /*!< [3..3] Ethernet Subsystem Register Module Stop */ + uint32_t : 4; + __IOM uint32_t MSTPCRE08 : 1; /*!< [8..8] USB Module Stop */ + uint32_t : 23; + } MSTPCRE_b; + }; + __IM uint32_t RESERVED4[891]; + + union + { + __IM uint32_t MD_MON; /*!< (@ 0x00001100) Operating Mode Monitor Register */ + + struct + { + __IM uint32_t MDDMON : 1; /*!< [0..0] MDD status flag */ + uint32_t : 7; + __IM uint32_t MDP : 1; /*!< [8..8] Package type */ + uint32_t : 3; + __IM uint32_t MD0MON : 1; /*!< [12..12] MD0 pin status flag */ + __IM uint32_t MD1MON : 1; /*!< [13..13] MD1 pin status flag */ + __IM uint32_t MD2MON : 1; /*!< [14..14] MD2 pin status flag */ + uint32_t : 1; + __IM uint32_t MDV0MON : 1; /*!< [16..16] MDV0 status flag (ETH0 domain) */ + __IM uint32_t MDV1MON : 1; /*!< [17..17] MDV1 status flag (ETH1 domain) */ + __IM uint32_t MDV2MON : 1; /*!< [18..18] MDV2 status flag (ETH2 domain) */ + __IM uint32_t MDV3MON : 1; /*!< [19..19] MDV3 status flag (xSPI0 domain) */ + __IM uint32_t MDV4MON : 1; /*!< [20..20] MDV4 status flag (xSPI1 domain) */ + uint32_t : 11; + } MD_MON_b; + }; +} R_SYSC_NS_Type; /*!< Size = 4356 (0x1104) */ + +/* =========================================================================================================================== */ +/* ================ R_ELO ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Evnet Link Option Setting (R_ELO) + */ + +typedef struct /*!< (@ 0x80281200) R_ELO Structure */ +{ + union + { + __IOM uint32_t ELOPA; /*!< (@ 0x00000000) Event Link Option Setting Register A */ + + struct + { + __IOM uint32_t MTU0MD : 2; /*!< [1..0] MTU0 Operation Select */ + uint32_t : 4; + __IOM uint32_t MTU3MD : 2; /*!< [7..6] MTU3 Operation Select */ + uint32_t : 24; + } ELOPA_b; + }; + + union + { + __IOM uint32_t ELOPB; /*!< (@ 0x00000004) Event Link Option Setting Register B */ + + struct + { + __IOM uint32_t MTU4MD : 2; /*!< [1..0] MTU4 Operation Select */ + uint32_t : 30; + } ELOPB_b; + }; +} R_ELO_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_NS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Register Write Protection for Non-safety Area (R_RWP_NS) + */ + +typedef struct /*!< (@ 0x80281A10) R_RWP_NS Structure */ +{ + union + { + __IOM uint32_t PRCRN; /*!< (@ 0x00000000) Non_Safety Area Protect Register */ + + struct + { + __IOM uint32_t PRC0 : 1; /*!< [0..0] Protect 0 */ + __IOM uint32_t PRC1 : 1; /*!< [1..1] Protect 1 */ + __IOM uint32_t PRC2 : 1; /*!< [2..2] Protect 2 */ + uint32_t : 5; + __OM uint32_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + uint32_t : 16; + } PRCRN_b; + }; +} R_RWP_NS_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Real Time Clock (R_RTC) + */ + +typedef struct /*!< (@ 0x81009000) R_RTC Structure */ +{ + union + { + __IOM uint32_t RTCA0CTL0; /*!< (@ 0x00000000) RTC Control Register 0 */ + + struct + { + uint32_t : 4; + __IOM uint32_t RTCA0SLSB : 1; /*!< [4..4] RTCA0SCMP enable/disable setting */ + __IOM uint32_t RTCA0AMPM : 1; /*!< [5..5] RTCA0HOUR, RTCA0ALH display format selection bit */ + __IM uint32_t RTCA0CEST : 1; /*!< [6..6] RTC Controller Enable Status */ + __IOM uint32_t RTCA0CE : 1; /*!< [7..7] RTC Controller Enable Bit */ + uint32_t : 24; + } RTCA0CTL0_b; + }; + + union + { + __IOM uint32_t RTCA0CTL1; /*!< (@ 0x00000004) RTC Control Register 1 */ + + struct + { + __IOM uint32_t RTCA0CT : 3; /*!< [2..0] Fixed interval interrupt (RTC_PRD) output setting bit */ + __IOM uint32_t RTCA01SE : 1; /*!< [3..3] 1 second interrupt (RTC_1S) output enable bit */ + __IOM uint32_t RTCA0ALME : 1; /*!< [4..4] Alarm interrupt (RTC_ALM) output enable bit */ + __IOM uint32_t RTCA01HZE : 1; /*!< [5..5] This bit enables/disables 1 Hz pulse output (RTCAT1HZ). */ + uint32_t : 26; + } RTCA0CTL1_b; + }; + + union + { + __IOM uint32_t RTCA0CTL2; /*!< (@ 0x00000008) RTC Control Register 2 */ + + struct + { + __IOM uint32_t RTCA0WAIT : 1; /*!< [0..0] RTC Controller Counter Wait Control */ + __IM uint32_t RTCA0WST : 1; /*!< [1..1] RTC Controller Counter Wait Status */ + __IOM uint32_t RTCA0RSUB : 1; /*!< [2..2] RTCA0SUBC Data Transfer Control */ + __IM uint32_t RTCA0RSST : 1; /*!< [3..3] RTCA0SRBU Transfer Status */ + __IM uint32_t RTCA0WSST : 1; /*!< [4..4] RTCA0SCMP Write Status */ + uint32_t : 27; + } RTCA0CTL2_b; + }; + + union + { + __IM uint32_t RTCA0SUBC; /*!< (@ 0x0000000C) RTC Sub Count Register */ + + struct + { + __IM uint32_t RTCA0SUBC : 22; /*!< [21..0] Register that counts the 1 second reference time */ + uint32_t : 10; + } RTCA0SUBC_b; + }; + + union + { + __IM uint32_t RTCA0SRBU; /*!< (@ 0x00000010) RTC Sub Count Register Read Buffer */ + + struct + { + __IM uint32_t RTCA0SRBU : 22; /*!< [21..0] Read buffer register of RTCA0SUBC */ + uint32_t : 10; + } RTCA0SRBU_b; + }; + + union + { + __IOM uint32_t RTCA0SEC; /*!< (@ 0x00000014) RTC Sec Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0SEC : 7; /*!< [6..0] Buffer register to read/write RTC Second Count register + * (RTCA0SECC). */ + uint32_t : 25; + } RTCA0SEC_b; + }; + + union + { + __IOM uint32_t RTCA0MIN; /*!< (@ 0x00000018) RTC Min Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0MIN : 7; /*!< [6..0] Buffer register to read/write RTC Minute Count register + * (RTCA0MINC). */ + uint32_t : 25; + } RTCA0MIN_b; + }; + + union + { + __IOM uint32_t RTCA0HOUR; /*!< (@ 0x0000001C) RTC Hour Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0HOUR : 6; /*!< [5..0] Buffer register to read/write RTC Hour Count register + * (RTCA0HOURC). */ + uint32_t : 26; + } RTCA0HOUR_b; + }; + + union + { + __IOM uint32_t RTCA0WEEK; /*!< (@ 0x00000020) RTC Week Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0WEEK : 3; /*!< [2..0] Buffer register to read/write RTC Week Count register + * (RTCA0WEEKC). */ + uint32_t : 29; + } RTCA0WEEK_b; + }; + + union + { + __IOM uint32_t RTCA0DAY; /*!< (@ 0x00000024) RTC Day Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0DAY : 6; /*!< [5..0] Buffer register to read/write RTC Day Count register + * (RTCA0DAYC). */ + uint32_t : 26; + } RTCA0DAY_b; + }; + + union + { + __IOM uint32_t RTCA0MONTH; /*!< (@ 0x00000028) RTC Month Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0MONTH : 5; /*!< [4..0] Buffer register to read/write RTC Month Count register + * (RTCA0MONC). */ + uint32_t : 27; + } RTCA0MONTH_b; + }; + + union + { + __IOM uint32_t RTCA0YEAR; /*!< (@ 0x0000002C) RTC Year Count Buffer Register */ + + struct + { + __IOM uint32_t RTCA0YEAR : 8; /*!< [7..0] Buffer register to read/write RTC Year Count register + * (RTCA0YEARC). */ + uint32_t : 24; + } RTCA0YEAR_b; + }; + + union + { + __IOM uint32_t RTCA0TIME; /*!< (@ 0x00000030) RTC Time Set Register */ + + struct + { + __IOM uint32_t RTCA0SEC : 8; /*!< [7..0] See RTCA0SEC register */ + __IOM uint32_t RTCA0MIN : 8; /*!< [15..8] See RTCA0MIN register */ + __IOM uint32_t RTCA0HOUR : 8; /*!< [23..16] See RTCA0HOUR register */ + uint32_t : 8; + } RTCA0TIME_b; + }; + + union + { + __IOM uint32_t RTCA0CAL; /*!< (@ 0x00000034) RTC Calendar Set Register */ + + struct + { + __IOM uint32_t RTCA0WEEK : 8; /*!< [7..0] See RTCA0WEEK register */ + __IOM uint32_t RTCA0DAY : 8; /*!< [15..8] See RTCA0DAY register */ + __IOM uint32_t RTCA0MONTH : 8; /*!< [23..16] See RTCA0MONTH register */ + __IOM uint32_t RTCA0YEAR : 8; /*!< [31..24] See RTCA0YEAR register */ + } RTCA0CAL_b; + }; + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t RTCA0SCMP; /*!< (@ 0x0000003C) RTC Sub Count Compare Register */ + + struct + { + __IOM uint32_t RTCA0SCMP : 22; /*!< [21..0] Register that sets the compare value of RTCA0SUBC (sub-counter). */ + uint32_t : 10; + } RTCA0SCMP_b; + }; + + union + { + __IOM uint32_t RTCA0ALM; /*!< (@ 0x00000040) RTC Alarm Min Set Register */ + + struct + { + __IOM uint32_t RTCA0ALM : 7; /*!< [6..0] RTCA0ALM is a register that performs the minute setting + * for the alarm interrupt. */ + uint32_t : 25; + } RTCA0ALM_b; + }; + + union + { + __IOM uint32_t RTCA0ALH; /*!< (@ 0x00000044) RTC Alarm Hour Set Register */ + + struct + { + __IOM uint32_t RTCA0ALH : 6; /*!< [5..0] RTCA0ALH is a register that performs the hour setting + * for the alarm interrupt. */ + uint32_t : 26; + } RTCA0ALH_b; + }; + + union + { + __IOM uint32_t RTCA0ALW; /*!< (@ 0x00000048) RTC Alarm Week Set Register */ + + struct + { + __IOM uint32_t RTCA0ALW0 : 1; /*!< [0..0] Alarm interrupt day of the week setting bit 0 */ + __IOM uint32_t RTCA0ALW1 : 1; /*!< [1..1] Alarm interrupt day of the week setting bit 1 */ + __IOM uint32_t RTCA0ALW2 : 1; /*!< [2..2] Alarm interrupt day of the week setting bit 2 */ + __IOM uint32_t RTCA0ALW3 : 1; /*!< [3..3] Alarm interrupt day of the week setting bit 3 */ + __IOM uint32_t RTCA0ALW4 : 1; /*!< [4..4] Alarm interrupt day of the week setting bit 4 */ + __IOM uint32_t RTCA0ALW5 : 1; /*!< [5..5] Alarm interrupt day of the week setting bit 5 */ + __IOM uint32_t RTCA0ALW6 : 1; /*!< [6..6] Alarm interrupt day of the week setting bit 6 */ + uint32_t : 25; + } RTCA0ALW_b; + }; + + union + { + __IM uint32_t RTCA0SECC; /*!< (@ 0x0000004C) RTC Second Count Register */ + + struct + { + __IM uint32_t RTCA0SECC : 7; /*!< [6..0] Counts up the seconds */ + uint32_t : 25; + } RTCA0SECC_b; + }; + + union + { + __IM uint32_t RTCA0MINC; /*!< (@ 0x00000050) RTC Minute Count Register */ + + struct + { + __IM uint32_t RTCA0MINC : 7; /*!< [6..0] Counts up the minutes */ + uint32_t : 25; + } RTCA0MINC_b; + }; + + union + { + __IM uint32_t RTCA0HOURC; /*!< (@ 0x00000054) RTC Hour Count Register */ + + struct + { + __IM uint32_t RTCA0HOURC : 6; /*!< [5..0] Counts up the hours */ + uint32_t : 26; + } RTCA0HOURC_b; + }; + + union + { + __IM uint32_t RTCA0WEEKC; /*!< (@ 0x00000058) RTC Week Count Register */ + + struct + { + __IM uint32_t RTCA0WEEKC : 3; /*!< [2..0] Counts up the weeks */ + uint32_t : 29; + } RTCA0WEEKC_b; + }; + + union + { + __IM uint32_t RTCA0DAYC; /*!< (@ 0x0000005C) RTC Day Count Register */ + + struct + { + __IM uint32_t RTCA0DAYC : 6; /*!< [5..0] Counts up the days */ + uint32_t : 26; + } RTCA0DAYC_b; + }; + + union + { + __IM uint32_t RTCA0MONC; /*!< (@ 0x00000060) RTC Month Count Register */ + + struct + { + __IM uint32_t RTCA0MONC : 5; /*!< [4..0] Counts up the months */ + uint32_t : 27; + } RTCA0MONC_b; + }; + + union + { + __IM uint32_t RTCA0YEARC; /*!< (@ 0x00000064) RTC Year Count Register */ + + struct + { + __IM uint32_t RTCA0YEARC : 8; /*!< [7..0] Counts up the years */ + uint32_t : 24; + } RTCA0YEARC_b; + }; + + union + { + __IM uint32_t RTCA0TIMEC; /*!< (@ 0x00000068) RTC Time Count Register */ + + struct + { + __IM uint32_t RTCA0SECC : 8; /*!< [7..0] See RTCA0SECC register */ + __IM uint32_t RTCA0MINC : 8; /*!< [15..8] See RTCA0MINC register */ + __IM uint32_t RTCA0HOURC : 8; /*!< [23..16] See RTCA0HOURC register */ + uint32_t : 8; + } RTCA0TIMEC_b; + }; + + union + { + __IM uint32_t RTCA0CALC; /*!< (@ 0x0000006C) RTC Calendar Count Register */ + + struct + { + __IM uint32_t RTCA0WEEKC : 8; /*!< [7..0] See RTCA0WEEKC register */ + __IM uint32_t RTCA0DAYC : 8; /*!< [15..8] See RTCA0DAYC register */ + __IM uint32_t RTCA0MONC : 8; /*!< [23..16] See RTCA0MONC register */ + __IM uint32_t RTCA0YEARC : 8; /*!< [31..24] See RTCA0YEARC register */ + } RTCA0CALC_b; + }; +} R_RTC_Type; /*!< Size = 112 (0x70) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPT Port Output Enable 2 (R_POEG2) + */ + +typedef struct /*!< (@ 0x8100A000) R_POEG2 Structure */ +{ + union + { + __IOM uint32_t POEG2GA; /*!< (@ 0x00000000) POEG2 Group A Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GA_b; + }; + __IM uint32_t RESERVED[255]; + + union + { + __IOM uint32_t POEG2GB; /*!< (@ 0x00000400) POEG2 Group B Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GB_b; + }; + __IM uint32_t RESERVED1[255]; + + union + { + __IOM uint32_t POEG2GC; /*!< (@ 0x00000800) POEG2 Group C Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GC_b; + }; + __IM uint32_t RESERVED2[255]; + + union + { + __IOM uint32_t POEG2GD; /*!< (@ 0x00000C00) POEG2 Group D Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 11; + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG2GD_b; + }; +} R_POEG2_Type; /*!< Size = 3076 (0xc04) */ + +/* =========================================================================================================================== */ +/* ================ R_OTP ================ */ +/* =========================================================================================================================== */ + +/** + * @brief One-Time Programmable Memory (R_OTP) + */ + +typedef struct /*!< (@ 0x81028000) R_OTP Structure */ +{ + union + { + __IOM uint32_t OTPPWR; /*!< (@ 0x00000000) OTP Power Control Register */ + + struct + { + __IOM uint32_t PWR : 1; /*!< [0..0] OTP power on/off setting */ + uint32_t : 3; + __IOM uint32_t ACCL : 1; /*!< [4..4] Selects OTP access I/F */ + uint32_t : 27; + } OTPPWR_b; + }; + + union + { + __IOM uint32_t OTPSTR; /*!< (@ 0x00000004) OTP Access Status Register */ + + struct + { + __IM uint32_t CMD_RDY : 1; /*!< [0..0] Indicates whether OTP controller is ready to receive + * command or not. */ + __IM uint32_t ERR_WR : 2; /*!< [2..1] OTP write status */ + __IM uint32_t ERR_WP : 1; /*!< [3..3] Write protection error */ + __IM uint32_t ERR_RP : 1; /*!< [4..4] Read protection error */ + uint32_t : 3; + __IOM uint32_t ERR_RDY_WR : 1; /*!< [8..8] OTP write command ready error */ + __IOM uint32_t ERR_RDY_RD : 1; /*!< [9..9] OTP read command ready error */ + uint32_t : 5; + __IM uint32_t CNT_ST_IDLE : 1; /*!< [15..15] Indicates status of OTP controller */ + uint32_t : 16; + } OTPSTR_b; + }; + + union + { + __IOM uint32_t OTPSTAWR; /*!< (@ 0x00000008) OTP Write Command Register */ + + struct + { + __IOM uint32_t STAWR : 1; /*!< [0..0] OTP write start */ + uint32_t : 31; + } OTPSTAWR_b; + }; + + union + { + __IOM uint32_t OTPADRWR; /*!< (@ 0x0000000C) OTP Write Address Register */ + + struct + { + __IOM uint32_t ADRWR : 9; /*!< [8..0] OTP write address */ + uint32_t : 23; + } OTPADRWR_b; + }; + + union + { + __IOM uint32_t OTPDATAWR; /*!< (@ 0x00000010) OTP Write Data Register */ + + struct + { + __IOM uint32_t DATAWR : 16; /*!< [15..0] OTP write data */ + uint32_t : 16; + } OTPDATAWR_b; + }; + + union + { + __IOM uint32_t OTPADRRD; /*!< (@ 0x00000014) OTP Read Address Register */ + + struct + { + __IOM uint32_t ADRRD : 9; /*!< [8..0] OTP read address */ + uint32_t : 23; + } OTPADRRD_b; + }; + + union + { + __IM uint32_t OTPDATARD; /*!< (@ 0x00000018) OTP Read Data Register */ + + struct + { + __IM uint32_t DATARD : 16; /*!< [15..0] OTP read data */ + uint32_t : 16; + } OTPDATARD_b; + }; +} R_OTP_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_PTADR ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Address Selection (R_PTADR) + */ + +typedef struct /*!< (@ 0x81030C00) R_PTADR Structure */ +{ + union + { + __IOM uint8_t RSELP[25]; /*!< (@ 0x00000000) Port [0..24] Region Select Register */ + + struct + { + __IOM uint8_t RS0 : 1; /*!< [0..0] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS1 : 1; /*!< [1..1] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS2 : 1; /*!< [2..2] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS3 : 1; /*!< [3..3] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS4 : 1; /*!< [4..4] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS5 : 1; /*!< [5..5] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS6 : 1; /*!< [6..6] Pm_n pin I/O port registers Region Select (n = bit position) */ + __IOM uint8_t RS7 : 1; /*!< [7..7] Pm_n pin I/O port registers Region Select (n = bit position) */ + } RSELP_b[25]; + }; +} R_PTADR_Type; /*!< Size = 25 (0x19) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System SRAM 0 (R_SYSRAM0) + */ + +typedef struct /*!< (@ 0x81040000) R_SYSRAM0 Structure */ +{ + __IOM R_SYSRAM0_W_Type W[4]; /*!< (@ 0x00000000) System SRAM Wn Registers (n = 0 to 3) */ +} R_SYSRAM0_Type; /*!< Size = 256 (0x100) */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Interrupt Controller (R_ICU) + */ + +typedef struct /*!< (@ 0x81048000) R_ICU Structure */ +{ + union + { + __OM uint32_t S_SWINT; /*!< (@ 0x00000000) Software Interrupt Register for Safety Register */ + + struct + { + __OM uint32_t IC6 : 1; /*!< [0..0] Software Interrupt register */ + __OM uint32_t IC7 : 1; /*!< [1..1] Software Interrupt register */ + uint32_t : 30; + } S_SWINT_b; + }; + + union + { + __IOM uint32_t S_PORTNF_FLTSEL; /*!< (@ 0x00000004) Interrupt Noise Filter Enable Register for Safety + * Register */ + + struct + { + __IOM uint32_t FLT14 : 1; /*!< [0..0] Noise filter enable for IRQ14 */ + __IOM uint32_t FLT15 : 1; /*!< [1..1] Noise filter enable for IRQ15 */ + __IOM uint32_t FLTNMI : 1; /*!< [2..2] Noise filter enable for NMI */ + uint32_t : 29; + } S_PORTNF_FLTSEL_b; + }; + + union + { + __IOM uint32_t S_PORTNF_CLKSEL; /*!< (@ 0x00000008) Interrupt Noise Filter Setting Register for Safety + * Register */ + + struct + { + __IOM uint32_t CKSEL14 : 2; /*!< [1..0] Select noise filter sampling frequency dividend rate + * for IRQ14. */ + __IOM uint32_t CKSEL15 : 2; /*!< [3..2] Select noise filter sampling frequency dividend rate + * for IRQ15. */ + __IOM uint32_t CKSELNMI : 2; /*!< [5..4] Select noise filter sampling frequency dividend rate + * for NMI. */ + uint32_t : 26; + } S_PORTNF_CLKSEL_b; + }; + + union + { + __IOM uint32_t S_PORTNF_MD; /*!< (@ 0x0000000C) Interrupt Edge Detection Setting Register for + * Safety Register */ + + struct + { + __IOM uint32_t MD14 : 2; /*!< [1..0] Select detection mode for IRQ14 */ + __IOM uint32_t MD15 : 2; /*!< [3..2] Select detection mode for IRQ15 */ + __IOM uint32_t MDNMI : 2; /*!< [5..4] Select detection mode for NMI */ + uint32_t : 26; + } S_PORTNF_MD_b; + }; + __IM uint32_t RESERVED[20]; + + union + { + __IM uint32_t CPU0ERR_STAT; /*!< (@ 0x00000060) CPU0 Error Event Status Register */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate captured error status for CPU0_ERREVENT0 */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate captured error status for CPU0_ERREVENT1 */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate captured error status for CPU0_ERREVENT2 */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate captured error status for CPU0_ERREVENT3 */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate captured error status for CPU0_ERREVENT4 */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate captured error status for CPU0_ERREVENT5 */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate captured error status for CPU0_ERREVENT6 */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate captured error status for CPU0_ERREVENT7 */ + __IM uint32_t ER_ST8 : 1; /*!< [8..8] Indicate captured error status for CPU0_ERREVENT8 */ + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate captured error status for CPU0_ERREVENT9 */ + __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for CPU0_ERREVENT10 */ + __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for CPU0_ERREVENT11 */ + __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for CPU0_ERREVENT12 */ + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for CPU0_ERREVENT13 */ + __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for CPU0_ERREVENT14 */ + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for CPU0_ERREVENT15 */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for CPU0_ERREVENT16 */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for CPU0_ERREVENT17 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for CPU0_ERREVENT18 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for CPU0_ERREVENT19 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for CPU0_ERREVENT20 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for CPU0_ERREVENT21 */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for CPU0_ERREVENT22 */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for CPU0_ERREVENT23 */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for CPU0_ERREVENT24 */ + __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for CPU0_ERREVENT25 */ + uint32_t : 6; + } CPU0ERR_STAT_b; + }; + __IM uint32_t RESERVED1; + + union + { + __IM uint32_t PERIERR_STAT0; /*!< (@ 0x00000068) Peripheral Error Event Status Register 0 */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate captured error status for CLMA3_INT */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate captured error status for CLMA0_INT */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate captured error status for CLMA1_INT */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate captured error status for CLMA2_INT */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate captured error status for BSC_WTO */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate captured error status for DMAC0_ERR */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate captured error status for DMAC1_ERR */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate captured error status for WDT_NMIUNDF0 */ + uint32_t : 1; + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate captured error status for USB_FDMAERR */ + __IM uint32_t ER_ST10 : 1; /*!< [10..10] Indicate captured error status for DSMIF0_LTCSE */ + __IM uint32_t ER_ST11 : 1; /*!< [11..11] Indicate captured error status for DSMIF0_UTCSE */ + __IM uint32_t ER_ST12 : 1; /*!< [12..12] Indicate captured error status for DSMIF0_LTODE0 */ + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for DSMIF0_LTODE1 */ + __IM uint32_t ER_ST14 : 1; /*!< [14..14] Indicate captured error status for DSMIF0_LTODE2 */ + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for DSMIF0_UTODE0 */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for DSMIF0_UTODE1 */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for DSMIF0_UTODE2 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for DSMIF0_SCDE0 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for DSMIF0_SCDE1 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for DSMIF0_SCDE2 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for DSMIF1_LTCSE */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for DSMIF1_UTCSE */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for DSMIF1_LTODE0 */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for DSMIF1_LTODE1 */ + __IM uint32_t ER_ST25 : 1; /*!< [25..25] Indicate captured error status for DSMIF1_LTODE2 */ + __IM uint32_t ER_ST26 : 1; /*!< [26..26] Indicate captured error status for DSMIF1_UTODE0 */ + __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for DSMIF1_UTODE1 */ + __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for DSMIF1_UTODE2 */ + __IM uint32_t ER_ST29 : 1; /*!< [29..29] Indicate captured error status for DSMIF1_SCDE0 */ + __IM uint32_t ER_ST30 : 1; /*!< [30..30] Indicate captured error status for DSMIF1_SCDE1 */ + __IM uint32_t ER_ST31 : 1; /*!< [31..31] Indicate captured error status for DSMIF1_SCDE2 */ + } PERIERR_STAT0_b; + }; + + union + { + __IM uint32_t PERIERR_STAT1; /*!< (@ 0x0000006C) Peripheral Error Event Status Register 1 */ + + struct + { + __IM uint32_t ER_ST0 : 1; /*!< [0..0] Indicate captured error status for DOC_DOPCI */ + __IM uint32_t ER_ST1 : 1; /*!< [1..1] Indicate captured error status for SRAM0_IE1 */ + __IM uint32_t ER_ST2 : 1; /*!< [2..2] Indicate captured error status for SRAM0_IE2 */ + __IM uint32_t ER_ST3 : 1; /*!< [3..3] Indicate captured error status for SRAM0_OVF */ + __IM uint32_t ER_ST4 : 1; /*!< [4..4] Indicate captured error status for SRAM1_IE1 */ + __IM uint32_t ER_ST5 : 1; /*!< [5..5] Indicate captured error status for SRAM1_IE2 */ + __IM uint32_t ER_ST6 : 1; /*!< [6..6] Indicate captured error status for SRAM1_OVF */ + __IM uint32_t ER_ST7 : 1; /*!< [7..7] Indicate captured error status for SRAM2_IE1 */ + __IM uint32_t ER_ST8 : 1; /*!< [8..8] Indicate captured error status for SRAM2_IE2 */ + __IM uint32_t ER_ST9 : 1; /*!< [9..9] Indicate captured error status for SRAM2_OVF */ + uint32_t : 3; + __IM uint32_t ER_ST13 : 1; /*!< [13..13] Indicate captured error status for BUS_ERRINT */ + uint32_t : 1; + __IM uint32_t ER_ST15 : 1; /*!< [15..15] Indicate captured error status for MPU_SHOSTIF */ + __IM uint32_t ER_ST16 : 1; /*!< [16..16] Indicate captured error status for MPU_PHOSTIF */ + __IM uint32_t ER_ST17 : 1; /*!< [17..17] Indicate captured error status for MPU_DMACR0 */ + __IM uint32_t ER_ST18 : 1; /*!< [18..18] Indicate captured error status for MPU_DMACW0 */ + __IM uint32_t ER_ST19 : 1; /*!< [19..19] Indicate captured error status for MPU_DMACR1 */ + __IM uint32_t ER_ST20 : 1; /*!< [20..20] Indicate captured error status for MPU_DMACW1 */ + __IM uint32_t ER_ST21 : 1; /*!< [21..21] Indicate captured error status for MPU_GMACR */ + __IM uint32_t ER_ST22 : 1; /*!< [22..22] Indicate captured error status for MPU_GMACW */ + __IM uint32_t ER_ST23 : 1; /*!< [23..23] Indicate captured error status for MPU_USBH */ + __IM uint32_t ER_ST24 : 1; /*!< [24..24] Indicate captured error status for MPU_USBF */ + uint32_t : 2; + __IM uint32_t ER_ST27 : 1; /*!< [27..27] Indicate captured error status for MPU_DBGR */ + __IM uint32_t ER_ST28 : 1; /*!< [28..28] Indicate captured error status for MPU_DBGW */ + uint32_t : 3; + } PERIERR_STAT1_b; + }; + + union + { + __OM uint32_t CPU0ERR_CLR; /*!< (@ 0x00000070) CPU0 Error Event Status Clear Register */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL8 : 1; /*!< [8..8] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL9 : 1; /*!< [9..9] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for CPU0ERR_STAT register + * by writing 1 */ + uint32_t : 6; + } CPU0ERR_CLR_b; + }; + __IM uint32_t RESERVED2; + + union + { + __OM uint32_t PERIERR_CLR0; /*!< (@ 0x00000078) Peripheral Error Event Status Clear Register + * 0 */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + uint32_t : 1; + __OM uint32_t ER_CL9 : 1; /*!< [9..9] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL10 : 1; /*!< [10..10] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL11 : 1; /*!< [11..11] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL12 : 1; /*!< [12..12] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL14 : 1; /*!< [14..14] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL25 : 1; /*!< [25..25] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL26 : 1; /*!< [26..26] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL29 : 1; /*!< [29..29] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL30 : 1; /*!< [30..30] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + __OM uint32_t ER_CL31 : 1; /*!< [31..31] Clear captured error status for PERIERR_STAT0 register + * by writing 1 */ + } PERIERR_CLR0_b; + }; + + union + { + __OM uint32_t PERIERR_CLR1; /*!< (@ 0x0000007C) Peripheral Error Event Status Clear Register + * 1 */ + + struct + { + __OM uint32_t ER_CL0 : 1; /*!< [0..0] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL1 : 1; /*!< [1..1] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL2 : 1; /*!< [2..2] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL3 : 1; /*!< [3..3] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL4 : 1; /*!< [4..4] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL5 : 1; /*!< [5..5] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL6 : 1; /*!< [6..6] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL7 : 1; /*!< [7..7] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL8 : 1; /*!< [8..8] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL9 : 1; /*!< [9..9] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + uint32_t : 3; + __OM uint32_t ER_CL13 : 1; /*!< [13..13] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + uint32_t : 1; + __OM uint32_t ER_CL15 : 1; /*!< [15..15] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL16 : 1; /*!< [16..16] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL17 : 1; /*!< [17..17] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL18 : 1; /*!< [18..18] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL19 : 1; /*!< [19..19] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL20 : 1; /*!< [20..20] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL21 : 1; /*!< [21..21] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL22 : 1; /*!< [22..22] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL23 : 1; /*!< [23..23] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL24 : 1; /*!< [24..24] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + uint32_t : 2; + __OM uint32_t ER_CL27 : 1; /*!< [27..27] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + __OM uint32_t ER_CL28 : 1; /*!< [28..28] Clear captured error status for PERIERR_STAT1 register + * by writing 1 */ + uint32_t : 3; + } PERIERR_CLR1_b; + }; + + union + { + __IOM uint32_t CPU0ERR_RSTMSK; /*!< (@ 0x00000080) CPU0 Error Event Reset Mask Register */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK8 : 1; /*!< [8..8] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for CPU0ERR_STAT */ + __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for CPU0ERR_STAT */ + uint32_t : 6; + } CPU0ERR_RSTMSK_b; + }; + __IM uint32_t RESERVED3; + + union + { + __IOM uint32_t PERIERR_RSTMSK0; /*!< (@ 0x00000088) Peripheral Error Event Reset Mask Register 0 */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT0 */ + uint32_t : 1; + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK10 : 1; /*!< [10..10] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK11 : 1; /*!< [11..11] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK12 : 1; /*!< [12..12] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK14 : 1; /*!< [14..14] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK25 : 1; /*!< [25..25] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK26 : 1; /*!< [26..26] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK29 : 1; /*!< [29..29] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK30 : 1; /*!< [30..30] Mask captured error status as a reset event for PERIERR_STAT0 */ + __IOM uint32_t RS_MK31 : 1; /*!< [31..31] Mask captured error status as a reset event for PERIERR_STAT0 */ + } PERIERR_RSTMSK0_b; + }; + + union + { + __IOM uint32_t PERIERR_RSTMSK1; /*!< (@ 0x0000008C) Peripheral Error Event Reset Mask Register 1 */ + + struct + { + __IOM uint32_t RS_MK0 : 1; /*!< [0..0] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK1 : 1; /*!< [1..1] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK2 : 1; /*!< [2..2] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK3 : 1; /*!< [3..3] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK4 : 1; /*!< [4..4] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK5 : 1; /*!< [5..5] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK6 : 1; /*!< [6..6] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK7 : 1; /*!< [7..7] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK8 : 1; /*!< [8..8] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK9 : 1; /*!< [9..9] Mask captured error status as a reset event for PERIERR_STAT1 */ + uint32_t : 3; + __IOM uint32_t RS_MK13 : 1; /*!< [13..13] Mask captured error status as a reset event for PERIERR_STAT1 */ + uint32_t : 1; + __IOM uint32_t RS_MK15 : 1; /*!< [15..15] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK16 : 1; /*!< [16..16] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK17 : 1; /*!< [17..17] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK18 : 1; /*!< [18..18] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK19 : 1; /*!< [19..19] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK20 : 1; /*!< [20..20] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK21 : 1; /*!< [21..21] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK22 : 1; /*!< [22..22] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK23 : 1; /*!< [23..23] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK24 : 1; /*!< [24..24] Mask captured error status as a reset event for PERIERR_STAT1 */ + uint32_t : 2; + __IOM uint32_t RS_MK27 : 1; /*!< [27..27] Mask captured error status as a reset event for PERIERR_STAT1 */ + __IOM uint32_t RS_MK28 : 1; /*!< [28..28] Mask captured error status as a reset event for PERIERR_STAT1 */ + uint32_t : 3; + } PERIERR_RSTMSK1_b; + }; + + union + { + __IOM uint32_t CPU0ERR_E0MSK; /*!< (@ 0x00000090) CPU0 E0 Error Event Mask Register */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK8 : 1; /*!< [8..8] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an CPU0_ERR0 event for + * CPU0ERR_STAT */ + uint32_t : 6; + } CPU0ERR_E0MSK_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IOM uint32_t PERIERR_E0MSK0; /*!< (@ 0x00000098) Peripheral E0 Error Event Mask Register 0 */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + uint32_t : 1; + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK10 : 1; /*!< [10..10] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK11 : 1; /*!< [11..11] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK12 : 1; /*!< [12..12] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK14 : 1; /*!< [14..14] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK25 : 1; /*!< [25..25] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK26 : 1; /*!< [26..26] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK29 : 1; /*!< [29..29] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK30 : 1; /*!< [30..30] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + __IOM uint32_t E0_MK31 : 1; /*!< [31..31] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT0 */ + } PERIERR_E0MSK0_b; + }; + + union + { + __IOM uint32_t PERIERR_E0MSK1; /*!< (@ 0x0000009C) Peripheral E0 Error Event Mask Register 1 */ + + struct + { + __IOM uint32_t E0_MK0 : 1; /*!< [0..0] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK1 : 1; /*!< [1..1] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK2 : 1; /*!< [2..2] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK3 : 1; /*!< [3..3] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK4 : 1; /*!< [4..4] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK5 : 1; /*!< [5..5] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK6 : 1; /*!< [6..6] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK7 : 1; /*!< [7..7] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK8 : 1; /*!< [8..8] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK9 : 1; /*!< [9..9] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + uint32_t : 3; + __IOM uint32_t E0_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + uint32_t : 1; + __IOM uint32_t E0_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + uint32_t : 2; + __IOM uint32_t E0_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + __IOM uint32_t E0_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR0 event for + * PERIERR_STAT1 */ + uint32_t : 3; + } PERIERR_E0MSK1_b; + }; + __IM uint32_t RESERVED5[24]; + + union + { + __IOM uint32_t CPU0ERR_E1MSK; /*!< (@ 0x00000100) CPU0 E1 Error Event Mask Register */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK8 : 1; /*!< [8..8] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an CPU0_ERR1 event for + * CPU0ERR_STAT */ + uint32_t : 6; + } CPU0ERR_E1MSK_b; + }; + __IM uint32_t RESERVED6; + + union + { + __IOM uint32_t PERIERR_E1MSK0; /*!< (@ 0x00000108) Peripheral E1 Error Event Mask Register 0 */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + uint32_t : 1; + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK10 : 1; /*!< [10..10] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK11 : 1; /*!< [11..11] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK12 : 1; /*!< [12..12] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK14 : 1; /*!< [14..14] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK25 : 1; /*!< [25..25] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK26 : 1; /*!< [26..26] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK29 : 1; /*!< [29..29] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK30 : 1; /*!< [30..30] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + __IOM uint32_t E1_MK31 : 1; /*!< [31..31] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT0 */ + } PERIERR_E1MSK0_b; + }; + + union + { + __IOM uint32_t PERIERR_E1MSK1; /*!< (@ 0x0000010C) Peripheral E1 Error Event Mask Register 1 */ + + struct + { + __IOM uint32_t E1_MK0 : 1; /*!< [0..0] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK1 : 1; /*!< [1..1] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK2 : 1; /*!< [2..2] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK3 : 1; /*!< [3..3] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK4 : 1; /*!< [4..4] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK5 : 1; /*!< [5..5] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK6 : 1; /*!< [6..6] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK7 : 1; /*!< [7..7] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK8 : 1; /*!< [8..8] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK9 : 1; /*!< [9..9] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + uint32_t : 3; + __IOM uint32_t E1_MK13 : 1; /*!< [13..13] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + uint32_t : 1; + __IOM uint32_t E1_MK15 : 1; /*!< [15..15] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK16 : 1; /*!< [16..16] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK17 : 1; /*!< [17..17] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK18 : 1; /*!< [18..18] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK19 : 1; /*!< [19..19] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK20 : 1; /*!< [20..20] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK21 : 1; /*!< [21..21] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK22 : 1; /*!< [22..22] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK23 : 1; /*!< [23..23] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK24 : 1; /*!< [24..24] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + uint32_t : 2; + __IOM uint32_t E1_MK27 : 1; /*!< [27..27] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + __IOM uint32_t E1_MK28 : 1; /*!< [28..28] Mask captured error status as an PERI_ERR1 event for + * PERIERR_STAT1 */ + uint32_t : 3; + } PERIERR_E1MSK1_b; + }; +} R_ICU_Type; /*!< Size = 272 (0x110) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_S ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Register Write Protection for Safety Area (R_SYSC_S) + */ + +typedef struct /*!< (@ 0x81280000) R_SYSC_S Structure */ +{ + __IM uint32_t RESERVED; + + union + { + __IOM uint32_t SCKCR2; /*!< (@ 0x00000004) System Clock Control Register 2 */ + + struct + { + __IOM uint32_t FSELCPU0 : 1; /*!< [0..0] Set the frequency of the clock provided to Coretex-R52 + * CPU0 in combination with bit 5 (DIVSELSUB). The combination + * is shown below. */ + uint32_t : 4; + __IOM uint32_t DIVSELSUB : 1; /*!< [5..5] Select the base clock frequency for peripheral module. */ + uint32_t : 18; + __IOM uint32_t SPI3ASYNCSEL : 1; /*!< [24..24] Select clock frequency when asynchronous serial clock + * is selected in SPI3 */ + __IOM uint32_t SCI5ASYNCSEL : 1; /*!< [25..25] Select clock frequency when asynchronous serial clock + * is selected in SCI5 */ + uint32_t : 6; + } SCKCR2_b; + }; + __IM uint32_t RESERVED1[6]; + + union + { + __IM uint32_t PLL0MON; /*!< (@ 0x00000020) PLL0 Monitor Register */ + + struct + { + __IM uint32_t PLL0MON : 1; /*!< [0..0] PLL0 Lock State Monitor */ + uint32_t : 31; + } PLL0MON_b; + }; + __IM uint32_t RESERVED2[7]; + + union + { + __IM uint32_t PLL1MON; /*!< (@ 0x00000040) PLL1 Monitor Register */ + + struct + { + __IM uint32_t PLL1MON : 1; /*!< [0..0] PLL1 Lock State Monitor */ + uint32_t : 31; + } PLL1MON_b; + }; + __IM uint32_t RESERVED3[3]; + + union + { + __IOM uint32_t PLL1EN; /*!< (@ 0x00000050) PLL1 Enable Register */ + + struct + { + __IOM uint32_t PLL1EN : 1; /*!< [0..0] PLL1 Enable */ + uint32_t : 31; + } PLL1EN_b; + }; + __IM uint32_t RESERVED4[7]; + + union + { + __IOM uint32_t LOCOCR; /*!< (@ 0x00000070) Low-Speed On-Chip Oscillator Control Register */ + + struct + { + __IOM uint32_t LCSTP : 1; /*!< [0..0] LOCO Stop */ + uint32_t : 31; + } LOCOCR_b; + }; + __IM uint32_t RESERVED5[3]; + + union + { + __IOM uint32_t HIZCTRLEN; /*!< (@ 0x00000080) High-Impedance Control Enable Register */ + + struct + { + __IOM uint32_t CLMA3MASK : 1; /*!< [0..0] CLMA3 error mask to POE3 and POEG */ + __IOM uint32_t CLMA0MASK : 1; /*!< [1..1] CLMA0 error mask to POE3 and POEG */ + __IOM uint32_t CLMA1MASK : 1; /*!< [2..2] CLMA1 error mask to POE3 and POEG */ + uint32_t : 29; + } HIZCTRLEN_b; + }; + __IM uint32_t RESERVED6[99]; + + union + { + __OM uint32_t SWRSYS; /*!< (@ 0x00000210) System Software Reset Register */ + + struct + { + __OM uint32_t SWR : 32; /*!< [31..0] System Software Reset */ + } SWRSYS_b; + }; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint32_t SWRCPU0; /*!< (@ 0x00000220) CPU0 Software Reset Register */ + + struct + { + __IOM uint32_t SWR : 32; /*!< [31..0] CPU0 Software Reset */ + } SWRCPU0_b; + }; + __IM uint32_t RESERVED8[15]; + + union + { + __IOM uint32_t MRCTLI; /*!< (@ 0x00000260) Module Reset Control Register I */ + + struct + { + __IOM uint32_t MRCTLI00 : 1; /*!< [0..0] PHOSTIF Reset Control */ + __IOM uint32_t MRCTLI01 : 1; /*!< [1..1] SHOSTIF (Master bus clock domain) Reset Control */ + __IOM uint32_t MRCTLI02 : 1; /*!< [2..2] SHOSTIF (Slave bus clock domain) Reset Control */ + __IOM uint32_t MRCTLI03 : 1; /*!< [3..3] SHOSTIF (IP clock domain) Reset Control */ + uint32_t : 28; + } MRCTLI_b; + }; + __IM uint32_t RESERVED9[44]; + + union + { + __IOM uint32_t MSTPCRF; /*!< (@ 0x00000314) Module Stop Control Register F */ + + struct + { + __IOM uint32_t MSTPCRF00 : 1; /*!< [0..0] Trace Clock for Debugging Interface Module Stop */ + uint32_t : 31; + } MSTPCRF_b; + }; + + union + { + __IOM uint32_t MSTPCRG; /*!< (@ 0x00000318) Module Stop Control Register G */ + + struct + { + __IOM uint32_t MSTPCRG00 : 1; /*!< [0..0] SCI Unit 5 Module Stop */ + __IOM uint32_t MSTPCRG01 : 1; /*!< [1..1] IIC Unit 2 Module Stop */ + __IOM uint32_t MSTPCRG02 : 1; /*!< [2..2] SPI Unit 3 Module Stop */ + __IOM uint32_t MSTPCRG03 : 1; /*!< [3..3] GPT Unit 2 Module Stop */ + __IOM uint32_t MSTPCRG04 : 1; /*!< [4..4] CRC Unit 1 Module Stop */ + __IOM uint32_t MSTPCRG05 : 1; /*!< [5..5] RTC Module Stop */ + uint32_t : 2; + __IOM uint32_t MSTPCRG08 : 1; /*!< [8..8] CLMA3 Module Stop */ + __IOM uint32_t MSTPCRG09 : 1; /*!< [9..9] CLMA0 Module Stop */ + __IOM uint32_t MSTPCRG10 : 1; /*!< [10..10] CLMA1 Module Stop */ + __IOM uint32_t MSTPCRG11 : 1; /*!< [11..11] CLMA2 Module Stop */ + uint32_t : 20; + } MSTPCRG_b; + }; + __IM uint32_t RESERVED10; + + union + { + __IOM uint32_t MSTPCRI; /*!< (@ 0x00000320) Module Stop Control Register I */ + + struct + { + __IOM uint32_t MSTPCRI00 : 1; /*!< [0..0] PHOSTIF Module Stop */ + __IOM uint32_t MSTPCRI01 : 1; /*!< [1..1] SHOSTIF Module Stop */ + uint32_t : 30; + } MSTPCRI_b; + }; +} R_SYSC_S_Type; /*!< Size = 804 (0x324) */ + +/* =========================================================================================================================== */ +/* ================ R_CLMA0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Clock Monitor Circuit 0 (R_CLMA0) + */ + +typedef struct /*!< (@ 0x81280800) R_CLMA0 Structure */ +{ + union + { + __IOM uint8_t CTL0; /*!< (@ 0x00000000) CLMA Control Register 0 */ + + struct + { + __IOM uint8_t CLME : 1; /*!< [0..0] Clock Monitor m Enable (m = 0 to 3) */ + uint8_t : 7; + } CTL0_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t CMPL; /*!< (@ 0x00000008) CLMA Compare Register L */ + + struct + { + __IOM uint16_t CMPL : 12; /*!< [11..0] Clock Monitor m Compare L (m = 0 to 3) */ + uint16_t : 4; + } CMPL_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t CMPH; /*!< (@ 0x0000000C) CLMA Compare Register H */ + + struct + { + __IOM uint16_t CMPH : 12; /*!< [11..0] Clock Monitor m Compare H (m = 0 to 3) */ + uint16_t : 4; + } CMPH_b; + }; + __IM uint16_t RESERVED3; + __OM uint8_t PCMD; /*!< (@ 0x00000010) CLMA Command Register */ + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; + + union + { + __IM uint8_t PROTSR; /*!< (@ 0x00000014) CLMA Protection Status Register */ + + struct + { + __IM uint8_t PRERR : 1; /*!< [0..0] CLMAm Error (m = 0 to 3) */ + uint8_t : 7; + } PROTSR_b; + }; + __IM uint8_t RESERVED6; + __IM uint16_t RESERVED7; +} R_CLMA0_Type; /*!< Size = 24 (0x18) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Master MPU 0 (R_MPU0) + */ + +typedef struct /*!< (@ 0x81281100) R_MPU0 Structure */ +{ + __IOM R_MPU0_RGN_Type RGN[8]; /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register + * [0..7] */ + + union + { + __IOM uint32_t ERRINF_R; /*!< (@ 0x00000080) Master MPU Error Information Register for AXI + * type */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Validity of access error information */ + __IM uint32_t RW : 1; /*!< [1..1] Access error type */ + __IM uint32_t ERRADDR : 30; /*!< [31..2] Access error address */ + } ERRINF_R_b; + }; + + union + { + __IOM uint32_t ERRINF_W; /*!< (@ 0x00000084) Master MPU Error Information Register for AXI + * type */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Validity of access error information */ + __IM uint32_t RW : 1; /*!< [1..1] Access error type */ + __IM uint32_t ERRADDR : 30; /*!< [31..2] Access error address */ + } ERRINF_W_b; + }; +} R_MPU0_Type; /*!< Size = 136 (0x88) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Master MPU 3 (R_MPU3) + */ + +typedef struct /*!< (@ 0x81281400) R_MPU3 Structure */ +{ + __IOM R_MPU0_RGN_Type RGN[8]; /*!< (@ 0x00000000) Master MPU Safety Region Start Address Register + * [0..7] */ + + union + { + __IOM uint32_t ERRINF; /*!< (@ 0x00000080) Master MPU Error Information Register for AHB + * type */ + + struct + { + __IOM uint32_t VALID : 1; /*!< [0..0] Validity of Access Error Information */ + __IM uint32_t RW : 1; /*!< [1..1] Access error type */ + __IM uint32_t ERRADDR : 30; /*!< [31..2] Access Error Address */ + } ERRINF_b; + }; +} R_MPU3_Type; /*!< Size = 132 (0x84) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM_CTL ================ */ +/* =========================================================================================================================== */ + +/** + * @brief System SRAM Control (R_SYSRAM_CTL) + */ + +typedef struct /*!< (@ 0x81281800) R_SYSRAM_CTL Structure */ +{ + union + { + __IOM uint32_t SYSRAM_CTRL0; /*!< (@ 0x00000000) System SRAM Control Register 0 */ + + struct + { + __IOM uint32_t VECEN : 1; /*!< [0..0] Enables or disables error correction with ECC */ + uint32_t : 15; + __IOM uint32_t VRWEN : 4; /*!< [19..16] Enables write for each page of RAM */ + __IOM uint32_t VCEN : 1; /*!< [20..20] Enables access to RAM */ + __IOM uint32_t VLWEN : 1; /*!< [21..21] Enables write for RAM */ + uint32_t : 2; + __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors */ + uint32_t : 7; + } SYSRAM_CTRL0_b; + }; + __IM uint32_t RESERVED[3]; + + union + { + __IOM uint32_t SYSRAM_CTRL1; /*!< (@ 0x00000010) System SRAM Control Register 1 */ + + struct + { + __IOM uint32_t VECEN : 1; /*!< [0..0] Enables or disables error correction with ECC */ + uint32_t : 15; + __IOM uint32_t VRWEN : 4; /*!< [19..16] Enables write for each page of RAM */ + __IOM uint32_t VCEN : 1; /*!< [20..20] Enables access to RAM */ + __IOM uint32_t VLWEN : 1; /*!< [21..21] Enables write for RAM */ + uint32_t : 2; + __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors */ + uint32_t : 7; + } SYSRAM_CTRL1_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t SYSRAM_CTRL2; /*!< (@ 0x00000020) System SRAM Control Register 2 */ + + struct + { + __IOM uint32_t VECEN : 1; /*!< [0..0] Enables or disables error correction with ECC */ + uint32_t : 15; + __IOM uint32_t VRWEN : 4; /*!< [19..16] Enables write for each page of RAM */ + __IOM uint32_t VCEN : 1; /*!< [20..20] Enables access to RAM */ + __IOM uint32_t VLWEN : 1; /*!< [21..21] Enables write for RAM */ + uint32_t : 2; + __IOM uint32_t MKICCAXIERR : 1; /*!< [24..24] Controls AXI-SLVERR issuance for ECC 2-bit errors */ + uint32_t : 7; + } SYSRAM_CTRL2_b; + }; +} R_SYSRAM_CTL_Type; /*!< Size = 36 (0x24) */ + +/* =========================================================================================================================== */ +/* ================ R_SHOSTIF_CFG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Serial Host Interface Configuration (R_SHOSTIF_CFG) + */ + +typedef struct /*!< (@ 0x81281920) R_SHOSTIF_CFG Structure */ +{ + union + { + __IOM uint32_t SHCFG; /*!< (@ 0x00000000) SHOSTIF Configuration Register */ + + struct + { + __IOM uint32_t SPIMODE : 2; /*!< [1..0] SPI Frame Format Select */ + __IOM uint32_t BYTESWAP : 1; /*!< [2..2] Byte Swap Mode */ + __IOM uint32_t ADDRESSING : 1; /*!< [3..3] Addressing Mode */ + __IM uint32_t SLEEP : 1; /*!< [4..4] SHOSTIF Enable Flag Monitor */ + uint32_t : 11; + __IOM uint32_t INTMASKI : 6; /*!< [21..16] Interrupt Mask Enable for Internal Interrupt (SHOST_INT) */ + uint32_t : 2; + __IOM uint32_t INTMASKE : 6; /*!< [29..24] Interrupt Mask Enable for External Interrupt (HSPI_INT# + * signal) */ + uint32_t : 2; + } SHCFG_b; + }; +} R_SHOSTIF_CFG_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_PHOSTIF_CFG ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Parallel Host Interface Configuration (R_PHOSTIF_CFG) + */ + +typedef struct /*!< (@ 0x81281930) R_PHOSTIF_CFG Structure */ +{ + union + { + __IOM uint32_t PHCFG; /*!< (@ 0x00000000) PHOSTIF Configureation Register */ + + struct + { + __IOM uint32_t MEMIFSEL : 1; /*!< [0..0] MEMIFSEL */ + uint32_t : 3; + __IOM uint32_t BUSSSEL : 1; /*!< [4..4] BUSSSEL */ + uint32_t : 3; + __IOM uint32_t HIFSYNC : 1; /*!< [8..8] HIFSYNC */ + uint32_t : 3; + __IOM uint32_t MEMCSEL : 1; /*!< [12..12] MEMCSEL */ + uint32_t : 3; + __IOM uint32_t HWRZSEL : 1; /*!< [16..16] HWRZSEL */ + uint32_t : 3; + __IOM uint32_t ADMUXMODE : 1; /*!< [20..20] ADMUXMODE */ + uint32_t : 11; + } PHCFG_b; + }; + + union + { + __IOM uint32_t PHACC; /*!< (@ 0x00000004) PHOSTIF Register Access Control Register */ + + struct + { + __IOM uint32_t HIFRDYSEL : 1; /*!< [0..0] HIFRDYSEL */ + uint32_t : 7; + __IOM uint32_t HIFBCCSEL : 1; /*!< [8..8] HIFBCCSEL */ + __IOM uint32_t HIFBTCSEL : 1; /*!< [9..9] HIFBTCSEL */ + __IOM uint32_t HIFPRCSEL : 1; /*!< [10..10] HIFPRCSEL */ + __IOM uint32_t HIFIRCSEL : 1; /*!< [11..11] HIFIRCSEL */ + __IOM uint32_t HIFXALSEL : 1; /*!< [12..12] HIFXALSEL */ + __IOM uint32_t HIFXAHSEL : 1; /*!< [13..13] HIFXAHSEL */ + __IOM uint32_t HIFEXT0SEL : 1; /*!< [14..14] HIFEXT0SEL */ + __IOM uint32_t HIFEXT1SEL : 1; /*!< [15..15] HIFEXT1SEL */ + __IOM uint32_t CSSWAP : 1; /*!< [16..16] CSSWAP */ + __IOM uint32_t BSCADMUX : 1; /*!< [17..17] BSCADMUX */ + uint32_t : 14; + } PHACC_b; + }; +} R_PHOSTIF_CFG_Type; /*!< Size = 8 (0x8) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_S ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Register Write Protection for Safety Area (R_RWP_S) + */ + +typedef struct /*!< (@ 0x81281A00) R_RWP_S Structure */ +{ + union + { + __IOM uint32_t PRCRS; /*!< (@ 0x00000000) Safety Area Protect Register */ + + struct + { + __IOM uint32_t PRC0 : 1; /*!< [0..0] Protect 0 */ + __IOM uint32_t PRC1 : 1; /*!< [1..1] Protect 1 */ + __IOM uint32_t PRC2 : 1; /*!< [2..2] Protect 2 */ + __IOM uint32_t PRC3 : 1; /*!< [3..3] Protect 3 */ + uint32_t : 4; + __OM uint32_t PRKEY : 8; /*!< [15..8] PRC Key Code */ + uint32_t : 16; + } PRCRS_b; + }; +} R_RWP_S_Type; /*!< Size = 4 (0x4) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit (R_MTU) + */ + +typedef struct /*!< (@ 0x90001000) R_MTU Structure */ +{ + __IM uint16_t RESERVED[261]; + + union + { + __IOM uint8_t TOERA; /*!< (@ 0x0000020A) Timer Output Master Enable Register A */ + + struct + { + __IOM uint8_t OE3B : 1; /*!< [0..0] Master Enable MTIOC3B */ + __IOM uint8_t OE4A : 1; /*!< [1..1] Master Enable MTIOC4A */ + __IOM uint8_t OE4B : 1; /*!< [2..2] Master Enable MTIOC4B */ + __IOM uint8_t OE3D : 1; /*!< [3..3] Master Enable MTIOC3D */ + __IOM uint8_t OE4C : 1; /*!< [4..4] Master Enable MTIOC4C */ + __IOM uint8_t OE4D : 1; /*!< [5..5] Master Enable MTIOC4D */ + uint8_t : 2; + } TOERA_b; + }; + __IM uint8_t RESERVED1[2]; + + union + { + __IOM uint8_t TGCRA; /*!< (@ 0x0000020D) Timer Gate Control Register A */ + + struct + { + __IOM uint8_t UF : 1; /*!< [0..0] Output Phase Switch */ + __IOM uint8_t VF : 1; /*!< [1..1] Output Phase Switch */ + __IOM uint8_t WF : 1; /*!< [2..2] Output Phase Switch */ + __IOM uint8_t FB : 1; /*!< [3..3] External Feedback Signal Enable */ + __IOM uint8_t P : 1; /*!< [4..4] Positive-Phase Output (P) Control */ + __IOM uint8_t N : 1; /*!< [5..5] Negative-Phase Output (N) Control */ + __IOM uint8_t BDC : 1; /*!< [6..6] Brushless DC Motor */ + uint8_t : 1; + } TGCRA_b; + }; + + union + { + __IOM uint8_t TOCR1A; /*!< (@ 0x0000020E) Timer Output Control Register 1A */ + + struct + { + __IOM uint8_t OLSP : 1; /*!< [0..0] Output Level Select P */ + __IOM uint8_t OLSN : 1; /*!< [1..1] Output Level Select N */ + __IOM uint8_t TOCS : 1; /*!< [2..2] TOC Select */ + __IOM uint8_t TOCL : 1; /*!< [3..3] TOC Register Write Protection */ + uint8_t : 2; + __IOM uint8_t PSYE : 1; /*!< [6..6] PWM Synchronous Output Enable */ + uint8_t : 1; + } TOCR1A_b; + }; + + union + { + __IOM uint8_t TOCR2A; /*!< (@ 0x0000020F) Timer Output Control Register 2A */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + __IOM uint8_t BF : 2; /*!< [7..6] TOLBR Buffer Transfer Timing Select */ + } TOCR2A_b; + }; + __IM uint16_t RESERVED2[2]; + __IOM uint16_t TCDRA; /*!< (@ 0x00000214) Timer Cycle Data Register A */ + __IOM uint16_t TDDRA; /*!< (@ 0x00000216) Timer Dead Time Data Register A */ + __IM uint16_t RESERVED3[4]; + __IM uint16_t TCNTSA; /*!< (@ 0x00000220) Timer Subcounter A */ + __IOM uint16_t TCBRA; /*!< (@ 0x00000222) Timer Cycle Buffer Register A */ + __IM uint16_t RESERVED4[6]; + + union + { + __IOM uint8_t TITCR1A; /*!< (@ 0x00000230) Timer Interrupt Skipping Set Register 1A */ + + struct + { + __IOM uint8_t T4VCOR : 3; /*!< [2..0] TCIV4 Interrupt Skipping Count Setting */ + __IOM uint8_t T4VEN : 1; /*!< [3..3] TCIV4 Interrupt Skipping Enable */ + __IOM uint8_t T3ACOR : 3; /*!< [6..4] TGIA3 Interrupt Skipping Count Setting */ + __IOM uint8_t T3AEN : 1; /*!< [7..7] TGIA3 Interrupt Skipping Enable */ + } TITCR1A_b; + }; + + union + { + __IM uint8_t TITCNT1A; /*!< (@ 0x00000231) Timer Interrupt Skipping Counter 1A */ + + struct + { + __IM uint8_t T4VCNT : 3; /*!< [2..0] TCIV4 Interrupt Counter */ + uint8_t : 1; + __IM uint8_t T3ACNT : 3; /*!< [6..4] TGIA3 Interrupt Counter */ + uint8_t : 1; + } TITCNT1A_b; + }; + + union + { + __IOM uint8_t TBTERA; /*!< (@ 0x00000232) Timer Buffer Transfer Set Register A */ + + struct + { + __IOM uint8_t BTE : 2; /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting */ + uint8_t : 6; + } TBTERA_b; + }; + __IM uint8_t RESERVED5; + + union + { + __IOM uint8_t TDERA; /*!< (@ 0x00000234) Timer Dead Time Enable Register A */ + + struct + { + __IOM uint8_t TDER : 1; /*!< [0..0] Dead Time Enable */ + uint8_t : 7; + } TDERA_b; + }; + __IM uint8_t RESERVED6; + + union + { + __IOM uint8_t TOLBRA; /*!< (@ 0x00000236) Timer Output Level Buffer Register A */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + uint8_t : 2; + } TOLBRA_b; + }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; + + union + { + __IOM uint8_t TITMRA; /*!< (@ 0x0000023A) Timer Interrupt Skipping Mode Register A */ + + struct + { + __IOM uint8_t TITM : 1; /*!< [0..0] Interrupt Skipping Function Select */ + uint8_t : 7; + } TITMRA_b; + }; + + union + { + __IOM uint8_t TITCR2A; /*!< (@ 0x0000023B) Timer Interrupt Skipping Set Register 2A */ + + struct + { + __IOM uint8_t TRG4COR : 3; /*!< [2..0] TRG4AN/TRG4BN Interrupt Skipping Count Setting */ + uint8_t : 5; + } TITCR2A_b; + }; + + union + { + __IM uint8_t TITCNT2A; /*!< (@ 0x0000023C) Timer Interrupt Skipping Counter 2A */ + + struct + { + __IM uint8_t TRG4CNT : 3; /*!< [2..0] TRG4AN/TRG4BN Interrupt Counter */ + uint8_t : 5; + } TITCNT2A_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10[17]; + + union + { + __IOM uint8_t TWCRA; /*!< (@ 0x00000260) Timer Waveform Control Register A */ + + struct + { + __IOM uint8_t WRE : 1; /*!< [0..0] Waveform Retain Enable */ + __IOM uint8_t SCC : 1; /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB) */ + uint8_t : 5; + __IOM uint8_t CCE : 1; /*!< [7..7] Compare Match Clear Enable */ + } TWCRA_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12[7]; + + union + { + __IOM uint8_t TMDR2A; /*!< (@ 0x00000270) Timer Mode Register 2A */ + + struct + { + __IOM uint8_t DRS : 1; /*!< [0..0] Double Buffer Select */ + uint8_t : 7; + } TMDR2A_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14[7]; + + union + { + __IOM uint8_t TSTRA; /*!< (@ 0x00000280) Timer Start Register A */ + + struct + { + __IOM uint8_t CST0 : 1; /*!< [0..0] Counter Start 0 */ + __IOM uint8_t CST1 : 1; /*!< [1..1] Counter Start 1 */ + __IOM uint8_t CST2 : 1; /*!< [2..2] Counter Start 2 */ + __IOM uint8_t CST8 : 1; /*!< [3..3] Counter Start 8 */ + uint8_t : 2; + __IOM uint8_t CST3 : 1; /*!< [6..6] Counter Start 3 */ + __IOM uint8_t CST4 : 1; /*!< [7..7] Counter Start 4 */ + } TSTRA_b; + }; + + union + { + __IOM uint8_t TSYRA; /*!< (@ 0x00000281) Timer Synchronous Register A */ + + struct + { + __IOM uint8_t SYNC0 : 1; /*!< [0..0] Timer Synchronous Operation 0 */ + __IOM uint8_t SYNC1 : 1; /*!< [1..1] Timer Synchronous Operation 1 */ + __IOM uint8_t SYNC2 : 1; /*!< [2..2] Timer Synchronous Operation 2 */ + uint8_t : 3; + __IOM uint8_t SYNC3 : 1; /*!< [6..6] Timer Synchronous Operation 3 */ + __IOM uint8_t SYNC4 : 1; /*!< [7..7] Timer Synchronous Operation 4 */ + } TSYRA_b; + }; + + union + { + __IOM uint8_t TCSYSTR; /*!< (@ 0x00000282) Timer Counter Synchronous Start Register */ + + struct + { + __IOM uint8_t SCH7 : 1; /*!< [0..0] Synchronous Start 7 */ + __IOM uint8_t SCH6 : 1; /*!< [1..1] Synchronous Start 6 */ + uint8_t : 1; + __IOM uint8_t SCH4 : 1; /*!< [3..3] Synchronous Start 4 */ + __IOM uint8_t SCH3 : 1; /*!< [4..4] Synchronous Start 3 */ + __IOM uint8_t SCH2 : 1; /*!< [5..5] Synchronous Start 2 */ + __IOM uint8_t SCH1 : 1; /*!< [6..6] Synchronous Start 1 */ + __IOM uint8_t SCH0 : 1; /*!< [7..7] Synchronous Start 0 */ + } TCSYSTR_b; + }; + __IM uint8_t RESERVED15; + + union + { + __IOM uint8_t TRWERA; /*!< (@ 0x00000284) Timer Read/Write Enable Register A */ + + struct + { + __IOM uint8_t RWE : 1; /*!< [0..0] Read/Write Enable */ + uint8_t : 7; + } TRWERA_b; + }; + __IM uint8_t RESERVED16; + __IM uint16_t RESERVED17[962]; + + union + { + __IOM uint8_t TOERB; /*!< (@ 0x00000A0A) Timer Output Master Enable Register B */ + + struct + { + __IOM uint8_t OE6B : 1; /*!< [0..0] Master Enable MTIOC6B */ + __IOM uint8_t OE7A : 1; /*!< [1..1] Master Enable MTIOC7A */ + __IOM uint8_t OE7B : 1; /*!< [2..2] Master Enable MTIOC7B */ + __IOM uint8_t OE6D : 1; /*!< [3..3] Master Enable MTIOC6D */ + __IOM uint8_t OE7C : 1; /*!< [4..4] Master Enable MTIOC7C */ + __IOM uint8_t OE7D : 1; /*!< [5..5] Master Enable MTIOC7D */ + uint8_t : 2; + } TOERB_b; + }; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; + + union + { + __IOM uint8_t TOCR1B; /*!< (@ 0x00000A0E) Timer Output Control Register 1B */ + + struct + { + __IOM uint8_t OLSP : 1; /*!< [0..0] Output Level Select P */ + __IOM uint8_t OLSN : 1; /*!< [1..1] Output Level Select N */ + __IOM uint8_t TOCS : 1; /*!< [2..2] TOC Select */ + __IOM uint8_t TOCL : 1; /*!< [3..3] TOC Register Write Protection */ + uint8_t : 2; + __IOM uint8_t PSYE : 1; /*!< [6..6] PWM Synchronous Output Enable */ + uint8_t : 1; + } TOCR1B_b; + }; + + union + { + __IOM uint8_t TOCR2B; /*!< (@ 0x00000A0F) Timer Output Control Register 2B */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + __IOM uint8_t BF : 2; /*!< [7..6] TOLBR Buffer Transfer Timing Select */ + } TOCR2B_b; + }; + __IM uint16_t RESERVED20[2]; + __IOM uint16_t TCDRB; /*!< (@ 0x00000A14) Timer Cycle Data Register B */ + __IOM uint16_t TDDRB; /*!< (@ 0x00000A16) Timer Dead Time Data Register B */ + __IM uint16_t RESERVED21[4]; + __IM uint16_t TCNTSB; /*!< (@ 0x00000A20) Timer Subcounter B */ + __IOM uint16_t TCBRB; /*!< (@ 0x00000A22) Timer Cycle Buffer Register B */ + __IM uint16_t RESERVED22[6]; + + union + { + __IOM uint8_t TITCR1B; /*!< (@ 0x00000A30) Timer Interrupt Skipping Set Register 1B */ + + struct + { + __IOM uint8_t T7VCOR : 3; /*!< [2..0] TCIV7 Interrupt Skipping Count Setting */ + __IOM uint8_t T7VEN : 1; /*!< [3..3] TCIV7 Interrupt Skipping Enable */ + __IOM uint8_t T6ACOR : 3; /*!< [6..4] TGIA6 Interrupt Skipping Count Setting */ + __IOM uint8_t T6AEN : 1; /*!< [7..7] TGIA6 Interrupt Skipping Enable */ + } TITCR1B_b; + }; + + union + { + __IM uint8_t TITCNT1B; /*!< (@ 0x00000A31) Timer Interrupt Skipping Counter 1B */ + + struct + { + __IM uint8_t T7VCNT : 3; /*!< [2..0] TCIV7 Interrupt Counter */ + uint8_t : 1; + __IM uint8_t T6ACNT : 3; /*!< [6..4] TGIA6 Interrupt Counter */ + uint8_t : 1; + } TITCNT1B_b; + }; + + union + { + __IOM uint8_t TBTERB; /*!< (@ 0x00000A32) Timer Buffer Transfer Set Register B */ + + struct + { + __IOM uint8_t BTE : 2; /*!< [1..0] Buffer Transfer Disable and Interrupt Skipping Link Setting */ + uint8_t : 6; + } TBTERB_b; + }; + __IM uint8_t RESERVED23; + + union + { + __IOM uint8_t TDERB; /*!< (@ 0x00000A34) Timer Dead Time Enable Register B */ + + struct + { + __IOM uint8_t TDER : 1; /*!< [0..0] Dead Time Enable */ + uint8_t : 7; + } TDERB_b; + }; + __IM uint8_t RESERVED24; + + union + { + __IOM uint8_t TOLBRB; /*!< (@ 0x00000A36) Timer Output Level Buffer Register B */ + + struct + { + __IOM uint8_t OLS1P : 1; /*!< [0..0] Output Level Select 1P */ + __IOM uint8_t OLS1N : 1; /*!< [1..1] Output Level Select 1N */ + __IOM uint8_t OLS2P : 1; /*!< [2..2] Output Level Select 2P */ + __IOM uint8_t OLS2N : 1; /*!< [3..3] Output Level Select 2N */ + __IOM uint8_t OLS3P : 1; /*!< [4..4] Output Level Select 3P */ + __IOM uint8_t OLS3N : 1; /*!< [5..5] Output Level Select 3N */ + uint8_t : 2; + } TOLBRB_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + + union + { + __IOM uint8_t TITMRB; /*!< (@ 0x00000A3A) Timer Interrupt Skipping Mode Register B */ + + struct + { + __IOM uint8_t TITM : 1; /*!< [0..0] Interrupt Skipping Function Select */ + uint8_t : 7; + } TITMRB_b; + }; + + union + { + __IOM uint8_t TITCR2B; /*!< (@ 0x00000A3B) Timer Interrupt Skipping Set Register 2B */ + + struct + { + __IOM uint8_t TRG7COR : 3; /*!< [2..0] TRG7AN/TRG7BN Interrupt Skipping Count Setting */ + uint8_t : 5; + } TITCR2B_b; + }; + + union + { + __IM uint8_t TITCNT2B; /*!< (@ 0x00000A3C) Timer Interrupt Skipping Counter 2B */ + + struct + { + __IM uint8_t TRG7CNT : 3; /*!< [2..0] TRG7AN/TRG7BN Interrupt Counter */ + uint8_t : 5; + } TITCNT2B_b; + }; + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28[17]; + + union + { + __IOM uint8_t TWCRB; /*!< (@ 0x00000A60) Timer Waveform Control Register B */ + + struct + { + __IOM uint8_t WRE : 1; /*!< [0..0] Waveform Retain Enable */ + __IOM uint8_t SCC : 1; /*!< [1..1] Synchronous Clearing Control (Only valid in TWCRB) */ + uint8_t : 5; + __IOM uint8_t CCE : 1; /*!< [7..7] Compare Match Clear Enable */ + } TWCRB_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30[7]; + + union + { + __IOM uint8_t TMDR2B; /*!< (@ 0x00000A70) Timer Mode Register 2B */ + + struct + { + __IOM uint8_t DRS : 1; /*!< [0..0] Double Buffer Select */ + uint8_t : 7; + } TMDR2B_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32[7]; + + union + { + __IOM uint8_t TSTRB; /*!< (@ 0x00000A80) Timer Start Register B */ + + struct + { + uint8_t : 6; + __IOM uint8_t CST6 : 1; /*!< [6..6] Counter Start 6 */ + __IOM uint8_t CST7 : 1; /*!< [7..7] Counter Start 7 */ + } TSTRB_b; + }; + + union + { + __IOM uint8_t TSYRB; /*!< (@ 0x00000A81) Timer Synchronous Register B */ + + struct + { + uint8_t : 6; + __IOM uint8_t SYNC6 : 1; /*!< [6..6] Timer Synchronous Operation 6 */ + __IOM uint8_t SYNC7 : 1; /*!< [7..7] Timer Synchronous Operation 7 */ + } TSYRB_b; + }; + __IM uint16_t RESERVED33; + + union + { + __IOM uint8_t TRWERB; /*!< (@ 0x00000A84) Timer Read/Write Enable Register B */ + + struct + { + __IOM uint8_t RWE : 1; /*!< [0..0] Read/Write Enable */ + uint8_t : 7; + } TRWERB_b; + }; + __IM uint8_t RESERVED34; + __IM uint16_t RESERVED35; +} R_MTU_Type; /*!< Size = 2696 (0xa88) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 3 (R_MTU3) + */ + +typedef struct /*!< (@ 0x90001100) R_MTU3 Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000100) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000102) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000104) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000105) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000108) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[3]; + __IOM uint16_t TCNT; /*!< (@ 0x00000110) Timer Counter */ + __IM uint16_t RESERVED6[3]; + __IOM uint16_t TGRA; /*!< (@ 0x00000118) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000011A) Timer General Register B */ + __IM uint16_t RESERVED7[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000124) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x00000126) Timer General Register D */ + __IM uint16_t RESERVED8[2]; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000012C) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10[5]; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12[9]; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000014C) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14[18]; + __IOM uint16_t TGRE; /*!< (@ 0x00000172) Timer General Register E */ +} R_MTU3_Type; /*!< Size = 372 (0x174) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU4 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 4 (R_MTU4) + */ + +typedef struct /*!< (@ 0x90001200) R_MTU4 Structure */ +{ + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000001) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000003) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000006) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000007) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000009) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE2 : 1; /*!< [6..6] A/D Converter Start Request Enable 2 */ + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint16_t RESERVED4[4]; + __IOM uint16_t TCNT; /*!< (@ 0x00000012) Timer Counter */ + __IM uint16_t RESERVED5[4]; + __IOM uint16_t TGRA; /*!< (@ 0x0000001C) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000001E) Timer General Register B */ + __IM uint16_t RESERVED6[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000028) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x0000002A) Timer General Register D */ + __IM uint8_t RESERVED7; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000002D) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint16_t RESERVED8[5]; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint16_t RESERVED10[3]; + + union + { + __IOM uint16_t TADCR; /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register */ + + struct + { + __IOM uint16_t ITB4VE : 1; /*!< [0..0] TCIV4 Interrupt Skipping Link Enable */ + __IOM uint16_t ITB3AE : 1; /*!< [1..1] TGIA3 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA4VE : 1; /*!< [2..2] TCIV4 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA3AE : 1; /*!< [3..3] TGIA3 Interrupt Skipping Link Enable */ + __IOM uint16_t DT4BE : 1; /*!< [4..4] Down-Count TRG4BN Enable */ + __IOM uint16_t UT4BE : 1; /*!< [5..5] Up-Count TRG4BN Enable */ + __IOM uint16_t DT4AE : 1; /*!< [6..6] Down-Count TRG4AN Enable */ + __IOM uint16_t UT4AE : 1; /*!< [7..7] Up-Count TRG4AN Enable */ + uint16_t : 6; + __IOM uint16_t BF : 2; /*!< [15..14] MTU4.TADCOBRA/TADCOBRB Transfer Timing Select */ + } TADCR_b; + }; + __IM uint16_t RESERVED11; + __IOM uint16_t TADCORA; /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register + * A */ + __IOM uint16_t TADCORB; /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register + * B */ + __IOM uint16_t TADCOBRA; /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer + * Register A */ + __IOM uint16_t TADCOBRB; /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer + * Register B */ + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000004D) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint16_t RESERVED13[19]; + __IOM uint16_t TGRE; /*!< (@ 0x00000074) Timer General Register E */ + __IOM uint16_t TGRF; /*!< (@ 0x00000076) Timer General Register F */ +} R_MTU4_Type; /*!< Size = 120 (0x78) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU_NF ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Noise Filter (R_MTU_NF) + */ + +typedef struct /*!< (@ 0x90001290) R_MTU_NF Structure */ +{ + union + { + __IOM uint8_t NFCR0; /*!< (@ 0x00000000) Noise Filter Control Register 0 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR0_b; + }; + + union + { + __IOM uint8_t NFCR1; /*!< (@ 0x00000001) Noise Filter Control Register 1 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + uint8_t : 2; + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR1_b; + }; + + union + { + __IOM uint8_t NFCR2; /*!< (@ 0x00000002) Noise Filter Control Register 2 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + uint8_t : 2; + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR2_b; + }; + + union + { + __IOM uint8_t NFCR3; /*!< (@ 0x00000003) Noise Filter Control Register 3 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR3_b; + }; + + union + { + __IOM uint8_t NFCR4; /*!< (@ 0x00000004) Noise Filter Control Register 4 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR4_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t NFCR8; /*!< (@ 0x00000008) Noise Filter Control Register 8 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR8_b; + }; + + union + { + __IOM uint8_t NFCRC; /*!< (@ 0x00000009) Noise Filter Control Register C */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCRC_b; + }; + __IM uint8_t RESERVED1[2041]; + + union + { + __IOM uint8_t NFCR6; /*!< (@ 0x00000803) Noise Filter Control Register 6 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR6_b; + }; + + union + { + __IOM uint8_t NFCR7; /*!< (@ 0x00000804) Noise Filter Control Register 7 */ + + struct + { + __IOM uint8_t NFAEN : 1; /*!< [0..0] Noise Filter A Enable */ + __IOM uint8_t NFBEN : 1; /*!< [1..1] Noise Filter B Enable */ + __IOM uint8_t NFCEN : 1; /*!< [2..2] Noise Filter C Enable */ + __IOM uint8_t NFDEN : 1; /*!< [3..3] Noise Filter D Enable */ + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR7_b; + }; + + union + { + __IOM uint8_t NFCR5; /*!< (@ 0x00000805) Noise Filter Control Register 5 */ + + struct + { + __IOM uint8_t NFUEN : 1; /*!< [0..0] Noise Filter U Enable */ + __IOM uint8_t NFVEN : 1; /*!< [1..1] Noise Filter V Enable */ + __IOM uint8_t NFWEN : 1; /*!< [2..2] Noise Filter W Enable */ + uint8_t : 1; + __IOM uint8_t NFCS : 2; /*!< [5..4] Noise Filter Clock Select */ + uint8_t : 2; + } NFCR5_b; + }; +} R_MTU_NF_Type; /*!< Size = 2054 (0x806) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 0 (R_MTU0) + */ + +typedef struct /*!< (@ 0x90001300) R_MTU0 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + __IOM uint8_t BFE : 1; /*!< [6..6] Buffer Operation E */ + uint8_t : 1; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000002) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000003) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint8_t RESERVED; + __IOM uint16_t TCNT; /*!< (@ 0x00000006) Timer Counter */ + __IOM uint16_t TGRA; /*!< (@ 0x00000008) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000000A) Timer General Register B */ + __IOM uint16_t TGRC; /*!< (@ 0x0000000C) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x0000000E) Timer General Register D */ + __IM uint16_t RESERVED1[8]; + __IOM uint16_t TGRE; /*!< (@ 0x00000020) Timer General Register E */ + __IOM uint16_t TGRF; /*!< (@ 0x00000022) Timer General Register F */ + + union + { + __IOM uint8_t TIER2; /*!< (@ 0x00000024) Timer Interrupt Enable Register 2 */ + + struct + { + __IOM uint8_t TGIEE : 1; /*!< [0..0] TGR Interrupt Enable E */ + __IOM uint8_t TGIEF : 1; /*!< [1..1] TGR Interrupt Enable F */ + uint8_t : 5; + __IOM uint8_t TTGE2 : 1; /*!< [7..7] A/D Converter Start Request Enable 2 */ + } TIER2_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000026) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + __IOM uint8_t TTSE : 1; /*!< [2..2] Timing Select E */ + uint8_t : 5; + } TBTM_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x00000028) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; +} R_MTU0_Type; /*!< Size = 44 (0x2c) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU1 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 1 (R_MTU1) + */ + +typedef struct /*!< (@ 0x90001380) R_MTU1 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + uint8_t : 4; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIOR; /*!< (@ 0x00000002) Timer I/O Control Register */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIOR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + uint8_t : 2; + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + __IOM uint8_t TCIEU : 1; /*!< [5..5] Underflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x00000005) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IOM uint16_t TCNT; /*!< (@ 0x00000006) Timer Counter */ + __IOM uint16_t TGRA; /*!< (@ 0x00000008) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000000A) Timer General Register B */ + __IM uint32_t RESERVED1; + + union + { + __IOM uint8_t TICCR; /*!< (@ 0x00000010) Timer Input Capture Control Register */ + + struct + { + __IOM uint8_t I1AE : 1; /*!< [0..0] Input Capture Enable */ + __IOM uint8_t I1BE : 1; /*!< [1..1] Input Capture Enable */ + __IOM uint8_t I2AE : 1; /*!< [2..2] Input Capture Enable */ + __IOM uint8_t I2BE : 1; /*!< [3..3] Input Capture Enable */ + uint8_t : 4; + } TICCR_b; + }; + + union + { + __IOM uint8_t TMDR3; /*!< (@ 0x00000011) Timer Mode Register 3 */ + + struct + { + __IOM uint8_t LWA : 1; /*!< [0..0] MTU1/MTU2 Combination Longword Access Control */ + __IOM uint8_t PHCKSEL : 1; /*!< [1..1] External Input Phase Clock Select */ + uint8_t : 6; + } TMDR3_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x00000014) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t PCB : 2; /*!< [4..3] Functional Expansion Control for Phase Counting Modes + * 2, 3, and 5 */ + uint8_t : 3; + } TCR2_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + __IOM uint32_t TCNTLW; /*!< (@ 0x00000020) Timer Longword Counter */ + __IOM uint32_t TGRALW; /*!< (@ 0x00000024) Timer Longword General Register A */ + __IOM uint32_t TGRBLW; /*!< (@ 0x00000028) Timer Longword General Register B */ +} R_MTU1_Type; /*!< Size = 44 (0x2c) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU2 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 2 (R_MTU2) + */ + +typedef struct /*!< (@ 0x90001400) R_MTU2 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + uint8_t : 4; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIOR; /*!< (@ 0x00000002) Timer I/O Control Register */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIOR_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + uint8_t : 2; + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + __IOM uint8_t TCIEU : 1; /*!< [5..5] Underflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x00000005) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IOM uint16_t TCNT; /*!< (@ 0x00000006) Timer Counter */ + __IOM uint16_t TGRA; /*!< (@ 0x00000008) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000000A) Timer General Register B */ + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000000C) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t PCB : 2; /*!< [4..3] Functional Expansion Control for Phase Counting Modes + * 2, 3, and 5 */ + uint8_t : 3; + } TCR2_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; +} R_MTU2_Type; /*!< Size = 16 (0x10) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU8 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 8 (R_MTU8) + */ + +typedef struct /*!< (@ 0x90001600) R_MTU8 Structure */ +{ + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000000) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000001) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000002) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000003) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000004) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 3; + } TIER_b; + }; + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x00000006) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED1; + __IOM uint32_t TCNT; /*!< (@ 0x00000008) Timer Counter */ + __IOM uint32_t TGRA; /*!< (@ 0x0000000C) Timer General Register A */ + __IOM uint32_t TGRB; /*!< (@ 0x00000010) Timer General Register B */ + __IOM uint32_t TGRC; /*!< (@ 0x00000014) Timer General Register C */ + __IOM uint32_t TGRD; /*!< (@ 0x00000018) Timer General Register D */ +} R_MTU8_Type; /*!< Size = 28 (0x1c) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU6 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 6 (R_MTU6) + */ + +typedef struct /*!< (@ 0x90001900) R_MTU6 Structure */ +{ + __IM uint16_t RESERVED[128]; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000100) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000102) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000104) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000105) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000108) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 2; + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5[3]; + __IOM uint16_t TCNT; /*!< (@ 0x00000110) Timer Counter */ + __IM uint16_t RESERVED6[3]; + __IOM uint16_t TGRA; /*!< (@ 0x00000118) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000011A) Timer General Register B */ + __IM uint16_t RESERVED7[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000124) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x00000126) Timer General Register D */ + __IM uint16_t RESERVED8[2]; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000012C) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10[5]; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000138) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12[9]; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000014C) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint8_t RESERVED13; + __IM uint16_t RESERVED14; + + union + { + __IOM uint8_t TSYCR; /*!< (@ 0x00000150) Timer Synchronous Clear Register */ + + struct + { + __IOM uint8_t CE2B : 1; /*!< [0..0] Clear Enable 2B */ + __IOM uint8_t CE2A : 1; /*!< [1..1] Clear Enable 2A */ + __IOM uint8_t CE1B : 1; /*!< [2..2] Clear Enable 1B */ + __IOM uint8_t CE1A : 1; /*!< [3..3] Clear Enable 1A */ + __IOM uint8_t CE0D : 1; /*!< [4..4] Clear Enable 0D */ + __IOM uint8_t CE0C : 1; /*!< [5..5] Clear Enable 0C */ + __IOM uint8_t CE0B : 1; /*!< [6..6] Clear Enable 0B */ + __IOM uint8_t CE0A : 1; /*!< [7..7] Clear Enable 0A */ + } TSYCR_b; + }; + __IM uint8_t RESERVED15; + __IM uint16_t RESERVED16[16]; + __IOM uint16_t TGRE; /*!< (@ 0x00000172) Timer General Register E */ +} R_MTU6_Type; /*!< Size = 372 (0x174) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU7 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 7 (R_MTU7) + */ + +typedef struct /*!< (@ 0x90001A00) R_MTU7 Structure */ +{ + __IM uint8_t RESERVED; + + union + { + __IOM uint8_t TCR; /*!< (@ 0x00000001) Timer Control Register */ + + struct + { + __IOM uint8_t TPSC : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + __IOM uint8_t CCLR : 3; /*!< [7..5] Counter Clear Source Select */ + } TCR_b; + }; + __IM uint8_t RESERVED1; + + union + { + __IOM uint8_t TMDR1; /*!< (@ 0x00000003) Timer Mode Register 1 */ + + struct + { + __IOM uint8_t MD : 4; /*!< [3..0] Mode Select */ + __IOM uint8_t BFA : 1; /*!< [4..4] Buffer Operation A */ + __IOM uint8_t BFB : 1; /*!< [5..5] Buffer Operation B */ + uint8_t : 2; + } TMDR1_b; + }; + __IM uint16_t RESERVED2; + + union + { + __IOM uint8_t TIORH; /*!< (@ 0x00000006) Timer I/O Control Register H */ + + struct + { + __IOM uint8_t IOA : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOB : 4; /*!< [7..4] I/O Control B */ + } TIORH_b; + }; + + union + { + __IOM uint8_t TIORL; /*!< (@ 0x00000007) Timer I/O Control Register L */ + + struct + { + __IOM uint8_t IOC : 4; /*!< [3..0] I/O Control A */ + __IOM uint8_t IOD : 4; /*!< [7..4] I/O Control B */ + } TIORL_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x00000009) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIEA : 1; /*!< [0..0] TGR Interrupt Enable A */ + __IOM uint8_t TGIEB : 1; /*!< [1..1] TGR Interrupt Enable B */ + __IOM uint8_t TGIEC : 1; /*!< [2..2] TGR Interrupt Enable C */ + __IOM uint8_t TGIED : 1; /*!< [3..3] TGR Interrupt Enable D */ + __IOM uint8_t TCIEV : 1; /*!< [4..4] Overflow Interrupt Enable */ + uint8_t : 1; + __IOM uint8_t TTGE2 : 1; /*!< [6..6] A/D Converter Start Request Enable 2 */ + __IOM uint8_t TTGE : 1; /*!< [7..7] A/D Converter Start Request Enable */ + } TIER_b; + }; + __IM uint16_t RESERVED4[4]; + __IOM uint16_t TCNT; /*!< (@ 0x00000012) Timer Counter */ + __IM uint16_t RESERVED5[4]; + __IOM uint16_t TGRA; /*!< (@ 0x0000001C) Timer General Register A */ + __IOM uint16_t TGRB; /*!< (@ 0x0000001E) Timer General Register B */ + __IM uint16_t RESERVED6[4]; + __IOM uint16_t TGRC; /*!< (@ 0x00000028) Timer General Register C */ + __IOM uint16_t TGRD; /*!< (@ 0x0000002A) Timer General Register D */ + __IM uint8_t RESERVED7; + + union + { + __IOM uint8_t TSR; /*!< (@ 0x0000002D) Timer Status Register */ + + struct + { + __IOM uint8_t TGFA : 1; /*!< [0..0] Input Capture/Output Compare Flag A */ + __IOM uint8_t TGFB : 1; /*!< [1..1] Input Capture/Output Compare Flag B */ + __IOM uint8_t TGFC : 1; /*!< [2..2] Input Capture/Output Compare Flag C */ + __IOM uint8_t TGFD : 1; /*!< [3..3] Input Capture/Output Compare Flag D */ + __IOM uint8_t TCFV : 1; /*!< [4..4] Overflow flag */ + __IOM uint8_t TCFU : 1; /*!< [5..5] Underflow flag */ + uint8_t : 1; + __IM uint8_t TCFD : 1; /*!< [7..7] Count Direction Flag */ + } TSR_b; + }; + __IM uint16_t RESERVED8[5]; + __IM uint8_t RESERVED9; + + union + { + __IOM uint8_t TBTM; /*!< (@ 0x00000039) Timer Buffer Operation Transfer Mode Register */ + + struct + { + __IOM uint8_t TTSA : 1; /*!< [0..0] Timing Select A */ + __IOM uint8_t TTSB : 1; /*!< [1..1] Timing Select B */ + uint8_t : 6; + } TBTM_b; + }; + __IM uint16_t RESERVED10[3]; + + union + { + __IOM uint16_t TADCR; /*!< (@ 0x00000040) Timer A/D Converter Start Request Control Register */ + + struct + { + __IOM uint16_t ITB7VE : 1; /*!< [0..0] TCIV7 Interrupt Skipping Link Enable */ + __IOM uint16_t ITB6AE : 1; /*!< [1..1] TGIA6 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA7VE : 1; /*!< [2..2] TCIV7 Interrupt Skipping Link Enable */ + __IOM uint16_t ITA6AE : 1; /*!< [3..3] TGIA6 Interrupt Skipping Link Enable */ + __IOM uint16_t DT7BE : 1; /*!< [4..4] Down-Count TRG7BN Enable */ + __IOM uint16_t UT7BE : 1; /*!< [5..5] Up-Count TRG7BN Enable */ + __IOM uint16_t DT7AE : 1; /*!< [6..6] Down-Count TRG7AN Enable */ + __IOM uint16_t UT7AE : 1; /*!< [7..7] Up-Count TRG7AN Enable */ + uint16_t : 6; + __IOM uint16_t BF : 2; /*!< [15..14] MTU7.TADCOBRA/TADCOBRB Transfer Timing Select */ + } TADCR_b; + }; + __IM uint16_t RESERVED11; + __IOM uint16_t TADCORA; /*!< (@ 0x00000044) Timer A/D Converter Start Request Cycle Set Register + * A */ + __IOM uint16_t TADCORB; /*!< (@ 0x00000046) Timer A/D Converter Start Request Cycle Set Register + * B */ + __IOM uint16_t TADCOBRA; /*!< (@ 0x00000048) Timer A/D Converter Start Request Cycle Set Buffer + * Register A */ + __IOM uint16_t TADCOBRB; /*!< (@ 0x0000004A) Timer A/D Converter Start Request Cycle Set Buffer + * Register B */ + __IM uint8_t RESERVED12; + + union + { + __IOM uint8_t TCR2; /*!< (@ 0x0000004D) Timer Control Register 2 */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + uint8_t : 5; + } TCR2_b; + }; + __IM uint16_t RESERVED13[19]; + __IOM uint16_t TGRE; /*!< (@ 0x00000074) Timer General Register E */ + __IOM uint16_t TGRF; /*!< (@ 0x00000076) Timer General Register F */ +} R_MTU7_Type; /*!< Size = 120 (0x78) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU5 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Multi-Function Timer Pulse Unit Channel 5 (R_MTU5) + */ + +typedef struct /*!< (@ 0x90001C00) R_MTU5 Structure */ +{ + __IM uint16_t RESERVED[64]; + __IOM uint16_t TCNTU; /*!< (@ 0x00000080) Timer Counter U */ + __IOM uint16_t TGRU; /*!< (@ 0x00000082) Timer General Register U */ + + union + { + __IOM uint8_t TCRU; /*!< (@ 0x00000084) Timer Control Register U */ + + struct + { + __IOM uint8_t TPSC : 2; /*!< [1..0] Time Prescaler Select */ + uint8_t : 6; + } TCRU_b; + }; + + union + { + __IOM uint8_t TCR2U; /*!< (@ 0x00000085) Timer Control Register 2U */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + uint8_t : 3; + } TCR2U_b; + }; + + union + { + __IOM uint8_t TIORU; /*!< (@ 0x00000086) Timer I/O Control Register U */ + + struct + { + __IOM uint8_t IOC : 5; /*!< [4..0] I/O Control C */ + uint8_t : 3; + } TIORU_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2[4]; + __IOM uint16_t TCNTV; /*!< (@ 0x00000090) Timer Counter V */ + __IOM uint16_t TGRV; /*!< (@ 0x00000092) Timer General Register V */ + + union + { + __IOM uint8_t TCRV; /*!< (@ 0x00000094) Timer Control Register V */ + + struct + { + __IOM uint8_t TPSC : 2; /*!< [1..0] Time Prescaler Select */ + uint8_t : 6; + } TCRV_b; + }; + + union + { + __IOM uint8_t TCR2V; /*!< (@ 0x00000095) Timer Control Register 2V */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + uint8_t : 3; + } TCR2V_b; + }; + + union + { + __IOM uint8_t TIORV; /*!< (@ 0x00000096) Timer I/O Control Register V */ + + struct + { + __IOM uint8_t IOC : 5; /*!< [4..0] I/O Control C */ + uint8_t : 3; + } TIORV_b; + }; + __IM uint8_t RESERVED3; + __IM uint16_t RESERVED4[4]; + __IOM uint16_t TCNTW; /*!< (@ 0x000000A0) Timer Counter W */ + __IOM uint16_t TGRW; /*!< (@ 0x000000A2) Timer General Register W */ + + union + { + __IOM uint8_t TCRW; /*!< (@ 0x000000A4) Timer Control Register W */ + + struct + { + __IOM uint8_t TPSC : 2; /*!< [1..0] Time Prescaler Select */ + uint8_t : 6; + } TCRW_b; + }; + + union + { + __IOM uint8_t TCR2W; /*!< (@ 0x000000A5) Timer Control Register 2W */ + + struct + { + __IOM uint8_t TPSC2 : 3; /*!< [2..0] Time Prescaler Select */ + __IOM uint8_t CKEG : 2; /*!< [4..3] Clock Edge Select */ + uint8_t : 3; + } TCR2W_b; + }; + + union + { + __IOM uint8_t TIORW; /*!< (@ 0x000000A6) Timer I/O Control Register W */ + + struct + { + __IOM uint8_t IOC : 5; /*!< [4..0] I/O Control C */ + uint8_t : 3; + } TIORW_b; + }; + __IM uint8_t RESERVED5; + __IM uint16_t RESERVED6[5]; + + union + { + __IOM uint8_t TIER; /*!< (@ 0x000000B2) Timer Interrupt Enable Register */ + + struct + { + __IOM uint8_t TGIE5W : 1; /*!< [0..0] TGR Interrupt Enable 5W */ + __IOM uint8_t TGIE5V : 1; /*!< [1..1] TGR Interrupt Enable 5V */ + __IOM uint8_t TGIE5U : 1; /*!< [2..2] TGR Interrupt Enable 5U */ + uint8_t : 5; + } TIER_b; + }; + __IM uint8_t RESERVED7; + + union + { + __IOM uint8_t TSTR; /*!< (@ 0x000000B4) Timer Start Register */ + + struct + { + __IOM uint8_t CSTW5 : 1; /*!< [0..0] Counter Start W5 */ + __IOM uint8_t CSTV5 : 1; /*!< [1..1] Counter Start V5 */ + __IOM uint8_t CSTU5 : 1; /*!< [2..2] Counter Start U5 */ + uint8_t : 5; + } TSTR_b; + }; + __IM uint8_t RESERVED8; + + union + { + __IOM uint8_t TCNTCMPCLR; /*!< (@ 0x000000B6) Timer Compare Match Clear Register */ + + struct + { + __IOM uint8_t CMPCLR5W : 1; /*!< [0..0] TCNT Compare Clear 5W */ + __IOM uint8_t CMPCLR5V : 1; /*!< [1..1] TCNT Compare Clear 5V */ + __IOM uint8_t CMPCLR5U : 1; /*!< [2..2] TCNT Compare Clear 5U */ + uint8_t : 5; + } TCNTCMPCLR_b; + }; + __IM uint8_t RESERVED9; + __IM uint16_t RESERVED10; +} R_MTU5_Type; /*!< Size = 186 (0xba) */ + +/* =========================================================================================================================== */ +/* ================ R_TFU ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Trigonometric Function Unit (R_TFU) + */ + +typedef struct /*!< (@ 0x90003000) R_TFU Structure */ +{ + __IM uint32_t RESERVED[2]; + + union + { + __IM uint8_t TRGSTS; /*!< (@ 0x00000008) Trigonometric Status Register */ + + struct + { + __IM uint8_t BSYF : 1; /*!< [0..0] Calculation in progress flag */ + __IM uint8_t ERRF : 1; /*!< [1..1] Input error flag */ + uint8_t : 6; + } TRGSTS_b; + }; + __IM uint8_t RESERVED1; + __IM uint16_t RESERVED2; + __IM uint32_t RESERVED3; + + union + { + __IOM float SCDT0; /*!< (@ 0x00000010) Sine Cosine Data Register 0 */ + + struct + { + __IOM uint32_t SCDT0 : 32; /*!< [31..0] Sine Cosine Data Register 0 (single-precision floating-point) */ + } SCDT0_b; + }; + + union + { + __IOM float SCDT1; /*!< (@ 0x00000014) Sine Cosine Data Register 1 */ + + struct + { + __IOM uint32_t SCDT1 : 32; /*!< [31..0] Sine Cosine Data Register 1 (single-precision floating-point) */ + } SCDT1_b; + }; + + union + { + __IOM float ATDT0; /*!< (@ 0x00000018) Arctangent Data Register 0 */ + + struct + { + __IOM uint32_t ATDT0 : 32; /*!< [31..0] Arctangent Data Register 0 (single-precision floating-point) */ + } ATDT0_b; + }; + + union + { + __IOM float ATDT1; /*!< (@ 0x0000001C) Arctangent Data Register 1 */ + + struct + { + __IOM uint32_t ATDT1 : 32; /*!< [31..0] Arctangent Data Register 1 (single-precision floating-point) */ + } ATDT1_b; + }; +} R_TFU_Type; /*!< Size = 32 (0x20) */ + +/* =========================================================================================================================== */ +/* ================ R_POE3 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Port Output Enable 3 (R_POE3) + */ + +typedef struct /*!< (@ 0x90005000) R_POE3 Structure */ +{ + union + { + __IOM uint16_t ICSR1; /*!< (@ 0x00000000) Input Level Control/Status Register 1 */ + + struct + { + __IOM uint16_t POE0M : 2; /*!< [1..0] POE0 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE1 : 1; /*!< [8..8] Port Interrupt Enable 1 */ + uint16_t : 3; + __IOM uint16_t POE0F : 1; /*!< [12..12] POE0 Flag */ + uint16_t : 3; + } ICSR1_b; + }; + + union + { + __IOM uint16_t OCSR1; /*!< (@ 0x00000002) Output Level Control/Status Register 1 */ + + struct + { + uint16_t : 8; + __IOM uint16_t OIE1 : 1; /*!< [8..8] Output Short Circuit Interrupt Enable 1 */ + __IOM uint16_t OCE1 : 1; /*!< [9..9] Output Short Circuit High-Impedance Enable 1 */ + uint16_t : 5; + __IOM uint16_t OSF1 : 1; /*!< [15..15] Output Short Circuit Flag 1 */ + } OCSR1_b; + }; + + union + { + __IOM uint16_t ICSR2; /*!< (@ 0x00000004) Input Level Control/Status Register 2 */ + + struct + { + __IOM uint16_t POE4M : 2; /*!< [1..0] POE4 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE2 : 1; /*!< [8..8] Port Interrupt Enable 2 */ + uint16_t : 3; + __IOM uint16_t POE4F : 1; /*!< [12..12] POE4 Flag */ + uint16_t : 3; + } ICSR2_b; + }; + + union + { + __IOM uint16_t OCSR2; /*!< (@ 0x00000006) Output Level Control/Status Register 2 */ + + struct + { + uint16_t : 8; + __IOM uint16_t OIE2 : 1; /*!< [8..8] Output Short Circuit Interrupt Enable 2 */ + __IOM uint16_t OCE2 : 1; /*!< [9..9] Output Short Circuit High-Impedance Enable 2 */ + uint16_t : 5; + __IOM uint16_t OSF2 : 1; /*!< [15..15] Output Short Circuit Flag 2 */ + } OCSR2_b; + }; + + union + { + __IOM uint16_t ICSR3; /*!< (@ 0x00000008) Input Level Control/Status Register 3 */ + + struct + { + __IOM uint16_t POE8M : 2; /*!< [1..0] POE8 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE3 : 1; /*!< [8..8] Port Interrupt Enable 3 */ + __IOM uint16_t POE8E : 1; /*!< [9..9] POE8 High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t POE8F : 1; /*!< [12..12] POE8 Flag */ + uint16_t : 3; + } ICSR3_b; + }; + + union + { + __IOM uint8_t SPOER; /*!< (@ 0x0000000A) Software Port Output Enable Register */ + + struct + { + __IOM uint8_t MTUCH34HIZ : 1; /*!< [0..0] MTU3 and MTU4 Output High-Impedance Enable */ + __IOM uint8_t MTUCH67HIZ : 1; /*!< [1..1] MTU6 and MTU7 Output High-Impedance Enable */ + __IOM uint8_t MTUCH0HIZ : 1; /*!< [2..2] MTU0 Pin High-Impedance Enable */ + uint8_t : 5; + } SPOER_b; + }; + + union + { + __IOM uint8_t POECR1; /*!< (@ 0x0000000B) Port Output Enable Control Register 1 */ + + struct + { + __IOM uint8_t MTU0AZE : 1; /*!< [0..0] MTIOC0A High-Impedance Enable */ + __IOM uint8_t MTU0BZE : 1; /*!< [1..1] MTIOC0B High-Impedance Enable */ + __IOM uint8_t MTU0CZE : 1; /*!< [2..2] MTIOC0C High-Impedance Enable */ + __IOM uint8_t MTU0DZE : 1; /*!< [3..3] MTIOC0D High-Impedance Enable */ + uint8_t : 4; + } POECR1_b; + }; + + union + { + __IOM uint16_t POECR2; /*!< (@ 0x0000000C) Port Output Enable Control Register 2 */ + + struct + { + __IOM uint16_t MTU7BDZE : 1; /*!< [0..0] MTIOC7B/MTIOC7D High-Impedance Enable */ + __IOM uint16_t MTU7ACZE : 1; /*!< [1..1] MTIOC7A/MTIOC7C High-Impedance Enable */ + __IOM uint16_t MTU6BDZE : 1; /*!< [2..2] MTIOC6B/MTIOC6D High-Impedance Enable */ + uint16_t : 5; + __IOM uint16_t MTU4BDZE : 1; /*!< [8..8] MTIOC4B/MTIOC4D High-Impedance Enable */ + __IOM uint16_t MTU4ACZE : 1; /*!< [9..9] MTIOC4A/MTIOC4C High-Impedance Enable */ + __IOM uint16_t MTU3BDZE : 1; /*!< [10..10] MTIOC3B/MTIOC3D High-Impedance Enable */ + uint16_t : 5; + } POECR2_b; + }; + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t POECR4; /*!< (@ 0x00000010) Port Output Enable Control Register 4 */ + + struct + { + uint16_t : 2; + __IOM uint16_t IC2ADDMT34ZE : 1; /*!< [2..2] MTU3 and MTU4 High-Impedance POE4F Add */ + __IOM uint16_t IC3ADDMT34ZE : 1; /*!< [3..3] MTU3 and MTU4 High-Impedance POE8F Add */ + __IOM uint16_t IC4ADDMT34ZE : 1; /*!< [4..4] MTU3 and MTU4 High-Impedance POE10F Add */ + __IOM uint16_t IC5ADDMT34ZE : 1; /*!< [5..5] MTU3 and MTU4 High-Impedance POE11F Add */ + __IOM uint16_t DE0ADDMT34ZE : 1; /*!< [6..6] MTU3 and MTU4 High-Impedance DERR0ST Add */ + __IOM uint16_t DE1ADDMT34ZE : 1; /*!< [7..7] MTU3 and MTU4 High-Impedance DERR1ST Add */ + uint16_t : 1; + __IOM uint16_t IC1ADDMT67ZE : 1; /*!< [9..9] MTU6 and MTU7 High-Impedance POE0F Add */ + uint16_t : 1; + __IOM uint16_t IC3ADDMT67ZE : 1; /*!< [11..11] MTU6 and MTU7 High-Impedance POE8F Add */ + __IOM uint16_t IC4ADDMT67ZE : 1; /*!< [12..12] MTU6 and MTU7 High-Impedance POE10F Add */ + __IOM uint16_t IC5ADDMT67ZE : 1; /*!< [13..13] MTU6 and MTU7 High-Impedance POE11F Add */ + __IOM uint16_t DE0ADDMT67ZE : 1; /*!< [14..14] MTU6 and MTU7 High-Impedance DERR0ST Add */ + __IOM uint16_t DE1ADDMT67ZE : 1; /*!< [15..15] MTU6 and MTU7 High-Impedance DERR1ST Add */ + } POECR4_b; + }; + + union + { + __IOM uint16_t POECR5; /*!< (@ 0x00000012) Port Output Enable Control Register 5 */ + + struct + { + uint16_t : 1; + __IOM uint16_t IC1ADDMT0ZE : 1; /*!< [1..1] MTU0 High-Impedance POE0F Add */ + __IOM uint16_t IC2ADDMT0ZE : 1; /*!< [2..2] MTU0 High-Impedance POE4F Add */ + uint16_t : 1; + __IOM uint16_t IC4ADDMT0ZE : 1; /*!< [4..4] MTU0 High-Impedance POE10F Add */ + __IOM uint16_t IC5ADDMT0ZE : 1; /*!< [5..5] MTU0 High-Impedance POE11F Add */ + __IOM uint16_t DE0ADDMT0ZE : 1; /*!< [6..6] MTU0 High-Impedance DERR0ST Add */ + __IOM uint16_t DE1ADDMT0ZE : 1; /*!< [7..7] MTU0 High-Impedance DERR1ST Add */ + uint16_t : 8; + } POECR5_b; + }; + __IM uint16_t RESERVED1; + + union + { + __IOM uint16_t ICSR4; /*!< (@ 0x00000016) Input Level Control/Status Register 4 */ + + struct + { + __IOM uint16_t POE10M : 2; /*!< [1..0] POE10 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE4 : 1; /*!< [8..8] Port Interrupt Enable 4 */ + __IOM uint16_t POE10E : 1; /*!< [9..9] POE10 High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t POE10F : 1; /*!< [12..12] POE10 Flag */ + uint16_t : 3; + } ICSR4_b; + }; + + union + { + __IOM uint16_t ICSR5; /*!< (@ 0x00000018) Input Level Control/Status Register 5 */ + + struct + { + __IOM uint16_t POE11M : 2; /*!< [1..0] POE11 Mode Select */ + uint16_t : 6; + __IOM uint16_t PIE5 : 1; /*!< [8..8] Port Interrupt Enable 5 */ + __IOM uint16_t POE11E : 1; /*!< [9..9] POE11 High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t POE11F : 1; /*!< [12..12] POE11 Flag */ + uint16_t : 3; + } ICSR5_b; + }; + + union + { + __IOM uint16_t ALR1; /*!< (@ 0x0000001A) Active Level Setting Register 1 */ + + struct + { + __IOM uint16_t OLSG0A : 1; /*!< [0..0] MTIOC3B Pin Active Level Setting */ + __IOM uint16_t OLSG0B : 1; /*!< [1..1] MTIOC3D Pin Active Level Setting */ + __IOM uint16_t OLSG1A : 1; /*!< [2..2] MTIOC4A Pin Active Level Setting */ + __IOM uint16_t OLSG1B : 1; /*!< [3..3] MTIOC4C Pin Active Level Setting */ + __IOM uint16_t OLSG2A : 1; /*!< [4..4] MTIOC4B Pin Active Level Setting */ + __IOM uint16_t OLSG2B : 1; /*!< [5..5] MTIOC4D Pin Active Level Setting */ + uint16_t : 1; + __IOM uint16_t OLSEN : 1; /*!< [7..7] Active Level Setting Enable */ + uint16_t : 8; + } ALR1_b; + }; + + union + { + __IOM uint16_t ICSR6; /*!< (@ 0x0000001C) Input Level Control/Status Register 6 */ + + struct + { + uint16_t : 9; + __IOM uint16_t OSTSTE : 1; /*!< [9..9] Oscillation Stop High-Impedance Enable */ + uint16_t : 2; + __IOM uint16_t OSTSTF : 1; /*!< [12..12] Oscillation Stop High-Impedance Flag */ + uint16_t : 3; + } ICSR6_b; + }; + + union + { + __IOM uint16_t ICSR7; /*!< (@ 0x0000001E) Input Level Control/Status Register 7 */ + + struct + { + uint16_t : 6; + __IOM uint16_t DERR0IE : 1; /*!< [6..6] DSMIF0 Error Interrupt Enable */ + __IOM uint16_t DERR1IE : 1; /*!< [7..7] DSMIF1 Error Interrupt Enable */ + uint16_t : 5; + __IM uint16_t DERR0ST : 1; /*!< [13..13] DSMIF0 Error Status */ + __IM uint16_t DERR1ST : 1; /*!< [14..14] DSMIF1 Error Status */ + uint16_t : 1; + } ICSR7_b; + }; + __IM uint16_t RESERVED2[2]; + + union + { + __IOM uint8_t M0SELR1; /*!< (@ 0x00000024) MTU0 Pin Select Register 1 */ + + struct + { + __IOM uint8_t M0ASEL : 4; /*!< [3..0] MTU0-A (MTIOC0A) Pin Select */ + __IOM uint8_t M0BSEL : 4; /*!< [7..4] MTU0-B (MTIOC0B) Pin Select */ + } M0SELR1_b; + }; + + union + { + __IOM uint8_t M0SELR2; /*!< (@ 0x00000025) MTU0 Pin Select Register 2 */ + + struct + { + __IOM uint8_t M0CSEL : 4; /*!< [3..0] MTU0-C (MTIOC0C) Pin Select */ + __IOM uint8_t M0DSEL : 4; /*!< [7..4] MTU0-D (MTIOC0D) Pin Select */ + } M0SELR2_b; + }; + + union + { + __IOM uint8_t M3SELR; /*!< (@ 0x00000026) MTU3 Pin Select Register */ + + struct + { + __IOM uint8_t M3BSEL : 4; /*!< [3..0] MTU3-B (MTIOC3B) Pin Select */ + __IOM uint8_t M3DSEL : 4; /*!< [7..4] MTU3-D (MTIOC3D) Pin Select */ + } M3SELR_b; + }; + + union + { + __IOM uint8_t M4SELR1; /*!< (@ 0x00000027) MTU4 Pin Select Register 1 */ + + struct + { + __IOM uint8_t M4ASEL : 4; /*!< [3..0] MTU4-A (MTIOC4A) Pin Select */ + __IOM uint8_t M4CSEL : 4; /*!< [7..4] MTU4-C (MTIOC4C) Pin Select */ + } M4SELR1_b; + }; + + union + { + __IOM uint8_t M4SELR2; /*!< (@ 0x00000028) MTU4 Pin Select Register 2 */ + + struct + { + __IOM uint8_t M4BSEL : 4; /*!< [3..0] MTU4-B (MTIOC4B) Pin Select */ + __IOM uint8_t M4DSEL : 4; /*!< [7..4] MTU4-D (MTIOC4D) Pin Select */ + } M4SELR2_b; + }; + __IM uint8_t RESERVED3; + + union + { + __IOM uint8_t M6SELR; /*!< (@ 0x0000002A) MTU6 Pin Select Register */ + + struct + { + __IOM uint8_t M6BSEL : 4; /*!< [3..0] MTU6-B (MTIOC6B) Pin Select */ + __IOM uint8_t M6DSEL : 4; /*!< [7..4] MTU6-D (MTIOC6D) Pin Select */ + } M6SELR_b; + }; + + union + { + __IOM uint8_t M7SELR1; /*!< (@ 0x0000002B) MTU7 Pin Select Register 1 */ + + struct + { + __IOM uint8_t M7ASEL : 4; /*!< [3..0] MTU7-A (MTIOC7A) Pin Select */ + __IOM uint8_t M7CSEL : 4; /*!< [7..4] MTU7-C (MTIOC7C) Pin Select */ + } M7SELR1_b; + }; + + union + { + __IOM uint8_t M7SELR2; /*!< (@ 0x0000002C) MTU7 Pin Select Register 2 */ + + struct + { + __IOM uint8_t M7BSEL : 4; /*!< [3..0] MTU7-B (MTIOC7B) Pin Select */ + __IOM uint8_t M7DSEL : 4; /*!< [7..4] MTU7-D (MTIOC7D) Pin Select */ + } M7SELR2_b; + }; + __IM uint8_t RESERVED4; + __IM uint16_t RESERVED5; +} R_POE3_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief GPT Port Output Enable 0 (R_POEG0) + */ + +typedef struct /*!< (@ 0x90006000) R_POEG0 Structure */ +{ + union + { + __IOM uint32_t POEG0GA; /*!< (@ 0x00000000) POEG0 Group A Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GA_b; + }; + __IM uint32_t RESERVED[255]; + + union + { + __IOM uint32_t POEG0GB; /*!< (@ 0x00000400) POEG0 Group B Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GB_b; + }; + __IM uint32_t RESERVED1[255]; + + union + { + __IOM uint32_t POEG0GC; /*!< (@ 0x00000800) POEG0 Group C Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GC_b; + }; + __IM uint32_t RESERVED2[255]; + + union + { + __IOM uint32_t POEG0GD; /*!< (@ 0x00000C00) POEG0 Group D Setting Register */ + + struct + { + __IOM uint32_t PIDF : 1; /*!< [0..0] Port Input Detection Flag */ + __IOM uint32_t IOCF : 1; /*!< [1..1] GPT Output Stop Request Detection Flag */ + __IOM uint32_t OSTPF : 1; /*!< [2..2] Oscillation Stop Detection Flag */ + __IOM uint32_t SSF : 1; /*!< [3..3] Software Stop Flag */ + __IOM uint32_t PIDE : 1; /*!< [4..4] Port Input Detection Enable */ + __IOM uint32_t IOCE : 1; /*!< [5..5] GPT Output Stop Request Enable */ + __IOM uint32_t OSTPE : 1; /*!< [6..6] Enable Stopping Output on Stopping of Oscillation */ + uint32_t : 9; + __IM uint32_t ST : 1; /*!< [16..16] GTETRGn Input Status Flag */ + uint32_t : 7; + __IOM uint32_t DERR0ST : 1; /*!< [24..24] DSMIF0 error status */ + __IOM uint32_t DERR1ST : 1; /*!< [25..25] DSMIF1 error status */ + __IOM uint32_t DERR0E : 1; /*!< [26..26] Permit output disabled by DSMIF0 error detection */ + __IOM uint32_t DERR1E : 1; /*!< [27..27] Permit output disabled by DSMIF1 error detection */ + __IOM uint32_t INV : 1; /*!< [28..28] GTETRGn Input Inverting */ + __IOM uint32_t NFEN : 1; /*!< [29..29] Noise filter Enable */ + __IOM uint32_t NFCS : 2; /*!< [31..30] Noise filter Clock Select */ + } POEG0GD_b; + }; +} R_POEG0_Type; /*!< Size = 3076 (0xc04) */ + +/* =========================================================================================================================== */ +/* ================ R_DSMIF0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Delta-sigma Interface 0 (R_DSMIF0) + */ + +typedef struct /*!< (@ 0x90008000) R_DSMIF0 Structure */ +{ + __IM uint32_t RESERVED[16]; + + union + { + __IOM uint32_t DSSEICR; /*!< (@ 0x00000040) Overcurrent Sum Error Detect Interrupt Control + * Register */ + + struct + { + __IOM uint32_t ISEL : 1; /*!< [0..0] Overcurrent sum error lower limit detection interrupt + * enable bit */ + __IOM uint32_t ISEH : 1; /*!< [1..1] Overcurrent sum error upper limit detection interrupt + * enable bit */ + uint32_t : 30; + } DSSEICR_b; + }; + + union + { + __IOM uint32_t DSSECSR; /*!< (@ 0x00000044) Overcurrent Sum Error Detect Channel Setting + * Register */ + + struct + { + __IOM uint32_t SEDM : 3; /*!< [2..0] Overcurrent sum error detect mode setting bit */ + uint32_t : 29; + } DSSECSR_b; + }; + + union + { + __IOM uint32_t DSSELTR; /*!< (@ 0x00000048) Overcurrent Sum Error Detect Low Threshold Register */ + + struct + { + __IOM uint32_t SCMPTBL : 18; /*!< [17..0] Overcurrent sum error detect lower limit */ + uint32_t : 14; + } DSSELTR_b; + }; + + union + { + __IOM uint32_t DSSEHTR; /*!< (@ 0x0000004C) Overcurrent Sum Error Detect High Threshold Register */ + + struct + { + __IOM uint32_t SCMPTBH : 18; /*!< [17..0] Overcurrent sum error detect upper limit */ + uint32_t : 14; + } DSSEHTR_b; + }; + + union + { + __IOM uint32_t DSSECR; /*!< (@ 0x00000050) Overcurrent Sum Error Detect Control Register */ + + struct + { + __IOM uint32_t SEEL : 1; /*!< [0..0] Overcurrent sum error lower limit detection enable bit */ + __IOM uint32_t SEEH : 1; /*!< [1..1] Overcurrent sum error upper limit detection enable bit */ + uint32_t : 30; + } DSSECR_b; + }; + __IM uint32_t RESERVED1[3]; + + union + { + __IOM uint32_t DSSECDR[3]; /*!< (@ 0x00000060) Overcurrent Sum Error Detect Capture Data Register + * [0..2] */ + + struct + { + __IOM uint32_t SECDR : 16; /*!< [15..0] Overcurrent sum error detect capture data n */ + uint32_t : 16; + } DSSECDR_b[3]; + }; + __IM uint32_t RESERVED2[37]; + + union + { + __IOM uint32_t DSCSTRTR; /*!< (@ 0x00000100) Channel Software Start Trigger Register */ + + struct + { + __IOM uint32_t STRTRG0 : 1; /*!< [0..0] Channel 0 start trigger */ + __IOM uint32_t STRTRG1 : 1; /*!< [1..1] Channel 1 start trigger */ + __IOM uint32_t STRTRG2 : 1; /*!< [2..2] Channel 2 start trigger */ + uint32_t : 29; + } DSCSTRTR_b; + }; + + union + { + __IOM uint32_t DSCSTPTR; /*!< (@ 0x00000104) Channel Software Stop Trigger Register */ + + struct + { + __IOM uint32_t STPTRG0 : 1; /*!< [0..0] Channel 0 stop trigger */ + __IOM uint32_t STPTRG1 : 1; /*!< [1..1] Channel 1 stop trigger */ + __IOM uint32_t STPTRG2 : 1; /*!< [2..2] Channel 2 stop trigger */ + uint32_t : 29; + } DSCSTPTR_b; + }; + __IM uint32_t RESERVED3[2]; + + union + { + __IM uint32_t DSCESR; /*!< (@ 0x00000110) Channel Error Status Register */ + + struct + { + __IM uint32_t OCFL0 : 1; /*!< [0..0] Channel 0 overcurrent lower limit detection flag */ + __IM uint32_t OCFL1 : 1; /*!< [1..1] Channel 1 overcurrent lower limit detection flag */ + __IM uint32_t OCFL2 : 1; /*!< [2..2] Channel 2 overcurrent lower limit detection flag */ + uint32_t : 1; + __IM uint32_t OCFH0 : 1; /*!< [4..4] Channel 0 overcurrent upper limit detection flag */ + __IM uint32_t OCFH1 : 1; /*!< [5..5] Channel 1 overcurrent upper limit detection flag */ + __IM uint32_t OCFH2 : 1; /*!< [6..6] Channel 2 overcurrent upper limit detection flag */ + uint32_t : 1; + __IM uint32_t SCF0 : 1; /*!< [8..8] Channel 0 short circuit detection flag */ + __IM uint32_t SCF1 : 1; /*!< [9..9] Channel 1 short circuit detection flag */ + __IM uint32_t SCF2 : 1; /*!< [10..10] Channel 2 short circuit detection flag */ + uint32_t : 5; + __IM uint32_t SUMERRL : 1; /*!< [16..16] Overcurrent sum error lower limit detection flag */ + __IM uint32_t SUMERRH : 1; /*!< [17..17] Overcurrent sum error upper limit detection flag */ + uint32_t : 14; + } DSCESR_b; + }; + __IM uint32_t RESERVED4; + + union + { + __IM uint32_t DSCSR; /*!< (@ 0x00000118) Channel Status Register */ + + struct + { + __IM uint32_t DUF0 : 1; /*!< [0..0] Channel 0 Data Update flag */ + __IM uint32_t DUF1 : 1; /*!< [1..1] Channel 1 Data Update flag */ + __IM uint32_t DUF2 : 1; /*!< [2..2] Channel 2 Data Update flag */ + uint32_t : 29; + } DSCSR_b; + }; + + union + { + __IM uint32_t DSCSSR; /*!< (@ 0x0000011C) Channel State Status Register */ + + struct + { + __IM uint32_t CHSTATE0 : 1; /*!< [0..0] Channel 0 state */ + uint32_t : 3; + __IM uint32_t CHSTATE1 : 1; /*!< [4..4] Channel 1 state */ + uint32_t : 3; + __IM uint32_t CHSTATE2 : 1; /*!< [8..8] Channel 2 state */ + uint32_t : 23; + } DSCSSR_b; + }; + + union + { + __OM uint32_t DSCESCR; /*!< (@ 0x00000120) Channel Error Status Clear Register */ + + struct + { + __OM uint32_t CLROCFL0 : 1; /*!< [0..0] Channel 0 Overcurrent Lower Limit Detection Flag Clear */ + __OM uint32_t CLROCFL1 : 1; /*!< [1..1] Channel 1 Overcurrent Lower Limit Detection Flag Clear */ + __OM uint32_t CLROCFL2 : 1; /*!< [2..2] Channel 2 Overcurrent Lower Limit Detection Flag Clear */ + uint32_t : 1; + __OM uint32_t CLROCFH0 : 1; /*!< [4..4] Channel 0 Overcurrent Upper Limit Detection Flag Clear */ + __OM uint32_t CLROCFH1 : 1; /*!< [5..5] Channel 1 Overcurrent Upper Limit Detection Flag Clear */ + __OM uint32_t CLROCFH2 : 1; /*!< [6..6] Channel 2 Overcurrent Upper Limit Detection Flag Clear */ + uint32_t : 1; + __OM uint32_t CLRSCF0 : 1; /*!< [8..8] Channel 0 Short Circuit Detection Flag Clear */ + __OM uint32_t CLRSCF1 : 1; /*!< [9..9] Channel 1 Short Circuit Detection Flag Clear */ + __OM uint32_t CLRSCF2 : 1; /*!< [10..10] Channel 2 Short Circuit Detection Flag Clear */ + uint32_t : 5; + __OM uint32_t CLRSUMERRL : 1; /*!< [16..16] Overcurrent Sum Error Lower Limit Detection Flag Clear */ + __OM uint32_t CLRSUMERRH : 1; /*!< [17..17] Overcurrent Sum Error Upper Limit Detection Flag Clear */ + uint32_t : 14; + } DSCESCR_b; + }; + __IM uint32_t RESERVED5; + + union + { + __OM uint32_t DSCSCR; /*!< (@ 0x00000128) Channel Status Clear Register */ + + struct + { + __OM uint32_t CLRDUF0 : 1; /*!< [0..0] Channel 0 Data Update Flag Clear */ + __OM uint32_t CLRDUF1 : 1; /*!< [1..1] Channel 1 Data Update Flag Clear */ + __OM uint32_t CLRDUF2 : 1; /*!< [2..2] Channel 2 Data Update Flag Clear */ + uint32_t : 29; + } DSCSCR_b; + }; + __IM uint32_t RESERVED6[21]; + __IOM R_DSMIF0_CH_Type CH[3]; /*!< (@ 0x00000180) Channel Registers [0..2] */ +} R_DSMIF0_Type; /*!< Size = 816 (0x330) */ + +/* =========================================================================================================================== */ +/* ================ R_GSC ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Global System Counter (R_GSC) + */ + +typedef struct /*!< (@ 0xC0060000) R_GSC Structure */ +{ + union + { + __IOM uint32_t CNTCR; /*!< (@ 0x00000000) Global System Counter Control Register */ + + struct + { + __IOM uint32_t EN : 1; /*!< [0..0] Counter Enable */ + __IOM uint32_t HDBG : 1; /*!< [1..1] Halt on Debug */ + uint32_t : 30; + } CNTCR_b; + }; + + union + { + __IM uint32_t CNTSR; /*!< (@ 0x00000004) Global System Counter Status Register */ + + struct + { + uint32_t : 1; + __IM uint32_t DBGH : 1; /*!< [1..1] Debug Halted */ + uint32_t : 30; + } CNTSR_b; + }; + + union + { + __IOM uint32_t CNTCVL; /*!< (@ 0x00000008) Global System Counter Current Value Lower Register */ + + struct + { + __IOM uint32_t CNTCVL_L_32 : 32; /*!< [31..0] Current value of the counter, lower 32 bits */ + } CNTCVL_b; + }; + + union + { + __IOM uint32_t CNTCVU; /*!< (@ 0x0000000C) Global System Counter Current Value Upper Register */ + + struct + { + __IOM uint32_t CNTCVU_U_32 : 32; /*!< [31..0] Current value of the counter, upper 32 bits */ + } CNTCVU_b; + }; + __IM uint32_t RESERVED[4]; + + union + { + __IOM uint32_t CNTFID0; /*!< (@ 0x00000020) Global System Counter Base Frequency ID Register */ + + struct + { + __IOM uint32_t FREQ : 32; /*!< [31..0] Frequency in number of ticks per second */ + } CNTFID0_b; + }; +} R_GSC_Type; /*!< Size = 36 (0x24) */ + +/** @} */ /* End of group Device_Peripheral_peripherals */ + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + + #define R_GPT7_BASE 0x80000000UL + #define R_GPT8_BASE 0x80000100UL + #define R_GPT9_BASE 0x80000200UL + #define R_GPT10_BASE 0x80000300UL + #define R_GPT11_BASE 0x80000400UL + #define R_GPT12_BASE 0x80000500UL + #define R_GPT13_BASE 0x80000600UL + #define R_SCI0_BASE 0x80001000UL + #define R_SCI1_BASE 0x80001400UL + #define R_SCI2_BASE 0x80001800UL + #define R_SCI3_BASE 0x80001C00UL + #define R_SCI4_BASE 0x80002000UL + #define R_SPI0_BASE 0x80003000UL + #define R_SPI1_BASE 0x80003400UL + #define R_SPI2_BASE 0x80003800UL + #define R_CRC0_BASE 0x80004000UL + #define R_CANFD_BASE 0x80020000UL + #define R_CMT_BASE 0x80040000UL + #define R_CMTW0_BASE 0x80041000UL + #define R_CMTW1_BASE 0x80041400UL + #define R_WDT0_BASE 0x80042000UL + #define R_IIC0_BASE 0x80043000UL + #define R_IIC1_BASE 0x80043400UL + #define R_DOC_BASE 0x80044000UL + #define R_ADC121_BASE 0x80045000UL + #define R_TSU_BASE 0x80046000UL + #define R_POEG1_BASE 0x80047000UL + #define R_DMAC0_BASE 0x80080000UL + #define R_DMAC1_BASE 0x80081000UL + #define R_ICU_NS_BASE 0x80090000UL + #define R_ELC_BASE 0x80090010UL + #define R_DMA_BASE 0x80090060UL + #define R_PORT_NSR_BASE 0x800A0000UL + #define R_GMAC_BASE 0x80100000UL + #define R_ETHSS_BASE 0x80110000UL + #define R_ESC_INI_BASE 0x80110200UL + #define R_ETHSW_PTP_BASE 0x80110400UL + #define R_ETHSW_BASE 0x80120000UL + #define R_ESC_BASE 0x80130000UL + #define R_USBHC_BASE 0x80200000UL + #define R_USBF_BASE 0x80201000UL + #define R_BSC_BASE 0x80210000UL + #define R_XSPI0_BASE 0x80220000UL + #define R_XSPI1_BASE 0x80221000UL + #define R_MBXSEM_BASE 0x80240000UL + #define R_SHOSTIF_BASE 0x80241000UL + #define R_PHOSTIF_BASE 0x80242000UL + #define R_SYSC_NS_BASE 0x80280000UL + #define R_ELO_BASE 0x80281200UL + #define R_RWP_NS_BASE 0x80281A10UL + #define R_GPT14_BASE 0x81000000UL + #define R_GPT15_BASE 0x81000100UL + #define R_GPT16_BASE 0x81000200UL + #define R_GPT17_BASE 0x81000300UL + #define R_SCI5_BASE 0x81001000UL + #define R_SPI3_BASE 0x81002000UL + #define R_CRC1_BASE 0x81003000UL + #define R_IIC2_BASE 0x81008000UL + #define R_RTC_BASE 0x81009000UL + #define R_POEG2_BASE 0x8100A000UL + #define R_OTP_BASE 0x81028000UL + #define R_PORT_SR_BASE 0x81030000UL + #define R_PTADR_BASE 0x81030C00UL + #define R_SYSRAM0_BASE 0x81040000UL + #define R_SYSRAM1_BASE 0x81041000UL + #define R_SYSRAM2_BASE 0x81042000UL + #define R_ICU_BASE 0x81048000UL + #define R_SYSC_S_BASE 0x81280000UL + #define R_CLMA0_BASE 0x81280800UL + #define R_CLMA1_BASE 0x81280820UL + #define R_CLMA2_BASE 0x81280840UL + #define R_CLMA3_BASE 0x81280860UL + #define R_MPU0_BASE 0x81281100UL + #define R_MPU1_BASE 0x81281200UL + #define R_MPU2_BASE 0x81281300UL + #define R_MPU3_BASE 0x81281400UL + #define R_MPU4_BASE 0x81281500UL + #define R_MPU6_BASE 0x81281700UL + #define R_SYSRAM_CTL_BASE 0x81281800UL + #define R_SHOSTIF_CFG_BASE 0x81281920UL + #define R_PHOSTIF_CFG_BASE 0x81281930UL + #define R_RWP_S_BASE 0x81281A00UL + #define R_MPU7_BASE 0x81281C00UL + #define R_MPU8_BASE 0x81281D00UL + #define R_MTU_BASE 0x90001000UL + #define R_MTU3_BASE 0x90001100UL + #define R_MTU4_BASE 0x90001200UL + #define R_MTU_NF_BASE 0x90001290UL + #define R_MTU0_BASE 0x90001300UL + #define R_MTU1_BASE 0x90001380UL + #define R_MTU2_BASE 0x90001400UL + #define R_MTU8_BASE 0x90001600UL + #define R_MTU6_BASE 0x90001900UL + #define R_MTU7_BASE 0x90001A00UL + #define R_MTU5_BASE 0x90001C00UL + #define R_GPT0_BASE 0x90002000UL + #define R_GPT1_BASE 0x90002100UL + #define R_GPT2_BASE 0x90002200UL + #define R_GPT3_BASE 0x90002300UL + #define R_GPT4_BASE 0x90002400UL + #define R_GPT5_BASE 0x90002500UL + #define R_GPT6_BASE 0x90002600UL + #define R_TFU_BASE 0x90003000UL + #define R_ADC120_BASE 0x90004000UL + #define R_POE3_BASE 0x90005000UL + #define R_POEG0_BASE 0x90006000UL + #define R_DSMIF0_BASE 0x90008000UL + #define R_DSMIF1_BASE 0x90008400UL + #define R_GSC_BASE 0xC0060000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + + #define R_GPT7 ((R_GPT0_Type *) R_GPT7_BASE) + #define R_GPT8 ((R_GPT0_Type *) R_GPT8_BASE) + #define R_GPT9 ((R_GPT0_Type *) R_GPT9_BASE) + #define R_GPT10 ((R_GPT0_Type *) R_GPT10_BASE) + #define R_GPT11 ((R_GPT0_Type *) R_GPT11_BASE) + #define R_GPT12 ((R_GPT0_Type *) R_GPT12_BASE) + #define R_GPT13 ((R_GPT0_Type *) R_GPT13_BASE) + #define R_SCI0 ((R_SCI0_Type *) R_SCI0_BASE) + #define R_SCI1 ((R_SCI0_Type *) R_SCI1_BASE) + #define R_SCI2 ((R_SCI0_Type *) R_SCI2_BASE) + #define R_SCI3 ((R_SCI0_Type *) R_SCI3_BASE) + #define R_SCI4 ((R_SCI0_Type *) R_SCI4_BASE) + #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) + #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) + #define R_SPI2 ((R_SPI0_Type *) R_SPI2_BASE) + #define R_CRC0 ((R_CRC0_Type *) R_CRC0_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CMT ((R_CMT_Type *) R_CMT_BASE) + #define R_CMTW0 ((R_CMTW0_Type *) R_CMTW0_BASE) + #define R_CMTW1 ((R_CMTW0_Type *) R_CMTW1_BASE) + #define R_WDT0 ((R_WDT0_Type *) R_WDT0_BASE) + #define R_IIC0 ((R_IIC0_Type *) R_IIC0_BASE) + #define R_IIC1 ((R_IIC0_Type *) R_IIC1_BASE) + #define R_DOC ((R_DOC_Type *) R_DOC_BASE) + #define R_ADC121 ((R_ADC121_Type *) R_ADC121_BASE) + #define R_TSU ((R_TSU_Type *) R_TSU_BASE) + #define R_POEG1 ((R_POEG1_Type *) R_POEG1_BASE) + #define R_DMAC0 ((R_DMAC0_Type *) R_DMAC0_BASE) + #define R_DMAC1 ((R_DMAC0_Type *) R_DMAC1_BASE) + #define R_ICU_NS ((R_ICU_NS_Type *) R_ICU_NS_BASE) + #define R_ELC ((R_ELC_Type *) R_ELC_BASE) + #define R_DMA ((R_DMA_Type *) R_DMA_BASE) + #define R_PORT_NSR ((R_PORT_COMMON_Type *) R_PORT_NSR_BASE) + #define R_GMAC ((R_GMAC_Type *) R_GMAC_BASE) + #define R_ETHSS ((R_ETHSS_Type *) R_ETHSS_BASE) + #define R_ESC_INI ((R_ESC_INI_Type *) R_ESC_INI_BASE) + #define R_ETHSW_PTP ((R_ETHSW_PTP_Type *) R_ETHSW_PTP_BASE) + #define R_ETHSW ((R_ETHSW_Type *) R_ETHSW_BASE) + #define R_ESC ((R_ESC_Type *) R_ESC_BASE) + #define R_USBHC ((R_USBHC_Type *) R_USBHC_BASE) + #define R_USBF ((R_USBF_Type *) R_USBF_BASE) + #define R_BSC ((R_BSC_Type *) R_BSC_BASE) + #define R_XSPI0 ((R_XSPI0_Type *) R_XSPI0_BASE) + #define R_XSPI1 ((R_XSPI0_Type *) R_XSPI1_BASE) + #define R_MBXSEM ((R_MBXSEM_Type *) R_MBXSEM_BASE) + #define R_SHOSTIF ((R_SHOSTIF_Type *) R_SHOSTIF_BASE) + #define R_PHOSTIF ((R_PHOSTIF_Type *) R_PHOSTIF_BASE) + #define R_SYSC_NS ((R_SYSC_NS_Type *) R_SYSC_NS_BASE) + #define R_ELO ((R_ELO_Type *) R_ELO_BASE) + #define R_RWP_NS ((R_RWP_NS_Type *) R_RWP_NS_BASE) + #define R_GPT14 ((R_GPT0_Type *) R_GPT14_BASE) + #define R_GPT15 ((R_GPT0_Type *) R_GPT15_BASE) + #define R_GPT16 ((R_GPT0_Type *) R_GPT16_BASE) + #define R_GPT17 ((R_GPT0_Type *) R_GPT17_BASE) + #define R_SCI5 ((R_SCI0_Type *) R_SCI5_BASE) + #define R_SPI3 ((R_SPI0_Type *) R_SPI3_BASE) + #define R_CRC1 ((R_CRC0_Type *) R_CRC1_BASE) + #define R_IIC2 ((R_IIC0_Type *) R_IIC2_BASE) + #define R_RTC ((R_RTC_Type *) R_RTC_BASE) + #define R_POEG2 ((R_POEG2_Type *) R_POEG2_BASE) + #define R_OTP ((R_OTP_Type *) R_OTP_BASE) + #define R_PORT_SR ((R_PORT_COMMON_Type *) R_PORT_SR_BASE) + #define R_PTADR ((R_PTADR_Type *) R_PTADR_BASE) + #define R_SYSRAM0 ((R_SYSRAM0_Type *) R_SYSRAM0_BASE) + #define R_SYSRAM1 ((R_SYSRAM0_Type *) R_SYSRAM1_BASE) + #define R_SYSRAM2 ((R_SYSRAM0_Type *) R_SYSRAM2_BASE) + #define R_ICU ((R_ICU_Type *) R_ICU_BASE) + #define R_SYSC_S ((R_SYSC_S_Type *) R_SYSC_S_BASE) + #define R_CLMA0 ((R_CLMA0_Type *) R_CLMA0_BASE) + #define R_CLMA1 ((R_CLMA0_Type *) R_CLMA1_BASE) + #define R_CLMA2 ((R_CLMA0_Type *) R_CLMA2_BASE) + #define R_CLMA3 ((R_CLMA0_Type *) R_CLMA3_BASE) + #define R_MPU0 ((R_MPU0_Type *) R_MPU0_BASE) + #define R_MPU1 ((R_MPU0_Type *) R_MPU1_BASE) + #define R_MPU2 ((R_MPU0_Type *) R_MPU2_BASE) + #define R_MPU3 ((R_MPU3_Type *) R_MPU3_BASE) + #define R_MPU4 ((R_MPU3_Type *) R_MPU4_BASE) + #define R_MPU6 ((R_MPU0_Type *) R_MPU6_BASE) + #define R_SYSRAM_CTL ((R_SYSRAM_CTL_Type *) R_SYSRAM_CTL_BASE) + #define R_SHOSTIF_CFG ((R_SHOSTIF_CFG_Type *) R_SHOSTIF_CFG_BASE) + #define R_PHOSTIF_CFG ((R_PHOSTIF_CFG_Type *) R_PHOSTIF_CFG_BASE) + #define R_RWP_S ((R_RWP_S_Type *) R_RWP_S_BASE) + #define R_MPU7 ((R_MPU3_Type *) R_MPU7_BASE) + #define R_MPU8 ((R_MPU3_Type *) R_MPU8_BASE) + #define R_MTU ((R_MTU_Type *) R_MTU_BASE) + #define R_MTU3 ((R_MTU3_Type *) R_MTU3_BASE) + #define R_MTU4 ((R_MTU4_Type *) R_MTU4_BASE) + #define R_MTU_NF ((R_MTU_NF_Type *) R_MTU_NF_BASE) + #define R_MTU0 ((R_MTU0_Type *) R_MTU0_BASE) + #define R_MTU1 ((R_MTU1_Type *) R_MTU1_BASE) + #define R_MTU2 ((R_MTU2_Type *) R_MTU2_BASE) + #define R_MTU8 ((R_MTU8_Type *) R_MTU8_BASE) + #define R_MTU6 ((R_MTU6_Type *) R_MTU6_BASE) + #define R_MTU7 ((R_MTU7_Type *) R_MTU7_BASE) + #define R_MTU5 ((R_MTU5_Type *) R_MTU5_BASE) + #define R_GPT0 ((R_GPT0_Type *) R_GPT0_BASE) + #define R_GPT1 ((R_GPT0_Type *) R_GPT1_BASE) + #define R_GPT2 ((R_GPT0_Type *) R_GPT2_BASE) + #define R_GPT3 ((R_GPT0_Type *) R_GPT3_BASE) + #define R_GPT4 ((R_GPT0_Type *) R_GPT4_BASE) + #define R_GPT5 ((R_GPT0_Type *) R_GPT5_BASE) + #define R_GPT6 ((R_GPT0_Type *) R_GPT6_BASE) + #define R_TFU ((R_TFU_Type *) R_TFU_BASE) + #define R_ADC120 ((R_ADC121_Type *) R_ADC120_BASE) + #define R_POE3 ((R_POE3_Type *) R_POE3_BASE) + #define R_POEG0 ((R_POEG0_Type *) R_POEG0_BASE) + #define R_DSMIF0 ((R_DSMIF0_Type *) R_DSMIF0_BASE) + #define R_DSMIF1 ((R_DSMIF0_Type *) R_DSMIF1_BASE) + #define R_GSC ((R_GSC_Type *) R_GSC_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + +/* ========================================= End of section using anonymous unions ========================================= */ + #if defined(__CC_ARM) + #pragma pop + #elif defined(__ICCARM__) + +/* leave anonymous unions enabled */ + #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #elif defined(__GNUC__) + +/* anonymous unions are enabled by default */ + #elif defined(__TMS470__) + +/* anonymous unions are enabled by default */ + #elif defined(__TASKING__) + #pragma warning restore + #elif defined(__CSMC__) + +/* anonymous unions are enabled by default */ + #endif + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Cluster Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_clusters + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ CFDC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NCFG ========================================================== */ + #define R_CANFD_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ + #define R_CANFD_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ + #define R_CANFD_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ + #define R_CANFD_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ + #define R_CANFD_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ + #define R_CANFD_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ +/* ========================================================== CTR ========================================================== */ + #define R_CANFD_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ + #define R_CANFD_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ + #define R_CANFD_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ + #define R_CANFD_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ + #define R_CANFD_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ + #define R_CANFD_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ + #define R_CANFD_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ + #define R_CANFD_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ + #define R_CANFD_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ + #define R_CANFD_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ + #define R_CANFD_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ + #define R_CANFD_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ + #define R_CANFD_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ + #define R_CANFD_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ + #define R_CANFD_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ + #define R_CANFD_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ + #define R_CANFD_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ + #define R_CANFD_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ + #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ + #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ + #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ + #define R_CANFD_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ +/* ========================================================== STS ========================================================== */ + #define R_CANFD_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ + #define R_CANFD_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ + #define R_CANFD_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ + #define R_CANFD_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ + #define R_CANFD_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ + #define R_CANFD_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ + #define R_CANFD_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ + #define R_CANFD_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ + #define R_CANFD_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ + #define R_CANFD_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ + #define R_CANFD_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ + #define R_CANFD_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ +/* ========================================================= ERFL ========================================================== */ + #define R_CANFD_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ + #define R_CANFD_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ + #define R_CANFD_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ + #define R_CANFD_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ + #define R_CANFD_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ + #define R_CANFD_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ + #define R_CANFD_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ + #define R_CANFD_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ + #define R_CANFD_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ + #define R_CANFD_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ + #define R_CANFD_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ + #define R_CANFD_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ + #define R_CANFD_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ + #define R_CANFD_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ + #define R_CANFD_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ + #define R_CANFD_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ + #define R_CANFD_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDC2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCFG ========================================================== */ + #define R_CANFD_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ + #define R_CANFD_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ + #define R_CANFD_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ + #define R_CANFD_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ + #define R_CANFD_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCFG ========================================================= */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ + #define R_CANFD_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ + #define R_CANFD_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ + #define R_CANFD_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ + #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ + #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ + #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ + #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ + #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ + #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ + #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ + #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ + #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ + #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ + #define R_CANFD_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ + #define R_CANFD_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ + #define R_CANFD_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ + #define R_CANFD_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ + #define R_CANFD_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ + #define R_CANFD_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ + #define R_CANFD_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ +/* ========================================================= FDCRC ========================================================= */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ + #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (25UL) /*!< SCNT (Bit 25) */ + #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0x1e000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ +/* ========================================================= BLCT ========================================================== */ + #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ + #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ + #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ +/* ========================================================= BLSTS ========================================================= */ + #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ + #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ + +/* =========================================================================================================================== */ +/* ================ CFDGAFL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ + #define R_CANFD_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ + #define R_CANFD_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ + #define R_CANFD_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ + #define R_CANFD_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ +/* =========================================================== M =========================================================== */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ + #define R_CANFD_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ + #define R_CANFD_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ + #define R_CANFD_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ + #define R_CANFD_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ +/* ========================================================== P0 =========================================================== */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ + #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ + #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ + #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ + #define R_CANFD_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ + #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================== P1 =========================================================== */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Pos (0UL) /*!< RMDB_LL (Bit 0) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LL_Msk (0xffUL) /*!< RMDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Pos (8UL) /*!< RMDB_LH (Bit 8) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_LH_Msk (0xff00UL) /*!< RMDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Pos (16UL) /*!< RMDB_HL (Bit 16) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HL_Msk (0xff0000UL) /*!< RMDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Pos (24UL) /*!< RMDB_HH (Bit 24) */ + #define R_CANFD_CFDRM_DF_WD_RMDB_HH_Msk (0xff000000UL) /*!< RMDB_HH (Bitfield-Mask: 0xff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDRF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ + #define R_CANFD_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ + #define R_CANFD_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ + #define R_CANFD_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ + #define R_CANFD_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ + #define R_CANFD_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDSTS ========================================================= */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ + #define R_CANFD_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ + #define R_CANFD_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ + #define R_CANFD_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ + #define R_CANFD_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Pos (16UL) /*!< CFDRFPTR (Bit 16) */ + #define R_CANFD_CFDRF_FDSTS_CFDRFPTR_Msk (0xffff0000UL) /*!< CFDRFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Pos (0UL) /*!< RFDB_LL (Bit 0) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LL_Msk (0xffUL) /*!< RFDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Pos (8UL) /*!< RFDB_LH (Bit 8) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_LH_Msk (0xff00UL) /*!< RFDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Pos (16UL) /*!< RFDB_HL (Bit 16) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HL_Msk (0xff0000UL) /*!< RFDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Pos (24UL) /*!< RFDB_HH (Bit 24) */ + #define R_CANFD_CFDRF_DF_WD_RFDB_HH_Msk (0xff000000UL) /*!< RFDB_HH (Bitfield-Mask: 0xff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ + #define R_CANFD_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDCF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ + #define R_CANFD_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDCF_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDCF_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ + #define R_CANFD_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ + #define R_CANFD_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ + #define R_CANFD_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ + #define R_CANFD_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ +/* ======================================================== FDCSTS ========================================================= */ + #define R_CANFD_CFDCF_FDCSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ + #define R_CANFD_CFDCF_FDCSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDCSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ + #define R_CANFD_CFDCF_FDCSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDCSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ + #define R_CANFD_CFDCF_FDCSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCF_FDCSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ + #define R_CANFD_CFDCF_FDCSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCF_FDCSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ + #define R_CANFD_CFDCF_FDCSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Pos (0UL) /*!< CFDB_LL (Bit 0) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LL_Msk (0xffUL) /*!< CFDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Pos (8UL) /*!< CFDB_LH (Bit 8) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_LH_Msk (0xff00UL) /*!< CFDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Pos (16UL) /*!< CFDB_HL (Bit 16) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HL_Msk (0xff0000UL) /*!< CFDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Pos (24UL) /*!< CFDB_HH (Bit 24) */ + #define R_CANFD_CFDCF_DF_WD_CFDB_HH_Msk (0xff000000UL) /*!< CFDB_HH (Bitfield-Mask: 0xff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ + #define R_CANFD_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CFDTHL ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ACC0 ========================================================== */ + #define R_CANFD_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ + #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ + #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ + #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ + #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ +/* ========================================================= ACC1 ========================================================== */ + #define R_CANFD_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ + #define R_CANFD_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ + #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ CFDTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ID =========================================================== */ + #define R_CANFD_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ + #define R_CANFD_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDTM_ID_THLEN_Pos (29UL) /*!< THLEN (Bit 29) */ + #define R_CANFD_CFDTM_ID_THLEN_Msk (0x20000000UL) /*!< THLEN (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ + #define R_CANFD_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ + #define R_CANFD_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ +/* ========================================================== PTR ========================================================== */ + #define R_CANFD_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ + #define R_CANFD_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ +/* ========================================================= FDCTR ========================================================= */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ + #define R_CANFD_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ + #define R_CANFD_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ + #define R_CANFD_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ + #define R_CANFD_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ + #define R_CANFD_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DF_WD ========================================================= */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Pos (0UL) /*!< TMDB_LL (Bit 0) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LL_Msk (0xffUL) /*!< TMDB_LL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Pos (8UL) /*!< TMDB_LH (Bit 8) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_LH_Msk (0xff00UL) /*!< TMDB_LH (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Pos (16UL) /*!< TMDB_HL (Bit 16) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HL_Msk (0xff0000UL) /*!< TMDB_HL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Pos (24UL) /*!< TMDB_HH (Bit 24) */ + #define R_CANFD_CFDTM_DF_WD_TMDB_HH_Msk (0xff000000UL) /*!< TMDB_HH (Bitfield-Mask: 0xff) */ +/* ========================================================== DF =========================================================== */ + #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ + #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ CM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_CMT_UNT_CM_CR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_CMT_UNT_CM_CR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_CMT_UNT_CM_CR_CMIE_Pos (6UL) /*!< CMIE (Bit 6) */ + #define R_CMT_UNT_CM_CR_CMIE_Msk (0x40UL) /*!< CMIE (Bitfield-Mask: 0x01) */ +/* ========================================================== CNT ========================================================== */ +/* ========================================================== COR ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ UNT ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMSTR0 ========================================================= */ + #define R_CMT_UNT_CMSTR0_STR0_Pos (0UL) /*!< STR0 (Bit 0) */ + #define R_CMT_UNT_CMSTR0_STR0_Msk (0x1UL) /*!< STR0 (Bitfield-Mask: 0x01) */ + #define R_CMT_UNT_CMSTR0_STR1_Pos (1UL) /*!< STR1 (Bit 1) */ + #define R_CMT_UNT_CMSTR0_STR1_Msk (0x2UL) /*!< STR1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SAR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_IIC0_SAR_L_SVA0_Pos (0UL) /*!< SVA0 (Bit 0) */ + #define R_IIC0_SAR_L_SVA0_Msk (0x1UL) /*!< SVA0 (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_L_SVA_Pos (1UL) /*!< SVA (Bit 1) */ + #define R_IIC0_SAR_L_SVA_Msk (0xfeUL) /*!< SVA (Bitfield-Mask: 0x7f) */ +/* =========================================================== U =========================================================== */ + #define R_IIC0_SAR_U_FS_Pos (0UL) /*!< FS (Bit 0) */ + #define R_IIC0_SAR_U_FS_Msk (0x1UL) /*!< FS (Bitfield-Mask: 0x01) */ + #define R_IIC0_SAR_U_SVA_Pos (1UL) /*!< SVA (Bit 1) */ + #define R_IIC0_SAR_U_SVA_Msk (0x6UL) /*!< SVA (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ N ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SA =========================================================== */ +/* ========================================================== DA =========================================================== */ +/* ========================================================== TB =========================================================== */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CRSA ========================================================== */ +/* ========================================================= CRDA ========================================================== */ +/* ========================================================= CRTB ========================================================== */ +/* ======================================================== CHSTAT ========================================================= */ + #define R_DMAC0_GRP_CH_CHSTAT_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_DMAC0_GRP_CH_CHSTAT_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_RQST_Pos (1UL) /*!< RQST (Bit 1) */ + #define R_DMAC0_GRP_CH_CHSTAT_RQST_Msk (0x2UL) /*!< RQST (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_TACT_Pos (2UL) /*!< TACT (Bit 2) */ + #define R_DMAC0_GRP_CH_CHSTAT_TACT_Msk (0x4UL) /*!< TACT (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_SUS_Pos (3UL) /*!< SUS (Bit 3) */ + #define R_DMAC0_GRP_CH_CHSTAT_SUS_Msk (0x8UL) /*!< SUS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_ER_Pos (4UL) /*!< ER (Bit 4) */ + #define R_DMAC0_GRP_CH_CHSTAT_ER_Msk (0x10UL) /*!< ER (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_END_Pos (5UL) /*!< END (Bit 5) */ + #define R_DMAC0_GRP_CH_CHSTAT_END_Msk (0x20UL) /*!< END (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_TC_Pos (6UL) /*!< TC (Bit 6) */ + #define R_DMAC0_GRP_CH_CHSTAT_TC_Msk (0x40UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_SR_Pos (7UL) /*!< SR (Bit 7) */ + #define R_DMAC0_GRP_CH_CHSTAT_SR_Msk (0x80UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_DL_Pos (8UL) /*!< DL (Bit 8) */ + #define R_DMAC0_GRP_CH_CHSTAT_DL_Msk (0x100UL) /*!< DL (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_DW_Pos (9UL) /*!< DW (Bit 9) */ + #define R_DMAC0_GRP_CH_CHSTAT_DW_Msk (0x200UL) /*!< DW (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_DER_Pos (10UL) /*!< DER (Bit 10) */ + #define R_DMAC0_GRP_CH_CHSTAT_DER_Msk (0x400UL) /*!< DER (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_MODE_Pos (11UL) /*!< MODE (Bit 11) */ + #define R_DMAC0_GRP_CH_CHSTAT_MODE_Msk (0x800UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHSTAT_INTM_Pos (16UL) /*!< INTM (Bit 16) */ + #define R_DMAC0_GRP_CH_CHSTAT_INTM_Msk (0x10000UL) /*!< INTM (Bitfield-Mask: 0x01) */ +/* ======================================================== CHCTRL ========================================================= */ + #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Pos (0UL) /*!< SETEN (Bit 0) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETEN_Msk (0x1UL) /*!< SETEN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Pos (1UL) /*!< CLREN (Bit 1) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREN_Msk (0x2UL) /*!< CLREN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_STG_Pos (2UL) /*!< STG (Bit 2) */ + #define R_DMAC0_GRP_CH_CHCTRL_STG_Msk (0x4UL) /*!< STG (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Pos (3UL) /*!< SWRST (Bit 3) */ + #define R_DMAC0_GRP_CH_CHCTRL_SWRST_Msk (0x8UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Pos (4UL) /*!< CLRRQ (Bit 4) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRRQ_Msk (0x10UL) /*!< CLRRQ (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Pos (5UL) /*!< CLREND (Bit 5) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLREND_Msk (0x20UL) /*!< CLREND (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Pos (6UL) /*!< CLRTC (Bit 6) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRTC_Msk (0x40UL) /*!< CLRTC (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Pos (8UL) /*!< SETSUS (Bit 8) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETSUS_Msk (0x100UL) /*!< SETSUS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Pos (9UL) /*!< CLRSUS (Bit 9) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRSUS_Msk (0x200UL) /*!< CLRSUS (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Pos (16UL) /*!< SETINTM (Bit 16) */ + #define R_DMAC0_GRP_CH_CHCTRL_SETINTM_Msk (0x10000UL) /*!< SETINTM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Pos (17UL) /*!< CLRINTM (Bit 17) */ + #define R_DMAC0_GRP_CH_CHCTRL_CLRINTM_Msk (0x20000UL) /*!< CLRINTM (Bitfield-Mask: 0x01) */ +/* ========================================================= CHCFG ========================================================= */ + #define R_DMAC0_GRP_CH_CHCFG_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_DMAC0_GRP_CH_CHCFG_SEL_Msk (0x7UL) /*!< SEL (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHCFG_REQD_Pos (3UL) /*!< REQD (Bit 3) */ + #define R_DMAC0_GRP_CH_CHCFG_REQD_Msk (0x8UL) /*!< REQD (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_LOEN_Pos (4UL) /*!< LOEN (Bit 4) */ + #define R_DMAC0_GRP_CH_CHCFG_LOEN_Msk (0x10UL) /*!< LOEN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_HIEN_Pos (5UL) /*!< HIEN (Bit 5) */ + #define R_DMAC0_GRP_CH_CHCFG_HIEN_Msk (0x20UL) /*!< HIEN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_LVL_Pos (6UL) /*!< LVL (Bit 6) */ + #define R_DMAC0_GRP_CH_CHCFG_LVL_Msk (0x40UL) /*!< LVL (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_AM_Pos (8UL) /*!< AM (Bit 8) */ + #define R_DMAC0_GRP_CH_CHCFG_AM_Msk (0x700UL) /*!< AM (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHCFG_SDS_Pos (12UL) /*!< SDS (Bit 12) */ + #define R_DMAC0_GRP_CH_CHCFG_SDS_Msk (0xf000UL) /*!< SDS (Bitfield-Mask: 0x0f) */ + #define R_DMAC0_GRP_CH_CHCFG_DDS_Pos (16UL) /*!< DDS (Bit 16) */ + #define R_DMAC0_GRP_CH_CHCFG_DDS_Msk (0xf0000UL) /*!< DDS (Bitfield-Mask: 0x0f) */ + #define R_DMAC0_GRP_CH_CHCFG_SAD_Pos (20UL) /*!< SAD (Bit 20) */ + #define R_DMAC0_GRP_CH_CHCFG_SAD_Msk (0x100000UL) /*!< SAD (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_DAD_Pos (21UL) /*!< DAD (Bit 21) */ + #define R_DMAC0_GRP_CH_CHCFG_DAD_Msk (0x200000UL) /*!< DAD (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_TM_Pos (22UL) /*!< TM (Bit 22) */ + #define R_DMAC0_GRP_CH_CHCFG_TM_Msk (0x400000UL) /*!< TM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_DEM_Pos (24UL) /*!< DEM (Bit 24) */ + #define R_DMAC0_GRP_CH_CHCFG_DEM_Msk (0x1000000UL) /*!< DEM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_TCM_Pos (25UL) /*!< TCM (Bit 25) */ + #define R_DMAC0_GRP_CH_CHCFG_TCM_Msk (0x2000000UL) /*!< TCM (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_SBE_Pos (27UL) /*!< SBE (Bit 27) */ + #define R_DMAC0_GRP_CH_CHCFG_SBE_Msk (0x8000000UL) /*!< SBE (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_RSEL_Pos (28UL) /*!< RSEL (Bit 28) */ + #define R_DMAC0_GRP_CH_CHCFG_RSEL_Msk (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_RSW_Pos (29UL) /*!< RSW (Bit 29) */ + #define R_DMAC0_GRP_CH_CHCFG_RSW_Msk (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_REN_Pos (30UL) /*!< REN (Bit 30) */ + #define R_DMAC0_GRP_CH_CHCFG_REN_Msk (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_CH_CHCFG_DMS_Pos (31UL) /*!< DMS (Bit 31) */ + #define R_DMAC0_GRP_CH_CHCFG_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */ +/* ======================================================== CHITVL ========================================================= */ + #define R_DMAC0_GRP_CH_CHITVL_ITVL_Pos (0UL) /*!< ITVL (Bit 0) */ + #define R_DMAC0_GRP_CH_CHITVL_ITVL_Msk (0xffffUL) /*!< ITVL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CHEXT ========================================================= */ + #define R_DMAC0_GRP_CH_CHEXT_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_DMAC0_GRP_CH_CHEXT_SPR_Msk (0x7UL) /*!< SPR (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHEXT_SCA_Pos (4UL) /*!< SCA (Bit 4) */ + #define R_DMAC0_GRP_CH_CHEXT_SCA_Msk (0xf0UL) /*!< SCA (Bitfield-Mask: 0x0f) */ + #define R_DMAC0_GRP_CH_CHEXT_DPR_Pos (8UL) /*!< DPR (Bit 8) */ + #define R_DMAC0_GRP_CH_CHEXT_DPR_Msk (0x700UL) /*!< DPR (Bitfield-Mask: 0x07) */ + #define R_DMAC0_GRP_CH_CHEXT_DCA_Pos (12UL) /*!< DCA (Bit 12) */ + #define R_DMAC0_GRP_CH_CHEXT_DCA_Msk (0xf000UL) /*!< DCA (Bitfield-Mask: 0x0f) */ +/* ========================================================= NXLA ========================================================== */ +/* ========================================================= CRLA ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ GRP ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DCTRL ========================================================= */ + #define R_DMAC0_GRP_DCTRL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_DMAC0_GRP_DCTRL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DCTRL_LVINT_Pos (1UL) /*!< LVINT (Bit 1) */ + #define R_DMAC0_GRP_DCTRL_LVINT_Msk (0x2UL) /*!< LVINT (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_EN ======================================================== */ + #define R_DMAC0_GRP_DSTAT_EN_EN00_Pos (0UL) /*!< EN00 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_EN_EN00_Msk (0x1UL) /*!< EN00 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN01_Pos (1UL) /*!< EN01 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_EN_EN01_Msk (0x2UL) /*!< EN01 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN02_Pos (2UL) /*!< EN02 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_EN_EN02_Msk (0x4UL) /*!< EN02 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN03_Pos (3UL) /*!< EN03 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_EN_EN03_Msk (0x8UL) /*!< EN03 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN04_Pos (4UL) /*!< EN04 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_EN_EN04_Msk (0x10UL) /*!< EN04 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN05_Pos (5UL) /*!< EN05 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_EN_EN05_Msk (0x20UL) /*!< EN05 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN06_Pos (6UL) /*!< EN06 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_EN_EN06_Msk (0x40UL) /*!< EN06 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_EN_EN07_Pos (7UL) /*!< EN07 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_EN_EN07_Msk (0x80UL) /*!< EN07 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_ER ======================================================== */ + #define R_DMAC0_GRP_DSTAT_ER_ER00_Pos (0UL) /*!< ER00 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_ER_ER00_Msk (0x1UL) /*!< ER00 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER01_Pos (1UL) /*!< ER01 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_ER_ER01_Msk (0x2UL) /*!< ER01 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER02_Pos (2UL) /*!< ER02 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_ER_ER02_Msk (0x4UL) /*!< ER02 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER03_Pos (3UL) /*!< ER03 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_ER_ER03_Msk (0x8UL) /*!< ER03 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER04_Pos (4UL) /*!< ER04 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_ER_ER04_Msk (0x10UL) /*!< ER04 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER05_Pos (5UL) /*!< ER05 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_ER_ER05_Msk (0x20UL) /*!< ER05 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER06_Pos (6UL) /*!< ER06 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_ER_ER06_Msk (0x40UL) /*!< ER06 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_ER_ER07_Pos (7UL) /*!< ER07 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_ER_ER07_Msk (0x80UL) /*!< ER07 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_END ======================================================= */ + #define R_DMAC0_GRP_DSTAT_END_END00_Pos (0UL) /*!< END00 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_END_END00_Msk (0x1UL) /*!< END00 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END01_Pos (1UL) /*!< END01 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_END_END01_Msk (0x2UL) /*!< END01 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END02_Pos (2UL) /*!< END02 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_END_END02_Msk (0x4UL) /*!< END02 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END03_Pos (3UL) /*!< END03 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_END_END03_Msk (0x8UL) /*!< END03 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END04_Pos (4UL) /*!< END04 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_END_END04_Msk (0x10UL) /*!< END04 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END05_Pos (5UL) /*!< END05 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_END_END05_Msk (0x20UL) /*!< END05 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END06_Pos (6UL) /*!< END06 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_END_END06_Msk (0x40UL) /*!< END06 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_END_END07_Pos (7UL) /*!< END07 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_END_END07_Msk (0x80UL) /*!< END07 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_SUS ======================================================= */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS00_Pos (0UL) /*!< SUS00 (Bit 0) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS00_Msk (0x1UL) /*!< SUS00 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS01_Pos (1UL) /*!< SUS01 (Bit 1) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS01_Msk (0x2UL) /*!< SUS01 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS02_Pos (2UL) /*!< SUS02 (Bit 2) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS02_Msk (0x4UL) /*!< SUS02 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS03_Pos (3UL) /*!< SUS03 (Bit 3) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS03_Msk (0x8UL) /*!< SUS03 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS04_Pos (4UL) /*!< SUS04 (Bit 4) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS04_Msk (0x10UL) /*!< SUS04 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS05_Pos (5UL) /*!< SUS05 (Bit 5) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS05_Msk (0x20UL) /*!< SUS05 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS06_Pos (6UL) /*!< SUS06 (Bit 6) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS06_Msk (0x40UL) /*!< SUS06 (Bitfield-Mask: 0x01) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS07_Pos (7UL) /*!< SUS07 (Bit 7) */ + #define R_DMAC0_GRP_DSTAT_SUS_SUS07_Msk (0x80UL) /*!< SUS07 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ DRCTL ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== L =========================================================== */ + #define R_PORT_NSR_DRCTL_L_DRV0_Pos (0UL) /*!< DRV0 (Bit 0) */ + #define R_PORT_NSR_DRCTL_L_DRV0_Msk (0x3UL) /*!< DRV0 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD0_Pos (2UL) /*!< PUD0 (Bit 2) */ + #define R_PORT_NSR_DRCTL_L_PUD0_Msk (0xcUL) /*!< PUD0 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT0_Pos (4UL) /*!< SMT0 (Bit 4) */ + #define R_PORT_NSR_DRCTL_L_SMT0_Msk (0x10UL) /*!< SMT0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR0_Pos (5UL) /*!< SR0 (Bit 5) */ + #define R_PORT_NSR_DRCTL_L_SR0_Msk (0x20UL) /*!< SR0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_DRV1_Pos (8UL) /*!< DRV1 (Bit 8) */ + #define R_PORT_NSR_DRCTL_L_DRV1_Msk (0x300UL) /*!< DRV1 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD1_Pos (10UL) /*!< PUD1 (Bit 10) */ + #define R_PORT_NSR_DRCTL_L_PUD1_Msk (0xc00UL) /*!< PUD1 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT1_Pos (12UL) /*!< SMT1 (Bit 12) */ + #define R_PORT_NSR_DRCTL_L_SMT1_Msk (0x1000UL) /*!< SMT1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR1_Pos (13UL) /*!< SR1 (Bit 13) */ + #define R_PORT_NSR_DRCTL_L_SR1_Msk (0x2000UL) /*!< SR1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_DRV2_Pos (16UL) /*!< DRV2 (Bit 16) */ + #define R_PORT_NSR_DRCTL_L_DRV2_Msk (0x30000UL) /*!< DRV2 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD2_Pos (18UL) /*!< PUD2 (Bit 18) */ + #define R_PORT_NSR_DRCTL_L_PUD2_Msk (0xc0000UL) /*!< PUD2 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT2_Pos (20UL) /*!< SMT2 (Bit 20) */ + #define R_PORT_NSR_DRCTL_L_SMT2_Msk (0x100000UL) /*!< SMT2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR2_Pos (21UL) /*!< SR2 (Bit 21) */ + #define R_PORT_NSR_DRCTL_L_SR2_Msk (0x200000UL) /*!< SR2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_DRV3_Pos (24UL) /*!< DRV3 (Bit 24) */ + #define R_PORT_NSR_DRCTL_L_DRV3_Msk (0x3000000UL) /*!< DRV3 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_PUD3_Pos (26UL) /*!< PUD3 (Bit 26) */ + #define R_PORT_NSR_DRCTL_L_PUD3_Msk (0xc000000UL) /*!< PUD3 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_L_SMT3_Pos (28UL) /*!< SMT3 (Bit 28) */ + #define R_PORT_NSR_DRCTL_L_SMT3_Msk (0x10000000UL) /*!< SMT3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_L_SR3_Pos (29UL) /*!< SR3 (Bit 29) */ + #define R_PORT_NSR_DRCTL_L_SR3_Msk (0x20000000UL) /*!< SR3 (Bitfield-Mask: 0x01) */ +/* =========================================================== H =========================================================== */ + #define R_PORT_NSR_DRCTL_H_DRV4_Pos (0UL) /*!< DRV4 (Bit 0) */ + #define R_PORT_NSR_DRCTL_H_DRV4_Msk (0x3UL) /*!< DRV4 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD4_Pos (2UL) /*!< PUD4 (Bit 2) */ + #define R_PORT_NSR_DRCTL_H_PUD4_Msk (0xcUL) /*!< PUD4 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT4_Pos (4UL) /*!< SMT4 (Bit 4) */ + #define R_PORT_NSR_DRCTL_H_SMT4_Msk (0x10UL) /*!< SMT4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR4_Pos (5UL) /*!< SR4 (Bit 5) */ + #define R_PORT_NSR_DRCTL_H_SR4_Msk (0x20UL) /*!< SR4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_DRV5_Pos (8UL) /*!< DRV5 (Bit 8) */ + #define R_PORT_NSR_DRCTL_H_DRV5_Msk (0x300UL) /*!< DRV5 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD5_Pos (10UL) /*!< PUD5 (Bit 10) */ + #define R_PORT_NSR_DRCTL_H_PUD5_Msk (0xc00UL) /*!< PUD5 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT5_Pos (12UL) /*!< SMT5 (Bit 12) */ + #define R_PORT_NSR_DRCTL_H_SMT5_Msk (0x1000UL) /*!< SMT5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR5_Pos (13UL) /*!< SR5 (Bit 13) */ + #define R_PORT_NSR_DRCTL_H_SR5_Msk (0x2000UL) /*!< SR5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_DRV6_Pos (16UL) /*!< DRV6 (Bit 16) */ + #define R_PORT_NSR_DRCTL_H_DRV6_Msk (0x30000UL) /*!< DRV6 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD6_Pos (18UL) /*!< PUD6 (Bit 18) */ + #define R_PORT_NSR_DRCTL_H_PUD6_Msk (0xc0000UL) /*!< PUD6 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT6_Pos (20UL) /*!< SMT6 (Bit 20) */ + #define R_PORT_NSR_DRCTL_H_SMT6_Msk (0x100000UL) /*!< SMT6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR6_Pos (21UL) /*!< SR6 (Bit 21) */ + #define R_PORT_NSR_DRCTL_H_SR6_Msk (0x200000UL) /*!< SR6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_DRV7_Pos (24UL) /*!< DRV7 (Bit 24) */ + #define R_PORT_NSR_DRCTL_H_DRV7_Msk (0x3000000UL) /*!< DRV7 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_PUD7_Pos (26UL) /*!< PUD7 (Bit 26) */ + #define R_PORT_NSR_DRCTL_H_PUD7_Msk (0xc000000UL) /*!< PUD7 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_DRCTL_H_SMT7_Pos (28UL) /*!< SMT7 (Bit 28) */ + #define R_PORT_NSR_DRCTL_H_SMT7_Msk (0x10000000UL) /*!< SMT7 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_DRCTL_H_SR7_Pos (29UL) /*!< SR7 (Bit 29) */ + #define R_PORT_NSR_DRCTL_H_SR7_Msk (0x20000000UL) /*!< SR7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ ELC_PDBF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== BY =========================================================== */ + #define R_PORT_NSR_ELC_PDBF_BY_PB0_Pos (0UL) /*!< PB0 (Bit 0) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB0_Msk (0x1UL) /*!< PB0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB1_Pos (1UL) /*!< PB1 (Bit 1) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB1_Msk (0x2UL) /*!< PB1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB2_Pos (2UL) /*!< PB2 (Bit 2) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB2_Msk (0x4UL) /*!< PB2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB3_Pos (3UL) /*!< PB3 (Bit 3) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB3_Msk (0x8UL) /*!< PB3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB4_Pos (4UL) /*!< PB4 (Bit 4) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB4_Msk (0x10UL) /*!< PB4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB5_Pos (5UL) /*!< PB5 (Bit 5) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB5_Msk (0x20UL) /*!< PB5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB6_Pos (6UL) /*!< PB6 (Bit 6) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB6_Msk (0x40UL) /*!< PB6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB7_Pos (7UL) /*!< PB7 (Bit 7) */ + #define R_PORT_NSR_ELC_PDBF_BY_PB7_Msk (0x80UL) /*!< PB7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SWTM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== EN =========================================================== */ + #define R_ETHSW_PTP_SWTM_EN_OUTEN_Pos (0UL) /*!< OUTEN (Bit 0) */ + #define R_ETHSW_PTP_SWTM_EN_OUTEN_Msk (0x1UL) /*!< OUTEN (Bitfield-Mask: 0x01) */ +/* ========================================================= STSEC ========================================================= */ + #define R_ETHSW_PTP_SWTM_STSEC_STSEC_Pos (0UL) /*!< STSEC (Bit 0) */ + #define R_ETHSW_PTP_SWTM_STSEC_STSEC_Msk (0xffffffffUL) /*!< STSEC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= STNS ========================================================== */ + #define R_ETHSW_PTP_SWTM_STNS_STNS_Pos (0UL) /*!< STNS (Bit 0) */ + #define R_ETHSW_PTP_SWTM_STNS_STNS_Msk (0xffffffffUL) /*!< STNS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= PSEC ========================================================== */ + #define R_ETHSW_PTP_SWTM_PSEC_PSEC_Pos (0UL) /*!< PSEC (Bit 0) */ + #define R_ETHSW_PTP_SWTM_PSEC_PSEC_Msk (0xffffffffUL) /*!< PSEC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== PNS ========================================================== */ + #define R_ETHSW_PTP_SWTM_PNS_PNS_Pos (0UL) /*!< PNS (Bit 0) */ + #define R_ETHSW_PTP_SWTM_PNS_PNS_Msk (0xffffffffUL) /*!< PNS (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== WTH ========================================================== */ + #define R_ETHSW_PTP_SWTM_WTH_WIDTH_Pos (0UL) /*!< WIDTH (Bit 0) */ + #define R_ETHSW_PTP_SWTM_WTH_WIDTH_Msk (0xffffUL) /*!< WIDTH (Bitfield-Mask: 0xffff) */ +/* ========================================================= MAXP ========================================================== */ + #define R_ETHSW_PTP_SWTM_MAXP_MAXP_Pos (0UL) /*!< MAXP (Bit 0) */ + #define R_ETHSW_PTP_SWTM_MAXP_MAXP_Msk (0xffffffffUL) /*!< MAXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LATSEC ========================================================= */ + #define R_ETHSW_PTP_SWTM_LATSEC_LATSEC_Pos (0UL) /*!< LATSEC (Bit 0) */ + #define R_ETHSW_PTP_SWTM_LATSEC_LATSEC_Msk (0xffffffffUL) /*!< LATSEC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= LATNS ========================================================= */ + #define R_ETHSW_PTP_SWTM_LATNS_LATNS_Pos (0UL) /*!< LATNS (Bit 0) */ + #define R_ETHSW_PTP_SWTM_LATNS_LATNS_Msk (0xffffffffUL) /*!< LATNS (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ MGMT_ADDR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== lo =========================================================== */ + #define R_ETHSW_MGMT_ADDR_lo_BPDU_DST_Pos (0UL) /*!< BPDU_DST (Bit 0) */ + #define R_ETHSW_MGMT_ADDR_lo_BPDU_DST_Msk (0xffffffffUL) /*!< BPDU_DST (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== hi =========================================================== */ + #define R_ETHSW_MGMT_ADDR_hi_BPDU_DST_Pos (0UL) /*!< BPDU_DST (Bit 0) */ + #define R_ETHSW_MGMT_ADDR_hi_BPDU_DST_Msk (0xffffUL) /*!< BPDU_DST (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_MGMT_ADDR_hi_MASK_Pos (16UL) /*!< MASK (Bit 16) */ + #define R_ETHSW_MGMT_ADDR_hi_MASK_Msk (0xff0000UL) /*!< MASK (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ FMMU ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== L_START_ADR ====================================================== */ + #define R_ESC_FMMU_L_START_ADR_LSTAADR_Pos (0UL) /*!< LSTAADR (Bit 0) */ + #define R_ESC_FMMU_L_START_ADR_LSTAADR_Msk (0xffffffffUL) /*!< LSTAADR (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== LEN ========================================================== */ + #define R_ESC_FMMU_LEN_FMMULEN_Pos (0UL) /*!< FMMULEN (Bit 0) */ + #define R_ESC_FMMU_LEN_FMMULEN_Msk (0xffffUL) /*!< FMMULEN (Bitfield-Mask: 0xffff) */ +/* ====================================================== L_START_BIT ====================================================== */ + #define R_ESC_FMMU_L_START_BIT_LSTABIT_Pos (0UL) /*!< LSTABIT (Bit 0) */ + #define R_ESC_FMMU_L_START_BIT_LSTABIT_Msk (0x7UL) /*!< LSTABIT (Bitfield-Mask: 0x07) */ +/* ====================================================== L_STOP_BIT ======================================================= */ + #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Pos (0UL) /*!< LSTPBIT (Bit 0) */ + #define R_ESC_FMMU_L_STOP_BIT_LSTPBIT_Msk (0x7UL) /*!< LSTPBIT (Bitfield-Mask: 0x07) */ +/* ====================================================== P_START_ADR ====================================================== */ + #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Pos (0UL) /*!< PHYSTAADR (Bit 0) */ + #define R_ESC_FMMU_P_START_ADR_PHYSTAADR_Msk (0xffffUL) /*!< PHYSTAADR (Bitfield-Mask: 0xffff) */ +/* ====================================================== P_START_BIT ====================================================== */ + #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Pos (0UL) /*!< PHYSTABIT (Bit 0) */ + #define R_ESC_FMMU_P_START_BIT_PHYSTABIT_Msk (0x7UL) /*!< PHYSTABIT (Bitfield-Mask: 0x07) */ +/* ========================================================= TYPE ========================================================== */ + #define R_ESC_FMMU_TYPE_READ_Pos (0UL) /*!< READ (Bit 0) */ + #define R_ESC_FMMU_TYPE_READ_Msk (0x1UL) /*!< READ (Bitfield-Mask: 0x01) */ + #define R_ESC_FMMU_TYPE_WRITE_Pos (1UL) /*!< WRITE (Bit 1) */ + #define R_ESC_FMMU_TYPE_WRITE_Msk (0x2UL) /*!< WRITE (Bitfield-Mask: 0x01) */ +/* ========================================================== ACT ========================================================== */ + #define R_ESC_FMMU_ACT_ACTIVATE_Pos (0UL) /*!< ACTIVATE (Bit 0) */ + #define R_ESC_FMMU_ACT_ACTIVATE_Msk (0x1UL) /*!< ACTIVATE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ SM ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== P_START_ADR ====================================================== */ + #define R_ESC_SM_P_START_ADR_SMSTAADDR_Pos (0UL) /*!< SMSTAADDR (Bit 0) */ + #define R_ESC_SM_P_START_ADR_SMSTAADDR_Msk (0xffffUL) /*!< SMSTAADDR (Bitfield-Mask: 0xffff) */ +/* ========================================================== LEN ========================================================== */ + #define R_ESC_SM_LEN_SMLEN_Pos (0UL) /*!< SMLEN (Bit 0) */ + #define R_ESC_SM_LEN_SMLEN_Msk (0xffffUL) /*!< SMLEN (Bitfield-Mask: 0xffff) */ +/* ======================================================== CONTROL ======================================================== */ + #define R_ESC_SM_CONTROL_OPEMODE_Pos (0UL) /*!< OPEMODE (Bit 0) */ + #define R_ESC_SM_CONTROL_OPEMODE_Msk (0x3UL) /*!< OPEMODE (Bitfield-Mask: 0x03) */ + #define R_ESC_SM_CONTROL_DIR_Pos (2UL) /*!< DIR (Bit 2) */ + #define R_ESC_SM_CONTROL_DIR_Msk (0xcUL) /*!< DIR (Bitfield-Mask: 0x03) */ + #define R_ESC_SM_CONTROL_IRQECAT_Pos (4UL) /*!< IRQECAT (Bit 4) */ + #define R_ESC_SM_CONTROL_IRQECAT_Msk (0x10UL) /*!< IRQECAT (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_CONTROL_IRQPDI_Pos (5UL) /*!< IRQPDI (Bit 5) */ + #define R_ESC_SM_CONTROL_IRQPDI_Msk (0x20UL) /*!< IRQPDI (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_CONTROL_WDTRGEN_Pos (6UL) /*!< WDTRGEN (Bit 6) */ + #define R_ESC_SM_CONTROL_WDTRGEN_Msk (0x40UL) /*!< WDTRGEN (Bitfield-Mask: 0x01) */ +/* ======================================================== STATUS ========================================================= */ + #define R_ESC_SM_STATUS_INTWR_Pos (0UL) /*!< INTWR (Bit 0) */ + #define R_ESC_SM_STATUS_INTWR_Msk (0x1UL) /*!< INTWR (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_INTRD_Pos (1UL) /*!< INTRD (Bit 1) */ + #define R_ESC_SM_STATUS_INTRD_Msk (0x2UL) /*!< INTRD (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_MAILBOX_Pos (3UL) /*!< MAILBOX (Bit 3) */ + #define R_ESC_SM_STATUS_MAILBOX_Msk (0x8UL) /*!< MAILBOX (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_BUFFERED_Pos (4UL) /*!< BUFFERED (Bit 4) */ + #define R_ESC_SM_STATUS_BUFFERED_Msk (0x30UL) /*!< BUFFERED (Bitfield-Mask: 0x03) */ + #define R_ESC_SM_STATUS_RDBUF_Pos (6UL) /*!< RDBUF (Bit 6) */ + #define R_ESC_SM_STATUS_RDBUF_Msk (0x40UL) /*!< RDBUF (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_STATUS_WRBUF_Pos (7UL) /*!< WRBUF (Bit 7) */ + #define R_ESC_SM_STATUS_WRBUF_Msk (0x80UL) /*!< WRBUF (Bitfield-Mask: 0x01) */ +/* ========================================================== ACT ========================================================== */ + #define R_ESC_SM_ACT_SMEN_Pos (0UL) /*!< SMEN (Bit 0) */ + #define R_ESC_SM_ACT_SMEN_Msk (0x1UL) /*!< SMEN (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_ACT_REPEATREQ_Pos (1UL) /*!< REPEATREQ (Bit 1) */ + #define R_ESC_SM_ACT_REPEATREQ_Msk (0x2UL) /*!< REPEATREQ (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_ACT_LATCHECAT_Pos (6UL) /*!< LATCHECAT (Bit 6) */ + #define R_ESC_SM_ACT_LATCHECAT_Msk (0x40UL) /*!< LATCHECAT (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_ACT_LATCHPDI_Pos (7UL) /*!< LATCHPDI (Bit 7) */ + #define R_ESC_SM_ACT_LATCHPDI_Msk (0x80UL) /*!< LATCHPDI (Bitfield-Mask: 0x01) */ +/* ======================================================= PDI_CONT ======================================================== */ + #define R_ESC_SM_PDI_CONT_DEACTIVE_Pos (0UL) /*!< DEACTIVE (Bit 0) */ + #define R_ESC_SM_PDI_CONT_DEACTIVE_Msk (0x1UL) /*!< DEACTIVE (Bitfield-Mask: 0x01) */ + #define R_ESC_SM_PDI_CONT_REPEATACK_Pos (1UL) /*!< REPEATACK (Bit 1) */ + #define R_ESC_SM_PDI_CONT_REPEATACK_Msk (0x2UL) /*!< REPEATACK (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ PIPE_TR ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== E =========================================================== */ + #define R_USBF_PIPE_TR_E_TRCLR_Pos (8UL) /*!< TRCLR (Bit 8) */ + #define R_USBF_PIPE_TR_E_TRCLR_Msk (0x100UL) /*!< TRCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_TR_E_TRENB_Pos (9UL) /*!< TRENB (Bit 9) */ + #define R_USBF_PIPE_TR_E_TRENB_Msk (0x200UL) /*!< TRENB (Bitfield-Mask: 0x01) */ +/* =========================================================== N =========================================================== */ + #define R_USBF_PIPE_TR_N_TRNCNT_Pos (0UL) /*!< TRNCNT (Bit 0) */ + #define R_USBF_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /*!< TRNCNT (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ N ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SA =========================================================== */ + #define R_USBF_CHa_N_SA_SAWD_Pos (0UL) /*!< SAWD (Bit 0) */ + #define R_USBF_CHa_N_SA_SAWD_Msk (0xffffffffUL) /*!< SAWD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== DA =========================================================== */ + #define R_USBF_CHa_N_DA_DA_Pos (0UL) /*!< DA (Bit 0) */ + #define R_USBF_CHa_N_DA_DA_Msk (0xffffffffUL) /*!< DA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================== TB =========================================================== */ + #define R_USBF_CHa_N_TB_TB_Pos (0UL) /*!< TB (Bit 0) */ + #define R_USBF_CHa_N_TB_TB_Msk (0xffffffffUL) /*!< TB (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CHa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CRSA ========================================================== */ + #define R_USBF_CHa_CRSA_CRSA_Pos (0UL) /*!< CRSA (Bit 0) */ + #define R_USBF_CHa_CRSA_CRSA_Msk (0xffffffffUL) /*!< CRSA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CRDA ========================================================== */ + #define R_USBF_CHa_CRDA_CRDA_Pos (0UL) /*!< CRDA (Bit 0) */ + #define R_USBF_CHa_CRDA_CRDA_Msk (0xffffffffUL) /*!< CRDA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CRTB ========================================================== */ + #define R_USBF_CHa_CRTB_CRTB_Pos (0UL) /*!< CRTB (Bit 0) */ + #define R_USBF_CHa_CRTB_CRTB_Msk (0xffffffffUL) /*!< CRTB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CHSTAT ========================================================= */ + #define R_USBF_CHa_CHSTAT_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_USBF_CHa_CHSTAT_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_RQST_Pos (1UL) /*!< RQST (Bit 1) */ + #define R_USBF_CHa_CHSTAT_RQST_Msk (0x2UL) /*!< RQST (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_TACT_Pos (2UL) /*!< TACT (Bit 2) */ + #define R_USBF_CHa_CHSTAT_TACT_Msk (0x4UL) /*!< TACT (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_SUS_Pos (3UL) /*!< SUS (Bit 3) */ + #define R_USBF_CHa_CHSTAT_SUS_Msk (0x8UL) /*!< SUS (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_ER_Pos (4UL) /*!< ER (Bit 4) */ + #define R_USBF_CHa_CHSTAT_ER_Msk (0x10UL) /*!< ER (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_END_Pos (5UL) /*!< END (Bit 5) */ + #define R_USBF_CHa_CHSTAT_END_Msk (0x20UL) /*!< END (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_TC_Pos (6UL) /*!< TC (Bit 6) */ + #define R_USBF_CHa_CHSTAT_TC_Msk (0x40UL) /*!< TC (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_SR_Pos (7UL) /*!< SR (Bit 7) */ + #define R_USBF_CHa_CHSTAT_SR_Msk (0x80UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DL_Pos (8UL) /*!< DL (Bit 8) */ + #define R_USBF_CHa_CHSTAT_DL_Msk (0x100UL) /*!< DL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DW_Pos (9UL) /*!< DW (Bit 9) */ + #define R_USBF_CHa_CHSTAT_DW_Msk (0x200UL) /*!< DW (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DER_Pos (10UL) /*!< DER (Bit 10) */ + #define R_USBF_CHa_CHSTAT_DER_Msk (0x400UL) /*!< DER (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_MODE_Pos (11UL) /*!< MODE (Bit 11) */ + #define R_USBF_CHa_CHSTAT_MODE_Msk (0x800UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_INTM_Pos (16UL) /*!< INTM (Bit 16) */ + #define R_USBF_CHa_CHSTAT_INTM_Msk (0x10000UL) /*!< INTM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DMARQM_Pos (17UL) /*!< DMARQM (Bit 17) */ + #define R_USBF_CHa_CHSTAT_DMARQM_Msk (0x20000UL) /*!< DMARQM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_SWPRQ_Pos (18UL) /*!< SWPRQ (Bit 18) */ + #define R_USBF_CHa_CHSTAT_SWPRQ_Msk (0x40000UL) /*!< SWPRQ (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHSTAT_DNUM_Pos (24UL) /*!< DNUM (Bit 24) */ + #define R_USBF_CHa_CHSTAT_DNUM_Msk (0xff000000UL) /*!< DNUM (Bitfield-Mask: 0xff) */ +/* ======================================================== CHCTRL ========================================================= */ + #define R_USBF_CHa_CHCTRL_SETEN_Pos (0UL) /*!< SETEN (Bit 0) */ + #define R_USBF_CHa_CHCTRL_SETEN_Msk (0x1UL) /*!< SETEN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLREN_Pos (1UL) /*!< CLREN (Bit 1) */ + #define R_USBF_CHa_CHCTRL_CLREN_Msk (0x2UL) /*!< CLREN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_STG_Pos (2UL) /*!< STG (Bit 2) */ + #define R_USBF_CHa_CHCTRL_STG_Msk (0x4UL) /*!< STG (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SWRST_Pos (3UL) /*!< SWRST (Bit 3) */ + #define R_USBF_CHa_CHCTRL_SWRST_Msk (0x8UL) /*!< SWRST (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRRQ_Pos (4UL) /*!< CLRRQ (Bit 4) */ + #define R_USBF_CHa_CHCTRL_CLRRQ_Msk (0x10UL) /*!< CLRRQ (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLREND_Pos (5UL) /*!< CLREND (Bit 5) */ + #define R_USBF_CHa_CHCTRL_CLREND_Msk (0x20UL) /*!< CLREND (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRTC_Pos (6UL) /*!< CLRTC (Bit 6) */ + #define R_USBF_CHa_CHCTRL_CLRTC_Msk (0x40UL) /*!< CLRTC (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRDER_Pos (7UL) /*!< CLRDER (Bit 7) */ + #define R_USBF_CHa_CHCTRL_CLRDER_Msk (0x80UL) /*!< CLRDER (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETSUS_Pos (8UL) /*!< SETSUS (Bit 8) */ + #define R_USBF_CHa_CHCTRL_SETSUS_Msk (0x100UL) /*!< SETSUS (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRSUS_Pos (9UL) /*!< CLRSUS (Bit 9) */ + #define R_USBF_CHa_CHCTRL_CLRSUS_Msk (0x200UL) /*!< CLRSUS (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETREN_Pos (12UL) /*!< SETREN (Bit 12) */ + #define R_USBF_CHa_CHCTRL_SETREN_Msk (0x1000UL) /*!< SETREN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Pos (14UL) /*!< SETSSWPRQ (Bit 14) */ + #define R_USBF_CHa_CHCTRL_SETSSWPRQ_Msk (0x4000UL) /*!< SETSSWPRQ (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETINTM_Pos (16UL) /*!< SETINTM (Bit 16) */ + #define R_USBF_CHa_CHCTRL_SETINTM_Msk (0x10000UL) /*!< SETINTM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRINTM_Pos (17UL) /*!< CLRINTM (Bit 17) */ + #define R_USBF_CHa_CHCTRL_CLRINTM_Msk (0x20000UL) /*!< CLRINTM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_SETDMARQM_Pos (18UL) /*!< SETDMARQM (Bit 18) */ + #define R_USBF_CHa_CHCTRL_SETDMARQM_Msk (0x40000UL) /*!< SETDMARQM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCTRL_CLRDMARQM_Pos (19UL) /*!< CLRDMARQM (Bit 19) */ + #define R_USBF_CHa_CHCTRL_CLRDMARQM_Msk (0x80000UL) /*!< CLRDMARQM (Bitfield-Mask: 0x01) */ +/* ========================================================= CHCFG ========================================================= */ + #define R_USBF_CHa_CHCFG_SEL_Pos (0UL) /*!< SEL (Bit 0) */ + #define R_USBF_CHa_CHCFG_SEL_Msk (0x1UL) /*!< SEL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_REQD_Pos (3UL) /*!< REQD (Bit 3) */ + #define R_USBF_CHa_CHCFG_REQD_Msk (0x8UL) /*!< REQD (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_LOEN_Pos (4UL) /*!< LOEN (Bit 4) */ + #define R_USBF_CHa_CHCFG_LOEN_Msk (0x10UL) /*!< LOEN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_HIEN_Pos (5UL) /*!< HIEN (Bit 5) */ + #define R_USBF_CHa_CHCFG_HIEN_Msk (0x20UL) /*!< HIEN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_LVL_Pos (6UL) /*!< LVL (Bit 6) */ + #define R_USBF_CHa_CHCFG_LVL_Msk (0x40UL) /*!< LVL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_AM_Pos (8UL) /*!< AM (Bit 8) */ + #define R_USBF_CHa_CHCFG_AM_Msk (0x700UL) /*!< AM (Bitfield-Mask: 0x07) */ + #define R_USBF_CHa_CHCFG_DRRP_Pos (11UL) /*!< DRRP (Bit 11) */ + #define R_USBF_CHa_CHCFG_DRRP_Msk (0x800UL) /*!< DRRP (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_SDS_Pos (12UL) /*!< SDS (Bit 12) */ + #define R_USBF_CHa_CHCFG_SDS_Msk (0xf000UL) /*!< SDS (Bitfield-Mask: 0x0f) */ + #define R_USBF_CHa_CHCFG_DDS_Pos (16UL) /*!< DDS (Bit 16) */ + #define R_USBF_CHa_CHCFG_DDS_Msk (0xf0000UL) /*!< DDS (Bitfield-Mask: 0x0f) */ + #define R_USBF_CHa_CHCFG_SAD_Pos (20UL) /*!< SAD (Bit 20) */ + #define R_USBF_CHa_CHCFG_SAD_Msk (0x100000UL) /*!< SAD (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DAD_Pos (21UL) /*!< DAD (Bit 21) */ + #define R_USBF_CHa_CHCFG_DAD_Msk (0x200000UL) /*!< DAD (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_TM_Pos (22UL) /*!< TM (Bit 22) */ + #define R_USBF_CHa_CHCFG_TM_Msk (0x400000UL) /*!< TM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_WONLY_Pos (23UL) /*!< WONLY (Bit 23) */ + #define R_USBF_CHa_CHCFG_WONLY_Msk (0x800000UL) /*!< WONLY (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DEM_Pos (24UL) /*!< DEM (Bit 24) */ + #define R_USBF_CHa_CHCFG_DEM_Msk (0x1000000UL) /*!< DEM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DIM_Pos (26UL) /*!< DIM (Bit 26) */ + #define R_USBF_CHa_CHCFG_DIM_Msk (0x4000000UL) /*!< DIM (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_SBE_Pos (27UL) /*!< SBE (Bit 27) */ + #define R_USBF_CHa_CHCFG_SBE_Msk (0x8000000UL) /*!< SBE (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_RSEL_Pos (28UL) /*!< RSEL (Bit 28) */ + #define R_USBF_CHa_CHCFG_RSEL_Msk (0x10000000UL) /*!< RSEL (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_RSW_Pos (29UL) /*!< RSW (Bit 29) */ + #define R_USBF_CHa_CHCFG_RSW_Msk (0x20000000UL) /*!< RSW (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_REN_Pos (30UL) /*!< REN (Bit 30) */ + #define R_USBF_CHa_CHCFG_REN_Msk (0x40000000UL) /*!< REN (Bitfield-Mask: 0x01) */ + #define R_USBF_CHa_CHCFG_DMS_Pos (31UL) /*!< DMS (Bit 31) */ + #define R_USBF_CHa_CHCFG_DMS_Msk (0x80000000UL) /*!< DMS (Bitfield-Mask: 0x01) */ +/* ======================================================== CHITVL ========================================================= */ + #define R_USBF_CHa_CHITVL_ITVL_Pos (0UL) /*!< ITVL (Bit 0) */ + #define R_USBF_CHa_CHITVL_ITVL_Msk (0xffffUL) /*!< ITVL (Bitfield-Mask: 0xffff) */ +/* ========================================================= CHEXT ========================================================= */ + #define R_USBF_CHa_CHEXT_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_USBF_CHa_CHEXT_SPR_Msk (0xfUL) /*!< SPR (Bitfield-Mask: 0x0f) */ + #define R_USBF_CHa_CHEXT_DPR_Pos (8UL) /*!< DPR (Bit 8) */ + #define R_USBF_CHa_CHEXT_DPR_Msk (0xf00UL) /*!< DPR (Bitfield-Mask: 0x0f) */ +/* ========================================================= NXLA ========================================================== */ + #define R_USBF_CHa_NXLA_NXLA_Pos (0UL) /*!< NXLA (Bit 0) */ + #define R_USBF_CHa_NXLA_NXLA_Msk (0xffffffffUL) /*!< NXLA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CRLA ========================================================== */ + #define R_USBF_CHa_CRLA_CRLA_Pos (0UL) /*!< CRLA (Bit 0) */ + #define R_USBF_CHa_CRLA_CRLA_Msk (0xffffffffUL) /*!< CRLA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CHb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SCNT ========================================================== */ + #define R_USBF_CHb_SCNT_SCNT_Pos (0UL) /*!< SCNT (Bit 0) */ + #define R_USBF_CHb_SCNT_SCNT_Msk (0xffffffffUL) /*!< SCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SSKP ========================================================== */ + #define R_USBF_CHb_SSKP_SSKP_Pos (0UL) /*!< SSKP (Bit 0) */ + #define R_USBF_CHb_SSKP_SSKP_Msk (0xffffffffUL) /*!< SSKP (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DCNT ========================================================== */ + #define R_USBF_CHb_DCNT_DCNT_Pos (0UL) /*!< DCNT (Bit 0) */ + #define R_USBF_CHb_DCNT_DCNT_Msk (0xffffffffUL) /*!< DCNT (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= DSKP ========================================================== */ + #define R_USBF_CHb_DSKP_DSKP_Pos (0UL) /*!< DSKP (Bit 0) */ + #define R_USBF_CHb_DSKP_DSKP_Msk (0xffffffffUL) /*!< DSKP (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMCFG0 ========================================================= */ + #define R_XSPI0_CSa_CMCFG0_FFMT_Pos (0UL) /*!< FFMT (Bit 0) */ + #define R_XSPI0_CSa_CMCFG0_FFMT_Msk (0x3UL) /*!< FFMT (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_CSa_CMCFG0_ADDSIZE_Msk (0xcUL) /*!< ADDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Pos (16UL) /*!< ADDRPEN (Bit 16) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPEN_Msk (0xff0000UL) /*!< ADDRPEN (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Pos (24UL) /*!< ADDRPCD (Bit 24) */ + #define R_XSPI0_CSa_CMCFG0_ADDRPCD_Msk (0xff000000UL) /*!< ADDRPCD (Bitfield-Mask: 0xff) */ +/* ======================================================== CMCFG1 ========================================================= */ + #define R_XSPI0_CSa_CMCFG1_RDCMD_Pos (0UL) /*!< RDCMD (Bit 0) */ + #define R_XSPI0_CSa_CMCFG1_RDCMD_Msk (0xffffUL) /*!< RDCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CSa_CMCFG1_RDLATE_Pos (16UL) /*!< RDLATE (Bit 16) */ + #define R_XSPI0_CSa_CMCFG1_RDLATE_Msk (0x1f0000UL) /*!< RDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CMCFG2 ========================================================= */ + #define R_XSPI0_CSa_CMCFG2_WRCMD_Pos (0UL) /*!< WRCMD (Bit 0) */ + #define R_XSPI0_CSa_CMCFG2_WRCMD_Msk (0xffffUL) /*!< WRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CSa_CMCFG2_WRLATE_Pos (16UL) /*!< WRLATE (Bit 16) */ + #define R_XSPI0_CSa_CMCFG2_WRLATE_Msk (0x1f0000UL) /*!< WRLATE (Bitfield-Mask: 0x1f) */ + +/* =========================================================================================================================== */ +/* ================ BUF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CDT ========================================================== */ + #define R_XSPI0_BUF_CDT_CMDSIZE_Pos (0UL) /*!< CMDSIZE (Bit 0) */ + #define R_XSPI0_BUF_CDT_CMDSIZE_Msk (0x3UL) /*!< CMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BUF_CDT_ADDSIZE_Pos (2UL) /*!< ADDSIZE (Bit 2) */ + #define R_XSPI0_BUF_CDT_ADDSIZE_Msk (0x1cUL) /*!< ADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_BUF_CDT_DATASIZE_Pos (5UL) /*!< DATASIZE (Bit 5) */ + #define R_XSPI0_BUF_CDT_DATASIZE_Msk (0x1e0UL) /*!< DATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_BUF_CDT_LATE_Pos (9UL) /*!< LATE (Bit 9) */ + #define R_XSPI0_BUF_CDT_LATE_Msk (0x3e00UL) /*!< LATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_BUF_CDT_TRTYPE_Pos (15UL) /*!< TRTYPE (Bit 15) */ + #define R_XSPI0_BUF_CDT_TRTYPE_Msk (0x8000UL) /*!< TRTYPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BUF_CDT_CMD_Pos (16UL) /*!< CMD (Bit 16) */ + #define R_XSPI0_BUF_CDT_CMD_Msk (0xffff0000UL) /*!< CMD (Bitfield-Mask: 0xffff) */ +/* ========================================================== CDA ========================================================== */ + #define R_XSPI0_BUF_CDA_ADD_Pos (0UL) /*!< ADD (Bit 0) */ + #define R_XSPI0_BUF_CDA_ADD_Msk (0xffffffffUL) /*!< ADD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD0 ========================================================== */ + #define R_XSPI0_BUF_CDD0_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_BUF_CDD0_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= CDD1 ========================================================== */ + #define R_XSPI0_BUF_CDD1_DATA_Pos (0UL) /*!< DATA (Bit 0) */ + #define R_XSPI0_BUF_CDD1_DATA_Msk (0xffffffffUL) /*!< DATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CCCTL0 ========================================================= */ + #define R_XSPI0_CSb_CCCTL0_CAEN_Pos (0UL) /*!< CAEN (Bit 0) */ + #define R_XSPI0_CSb_CCCTL0_CAEN_Msk (0x1UL) /*!< CAEN (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CSb_CCCTL0_CANOWR_Pos (1UL) /*!< CANOWR (Bit 1) */ + #define R_XSPI0_CSb_CCCTL0_CANOWR_Msk (0x2UL) /*!< CANOWR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CSb_CCCTL0_CAITV_Pos (8UL) /*!< CAITV (Bit 8) */ + #define R_XSPI0_CSb_CCCTL0_CAITV_Msk (0x1f00UL) /*!< CAITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Pos (16UL) /*!< CASFTSTA (Bit 16) */ + #define R_XSPI0_CSb_CCCTL0_CASFTSTA_Msk (0x1f0000UL) /*!< CASFTSTA (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CSb_CCCTL0_CASFTEND_Pos (24UL) /*!< CASFTEND (Bit 24) */ + #define R_XSPI0_CSb_CCCTL0_CASFTEND_Msk (0x1f000000UL) /*!< CASFTEND (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL1 ========================================================= */ + #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Pos (0UL) /*!< CACMDSIZE (Bit 0) */ + #define R_XSPI0_CSb_CCCTL1_CACMDSIZE_Msk (0x3UL) /*!< CACMDSIZE (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Pos (2UL) /*!< CAADDSIZE (Bit 2) */ + #define R_XSPI0_CSb_CCCTL1_CAADDSIZE_Msk (0x1cUL) /*!< CAADDSIZE (Bitfield-Mask: 0x07) */ + #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Pos (5UL) /*!< CADATASIZE (Bit 5) */ + #define R_XSPI0_CSb_CCCTL1_CADATASIZE_Msk (0x1e0UL) /*!< CADATASIZE (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Pos (16UL) /*!< CAWRLATE (Bit 16) */ + #define R_XSPI0_CSb_CCCTL1_CAWRLATE_Msk (0x1f0000UL) /*!< CAWRLATE (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CSb_CCCTL1_CARDLATE_Pos (24UL) /*!< CARDLATE (Bit 24) */ + #define R_XSPI0_CSb_CCCTL1_CARDLATE_Msk (0x1f000000UL) /*!< CARDLATE (Bitfield-Mask: 0x1f) */ +/* ======================================================== CCCTL2 ========================================================= */ + #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Pos (0UL) /*!< CAWRCMD (Bit 0) */ + #define R_XSPI0_CSb_CCCTL2_CAWRCMD_Msk (0xffffUL) /*!< CAWRCMD (Bitfield-Mask: 0xffff) */ + #define R_XSPI0_CSb_CCCTL2_CARDCMD_Pos (16UL) /*!< CARDCMD (Bit 16) */ + #define R_XSPI0_CSb_CCCTL2_CARDCMD_Msk (0xffff0000UL) /*!< CARDCMD (Bitfield-Mask: 0xffff) */ +/* ======================================================== CCCTL3 ========================================================= */ + #define R_XSPI0_CSb_CCCTL3_CAADD_Pos (0UL) /*!< CAADD (Bit 0) */ + #define R_XSPI0_CSb_CCCTL3_CAADD_Msk (0xffffffffUL) /*!< CAADD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL4 ========================================================= */ + #define R_XSPI0_CSb_CCCTL4_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL4_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL5 ========================================================= */ + #define R_XSPI0_CSb_CCCTL5_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL5_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL6 ========================================================= */ + #define R_XSPI0_CSb_CCCTL6_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL6_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CCCTL7 ========================================================= */ + #define R_XSPI0_CSb_CCCTL7_CADATA_Pos (0UL) /*!< CADATA (Bit 0) */ + #define R_XSPI0_CSb_CCCTL7_CADATA_Msk (0xffffffffUL) /*!< CADATA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ W ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= EC710CTL ======================================================== */ + #define R_SYSRAM0_W_EC710CTL_ECEMF_Pos (0UL) /*!< ECEMF (Bit 0) */ + #define R_SYSRAM0_W_EC710CTL_ECEMF_Msk (0x1UL) /*!< ECEMF (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER1F_Pos (1UL) /*!< ECER1F (Bit 1) */ + #define R_SYSRAM0_W_EC710CTL_ECER1F_Msk (0x2UL) /*!< ECER1F (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER2F_Pos (2UL) /*!< ECER2F (Bit 2) */ + #define R_SYSRAM0_W_EC710CTL_ECER2F_Msk (0x4UL) /*!< ECER2F (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Pos (3UL) /*!< EC1EDIC (Bit 3) */ + #define R_SYSRAM0_W_EC710CTL_EC1EDIC_Msk (0x8UL) /*!< EC1EDIC (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Pos (4UL) /*!< EC2EDIC (Bit 4) */ + #define R_SYSRAM0_W_EC710CTL_EC2EDIC_Msk (0x10UL) /*!< EC2EDIC (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EC1ECP_Pos (5UL) /*!< EC1ECP (Bit 5) */ + #define R_SYSRAM0_W_EC710CTL_EC1ECP_Msk (0x20UL) /*!< EC1ECP (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECERVF_Pos (6UL) /*!< ECERVF (Bit 6) */ + #define R_SYSRAM0_W_EC710CTL_ECERVF_Msk (0x40UL) /*!< ECERVF (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECTHM_Pos (7UL) /*!< ECTHM (Bit 7) */ + #define R_SYSRAM0_W_EC710CTL_ECTHM_Msk (0x80UL) /*!< ECTHM (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER1C_Pos (9UL) /*!< ECER1C (Bit 9) */ + #define R_SYSRAM0_W_EC710CTL_ECER1C_Msk (0x200UL) /*!< ECER1C (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECER2C_Pos (10UL) /*!< ECER2C (Bit 10) */ + #define R_SYSRAM0_W_EC710CTL_ECER2C_Msk (0x400UL) /*!< ECER2C (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_ECOVFF_Pos (11UL) /*!< ECOVFF (Bit 11) */ + #define R_SYSRAM0_W_EC710CTL_ECOVFF_Msk (0x800UL) /*!< ECOVFF (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710CTL_EMCA_Pos (14UL) /*!< EMCA (Bit 14) */ + #define R_SYSRAM0_W_EC710CTL_EMCA_Msk (0xc000UL) /*!< EMCA (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF0_Pos (16UL) /*!< ECEDF0 (Bit 16) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF0_Msk (0x30000UL) /*!< ECEDF0 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF1_Pos (18UL) /*!< ECEDF1 (Bit 18) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF1_Msk (0xc0000UL) /*!< ECEDF1 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF2_Pos (20UL) /*!< ECEDF2 (Bit 20) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF2_Msk (0x300000UL) /*!< ECEDF2 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF3_Pos (22UL) /*!< ECEDF3 (Bit 22) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF3_Msk (0xc00000UL) /*!< ECEDF3 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF4_Pos (24UL) /*!< ECEDF4 (Bit 24) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF4_Msk (0x3000000UL) /*!< ECEDF4 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF5_Pos (26UL) /*!< ECEDF5 (Bit 26) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF5_Msk (0xc000000UL) /*!< ECEDF5 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF6_Pos (28UL) /*!< ECEDF6 (Bit 28) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF6_Msk (0x30000000UL) /*!< ECEDF6 (Bitfield-Mask: 0x03) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF7_Pos (30UL) /*!< ECEDF7 (Bit 30) */ + #define R_SYSRAM0_W_EC710CTL_ECEDF7_Msk (0xc0000000UL) /*!< ECEDF7 (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TMC ======================================================== */ + #define R_SYSRAM0_W_EC710TMC_ECREIS_Pos (0UL) /*!< ECREIS (Bit 0) */ + #define R_SYSRAM0_W_EC710TMC_ECREIS_Msk (0x1UL) /*!< ECREIS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECDCS_Pos (1UL) /*!< ECDCS (Bit 1) */ + #define R_SYSRAM0_W_EC710TMC_ECDCS_Msk (0x2UL) /*!< ECDCS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECENS_Pos (2UL) /*!< ECENS (Bit 2) */ + #define R_SYSRAM0_W_EC710TMC_ECENS_Msk (0x4UL) /*!< ECENS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECREOS_Pos (3UL) /*!< ECREOS (Bit 3) */ + #define R_SYSRAM0_W_EC710TMC_ECREOS_Msk (0x8UL) /*!< ECREOS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECTRRS_Pos (4UL) /*!< ECTRRS (Bit 4) */ + #define R_SYSRAM0_W_EC710TMC_ECTRRS_Msk (0x10UL) /*!< ECTRRS (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ECTMCE_Pos (7UL) /*!< ECTMCE (Bit 7) */ + #define R_SYSRAM0_W_EC710TMC_ECTMCE_Msk (0x80UL) /*!< ECTMCE (Bitfield-Mask: 0x01) */ + #define R_SYSRAM0_W_EC710TMC_ETMA_Pos (14UL) /*!< ETMA (Bit 14) */ + #define R_SYSRAM0_W_EC710TMC_ETMA_Msk (0xc000UL) /*!< ETMA (Bitfield-Mask: 0x03) */ +/* ======================================================= EC710TRC ======================================================== */ + #define R_SYSRAM0_W_EC710TRC_ECERDB_Pos (0UL) /*!< ECERDB (Bit 0) */ + #define R_SYSRAM0_W_EC710TRC_ECERDB_Msk (0x7fUL) /*!< ECERDB (Bitfield-Mask: 0x7f) */ + #define R_SYSRAM0_W_EC710TRC_ECECRD_Pos (8UL) /*!< ECECRD (Bit 8) */ + #define R_SYSRAM0_W_EC710TRC_ECECRD_Msk (0x7f00UL) /*!< ECECRD (Bitfield-Mask: 0x7f) */ + #define R_SYSRAM0_W_EC710TRC_ECHORD_Pos (16UL) /*!< ECHORD (Bit 16) */ + #define R_SYSRAM0_W_EC710TRC_ECHORD_Msk (0x7f0000UL) /*!< ECHORD (Bitfield-Mask: 0x7f) */ + #define R_SYSRAM0_W_EC710TRC_ECSYND_Pos (24UL) /*!< ECSYND (Bit 24) */ + #define R_SYSRAM0_W_EC710TRC_ECSYND_Msk (0x7f000000UL) /*!< ECSYND (Bitfield-Mask: 0x7f) */ +/* ======================================================= EC710TED ======================================================== */ + #define R_SYSRAM0_W_EC710TED_ECEDB_Pos (0UL) /*!< ECEDB (Bit 0) */ + #define R_SYSRAM0_W_EC710TED_ECEDB_Msk (0xffffffffUL) /*!< ECEDB (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EC710EAD ======================================================== */ + #define R_SYSRAM0_W_EC710EAD_ECEAD_Pos (0UL) /*!< ECEAD (Bit 0) */ + #define R_SYSRAM0_W_EC710EAD_ECEAD_Msk (0x7fffUL) /*!< ECEAD (Bitfield-Mask: 0x7fff) */ + +/* =========================================================================================================================== */ +/* ================ RGN ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= STADD ========================================================= */ + #define R_MPU0_RGN_STADD_RDPR_Pos (0UL) /*!< RDPR (Bit 0) */ + #define R_MPU0_RGN_STADD_RDPR_Msk (0x1UL) /*!< RDPR (Bitfield-Mask: 0x01) */ + #define R_MPU0_RGN_STADD_WRPR_Pos (1UL) /*!< WRPR (Bit 1) */ + #define R_MPU0_RGN_STADD_WRPR_Msk (0x2UL) /*!< WRPR (Bitfield-Mask: 0x01) */ + #define R_MPU0_RGN_STADD_STADDR_Pos (10UL) /*!< STADDR (Bit 10) */ + #define R_MPU0_RGN_STADD_STADDR_Msk (0xfffffc00UL) /*!< STADDR (Bitfield-Mask: 0x3fffff) */ +/* ======================================================== ENDADD ========================================================= */ + #define R_MPU0_RGN_ENDADD_ENDADDR_Pos (10UL) /*!< ENDADDR (Bit 10) */ + #define R_MPU0_RGN_ENDADD_ENDADDR_Msk (0xfffffc00UL) /*!< ENDADDR (Bitfield-Mask: 0x3fffff) */ + +/* =========================================================================================================================== */ +/* ================ CH ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DSICR ========================================================= */ + #define R_DSMIF0_CH_DSICR_IOEL_Pos (0UL) /*!< IOEL (Bit 0) */ + #define R_DSMIF0_CH_DSICR_IOEL_Msk (0x1UL) /*!< IOEL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IOEH_Pos (1UL) /*!< IOEH (Bit 1) */ + #define R_DSMIF0_CH_DSICR_IOEH_Msk (0x2UL) /*!< IOEH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_ISE_Pos (2UL) /*!< ISE (Bit 2) */ + #define R_DSMIF0_CH_DSICR_ISE_Msk (0x4UL) /*!< ISE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSICR_IUE_Pos (3UL) /*!< IUE (Bit 3) */ + #define R_DSMIF0_CH_DSICR_IUE_Msk (0x8UL) /*!< IUE (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCMCCR ======================================================== */ + #define R_DSMIF0_CH_DSCMCCR_CKDIR_Pos (0UL) /*!< CKDIR (Bit 0) */ + #define R_DSMIF0_CH_DSCMCCR_CKDIR_Msk (0x1UL) /*!< CKDIR (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCMCCR_SEDGE_Pos (7UL) /*!< SEDGE (Bit 7) */ + #define R_DSMIF0_CH_DSCMCCR_SEDGE_Msk (0x80UL) /*!< SEDGE (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCMCCR_CKDIV_Pos (8UL) /*!< CKDIV (Bit 8) */ + #define R_DSMIF0_CH_DSCMCCR_CKDIV_Msk (0x3f00UL) /*!< CKDIV (Bitfield-Mask: 0x3f) */ +/* ======================================================== DSCMFCR ======================================================== */ + #define R_DSMIF0_CH_DSCMFCR_CMSINC_Pos (0UL) /*!< CMSINC (Bit 0) */ + #define R_DSMIF0_CH_DSCMFCR_CMSINC_Msk (0x3UL) /*!< CMSINC (Bitfield-Mask: 0x03) */ + #define R_DSMIF0_CH_DSCMFCR_CMDEC_Pos (8UL) /*!< CMDEC (Bit 8) */ + #define R_DSMIF0_CH_DSCMFCR_CMDEC_Msk (0xff00UL) /*!< CMDEC (Bitfield-Mask: 0xff) */ + #define R_DSMIF0_CH_DSCMFCR_CMSH_Pos (16UL) /*!< CMSH (Bit 16) */ + #define R_DSMIF0_CH_DSCMFCR_CMSH_Msk (0x1f0000UL) /*!< CMSH (Bitfield-Mask: 0x1f) */ +/* ======================================================= DSCMCTCR ======================================================== */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Pos (0UL) /*!< CTSELA (Bit 0) */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELA_Msk (0x7UL) /*!< CTSELA (Bitfield-Mask: 0x07) */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Pos (8UL) /*!< CTSELB (Bit 8) */ + #define R_DSMIF0_CH_DSCMCTCR_CTSELB_Msk (0x700UL) /*!< CTSELB (Bitfield-Mask: 0x07) */ + #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Pos (16UL) /*!< DITSEL (Bit 16) */ + #define R_DSMIF0_CH_DSCMCTCR_DITSEL_Msk (0x30000UL) /*!< DITSEL (Bitfield-Mask: 0x03) */ + #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Pos (23UL) /*!< DEDGE (Bit 23) */ + #define R_DSMIF0_CH_DSCMCTCR_DEDGE_Msk (0x800000UL) /*!< DEDGE (Bitfield-Mask: 0x01) */ +/* ======================================================== DSEDCR ========================================================= */ + #define R_DSMIF0_CH_DSEDCR_SDE_Pos (0UL) /*!< SDE (Bit 0) */ + #define R_DSMIF0_CH_DSEDCR_SDE_Msk (0x1UL) /*!< SDE (Bitfield-Mask: 0x01) */ +/* ======================================================== DSOCFCR ======================================================== */ + #define R_DSMIF0_CH_DSOCFCR_OCSINC_Pos (0UL) /*!< OCSINC (Bit 0) */ + #define R_DSMIF0_CH_DSOCFCR_OCSINC_Msk (0x3UL) /*!< OCSINC (Bitfield-Mask: 0x03) */ + #define R_DSMIF0_CH_DSOCFCR_OCDEC_Pos (8UL) /*!< OCDEC (Bit 8) */ + #define R_DSMIF0_CH_DSOCFCR_OCDEC_Msk (0xff00UL) /*!< OCDEC (Bitfield-Mask: 0xff) */ + #define R_DSMIF0_CH_DSOCFCR_OCSH_Pos (16UL) /*!< OCSH (Bit 16) */ + #define R_DSMIF0_CH_DSOCFCR_OCSH_Msk (0x1f0000UL) /*!< OCSH (Bitfield-Mask: 0x1f) */ +/* ======================================================== DSOCLTR ======================================================== */ + #define R_DSMIF0_CH_DSOCLTR_OCMPTBL_Pos (0UL) /*!< OCMPTBL (Bit 0) */ + #define R_DSMIF0_CH_DSOCLTR_OCMPTBL_Msk (0xffffUL) /*!< OCMPTBL (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSOCHTR ======================================================== */ + #define R_DSMIF0_CH_DSOCHTR_OCMPTBH_Pos (0UL) /*!< OCMPTBH (Bit 0) */ + #define R_DSMIF0_CH_DSOCHTR_OCMPTBH_Msk (0xffffUL) /*!< OCMPTBH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSSCTSR ======================================================== */ + #define R_DSMIF0_CH_DSSCTSR_SCNTL_Pos (0UL) /*!< SCNTL (Bit 0) */ + #define R_DSMIF0_CH_DSSCTSR_SCNTL_Msk (0x1fffUL) /*!< SCNTL (Bitfield-Mask: 0x1fff) */ + #define R_DSMIF0_CH_DSSCTSR_SCNTH_Pos (16UL) /*!< SCNTH (Bit 16) */ + #define R_DSMIF0_CH_DSSCTSR_SCNTH_Msk (0x1fff0000UL) /*!< SCNTH (Bitfield-Mask: 0x1fff) */ +/* ======================================================== DSODCR ========================================================= */ + #define R_DSMIF0_CH_DSODCR_ODEL_Pos (0UL) /*!< ODEL (Bit 0) */ + #define R_DSMIF0_CH_DSODCR_ODEL_Msk (0x1UL) /*!< ODEL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSODCR_ODEH_Pos (1UL) /*!< ODEH (Bit 1) */ + #define R_DSMIF0_CH_DSODCR_ODEH_Msk (0x2UL) /*!< ODEH (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCSTRTR ======================================================== */ + #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Pos (0UL) /*!< STRTRG (Bit 0) */ + #define R_DSMIF0_CH_DSCSTRTR_STRTRG_Msk (0x1UL) /*!< STRTRG (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCSTPTR ======================================================== */ + #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Pos (0UL) /*!< STPTRG (Bit 0) */ + #define R_DSMIF0_CH_DSCSTPTR_STPTRG_Msk (0x1UL) /*!< STPTRG (Bitfield-Mask: 0x01) */ +/* ========================================================= DSCDR ========================================================= */ + #define R_DSMIF0_CH_DSCDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_DSMIF0_CH_DSCDR_ADDR_Msk (0xffffUL) /*!< ADDR (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSCCDRA ======================================================== */ + #define R_DSMIF0_CH_DSCCDRA_CDRA_Pos (0UL) /*!< CDRA (Bit 0) */ + #define R_DSMIF0_CH_DSCCDRA_CDRA_Msk (0xffffUL) /*!< CDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSCCDRB ======================================================== */ + #define R_DSMIF0_CH_DSCCDRB_CDRB_Pos (0UL) /*!< CDRB (Bit 0) */ + #define R_DSMIF0_CH_DSCCDRB_CDRB_Msk (0xffffUL) /*!< CDRB (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSOCDR ========================================================= */ + #define R_DSMIF0_CH_DSOCDR_ODR_Pos (0UL) /*!< ODR (Bit 0) */ + #define R_DSMIF0_CH_DSOCDR_ODR_Msk (0xffffUL) /*!< ODR (Bitfield-Mask: 0xffff) */ +/* ======================================================== DSCOCDR ======================================================== */ + #define R_DSMIF0_CH_DSCOCDR_CODR_Pos (0UL) /*!< CODR (Bit 0) */ + #define R_DSMIF0_CH_DSCOCDR_CODR_Msk (0xffffUL) /*!< CODR (Bitfield-Mask: 0xffff) */ +/* ========================================================= DSCSR ========================================================= */ + #define R_DSMIF0_CH_DSCSR_DUF_Pos (0UL) /*!< DUF (Bit 0) */ + #define R_DSMIF0_CH_DSCSR_DUF_Msk (0x1UL) /*!< DUF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OCFL_Pos (1UL) /*!< OCFL (Bit 1) */ + #define R_DSMIF0_CH_DSCSR_OCFL_Msk (0x2UL) /*!< OCFL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_OCFH_Pos (2UL) /*!< OCFH (Bit 2) */ + #define R_DSMIF0_CH_DSCSR_OCFH_Msk (0x4UL) /*!< OCFH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_SCF_Pos (3UL) /*!< SCF (Bit 3) */ + #define R_DSMIF0_CH_DSCSR_SCF_Msk (0x8UL) /*!< SCF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSR_CHSTATE_Pos (16UL) /*!< CHSTATE (Bit 16) */ + #define R_DSMIF0_CH_DSCSR_CHSTATE_Msk (0x10000UL) /*!< CHSTATE (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCSCR ========================================================= */ + #define R_DSMIF0_CH_DSCSCR_CLRDUF_Pos (0UL) /*!< CLRDUF (Bit 0) */ + #define R_DSMIF0_CH_DSCSCR_CLRDUF_Msk (0x1UL) /*!< CLRDUF (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROCFL_Pos (1UL) /*!< CLROCFL (Bit 1) */ + #define R_DSMIF0_CH_DSCSCR_CLROCFL_Msk (0x2UL) /*!< CLROCFL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLROCFH_Pos (2UL) /*!< CLROCFH (Bit 2) */ + #define R_DSMIF0_CH_DSCSCR_CLROCFH_Msk (0x4UL) /*!< CLROCFH (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_CH_DSCSCR_CLRSCF_Pos (3UL) /*!< CLRSCF (Bit 3) */ + #define R_DSMIF0_CH_DSCSCR_CLRSCF_Msk (0x8UL) /*!< CLRSCF (Bitfield-Mask: 0x01) */ + +/** @} */ /* End of group PosMask_clusters */ + +/* =========================================================================================================================== */ +/* ================ Pos/Mask Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/** @addtogroup PosMask_peripherals + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ R_GPT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= GTWP ========================================================== */ + #define R_GPT7_GTWP_WP_Pos (0UL) /*!< WP (Bit 0) */ + #define R_GPT7_GTWP_WP_Msk (0x1UL) /*!< WP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_STRWP_Pos (1UL) /*!< STRWP (Bit 1) */ + #define R_GPT7_GTWP_STRWP_Msk (0x2UL) /*!< STRWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_STPWP_Pos (2UL) /*!< STPWP (Bit 2) */ + #define R_GPT7_GTWP_STPWP_Msk (0x4UL) /*!< STPWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_CLRWP_Pos (3UL) /*!< CLRWP (Bit 3) */ + #define R_GPT7_GTWP_CLRWP_Msk (0x8UL) /*!< CLRWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_CMNWP_Pos (4UL) /*!< CMNWP (Bit 4) */ + #define R_GPT7_GTWP_CMNWP_Msk (0x10UL) /*!< CMNWP (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTWP_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_GPT7_GTWP_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ +/* ========================================================= GTSTR ========================================================= */ + #define R_GPT7_GTSTR_CSTRT0_Pos (0UL) /*!< CSTRT0 (Bit 0) */ + #define R_GPT7_GTSTR_CSTRT0_Msk (0x1UL) /*!< CSTRT0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT1_Pos (1UL) /*!< CSTRT1 (Bit 1) */ + #define R_GPT7_GTSTR_CSTRT1_Msk (0x2UL) /*!< CSTRT1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT2_Pos (2UL) /*!< CSTRT2 (Bit 2) */ + #define R_GPT7_GTSTR_CSTRT2_Msk (0x4UL) /*!< CSTRT2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT3_Pos (3UL) /*!< CSTRT3 (Bit 3) */ + #define R_GPT7_GTSTR_CSTRT3_Msk (0x8UL) /*!< CSTRT3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT4_Pos (4UL) /*!< CSTRT4 (Bit 4) */ + #define R_GPT7_GTSTR_CSTRT4_Msk (0x10UL) /*!< CSTRT4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT5_Pos (5UL) /*!< CSTRT5 (Bit 5) */ + #define R_GPT7_GTSTR_CSTRT5_Msk (0x20UL) /*!< CSTRT5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTR_CSTRT6_Pos (6UL) /*!< CSTRT6 (Bit 6) */ + #define R_GPT7_GTSTR_CSTRT6_Msk (0x40UL) /*!< CSTRT6 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSTP ========================================================= */ + #define R_GPT7_GTSTP_CSTOP0_Pos (0UL) /*!< CSTOP0 (Bit 0) */ + #define R_GPT7_GTSTP_CSTOP0_Msk (0x1UL) /*!< CSTOP0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP1_Pos (1UL) /*!< CSTOP1 (Bit 1) */ + #define R_GPT7_GTSTP_CSTOP1_Msk (0x2UL) /*!< CSTOP1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP2_Pos (2UL) /*!< CSTOP2 (Bit 2) */ + #define R_GPT7_GTSTP_CSTOP2_Msk (0x4UL) /*!< CSTOP2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP3_Pos (3UL) /*!< CSTOP3 (Bit 3) */ + #define R_GPT7_GTSTP_CSTOP3_Msk (0x8UL) /*!< CSTOP3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP4_Pos (4UL) /*!< CSTOP4 (Bit 4) */ + #define R_GPT7_GTSTP_CSTOP4_Msk (0x10UL) /*!< CSTOP4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP5_Pos (5UL) /*!< CSTOP5 (Bit 5) */ + #define R_GPT7_GTSTP_CSTOP5_Msk (0x20UL) /*!< CSTOP5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSTP_CSTOP6_Pos (6UL) /*!< CSTOP6 (Bit 6) */ + #define R_GPT7_GTSTP_CSTOP6_Msk (0x40UL) /*!< CSTOP6 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCLR ========================================================= */ + #define R_GPT7_GTCLR_CCLR0_Pos (0UL) /*!< CCLR0 (Bit 0) */ + #define R_GPT7_GTCLR_CCLR0_Msk (0x1UL) /*!< CCLR0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR1_Pos (1UL) /*!< CCLR1 (Bit 1) */ + #define R_GPT7_GTCLR_CCLR1_Msk (0x2UL) /*!< CCLR1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR2_Pos (2UL) /*!< CCLR2 (Bit 2) */ + #define R_GPT7_GTCLR_CCLR2_Msk (0x4UL) /*!< CCLR2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR3_Pos (3UL) /*!< CCLR3 (Bit 3) */ + #define R_GPT7_GTCLR_CCLR3_Msk (0x8UL) /*!< CCLR3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR4_Pos (4UL) /*!< CCLR4 (Bit 4) */ + #define R_GPT7_GTCLR_CCLR4_Msk (0x10UL) /*!< CCLR4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR5_Pos (5UL) /*!< CCLR5 (Bit 5) */ + #define R_GPT7_GTCLR_CCLR5_Msk (0x20UL) /*!< CCLR5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCLR_CCLR6_Pos (6UL) /*!< CCLR6 (Bit 6) */ + #define R_GPT7_GTCLR_CCLR6_Msk (0x40UL) /*!< CCLR6 (Bitfield-Mask: 0x01) */ +/* ========================================================= GTSSR ========================================================= */ + #define R_GPT7_GTSSR_SSGTRGAFR_Pos (0UL) /*!< SSGTRGAFR (Bit 0) */ + #define R_GPT7_GTSSR_SSGTRGAFR_Msk (0x3UL) /*!< SSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSGTRGBFR_Pos (2UL) /*!< SSGTRGBFR (Bit 2) */ + #define R_GPT7_GTSSR_SSGTRGBFR_Msk (0xcUL) /*!< SSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSGTRGCFR_Pos (4UL) /*!< SSGTRGCFR (Bit 4) */ + #define R_GPT7_GTSSR_SSGTRGCFR_Msk (0x30UL) /*!< SSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSGTRGDFR_Pos (6UL) /*!< SSGTRGDFR (Bit 6) */ + #define R_GPT7_GTSSR_SSGTRGDFR_Msk (0xc0UL) /*!< SSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCARBHL_Pos (8UL) /*!< SSCARBHL (Bit 8) */ + #define R_GPT7_GTSSR_SSCARBHL_Msk (0x300UL) /*!< SSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCAFBHL_Pos (10UL) /*!< SSCAFBHL (Bit 10) */ + #define R_GPT7_GTSSR_SSCAFBHL_Msk (0xc00UL) /*!< SSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCBRAHL_Pos (12UL) /*!< SSCBRAHL (Bit 12) */ + #define R_GPT7_GTSSR_SSCBRAHL_Msk (0x3000UL) /*!< SSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSCBFAHL_Pos (14UL) /*!< SSCBFAHL (Bit 14) */ + #define R_GPT7_GTSSR_SSCBFAHL_Msk (0xc000UL) /*!< SSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSSR_SSELCA_Pos (16UL) /*!< SSELCA (Bit 16) */ + #define R_GPT7_GTSSR_SSELCA_Msk (0x10000UL) /*!< SSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCB_Pos (17UL) /*!< SSELCB (Bit 17) */ + #define R_GPT7_GTSSR_SSELCB_Msk (0x20000UL) /*!< SSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCC_Pos (18UL) /*!< SSELCC (Bit 18) */ + #define R_GPT7_GTSSR_SSELCC_Msk (0x40000UL) /*!< SSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCD_Pos (19UL) /*!< SSELCD (Bit 19) */ + #define R_GPT7_GTSSR_SSELCD_Msk (0x80000UL) /*!< SSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCE_Pos (20UL) /*!< SSELCE (Bit 20) */ + #define R_GPT7_GTSSR_SSELCE_Msk (0x100000UL) /*!< SSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCF_Pos (21UL) /*!< SSELCF (Bit 21) */ + #define R_GPT7_GTSSR_SSELCF_Msk (0x200000UL) /*!< SSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCG_Pos (22UL) /*!< SSELCG (Bit 22) */ + #define R_GPT7_GTSSR_SSELCG_Msk (0x400000UL) /*!< SSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_SSELCH_Pos (23UL) /*!< SSELCH (Bit 23) */ + #define R_GPT7_GTSSR_SSELCH_Msk (0x800000UL) /*!< SSELCH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSSR_CSTRT_Pos (31UL) /*!< CSTRT (Bit 31) */ + #define R_GPT7_GTSSR_CSTRT_Msk (0x80000000UL) /*!< CSTRT (Bitfield-Mask: 0x01) */ +/* ========================================================= GTPSR ========================================================= */ + #define R_GPT7_GTPSR_PSGTRGAFR_Pos (0UL) /*!< PSGTRGAFR (Bit 0) */ + #define R_GPT7_GTPSR_PSGTRGAFR_Msk (0x3UL) /*!< PSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSGTRGBFR_Pos (2UL) /*!< PSGTRGBFR (Bit 2) */ + #define R_GPT7_GTPSR_PSGTRGBFR_Msk (0xcUL) /*!< PSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSGTRGCFR_Pos (4UL) /*!< PSGTRGCFR (Bit 4) */ + #define R_GPT7_GTPSR_PSGTRGCFR_Msk (0x30UL) /*!< PSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSGTRGDFR_Pos (6UL) /*!< PSGTRGDFR (Bit 6) */ + #define R_GPT7_GTPSR_PSGTRGDFR_Msk (0xc0UL) /*!< PSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCARBHL_Pos (8UL) /*!< PSCARBHL (Bit 8) */ + #define R_GPT7_GTPSR_PSCARBHL_Msk (0x300UL) /*!< PSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCAFBHL_Pos (10UL) /*!< PSCAFBHL (Bit 10) */ + #define R_GPT7_GTPSR_PSCAFBHL_Msk (0xc00UL) /*!< PSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCBRAHL_Pos (12UL) /*!< PSCBRAHL (Bit 12) */ + #define R_GPT7_GTPSR_PSCBRAHL_Msk (0x3000UL) /*!< PSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSCBFAHL_Pos (14UL) /*!< PSCBFAHL (Bit 14) */ + #define R_GPT7_GTPSR_PSCBFAHL_Msk (0xc000UL) /*!< PSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTPSR_PSELCA_Pos (16UL) /*!< PSELCA (Bit 16) */ + #define R_GPT7_GTPSR_PSELCA_Msk (0x10000UL) /*!< PSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCB_Pos (17UL) /*!< PSELCB (Bit 17) */ + #define R_GPT7_GTPSR_PSELCB_Msk (0x20000UL) /*!< PSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCC_Pos (18UL) /*!< PSELCC (Bit 18) */ + #define R_GPT7_GTPSR_PSELCC_Msk (0x40000UL) /*!< PSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCD_Pos (19UL) /*!< PSELCD (Bit 19) */ + #define R_GPT7_GTPSR_PSELCD_Msk (0x80000UL) /*!< PSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCE_Pos (20UL) /*!< PSELCE (Bit 20) */ + #define R_GPT7_GTPSR_PSELCE_Msk (0x100000UL) /*!< PSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCF_Pos (21UL) /*!< PSELCF (Bit 21) */ + #define R_GPT7_GTPSR_PSELCF_Msk (0x200000UL) /*!< PSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCG_Pos (22UL) /*!< PSELCG (Bit 22) */ + #define R_GPT7_GTPSR_PSELCG_Msk (0x400000UL) /*!< PSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_PSELCH_Pos (23UL) /*!< PSELCH (Bit 23) */ + #define R_GPT7_GTPSR_PSELCH_Msk (0x800000UL) /*!< PSELCH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTPSR_CSTOP_Pos (31UL) /*!< CSTOP (Bit 31) */ + #define R_GPT7_GTPSR_CSTOP_Msk (0x80000000UL) /*!< CSTOP (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCSR ========================================================= */ + #define R_GPT7_GTCSR_CSGTRGAFR_Pos (0UL) /*!< CSGTRGAFR (Bit 0) */ + #define R_GPT7_GTCSR_CSGTRGAFR_Msk (0x3UL) /*!< CSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSGTRGBFR_Pos (2UL) /*!< CSGTRGBFR (Bit 2) */ + #define R_GPT7_GTCSR_CSGTRGBFR_Msk (0xcUL) /*!< CSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSGTRGCFR_Pos (4UL) /*!< CSGTRGCFR (Bit 4) */ + #define R_GPT7_GTCSR_CSGTRGCFR_Msk (0x30UL) /*!< CSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSGTRGDFR_Pos (6UL) /*!< CSGTRGDFR (Bit 6) */ + #define R_GPT7_GTCSR_CSGTRGDFR_Msk (0xc0UL) /*!< CSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCARBHL_Pos (8UL) /*!< CSCARBHL (Bit 8) */ + #define R_GPT7_GTCSR_CSCARBHL_Msk (0x300UL) /*!< CSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCAFBHL_Pos (10UL) /*!< CSCAFBHL (Bit 10) */ + #define R_GPT7_GTCSR_CSCAFBHL_Msk (0xc00UL) /*!< CSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCBRAHL_Pos (12UL) /*!< CSCBRAHL (Bit 12) */ + #define R_GPT7_GTCSR_CSCBRAHL_Msk (0x3000UL) /*!< CSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSCBFAHL_Pos (14UL) /*!< CSCBFAHL (Bit 14) */ + #define R_GPT7_GTCSR_CSCBFAHL_Msk (0xc000UL) /*!< CSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTCSR_CSELCA_Pos (16UL) /*!< CSELCA (Bit 16) */ + #define R_GPT7_GTCSR_CSELCA_Msk (0x10000UL) /*!< CSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCB_Pos (17UL) /*!< CSELCB (Bit 17) */ + #define R_GPT7_GTCSR_CSELCB_Msk (0x20000UL) /*!< CSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCC_Pos (18UL) /*!< CSELCC (Bit 18) */ + #define R_GPT7_GTCSR_CSELCC_Msk (0x40000UL) /*!< CSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCD_Pos (19UL) /*!< CSELCD (Bit 19) */ + #define R_GPT7_GTCSR_CSELCD_Msk (0x80000UL) /*!< CSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCE_Pos (20UL) /*!< CSELCE (Bit 20) */ + #define R_GPT7_GTCSR_CSELCE_Msk (0x100000UL) /*!< CSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCF_Pos (21UL) /*!< CSELCF (Bit 21) */ + #define R_GPT7_GTCSR_CSELCF_Msk (0x200000UL) /*!< CSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCG_Pos (22UL) /*!< CSELCG (Bit 22) */ + #define R_GPT7_GTCSR_CSELCG_Msk (0x400000UL) /*!< CSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CSELCH_Pos (23UL) /*!< CSELCH (Bit 23) */ + #define R_GPT7_GTCSR_CSELCH_Msk (0x800000UL) /*!< CSELCH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCSR_CCLR_Pos (31UL) /*!< CCLR (Bit 31) */ + #define R_GPT7_GTCSR_CCLR_Msk (0x80000000UL) /*!< CCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTUPSR ========================================================= */ + #define R_GPT7_GTUPSR_USGTRGAFR_Pos (0UL) /*!< USGTRGAFR (Bit 0) */ + #define R_GPT7_GTUPSR_USGTRGAFR_Msk (0x3UL) /*!< USGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USGTRGBFR_Pos (2UL) /*!< USGTRGBFR (Bit 2) */ + #define R_GPT7_GTUPSR_USGTRGBFR_Msk (0xcUL) /*!< USGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USGTRGCFR_Pos (4UL) /*!< USGTRGCFR (Bit 4) */ + #define R_GPT7_GTUPSR_USGTRGCFR_Msk (0x30UL) /*!< USGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USGTRGDFR_Pos (6UL) /*!< USGTRGDFR (Bit 6) */ + #define R_GPT7_GTUPSR_USGTRGDFR_Msk (0xc0UL) /*!< USGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCARBHL_Pos (8UL) /*!< USCARBHL (Bit 8) */ + #define R_GPT7_GTUPSR_USCARBHL_Msk (0x300UL) /*!< USCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCAFBHL_Pos (10UL) /*!< USCAFBHL (Bit 10) */ + #define R_GPT7_GTUPSR_USCAFBHL_Msk (0xc00UL) /*!< USCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCBRAHL_Pos (12UL) /*!< USCBRAHL (Bit 12) */ + #define R_GPT7_GTUPSR_USCBRAHL_Msk (0x3000UL) /*!< USCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USCBFAHL_Pos (14UL) /*!< USCBFAHL (Bit 14) */ + #define R_GPT7_GTUPSR_USCBFAHL_Msk (0xc000UL) /*!< USCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUPSR_USELCA_Pos (16UL) /*!< USELCA (Bit 16) */ + #define R_GPT7_GTUPSR_USELCA_Msk (0x10000UL) /*!< USELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCB_Pos (17UL) /*!< USELCB (Bit 17) */ + #define R_GPT7_GTUPSR_USELCB_Msk (0x20000UL) /*!< USELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCC_Pos (18UL) /*!< USELCC (Bit 18) */ + #define R_GPT7_GTUPSR_USELCC_Msk (0x40000UL) /*!< USELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCD_Pos (19UL) /*!< USELCD (Bit 19) */ + #define R_GPT7_GTUPSR_USELCD_Msk (0x80000UL) /*!< USELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCE_Pos (20UL) /*!< USELCE (Bit 20) */ + #define R_GPT7_GTUPSR_USELCE_Msk (0x100000UL) /*!< USELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCF_Pos (21UL) /*!< USELCF (Bit 21) */ + #define R_GPT7_GTUPSR_USELCF_Msk (0x200000UL) /*!< USELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCG_Pos (22UL) /*!< USELCG (Bit 22) */ + #define R_GPT7_GTUPSR_USELCG_Msk (0x400000UL) /*!< USELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUPSR_USELCH_Pos (23UL) /*!< USELCH (Bit 23) */ + #define R_GPT7_GTUPSR_USELCH_Msk (0x800000UL) /*!< USELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTDNSR ========================================================= */ + #define R_GPT7_GTDNSR_DSGTRGAFR_Pos (0UL) /*!< DSGTRGAFR (Bit 0) */ + #define R_GPT7_GTDNSR_DSGTRGAFR_Msk (0x3UL) /*!< DSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSGTRGBFR_Pos (2UL) /*!< DSGTRGBFR (Bit 2) */ + #define R_GPT7_GTDNSR_DSGTRGBFR_Msk (0xcUL) /*!< DSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSGTRGCFR_Pos (4UL) /*!< DSGTRGCFR (Bit 4) */ + #define R_GPT7_GTDNSR_DSGTRGCFR_Msk (0x30UL) /*!< DSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSGTRGDFR_Pos (6UL) /*!< DSGTRGDFR (Bit 6) */ + #define R_GPT7_GTDNSR_DSGTRGDFR_Msk (0xc0UL) /*!< DSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCARBHL_Pos (8UL) /*!< DSCARBHL (Bit 8) */ + #define R_GPT7_GTDNSR_DSCARBHL_Msk (0x300UL) /*!< DSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCAFBHL_Pos (10UL) /*!< DSCAFBHL (Bit 10) */ + #define R_GPT7_GTDNSR_DSCAFBHL_Msk (0xc00UL) /*!< DSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCBRAHL_Pos (12UL) /*!< DSCBRAHL (Bit 12) */ + #define R_GPT7_GTDNSR_DSCBRAHL_Msk (0x3000UL) /*!< DSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSCBFAHL_Pos (14UL) /*!< DSCBFAHL (Bit 14) */ + #define R_GPT7_GTDNSR_DSCBFAHL_Msk (0xc000UL) /*!< DSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTDNSR_DSELCA_Pos (16UL) /*!< DSELCA (Bit 16) */ + #define R_GPT7_GTDNSR_DSELCA_Msk (0x10000UL) /*!< DSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCB_Pos (17UL) /*!< DSELCB (Bit 17) */ + #define R_GPT7_GTDNSR_DSELCB_Msk (0x20000UL) /*!< DSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCC_Pos (18UL) /*!< DSELCC (Bit 18) */ + #define R_GPT7_GTDNSR_DSELCC_Msk (0x40000UL) /*!< DSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCD_Pos (19UL) /*!< DSELCD (Bit 19) */ + #define R_GPT7_GTDNSR_DSELCD_Msk (0x80000UL) /*!< DSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCE_Pos (20UL) /*!< DSELCE (Bit 20) */ + #define R_GPT7_GTDNSR_DSELCE_Msk (0x100000UL) /*!< DSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCF_Pos (21UL) /*!< DSELCF (Bit 21) */ + #define R_GPT7_GTDNSR_DSELCF_Msk (0x200000UL) /*!< DSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCG_Pos (22UL) /*!< DSELCG (Bit 22) */ + #define R_GPT7_GTDNSR_DSELCG_Msk (0x400000UL) /*!< DSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDNSR_DSELCH_Pos (23UL) /*!< DSELCH (Bit 23) */ + #define R_GPT7_GTDNSR_DSELCH_Msk (0x800000UL) /*!< DSELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICASR ======================================================== */ + #define R_GPT7_GTICASR_ASGTRGAFR_Pos (0UL) /*!< ASGTRGAFR (Bit 0) */ + #define R_GPT7_GTICASR_ASGTRGAFR_Msk (0x3UL) /*!< ASGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASGTRGBFR_Pos (2UL) /*!< ASGTRGBFR (Bit 2) */ + #define R_GPT7_GTICASR_ASGTRGBFR_Msk (0xcUL) /*!< ASGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASGTRGCFR_Pos (4UL) /*!< ASGTRGCFR (Bit 4) */ + #define R_GPT7_GTICASR_ASGTRGCFR_Msk (0x30UL) /*!< ASGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASGTRGDFR_Pos (6UL) /*!< ASGTRGDFR (Bit 6) */ + #define R_GPT7_GTICASR_ASGTRGDFR_Msk (0xc0UL) /*!< ASGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCARBHL_Pos (8UL) /*!< ASCARBHL (Bit 8) */ + #define R_GPT7_GTICASR_ASCARBHL_Msk (0x300UL) /*!< ASCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCAFBHL_Pos (10UL) /*!< ASCAFBHL (Bit 10) */ + #define R_GPT7_GTICASR_ASCAFBHL_Msk (0xc00UL) /*!< ASCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCBRAHL_Pos (12UL) /*!< ASCBRAHL (Bit 12) */ + #define R_GPT7_GTICASR_ASCBRAHL_Msk (0x3000UL) /*!< ASCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASCBFAHL_Pos (14UL) /*!< ASCBFAHL (Bit 14) */ + #define R_GPT7_GTICASR_ASCBFAHL_Msk (0xc000UL) /*!< ASCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICASR_ASELCA_Pos (16UL) /*!< ASELCA (Bit 16) */ + #define R_GPT7_GTICASR_ASELCA_Msk (0x10000UL) /*!< ASELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCB_Pos (17UL) /*!< ASELCB (Bit 17) */ + #define R_GPT7_GTICASR_ASELCB_Msk (0x20000UL) /*!< ASELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCC_Pos (18UL) /*!< ASELCC (Bit 18) */ + #define R_GPT7_GTICASR_ASELCC_Msk (0x40000UL) /*!< ASELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCD_Pos (19UL) /*!< ASELCD (Bit 19) */ + #define R_GPT7_GTICASR_ASELCD_Msk (0x80000UL) /*!< ASELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCE_Pos (20UL) /*!< ASELCE (Bit 20) */ + #define R_GPT7_GTICASR_ASELCE_Msk (0x100000UL) /*!< ASELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCF_Pos (21UL) /*!< ASELCF (Bit 21) */ + #define R_GPT7_GTICASR_ASELCF_Msk (0x200000UL) /*!< ASELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCG_Pos (22UL) /*!< ASELCG (Bit 22) */ + #define R_GPT7_GTICASR_ASELCG_Msk (0x400000UL) /*!< ASELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICASR_ASELCH_Pos (23UL) /*!< ASELCH (Bit 23) */ + #define R_GPT7_GTICASR_ASELCH_Msk (0x800000UL) /*!< ASELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTICBSR ======================================================== */ + #define R_GPT7_GTICBSR_BSGTRGAFR_Pos (0UL) /*!< BSGTRGAFR (Bit 0) */ + #define R_GPT7_GTICBSR_BSGTRGAFR_Msk (0x3UL) /*!< BSGTRGAFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSGTRGBFR_Pos (2UL) /*!< BSGTRGBFR (Bit 2) */ + #define R_GPT7_GTICBSR_BSGTRGBFR_Msk (0xcUL) /*!< BSGTRGBFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSGTRGCFR_Pos (4UL) /*!< BSGTRGCFR (Bit 4) */ + #define R_GPT7_GTICBSR_BSGTRGCFR_Msk (0x30UL) /*!< BSGTRGCFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSGTRGDFR_Pos (6UL) /*!< BSGTRGDFR (Bit 6) */ + #define R_GPT7_GTICBSR_BSGTRGDFR_Msk (0xc0UL) /*!< BSGTRGDFR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCARBHL_Pos (8UL) /*!< BSCARBHL (Bit 8) */ + #define R_GPT7_GTICBSR_BSCARBHL_Msk (0x300UL) /*!< BSCARBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCAFBHL_Pos (10UL) /*!< BSCAFBHL (Bit 10) */ + #define R_GPT7_GTICBSR_BSCAFBHL_Msk (0xc00UL) /*!< BSCAFBHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCBRAHL_Pos (12UL) /*!< BSCBRAHL (Bit 12) */ + #define R_GPT7_GTICBSR_BSCBRAHL_Msk (0x3000UL) /*!< BSCBRAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSCBFAHL_Pos (14UL) /*!< BSCBFAHL (Bit 14) */ + #define R_GPT7_GTICBSR_BSCBFAHL_Msk (0xc000UL) /*!< BSCBFAHL (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTICBSR_BSELCA_Pos (16UL) /*!< BSELCA (Bit 16) */ + #define R_GPT7_GTICBSR_BSELCA_Msk (0x10000UL) /*!< BSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCB_Pos (17UL) /*!< BSELCB (Bit 17) */ + #define R_GPT7_GTICBSR_BSELCB_Msk (0x20000UL) /*!< BSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCC_Pos (18UL) /*!< BSELCC (Bit 18) */ + #define R_GPT7_GTICBSR_BSELCC_Msk (0x40000UL) /*!< BSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCD_Pos (19UL) /*!< BSELCD (Bit 19) */ + #define R_GPT7_GTICBSR_BSELCD_Msk (0x80000UL) /*!< BSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCE_Pos (20UL) /*!< BSELCE (Bit 20) */ + #define R_GPT7_GTICBSR_BSELCE_Msk (0x100000UL) /*!< BSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCF_Pos (21UL) /*!< BSELCF (Bit 21) */ + #define R_GPT7_GTICBSR_BSELCF_Msk (0x200000UL) /*!< BSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCG_Pos (22UL) /*!< BSELCG (Bit 22) */ + #define R_GPT7_GTICBSR_BSELCG_Msk (0x400000UL) /*!< BSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTICBSR_BSELCH_Pos (23UL) /*!< BSELCH (Bit 23) */ + #define R_GPT7_GTICBSR_BSELCH_Msk (0x800000UL) /*!< BSELCH (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCR ========================================================== */ + #define R_GPT7_GTCR_CST_Pos (0UL) /*!< CST (Bit 0) */ + #define R_GPT7_GTCR_CST_Msk (0x1UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCR_ICDS_Pos (8UL) /*!< ICDS (Bit 8) */ + #define R_GPT7_GTCR_ICDS_Msk (0x100UL) /*!< ICDS (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTCR_MD_Pos (16UL) /*!< MD (Bit 16) */ + #define R_GPT7_GTCR_MD_Msk (0x70000UL) /*!< MD (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTCR_TPCS_Pos (23UL) /*!< TPCS (Bit 23) */ + #define R_GPT7_GTCR_TPCS_Msk (0x7800000UL) /*!< TPCS (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTCR_SWMD_Pos (29UL) /*!< SWMD (Bit 29) */ + #define R_GPT7_GTCR_SWMD_Msk (0xe0000000UL) /*!< SWMD (Bitfield-Mask: 0x07) */ +/* ======================================================= GTUDDTYC ======================================================== */ + #define R_GPT7_GTUDDTYC_UD_Pos (0UL) /*!< UD (Bit 0) */ + #define R_GPT7_GTUDDTYC_UD_Msk (0x1UL) /*!< UD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_UDF_Pos (1UL) /*!< UDF (Bit 1) */ + #define R_GPT7_GTUDDTYC_UDF_Msk (0x2UL) /*!< UDF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OADTY_Pos (16UL) /*!< OADTY (Bit 16) */ + #define R_GPT7_GTUDDTYC_OADTY_Msk (0x30000UL) /*!< OADTY (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUDDTYC_OADTYF_Pos (18UL) /*!< OADTYF (Bit 18) */ + #define R_GPT7_GTUDDTYC_OADTYF_Msk (0x40000UL) /*!< OADTYF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OADTYR_Pos (19UL) /*!< OADTYR (Bit 19) */ + #define R_GPT7_GTUDDTYC_OADTYR_Msk (0x80000UL) /*!< OADTYR (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OBDTY_Pos (24UL) /*!< OBDTY (Bit 24) */ + #define R_GPT7_GTUDDTYC_OBDTY_Msk (0x3000000UL) /*!< OBDTY (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTUDDTYC_OBDTYF_Pos (26UL) /*!< OBDTYF (Bit 26) */ + #define R_GPT7_GTUDDTYC_OBDTYF_Msk (0x4000000UL) /*!< OBDTYF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTUDDTYC_OBDTYR_Pos (27UL) /*!< OBDTYR (Bit 27) */ + #define R_GPT7_GTUDDTYC_OBDTYR_Msk (0x8000000UL) /*!< OBDTYR (Bitfield-Mask: 0x01) */ +/* ========================================================= GTIOR ========================================================= */ + #define R_GPT7_GTIOR_GTIOA_Pos (0UL) /*!< GTIOA (Bit 0) */ + #define R_GPT7_GTIOR_GTIOA_Msk (0x1fUL) /*!< GTIOA (Bitfield-Mask: 0x1f) */ + #define R_GPT7_GTIOR_OADFLT_Pos (6UL) /*!< OADFLT (Bit 6) */ + #define R_GPT7_GTIOR_OADFLT_Msk (0x40UL) /*!< OADFLT (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OAHLD_Pos (7UL) /*!< OAHLD (Bit 7) */ + #define R_GPT7_GTIOR_OAHLD_Msk (0x80UL) /*!< OAHLD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OAE_Pos (8UL) /*!< OAE (Bit 8) */ + #define R_GPT7_GTIOR_OAE_Msk (0x100UL) /*!< OAE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OADF_Pos (9UL) /*!< OADF (Bit 9) */ + #define R_GPT7_GTIOR_OADF_Msk (0x600UL) /*!< OADF (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTIOR_NFAEN_Pos (13UL) /*!< NFAEN (Bit 13) */ + #define R_GPT7_GTIOR_NFAEN_Msk (0x2000UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_NFCSA_Pos (14UL) /*!< NFCSA (Bit 14) */ + #define R_GPT7_GTIOR_NFCSA_Msk (0xc000UL) /*!< NFCSA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTIOR_GTIOB_Pos (16UL) /*!< GTIOB (Bit 16) */ + #define R_GPT7_GTIOR_GTIOB_Msk (0x1f0000UL) /*!< GTIOB (Bitfield-Mask: 0x1f) */ + #define R_GPT7_GTIOR_OBDFLT_Pos (22UL) /*!< OBDFLT (Bit 22) */ + #define R_GPT7_GTIOR_OBDFLT_Msk (0x400000UL) /*!< OBDFLT (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OBHLD_Pos (23UL) /*!< OBHLD (Bit 23) */ + #define R_GPT7_GTIOR_OBHLD_Msk (0x800000UL) /*!< OBHLD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OBE_Pos (24UL) /*!< OBE (Bit 24) */ + #define R_GPT7_GTIOR_OBE_Msk (0x1000000UL) /*!< OBE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_OBDF_Pos (25UL) /*!< OBDF (Bit 25) */ + #define R_GPT7_GTIOR_OBDF_Msk (0x6000000UL) /*!< OBDF (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTIOR_NFBEN_Pos (29UL) /*!< NFBEN (Bit 29) */ + #define R_GPT7_GTIOR_NFBEN_Msk (0x20000000UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTIOR_NFCSB_Pos (30UL) /*!< NFCSB (Bit 30) */ + #define R_GPT7_GTIOR_NFCSB_Msk (0xc0000000UL) /*!< NFCSB (Bitfield-Mask: 0x03) */ +/* ======================================================== GTINTAD ======================================================== */ + #define R_GPT7_GTINTAD_GTINTA_Pos (0UL) /*!< GTINTA (Bit 0) */ + #define R_GPT7_GTINTAD_GTINTA_Msk (0x1UL) /*!< GTINTA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTB_Pos (1UL) /*!< GTINTB (Bit 1) */ + #define R_GPT7_GTINTAD_GTINTB_Msk (0x2UL) /*!< GTINTB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTC_Pos (2UL) /*!< GTINTC (Bit 2) */ + #define R_GPT7_GTINTAD_GTINTC_Msk (0x4UL) /*!< GTINTC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTD_Pos (3UL) /*!< GTINTD (Bit 3) */ + #define R_GPT7_GTINTAD_GTINTD_Msk (0x8UL) /*!< GTINTD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTE_Pos (4UL) /*!< GTINTE (Bit 4) */ + #define R_GPT7_GTINTAD_GTINTE_Msk (0x10UL) /*!< GTINTE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTF_Pos (5UL) /*!< GTINTF (Bit 5) */ + #define R_GPT7_GTINTAD_GTINTF_Msk (0x20UL) /*!< GTINTF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GTINTPR_Pos (6UL) /*!< GTINTPR (Bit 6) */ + #define R_GPT7_GTINTAD_GTINTPR_Msk (0xc0UL) /*!< GTINTPR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTINTAD_ADTRAUEN_Pos (16UL) /*!< ADTRAUEN (Bit 16) */ + #define R_GPT7_GTINTAD_ADTRAUEN_Msk (0x10000UL) /*!< ADTRAUEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_ADTRADEN_Pos (17UL) /*!< ADTRADEN (Bit 17) */ + #define R_GPT7_GTINTAD_ADTRADEN_Msk (0x20000UL) /*!< ADTRADEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_ADTRBUEN_Pos (18UL) /*!< ADTRBUEN (Bit 18) */ + #define R_GPT7_GTINTAD_ADTRBUEN_Msk (0x40000UL) /*!< ADTRBUEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_ADTRBDEN_Pos (19UL) /*!< ADTRBDEN (Bit 19) */ + #define R_GPT7_GTINTAD_ADTRBDEN_Msk (0x80000UL) /*!< ADTRBDEN (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GRP_Pos (24UL) /*!< GRP (Bit 24) */ + #define R_GPT7_GTINTAD_GRP_Msk (0x3000000UL) /*!< GRP (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTINTAD_GRPDTE_Pos (28UL) /*!< GRPDTE (Bit 28) */ + #define R_GPT7_GTINTAD_GRPDTE_Msk (0x10000000UL) /*!< GRPDTE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GRPABH_Pos (29UL) /*!< GRPABH (Bit 29) */ + #define R_GPT7_GTINTAD_GRPABH_Msk (0x20000000UL) /*!< GRPABH (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTINTAD_GRPABL_Pos (30UL) /*!< GRPABL (Bit 30) */ + #define R_GPT7_GTINTAD_GRPABL_Msk (0x40000000UL) /*!< GRPABL (Bitfield-Mask: 0x01) */ +/* ========================================================= GTST ========================================================== */ + #define R_GPT7_GTST_ITCNT_Pos (8UL) /*!< ITCNT (Bit 8) */ + #define R_GPT7_GTST_ITCNT_Msk (0x700UL) /*!< ITCNT (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTST_TUCF_Pos (15UL) /*!< TUCF (Bit 15) */ + #define R_GPT7_GTST_TUCF_Msk (0x8000UL) /*!< TUCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRAUF_Pos (16UL) /*!< ADTRAUF (Bit 16) */ + #define R_GPT7_GTST_ADTRAUF_Msk (0x10000UL) /*!< ADTRAUF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRADF_Pos (17UL) /*!< ADTRADF (Bit 17) */ + #define R_GPT7_GTST_ADTRADF_Msk (0x20000UL) /*!< ADTRADF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRBUF_Pos (18UL) /*!< ADTRBUF (Bit 18) */ + #define R_GPT7_GTST_ADTRBUF_Msk (0x40000UL) /*!< ADTRBUF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ADTRBDF_Pos (19UL) /*!< ADTRBDF (Bit 19) */ + #define R_GPT7_GTST_ADTRBDF_Msk (0x80000UL) /*!< ADTRBDF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_ODF_Pos (24UL) /*!< ODF (Bit 24) */ + #define R_GPT7_GTST_ODF_Msk (0x1000000UL) /*!< ODF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_DTEF_Pos (28UL) /*!< DTEF (Bit 28) */ + #define R_GPT7_GTST_DTEF_Msk (0x10000000UL) /*!< DTEF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_OABHF_Pos (29UL) /*!< OABHF (Bit 29) */ + #define R_GPT7_GTST_OABHF_Msk (0x20000000UL) /*!< OABHF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTST_OABLF_Pos (30UL) /*!< OABLF (Bit 30) */ + #define R_GPT7_GTST_OABLF_Msk (0x40000000UL) /*!< OABLF (Bitfield-Mask: 0x01) */ +/* ========================================================= GTBER ========================================================= */ + #define R_GPT7_GTBER_BD0_Pos (0UL) /*!< BD0 (Bit 0) */ + #define R_GPT7_GTBER_BD0_Msk (0x1UL) /*!< BD0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_BD1_Pos (1UL) /*!< BD1 (Bit 1) */ + #define R_GPT7_GTBER_BD1_Msk (0x2UL) /*!< BD1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_BD2_Pos (2UL) /*!< BD2 (Bit 2) */ + #define R_GPT7_GTBER_BD2_Msk (0x4UL) /*!< BD2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_BD3_Pos (3UL) /*!< BD3 (Bit 3) */ + #define R_GPT7_GTBER_BD3_Msk (0x8UL) /*!< BD3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_DBRTECA_Pos (8UL) /*!< DBRTECA (Bit 8) */ + #define R_GPT7_GTBER_DBRTECA_Msk (0x100UL) /*!< DBRTECA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_DBRTECB_Pos (10UL) /*!< DBRTECB (Bit 10) */ + #define R_GPT7_GTBER_DBRTECB_Msk (0x400UL) /*!< DBRTECB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_CCRA_Pos (16UL) /*!< CCRA (Bit 16) */ + #define R_GPT7_GTBER_CCRA_Msk (0x30000UL) /*!< CCRA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_CCRB_Pos (18UL) /*!< CCRB (Bit 18) */ + #define R_GPT7_GTBER_CCRB_Msk (0xc0000UL) /*!< CCRB (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_PR_Pos (20UL) /*!< PR (Bit 20) */ + #define R_GPT7_GTBER_PR_Msk (0x300000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_CCRSWT_Pos (22UL) /*!< CCRSWT (Bit 22) */ + #define R_GPT7_GTBER_CCRSWT_Msk (0x400000UL) /*!< CCRSWT (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_ADTTA_Pos (24UL) /*!< ADTTA (Bit 24) */ + #define R_GPT7_GTBER_ADTTA_Msk (0x3000000UL) /*!< ADTTA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_ADTDA_Pos (26UL) /*!< ADTDA (Bit 26) */ + #define R_GPT7_GTBER_ADTDA_Msk (0x4000000UL) /*!< ADTDA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTBER_ADTTB_Pos (28UL) /*!< ADTTB (Bit 28) */ + #define R_GPT7_GTBER_ADTTB_Msk (0x30000000UL) /*!< ADTTB (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTBER_ADTDB_Pos (30UL) /*!< ADTDB (Bit 30) */ + #define R_GPT7_GTBER_ADTDB_Msk (0x40000000UL) /*!< ADTDB (Bitfield-Mask: 0x01) */ +/* ========================================================= GTITC ========================================================= */ + #define R_GPT7_GTITC_ITLA_Pos (0UL) /*!< ITLA (Bit 0) */ + #define R_GPT7_GTITC_ITLA_Msk (0x1UL) /*!< ITLA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLB_Pos (1UL) /*!< ITLB (Bit 1) */ + #define R_GPT7_GTITC_ITLB_Msk (0x2UL) /*!< ITLB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLC_Pos (2UL) /*!< ITLC (Bit 2) */ + #define R_GPT7_GTITC_ITLC_Msk (0x4UL) /*!< ITLC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLD_Pos (3UL) /*!< ITLD (Bit 3) */ + #define R_GPT7_GTITC_ITLD_Msk (0x8UL) /*!< ITLD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLE_Pos (4UL) /*!< ITLE (Bit 4) */ + #define R_GPT7_GTITC_ITLE_Msk (0x10UL) /*!< ITLE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ITLF_Pos (5UL) /*!< ITLF (Bit 5) */ + #define R_GPT7_GTITC_ITLF_Msk (0x20UL) /*!< ITLF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_IVTC_Pos (6UL) /*!< IVTC (Bit 6) */ + #define R_GPT7_GTITC_IVTC_Msk (0xc0UL) /*!< IVTC (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTITC_IVTT_Pos (8UL) /*!< IVTT (Bit 8) */ + #define R_GPT7_GTITC_IVTT_Msk (0x700UL) /*!< IVTT (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTITC_ADTAL_Pos (12UL) /*!< ADTAL (Bit 12) */ + #define R_GPT7_GTITC_ADTAL_Msk (0x1000UL) /*!< ADTAL (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTITC_ADTBL_Pos (14UL) /*!< ADTBL (Bit 14) */ + #define R_GPT7_GTITC_ADTBL_Msk (0x4000UL) /*!< ADTBL (Bitfield-Mask: 0x01) */ +/* ========================================================= GTCNT ========================================================= */ +/* ========================================================= GTCCR ========================================================= */ +/* ========================================================= GTPR ========================================================== */ +/* ========================================================= GTPBR ========================================================= */ +/* ======================================================== GTPDBR ========================================================= */ +/* ======================================================== GTADTRA ======================================================== */ +/* ======================================================= GTADTBRA ======================================================== */ +/* ======================================================= GTADTDBRA ======================================================= */ +/* ======================================================== GTADTRB ======================================================== */ +/* ======================================================= GTADTBRB ======================================================== */ +/* ======================================================= GTADTDBRB ======================================================= */ +/* ======================================================== GTDTCR ========================================================= */ + #define R_GPT7_GTDTCR_TDE_Pos (0UL) /*!< TDE (Bit 0) */ + #define R_GPT7_GTDTCR_TDE_Msk (0x1UL) /*!< TDE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDTCR_TDBUE_Pos (4UL) /*!< TDBUE (Bit 4) */ + #define R_GPT7_GTDTCR_TDBUE_Msk (0x10UL) /*!< TDBUE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDTCR_TDBDE_Pos (5UL) /*!< TDBDE (Bit 5) */ + #define R_GPT7_GTDTCR_TDBDE_Msk (0x20UL) /*!< TDBDE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTDTCR_TDFER_Pos (8UL) /*!< TDFER (Bit 8) */ + #define R_GPT7_GTDTCR_TDFER_Msk (0x100UL) /*!< TDFER (Bitfield-Mask: 0x01) */ +/* ========================================================= GTDVU ========================================================= */ +/* ========================================================= GTDVD ========================================================= */ +/* ========================================================= GTDBU ========================================================= */ +/* ========================================================= GTDBD ========================================================= */ +/* ========================================================= GTSOS ========================================================= */ + #define R_GPT7_GTSOS_SOS_Pos (0UL) /*!< SOS (Bit 0) */ + #define R_GPT7_GTSOS_SOS_Msk (0x3UL) /*!< SOS (Bitfield-Mask: 0x03) */ +/* ======================================================== GTSOTR ========================================================= */ + #define R_GPT7_GTSOTR_SOTR_Pos (0UL) /*!< SOTR (Bit 0) */ + #define R_GPT7_GTSOTR_SOTR_Msk (0x1UL) /*!< SOTR (Bitfield-Mask: 0x01) */ +/* ======================================================== GTADSMR ======================================================== */ + #define R_GPT7_GTADSMR_ADSMS0_Pos (0UL) /*!< ADSMS0 (Bit 0) */ + #define R_GPT7_GTADSMR_ADSMS0_Msk (0x3UL) /*!< ADSMS0 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTADSMR_ADSMEN0_Pos (8UL) /*!< ADSMEN0 (Bit 8) */ + #define R_GPT7_GTADSMR_ADSMEN0_Msk (0x100UL) /*!< ADSMEN0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTADSMR_ADSMS1_Pos (16UL) /*!< ADSMS1 (Bit 16) */ + #define R_GPT7_GTADSMR_ADSMS1_Msk (0x30000UL) /*!< ADSMS1 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTADSMR_ADSMEN1_Pos (24UL) /*!< ADSMEN1 (Bit 24) */ + #define R_GPT7_GTADSMR_ADSMEN1_Msk (0x1000000UL) /*!< ADSMEN1 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTEITC ========================================================= */ + #define R_GPT7_GTEITC_EIVTC1_Pos (0UL) /*!< EIVTC1 (Bit 0) */ + #define R_GPT7_GTEITC_EIVTC1_Msk (0x3UL) /*!< EIVTC1 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTEITC_EIVTT1_Pos (4UL) /*!< EIVTT1 (Bit 4) */ + #define R_GPT7_GTEITC_EIVTT1_Msk (0xf0UL) /*!< EIVTT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EITCNT1_Pos (12UL) /*!< EITCNT1 (Bit 12) */ + #define R_GPT7_GTEITC_EITCNT1_Msk (0xf000UL) /*!< EITCNT1 (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EIVTC2_Pos (16UL) /*!< EIVTC2 (Bit 16) */ + #define R_GPT7_GTEITC_EIVTC2_Msk (0x30000UL) /*!< EIVTC2 (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTEITC_EIVTT2_Pos (20UL) /*!< EIVTT2 (Bit 20) */ + #define R_GPT7_GTEITC_EIVTT2_Msk (0xf00000UL) /*!< EIVTT2 (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EITCNT2IV_Pos (24UL) /*!< EITCNT2IV (Bit 24) */ + #define R_GPT7_GTEITC_EITCNT2IV_Msk (0xf000000UL) /*!< EITCNT2IV (Bitfield-Mask: 0x0f) */ + #define R_GPT7_GTEITC_EITCNT2_Pos (28UL) /*!< EITCNT2 (Bit 28) */ + #define R_GPT7_GTEITC_EITCNT2_Msk (0xf0000000UL) /*!< EITCNT2 (Bitfield-Mask: 0x0f) */ +/* ======================================================= GTEITLI1 ======================================================== */ + #define R_GPT7_GTEITLI1_EITLA_Pos (0UL) /*!< EITLA (Bit 0) */ + #define R_GPT7_GTEITLI1_EITLA_Msk (0x7UL) /*!< EITLA (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLB_Pos (4UL) /*!< EITLB (Bit 4) */ + #define R_GPT7_GTEITLI1_EITLB_Msk (0x70UL) /*!< EITLB (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLC_Pos (8UL) /*!< EITLC (Bit 8) */ + #define R_GPT7_GTEITLI1_EITLC_Msk (0x700UL) /*!< EITLC (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLD_Pos (12UL) /*!< EITLD (Bit 12) */ + #define R_GPT7_GTEITLI1_EITLD_Msk (0x7000UL) /*!< EITLD (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLE_Pos (16UL) /*!< EITLE (Bit 16) */ + #define R_GPT7_GTEITLI1_EITLE_Msk (0x70000UL) /*!< EITLE (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLF_Pos (20UL) /*!< EITLF (Bit 20) */ + #define R_GPT7_GTEITLI1_EITLF_Msk (0x700000UL) /*!< EITLF (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLV_Pos (24UL) /*!< EITLV (Bit 24) */ + #define R_GPT7_GTEITLI1_EITLV_Msk (0x7000000UL) /*!< EITLV (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI1_EITLU_Pos (28UL) /*!< EITLU (Bit 28) */ + #define R_GPT7_GTEITLI1_EITLU_Msk (0x70000000UL) /*!< EITLU (Bitfield-Mask: 0x07) */ +/* ======================================================= GTEITLI2 ======================================================== */ + #define R_GPT7_GTEITLI2_EADTAL_Pos (0UL) /*!< EADTAL (Bit 0) */ + #define R_GPT7_GTEITLI2_EADTAL_Msk (0x7UL) /*!< EADTAL (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLI2_EADTBL_Pos (4UL) /*!< EADTBL (Bit 4) */ + #define R_GPT7_GTEITLI2_EADTBL_Msk (0x70UL) /*!< EADTBL (Bitfield-Mask: 0x07) */ +/* ======================================================== GTEITLB ======================================================== */ + #define R_GPT7_GTEITLB_EBTLCA_Pos (0UL) /*!< EBTLCA (Bit 0) */ + #define R_GPT7_GTEITLB_EBTLCA_Msk (0x7UL) /*!< EBTLCA (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLCB_Pos (4UL) /*!< EBTLCB (Bit 4) */ + #define R_GPT7_GTEITLB_EBTLCB_Msk (0x70UL) /*!< EBTLCB (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLPR_Pos (8UL) /*!< EBTLPR (Bit 8) */ + #define R_GPT7_GTEITLB_EBTLPR_Msk (0x700UL) /*!< EBTLPR (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLADA_Pos (16UL) /*!< EBTLADA (Bit 16) */ + #define R_GPT7_GTEITLB_EBTLADA_Msk (0x70000UL) /*!< EBTLADA (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLADB_Pos (20UL) /*!< EBTLADB (Bit 20) */ + #define R_GPT7_GTEITLB_EBTLADB_Msk (0x700000UL) /*!< EBTLADB (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLDVU_Pos (24UL) /*!< EBTLDVU (Bit 24) */ + #define R_GPT7_GTEITLB_EBTLDVU_Msk (0x7000000UL) /*!< EBTLDVU (Bitfield-Mask: 0x07) */ + #define R_GPT7_GTEITLB_EBTLDVD_Pos (28UL) /*!< EBTLDVD (Bit 28) */ + #define R_GPT7_GTEITLB_EBTLDVD_Msk (0x70000000UL) /*!< EBTLDVD (Bitfield-Mask: 0x07) */ +/* ======================================================== GTSECSR ======================================================== */ + #define R_GPT7_GTSECSR_SECSEL0_Pos (0UL) /*!< SECSEL0 (Bit 0) */ + #define R_GPT7_GTSECSR_SECSEL0_Msk (0x1UL) /*!< SECSEL0 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL1_Pos (1UL) /*!< SECSEL1 (Bit 1) */ + #define R_GPT7_GTSECSR_SECSEL1_Msk (0x2UL) /*!< SECSEL1 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL2_Pos (2UL) /*!< SECSEL2 (Bit 2) */ + #define R_GPT7_GTSECSR_SECSEL2_Msk (0x4UL) /*!< SECSEL2 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL3_Pos (3UL) /*!< SECSEL3 (Bit 3) */ + #define R_GPT7_GTSECSR_SECSEL3_Msk (0x8UL) /*!< SECSEL3 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL4_Pos (4UL) /*!< SECSEL4 (Bit 4) */ + #define R_GPT7_GTSECSR_SECSEL4_Msk (0x10UL) /*!< SECSEL4 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL5_Pos (5UL) /*!< SECSEL5 (Bit 5) */ + #define R_GPT7_GTSECSR_SECSEL5_Msk (0x20UL) /*!< SECSEL5 (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECSR_SECSEL6_Pos (6UL) /*!< SECSEL6 (Bit 6) */ + #define R_GPT7_GTSECSR_SECSEL6_Msk (0x40UL) /*!< SECSEL6 (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSECR ========================================================= */ + #define R_GPT7_GTSECR_SBDCE_Pos (0UL) /*!< SBDCE (Bit 0) */ + #define R_GPT7_GTSECR_SBDCE_Msk (0x1UL) /*!< SBDCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDPE_Pos (1UL) /*!< SBDPE (Bit 1) */ + #define R_GPT7_GTSECR_SBDPE_Msk (0x2UL) /*!< SBDPE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDAE_Pos (2UL) /*!< SBDAE (Bit 2) */ + #define R_GPT7_GTSECR_SBDAE_Msk (0x4UL) /*!< SBDAE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDDE_Pos (3UL) /*!< SBDDE (Bit 3) */ + #define R_GPT7_GTSECR_SBDDE_Msk (0x8UL) /*!< SBDDE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDCD_Pos (8UL) /*!< SBDCD (Bit 8) */ + #define R_GPT7_GTSECR_SBDCD_Msk (0x100UL) /*!< SBDCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDPD_Pos (9UL) /*!< SBDPD (Bit 9) */ + #define R_GPT7_GTSECR_SBDPD_Msk (0x200UL) /*!< SBDPD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDAD_Pos (10UL) /*!< SBDAD (Bit 10) */ + #define R_GPT7_GTSECR_SBDAD_Msk (0x400UL) /*!< SBDAD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSECR_SBDDD_Pos (11UL) /*!< SBDDD (Bit 11) */ + #define R_GPT7_GTSECR_SBDDD_Msk (0x800UL) /*!< SBDDD (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSWSR ========================================================= */ + #define R_GPT7_GTSWSR_WSGTRGA_Pos (0UL) /*!< WSGTRGA (Bit 0) */ + #define R_GPT7_GTSWSR_WSGTRGA_Msk (0x3UL) /*!< WSGTRGA (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSGTRGB_Pos (2UL) /*!< WSGTRGB (Bit 2) */ + #define R_GPT7_GTSWSR_WSGTRGB_Msk (0xcUL) /*!< WSGTRGB (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSGTRGC_Pos (4UL) /*!< WSGTRGC (Bit 4) */ + #define R_GPT7_GTSWSR_WSGTRGC_Msk (0x30UL) /*!< WSGTRGC (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSGTRGD_Pos (6UL) /*!< WSGTRGD (Bit 6) */ + #define R_GPT7_GTSWSR_WSGTRGD_Msk (0xc0UL) /*!< WSGTRGD (Bitfield-Mask: 0x03) */ + #define R_GPT7_GTSWSR_WSELCA_Pos (16UL) /*!< WSELCA (Bit 16) */ + #define R_GPT7_GTSWSR_WSELCA_Msk (0x10000UL) /*!< WSELCA (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCB_Pos (17UL) /*!< WSELCB (Bit 17) */ + #define R_GPT7_GTSWSR_WSELCB_Msk (0x20000UL) /*!< WSELCB (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCC_Pos (18UL) /*!< WSELCC (Bit 18) */ + #define R_GPT7_GTSWSR_WSELCC_Msk (0x40000UL) /*!< WSELCC (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCD_Pos (19UL) /*!< WSELCD (Bit 19) */ + #define R_GPT7_GTSWSR_WSELCD_Msk (0x80000UL) /*!< WSELCD (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCE_Pos (20UL) /*!< WSELCE (Bit 20) */ + #define R_GPT7_GTSWSR_WSELCE_Msk (0x100000UL) /*!< WSELCE (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCF_Pos (21UL) /*!< WSELCF (Bit 21) */ + #define R_GPT7_GTSWSR_WSELCF_Msk (0x200000UL) /*!< WSELCF (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_WSELCG_Pos (22UL) /*!< WSELCG (Bit 22) */ + #define R_GPT7_GTSWSR_WSELCG_Msk (0x400000UL) /*!< WSELCG (Bitfield-Mask: 0x01) */ + #define R_GPT7_GTSWSR_CSELCH_Pos (23UL) /*!< CSELCH (Bit 23) */ + #define R_GPT7_GTSWSR_CSELCH_Msk (0x800000UL) /*!< CSELCH (Bitfield-Mask: 0x01) */ +/* ======================================================== GTSWOS ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_SCI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== RDR ========================================================== */ + #define R_SCI0_RDR_RDAT_Pos (0UL) /*!< RDAT (Bit 0) */ + #define R_SCI0_RDR_RDAT_Msk (0x1ffUL) /*!< RDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_RDR_MPB_Pos (9UL) /*!< MPB (Bit 9) */ + #define R_SCI0_RDR_MPB_Msk (0x200UL) /*!< MPB (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_DR_Pos (10UL) /*!< DR (Bit 10) */ + #define R_SCI0_RDR_DR_Msk (0x400UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_FPER_Pos (11UL) /*!< FPER (Bit 11) */ + #define R_SCI0_RDR_FPER_Msk (0x800UL) /*!< FPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_FFER_Pos (12UL) /*!< FFER (Bit 12) */ + #define R_SCI0_RDR_FFER_Msk (0x1000UL) /*!< FFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI0_RDR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI0_RDR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_RDR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI0_RDR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ +/* ========================================================== TDR ========================================================== */ + #define R_SCI0_TDR_TDAT_Pos (0UL) /*!< TDAT (Bit 0) */ + #define R_SCI0_TDR_TDAT_Msk (0x1ffUL) /*!< TDAT (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_TDR_MPBT_Pos (9UL) /*!< MPBT (Bit 9) */ + #define R_SCI0_TDR_MPBT_Msk (0x200UL) /*!< MPBT (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR0 ========================================================== */ + #define R_SCI0_CCR0_RE_Pos (0UL) /*!< RE (Bit 0) */ + #define R_SCI0_CCR0_RE_Msk (0x1UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_TE_Pos (4UL) /*!< TE (Bit 4) */ + #define R_SCI0_CCR0_TE_Msk (0x10UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_MPIE_Pos (8UL) /*!< MPIE (Bit 8) */ + #define R_SCI0_CCR0_MPIE_Msk (0x100UL) /*!< MPIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_DCME_Pos (9UL) /*!< DCME (Bit 9) */ + #define R_SCI0_CCR0_DCME_Msk (0x200UL) /*!< DCME (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_IDSEL_Pos (10UL) /*!< IDSEL (Bit 10) */ + #define R_SCI0_CCR0_IDSEL_Msk (0x400UL) /*!< IDSEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_RIE_Pos (16UL) /*!< RIE (Bit 16) */ + #define R_SCI0_CCR0_RIE_Msk (0x10000UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_TIE_Pos (20UL) /*!< TIE (Bit 20) */ + #define R_SCI0_CCR0_TIE_Msk (0x100000UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_TEIE_Pos (21UL) /*!< TEIE (Bit 21) */ + #define R_SCI0_CCR0_TEIE_Msk (0x200000UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR0_SSE_Pos (24UL) /*!< SSE (Bit 24) */ + #define R_SCI0_CCR0_SSE_Msk (0x1000000UL) /*!< SSE (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR1 ========================================================== */ + #define R_SCI0_CCR1_CTSE_Pos (0UL) /*!< CTSE (Bit 0) */ + #define R_SCI0_CCR1_CTSE_Msk (0x1UL) /*!< CTSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_CTSPEN_Pos (1UL) /*!< CTSPEN (Bit 1) */ + #define R_SCI0_CCR1_CTSPEN_Msk (0x2UL) /*!< CTSPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SPB2DT_Pos (4UL) /*!< SPB2DT (Bit 4) */ + #define R_SCI0_CCR1_SPB2DT_Msk (0x10UL) /*!< SPB2DT (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SPB2IO_Pos (5UL) /*!< SPB2IO (Bit 5) */ + #define R_SCI0_CCR1_SPB2IO_Msk (0x20UL) /*!< SPB2IO (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_PE_Pos (8UL) /*!< PE (Bit 8) */ + #define R_SCI0_CCR1_PE_Msk (0x100UL) /*!< PE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_PM_Pos (9UL) /*!< PM (Bit 9) */ + #define R_SCI0_CCR1_PM_Msk (0x200UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_TINV_Pos (12UL) /*!< TINV (Bit 12) */ + #define R_SCI0_CCR1_TINV_Msk (0x1000UL) /*!< TINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_RINV_Pos (13UL) /*!< RINV (Bit 13) */ + #define R_SCI0_CCR1_RINV_Msk (0x2000UL) /*!< RINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SPLP_Pos (16UL) /*!< SPLP (Bit 16) */ + #define R_SCI0_CCR1_SPLP_Msk (0x10000UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_SHARPS_Pos (20UL) /*!< SHARPS (Bit 20) */ + #define R_SCI0_CCR1_SHARPS_Msk (0x100000UL) /*!< SHARPS (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR1_NFCS_Pos (24UL) /*!< NFCS (Bit 24) */ + #define R_SCI0_CCR1_NFCS_Msk (0x7000000UL) /*!< NFCS (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR1_NFEN_Pos (28UL) /*!< NFEN (Bit 28) */ + #define R_SCI0_CCR1_NFEN_Msk (0x10000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR2 ========================================================== */ + #define R_SCI0_CCR2_BCP_Pos (0UL) /*!< BCP (Bit 0) */ + #define R_SCI0_CCR2_BCP_Msk (0x7UL) /*!< BCP (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR2_BGDM_Pos (4UL) /*!< BGDM (Bit 4) */ + #define R_SCI0_CCR2_BGDM_Msk (0x10UL) /*!< BGDM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_ABCS_Pos (5UL) /*!< ABCS (Bit 5) */ + #define R_SCI0_CCR2_ABCS_Msk (0x20UL) /*!< ABCS (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_ABCSE_Pos (6UL) /*!< ABCSE (Bit 6) */ + #define R_SCI0_CCR2_ABCSE_Msk (0x40UL) /*!< ABCSE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_BRR_Pos (8UL) /*!< BRR (Bit 8) */ + #define R_SCI0_CCR2_BRR_Msk (0xff00UL) /*!< BRR (Bitfield-Mask: 0xff) */ + #define R_SCI0_CCR2_BRME_Pos (16UL) /*!< BRME (Bit 16) */ + #define R_SCI0_CCR2_BRME_Msk (0x10000UL) /*!< BRME (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR2_CKS_Pos (20UL) /*!< CKS (Bit 20) */ + #define R_SCI0_CCR2_CKS_Msk (0x300000UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_SCI0_CCR2_MDDR_Pos (24UL) /*!< MDDR (Bit 24) */ + #define R_SCI0_CCR2_MDDR_Msk (0xff000000UL) /*!< MDDR (Bitfield-Mask: 0xff) */ +/* ========================================================= CCR3 ========================================================== */ + #define R_SCI0_CCR3_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SCI0_CCR3_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SCI0_CCR3_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_BPEN_Pos (7UL) /*!< BPEN (Bit 7) */ + #define R_SCI0_CCR3_BPEN_Msk (0x80UL) /*!< BPEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_CHR_Pos (8UL) /*!< CHR (Bit 8) */ + #define R_SCI0_CCR3_CHR_Msk (0x300UL) /*!< CHR (Bitfield-Mask: 0x03) */ + #define R_SCI0_CCR3_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SCI0_CCR3_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_SINV_Pos (13UL) /*!< SINV (Bit 13) */ + #define R_SCI0_CCR3_SINV_Msk (0x2000UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_STP_Pos (14UL) /*!< STP (Bit 14) */ + #define R_SCI0_CCR3_STP_Msk (0x4000UL) /*!< STP (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_RXDESEL_Pos (15UL) /*!< RXDESEL (Bit 15) */ + #define R_SCI0_CCR3_RXDESEL_Msk (0x8000UL) /*!< RXDESEL (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_MOD_Pos (16UL) /*!< MOD (Bit 16) */ + #define R_SCI0_CCR3_MOD_Msk (0x70000UL) /*!< MOD (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR3_MP_Pos (19UL) /*!< MP (Bit 19) */ + #define R_SCI0_CCR3_MP_Msk (0x80000UL) /*!< MP (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_FM_Pos (20UL) /*!< FM (Bit 20) */ + #define R_SCI0_CCR3_FM_Msk (0x100000UL) /*!< FM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_DEN_Pos (21UL) /*!< DEN (Bit 21) */ + #define R_SCI0_CCR3_DEN_Msk (0x200000UL) /*!< DEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_CKE_Pos (24UL) /*!< CKE (Bit 24) */ + #define R_SCI0_CCR3_CKE_Msk (0x3000000UL) /*!< CKE (Bitfield-Mask: 0x03) */ + #define R_SCI0_CCR3_GM_Pos (28UL) /*!< GM (Bit 28) */ + #define R_SCI0_CCR3_GM_Msk (0x10000000UL) /*!< GM (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR3_BLK_Pos (29UL) /*!< BLK (Bit 29) */ + #define R_SCI0_CCR3_BLK_Msk (0x20000000UL) /*!< BLK (Bitfield-Mask: 0x01) */ +/* ========================================================= CCR4 ========================================================== */ + #define R_SCI0_CCR4_CMPD_Pos (0UL) /*!< CMPD (Bit 0) */ + #define R_SCI0_CCR4_CMPD_Msk (0x1ffUL) /*!< CMPD (Bitfield-Mask: 0x1ff) */ + #define R_SCI0_CCR4_ASEN_Pos (16UL) /*!< ASEN (Bit 16) */ + #define R_SCI0_CCR4_ASEN_Msk (0x10000UL) /*!< ASEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR4_ATEN_Pos (17UL) /*!< ATEN (Bit 17) */ + #define R_SCI0_CCR4_ATEN_Msk (0x20000UL) /*!< ATEN (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR4_AST_Pos (24UL) /*!< AST (Bit 24) */ + #define R_SCI0_CCR4_AST_Msk (0x7000000UL) /*!< AST (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR4_AJD_Pos (27UL) /*!< AJD (Bit 27) */ + #define R_SCI0_CCR4_AJD_Msk (0x8000000UL) /*!< AJD (Bitfield-Mask: 0x01) */ + #define R_SCI0_CCR4_ATT_Pos (28UL) /*!< ATT (Bit 28) */ + #define R_SCI0_CCR4_ATT_Msk (0x70000000UL) /*!< ATT (Bitfield-Mask: 0x07) */ + #define R_SCI0_CCR4_AET_Pos (31UL) /*!< AET (Bit 31) */ + #define R_SCI0_CCR4_AET_Msk (0x80000000UL) /*!< AET (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SCI0_ICR_IICDL_Pos (0UL) /*!< IICDL (Bit 0) */ + #define R_SCI0_ICR_IICDL_Msk (0x1fUL) /*!< IICDL (Bitfield-Mask: 0x1f) */ + #define R_SCI0_ICR_IICINTM_Pos (8UL) /*!< IICINTM (Bit 8) */ + #define R_SCI0_ICR_IICINTM_Msk (0x100UL) /*!< IICINTM (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICCSC_Pos (9UL) /*!< IICCSC (Bit 9) */ + #define R_SCI0_ICR_IICCSC_Msk (0x200UL) /*!< IICCSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICACKT_Pos (13UL) /*!< IICACKT (Bit 13) */ + #define R_SCI0_ICR_IICACKT_Msk (0x2000UL) /*!< IICACKT (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICSTAREQ_Pos (16UL) /*!< IICSTAREQ (Bit 16) */ + #define R_SCI0_ICR_IICSTAREQ_Msk (0x10000UL) /*!< IICSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICRSTAREQ_Pos (17UL) /*!< IICRSTAREQ (Bit 17) */ + #define R_SCI0_ICR_IICRSTAREQ_Msk (0x20000UL) /*!< IICRSTAREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICSTPREQ_Pos (18UL) /*!< IICSTPREQ (Bit 18) */ + #define R_SCI0_ICR_IICSTPREQ_Msk (0x40000UL) /*!< IICSTPREQ (Bitfield-Mask: 0x01) */ + #define R_SCI0_ICR_IICSDAS_Pos (20UL) /*!< IICSDAS (Bit 20) */ + #define R_SCI0_ICR_IICSDAS_Msk (0x300000UL) /*!< IICSDAS (Bitfield-Mask: 0x03) */ + #define R_SCI0_ICR_IICSCLS_Pos (22UL) /*!< IICSCLS (Bit 22) */ + #define R_SCI0_ICR_IICSCLS_Msk (0xc00000UL) /*!< IICSCLS (Bitfield-Mask: 0x03) */ +/* ========================================================== FCR ========================================================== */ + #define R_SCI0_FCR_DRES_Pos (0UL) /*!< DRES (Bit 0) */ + #define R_SCI0_FCR_DRES_Msk (0x1UL) /*!< DRES (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SCI0_FCR_TTRG_Msk (0x1f00UL) /*!< TTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FCR_TFRST_Pos (15UL) /*!< TFRST (Bit 15) */ + #define R_SCI0_FCR_TFRST_Msk (0x8000UL) /*!< TFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RTRG_Pos (16UL) /*!< RTRG (Bit 16) */ + #define R_SCI0_FCR_RTRG_Msk (0x1f0000UL) /*!< RTRG (Bitfield-Mask: 0x1f) */ + #define R_SCI0_FCR_RFRST_Pos (23UL) /*!< RFRST (Bit 23) */ + #define R_SCI0_FCR_RFRST_Msk (0x800000UL) /*!< RFRST (Bitfield-Mask: 0x01) */ + #define R_SCI0_FCR_RSTRG_Pos (24UL) /*!< RSTRG (Bit 24) */ + #define R_SCI0_FCR_RSTRG_Msk (0x1f000000UL) /*!< RSTRG (Bitfield-Mask: 0x1f) */ +/* ========================================================== DCR ========================================================== */ + #define R_SCI0_DCR_DEPOL_Pos (0UL) /*!< DEPOL (Bit 0) */ + #define R_SCI0_DCR_DEPOL_Msk (0x1UL) /*!< DEPOL (Bitfield-Mask: 0x01) */ + #define R_SCI0_DCR_DEAST_Pos (8UL) /*!< DEAST (Bit 8) */ + #define R_SCI0_DCR_DEAST_Msk (0x1f00UL) /*!< DEAST (Bitfield-Mask: 0x1f) */ + #define R_SCI0_DCR_DENGT_Pos (16UL) /*!< DENGT (Bit 16) */ + #define R_SCI0_DCR_DENGT_Msk (0x1f0000UL) /*!< DENGT (Bitfield-Mask: 0x1f) */ +/* ========================================================== CSR ========================================================== */ + #define R_SCI0_CSR_ERS_Pos (4UL) /*!< ERS (Bit 4) */ + #define R_SCI0_CSR_ERS_Msk (0x10UL) /*!< ERS (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_RXDMON_Pos (15UL) /*!< RXDMON (Bit 15) */ + #define R_SCI0_CSR_RXDMON_Msk (0x8000UL) /*!< RXDMON (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_DCMF_Pos (16UL) /*!< DCMF (Bit 16) */ + #define R_SCI0_CSR_DCMF_Msk (0x10000UL) /*!< DCMF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_DPER_Pos (17UL) /*!< DPER (Bit 17) */ + #define R_SCI0_CSR_DPER_Msk (0x20000UL) /*!< DPER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_DFER_Pos (18UL) /*!< DFER (Bit 18) */ + #define R_SCI0_CSR_DFER_Msk (0x40000UL) /*!< DFER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_ORER_Pos (24UL) /*!< ORER (Bit 24) */ + #define R_SCI0_CSR_ORER_Msk (0x1000000UL) /*!< ORER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_MFF_Pos (26UL) /*!< MFF (Bit 26) */ + #define R_SCI0_CSR_MFF_Msk (0x4000000UL) /*!< MFF (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_PER_Pos (27UL) /*!< PER (Bit 27) */ + #define R_SCI0_CSR_PER_Msk (0x8000000UL) /*!< PER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_FER_Pos (28UL) /*!< FER (Bit 28) */ + #define R_SCI0_CSR_FER_Msk (0x10000000UL) /*!< FER (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_TDRE_Pos (29UL) /*!< TDRE (Bit 29) */ + #define R_SCI0_CSR_TDRE_Msk (0x20000000UL) /*!< TDRE (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_TEND_Pos (30UL) /*!< TEND (Bit 30) */ + #define R_SCI0_CSR_TEND_Msk (0x40000000UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_SCI0_CSR_RDRF_Pos (31UL) /*!< RDRF (Bit 31) */ + #define R_SCI0_CSR_RDRF_Msk (0x80000000UL) /*!< RDRF (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SCI0_ISR_IICACKR_Pos (0UL) /*!< IICACKR (Bit 0) */ + #define R_SCI0_ISR_IICACKR_Msk (0x1UL) /*!< IICACKR (Bitfield-Mask: 0x01) */ + #define R_SCI0_ISR_IICSTIF_Pos (3UL) /*!< IICSTIF (Bit 3) */ + #define R_SCI0_ISR_IICSTIF_Msk (0x8UL) /*!< IICSTIF (Bitfield-Mask: 0x01) */ +/* ========================================================= FRSR ========================================================== */ + #define R_SCI0_FRSR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_SCI0_FRSR_DR_Msk (0x1UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_SCI0_FRSR_R_Pos (8UL) /*!< R (Bit 8) */ + #define R_SCI0_FRSR_R_Msk (0x3f00UL) /*!< R (Bitfield-Mask: 0x3f) */ + #define R_SCI0_FRSR_PNUM_Pos (16UL) /*!< PNUM (Bit 16) */ + #define R_SCI0_FRSR_PNUM_Msk (0x3f0000UL) /*!< PNUM (Bitfield-Mask: 0x3f) */ + #define R_SCI0_FRSR_FNUM_Pos (24UL) /*!< FNUM (Bit 24) */ + #define R_SCI0_FRSR_FNUM_Msk (0x3f000000UL) /*!< FNUM (Bitfield-Mask: 0x3f) */ +/* ========================================================= FTSR ========================================================== */ + #define R_SCI0_FTSR_T_Pos (0UL) /*!< T (Bit 0) */ + #define R_SCI0_FTSR_T_Msk (0x3fUL) /*!< T (Bitfield-Mask: 0x3f) */ +/* ========================================================= CFCLR ========================================================= */ + #define R_SCI0_CFCLR_ERSC_Pos (4UL) /*!< ERSC (Bit 4) */ + #define R_SCI0_CFCLR_ERSC_Msk (0x10UL) /*!< ERSC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_DCMFC_Pos (16UL) /*!< DCMFC (Bit 16) */ + #define R_SCI0_CFCLR_DCMFC_Msk (0x10000UL) /*!< DCMFC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_DPERC_Pos (17UL) /*!< DPERC (Bit 17) */ + #define R_SCI0_CFCLR_DPERC_Msk (0x20000UL) /*!< DPERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_DFERC_Pos (18UL) /*!< DFERC (Bit 18) */ + #define R_SCI0_CFCLR_DFERC_Msk (0x40000UL) /*!< DFERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_ORERC_Pos (24UL) /*!< ORERC (Bit 24) */ + #define R_SCI0_CFCLR_ORERC_Msk (0x1000000UL) /*!< ORERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_MFFC_Pos (26UL) /*!< MFFC (Bit 26) */ + #define R_SCI0_CFCLR_MFFC_Msk (0x4000000UL) /*!< MFFC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_PERC_Pos (27UL) /*!< PERC (Bit 27) */ + #define R_SCI0_CFCLR_PERC_Msk (0x8000000UL) /*!< PERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_FERC_Pos (28UL) /*!< FERC (Bit 28) */ + #define R_SCI0_CFCLR_FERC_Msk (0x10000000UL) /*!< FERC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_TDREC_Pos (29UL) /*!< TDREC (Bit 29) */ + #define R_SCI0_CFCLR_TDREC_Msk (0x20000000UL) /*!< TDREC (Bitfield-Mask: 0x01) */ + #define R_SCI0_CFCLR_RDRFC_Pos (31UL) /*!< RDRFC (Bit 31) */ + #define R_SCI0_CFCLR_RDRFC_Msk (0x80000000UL) /*!< RDRFC (Bitfield-Mask: 0x01) */ +/* ======================================================== ICFCLR ========================================================= */ + #define R_SCI0_ICFCLR_IICSTIFC_Pos (3UL) /*!< IICSTIFC (Bit 3) */ + #define R_SCI0_ICFCLR_IICSTIFC_Msk (0x8UL) /*!< IICSTIFC (Bitfield-Mask: 0x01) */ +/* ========================================================= FFCLR ========================================================= */ + #define R_SCI0_FFCLR_DRC_Pos (0UL) /*!< DRC (Bit 0) */ + #define R_SCI0_FFCLR_DRC_Msk (0x1UL) /*!< DRC (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SPI0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SPDR ========================================================== */ + #define R_SPI0_SPDR_SPD_Pos (0UL) /*!< SPD (Bit 0) */ + #define R_SPI0_SPDR_SPD_Msk (0xffffffffUL) /*!< SPD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SPDR_HA ======================================================== */ +/* ======================================================== SPDR_BY ======================================================== */ +/* ========================================================= SPCKD ========================================================= */ + #define R_SPI0_SPCKD_SCKDL_Pos (0UL) /*!< SCKDL (Bit 0) */ + #define R_SPI0_SPCKD_SCKDL_Msk (0x7UL) /*!< SCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLND ========================================================= */ + #define R_SPI0_SSLND_SLNDL_Pos (0UL) /*!< SLNDL (Bit 0) */ + #define R_SPI0_SSLND_SLNDL_Msk (0x7UL) /*!< SLNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SPND ========================================================== */ + #define R_SPI0_SPND_SPNDL_Pos (0UL) /*!< SPNDL (Bit 0) */ + #define R_SPI0_SPND_SPNDL_Msk (0x7UL) /*!< SPNDL (Bitfield-Mask: 0x07) */ +/* ========================================================= MRCKD ========================================================= */ + #define R_SPI0_MRCKD_ARST_Pos (0UL) /*!< ARST (Bit 0) */ + #define R_SPI0_MRCKD_ARST_Msk (0x7UL) /*!< ARST (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCR ========================================================== */ + #define R_SPI0_SPCR_SPE_Pos (0UL) /*!< SPE (Bit 0) */ + #define R_SPI0_SPCR_SPE_Msk (0x1UL) /*!< SPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPSCKSEL_Pos (7UL) /*!< SPSCKSEL (Bit 7) */ + #define R_SPI0_SPCR_SPSCKSEL_Msk (0x80UL) /*!< SPSCKSEL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPPE_Pos (8UL) /*!< SPPE (Bit 8) */ + #define R_SPI0_SPCR_SPPE_Msk (0x100UL) /*!< SPPE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPOE_Pos (9UL) /*!< SPOE (Bit 9) */ + #define R_SPI0_SPCR_SPOE_Msk (0x200UL) /*!< SPOE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_PTE_Pos (11UL) /*!< PTE (Bit 11) */ + #define R_SPI0_SPCR_PTE_Msk (0x800UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SCKASE_Pos (12UL) /*!< SCKASE (Bit 12) */ + #define R_SPI0_SPCR_SCKASE_Msk (0x1000UL) /*!< SCKASE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_BFDS_Pos (13UL) /*!< BFDS (Bit 13) */ + #define R_SPI0_SPCR_BFDS_Msk (0x2000UL) /*!< BFDS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_MODFEN_Pos (14UL) /*!< MODFEN (Bit 14) */ + #define R_SPI0_SPCR_MODFEN_Msk (0x4000UL) /*!< MODFEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPEIE_Pos (16UL) /*!< SPEIE (Bit 16) */ + #define R_SPI0_SPCR_SPEIE_Msk (0x10000UL) /*!< SPEIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPRIE_Pos (17UL) /*!< SPRIE (Bit 17) */ + #define R_SPI0_SPCR_SPRIE_Msk (0x20000UL) /*!< SPRIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPIIE_Pos (18UL) /*!< SPIIE (Bit 18) */ + #define R_SPI0_SPCR_SPIIE_Msk (0x40000UL) /*!< SPIIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPDRES_Pos (19UL) /*!< SPDRES (Bit 19) */ + #define R_SPI0_SPCR_SPDRES_Msk (0x80000UL) /*!< SPDRES (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPTIE_Pos (20UL) /*!< SPTIE (Bit 20) */ + #define R_SPI0_SPCR_SPTIE_Msk (0x100000UL) /*!< SPTIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_CENDIE_Pos (21UL) /*!< CENDIE (Bit 21) */ + #define R_SPI0_SPCR_CENDIE_Msk (0x200000UL) /*!< CENDIE (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPMS_Pos (24UL) /*!< SPMS (Bit 24) */ + #define R_SPI0_SPCR_SPMS_Msk (0x1000000UL) /*!< SPMS (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_SPFRF_Pos (25UL) /*!< SPFRF (Bit 25) */ + #define R_SPI0_SPCR_SPFRF_Msk (0x2000000UL) /*!< SPFRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_TXMD_Pos (28UL) /*!< TXMD (Bit 28) */ + #define R_SPI0_SPCR_TXMD_Msk (0x30000000UL) /*!< TXMD (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCR_MSTR_Pos (30UL) /*!< MSTR (Bit 30) */ + #define R_SPI0_SPCR_MSTR_Msk (0x40000000UL) /*!< MSTR (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCR_BPEN_Pos (31UL) /*!< BPEN (Bit 31) */ + #define R_SPI0_SPCR_BPEN_Msk (0x80000000UL) /*!< BPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SPCRRM ========================================================= */ + #define R_SPI0_SPCRRM_RMFM_Pos (0UL) /*!< RMFM (Bit 0) */ + #define R_SPI0_SPCRRM_RMFM_Msk (0x1fUL) /*!< RMFM (Bitfield-Mask: 0x1f) */ + #define R_SPI0_SPCRRM_RMEDTG_Pos (6UL) /*!< RMEDTG (Bit 6) */ + #define R_SPI0_SPCRRM_RMEDTG_Msk (0x40UL) /*!< RMEDTG (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCRRM_RMSTTG_Pos (7UL) /*!< RMSTTG (Bit 7) */ + #define R_SPI0_SPCRRM_RMSTTG_Msk (0x80UL) /*!< RMSTTG (Bitfield-Mask: 0x01) */ +/* ======================================================== SPDRCR ========================================================= */ + #define R_SPI0_SPDRCR_SPDRC_Pos (0UL) /*!< SPDRC (Bit 0) */ + #define R_SPI0_SPDRCR_SPDRC_Msk (0xffUL) /*!< SPDRC (Bitfield-Mask: 0xff) */ +/* ========================================================= SPPCR ========================================================= */ + #define R_SPI0_SPPCR_SPLP_Pos (0UL) /*!< SPLP (Bit 0) */ + #define R_SPI0_SPPCR_SPLP_Msk (0x1UL) /*!< SPLP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPLP2_Pos (1UL) /*!< SPLP2 (Bit 1) */ + #define R_SPI0_SPPCR_SPLP2_Msk (0x2UL) /*!< SPLP2 (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_SPOM_Pos (2UL) /*!< SPOM (Bit 2) */ + #define R_SPI0_SPPCR_SPOM_Msk (0x4UL) /*!< SPOM (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFV_Pos (4UL) /*!< MOIFV (Bit 4) */ + #define R_SPI0_SPPCR_MOIFV_Msk (0x10UL) /*!< MOIFV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPPCR_MOIFE_Pos (5UL) /*!< MOIFE (Bit 5) */ + #define R_SPI0_SPPCR_MOIFE_Msk (0x20UL) /*!< MOIFE (Bitfield-Mask: 0x01) */ +/* ========================================================= SPCR2 ========================================================= */ + #define R_SPI0_SPCR2_SPSCKDL_Pos (0UL) /*!< SPSCKDL (Bit 0) */ + #define R_SPI0_SPCR2_SPSCKDL_Msk (0x7UL) /*!< SPSCKDL (Bitfield-Mask: 0x07) */ +/* ========================================================= SSLP ========================================================== */ + #define R_SPI0_SSLP_SSL0P_Pos (0UL) /*!< SSL0P (Bit 0) */ + #define R_SPI0_SSLP_SSL0P_Msk (0x1UL) /*!< SSL0P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL1P_Pos (1UL) /*!< SSL1P (Bit 1) */ + #define R_SPI0_SSLP_SSL1P_Msk (0x2UL) /*!< SSL1P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL2P_Pos (2UL) /*!< SSL2P (Bit 2) */ + #define R_SPI0_SSLP_SSL2P_Msk (0x4UL) /*!< SSL2P (Bitfield-Mask: 0x01) */ + #define R_SPI0_SSLP_SSL3P_Pos (3UL) /*!< SSL3P (Bit 3) */ + #define R_SPI0_SSLP_SSL3P_Msk (0x8UL) /*!< SSL3P (Bitfield-Mask: 0x01) */ +/* ========================================================= SPBR ========================================================== */ + #define R_SPI0_SPBR_SPR_Pos (0UL) /*!< SPR (Bit 0) */ + #define R_SPI0_SPBR_SPR_Msk (0xffUL) /*!< SPR (Bitfield-Mask: 0xff) */ +/* ========================================================= SPSCR ========================================================= */ + #define R_SPI0_SPSCR_SPSLN_Pos (0UL) /*!< SPSLN (Bit 0) */ + #define R_SPI0_SPSCR_SPSLN_Msk (0x7UL) /*!< SPSLN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPCMD ========================================================= */ + #define R_SPI0_SPCMD_CPHA_Pos (0UL) /*!< CPHA (Bit 0) */ + #define R_SPI0_SPCMD_CPHA_Msk (0x1UL) /*!< CPHA (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_CPOL_Pos (1UL) /*!< CPOL (Bit 1) */ + #define R_SPI0_SPCMD_CPOL_Msk (0x2UL) /*!< CPOL (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_BRDV_Pos (2UL) /*!< BRDV (Bit 2) */ + #define R_SPI0_SPCMD_BRDV_Msk (0xcUL) /*!< BRDV (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPCMD_SSLKP_Pos (7UL) /*!< SSLKP (Bit 7) */ + #define R_SPI0_SPCMD_SSLKP_Msk (0x80UL) /*!< SSLKP (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_LSBF_Pos (12UL) /*!< LSBF (Bit 12) */ + #define R_SPI0_SPCMD_LSBF_Msk (0x1000UL) /*!< LSBF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPNDEN_Pos (13UL) /*!< SPNDEN (Bit 13) */ + #define R_SPI0_SPCMD_SPNDEN_Msk (0x2000UL) /*!< SPNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SLNDEN_Pos (14UL) /*!< SLNDEN (Bit 14) */ + #define R_SPI0_SPCMD_SLNDEN_Msk (0x4000UL) /*!< SLNDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SCKDEN_Pos (15UL) /*!< SCKDEN (Bit 15) */ + #define R_SPI0_SPCMD_SCKDEN_Msk (0x8000UL) /*!< SCKDEN (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPCMD_SPB_Pos (16UL) /*!< SPB (Bit 16) */ + #define R_SPI0_SPCMD_SPB_Msk (0x1f0000UL) /*!< SPB (Bitfield-Mask: 0x1f) */ + #define R_SPI0_SPCMD_SSLA_Pos (24UL) /*!< SSLA (Bit 24) */ + #define R_SPI0_SPCMD_SSLA_Msk (0x3000000UL) /*!< SSLA (Bitfield-Mask: 0x03) */ +/* ========================================================= SPDCR ========================================================= */ + #define R_SPI0_SPDCR_BYSW_Pos (0UL) /*!< BYSW (Bit 0) */ + #define R_SPI0_SPDCR_BYSW_Msk (0x1UL) /*!< BYSW (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SLSEL_Pos (1UL) /*!< SLSEL (Bit 1) */ + #define R_SPI0_SPDCR_SLSEL_Msk (0x6UL) /*!< SLSEL (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR_SPRDTD_Pos (3UL) /*!< SPRDTD (Bit 3) */ + #define R_SPI0_SPDCR_SPRDTD_Msk (0x8UL) /*!< SPRDTD (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SINV_Pos (4UL) /*!< SINV (Bit 4) */ + #define R_SPI0_SPDCR_SINV_Msk (0x10UL) /*!< SINV (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPDCR_SPFC_Pos (8UL) /*!< SPFC (Bit 8) */ + #define R_SPI0_SPDCR_SPFC_Msk (0x300UL) /*!< SPFC (Bitfield-Mask: 0x03) */ +/* ======================================================== SPDCR2 ========================================================= */ + #define R_SPI0_SPDCR2_RTRG_Pos (0UL) /*!< RTRG (Bit 0) */ + #define R_SPI0_SPDCR2_RTRG_Msk (0x3UL) /*!< RTRG (Bitfield-Mask: 0x03) */ + #define R_SPI0_SPDCR2_TTRG_Pos (8UL) /*!< TTRG (Bit 8) */ + #define R_SPI0_SPDCR2_TTRG_Msk (0x300UL) /*!< TTRG (Bitfield-Mask: 0x03) */ +/* ========================================================= SPSSR ========================================================= */ + #define R_SPI0_SPSSR_SPCP_Pos (0UL) /*!< SPCP (Bit 0) */ + #define R_SPI0_SPSSR_SPCP_Msk (0x7UL) /*!< SPCP (Bitfield-Mask: 0x07) */ + #define R_SPI0_SPSSR_SPECM_Pos (4UL) /*!< SPECM (Bit 4) */ + #define R_SPI0_SPSSR_SPECM_Msk (0x70UL) /*!< SPECM (Bitfield-Mask: 0x07) */ +/* ========================================================= SPSR ========================================================== */ + #define R_SPI0_SPSR_SPDRF_Pos (7UL) /*!< SPDRF (Bit 7) */ + #define R_SPI0_SPSR_SPDRF_Msk (0x80UL) /*!< SPDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_OVRF_Pos (8UL) /*!< OVRF (Bit 8) */ + #define R_SPI0_SPSR_OVRF_Msk (0x100UL) /*!< OVRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_IDLNF_Pos (9UL) /*!< IDLNF (Bit 9) */ + #define R_SPI0_SPSR_IDLNF_Msk (0x200UL) /*!< IDLNF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_MODF_Pos (10UL) /*!< MODF (Bit 10) */ + #define R_SPI0_SPSR_MODF_Msk (0x400UL) /*!< MODF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_PERF_Pos (11UL) /*!< PERF (Bit 11) */ + #define R_SPI0_SPSR_PERF_Msk (0x800UL) /*!< PERF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_UDRF_Pos (12UL) /*!< UDRF (Bit 12) */ + #define R_SPI0_SPSR_UDRF_Msk (0x1000UL) /*!< UDRF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPTEF_Pos (13UL) /*!< SPTEF (Bit 13) */ + #define R_SPI0_SPSR_SPTEF_Msk (0x2000UL) /*!< SPTEF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_CENDF_Pos (14UL) /*!< CENDF (Bit 14) */ + #define R_SPI0_SPSR_CENDF_Msk (0x4000UL) /*!< CENDF (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSR_SPRF_Pos (15UL) /*!< SPRF (Bit 15) */ + #define R_SPI0_SPSR_SPRF_Msk (0x8000UL) /*!< SPRF (Bitfield-Mask: 0x01) */ +/* ======================================================== SPTFSR ========================================================= */ + #define R_SPI0_SPTFSR_TFDN_Pos (0UL) /*!< TFDN (Bit 0) */ + #define R_SPI0_SPTFSR_TFDN_Msk (0x7UL) /*!< TFDN (Bitfield-Mask: 0x07) */ +/* ======================================================== SPRFSR ========================================================= */ + #define R_SPI0_SPRFSR_RFDN_Pos (0UL) /*!< RFDN (Bit 0) */ + #define R_SPI0_SPRFSR_RFDN_Msk (0x7UL) /*!< RFDN (Bitfield-Mask: 0x07) */ +/* ========================================================= SPPSR ========================================================= */ + #define R_SPI0_SPPSR_SPEPS_Pos (0UL) /*!< SPEPS (Bit 0) */ + #define R_SPI0_SPPSR_SPEPS_Msk (0x1UL) /*!< SPEPS (Bitfield-Mask: 0x01) */ +/* ========================================================= SPSRC ========================================================= */ + #define R_SPI0_SPSRC_SPDRFC_Pos (7UL) /*!< SPDRFC (Bit 7) */ + #define R_SPI0_SPSRC_SPDRFC_Msk (0x80UL) /*!< SPDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_OVRFC_Pos (8UL) /*!< OVRFC (Bit 8) */ + #define R_SPI0_SPSRC_OVRFC_Msk (0x100UL) /*!< OVRFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_MODFC_Pos (10UL) /*!< MODFC (Bit 10) */ + #define R_SPI0_SPSRC_MODFC_Msk (0x400UL) /*!< MODFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_PERFC_Pos (11UL) /*!< PERFC (Bit 11) */ + #define R_SPI0_SPSRC_PERFC_Msk (0x800UL) /*!< PERFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_UDRFC_Pos (12UL) /*!< UDRFC (Bit 12) */ + #define R_SPI0_SPSRC_UDRFC_Msk (0x1000UL) /*!< UDRFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_SPTEFC_Pos (13UL) /*!< SPTEFC (Bit 13) */ + #define R_SPI0_SPSRC_SPTEFC_Msk (0x2000UL) /*!< SPTEFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_CENDFC_Pos (14UL) /*!< CENDFC (Bit 14) */ + #define R_SPI0_SPSRC_CENDFC_Msk (0x4000UL) /*!< CENDFC (Bitfield-Mask: 0x01) */ + #define R_SPI0_SPSRC_SPRFC_Pos (15UL) /*!< SPRFC (Bit 15) */ + #define R_SPI0_SPSRC_SPRFC_Msk (0x8000UL) /*!< SPRFC (Bitfield-Mask: 0x01) */ +/* ========================================================= SPFCR ========================================================= */ + #define R_SPI0_SPFCR_SPFRST_Pos (0UL) /*!< SPFRST (Bit 0) */ + #define R_SPI0_SPFCR_SPFRST_Msk (0x1UL) /*!< SPFRST (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CRC0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CRCCR0 ========================================================= */ + #define R_CRC0_CRCCR0_GPS_Pos (0UL) /*!< GPS (Bit 0) */ + #define R_CRC0_CRCCR0_GPS_Msk (0x7UL) /*!< GPS (Bitfield-Mask: 0x07) */ + #define R_CRC0_CRCCR0_LMS_Pos (6UL) /*!< LMS (Bit 6) */ + #define R_CRC0_CRCCR0_LMS_Msk (0x40UL) /*!< LMS (Bitfield-Mask: 0x01) */ + #define R_CRC0_CRCCR0_DORCLR_Pos (7UL) /*!< DORCLR (Bit 7) */ + #define R_CRC0_CRCCR0_DORCLR_Msk (0x80UL) /*!< DORCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CRCDIR ========================================================= */ +/* ======================================================= CRCDIR_BY ======================================================= */ +/* ======================================================== CRCDOR ========================================================= */ +/* ======================================================= CRCDOR_HA ======================================================= */ +/* ======================================================= CRCDOR_BY ======================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_CANFD ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CFDGIPV ======================================================== */ + #define R_CANFD_CFDGIPV_IPV_Pos (0UL) /*!< IPV (Bit 0) */ + #define R_CANFD_CFDGIPV_IPV_Msk (0xffUL) /*!< IPV (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDGIPV_IPT_Pos (8UL) /*!< IPT (Bit 8) */ + #define R_CANFD_CFDGIPV_IPT_Msk (0x300UL) /*!< IPT (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGIPV_PSI_Pos (16UL) /*!< PSI (Bit 16) */ + #define R_CANFD_CFDGIPV_PSI_Msk (0x3fff0000UL) /*!< PSI (Bitfield-Mask: 0x3fff) */ +/* ======================================================== CFDGCFG ======================================================== */ + #define R_CANFD_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ + #define R_CANFD_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ + #define R_CANFD_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ + #define R_CANFD_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ + #define R_CANFD_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ + #define R_CANFD_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ + #define R_CANFD_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ + #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ + #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ + #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ + #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFDGCTR ======================================================== */ + #define R_CANFD_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ + #define R_CANFD_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ + #define R_CANFD_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ + #define R_CANFD_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ + #define R_CANFD_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ + #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ + #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_QOWEIE_Pos (12UL) /*!< QOWEIE (Bit 12) */ + #define R_CANFD_CFDGCTR_QOWEIE_Msk (0x1000UL) /*!< QOWEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ + #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ + #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ + #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGSTS ======================================================== */ + #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ + #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ + #define R_CANFD_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ + #define R_CANFD_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ + #define R_CANFD_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGERFL ======================================================== */ + #define R_CANFD_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ + #define R_CANFD_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ + #define R_CANFD_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ + #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ + #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ + #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ + #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_MOWES_Pos (7UL) /*!< MOWES (Bit 7) */ + #define R_CANFD_CFDGERFL_MOWES_Msk (0x80UL) /*!< MOWES (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ + #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ + #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CFDGTSC ======================================================== */ + #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ + #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDGAFLECTR ====================================================== */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ + #define R_CANFD_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ + #define R_CANFD_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGAFLCFG0 ====================================================== */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ + #define R_CANFD_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ + #define R_CANFD_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ +/* ======================================================== CFDRMNB ======================================================== */ + #define R_CANFD_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ + #define R_CANFD_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ + #define R_CANFD_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDRMND0 ======================================================== */ + #define R_CANFD_CFDRMND0_RMNS_Pos (0UL) /*!< RMNS (Bit 0) */ + #define R_CANFD_CFDRMND0_RMNS_Msk (0xffffffffUL) /*!< RMNS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFDRFCC ======================================================== */ + #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ + #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ + #define R_CANFD_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ + #define R_CANFD_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ + #define R_CANFD_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ + #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ + #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ + #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFSTS ======================================================== */ + #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ + #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ + #define R_CANFD_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ + #define R_CANFD_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ + #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ + #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ + #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDRFPCTR ======================================================= */ + #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ + #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ +/* ======================================================== CFDCFCC ======================================================== */ + #define R_CANFD_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ + #define R_CANFD_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ + #define R_CANFD_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ + #define R_CANFD_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ + #define R_CANFD_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ + #define R_CANFD_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ + #define R_CANFD_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ + #define R_CANFD_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ + #define R_CANFD_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ + #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ + #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDCFCCE ======================================================== */ + #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ + #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ + #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ + #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ + #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ + #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFSTS ======================================================== */ + #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ + #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ + #define R_CANFD_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ + #define R_CANFD_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ + #define R_CANFD_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ + #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ + #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ + #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ + #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ + #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ + #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCFPCTR ======================================================= */ + #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ + #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDFESTS ======================================================== */ + #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFSTS ======================================================== */ + #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFMSTS ======================================================== */ + #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDRFISTS ======================================================= */ + #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ + #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDCFRISTS ======================================================= */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ + #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFTISTS ======================================================= */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ + #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFRISTS ====================================================== */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ + #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ +/* ===================================================== CFDCFOFTISTS ====================================================== */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ + #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDCFMOWSTS ====================================================== */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ + #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ +/* ======================================================= CFDFFFSTS ======================================================= */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ + #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ + #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ +/* ======================================================== CFDTMC ========================================================= */ + #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ + #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ + #define R_CANFD_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ + #define R_CANFD_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTMSTS ======================================================== */ + #define R_CANFD_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ + #define R_CANFD_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ + #define R_CANFD_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ + #define R_CANFD_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ + #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTMTRSTS ======================================================= */ + #define R_CANFD_CFDTMTRSTS_TMTRSTS_Pos (0UL) /*!< TMTRSTS (Bit 0) */ + #define R_CANFD_CFDTMTRSTS_TMTRSTS_Msk (0xffffUL) /*!< TMTRSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTARSTS ====================================================== */ + #define R_CANFD_CFDTMTARSTS_TMTARSTS_Pos (0UL) /*!< TMTARSTS (Bit 0) */ + #define R_CANFD_CFDTMTARSTS_TMTARSTS_Msk (0xffffUL) /*!< TMTARSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTCSTS ======================================================= */ + #define R_CANFD_CFDTMTCSTS_TMTCSTS_Pos (0UL) /*!< TMTCSTS (Bit 0) */ + #define R_CANFD_CFDTMTCSTS_TMTCSTS_Msk (0xffffUL) /*!< TMTCSTS (Bitfield-Mask: 0xffff) */ +/* ====================================================== CFDTMTASTS ======================================================= */ + #define R_CANFD_CFDTMTASTS_TMTASTS_Pos (0UL) /*!< TMTASTS (Bit 0) */ + #define R_CANFD_CFDTMTASTS_TMTASTS_Msk (0xffffUL) /*!< TMTASTS (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDTMIEC ======================================================== */ + #define R_CANFD_CFDTMIEC_TMIE_Pos (0UL) /*!< TMIE (Bit 0) */ + #define R_CANFD_CFDTMIEC_TMIE_Msk (0xffffUL) /*!< TMIE (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDTXQCC0 ======================================================= */ + #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC0_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS0 ======================================================= */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS0_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS0_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR0 ====================================================== */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC1 ======================================================= */ + #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC1_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS1 ======================================================= */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS1_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS1_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR1 ====================================================== */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC2 ======================================================= */ + #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ + #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC2_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ + #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ + #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS2 ======================================================= */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ + #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ + #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ + #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS2_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS2_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR2 ====================================================== */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDTXQCC3 ======================================================= */ + #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ + #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQOWE_Pos (2UL) /*!< TXQOWE (Bit 2) */ + #define R_CANFD_CFDTXQCC3_TXQOWE_Msk (0x4UL) /*!< TXQOWE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ + #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ + #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ + #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ + #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQSTS3 ======================================================= */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ + #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ + #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ + #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ + #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ + #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQSTS3_TXQMOW_Pos (20UL) /*!< TXQMOW (Bit 20) */ + #define R_CANFD_CFDTXQSTS3_TXQMOW_Msk (0x100000UL) /*!< TXQMOW (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDTXQPCTR3 ====================================================== */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ + #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQESTS ======================================================= */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ + #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ +/* ====================================================== CFDTXQFISTS ====================================================== */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ + #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ + #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQMSTS ======================================================= */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ + #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ + #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQISTS ======================================================= */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ + #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ + #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFTISTS ===================================================== */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ + #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ +/* ===================================================== CFDTXQOFRISTS ===================================================== */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ + #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ +/* ====================================================== CFDTXQFSTS ======================================================= */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ + #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ + #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDTHLCC ======================================================== */ + #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ + #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ + #define R_CANFD_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ + #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ + #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ + #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDTHLSTS ======================================================= */ + #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ + #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ + #define R_CANFD_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ + #define R_CANFD_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ + #define R_CANFD_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ + #define R_CANFD_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ +/* ====================================================== CFDTHLPCTR ======================================================= */ + #define R_CANFD_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ + #define R_CANFD_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ +/* ===================================================== CFDGTINTSTS0 ====================================================== */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ + #define R_CANFD_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ + #define R_CANFD_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ + #define R_CANFD_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ + #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ + #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ + #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ + #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ + #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ + #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ + #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ + #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGTSTCFG ======================================================= */ + #define R_CANFD_CFDGTSTCFG_C0ICBCE_Pos (0UL) /*!< C0ICBCE (Bit 0) */ + #define R_CANFD_CFDGTSTCFG_C0ICBCE_Msk (0x1UL) /*!< C0ICBCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCFG_C1ICBCE_Pos (1UL) /*!< C1ICBCE (Bit 1) */ + #define R_CANFD_CFDGTSTCFG_C1ICBCE_Msk (0x2UL) /*!< C1ICBCE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ + #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ +/* ====================================================== CFDGTSTCTR ======================================================= */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ + #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ + #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFDCFG ======================================================= */ + #define R_CANFD_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ + #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ + #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ +/* ======================================================= CFDGLOCKK ======================================================= */ + #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ + #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ +/* ======================================================= CFDCDTCT ======================================================== */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ + #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ + #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ + #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ + #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ + #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ + #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTSTS ======================================================= */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ + #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDCDTTCT ======================================================= */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ + #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ + #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ + #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ + #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDCDTTSTS ======================================================= */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ + #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ + #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ + #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ +/* ====================================================== CFDGRINTSTS ====================================================== */ + #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ + #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_BQFIF_Pos (4UL) /*!< BQFIF (Bit 4) */ + #define R_CANFD_CFDGRINTSTS_BQFIF_Msk (0x30UL) /*!< BQFIF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ + #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_BQOFRIF_Pos (12UL) /*!< BQOFRIF (Bit 12) */ + #define R_CANFD_CFDGRINTSTS_BQOFRIF_Msk (0x3000UL) /*!< BQOFRIF (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ + #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ + #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ + #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ +/* ======================================================= CFDGRSTC ======================================================== */ + #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ + #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ + #define R_CANFD_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ +/* ======================================================= CFDGFCMC ======================================================== */ + #define R_CANFD_CFDGFCMC_FLXC0_Pos (0UL) /*!< FLXC0 (Bit 0) */ + #define R_CANFD_CFDGFCMC_FLXC0_Msk (0x1UL) /*!< FLXC0 (Bitfield-Mask: 0x01) */ +/* ======================================================= CFDGFTBAC ======================================================= */ + #define R_CANFD_CFDGFTBAC_FLXMB0_Pos (0UL) /*!< FLXMB0 (Bit 0) */ + #define R_CANFD_CFDGFTBAC_FLXMB0_Msk (0xfUL) /*!< FLXMB0 (Bitfield-Mask: 0x0f) */ +/* ======================================================= CFDRPGACC ======================================================= */ + #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ + #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_CMT ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_CMTW0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CMWSTR ========================================================= */ + #define R_CMTW0_CMWSTR_STR_Pos (0UL) /*!< STR (Bit 0) */ + #define R_CMTW0_CMWSTR_STR_Msk (0x1UL) /*!< STR (Bitfield-Mask: 0x01) */ +/* ========================================================= CMWCR ========================================================= */ + #define R_CMTW0_CMWCR_CKS_Pos (0UL) /*!< CKS (Bit 0) */ + #define R_CMTW0_CMWCR_CKS_Msk (0x3UL) /*!< CKS (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWCR_CMWIE_Pos (3UL) /*!< CMWIE (Bit 3) */ + #define R_CMTW0_CMWCR_CMWIE_Msk (0x8UL) /*!< CMWIE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_IC0IE_Pos (4UL) /*!< IC0IE (Bit 4) */ + #define R_CMTW0_CMWCR_IC0IE_Msk (0x10UL) /*!< IC0IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_IC1IE_Pos (5UL) /*!< IC1IE (Bit 5) */ + #define R_CMTW0_CMWCR_IC1IE_Msk (0x20UL) /*!< IC1IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_OC0IE_Pos (6UL) /*!< OC0IE (Bit 6) */ + #define R_CMTW0_CMWCR_OC0IE_Msk (0x40UL) /*!< OC0IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_OC1IE_Pos (7UL) /*!< OC1IE (Bit 7) */ + #define R_CMTW0_CMWCR_OC1IE_Msk (0x80UL) /*!< OC1IE (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_CMS_Pos (9UL) /*!< CMS (Bit 9) */ + #define R_CMTW0_CMWCR_CMS_Msk (0x200UL) /*!< CMS (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWCR_CCLR_Pos (13UL) /*!< CCLR (Bit 13) */ + #define R_CMTW0_CMWCR_CCLR_Msk (0xe000UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ======================================================== CMWIOR ========================================================= */ + #define R_CMTW0_CMWIOR_IC0_Pos (0UL) /*!< IC0 (Bit 0) */ + #define R_CMTW0_CMWIOR_IC0_Msk (0x3UL) /*!< IC0 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_IC1_Pos (2UL) /*!< IC1 (Bit 2) */ + #define R_CMTW0_CMWIOR_IC1_Msk (0xcUL) /*!< IC1 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_IC0E_Pos (4UL) /*!< IC0E (Bit 4) */ + #define R_CMTW0_CMWIOR_IC0E_Msk (0x10UL) /*!< IC0E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_IC1E_Pos (5UL) /*!< IC1E (Bit 5) */ + #define R_CMTW0_CMWIOR_IC1E_Msk (0x20UL) /*!< IC1E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_OC0_Pos (8UL) /*!< OC0 (Bit 8) */ + #define R_CMTW0_CMWIOR_OC0_Msk (0x300UL) /*!< OC0 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_OC1_Pos (10UL) /*!< OC1 (Bit 10) */ + #define R_CMTW0_CMWIOR_OC1_Msk (0xc00UL) /*!< OC1 (Bitfield-Mask: 0x03) */ + #define R_CMTW0_CMWIOR_OC0E_Pos (12UL) /*!< OC0E (Bit 12) */ + #define R_CMTW0_CMWIOR_OC0E_Msk (0x1000UL) /*!< OC0E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_OC1E_Pos (13UL) /*!< OC1E (Bit 13) */ + #define R_CMTW0_CMWIOR_OC1E_Msk (0x2000UL) /*!< OC1E (Bitfield-Mask: 0x01) */ + #define R_CMTW0_CMWIOR_CMWE_Pos (15UL) /*!< CMWE (Bit 15) */ + #define R_CMTW0_CMWIOR_CMWE_Msk (0x8000UL) /*!< CMWE (Bitfield-Mask: 0x01) */ +/* ======================================================== CMWCNT ========================================================= */ +/* ======================================================== CMWCOR ========================================================= */ +/* ======================================================== CMWICR0 ======================================================== */ +/* ======================================================== CMWICR1 ======================================================== */ +/* ======================================================== CMWOCR0 ======================================================== */ +/* ======================================================== CMWOCR1 ======================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_WDT0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= WDTRR ========================================================= */ +/* ========================================================= WDTCR ========================================================= */ + #define R_WDT0_WDTCR_TOPS_Pos (0UL) /*!< TOPS (Bit 0) */ + #define R_WDT0_WDTCR_TOPS_Msk (0x3UL) /*!< TOPS (Bitfield-Mask: 0x03) */ + #define R_WDT0_WDTCR_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_WDT0_WDTCR_CKS_Msk (0xf0UL) /*!< CKS (Bitfield-Mask: 0x0f) */ + #define R_WDT0_WDTCR_RPES_Pos (8UL) /*!< RPES (Bit 8) */ + #define R_WDT0_WDTCR_RPES_Msk (0x300UL) /*!< RPES (Bitfield-Mask: 0x03) */ + #define R_WDT0_WDTCR_RPSS_Pos (12UL) /*!< RPSS (Bit 12) */ + #define R_WDT0_WDTCR_RPSS_Msk (0x3000UL) /*!< RPSS (Bitfield-Mask: 0x03) */ +/* ========================================================= WDTSR ========================================================= */ + #define R_WDT0_WDTSR_CNTVAL_Pos (0UL) /*!< CNTVAL (Bit 0) */ + #define R_WDT0_WDTSR_CNTVAL_Msk (0x3fffUL) /*!< CNTVAL (Bitfield-Mask: 0x3fff) */ + #define R_WDT0_WDTSR_UNDFF_Pos (14UL) /*!< UNDFF (Bit 14) */ + #define R_WDT0_WDTSR_UNDFF_Msk (0x4000UL) /*!< UNDFF (Bitfield-Mask: 0x01) */ + #define R_WDT0_WDTSR_REFEF_Pos (15UL) /*!< REFEF (Bit 15) */ + #define R_WDT0_WDTSR_REFEF_Msk (0x8000UL) /*!< REFEF (Bitfield-Mask: 0x01) */ +/* ======================================================== WDTRCR ========================================================= */ + #define R_WDT0_WDTRCR_RSTIRQS_Pos (7UL) /*!< RSTIRQS (Bit 7) */ + #define R_WDT0_WDTRCR_RSTIRQS_Msk (0x80UL) /*!< RSTIRQS (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_IIC0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICCR1 ========================================================= */ + #define R_IIC0_ICCR1_SDAI_Pos (0UL) /*!< SDAI (Bit 0) */ + #define R_IIC0_ICCR1_SDAI_Msk (0x1UL) /*!< SDAI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLI_Pos (1UL) /*!< SCLI (Bit 1) */ + #define R_IIC0_ICCR1_SCLI_Msk (0x2UL) /*!< SCLI (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SDAO_Pos (2UL) /*!< SDAO (Bit 2) */ + #define R_IIC0_ICCR1_SDAO_Msk (0x4UL) /*!< SDAO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SCLO_Pos (3UL) /*!< SCLO (Bit 3) */ + #define R_IIC0_ICCR1_SCLO_Msk (0x8UL) /*!< SCLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_SOWP_Pos (4UL) /*!< SOWP (Bit 4) */ + #define R_IIC0_ICCR1_SOWP_Msk (0x10UL) /*!< SOWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_CLO_Pos (5UL) /*!< CLO (Bit 5) */ + #define R_IIC0_ICCR1_CLO_Msk (0x20UL) /*!< CLO (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_IICRST_Pos (6UL) /*!< IICRST (Bit 6) */ + #define R_IIC0_ICCR1_IICRST_Msk (0x40UL) /*!< IICRST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR1_ICE_Pos (7UL) /*!< ICE (Bit 7) */ + #define R_IIC0_ICCR1_ICE_Msk (0x80UL) /*!< ICE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICCR2 ========================================================= */ + #define R_IIC0_ICCR2_ST_Pos (1UL) /*!< ST (Bit 1) */ + #define R_IIC0_ICCR2_ST_Msk (0x2UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_RS_Pos (2UL) /*!< RS (Bit 2) */ + #define R_IIC0_ICCR2_RS_Msk (0x4UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_SP_Pos (3UL) /*!< SP (Bit 3) */ + #define R_IIC0_ICCR2_SP_Msk (0x8UL) /*!< SP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_TRS_Pos (5UL) /*!< TRS (Bit 5) */ + #define R_IIC0_ICCR2_TRS_Msk (0x20UL) /*!< TRS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_MST_Pos (6UL) /*!< MST (Bit 6) */ + #define R_IIC0_ICCR2_MST_Msk (0x40UL) /*!< MST (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICCR2_BBSY_Pos (7UL) /*!< BBSY (Bit 7) */ + #define R_IIC0_ICCR2_BBSY_Msk (0x80UL) /*!< BBSY (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR1 ========================================================= */ + #define R_IIC0_ICMR1_BC_Pos (0UL) /*!< BC (Bit 0) */ + #define R_IIC0_ICMR1_BC_Msk (0x7UL) /*!< BC (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_BCWP_Pos (3UL) /*!< BCWP (Bit 3) */ + #define R_IIC0_ICMR1_BCWP_Msk (0x8UL) /*!< BCWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR1_CKS_Pos (4UL) /*!< CKS (Bit 4) */ + #define R_IIC0_ICMR1_CKS_Msk (0x70UL) /*!< CKS (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR1_MTWP_Pos (7UL) /*!< MTWP (Bit 7) */ + #define R_IIC0_ICMR1_MTWP_Msk (0x80UL) /*!< MTWP (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR2 ========================================================= */ + #define R_IIC0_ICMR2_TMOS_Pos (0UL) /*!< TMOS (Bit 0) */ + #define R_IIC0_ICMR2_TMOS_Msk (0x1UL) /*!< TMOS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOL_Pos (1UL) /*!< TMOL (Bit 1) */ + #define R_IIC0_ICMR2_TMOL_Msk (0x2UL) /*!< TMOL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_TMOH_Pos (2UL) /*!< TMOH (Bit 2) */ + #define R_IIC0_ICMR2_TMOH_Msk (0x4UL) /*!< TMOH (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR2_SDDL_Pos (4UL) /*!< SDDL (Bit 4) */ + #define R_IIC0_ICMR2_SDDL_Msk (0x70UL) /*!< SDDL (Bitfield-Mask: 0x07) */ + #define R_IIC0_ICMR2_DLCS_Pos (7UL) /*!< DLCS (Bit 7) */ + #define R_IIC0_ICMR2_DLCS_Msk (0x80UL) /*!< DLCS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICMR3 ========================================================= */ + #define R_IIC0_ICMR3_NF_Pos (0UL) /*!< NF (Bit 0) */ + #define R_IIC0_ICMR3_NF_Msk (0x3UL) /*!< NF (Bitfield-Mask: 0x03) */ + #define R_IIC0_ICMR3_ACKBR_Pos (2UL) /*!< ACKBR (Bit 2) */ + #define R_IIC0_ICMR3_ACKBR_Msk (0x4UL) /*!< ACKBR (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKBT_Pos (3UL) /*!< ACKBT (Bit 3) */ + #define R_IIC0_ICMR3_ACKBT_Msk (0x8UL) /*!< ACKBT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_ACKWP_Pos (4UL) /*!< ACKWP (Bit 4) */ + #define R_IIC0_ICMR3_ACKWP_Msk (0x10UL) /*!< ACKWP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_RDRFS_Pos (5UL) /*!< RDRFS (Bit 5) */ + #define R_IIC0_ICMR3_RDRFS_Msk (0x20UL) /*!< RDRFS (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_WAIT_Pos (6UL) /*!< WAIT (Bit 6) */ + #define R_IIC0_ICMR3_WAIT_Msk (0x40UL) /*!< WAIT (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICMR3_SMBS_Pos (7UL) /*!< SMBS (Bit 7) */ + #define R_IIC0_ICMR3_SMBS_Msk (0x80UL) /*!< SMBS (Bitfield-Mask: 0x01) */ +/* ========================================================= ICFER ========================================================= */ + #define R_IIC0_ICFER_TMOE_Pos (0UL) /*!< TMOE (Bit 0) */ + #define R_IIC0_ICFER_TMOE_Msk (0x1UL) /*!< TMOE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_MALE_Pos (1UL) /*!< MALE (Bit 1) */ + #define R_IIC0_ICFER_MALE_Msk (0x2UL) /*!< MALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NALE_Pos (2UL) /*!< NALE (Bit 2) */ + #define R_IIC0_ICFER_NALE_Msk (0x4UL) /*!< NALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SALE_Pos (3UL) /*!< SALE (Bit 3) */ + #define R_IIC0_ICFER_SALE_Msk (0x8UL) /*!< SALE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NACKE_Pos (4UL) /*!< NACKE (Bit 4) */ + #define R_IIC0_ICFER_NACKE_Msk (0x10UL) /*!< NACKE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_NFE_Pos (5UL) /*!< NFE (Bit 5) */ + #define R_IIC0_ICFER_NFE_Msk (0x20UL) /*!< NFE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICFER_SCLE_Pos (6UL) /*!< SCLE (Bit 6) */ + #define R_IIC0_ICFER_SCLE_Msk (0x40UL) /*!< SCLE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSER ========================================================= */ + #define R_IIC0_ICSER_SAR0E_Pos (0UL) /*!< SAR0E (Bit 0) */ + #define R_IIC0_ICSER_SAR0E_Msk (0x1UL) /*!< SAR0E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR1E_Pos (1UL) /*!< SAR1E (Bit 1) */ + #define R_IIC0_ICSER_SAR1E_Msk (0x2UL) /*!< SAR1E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_SAR2E_Pos (2UL) /*!< SAR2E (Bit 2) */ + #define R_IIC0_ICSER_SAR2E_Msk (0x4UL) /*!< SAR2E (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_GCAE_Pos (3UL) /*!< GCAE (Bit 3) */ + #define R_IIC0_ICSER_GCAE_Msk (0x8UL) /*!< GCAE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_DIDE_Pos (5UL) /*!< DIDE (Bit 5) */ + #define R_IIC0_ICSER_DIDE_Msk (0x20UL) /*!< DIDE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSER_HOAE_Pos (7UL) /*!< HOAE (Bit 7) */ + #define R_IIC0_ICSER_HOAE_Msk (0x80UL) /*!< HOAE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICIER ========================================================= */ + #define R_IIC0_ICIER_TMOIE_Pos (0UL) /*!< TMOIE (Bit 0) */ + #define R_IIC0_ICIER_TMOIE_Msk (0x1UL) /*!< TMOIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_ALIE_Pos (1UL) /*!< ALIE (Bit 1) */ + #define R_IIC0_ICIER_ALIE_Msk (0x2UL) /*!< ALIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_STIE_Pos (2UL) /*!< STIE (Bit 2) */ + #define R_IIC0_ICIER_STIE_Msk (0x4UL) /*!< STIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_SPIE_Pos (3UL) /*!< SPIE (Bit 3) */ + #define R_IIC0_ICIER_SPIE_Msk (0x8UL) /*!< SPIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_NAKIE_Pos (4UL) /*!< NAKIE (Bit 4) */ + #define R_IIC0_ICIER_NAKIE_Msk (0x10UL) /*!< NAKIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_RIE_Pos (5UL) /*!< RIE (Bit 5) */ + #define R_IIC0_ICIER_RIE_Msk (0x20UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TEIE_Pos (6UL) /*!< TEIE (Bit 6) */ + #define R_IIC0_ICIER_TEIE_Msk (0x40UL) /*!< TEIE (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICIER_TIE_Pos (7UL) /*!< TIE (Bit 7) */ + #define R_IIC0_ICIER_TIE_Msk (0x80UL) /*!< TIE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR1 ========================================================= */ + #define R_IIC0_ICSR1_AAS0_Pos (0UL) /*!< AAS0 (Bit 0) */ + #define R_IIC0_ICSR1_AAS0_Msk (0x1UL) /*!< AAS0 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS1_Pos (1UL) /*!< AAS1 (Bit 1) */ + #define R_IIC0_ICSR1_AAS1_Msk (0x2UL) /*!< AAS1 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_AAS2_Pos (2UL) /*!< AAS2 (Bit 2) */ + #define R_IIC0_ICSR1_AAS2_Msk (0x4UL) /*!< AAS2 (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_GCA_Pos (3UL) /*!< GCA (Bit 3) */ + #define R_IIC0_ICSR1_GCA_Msk (0x8UL) /*!< GCA (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_DID_Pos (5UL) /*!< DID (Bit 5) */ + #define R_IIC0_ICSR1_DID_Msk (0x20UL) /*!< DID (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR1_HOA_Pos (7UL) /*!< HOA (Bit 7) */ + #define R_IIC0_ICSR1_HOA_Msk (0x80UL) /*!< HOA (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_IIC0_ICSR2_TMOF_Pos (0UL) /*!< TMOF (Bit 0) */ + #define R_IIC0_ICSR2_TMOF_Msk (0x1UL) /*!< TMOF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_AL_Pos (1UL) /*!< AL (Bit 1) */ + #define R_IIC0_ICSR2_AL_Msk (0x2UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_START_Pos (2UL) /*!< START (Bit 2) */ + #define R_IIC0_ICSR2_START_Msk (0x4UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_STOP_Pos (3UL) /*!< STOP (Bit 3) */ + #define R_IIC0_ICSR2_STOP_Msk (0x8UL) /*!< STOP (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_NACKF_Pos (4UL) /*!< NACKF (Bit 4) */ + #define R_IIC0_ICSR2_NACKF_Msk (0x10UL) /*!< NACKF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_RDRF_Pos (5UL) /*!< RDRF (Bit 5) */ + #define R_IIC0_ICSR2_RDRF_Msk (0x20UL) /*!< RDRF (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TEND_Pos (6UL) /*!< TEND (Bit 6) */ + #define R_IIC0_ICSR2_TEND_Msk (0x40UL) /*!< TEND (Bitfield-Mask: 0x01) */ + #define R_IIC0_ICSR2_TDRE_Pos (7UL) /*!< TDRE (Bit 7) */ + #define R_IIC0_ICSR2_TDRE_Msk (0x80UL) /*!< TDRE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICBRL ========================================================= */ + #define R_IIC0_ICBRL_BRL_Pos (0UL) /*!< BRL (Bit 0) */ + #define R_IIC0_ICBRL_BRL_Msk (0x1fUL) /*!< BRL (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICBRH ========================================================= */ + #define R_IIC0_ICBRH_BRH_Pos (0UL) /*!< BRH (Bit 0) */ + #define R_IIC0_ICBRH_BRH_Msk (0x1fUL) /*!< BRH (Bitfield-Mask: 0x1f) */ +/* ========================================================= ICDRT ========================================================= */ +/* ========================================================= ICDRR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_DOC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= DOCR ========================================================== */ + #define R_DOC_DOCR_OMS_Pos (0UL) /*!< OMS (Bit 0) */ + #define R_DOC_DOCR_OMS_Msk (0x3UL) /*!< OMS (Bitfield-Mask: 0x03) */ + #define R_DOC_DOCR_DCSEL_Pos (2UL) /*!< DCSEL (Bit 2) */ + #define R_DOC_DOCR_DCSEL_Msk (0x4UL) /*!< DCSEL (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCIE_Pos (4UL) /*!< DOPCIE (Bit 4) */ + #define R_DOC_DOCR_DOPCIE_Msk (0x10UL) /*!< DOPCIE (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCF_Pos (5UL) /*!< DOPCF (Bit 5) */ + #define R_DOC_DOCR_DOPCF_Msk (0x20UL) /*!< DOPCF (Bitfield-Mask: 0x01) */ + #define R_DOC_DOCR_DOPCFCL_Pos (6UL) /*!< DOPCFCL (Bit 6) */ + #define R_DOC_DOCR_DOPCFCL_Msk (0x40UL) /*!< DOPCFCL (Bitfield-Mask: 0x01) */ +/* ========================================================= DODIR ========================================================= */ +/* ========================================================= DODSR ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_ADC121 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ADCSR ========================================================= */ + #define R_ADC121_ADCSR_DBLANS_Pos (0UL) /*!< DBLANS (Bit 0) */ + #define R_ADC121_ADCSR_DBLANS_Msk (0x1fUL) /*!< DBLANS (Bitfield-Mask: 0x1f) */ + #define R_ADC121_ADCSR_GBADIE_Pos (6UL) /*!< GBADIE (Bit 6) */ + #define R_ADC121_ADCSR_GBADIE_Msk (0x40UL) /*!< GBADIE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCSR_DBLE_Pos (7UL) /*!< DBLE (Bit 7) */ + #define R_ADC121_ADCSR_DBLE_Msk (0x80UL) /*!< DBLE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCSR_EXTRG_Pos (8UL) /*!< EXTRG (Bit 8) */ + #define R_ADC121_ADCSR_EXTRG_Msk (0x100UL) /*!< EXTRG (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCSR_TRGE_Pos (9UL) /*!< TRGE (Bit 9) */ + #define R_ADC121_ADCSR_TRGE_Msk (0x200UL) /*!< TRGE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCSR_ADIE_Pos (12UL) /*!< ADIE (Bit 12) */ + #define R_ADC121_ADCSR_ADIE_Msk (0x1000UL) /*!< ADIE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCSR_ADCS_Pos (13UL) /*!< ADCS (Bit 13) */ + #define R_ADC121_ADCSR_ADCS_Msk (0x6000UL) /*!< ADCS (Bitfield-Mask: 0x03) */ + #define R_ADC121_ADCSR_ADST_Pos (15UL) /*!< ADST (Bit 15) */ + #define R_ADC121_ADCSR_ADST_Msk (0x8000UL) /*!< ADST (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSA0 ======================================================== */ + #define R_ADC121_ADANSA0_ANSA0_Pos (0UL) /*!< ANSA0 (Bit 0) */ + #define R_ADC121_ADANSA0_ANSA0_Msk (0xffUL) /*!< ANSA0 (Bitfield-Mask: 0xff) */ +/* ======================================================== ADADS0 ========================================================= */ + #define R_ADC121_ADADS0_ADS0_Pos (0UL) /*!< ADS0 (Bit 0) */ + #define R_ADC121_ADADS0_ADS0_Msk (0xffUL) /*!< ADS0 (Bitfield-Mask: 0xff) */ +/* ========================================================= ADADC ========================================================= */ + #define R_ADC121_ADADC_ADC_Pos (0UL) /*!< ADC (Bit 0) */ + #define R_ADC121_ADADC_ADC_Msk (0x7UL) /*!< ADC (Bitfield-Mask: 0x07) */ + #define R_ADC121_ADADC_AVEE_Pos (7UL) /*!< AVEE (Bit 7) */ + #define R_ADC121_ADADC_AVEE_Msk (0x80UL) /*!< AVEE (Bitfield-Mask: 0x01) */ +/* ========================================================= ADCER ========================================================= */ + #define R_ADC121_ADCER_ADPRC_Pos (1UL) /*!< ADPRC (Bit 1) */ + #define R_ADC121_ADCER_ADPRC_Msk (0x6UL) /*!< ADPRC (Bitfield-Mask: 0x03) */ + #define R_ADC121_ADCER_ACE_Pos (5UL) /*!< ACE (Bit 5) */ + #define R_ADC121_ADCER_ACE_Msk (0x20UL) /*!< ACE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCER_ADRFMT_Pos (15UL) /*!< ADRFMT (Bit 15) */ + #define R_ADC121_ADCER_ADRFMT_Msk (0x8000UL) /*!< ADRFMT (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSTRGR ======================================================== */ + #define R_ADC121_ADSTRGR_TRSB_Pos (0UL) /*!< TRSB (Bit 0) */ + #define R_ADC121_ADSTRGR_TRSB_Msk (0x3fUL) /*!< TRSB (Bitfield-Mask: 0x3f) */ + #define R_ADC121_ADSTRGR_TRSA_Pos (8UL) /*!< TRSA (Bit 8) */ + #define R_ADC121_ADSTRGR_TRSA_Msk (0x3f00UL) /*!< TRSA (Bitfield-Mask: 0x3f) */ +/* ======================================================== ADANSB0 ======================================================== */ + #define R_ADC121_ADANSB0_ANSB0_Pos (0UL) /*!< ANSB0 (Bit 0) */ + #define R_ADC121_ADANSB0_ANSB0_Msk (0xffUL) /*!< ANSB0 (Bitfield-Mask: 0xff) */ +/* ======================================================== ADDBLDR ======================================================== */ + #define R_ADC121_ADDBLDR_DBLDR_Pos (0UL) /*!< DBLDR (Bit 0) */ + #define R_ADC121_ADDBLDR_DBLDR_Msk (0xffffUL) /*!< DBLDR (Bitfield-Mask: 0xffff) */ +/* ========================================================= ADDR ========================================================== */ + #define R_ADC121_ADDR_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_ADC121_ADDR_DR_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff) */ +/* ======================================================== ADSHCR ========================================================= */ + #define R_ADC121_ADSHCR_SSTSH_Pos (0UL) /*!< SSTSH (Bit 0) */ + #define R_ADC121_ADSHCR_SSTSH_Msk (0xffUL) /*!< SSTSH (Bitfield-Mask: 0xff) */ + #define R_ADC121_ADSHCR_SHANS_Pos (8UL) /*!< SHANS (Bit 8) */ + #define R_ADC121_ADSHCR_SHANS_Msk (0x700UL) /*!< SHANS (Bitfield-Mask: 0x07) */ +/* ======================================================== ADELCCR ======================================================== */ + #define R_ADC121_ADELCCR_ELCC_Pos (0UL) /*!< ELCC (Bit 0) */ + #define R_ADC121_ADELCCR_ELCC_Msk (0x3UL) /*!< ELCC (Bitfield-Mask: 0x03) */ + #define R_ADC121_ADELCCR_GCELC_Pos (2UL) /*!< GCELC (Bit 2) */ + #define R_ADC121_ADELCCR_GCELC_Msk (0x4UL) /*!< GCELC (Bitfield-Mask: 0x01) */ +/* ======================================================== ADGSPCR ======================================================== */ + #define R_ADC121_ADGSPCR_PGS_Pos (0UL) /*!< PGS (Bit 0) */ + #define R_ADC121_ADGSPCR_PGS_Msk (0x1UL) /*!< PGS (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADGSPCR_GBRSCN_Pos (1UL) /*!< GBRSCN (Bit 1) */ + #define R_ADC121_ADGSPCR_GBRSCN_Msk (0x2UL) /*!< GBRSCN (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADGSPCR_LGRRS_Pos (14UL) /*!< LGRRS (Bit 14) */ + #define R_ADC121_ADGSPCR_LGRRS_Msk (0x4000UL) /*!< LGRRS (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADGSPCR_GBRP_Pos (15UL) /*!< GBRP (Bit 15) */ + #define R_ADC121_ADGSPCR_GBRP_Msk (0x8000UL) /*!< GBRP (Bitfield-Mask: 0x01) */ +/* ======================================================= ADDBLDRA ======================================================== */ + #define R_ADC121_ADDBLDRA_DBLDRA_Pos (0UL) /*!< DBLDRA (Bit 0) */ + #define R_ADC121_ADDBLDRA_DBLDRA_Msk (0xffffUL) /*!< DBLDRA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADDBLDRB ======================================================== */ + #define R_ADC121_ADDBLDRB_DBLDRB_Pos (0UL) /*!< DBLDRB (Bit 0) */ + #define R_ADC121_ADDBLDRB_DBLDRB_Msk (0xffffUL) /*!< DBLDRB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINMON ======================================================== */ + #define R_ADC121_ADWINMON_MONCOMB_Pos (0UL) /*!< MONCOMB (Bit 0) */ + #define R_ADC121_ADWINMON_MONCOMB_Msk (0x1UL) /*!< MONCOMB (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADWINMON_MONCMPA_Pos (4UL) /*!< MONCMPA (Bit 4) */ + #define R_ADC121_ADWINMON_MONCMPA_Msk (0x10UL) /*!< MONCMPA (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADWINMON_MONCMPB_Pos (5UL) /*!< MONCMPB (Bit 5) */ + #define R_ADC121_ADWINMON_MONCMPB_Msk (0x20UL) /*!< MONCMPB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADCMPCR ======================================================== */ + #define R_ADC121_ADCMPCR_CMPAB_Pos (0UL) /*!< CMPAB (Bit 0) */ + #define R_ADC121_ADCMPCR_CMPAB_Msk (0x3UL) /*!< CMPAB (Bitfield-Mask: 0x03) */ + #define R_ADC121_ADCMPCR_CMPBE_Pos (9UL) /*!< CMPBE (Bit 9) */ + #define R_ADC121_ADCMPCR_CMPBE_Msk (0x200UL) /*!< CMPBE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCMPCR_CMPAE_Pos (11UL) /*!< CMPAE (Bit 11) */ + #define R_ADC121_ADCMPCR_CMPAE_Msk (0x800UL) /*!< CMPAE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCMPCR_CMPBIE_Pos (13UL) /*!< CMPBIE (Bit 13) */ + #define R_ADC121_ADCMPCR_CMPBIE_Msk (0x2000UL) /*!< CMPBIE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCMPCR_WCMPE_Pos (14UL) /*!< WCMPE (Bit 14) */ + #define R_ADC121_ADCMPCR_WCMPE_Msk (0x4000UL) /*!< WCMPE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADCMPCR_CMPAIE_Pos (15UL) /*!< CMPAIE (Bit 15) */ + #define R_ADC121_ADCMPCR_CMPAIE_Msk (0x8000UL) /*!< CMPAIE (Bitfield-Mask: 0x01) */ +/* ====================================================== ADCMPANSR0 ======================================================= */ + #define R_ADC121_ADCMPANSR0_CMPCHA0_Pos (0UL) /*!< CMPCHA0 (Bit 0) */ + #define R_ADC121_ADCMPANSR0_CMPCHA0_Msk (0xffUL) /*!< CMPCHA0 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCMPLR0 ======================================================== */ + #define R_ADC121_ADCMPLR0_CMPLCHA0_Pos (0UL) /*!< CMPLCHA0 (Bit 0) */ + #define R_ADC121_ADCMPLR0_CMPLCHA0_Msk (0xffUL) /*!< CMPLCHA0 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCMPDR0 ======================================================== */ + #define R_ADC121_ADCMPDR0_CMPLLA_Pos (0UL) /*!< CMPLLA (Bit 0) */ + #define R_ADC121_ADCMPDR0_CMPLLA_Msk (0xffffUL) /*!< CMPLLA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPDR1 ======================================================== */ + #define R_ADC121_ADCMPDR1_CMPULA_Pos (0UL) /*!< CMPULA (Bit 0) */ + #define R_ADC121_ADCMPDR1_CMPULA_Msk (0xffffUL) /*!< CMPULA (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPSR0 ======================================================== */ + #define R_ADC121_ADCMPSR0_CMPSTCHA0_Pos (0UL) /*!< CMPSTCHA0 (Bit 0) */ + #define R_ADC121_ADCMPSR0_CMPSTCHA0_Msk (0xffUL) /*!< CMPSTCHA0 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADCMPBNSR ======================================================= */ + #define R_ADC121_ADCMPBNSR_CMPCHB_Pos (0UL) /*!< CMPCHB (Bit 0) */ + #define R_ADC121_ADCMPBNSR_CMPCHB_Msk (0x3fUL) /*!< CMPCHB (Bitfield-Mask: 0x3f) */ + #define R_ADC121_ADCMPBNSR_CMPLB_Pos (7UL) /*!< CMPLB (Bit 7) */ + #define R_ADC121_ADCMPBNSR_CMPLB_Msk (0x80UL) /*!< CMPLB (Bitfield-Mask: 0x01) */ +/* ======================================================= ADWINLLB ======================================================== */ + #define R_ADC121_ADWINLLB_CMPLLB_Pos (0UL) /*!< CMPLLB (Bit 0) */ + #define R_ADC121_ADWINLLB_CMPLLB_Msk (0xffffUL) /*!< CMPLLB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADWINULB ======================================================== */ + #define R_ADC121_ADWINULB_CMPULB_Pos (0UL) /*!< CMPULB (Bit 0) */ + #define R_ADC121_ADWINULB_CMPULB_Msk (0xffffUL) /*!< CMPULB (Bitfield-Mask: 0xffff) */ +/* ======================================================= ADCMPBSR ======================================================== */ + #define R_ADC121_ADCMPBSR_CMPSTB_Pos (0UL) /*!< CMPSTB (Bit 0) */ + #define R_ADC121_ADCMPBSR_CMPSTB_Msk (0x1UL) /*!< CMPSTB (Bitfield-Mask: 0x01) */ +/* ======================================================== ADANSC0 ======================================================== */ + #define R_ADC121_ADANSC0_ANSC0_Pos (0UL) /*!< ANSC0 (Bit 0) */ + #define R_ADC121_ADANSC0_ANSC0_Msk (0xffUL) /*!< ANSC0 (Bitfield-Mask: 0xff) */ +/* ======================================================= ADGCTRGR ======================================================== */ + #define R_ADC121_ADGCTRGR_TRSC_Pos (0UL) /*!< TRSC (Bit 0) */ + #define R_ADC121_ADGCTRGR_TRSC_Msk (0x3fUL) /*!< TRSC (Bitfield-Mask: 0x3f) */ + #define R_ADC121_ADGCTRGR_GCADIE_Pos (6UL) /*!< GCADIE (Bit 6) */ + #define R_ADC121_ADGCTRGR_GCADIE_Msk (0x40UL) /*!< GCADIE (Bitfield-Mask: 0x01) */ + #define R_ADC121_ADGCTRGR_GRCE_Pos (7UL) /*!< GRCE (Bit 7) */ + #define R_ADC121_ADGCTRGR_GRCE_Msk (0x80UL) /*!< GRCE (Bitfield-Mask: 0x01) */ +/* ======================================================== ADSSTR ========================================================= */ + #define R_ADC121_ADSSTR_SST_Pos (0UL) /*!< SST (Bit 0) */ + #define R_ADC121_ADSSTR_SST_Msk (0xffUL) /*!< SST (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_TSU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TSUSM ========================================================= */ + #define R_TSU_TSUSM_TSEN_Pos (0UL) /*!< TSEN (Bit 0) */ + #define R_TSU_TSUSM_TSEN_Msk (0x1UL) /*!< TSEN (Bitfield-Mask: 0x01) */ + #define R_TSU_TSUSM_ADCEN_Pos (1UL) /*!< ADCEN (Bit 1) */ + #define R_TSU_TSUSM_ADCEN_Msk (0x2UL) /*!< ADCEN (Bitfield-Mask: 0x01) */ +/* ========================================================= TSUST ========================================================= */ + #define R_TSU_TSUST_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_TSU_TSUST_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ +/* ======================================================== TSUSCS ========================================================= */ + #define R_TSU_TSUSCS_CKDIV_Pos (3UL) /*!< CKDIV (Bit 3) */ + #define R_TSU_TSUSCS_CKDIV_Msk (0x8UL) /*!< CKDIV (Bitfield-Mask: 0x01) */ +/* ======================================================== TSUSAD ========================================================= */ + #define R_TSU_TSUSAD_DOUT_Pos (0UL) /*!< DOUT (Bit 0) */ + #define R_TSU_TSUSAD_DOUT_Msk (0xfffUL) /*!< DOUT (Bitfield-Mask: 0xfff) */ +/* ========================================================= TSUSS ========================================================= */ + #define R_TSU_TSUSS_CONV_Pos (0UL) /*!< CONV (Bit 0) */ + #define R_TSU_TSUSS_CONV_Msk (0x1UL) /*!< CONV (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG1 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== POEG1GA ======================================================== */ + #define R_POEG1_POEG1GA_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GA_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GA_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GA_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GA_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GA_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GA_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GA_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GA_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GA_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GA_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GA_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GA_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG1GB ======================================================== */ + #define R_POEG1_POEG1GB_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GB_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GB_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GB_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GB_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GB_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GB_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GB_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GB_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GB_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GB_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GB_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GB_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG1GC ======================================================== */ + #define R_POEG1_POEG1GC_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GC_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GC_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GC_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GC_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GC_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GC_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GC_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GC_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GC_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GC_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GC_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GC_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG1GD ======================================================== */ + #define R_POEG1_POEG1GD_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG1_POEG1GD_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG1_POEG1GD_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG1_POEG1GD_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG1_POEG1GD_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG1_POEG1GD_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG1_POEG1GD_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG1_POEG1GD_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG1_POEG1GD_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG1_POEG1GD_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG1_POEG1GD_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG1_POEG1GD_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG1_POEG1GD_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_DMAC0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_ICU_NS ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= NS_SWINT ======================================================== */ + #define R_ICU_NS_NS_SWINT_IC0_Pos (0UL) /*!< IC0 (Bit 0) */ + #define R_ICU_NS_NS_SWINT_IC0_Msk (0x1UL) /*!< IC0 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC1_Pos (1UL) /*!< IC1 (Bit 1) */ + #define R_ICU_NS_NS_SWINT_IC1_Msk (0x2UL) /*!< IC1 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC2_Pos (2UL) /*!< IC2 (Bit 2) */ + #define R_ICU_NS_NS_SWINT_IC2_Msk (0x4UL) /*!< IC2 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC3_Pos (3UL) /*!< IC3 (Bit 3) */ + #define R_ICU_NS_NS_SWINT_IC3_Msk (0x8UL) /*!< IC3 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC4_Pos (4UL) /*!< IC4 (Bit 4) */ + #define R_ICU_NS_NS_SWINT_IC4_Msk (0x10UL) /*!< IC4 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_SWINT_IC5_Pos (5UL) /*!< IC5 (Bit 5) */ + #define R_ICU_NS_NS_SWINT_IC5_Msk (0x20UL) /*!< IC5 (Bitfield-Mask: 0x01) */ +/* =================================================== NS_PORTNF_FLTSEL ==================================================== */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Pos (0UL) /*!< FLT0 (Bit 0) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT0_Msk (0x1UL) /*!< FLT0 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Pos (1UL) /*!< FLT1 (Bit 1) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT1_Msk (0x2UL) /*!< FLT1 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Pos (2UL) /*!< FLT2 (Bit 2) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT2_Msk (0x4UL) /*!< FLT2 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Pos (3UL) /*!< FLT3 (Bit 3) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT3_Msk (0x8UL) /*!< FLT3 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Pos (4UL) /*!< FLT4 (Bit 4) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT4_Msk (0x10UL) /*!< FLT4 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Pos (5UL) /*!< FLT5 (Bit 5) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT5_Msk (0x20UL) /*!< FLT5 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Pos (6UL) /*!< FLT6 (Bit 6) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT6_Msk (0x40UL) /*!< FLT6 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Pos (7UL) /*!< FLT7 (Bit 7) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT7_Msk (0x80UL) /*!< FLT7 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Pos (8UL) /*!< FLT8 (Bit 8) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT8_Msk (0x100UL) /*!< FLT8 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Pos (9UL) /*!< FLT9 (Bit 9) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT9_Msk (0x200UL) /*!< FLT9 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Pos (10UL) /*!< FLT10 (Bit 10) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT10_Msk (0x400UL) /*!< FLT10 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Pos (11UL) /*!< FLT11 (Bit 11) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT11_Msk (0x800UL) /*!< FLT11 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Pos (12UL) /*!< FLT12 (Bit 12) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT12_Msk (0x1000UL) /*!< FLT12 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Pos (13UL) /*!< FLT13 (Bit 13) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLT13_Msk (0x2000UL) /*!< FLT13 (Bitfield-Mask: 0x01) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Pos (14UL) /*!< FLTDRQ (Bit 14) */ + #define R_ICU_NS_NS_PORTNF_FLTSEL_FLTDRQ_Msk (0x4000UL) /*!< FLTDRQ (Bitfield-Mask: 0x01) */ +/* =================================================== NS_PORTNF_CLKSEL ==================================================== */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Pos (0UL) /*!< CKSEL0 (Bit 0) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL0_Msk (0x3UL) /*!< CKSEL0 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Pos (2UL) /*!< CKSEL1 (Bit 2) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL1_Msk (0xcUL) /*!< CKSEL1 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Pos (4UL) /*!< CKSEL2 (Bit 4) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL2_Msk (0x30UL) /*!< CKSEL2 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Pos (6UL) /*!< CKSEL3 (Bit 6) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL3_Msk (0xc0UL) /*!< CKSEL3 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Pos (8UL) /*!< CKSEL4 (Bit 8) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL4_Msk (0x300UL) /*!< CKSEL4 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Pos (10UL) /*!< CKSEL5 (Bit 10) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL5_Msk (0xc00UL) /*!< CKSEL5 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Pos (12UL) /*!< CKSEL6 (Bit 12) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL6_Msk (0x3000UL) /*!< CKSEL6 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Pos (14UL) /*!< CKSEL7 (Bit 14) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL7_Msk (0xc000UL) /*!< CKSEL7 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Pos (16UL) /*!< CKSEL8 (Bit 16) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL8_Msk (0x30000UL) /*!< CKSEL8 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Pos (18UL) /*!< CKSEL9 (Bit 18) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL9_Msk (0xc0000UL) /*!< CKSEL9 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Pos (20UL) /*!< CKSEL10 (Bit 20) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL10_Msk (0x300000UL) /*!< CKSEL10 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Pos (22UL) /*!< CKSEL11 (Bit 22) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL11_Msk (0xc00000UL) /*!< CKSEL11 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Pos (24UL) /*!< CKSEL12 (Bit 24) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL12_Msk (0x3000000UL) /*!< CKSEL12 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Pos (26UL) /*!< CKSEL13 (Bit 26) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSEL13_Msk (0xc000000UL) /*!< CKSEL13 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Pos (28UL) /*!< CKSELDREQ (Bit 28) */ + #define R_ICU_NS_NS_PORTNF_CLKSEL_CKSELDREQ_Msk (0x30000000UL) /*!< CKSELDREQ (Bitfield-Mask: 0x03) */ +/* ===================================================== NS_PORTNF_MD ====================================================== */ + #define R_ICU_NS_NS_PORTNF_MD_MD0_Pos (0UL) /*!< MD0 (Bit 0) */ + #define R_ICU_NS_NS_PORTNF_MD_MD0_Msk (0x3UL) /*!< MD0 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD1_Pos (2UL) /*!< MD1 (Bit 2) */ + #define R_ICU_NS_NS_PORTNF_MD_MD1_Msk (0xcUL) /*!< MD1 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD2_Pos (4UL) /*!< MD2 (Bit 4) */ + #define R_ICU_NS_NS_PORTNF_MD_MD2_Msk (0x30UL) /*!< MD2 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD3_Pos (6UL) /*!< MD3 (Bit 6) */ + #define R_ICU_NS_NS_PORTNF_MD_MD3_Msk (0xc0UL) /*!< MD3 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD4_Pos (8UL) /*!< MD4 (Bit 8) */ + #define R_ICU_NS_NS_PORTNF_MD_MD4_Msk (0x300UL) /*!< MD4 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD5_Pos (10UL) /*!< MD5 (Bit 10) */ + #define R_ICU_NS_NS_PORTNF_MD_MD5_Msk (0xc00UL) /*!< MD5 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD6_Pos (12UL) /*!< MD6 (Bit 12) */ + #define R_ICU_NS_NS_PORTNF_MD_MD6_Msk (0x3000UL) /*!< MD6 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD7_Pos (14UL) /*!< MD7 (Bit 14) */ + #define R_ICU_NS_NS_PORTNF_MD_MD7_Msk (0xc000UL) /*!< MD7 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD8_Pos (16UL) /*!< MD8 (Bit 16) */ + #define R_ICU_NS_NS_PORTNF_MD_MD8_Msk (0x30000UL) /*!< MD8 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD9_Pos (18UL) /*!< MD9 (Bit 18) */ + #define R_ICU_NS_NS_PORTNF_MD_MD9_Msk (0xc0000UL) /*!< MD9 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD10_Pos (20UL) /*!< MD10 (Bit 20) */ + #define R_ICU_NS_NS_PORTNF_MD_MD10_Msk (0x300000UL) /*!< MD10 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD11_Pos (22UL) /*!< MD11 (Bit 22) */ + #define R_ICU_NS_NS_PORTNF_MD_MD11_Msk (0xc00000UL) /*!< MD11 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD12_Pos (24UL) /*!< MD12 (Bit 24) */ + #define R_ICU_NS_NS_PORTNF_MD_MD12_Msk (0x3000000UL) /*!< MD12 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MD13_Pos (26UL) /*!< MD13 (Bit 26) */ + #define R_ICU_NS_NS_PORTNF_MD_MD13_Msk (0xc000000UL) /*!< MD13 (Bitfield-Mask: 0x03) */ + #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Pos (28UL) /*!< MDDRQ (Bit 28) */ + #define R_ICU_NS_NS_PORTNF_MD_MDDRQ_Msk (0x30000000UL) /*!< MDDRQ (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_ELC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ELC_SSEL ======================================================== */ + #define R_ELC_ELC_SSEL_ELC_SEL0_Pos (0UL) /*!< ELC_SEL0 (Bit 0) */ + #define R_ELC_ELC_SSEL_ELC_SEL0_Msk (0x3ffUL) /*!< ELC_SEL0 (Bitfield-Mask: 0x3ff) */ + #define R_ELC_ELC_SSEL_ELC_SEL1_Pos (10UL) /*!< ELC_SEL1 (Bit 10) */ + #define R_ELC_ELC_SSEL_ELC_SEL1_Msk (0xffc00UL) /*!< ELC_SEL1 (Bitfield-Mask: 0x3ff) */ + #define R_ELC_ELC_SSEL_ELC_SEL2_Pos (20UL) /*!< ELC_SEL2 (Bit 20) */ + #define R_ELC_ELC_SSEL_ELC_SEL2_Msk (0x3ff00000UL) /*!< ELC_SEL2 (Bitfield-Mask: 0x3ff) */ + +/* =========================================================================================================================== */ +/* ================ R_DMA ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== DMAC0_RSSEL ====================================================== */ + #define R_DMA_DMAC0_RSSEL_REQ_SELA_Pos (0UL) /*!< REQ_SELA (Bit 0) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELA_Msk (0x1ffUL) /*!< REQ_SELA (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELB_Pos (10UL) /*!< REQ_SELB (Bit 10) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELB_Msk (0x7fc00UL) /*!< REQ_SELB (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELC_Pos (20UL) /*!< REQ_SELC (Bit 20) */ + #define R_DMA_DMAC0_RSSEL_REQ_SELC_Msk (0x1ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x1ff) */ +/* ====================================================== DMAC1_RSSEL ====================================================== */ + #define R_DMA_DMAC1_RSSEL_REQ_SELA_Pos (0UL) /*!< REQ_SELA (Bit 0) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELA_Msk (0x1ffUL) /*!< REQ_SELA (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELB_Pos (10UL) /*!< REQ_SELB (Bit 10) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELB_Msk (0x7fc00UL) /*!< REQ_SELB (Bitfield-Mask: 0x1ff) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELC_Pos (20UL) /*!< REQ_SELC (Bit 20) */ + #define R_DMA_DMAC1_RSSEL_REQ_SELC_Msk (0x1ff00000UL) /*!< REQ_SELC (Bitfield-Mask: 0x1ff) */ + +/* =========================================================================================================================== */ +/* ================ R_PORT_COMMON ================ */ +/* =========================================================================================================================== */ + +/* =========================================================== P =========================================================== */ + #define R_PORT_NSR_P_POUT_0_Pos (0UL) /*!< POUT_0 (Bit 0) */ + #define R_PORT_NSR_P_POUT_0_Msk (0x1UL) /*!< POUT_0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_1_Pos (1UL) /*!< POUT_1 (Bit 1) */ + #define R_PORT_NSR_P_POUT_1_Msk (0x2UL) /*!< POUT_1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_2_Pos (2UL) /*!< POUT_2 (Bit 2) */ + #define R_PORT_NSR_P_POUT_2_Msk (0x4UL) /*!< POUT_2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_3_Pos (3UL) /*!< POUT_3 (Bit 3) */ + #define R_PORT_NSR_P_POUT_3_Msk (0x8UL) /*!< POUT_3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_4_Pos (4UL) /*!< POUT_4 (Bit 4) */ + #define R_PORT_NSR_P_POUT_4_Msk (0x10UL) /*!< POUT_4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_5_Pos (5UL) /*!< POUT_5 (Bit 5) */ + #define R_PORT_NSR_P_POUT_5_Msk (0x20UL) /*!< POUT_5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_6_Pos (6UL) /*!< POUT_6 (Bit 6) */ + #define R_PORT_NSR_P_POUT_6_Msk (0x40UL) /*!< POUT_6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_P_POUT_7_Pos (7UL) /*!< POUT_7 (Bit 7) */ + #define R_PORT_NSR_P_POUT_7_Msk (0x80UL) /*!< POUT_7 (Bitfield-Mask: 0x01) */ +/* ========================================================== PM =========================================================== */ + #define R_PORT_NSR_PM_PM0_Pos (0UL) /*!< PM0 (Bit 0) */ + #define R_PORT_NSR_PM_PM0_Msk (0x3UL) /*!< PM0 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM1_Pos (2UL) /*!< PM1 (Bit 2) */ + #define R_PORT_NSR_PM_PM1_Msk (0xcUL) /*!< PM1 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM2_Pos (4UL) /*!< PM2 (Bit 4) */ + #define R_PORT_NSR_PM_PM2_Msk (0x30UL) /*!< PM2 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM3_Pos (6UL) /*!< PM3 (Bit 6) */ + #define R_PORT_NSR_PM_PM3_Msk (0xc0UL) /*!< PM3 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM4_Pos (8UL) /*!< PM4 (Bit 8) */ + #define R_PORT_NSR_PM_PM4_Msk (0x300UL) /*!< PM4 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM5_Pos (10UL) /*!< PM5 (Bit 10) */ + #define R_PORT_NSR_PM_PM5_Msk (0xc00UL) /*!< PM5 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM6_Pos (12UL) /*!< PM6 (Bit 12) */ + #define R_PORT_NSR_PM_PM6_Msk (0x3000UL) /*!< PM6 (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_PM_PM7_Pos (14UL) /*!< PM7 (Bit 14) */ + #define R_PORT_NSR_PM_PM7_Msk (0xc000UL) /*!< PM7 (Bitfield-Mask: 0x03) */ +/* ========================================================== PMC ========================================================== */ + #define R_PORT_NSR_PMC_PMC0_Pos (0UL) /*!< PMC0 (Bit 0) */ + #define R_PORT_NSR_PMC_PMC0_Msk (0x1UL) /*!< PMC0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC1_Pos (1UL) /*!< PMC1 (Bit 1) */ + #define R_PORT_NSR_PMC_PMC1_Msk (0x2UL) /*!< PMC1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC2_Pos (2UL) /*!< PMC2 (Bit 2) */ + #define R_PORT_NSR_PMC_PMC2_Msk (0x4UL) /*!< PMC2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC3_Pos (3UL) /*!< PMC3 (Bit 3) */ + #define R_PORT_NSR_PMC_PMC3_Msk (0x8UL) /*!< PMC3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC4_Pos (4UL) /*!< PMC4 (Bit 4) */ + #define R_PORT_NSR_PMC_PMC4_Msk (0x10UL) /*!< PMC4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC5_Pos (5UL) /*!< PMC5 (Bit 5) */ + #define R_PORT_NSR_PMC_PMC5_Msk (0x20UL) /*!< PMC5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC6_Pos (6UL) /*!< PMC6 (Bit 6) */ + #define R_PORT_NSR_PMC_PMC6_Msk (0x40UL) /*!< PMC6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PMC_PMC7_Pos (7UL) /*!< PMC7 (Bit 7) */ + #define R_PORT_NSR_PMC_PMC7_Msk (0x80UL) /*!< PMC7 (Bitfield-Mask: 0x01) */ +/* ========================================================== PFC ========================================================== */ + #define R_PORT_NSR_PFC_PFC0_Pos (0UL) /*!< PFC0 (Bit 0) */ + #define R_PORT_NSR_PFC_PFC0_Msk (0xfUL) /*!< PFC0 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC1_Pos (4UL) /*!< PFC1 (Bit 4) */ + #define R_PORT_NSR_PFC_PFC1_Msk (0xf0UL) /*!< PFC1 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC2_Pos (8UL) /*!< PFC2 (Bit 8) */ + #define R_PORT_NSR_PFC_PFC2_Msk (0xf00UL) /*!< PFC2 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC3_Pos (12UL) /*!< PFC3 (Bit 12) */ + #define R_PORT_NSR_PFC_PFC3_Msk (0xf000UL) /*!< PFC3 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC4_Pos (16UL) /*!< PFC4 (Bit 16) */ + #define R_PORT_NSR_PFC_PFC4_Msk (0xf0000UL) /*!< PFC4 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC5_Pos (20UL) /*!< PFC5 (Bit 20) */ + #define R_PORT_NSR_PFC_PFC5_Msk (0xf00000UL) /*!< PFC5 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC6_Pos (24UL) /*!< PFC6 (Bit 24) */ + #define R_PORT_NSR_PFC_PFC6_Msk (0xf000000UL) /*!< PFC6 (Bitfield-Mask: 0x0f) */ + #define R_PORT_NSR_PFC_PFC7_Pos (28UL) /*!< PFC7 (Bit 28) */ + #define R_PORT_NSR_PFC_PFC7_Msk (0xf0000000UL) /*!< PFC7 (Bitfield-Mask: 0x0f) */ +/* ========================================================== PIN ========================================================== */ + #define R_PORT_NSR_PIN_PIN0_Pos (0UL) /*!< PIN0 (Bit 0) */ + #define R_PORT_NSR_PIN_PIN0_Msk (0x1UL) /*!< PIN0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN1_Pos (1UL) /*!< PIN1 (Bit 1) */ + #define R_PORT_NSR_PIN_PIN1_Msk (0x2UL) /*!< PIN1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN2_Pos (2UL) /*!< PIN2 (Bit 2) */ + #define R_PORT_NSR_PIN_PIN2_Msk (0x4UL) /*!< PIN2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN3_Pos (3UL) /*!< PIN3 (Bit 3) */ + #define R_PORT_NSR_PIN_PIN3_Msk (0x8UL) /*!< PIN3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN4_Pos (4UL) /*!< PIN4 (Bit 4) */ + #define R_PORT_NSR_PIN_PIN4_Msk (0x10UL) /*!< PIN4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN5_Pos (5UL) /*!< PIN5 (Bit 5) */ + #define R_PORT_NSR_PIN_PIN5_Msk (0x20UL) /*!< PIN5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN6_Pos (6UL) /*!< PIN6 (Bit 6) */ + #define R_PORT_NSR_PIN_PIN6_Msk (0x40UL) /*!< PIN6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_PIN_PIN7_Pos (7UL) /*!< PIN7 (Bit 7) */ + #define R_PORT_NSR_PIN_PIN7_Msk (0x80UL) /*!< PIN7 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELC_PGR ======================================================== */ + #define R_PORT_NSR_ELC_PGR_PG0_Pos (0UL) /*!< PG0 (Bit 0) */ + #define R_PORT_NSR_ELC_PGR_PG0_Msk (0x1UL) /*!< PG0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG1_Pos (1UL) /*!< PG1 (Bit 1) */ + #define R_PORT_NSR_ELC_PGR_PG1_Msk (0x2UL) /*!< PG1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG2_Pos (2UL) /*!< PG2 (Bit 2) */ + #define R_PORT_NSR_ELC_PGR_PG2_Msk (0x4UL) /*!< PG2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG3_Pos (3UL) /*!< PG3 (Bit 3) */ + #define R_PORT_NSR_ELC_PGR_PG3_Msk (0x8UL) /*!< PG3 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG4_Pos (4UL) /*!< PG4 (Bit 4) */ + #define R_PORT_NSR_ELC_PGR_PG4_Msk (0x10UL) /*!< PG4 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG5_Pos (5UL) /*!< PG5 (Bit 5) */ + #define R_PORT_NSR_ELC_PGR_PG5_Msk (0x20UL) /*!< PG5 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG6_Pos (6UL) /*!< PG6 (Bit 6) */ + #define R_PORT_NSR_ELC_PGR_PG6_Msk (0x40UL) /*!< PG6 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGR_PG7_Pos (7UL) /*!< PG7 (Bit 7) */ + #define R_PORT_NSR_ELC_PGR_PG7_Msk (0x80UL) /*!< PG7 (Bitfield-Mask: 0x01) */ +/* ======================================================== ELC_PGC ======================================================== */ + #define R_PORT_NSR_ELC_PGC_PGCI_Pos (0UL) /*!< PGCI (Bit 0) */ + #define R_PORT_NSR_ELC_PGC_PGCI_Msk (0x3UL) /*!< PGCI (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_ELC_PGC_PGCOVE_Pos (2UL) /*!< PGCOVE (Bit 2) */ + #define R_PORT_NSR_ELC_PGC_PGCOVE_Msk (0x4UL) /*!< PGCOVE (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_PGC_PGCO_Pos (4UL) /*!< PGCO (Bit 4) */ + #define R_PORT_NSR_ELC_PGC_PGCO_Msk (0x70UL) /*!< PGCO (Bitfield-Mask: 0x07) */ +/* ======================================================== ELC_PEL ======================================================== */ + #define R_PORT_NSR_ELC_PEL_PSB_Pos (0UL) /*!< PSB (Bit 0) */ + #define R_PORT_NSR_ELC_PEL_PSB_Msk (0x7UL) /*!< PSB (Bitfield-Mask: 0x07) */ + #define R_PORT_NSR_ELC_PEL_PSP_Pos (3UL) /*!< PSP (Bit 3) */ + #define R_PORT_NSR_ELC_PEL_PSP_Msk (0x18UL) /*!< PSP (Bitfield-Mask: 0x03) */ + #define R_PORT_NSR_ELC_PEL_PSM_Pos (5UL) /*!< PSM (Bit 5) */ + #define R_PORT_NSR_ELC_PEL_PSM_Msk (0x60UL) /*!< PSM (Bitfield-Mask: 0x03) */ +/* ======================================================= ELC_DPTC ======================================================== */ + #define R_PORT_NSR_ELC_DPTC_PTC0_Pos (0UL) /*!< PTC0 (Bit 0) */ + #define R_PORT_NSR_ELC_DPTC_PTC0_Msk (0x1UL) /*!< PTC0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_DPTC_PTC1_Pos (1UL) /*!< PTC1 (Bit 1) */ + #define R_PORT_NSR_ELC_DPTC_PTC1_Msk (0x2UL) /*!< PTC1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_DPTC_PTC2_Pos (2UL) /*!< PTC2 (Bit 2) */ + #define R_PORT_NSR_ELC_DPTC_PTC2_Msk (0x4UL) /*!< PTC2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_DPTC_PTC3_Pos (3UL) /*!< PTC3 (Bit 3) */ + #define R_PORT_NSR_ELC_DPTC_PTC3_Msk (0x8UL) /*!< PTC3 (Bitfield-Mask: 0x01) */ +/* ======================================================= ELC_ELSR2 ======================================================= */ + #define R_PORT_NSR_ELC_ELSR2_PEG1_Pos (2UL) /*!< PEG1 (Bit 2) */ + #define R_PORT_NSR_ELC_ELSR2_PEG1_Msk (0x4UL) /*!< PEG1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PEG2_Pos (3UL) /*!< PEG2 (Bit 3) */ + #define R_PORT_NSR_ELC_ELSR2_PEG2_Msk (0x8UL) /*!< PEG2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES0_Pos (4UL) /*!< PES0 (Bit 4) */ + #define R_PORT_NSR_ELC_ELSR2_PES0_Msk (0x10UL) /*!< PES0 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES1_Pos (5UL) /*!< PES1 (Bit 5) */ + #define R_PORT_NSR_ELC_ELSR2_PES1_Msk (0x20UL) /*!< PES1 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES2_Pos (6UL) /*!< PES2 (Bit 6) */ + #define R_PORT_NSR_ELC_ELSR2_PES2_Msk (0x40UL) /*!< PES2 (Bitfield-Mask: 0x01) */ + #define R_PORT_NSR_ELC_ELSR2_PES3_Pos (7UL) /*!< PES3 (Bit 7) */ + #define R_PORT_NSR_ELC_ELSR2_PES3_Msk (0x80UL) /*!< PES3 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GMAC ================ */ +/* =========================================================================================================================== */ + +/* =================================================== MAC_Configuration =================================================== */ + #define R_GMAC_MAC_Configuration_PRELEN_Pos (0UL) /*!< PRELEN (Bit 0) */ + #define R_GMAC_MAC_Configuration_PRELEN_Msk (0x3UL) /*!< PRELEN (Bitfield-Mask: 0x03) */ + #define R_GMAC_MAC_Configuration_RE_Pos (2UL) /*!< RE (Bit 2) */ + #define R_GMAC_MAC_Configuration_RE_Msk (0x4UL) /*!< RE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_TE_Pos (3UL) /*!< TE (Bit 3) */ + #define R_GMAC_MAC_Configuration_TE_Msk (0x8UL) /*!< TE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DC_Pos (4UL) /*!< DC (Bit 4) */ + #define R_GMAC_MAC_Configuration_DC_Msk (0x10UL) /*!< DC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_BL_Pos (5UL) /*!< BL (Bit 5) */ + #define R_GMAC_MAC_Configuration_BL_Msk (0x60UL) /*!< BL (Bitfield-Mask: 0x03) */ + #define R_GMAC_MAC_Configuration_ACS_Pos (7UL) /*!< ACS (Bit 7) */ + #define R_GMAC_MAC_Configuration_ACS_Msk (0x80UL) /*!< ACS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DR_Pos (9UL) /*!< DR (Bit 9) */ + #define R_GMAC_MAC_Configuration_DR_Msk (0x200UL) /*!< DR (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_IPC_Pos (10UL) /*!< IPC (Bit 10) */ + #define R_GMAC_MAC_Configuration_IPC_Msk (0x400UL) /*!< IPC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DM_Pos (11UL) /*!< DM (Bit 11) */ + #define R_GMAC_MAC_Configuration_DM_Msk (0x800UL) /*!< DM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_LM_Pos (12UL) /*!< LM (Bit 12) */ + #define R_GMAC_MAC_Configuration_LM_Msk (0x1000UL) /*!< LM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DO_Pos (13UL) /*!< DO (Bit 13) */ + #define R_GMAC_MAC_Configuration_DO_Msk (0x2000UL) /*!< DO (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_FES_Pos (14UL) /*!< FES (Bit 14) */ + #define R_GMAC_MAC_Configuration_FES_Msk (0x4000UL) /*!< FES (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_PS_Pos (15UL) /*!< PS (Bit 15) */ + #define R_GMAC_MAC_Configuration_PS_Msk (0x8000UL) /*!< PS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_DCRS_Pos (16UL) /*!< DCRS (Bit 16) */ + #define R_GMAC_MAC_Configuration_DCRS_Msk (0x10000UL) /*!< DCRS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_IFG_Pos (17UL) /*!< IFG (Bit 17) */ + #define R_GMAC_MAC_Configuration_IFG_Msk (0xe0000UL) /*!< IFG (Bitfield-Mask: 0x07) */ + #define R_GMAC_MAC_Configuration_JE_Pos (20UL) /*!< JE (Bit 20) */ + #define R_GMAC_MAC_Configuration_JE_Msk (0x100000UL) /*!< JE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_BE_Pos (21UL) /*!< BE (Bit 21) */ + #define R_GMAC_MAC_Configuration_BE_Msk (0x200000UL) /*!< BE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_JD_Pos (22UL) /*!< JD (Bit 22) */ + #define R_GMAC_MAC_Configuration_JD_Msk (0x400000UL) /*!< JD (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_WD_Pos (23UL) /*!< WD (Bit 23) */ + #define R_GMAC_MAC_Configuration_WD_Msk (0x800000UL) /*!< WD (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_CST_Pos (25UL) /*!< CST (Bit 25) */ + #define R_GMAC_MAC_Configuration_CST_Msk (0x2000000UL) /*!< CST (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Configuration_TWOKPE_Pos (27UL) /*!< TWOKPE (Bit 27) */ + #define R_GMAC_MAC_Configuration_TWOKPE_Msk (0x8000000UL) /*!< TWOKPE (Bitfield-Mask: 0x01) */ +/* =================================================== MAC_Frame_Filter ==================================================== */ + #define R_GMAC_MAC_Frame_Filter_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_GMAC_MAC_Frame_Filter_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_HUC_Pos (1UL) /*!< HUC (Bit 1) */ + #define R_GMAC_MAC_Frame_Filter_HUC_Msk (0x2UL) /*!< HUC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_HMC_Pos (2UL) /*!< HMC (Bit 2) */ + #define R_GMAC_MAC_Frame_Filter_HMC_Msk (0x4UL) /*!< HMC (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_DAIF_Pos (3UL) /*!< DAIF (Bit 3) */ + #define R_GMAC_MAC_Frame_Filter_DAIF_Msk (0x8UL) /*!< DAIF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_PM_Pos (4UL) /*!< PM (Bit 4) */ + #define R_GMAC_MAC_Frame_Filter_PM_Msk (0x10UL) /*!< PM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_DBF_Pos (5UL) /*!< DBF (Bit 5) */ + #define R_GMAC_MAC_Frame_Filter_DBF_Msk (0x20UL) /*!< DBF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_PCF_Pos (6UL) /*!< PCF (Bit 6) */ + #define R_GMAC_MAC_Frame_Filter_PCF_Msk (0xc0UL) /*!< PCF (Bitfield-Mask: 0x03) */ + #define R_GMAC_MAC_Frame_Filter_SAIF_Pos (8UL) /*!< SAIF (Bit 8) */ + #define R_GMAC_MAC_Frame_Filter_SAIF_Msk (0x100UL) /*!< SAIF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_SAF_Pos (9UL) /*!< SAF (Bit 9) */ + #define R_GMAC_MAC_Frame_Filter_SAF_Msk (0x200UL) /*!< SAF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_HPF_Pos (10UL) /*!< HPF (Bit 10) */ + #define R_GMAC_MAC_Frame_Filter_HPF_Msk (0x400UL) /*!< HPF (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_VTFE_Pos (16UL) /*!< VTFE (Bit 16) */ + #define R_GMAC_MAC_Frame_Filter_VTFE_Msk (0x10000UL) /*!< VTFE (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAC_Frame_Filter_RA_Pos (31UL) /*!< RA (Bit 31) */ + #define R_GMAC_MAC_Frame_Filter_RA_Msk (0x80000000UL) /*!< RA (Bitfield-Mask: 0x01) */ +/* ===================================================== GMII_Address ====================================================== */ + #define R_GMAC_GMII_Address_GB_Pos (0UL) /*!< GB (Bit 0) */ + #define R_GMAC_GMII_Address_GB_Msk (0x1UL) /*!< GB (Bitfield-Mask: 0x01) */ + #define R_GMAC_GMII_Address_GW_Pos (1UL) /*!< GW (Bit 1) */ + #define R_GMAC_GMII_Address_GW_Msk (0x2UL) /*!< GW (Bitfield-Mask: 0x01) */ + #define R_GMAC_GMII_Address_CR_Pos (2UL) /*!< CR (Bit 2) */ + #define R_GMAC_GMII_Address_CR_Msk (0x3cUL) /*!< CR (Bitfield-Mask: 0x0f) */ + #define R_GMAC_GMII_Address_GR_Pos (6UL) /*!< GR (Bit 6) */ + #define R_GMAC_GMII_Address_GR_Msk (0x7c0UL) /*!< GR (Bitfield-Mask: 0x1f) */ + #define R_GMAC_GMII_Address_PA_Pos (11UL) /*!< PA (Bit 11) */ + #define R_GMAC_GMII_Address_PA_Msk (0xf800UL) /*!< PA (Bitfield-Mask: 0x1f) */ +/* ======================================================= GMII_Data ======================================================= */ + #define R_GMAC_GMII_Data_GD_Pos (0UL) /*!< GD (Bit 0) */ + #define R_GMAC_GMII_Data_GD_Msk (0xffffUL) /*!< GD (Bitfield-Mask: 0xffff) */ +/* ===================================================== Flow_Control ====================================================== */ + #define R_GMAC_Flow_Control_FCA_BPA_Pos (0UL) /*!< FCA_BPA (Bit 0) */ + #define R_GMAC_Flow_Control_FCA_BPA_Msk (0x1UL) /*!< FCA_BPA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_TFE_Pos (1UL) /*!< TFE (Bit 1) */ + #define R_GMAC_Flow_Control_TFE_Msk (0x2UL) /*!< TFE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_RFE_Pos (2UL) /*!< RFE (Bit 2) */ + #define R_GMAC_Flow_Control_RFE_Msk (0x4UL) /*!< RFE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_UP_Pos (3UL) /*!< UP (Bit 3) */ + #define R_GMAC_Flow_Control_UP_Msk (0x8UL) /*!< UP (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_PLT_Pos (4UL) /*!< PLT (Bit 4) */ + #define R_GMAC_Flow_Control_PLT_Msk (0x30UL) /*!< PLT (Bitfield-Mask: 0x03) */ + #define R_GMAC_Flow_Control_DZPQ_Pos (7UL) /*!< DZPQ (Bit 7) */ + #define R_GMAC_Flow_Control_DZPQ_Msk (0x80UL) /*!< DZPQ (Bitfield-Mask: 0x01) */ + #define R_GMAC_Flow_Control_PT_Pos (16UL) /*!< PT (Bit 16) */ + #define R_GMAC_Flow_Control_PT_Msk (0xffff0000UL) /*!< PT (Bitfield-Mask: 0xffff) */ +/* ======================================================= VLAN_Tag ======================================================== */ + #define R_GMAC_VLAN_Tag_VL_Pos (0UL) /*!< VL (Bit 0) */ + #define R_GMAC_VLAN_Tag_VL_Msk (0xffffUL) /*!< VL (Bitfield-Mask: 0xffff) */ + #define R_GMAC_VLAN_Tag_ETV_Pos (16UL) /*!< ETV (Bit 16) */ + #define R_GMAC_VLAN_Tag_ETV_Msk (0x10000UL) /*!< ETV (Bitfield-Mask: 0x01) */ + #define R_GMAC_VLAN_Tag_VTIM_Pos (17UL) /*!< VTIM (Bit 17) */ + #define R_GMAC_VLAN_Tag_VTIM_Msk (0x20000UL) /*!< VTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_VLAN_Tag_ESVL_Pos (18UL) /*!< ESVL (Bit 18) */ + #define R_GMAC_VLAN_Tag_ESVL_Msk (0x40000UL) /*!< ESVL (Bitfield-Mask: 0x01) */ + #define R_GMAC_VLAN_Tag_VTHM_Pos (19UL) /*!< VTHM (Bit 19) */ + #define R_GMAC_VLAN_Tag_VTHM_Msk (0x80000UL) /*!< VTHM (Bitfield-Mask: 0x01) */ +/* ======================================================== Version ======================================================== */ + #define R_GMAC_Version_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_GMAC_Version_VER_Msk (0xffffUL) /*!< VER (Bitfield-Mask: 0xffff) */ +/* ========================================================= Debug ========================================================= */ + #define R_GMAC_Debug_RPESTS_Pos (0UL) /*!< RPESTS (Bit 0) */ + #define R_GMAC_Debug_RPESTS_Msk (0x1UL) /*!< RPESTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_RFCFCSTS_Pos (1UL) /*!< RFCFCSTS (Bit 1) */ + #define R_GMAC_Debug_RFCFCSTS_Msk (0x6UL) /*!< RFCFCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_RWCSTS_Pos (4UL) /*!< RWCSTS (Bit 4) */ + #define R_GMAC_Debug_RWCSTS_Msk (0x10UL) /*!< RWCSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_RRCSTS_Pos (5UL) /*!< RRCSTS (Bit 5) */ + #define R_GMAC_Debug_RRCSTS_Msk (0x60UL) /*!< RRCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_RXFSTS_Pos (8UL) /*!< RXFSTS (Bit 8) */ + #define R_GMAC_Debug_RXFSTS_Msk (0x300UL) /*!< RXFSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_TPESTS_Pos (16UL) /*!< TPESTS (Bit 16) */ + #define R_GMAC_Debug_TPESTS_Msk (0x10000UL) /*!< TPESTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TFCSTS_Pos (17UL) /*!< TFCSTS (Bit 17) */ + #define R_GMAC_Debug_TFCSTS_Msk (0x60000UL) /*!< TFCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_TXPAUSED_Pos (19UL) /*!< TXPAUSED (Bit 19) */ + #define R_GMAC_Debug_TXPAUSED_Msk (0x80000UL) /*!< TXPAUSED (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TRCSTS_Pos (20UL) /*!< TRCSTS (Bit 20) */ + #define R_GMAC_Debug_TRCSTS_Msk (0x300000UL) /*!< TRCSTS (Bitfield-Mask: 0x03) */ + #define R_GMAC_Debug_TWCSTS_Pos (22UL) /*!< TWCSTS (Bit 22) */ + #define R_GMAC_Debug_TWCSTS_Msk (0x400000UL) /*!< TWCSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TXFSTS_Pos (24UL) /*!< TXFSTS (Bit 24) */ + #define R_GMAC_Debug_TXFSTS_Msk (0x1000000UL) /*!< TXFSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Debug_TXSTSFSTS_Pos (25UL) /*!< TXSTSFSTS (Bit 25) */ + #define R_GMAC_Debug_TXSTSFSTS_Msk (0x2000000UL) /*!< TXSTSFSTS (Bitfield-Mask: 0x01) */ +/* ============================================== Remote_Wake_Up_Frame_Filter ============================================== */ + #define R_GMAC_Remote_Wake_Up_Frame_Filter_WKUPFRMFTR_Pos (0UL) /*!< WKUPFRMFTR (Bit 0) */ + #define R_GMAC_Remote_Wake_Up_Frame_Filter_WKUPFRMFTR_Msk (0xffffffffUL) /*!< WKUPFRMFTR (Bitfield-Mask: 0xffffffff) */ +/* ================================================== PMT_Control_Status =================================================== */ + #define R_GMAC_PMT_Control_Status_PWRDWN_Pos (0UL) /*!< PWRDWN (Bit 0) */ + #define R_GMAC_PMT_Control_Status_PWRDWN_Msk (0x1UL) /*!< PWRDWN (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_MGKPKTEN_Pos (1UL) /*!< MGKPKTEN (Bit 1) */ + #define R_GMAC_PMT_Control_Status_MGKPKTEN_Msk (0x2UL) /*!< MGKPKTEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_RWKPKTEN_Pos (2UL) /*!< RWKPKTEN (Bit 2) */ + #define R_GMAC_PMT_Control_Status_RWKPKTEN_Msk (0x4UL) /*!< RWKPKTEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_MGKPRCVD_Pos (5UL) /*!< MGKPRCVD (Bit 5) */ + #define R_GMAC_PMT_Control_Status_MGKPRCVD_Msk (0x20UL) /*!< MGKPRCVD (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_RWKPRCVD_Pos (6UL) /*!< RWKPRCVD (Bit 6) */ + #define R_GMAC_PMT_Control_Status_RWKPRCVD_Msk (0x40UL) /*!< RWKPRCVD (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_GLBLUCAST_Pos (9UL) /*!< GLBLUCAST (Bit 9) */ + #define R_GMAC_PMT_Control_Status_GLBLUCAST_Msk (0x200UL) /*!< GLBLUCAST (Bitfield-Mask: 0x01) */ + #define R_GMAC_PMT_Control_Status_RWKPTR_Pos (24UL) /*!< RWKPTR (Bit 24) */ + #define R_GMAC_PMT_Control_Status_RWKPTR_Msk (0x7000000UL) /*!< RWKPTR (Bitfield-Mask: 0x07) */ + #define R_GMAC_PMT_Control_Status_RWKFILTRST_Pos (31UL) /*!< RWKFILTRST (Bit 31) */ + #define R_GMAC_PMT_Control_Status_RWKFILTRST_Msk (0x80000000UL) /*!< RWKFILTRST (Bitfield-Mask: 0x01) */ +/* ================================================== LPI_Control_Status =================================================== */ + #define R_GMAC_LPI_Control_Status_TLPIEN_Pos (0UL) /*!< TLPIEN (Bit 0) */ + #define R_GMAC_LPI_Control_Status_TLPIEN_Msk (0x1UL) /*!< TLPIEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_TLPIEX_Pos (1UL) /*!< TLPIEX (Bit 1) */ + #define R_GMAC_LPI_Control_Status_TLPIEX_Msk (0x2UL) /*!< TLPIEX (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_RLPIEN_Pos (2UL) /*!< RLPIEN (Bit 2) */ + #define R_GMAC_LPI_Control_Status_RLPIEN_Msk (0x4UL) /*!< RLPIEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_RLPIEX_Pos (3UL) /*!< RLPIEX (Bit 3) */ + #define R_GMAC_LPI_Control_Status_RLPIEX_Msk (0x8UL) /*!< RLPIEX (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_TLPIST_Pos (8UL) /*!< TLPIST (Bit 8) */ + #define R_GMAC_LPI_Control_Status_TLPIST_Msk (0x100UL) /*!< TLPIST (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_RLPIST_Pos (9UL) /*!< RLPIST (Bit 9) */ + #define R_GMAC_LPI_Control_Status_RLPIST_Msk (0x200UL) /*!< RLPIST (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_LPIEN_Pos (16UL) /*!< LPIEN (Bit 16) */ + #define R_GMAC_LPI_Control_Status_LPIEN_Msk (0x10000UL) /*!< LPIEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_PLS_Pos (17UL) /*!< PLS (Bit 17) */ + #define R_GMAC_LPI_Control_Status_PLS_Msk (0x20000UL) /*!< PLS (Bitfield-Mask: 0x01) */ + #define R_GMAC_LPI_Control_Status_LPITXA_Pos (19UL) /*!< LPITXA (Bit 19) */ + #define R_GMAC_LPI_Control_Status_LPITXA_Msk (0x80000UL) /*!< LPITXA (Bitfield-Mask: 0x01) */ +/* ================================================== LPI_Timers_Control =================================================== */ + #define R_GMAC_LPI_Timers_Control_TWT_Pos (0UL) /*!< TWT (Bit 0) */ + #define R_GMAC_LPI_Timers_Control_TWT_Msk (0xffffUL) /*!< TWT (Bitfield-Mask: 0xffff) */ + #define R_GMAC_LPI_Timers_Control_LST_Pos (16UL) /*!< LST (Bit 16) */ + #define R_GMAC_LPI_Timers_Control_LST_Msk (0x3ff0000UL) /*!< LST (Bitfield-Mask: 0x3ff) */ +/* =================================================== Interrupt_Status ==================================================== */ + #define R_GMAC_Interrupt_Status_PMTIS_Pos (3UL) /*!< PMTIS (Bit 3) */ + #define R_GMAC_Interrupt_Status_PMTIS_Msk (0x8UL) /*!< PMTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCIS_Pos (4UL) /*!< MMCIS (Bit 4) */ + #define R_GMAC_Interrupt_Status_MMCIS_Msk (0x10UL) /*!< MMCIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCRXIS_Pos (5UL) /*!< MMCRXIS (Bit 5) */ + #define R_GMAC_Interrupt_Status_MMCRXIS_Msk (0x20UL) /*!< MMCRXIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCTXIS_Pos (6UL) /*!< MMCTXIS (Bit 6) */ + #define R_GMAC_Interrupt_Status_MMCTXIS_Msk (0x40UL) /*!< MMCTXIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_MMCRXIPIS_Pos (7UL) /*!< MMCRXIPIS (Bit 7) */ + #define R_GMAC_Interrupt_Status_MMCRXIPIS_Msk (0x80UL) /*!< MMCRXIPIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_TSIS_Pos (9UL) /*!< TSIS (Bit 9) */ + #define R_GMAC_Interrupt_Status_TSIS_Msk (0x200UL) /*!< TSIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Status_LPIIS_Pos (10UL) /*!< LPIIS (Bit 10) */ + #define R_GMAC_Interrupt_Status_LPIIS_Msk (0x400UL) /*!< LPIIS (Bitfield-Mask: 0x01) */ +/* ==================================================== Interrupt_Mask ===================================================== */ + #define R_GMAC_Interrupt_Mask_PMTIM_Pos (3UL) /*!< PMTIM (Bit 3) */ + #define R_GMAC_Interrupt_Mask_PMTIM_Msk (0x8UL) /*!< PMTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Mask_TSIM_Pos (9UL) /*!< TSIM (Bit 9) */ + #define R_GMAC_Interrupt_Mask_TSIM_Msk (0x200UL) /*!< TSIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Mask_LPIIM_Pos (10UL) /*!< LPIIM (Bit 10) */ + #define R_GMAC_Interrupt_Mask_LPIIM_Msk (0x400UL) /*!< LPIIM (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR0_H ========================================================= */ + #define R_GMAC_MAR0_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR0_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR0_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR0_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR0_L ========================================================= */ + #define R_GMAC_MAR0_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR0_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR1_H ========================================================= */ + #define R_GMAC_MAR1_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR1_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR1_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR1_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR1_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR1_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR1_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR1_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR2_H ========================================================= */ + #define R_GMAC_MAR2_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR2_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR2_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR2_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR2_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR2_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR2_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR2_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR3_H ========================================================= */ + #define R_GMAC_MAR3_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR3_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR3_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR3_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR3_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR3_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR3_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR3_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR4_H ========================================================= */ + #define R_GMAC_MAR4_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR4_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR4_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR4_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR4_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR4_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR4_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR4_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR5_H ========================================================= */ + #define R_GMAC_MAR5_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR5_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR5_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR5_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR5_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR5_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR5_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR5_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR6_H ========================================================= */ + #define R_GMAC_MAR6_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR6_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR6_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR6_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR6_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR6_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR6_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR6_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR7_H ========================================================= */ + #define R_GMAC_MAR7_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR7_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR7_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR7_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR7_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR7_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR7_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR7_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR8_H ========================================================= */ + #define R_GMAC_MAR8_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR8_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR8_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR8_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR8_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR8_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR8_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR8_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR9_H ========================================================= */ + #define R_GMAC_MAR9_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR9_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR9_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR9_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR9_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR9_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR9_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR9_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR10_H ======================================================== */ + #define R_GMAC_MAR10_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR10_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR10_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR10_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR10_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR10_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR10_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR10_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR11_H ======================================================== */ + #define R_GMAC_MAR11_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR11_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR11_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR11_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR11_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR11_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR11_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR11_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR12_H ======================================================== */ + #define R_GMAC_MAR12_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR12_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR12_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR12_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR12_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR12_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR12_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR12_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR13_H ======================================================== */ + #define R_GMAC_MAR13_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR13_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR13_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR13_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR13_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR13_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR13_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR13_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR14_H ======================================================== */ + #define R_GMAC_MAR14_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR14_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR14_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR14_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR14_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR14_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR14_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR14_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR15_H ======================================================== */ + #define R_GMAC_MAR15_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR15_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR15_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR15_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR15_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR15_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR15_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR15_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR1_L ========================================================= */ + #define R_GMAC_MAR1_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR1_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR2_L ========================================================= */ + #define R_GMAC_MAR2_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR2_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR3_L ========================================================= */ + #define R_GMAC_MAR3_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR3_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR4_L ========================================================= */ + #define R_GMAC_MAR4_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR4_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR5_L ========================================================= */ + #define R_GMAC_MAR5_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR5_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR6_L ========================================================= */ + #define R_GMAC_MAR6_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR6_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR7_L ========================================================= */ + #define R_GMAC_MAR7_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR7_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR8_L ========================================================= */ + #define R_GMAC_MAR8_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR8_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR9_L ========================================================= */ + #define R_GMAC_MAR9_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR9_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR10_L ======================================================== */ + #define R_GMAC_MAR10_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR10_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR11_L ======================================================== */ + #define R_GMAC_MAR11_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR11_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR12_L ======================================================== */ + #define R_GMAC_MAR12_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR12_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR13_L ======================================================== */ + #define R_GMAC_MAR13_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR13_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR14_L ======================================================== */ + #define R_GMAC_MAR14_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR14_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR15_L ======================================================== */ + #define R_GMAC_MAR15_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR15_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== WDog_Timeout ====================================================== */ + #define R_GMAC_WDog_Timeout_WTO_Pos (0UL) /*!< WTO (Bit 0) */ + #define R_GMAC_WDog_Timeout_WTO_Msk (0x3fffUL) /*!< WTO (Bitfield-Mask: 0x3fff) */ + #define R_GMAC_WDog_Timeout_PWE_Pos (16UL) /*!< PWE (Bit 16) */ + #define R_GMAC_WDog_Timeout_PWE_Msk (0x10000UL) /*!< PWE (Bitfield-Mask: 0x01) */ +/* ====================================================== MMC_Control ====================================================== */ + #define R_GMAC_MMC_Control_CNTRST_Pos (0UL) /*!< CNTRST (Bit 0) */ + #define R_GMAC_MMC_Control_CNTRST_Msk (0x1UL) /*!< CNTRST (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTSTOPRO_Pos (1UL) /*!< CNTSTOPRO (Bit 1) */ + #define R_GMAC_MMC_Control_CNTSTOPRO_Msk (0x2UL) /*!< CNTSTOPRO (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_RSTONRD_Pos (2UL) /*!< RSTONRD (Bit 2) */ + #define R_GMAC_MMC_Control_RSTONRD_Msk (0x4UL) /*!< RSTONRD (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTFREEZ_Pos (3UL) /*!< CNTFREEZ (Bit 3) */ + #define R_GMAC_MMC_Control_CNTFREEZ_Msk (0x8UL) /*!< CNTFREEZ (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTPRST_Pos (4UL) /*!< CNTPRST (Bit 4) */ + #define R_GMAC_MMC_Control_CNTPRST_Msk (0x10UL) /*!< CNTPRST (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_CNTPRSTLVL_Pos (5UL) /*!< CNTPRSTLVL (Bit 5) */ + #define R_GMAC_MMC_Control_CNTPRSTLVL_Msk (0x20UL) /*!< CNTPRSTLVL (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Control_UCDBC_Pos (8UL) /*!< UCDBC (Bit 8) */ + #define R_GMAC_MMC_Control_UCDBC_Msk (0x100UL) /*!< UCDBC (Bitfield-Mask: 0x01) */ +/* ================================================= MMC_Receive_Interrupt ================================================= */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBFRMIS_Pos (0UL) /*!< RXGBFRMIS (Bit 0) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBFRMIS_Msk (0x1UL) /*!< RXGBFRMIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBOCTIS_Pos (1UL) /*!< RXGBOCTIS (Bit 1) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGBOCTIS_Msk (0x2UL) /*!< RXGBOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGOCTIS_Pos (2UL) /*!< RXGOCTIS (Bit 2) */ + #define R_GMAC_MMC_Receive_Interrupt_RXGOCTIS_Msk (0x4UL) /*!< RXGOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXBCGFIS_Pos (3UL) /*!< RXBCGFIS (Bit 3) */ + #define R_GMAC_MMC_Receive_Interrupt_RXBCGFIS_Msk (0x8UL) /*!< RXBCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXMCGFIS_Pos (4UL) /*!< RXMCGFIS (Bit 4) */ + #define R_GMAC_MMC_Receive_Interrupt_RXMCGFIS_Msk (0x10UL) /*!< RXMCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCRCERFIS_Pos (5UL) /*!< RXCRCERFIS (Bit 5) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCRCERFIS_Msk (0x20UL) /*!< RXCRCERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXALGNERFIS_Pos (6UL) /*!< RXALGNERFIS (Bit 6) */ + #define R_GMAC_MMC_Receive_Interrupt_RXALGNERFIS_Msk (0x40UL) /*!< RXALGNERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRUNTFIS_Pos (7UL) /*!< RXRUNTFIS (Bit 7) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRUNTFIS_Msk (0x80UL) /*!< RXRUNTFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXJABERFIS_Pos (8UL) /*!< RXJABERFIS (Bit 8) */ + #define R_GMAC_MMC_Receive_Interrupt_RXJABERFIS_Msk (0x100UL) /*!< RXJABERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUSIZEGFIS_Pos (9UL) /*!< RXUSIZEGFIS (Bit 9) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUSIZEGFIS_Msk (0x200UL) /*!< RXUSIZEGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXOSIZEGFIS_Pos (10UL) /*!< RXOSIZEGFIS (Bit 10) */ + #define R_GMAC_MMC_Receive_Interrupt_RXOSIZEGFIS_Msk (0x400UL) /*!< RXOSIZEGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX64OCTGBFIS_Pos (11UL) /*!< RX64OCTGBFIS (Bit 11) */ + #define R_GMAC_MMC_Receive_Interrupt_RX64OCTGBFIS_Msk (0x800UL) /*!< RX64OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX65T127OCTGBFIS_Pos (12UL) /*!< RX65T127OCTGBFIS (Bit 12) */ + #define R_GMAC_MMC_Receive_Interrupt_RX65T127OCTGBFIS_Msk (0x1000UL) /*!< RX65T127OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX128T255OCTGBFIS_Pos (13UL) /*!< RX128T255OCTGBFIS (Bit 13) */ + #define R_GMAC_MMC_Receive_Interrupt_RX128T255OCTGBFIS_Msk (0x2000UL) /*!< RX128T255OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX256T511OCTGBFIS_Pos (14UL) /*!< RX256T511OCTGBFIS (Bit 14) */ + #define R_GMAC_MMC_Receive_Interrupt_RX256T511OCTGBFIS_Msk (0x4000UL) /*!< RX256T511OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX512T1023OCTGBFIS_Pos (15UL) /*!< RX512T1023OCTGBFIS (Bit 15) */ + #define R_GMAC_MMC_Receive_Interrupt_RX512T1023OCTGBFIS_Msk (0x8000UL) /*!< RX512T1023OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RX1024TMAXOCTGBFIS_Pos (16UL) /*!< RX1024TMAXOCTGBFIS (Bit 16) */ + #define R_GMAC_MMC_Receive_Interrupt_RX1024TMAXOCTGBFIS_Msk (0x10000UL) /*!< RX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUCGFIS_Pos (17UL) /*!< RXUCGFIS (Bit 17) */ + #define R_GMAC_MMC_Receive_Interrupt_RXUCGFIS_Msk (0x20000UL) /*!< RXUCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXLENERFIS_Pos (18UL) /*!< RXLENERFIS (Bit 18) */ + #define R_GMAC_MMC_Receive_Interrupt_RXLENERFIS_Msk (0x40000UL) /*!< RXLENERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXORANGEFIS_Pos (19UL) /*!< RXORANGEFIS (Bit 19) */ + #define R_GMAC_MMC_Receive_Interrupt_RXORANGEFIS_Msk (0x80000UL) /*!< RXORANGEFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXPAUSFIS_Pos (20UL) /*!< RXPAUSFIS (Bit 20) */ + #define R_GMAC_MMC_Receive_Interrupt_RXPAUSFIS_Msk (0x100000UL) /*!< RXPAUSFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXFOVFIS_Pos (21UL) /*!< RXFOVFIS (Bit 21) */ + #define R_GMAC_MMC_Receive_Interrupt_RXFOVFIS_Msk (0x200000UL) /*!< RXFOVFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXVLANGBFIS_Pos (22UL) /*!< RXVLANGBFIS (Bit 22) */ + #define R_GMAC_MMC_Receive_Interrupt_RXVLANGBFIS_Msk (0x400000UL) /*!< RXVLANGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXWDOGFIS_Pos (23UL) /*!< RXWDOGFIS (Bit 23) */ + #define R_GMAC_MMC_Receive_Interrupt_RXWDOGFIS_Msk (0x800000UL) /*!< RXWDOGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRCVERRFIS_Pos (24UL) /*!< RXRCVERRFIS (Bit 24) */ + #define R_GMAC_MMC_Receive_Interrupt_RXRCVERRFIS_Msk (0x1000000UL) /*!< RXRCVERRFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCTRLFIS_Pos (25UL) /*!< RXCTRLFIS (Bit 25) */ + #define R_GMAC_MMC_Receive_Interrupt_RXCTRLFIS_Msk (0x2000000UL) /*!< RXCTRLFIS (Bitfield-Mask: 0x01) */ +/* ================================================ MMC_Transmit_Interrupt ================================================= */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBOCTIS_Pos (0UL) /*!< TXGBOCTIS (Bit 0) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBOCTIS_Msk (0x1UL) /*!< TXGBOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBFRMIS_Pos (1UL) /*!< TXGBFRMIS (Bit 1) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGBFRMIS_Msk (0x2UL) /*!< TXGBFRMIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGFIS_Pos (2UL) /*!< TXBCGFIS (Bit 2) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGFIS_Msk (0x4UL) /*!< TXBCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGFIS_Pos (3UL) /*!< TXMCGFIS (Bit 3) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGFIS_Msk (0x8UL) /*!< TXMCGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX64OCTGBFIS_Pos (4UL) /*!< TX64OCTGBFIS (Bit 4) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX64OCTGBFIS_Msk (0x10UL) /*!< TX64OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX65T127OCTGBFIS_Pos (5UL) /*!< TX65T127OCTGBFIS (Bit 5) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX65T127OCTGBFIS_Msk (0x20UL) /*!< TX65T127OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX128T255OCTGBFIS_Pos (6UL) /*!< TX128T255OCTGBFIS (Bit 6) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX128T255OCTGBFIS_Msk (0x40UL) /*!< TX128T255OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX256T511OCTGBFIS_Pos (7UL) /*!< TX256T511OCTGBFIS (Bit 7) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX256T511OCTGBFIS_Msk (0x80UL) /*!< TX256T511OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX512T1023OCTGBFIS_Pos (8UL) /*!< TX512T1023OCTGBFIS (Bit 8) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX512T1023OCTGBFIS_Msk (0x100UL) /*!< TX512T1023OCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX1024TMAXOCTGBFIS_Pos (9UL) /*!< TX1024TMAXOCTGBFIS (Bit 9) */ + #define R_GMAC_MMC_Transmit_Interrupt_TX1024TMAXOCTGBFIS_Msk (0x200UL) /*!< TX1024TMAXOCTGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUCGBFIS_Pos (10UL) /*!< TXUCGBFIS (Bit 10) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUCGBFIS_Msk (0x400UL) /*!< TXUCGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGBFIS_Pos (11UL) /*!< TXMCGBFIS (Bit 11) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCGBFIS_Msk (0x800UL) /*!< TXMCGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGBFIS_Pos (12UL) /*!< TXBCGBFIS (Bit 12) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXBCGBFIS_Msk (0x1000UL) /*!< TXBCGBFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUFLOWERFIS_Pos (13UL) /*!< TXUFLOWERFIS (Bit 13) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXUFLOWERFIS_Msk (0x2000UL) /*!< TXUFLOWERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXSCOLGFIS_Pos (14UL) /*!< TXSCOLGFIS (Bit 14) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXSCOLGFIS_Msk (0x4000UL) /*!< TXSCOLGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCOLGFIS_Pos (15UL) /*!< TXMCOLGFIS (Bit 15) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXMCOLGFIS_Msk (0x8000UL) /*!< TXMCOLGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXDEFFIS_Pos (16UL) /*!< TXDEFFIS (Bit 16) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXDEFFIS_Msk (0x10000UL) /*!< TXDEFFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXLATCOLFIS_Pos (17UL) /*!< TXLATCOLFIS (Bit 17) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXLATCOLFIS_Msk (0x20000UL) /*!< TXLATCOLFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXCOLFIS_Pos (18UL) /*!< TXEXCOLFIS (Bit 18) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXCOLFIS_Msk (0x40000UL) /*!< TXEXCOLFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXCARERFIS_Pos (19UL) /*!< TXCARERFIS (Bit 19) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXCARERFIS_Msk (0x80000UL) /*!< TXCARERFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGOCTIS_Pos (20UL) /*!< TXGOCTIS (Bit 20) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGOCTIS_Msk (0x100000UL) /*!< TXGOCTIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGFRMIS_Pos (21UL) /*!< TXGFRMIS (Bit 21) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXGFRMIS_Msk (0x200000UL) /*!< TXGFRMIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXDEFFIS_Pos (22UL) /*!< TXEXDEFFIS (Bit 22) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXEXDEFFIS_Msk (0x400000UL) /*!< TXEXDEFFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXPAUSFIS_Pos (23UL) /*!< TXPAUSFIS (Bit 23) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXPAUSFIS_Msk (0x800000UL) /*!< TXPAUSFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXVLANGFIS_Pos (24UL) /*!< TXVLANGFIS (Bit 24) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXVLANGFIS_Msk (0x1000000UL) /*!< TXVLANGFIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXOSIZEGFIS_Pos (25UL) /*!< TXOSIZEGFIS (Bit 25) */ + #define R_GMAC_MMC_Transmit_Interrupt_TXOSIZEGFIS_Msk (0x2000000UL) /*!< TXOSIZEGFIS (Bitfield-Mask: 0x01) */ +/* ============================================== MMC_Receive_Interrupt_Mask =============================================== */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBFRMIM_Pos (0UL) /*!< RXGBFRMIM (Bit 0) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBFRMIM_Msk (0x1UL) /*!< RXGBFRMIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBOCTIM_Pos (1UL) /*!< RXGBOCTIM (Bit 1) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGBOCTIM_Msk (0x2UL) /*!< RXGBOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGOCTIM_Pos (2UL) /*!< RXGOCTIM (Bit 2) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXGOCTIM_Msk (0x4UL) /*!< RXGOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXBCGFIM_Pos (3UL) /*!< RXBCGFIM (Bit 3) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXBCGFIM_Msk (0x8UL) /*!< RXBCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXMCGFIM_Pos (4UL) /*!< RXMCGFIM (Bit 4) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXMCGFIM_Msk (0x10UL) /*!< RXMCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCRCERFIM_Pos (5UL) /*!< RXCRCERFIM (Bit 5) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCRCERFIM_Msk (0x20UL) /*!< RXCRCERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXALGNERFIM_Pos (6UL) /*!< RXALGNERFIM (Bit 6) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXALGNERFIM_Msk (0x40UL) /*!< RXALGNERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRUNTFIM_Pos (7UL) /*!< RXRUNTFIM (Bit 7) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRUNTFIM_Msk (0x80UL) /*!< RXRUNTFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXJABERFIM_Pos (8UL) /*!< RXJABERFIM (Bit 8) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXJABERFIM_Msk (0x100UL) /*!< RXJABERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUSIZEGFIM_Pos (9UL) /*!< RXUSIZEGFIM (Bit 9) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUSIZEGFIM_Msk (0x200UL) /*!< RXUSIZEGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXOSIZEGFIM_Pos (10UL) /*!< RXOSIZEGFIM (Bit 10) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXOSIZEGFIM_Msk (0x400UL) /*!< RXOSIZEGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX64OCTGBFIM_Pos (11UL) /*!< RX64OCTGBFIM (Bit 11) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX64OCTGBFIM_Msk (0x800UL) /*!< RX64OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX65T127OCTGBFIM_Pos (12UL) /*!< RX65T127OCTGBFIM (Bit 12) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX65T127OCTGBFIM_Msk (0x1000UL) /*!< RX65T127OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX128T255OCTGBFIM_Pos (13UL) /*!< RX128T255OCTGBFIM (Bit 13) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX128T255OCTGBFIM_Msk (0x2000UL) /*!< RX128T255OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX256T511OCTGBFIM_Pos (14UL) /*!< RX256T511OCTGBFIM (Bit 14) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX256T511OCTGBFIM_Msk (0x4000UL) /*!< RX256T511OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX512T1023OCTGBFIM_Pos (15UL) /*!< RX512T1023OCTGBFIM (Bit 15) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX512T1023OCTGBFIM_Msk (0x8000UL) /*!< RX512T1023OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX1024TMAXOCTGBFIM_Pos (16UL) /*!< RX1024TMAXOCTGBFIM (Bit 16) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RX1024TMAXOCTGBFIM_Msk (0x10000UL) /*!< RX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUCGFIM_Pos (17UL) /*!< RXUCGFIM (Bit 17) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXUCGFIM_Msk (0x20000UL) /*!< RXUCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXLENERFIM_Pos (18UL) /*!< RXLENERFIM (Bit 18) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXLENERFIM_Msk (0x40000UL) /*!< RXLENERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXORANGEFIM_Pos (19UL) /*!< RXORANGEFIM (Bit 19) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXORANGEFIM_Msk (0x80000UL) /*!< RXORANGEFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXPAUSFIM_Pos (20UL) /*!< RXPAUSFIM (Bit 20) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXPAUSFIM_Msk (0x100000UL) /*!< RXPAUSFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXFOVFIM_Pos (21UL) /*!< RXFOVFIM (Bit 21) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXFOVFIM_Msk (0x200000UL) /*!< RXFOVFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXVLANGBFIM_Pos (22UL) /*!< RXVLANGBFIM (Bit 22) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXVLANGBFIM_Msk (0x400000UL) /*!< RXVLANGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXWDOGFIM_Pos (23UL) /*!< RXWDOGFIM (Bit 23) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXWDOGFIM_Msk (0x800000UL) /*!< RXWDOGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRCVERRFIM_Pos (24UL) /*!< RXRCVERRFIM (Bit 24) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXRCVERRFIM_Msk (0x1000000UL) /*!< RXRCVERRFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCTRLFIM_Pos (25UL) /*!< RXCTRLFIM (Bit 25) */ + #define R_GMAC_MMC_Receive_Interrupt_Mask_RXCTRLFIM_Msk (0x2000000UL) /*!< RXCTRLFIM (Bitfield-Mask: 0x01) */ +/* ============================================== MMC_Transmit_Interrupt_Mask ============================================== */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBOCTIM_Pos (0UL) /*!< TXGBOCTIM (Bit 0) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBOCTIM_Msk (0x1UL) /*!< TXGBOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBFRMIM_Pos (1UL) /*!< TXGBFRMIM (Bit 1) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGBFRMIM_Msk (0x2UL) /*!< TXGBFRMIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGFIM_Pos (2UL) /*!< TXBCGFIM (Bit 2) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGFIM_Msk (0x4UL) /*!< TXBCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGFIM_Pos (3UL) /*!< TXMCGFIM (Bit 3) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGFIM_Msk (0x8UL) /*!< TXMCGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX64OCTGBFIM_Pos (4UL) /*!< TX64OCTGBFIM (Bit 4) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX64OCTGBFIM_Msk (0x10UL) /*!< TX64OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX65T127OCTGBFIM_Pos (5UL) /*!< TX65T127OCTGBFIM (Bit 5) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX65T127OCTGBFIM_Msk (0x20UL) /*!< TX65T127OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX128T255OCTGBFIM_Pos (6UL) /*!< TX128T255OCTGBFIM (Bit 6) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX128T255OCTGBFIM_Msk (0x40UL) /*!< TX128T255OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX256T511OCTGBFIM_Pos (7UL) /*!< TX256T511OCTGBFIM (Bit 7) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX256T511OCTGBFIM_Msk (0x80UL) /*!< TX256T511OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX512T1023OCTGBFIM_Pos (8UL) /*!< TX512T1023OCTGBFIM (Bit 8) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX512T1023OCTGBFIM_Msk (0x100UL) /*!< TX512T1023OCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX1024TMAXOCTGBFIM_Pos (9UL) /*!< TX1024TMAXOCTGBFIM (Bit 9) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TX1024TMAXOCTGBFIM_Msk (0x200UL) /*!< TX1024TMAXOCTGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUCGBFIM_Pos (10UL) /*!< TXUCGBFIM (Bit 10) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUCGBFIM_Msk (0x400UL) /*!< TXUCGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGBFIM_Pos (11UL) /*!< TXMCGBFIM (Bit 11) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCGBFIM_Msk (0x800UL) /*!< TXMCGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGBFIM_Pos (12UL) /*!< TXBCGBFIM (Bit 12) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXBCGBFIM_Msk (0x1000UL) /*!< TXBCGBFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUFLOWERFIM_Pos (13UL) /*!< TXUFLOWERFIM (Bit 13) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXUFLOWERFIM_Msk (0x2000UL) /*!< TXUFLOWERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXSCOLGFIM_Pos (14UL) /*!< TXSCOLGFIM (Bit 14) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXSCOLGFIM_Msk (0x4000UL) /*!< TXSCOLGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCOLGFIM_Pos (15UL) /*!< TXMCOLGFIM (Bit 15) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXMCOLGFIM_Msk (0x8000UL) /*!< TXMCOLGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXDEFFIM_Pos (16UL) /*!< TXDEFFIM (Bit 16) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXDEFFIM_Msk (0x10000UL) /*!< TXDEFFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXLATCOLFIM_Pos (17UL) /*!< TXLATCOLFIM (Bit 17) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXLATCOLFIM_Msk (0x20000UL) /*!< TXLATCOLFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXCOLFIM_Pos (18UL) /*!< TXEXCOLFIM (Bit 18) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXCOLFIM_Msk (0x40000UL) /*!< TXEXCOLFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXCARERFIM_Pos (19UL) /*!< TXCARERFIM (Bit 19) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXCARERFIM_Msk (0x80000UL) /*!< TXCARERFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGOCTIM_Pos (20UL) /*!< TXGOCTIM (Bit 20) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGOCTIM_Msk (0x100000UL) /*!< TXGOCTIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGFRMIM_Pos (21UL) /*!< TXGFRMIM (Bit 21) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXGFRMIM_Msk (0x200000UL) /*!< TXGFRMIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXDEFFIM_Pos (22UL) /*!< TXEXDEFFIM (Bit 22) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXEXDEFFIM_Msk (0x400000UL) /*!< TXEXDEFFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXPAUSFIM_Pos (23UL) /*!< TXPAUSFIM (Bit 23) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXPAUSFIM_Msk (0x800000UL) /*!< TXPAUSFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXVLANGFIM_Pos (24UL) /*!< TXVLANGFIM (Bit 24) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXVLANGFIM_Msk (0x1000000UL) /*!< TXVLANGFIM (Bitfield-Mask: 0x01) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXOSIZEGFIM_Pos (25UL) /*!< TXOSIZEGFIM (Bit 25) */ + #define R_GMAC_MMC_Transmit_Interrupt_Mask_TXOSIZEGFIM_Msk (0x2000000UL) /*!< TXOSIZEGFIM (Bitfield-Mask: 0x01) */ +/* ================================================ Tx_Octet_Count_Good_Bad ================================================ */ + #define R_GMAC_Tx_Octet_Count_Good_Bad_TXOCTGB_Pos (0UL) /*!< TXOCTGB (Bit 0) */ + #define R_GMAC_Tx_Octet_Count_Good_Bad_TXOCTGB_Msk (0xffffffffUL) /*!< TXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Tx_Frame_Count_Good_Bad ================================================ */ + #define R_GMAC_Tx_Frame_Count_Good_Bad_TXFRMGB_Pos (0UL) /*!< TXFRMGB (Bit 0) */ + #define R_GMAC_Tx_Frame_Count_Good_Bad_TXFRMGB_Msk (0xffffffffUL) /*!< TXFRMGB (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Tx_Broadcast_Frames_Good ================================================ */ + #define R_GMAC_Tx_Broadcast_Frames_Good_TXBCASTG_Pos (0UL) /*!< TXBCASTG (Bit 0) */ + #define R_GMAC_Tx_Broadcast_Frames_Good_TXBCASTG_Msk (0xffffffffUL) /*!< TXBCASTG (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Tx_Multicast_Frames_Good ================================================ */ + #define R_GMAC_Tx_Multicast_Frames_Good_TXMCASTG_Pos (0UL) /*!< TXMCASTG (Bit 0) */ + #define R_GMAC_Tx_Multicast_Frames_Good_TXMCASTG_Msk (0xffffffffUL) /*!< TXMCASTG (Bitfield-Mask: 0xffffffff) */ +/* ============================================== Tx_64Octets_Frames_Good_Bad ============================================== */ + #define R_GMAC_Tx_64Octets_Frames_Good_Bad_TX64OCTGB_Pos (0UL) /*!< TX64OCTGB (Bit 0) */ + #define R_GMAC_Tx_64Octets_Frames_Good_Bad_TX64OCTGB_Msk (0xffffffffUL) /*!< TX64OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Tx_65To127Octets_Frames_Good_Bad ============================================ */ + #define R_GMAC_Tx_65To127Octets_Frames_Good_Bad_TX65_127OCTGB_Pos (0UL) /*!< TX65_127OCTGB (Bit 0) */ + #define R_GMAC_Tx_65To127Octets_Frames_Good_Bad_TX65_127OCTGB_Msk (0xffffffffUL) /*!< TX65_127OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Tx_128To255Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_128To255Octets_Frames_Good_Bad_TX128_255OCTGB_Pos (0UL) /*!< TX128_255OCTGB (Bit 0) */ + #define R_GMAC_Tx_128To255Octets_Frames_Good_Bad_TX128_255OCTGB_Msk (0xffffffffUL) /*!< TX128_255OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Tx_256To511Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_256To511Octets_Frames_Good_Bad_TX256_511OCTGB_Pos (0UL) /*!< TX256_511OCTGB (Bit 0) */ + #define R_GMAC_Tx_256To511Octets_Frames_Good_Bad_TX256_511OCTGB_Msk (0xffffffffUL) /*!< TX256_511OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Tx_512To1023Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_512To1023Octets_Frames_Good_Bad_TX512_1023OCTGB_Pos (0UL) /*!< TX512_1023OCTGB (Bit 0) */ + #define R_GMAC_Tx_512To1023Octets_Frames_Good_Bad_TX512_1023OCTGB_Msk (0xffffffffUL) /*!< TX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Tx_1024ToMaxOctets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_TX1024_MAXOCTGB_Pos (0UL) /*!< TX1024_MAXOCTGB (Bit 0) */ + #define R_GMAC_Tx_1024ToMaxOctets_Frames_Good_Bad_TX1024_MAXOCTGB_Msk (0xffffffffUL) /*!< TX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ============================================== Tx_Unicast_Frames_Good_Bad =============================================== */ + #define R_GMAC_Tx_Unicast_Frames_Good_Bad_TXUCASTGB_Pos (0UL) /*!< TXUCASTGB (Bit 0) */ + #define R_GMAC_Tx_Unicast_Frames_Good_Bad_TXUCASTGB_Msk (0xffffffffUL) /*!< TXUCASTGB (Bitfield-Mask: 0xffffffff) */ +/* ============================================= Tx_Multicast_Frames_Good_Bad ============================================== */ + #define R_GMAC_Tx_Multicast_Frames_Good_Bad_TXMCASTGB_Pos (0UL) /*!< TXMCASTGB (Bit 0) */ + #define R_GMAC_Tx_Multicast_Frames_Good_Bad_TXMCASTGB_Msk (0xffffffffUL) /*!< TXMCASTGB (Bitfield-Mask: 0xffffffff) */ +/* ============================================= Tx_Broadcast_Frames_Good_Bad ============================================== */ + #define R_GMAC_Tx_Broadcast_Frames_Good_Bad_TXBCASTGB_Pos (0UL) /*!< TXBCASTGB (Bit 0) */ + #define R_GMAC_Tx_Broadcast_Frames_Good_Bad_TXBCASTGB_Msk (0xffffffffUL) /*!< TXBCASTGB (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Tx_Underflow_Error_Frames =============================================== */ + #define R_GMAC_Tx_Underflow_Error_Frames_TXUNDRFLW_Pos (0UL) /*!< TXUNDRFLW (Bit 0) */ + #define R_GMAC_Tx_Underflow_Error_Frames_TXUNDRFLW_Msk (0xffffUL) /*!< TXUNDRFLW (Bitfield-Mask: 0xffff) */ +/* ============================================ Tx_Single_Collision_Good_Frames ============================================ */ + #define R_GMAC_Tx_Single_Collision_Good_Frames_TXSNGLCOLG_Pos (0UL) /*!< TXSNGLCOLG (Bit 0) */ + #define R_GMAC_Tx_Single_Collision_Good_Frames_TXSNGLCOLG_Msk (0xffffUL) /*!< TXSNGLCOLG (Bitfield-Mask: 0xffff) */ +/* =========================================== Tx_Multiple_Collision_Good_Frames =========================================== */ + #define R_GMAC_Tx_Multiple_Collision_Good_Frames_TXMULTCOLG_Pos (0UL) /*!< TXMULTCOLG (Bit 0) */ + #define R_GMAC_Tx_Multiple_Collision_Good_Frames_TXMULTCOLG_Msk (0xffffUL) /*!< TXMULTCOLG (Bitfield-Mask: 0xffff) */ +/* ================================================== Tx_Deferred_Frames =================================================== */ + #define R_GMAC_Tx_Deferred_Frames_TXDEFRD_Pos (0UL) /*!< TXDEFRD (Bit 0) */ + #define R_GMAC_Tx_Deferred_Frames_TXDEFRD_Msk (0xffffUL) /*!< TXDEFRD (Bitfield-Mask: 0xffff) */ +/* =============================================== Tx_Late_Collision_Frames ================================================ */ + #define R_GMAC_Tx_Late_Collision_Frames_TXLATECOL_Pos (0UL) /*!< TXLATECOL (Bit 0) */ + #define R_GMAC_Tx_Late_Collision_Frames_TXLATECOL_Msk (0xffffUL) /*!< TXLATECOL (Bitfield-Mask: 0xffff) */ +/* ============================================= Tx_Excessive_Collision_Frames ============================================= */ + #define R_GMAC_Tx_Excessive_Collision_Frames_TXEXSCOL_Pos (0UL) /*!< TXEXSCOL (Bit 0) */ + #define R_GMAC_Tx_Excessive_Collision_Frames_TXEXSCOL_Msk (0xffffUL) /*!< TXEXSCOL (Bitfield-Mask: 0xffff) */ +/* ================================================ Tx_Carrier_Error_Frames ================================================ */ + #define R_GMAC_Tx_Carrier_Error_Frames_TXCARR_Pos (0UL) /*!< TXCARR (Bit 0) */ + #define R_GMAC_Tx_Carrier_Error_Frames_TXCARR_Msk (0xffffUL) /*!< TXCARR (Bitfield-Mask: 0xffff) */ +/* ================================================== Tx_Octet_Count_Good ================================================== */ + #define R_GMAC_Tx_Octet_Count_Good_TXOCTG_Pos (0UL) /*!< TXOCTG (Bit 0) */ + #define R_GMAC_Tx_Octet_Count_Good_TXOCTG_Msk (0xffffffffUL) /*!< TXOCTG (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Tx_Frame_Count_Good ================================================== */ + #define R_GMAC_Tx_Frame_Count_Good_TXFRMG_Pos (0UL) /*!< TXFRMG (Bit 0) */ + #define R_GMAC_Tx_Frame_Count_Good_TXFRMG_Msk (0xffffffffUL) /*!< TXFRMG (Bitfield-Mask: 0xffffffff) */ +/* ============================================== Tx_Excessive_Deferral_Error ============================================== */ + #define R_GMAC_Tx_Excessive_Deferral_Error_TXEXSDEF_Pos (0UL) /*!< TXEXSDEF (Bit 0) */ + #define R_GMAC_Tx_Excessive_Deferral_Error_TXEXSDEF_Msk (0xffffUL) /*!< TXEXSDEF (Bitfield-Mask: 0xffff) */ +/* ==================================================== Tx_Pause_Frames ==================================================== */ + #define R_GMAC_Tx_Pause_Frames_TXPAUSE_Pos (0UL) /*!< TXPAUSE (Bit 0) */ + #define R_GMAC_Tx_Pause_Frames_TXPAUSE_Msk (0xffffUL) /*!< TXPAUSE (Bitfield-Mask: 0xffff) */ +/* ================================================== Tx_VLAN_Frames_Good ================================================== */ + #define R_GMAC_Tx_VLAN_Frames_Good_TXVLANG_Pos (0UL) /*!< TXVLANG (Bit 0) */ + #define R_GMAC_Tx_VLAN_Frames_Good_TXVLANG_Msk (0xffffffffUL) /*!< TXVLANG (Bitfield-Mask: 0xffffffff) */ +/* ================================================= Tx_OSize_Frames_Good ================================================== */ + #define R_GMAC_Tx_OSize_Frames_Good_TXOSIZG_Pos (0UL) /*!< TXOSIZG (Bit 0) */ + #define R_GMAC_Tx_OSize_Frames_Good_TXOSIZG_Msk (0xffffUL) /*!< TXOSIZG (Bitfield-Mask: 0xffff) */ +/* =============================================== Rx_Frames_Count_Good_Bad ================================================ */ + #define R_GMAC_Rx_Frames_Count_Good_Bad_RXFRMGB_Pos (0UL) /*!< RXFRMGB (Bit 0) */ + #define R_GMAC_Rx_Frames_Count_Good_Bad_RXFRMGB_Msk (0xffffffffUL) /*!< RXFRMGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Rx_Octet_Count_Good_Bad ================================================ */ + #define R_GMAC_Rx_Octet_Count_Good_Bad_RXOCTGB_Pos (0UL) /*!< RXOCTGB (Bit 0) */ + #define R_GMAC_Rx_Octet_Count_Good_Bad_RXOCTGB_Msk (0xffffffffUL) /*!< RXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Rx_Octet_Count_Good ================================================== */ + #define R_GMAC_Rx_Octet_Count_Good_RXOCTG_Pos (0UL) /*!< RXOCTG (Bit 0) */ + #define R_GMAC_Rx_Octet_Count_Good_RXOCTG_Msk (0xffffffffUL) /*!< RXOCTG (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Rx_Broadcast_Frames_Good ================================================ */ + #define R_GMAC_Rx_Broadcast_Frames_Good_RXBCASTG_Pos (0UL) /*!< RXBCASTG (Bit 0) */ + #define R_GMAC_Rx_Broadcast_Frames_Good_RXBCASTG_Msk (0xffffffffUL) /*!< RXBCASTG (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Rx_Multicast_Frames_Good ================================================ */ + #define R_GMAC_Rx_Multicast_Frames_Good_RXMCASTG_Pos (0UL) /*!< RXMCASTG (Bit 0) */ + #define R_GMAC_Rx_Multicast_Frames_Good_RXMCASTG_Msk (0xffffffffUL) /*!< RXMCASTG (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Rx_CRC_Error_Frames ================================================== */ + #define R_GMAC_Rx_CRC_Error_Frames_RXCRCERR_Pos (0UL) /*!< RXCRCERR (Bit 0) */ + #define R_GMAC_Rx_CRC_Error_Frames_RXCRCERR_Msk (0xffffUL) /*!< RXCRCERR (Bitfield-Mask: 0xffff) */ +/* =============================================== Rx_Alignment_Error_Frames =============================================== */ + #define R_GMAC_Rx_Alignment_Error_Frames_RXALGNERR_Pos (0UL) /*!< RXALGNERR (Bit 0) */ + #define R_GMAC_Rx_Alignment_Error_Frames_RXALGNERR_Msk (0xffffUL) /*!< RXALGNERR (Bitfield-Mask: 0xffff) */ +/* ================================================= Rx_Runt_Error_Frames ================================================== */ + #define R_GMAC_Rx_Runt_Error_Frames_RXRUNTERR_Pos (0UL) /*!< RXRUNTERR (Bit 0) */ + #define R_GMAC_Rx_Runt_Error_Frames_RXRUNTERR_Msk (0xffffUL) /*!< RXRUNTERR (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Jabber_Error_Frames ================================================= */ + #define R_GMAC_Rx_Jabber_Error_Frames_RXJABERR_Pos (0UL) /*!< RXJABERR (Bit 0) */ + #define R_GMAC_Rx_Jabber_Error_Frames_RXJABERR_Msk (0xffffUL) /*!< RXJABERR (Bitfield-Mask: 0xffff) */ +/* =============================================== Rx_Undersize_Frames_Good ================================================ */ + #define R_GMAC_Rx_Undersize_Frames_Good_RXUNDERSZG_Pos (0UL) /*!< RXUNDERSZG (Bit 0) */ + #define R_GMAC_Rx_Undersize_Frames_Good_RXUNDERSZG_Msk (0xffffUL) /*!< RXUNDERSZG (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Oversize_Frames_Good ================================================ */ + #define R_GMAC_Rx_Oversize_Frames_Good_RXOVERSZG_Pos (0UL) /*!< RXOVERSZG (Bit 0) */ + #define R_GMAC_Rx_Oversize_Frames_Good_RXOVERSZG_Msk (0xffffUL) /*!< RXOVERSZG (Bitfield-Mask: 0xffff) */ +/* ============================================== Rx_64Octets_Frames_Good_Bad ============================================== */ + #define R_GMAC_Rx_64Octets_Frames_Good_Bad_RX64OCTGB_Pos (0UL) /*!< RX64OCTGB (Bit 0) */ + #define R_GMAC_Rx_64Octets_Frames_Good_Bad_RX64OCTGB_Msk (0xffffffffUL) /*!< RX64OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Rx_65To127Octets_Frames_Good_Bad ============================================ */ + #define R_GMAC_Rx_65To127Octets_Frames_Good_Bad_RX65_127OCTGB_Pos (0UL) /*!< RX65_127OCTGB (Bit 0) */ + #define R_GMAC_Rx_65To127Octets_Frames_Good_Bad_RX65_127OCTGB_Msk (0xffffffffUL) /*!< RX65_127OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Rx_128To255Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_128To255Octets_Frames_Good_Bad_RX128_255OCTGB_Pos (0UL) /*!< RX128_255OCTGB (Bit 0) */ + #define R_GMAC_Rx_128To255Octets_Frames_Good_Bad_RX128_255OCTGB_Msk (0xffffffffUL) /*!< RX128_255OCTGB (Bitfield-Mask: 0xffffffff) */ +/* =========================================== Rx_256To511Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_256To511Octets_Frames_Good_Bad_RX256_511OCTGB_Pos (0UL) /*!< RX256_511OCTGB (Bit 0) */ + #define R_GMAC_Rx_256To511Octets_Frames_Good_Bad_RX256_511OCTGB_Msk (0xffffffffUL) /*!< RX256_511OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Rx_512To1023Octets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_512To1023Octets_Frames_Good_Bad_RX512_1023OCTGB_Pos (0UL) /*!< RX512_1023OCTGB (Bit 0) */ + #define R_GMAC_Rx_512To1023Octets_Frames_Good_Bad_RX512_1023OCTGB_Msk (0xffffffffUL) /*!< RX512_1023OCTGB (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Rx_1024ToMaxOctets_Frames_Good_Bad =========================================== */ + #define R_GMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_RX1024_MAXOCTGB_Pos (0UL) /*!< RX1024_MAXOCTGB (Bit 0) */ + #define R_GMAC_Rx_1024ToMaxOctets_Frames_Good_Bad_RX1024_MAXOCTGB_Msk (0xffffffffUL) /*!< RX1024_MAXOCTGB (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Rx_Unicast_Frames_Good ================================================= */ + #define R_GMAC_Rx_Unicast_Frames_Good_RXUCASTG_Pos (0UL) /*!< RXUCASTG (Bit 0) */ + #define R_GMAC_Rx_Unicast_Frames_Good_RXUCASTG_Msk (0xffffffffUL) /*!< RXUCASTG (Bitfield-Mask: 0xffffffff) */ +/* ================================================ Rx_Length_Error_Frames ================================================= */ + #define R_GMAC_Rx_Length_Error_Frames_RXLENERR_Pos (0UL) /*!< RXLENERR (Bit 0) */ + #define R_GMAC_Rx_Length_Error_Frames_RXLENERR_Msk (0xffffUL) /*!< RXLENERR (Bitfield-Mask: 0xffff) */ +/* ============================================== Rx_Out_Of_Range_Type_Frames ============================================== */ + #define R_GMAC_Rx_Out_Of_Range_Type_Frames_RXOUTOFRNG_Pos (0UL) /*!< RXOUTOFRNG (Bit 0) */ + #define R_GMAC_Rx_Out_Of_Range_Type_Frames_RXOUTOFRNG_Msk (0xffffUL) /*!< RXOUTOFRNG (Bitfield-Mask: 0xffff) */ +/* ==================================================== Rx_Pause_Frames ==================================================== */ + #define R_GMAC_Rx_Pause_Frames_RXPAUSEFRM_Pos (0UL) /*!< RXPAUSEFRM (Bit 0) */ + #define R_GMAC_Rx_Pause_Frames_RXPAUSEFRM_Msk (0xffffUL) /*!< RXPAUSEFRM (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_FIFO_Overflow_Frames ================================================ */ + #define R_GMAC_Rx_FIFO_Overflow_Frames_RXFIFOOVFL_Pos (0UL) /*!< RXFIFOOVFL (Bit 0) */ + #define R_GMAC_Rx_FIFO_Overflow_Frames_RXFIFOOVFL_Msk (0xffffUL) /*!< RXFIFOOVFL (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_VLAN_Frames_Good_Bad ================================================ */ + #define R_GMAC_Rx_VLAN_Frames_Good_Bad_RXVLANFRGB_Pos (0UL) /*!< RXVLANFRGB (Bit 0) */ + #define R_GMAC_Rx_VLAN_Frames_Good_Bad_RXVLANFRGB_Msk (0xffffffffUL) /*!< RXVLANFRGB (Bitfield-Mask: 0xffffffff) */ +/* =============================================== Rx_Watchdog_Error_Frames ================================================ */ + #define R_GMAC_Rx_Watchdog_Error_Frames_RXWDGERR_Pos (0UL) /*!< RXWDGERR (Bit 0) */ + #define R_GMAC_Rx_Watchdog_Error_Frames_RXWDGERR_Msk (0xffffUL) /*!< RXWDGERR (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Receive_Error_Frames ================================================ */ + #define R_GMAC_Rx_Receive_Error_Frames_RXRCVERR_Pos (0UL) /*!< RXRCVERR (Bit 0) */ + #define R_GMAC_Rx_Receive_Error_Frames_RXRCVERR_Msk (0xffffUL) /*!< RXRCVERR (Bitfield-Mask: 0xffff) */ +/* ================================================ Rx_Control_Frames_Good ================================================= */ + #define R_GMAC_Rx_Control_Frames_Good_RXCTRLG_Pos (0UL) /*!< RXCTRLG (Bit 0) */ + #define R_GMAC_Rx_Control_Frames_Good_RXCTRLG_Msk (0xffffffffUL) /*!< RXCTRLG (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== GMACTRGSEL ======================================================= */ + #define R_GMAC_GMACTRGSEL_TRGSEL_Pos (0UL) /*!< TRGSEL (Bit 0) */ + #define R_GMAC_GMACTRGSEL_TRGSEL_Msk (0x3UL) /*!< TRGSEL (Bitfield-Mask: 0x03) */ +/* ==================================================== HASH_TABLE_REG ===================================================== */ + #define R_GMAC_HASH_TABLE_REG_HT_Pos (0UL) /*!< HT (Bit 0) */ + #define R_GMAC_HASH_TABLE_REG_HT_Msk (0xffffffffUL) /*!< HT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== VLAN_Hash_Table_Reg ================================================== */ + #define R_GMAC_VLAN_Hash_Table_Reg_VLHT_Pos (0UL) /*!< VLHT (Bit 0) */ + #define R_GMAC_VLAN_Hash_Table_Reg_VLHT_Msk (0xffffUL) /*!< VLHT (Bitfield-Mask: 0xffff) */ +/* =================================================== Timestamp_Control =================================================== */ + #define R_GMAC_Timestamp_Control_TSENA_Pos (0UL) /*!< TSENA (Bit 0) */ + #define R_GMAC_Timestamp_Control_TSENA_Msk (0x1UL) /*!< TSENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSENALL_Pos (8UL) /*!< TSENALL (Bit 8) */ + #define R_GMAC_Timestamp_Control_TSENALL_Msk (0x100UL) /*!< TSENALL (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSCTRLSSR_Pos (9UL) /*!< TSCTRLSSR (Bit 9) */ + #define R_GMAC_Timestamp_Control_TSCTRLSSR_Msk (0x200UL) /*!< TSCTRLSSR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSVER2ENA_Pos (10UL) /*!< TSVER2ENA (Bit 10) */ + #define R_GMAC_Timestamp_Control_TSVER2ENA_Msk (0x400UL) /*!< TSVER2ENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSIPENA_Pos (11UL) /*!< TSIPENA (Bit 11) */ + #define R_GMAC_Timestamp_Control_TSIPENA_Msk (0x800UL) /*!< TSIPENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSIPV6ENA_Pos (12UL) /*!< TSIPV6ENA (Bit 12) */ + #define R_GMAC_Timestamp_Control_TSIPV6ENA_Msk (0x1000UL) /*!< TSIPV6ENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSIPV4ENA_Pos (13UL) /*!< TSIPV4ENA (Bit 13) */ + #define R_GMAC_Timestamp_Control_TSIPV4ENA_Msk (0x2000UL) /*!< TSIPV4ENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSEVNTENA_Pos (14UL) /*!< TSEVNTENA (Bit 14) */ + #define R_GMAC_Timestamp_Control_TSEVNTENA_Msk (0x4000UL) /*!< TSEVNTENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_TSMSTRENA_Pos (15UL) /*!< TSMSTRENA (Bit 15) */ + #define R_GMAC_Timestamp_Control_TSMSTRENA_Msk (0x8000UL) /*!< TSMSTRENA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_SNAPTYPSEL_Pos (16UL) /*!< SNAPTYPSEL (Bit 16) */ + #define R_GMAC_Timestamp_Control_SNAPTYPSEL_Msk (0x30000UL) /*!< SNAPTYPSEL (Bitfield-Mask: 0x03) */ + #define R_GMAC_Timestamp_Control_TSENMACADDR_Pos (18UL) /*!< TSENMACADDR (Bit 18) */ + #define R_GMAC_Timestamp_Control_TSENMACADDR_Msk (0x40000UL) /*!< TSENMACADDR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_ATSFC_Pos (24UL) /*!< ATSFC (Bit 24) */ + #define R_GMAC_Timestamp_Control_ATSFC_Msk (0x1000000UL) /*!< ATSFC (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_ATSEN0_Pos (25UL) /*!< ATSEN0 (Bit 25) */ + #define R_GMAC_Timestamp_Control_ATSEN0_Msk (0x2000000UL) /*!< ATSEN0 (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Control_ATSEN1_Pos (26UL) /*!< ATSEN1 (Bit 26) */ + #define R_GMAC_Timestamp_Control_ATSEN1_Msk (0x4000000UL) /*!< ATSEN1 (Bitfield-Mask: 0x01) */ +/* =================================================== Timestamp_Status ==================================================== */ + #define R_GMAC_Timestamp_Status_AUXTSTRIG_Pos (2UL) /*!< AUXTSTRIG (Bit 2) */ + #define R_GMAC_Timestamp_Status_AUXTSTRIG_Msk (0x4UL) /*!< AUXTSTRIG (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Status_ATSSTN_Pos (16UL) /*!< ATSSTN (Bit 16) */ + #define R_GMAC_Timestamp_Status_ATSSTN_Msk (0xf0000UL) /*!< ATSSTN (Bitfield-Mask: 0x0f) */ + #define R_GMAC_Timestamp_Status_ATSSTM_Pos (24UL) /*!< ATSSTM (Bit 24) */ + #define R_GMAC_Timestamp_Status_ATSSTM_Msk (0x1000000UL) /*!< ATSSTM (Bitfield-Mask: 0x01) */ + #define R_GMAC_Timestamp_Status_ATSNS_Pos (25UL) /*!< ATSNS (Bit 25) */ + #define R_GMAC_Timestamp_Status_ATSNS_Msk (0x3e000000UL) /*!< ATSNS (Bitfield-Mask: 0x1f) */ +/* ============================================ Auxiliary_Timestamp_Nanoseconds ============================================ */ + #define R_GMAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Pos (0UL) /*!< AUXTSLO (Bit 0) */ + #define R_GMAC_Auxiliary_Timestamp_Nanoseconds_AUXTSLO_Msk (0x7fffffffUL) /*!< AUXTSLO (Bitfield-Mask: 0x7fffffff) */ +/* ============================================== Auxiliary_Timestamp_Seconds ============================================== */ + #define R_GMAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Pos (0UL) /*!< AUXTSHI (Bit 0) */ + #define R_GMAC_Auxiliary_Timestamp_Seconds_AUXTSHI_Msk (0xffffffffUL) /*!< AUXTSHI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR16_H ======================================================== */ + #define R_GMAC_MAR16_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR16_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR16_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR16_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR16_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR16_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR16_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR16_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR16_L ======================================================== */ + #define R_GMAC_MAR16_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR16_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MAR17_H ======================================================== */ + #define R_GMAC_MAR17_H_ADDRHI_Pos (0UL) /*!< ADDRHI (Bit 0) */ + #define R_GMAC_MAR17_H_ADDRHI_Msk (0xffffUL) /*!< ADDRHI (Bitfield-Mask: 0xffff) */ + #define R_GMAC_MAR17_H_MBC_Pos (24UL) /*!< MBC (Bit 24) */ + #define R_GMAC_MAR17_H_MBC_Msk (0x3f000000UL) /*!< MBC (Bitfield-Mask: 0x3f) */ + #define R_GMAC_MAR17_H_SA_Pos (30UL) /*!< SA (Bit 30) */ + #define R_GMAC_MAR17_H_SA_Msk (0x40000000UL) /*!< SA (Bitfield-Mask: 0x01) */ + #define R_GMAC_MAR17_H_AE_Pos (31UL) /*!< AE (Bit 31) */ + #define R_GMAC_MAR17_H_AE_Msk (0x80000000UL) /*!< AE (Bitfield-Mask: 0x01) */ +/* ======================================================== MAR17_L ======================================================== */ + #define R_GMAC_MAR17_L_ADDRLO_Pos (0UL) /*!< ADDRLO (Bit 0) */ + #define R_GMAC_MAR17_L_ADDRLO_Msk (0xffffffffUL) /*!< ADDRLO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= Bus_Mode ======================================================== */ + #define R_GMAC_Bus_Mode_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_GMAC_Bus_Mode_SWR_Msk (0x1UL) /*!< SWR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_DA_Pos (1UL) /*!< DA (Bit 1) */ + #define R_GMAC_Bus_Mode_DA_Msk (0x2UL) /*!< DA (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_DSL_Pos (2UL) /*!< DSL (Bit 2) */ + #define R_GMAC_Bus_Mode_DSL_Msk (0x7cUL) /*!< DSL (Bitfield-Mask: 0x1f) */ + #define R_GMAC_Bus_Mode_ATDS_Pos (7UL) /*!< ATDS (Bit 7) */ + #define R_GMAC_Bus_Mode_ATDS_Msk (0x80UL) /*!< ATDS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_PBL_Pos (8UL) /*!< PBL (Bit 8) */ + #define R_GMAC_Bus_Mode_PBL_Msk (0x3f00UL) /*!< PBL (Bitfield-Mask: 0x3f) */ + #define R_GMAC_Bus_Mode_PR_Pos (14UL) /*!< PR (Bit 14) */ + #define R_GMAC_Bus_Mode_PR_Msk (0xc000UL) /*!< PR (Bitfield-Mask: 0x03) */ + #define R_GMAC_Bus_Mode_FB_Pos (16UL) /*!< FB (Bit 16) */ + #define R_GMAC_Bus_Mode_FB_Msk (0x10000UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_RPBL_Pos (17UL) /*!< RPBL (Bit 17) */ + #define R_GMAC_Bus_Mode_RPBL_Msk (0x7e0000UL) /*!< RPBL (Bitfield-Mask: 0x3f) */ + #define R_GMAC_Bus_Mode_USP_Pos (23UL) /*!< USP (Bit 23) */ + #define R_GMAC_Bus_Mode_USP_Msk (0x800000UL) /*!< USP (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_PBLx8_Pos (24UL) /*!< PBLx8 (Bit 24) */ + #define R_GMAC_Bus_Mode_PBLx8_Msk (0x1000000UL) /*!< PBLx8 (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_AAL_Pos (25UL) /*!< AAL (Bit 25) */ + #define R_GMAC_Bus_Mode_AAL_Msk (0x2000000UL) /*!< AAL (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_MB_Pos (26UL) /*!< MB (Bit 26) */ + #define R_GMAC_Bus_Mode_MB_Msk (0x4000000UL) /*!< MB (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_TXPR_Pos (27UL) /*!< TXPR (Bit 27) */ + #define R_GMAC_Bus_Mode_TXPR_Msk (0x8000000UL) /*!< TXPR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Bus_Mode_PRWG_Pos (28UL) /*!< PRWG (Bit 28) */ + #define R_GMAC_Bus_Mode_PRWG_Msk (0x30000000UL) /*!< PRWG (Bitfield-Mask: 0x03) */ + #define R_GMAC_Bus_Mode_RIB_Pos (31UL) /*!< RIB (Bit 31) */ + #define R_GMAC_Bus_Mode_RIB_Msk (0x80000000UL) /*!< RIB (Bitfield-Mask: 0x01) */ +/* ================================================= Transmit_Poll_Demand ================================================== */ + #define R_GMAC_Transmit_Poll_Demand_TPD_Pos (0UL) /*!< TPD (Bit 0) */ + #define R_GMAC_Transmit_Poll_Demand_TPD_Msk (0xffffffffUL) /*!< TPD (Bitfield-Mask: 0xffffffff) */ +/* ================================================== Receive_Poll_Demand ================================================== */ + #define R_GMAC_Receive_Poll_Demand_RPD_Pos (0UL) /*!< RPD (Bit 0) */ + #define R_GMAC_Receive_Poll_Demand_RPD_Msk (0xffffffffUL) /*!< RPD (Bitfield-Mask: 0xffffffff) */ +/* ============================================ Receive_Descriptor_List_Address ============================================ */ + #define R_GMAC_Receive_Descriptor_List_Address_RDESLA_32bit_Pos (2UL) /*!< RDESLA_32bit (Bit 2) */ + #define R_GMAC_Receive_Descriptor_List_Address_RDESLA_32bit_Msk (0xfffffffcUL) /*!< RDESLA_32bit (Bitfield-Mask: 0x3fffffff) */ +/* =========================================== Transmit_Descriptor_List_Address ============================================ */ + #define R_GMAC_Transmit_Descriptor_List_Address_TDESLA_32bit_Pos (2UL) /*!< TDESLA_32bit (Bit 2) */ + #define R_GMAC_Transmit_Descriptor_List_Address_TDESLA_32bit_Msk (0xfffffffcUL) /*!< TDESLA_32bit (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================== Status ========================================================= */ + #define R_GMAC_Status_TI_Pos (0UL) /*!< TI (Bit 0) */ + #define R_GMAC_Status_TI_Msk (0x1UL) /*!< TI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TPS_Pos (1UL) /*!< TPS (Bit 1) */ + #define R_GMAC_Status_TPS_Msk (0x2UL) /*!< TPS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TU_Pos (2UL) /*!< TU (Bit 2) */ + #define R_GMAC_Status_TU_Msk (0x4UL) /*!< TU (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TJT_Pos (3UL) /*!< TJT (Bit 3) */ + #define R_GMAC_Status_TJT_Msk (0x8UL) /*!< TJT (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_OVF_Pos (4UL) /*!< OVF (Bit 4) */ + #define R_GMAC_Status_OVF_Msk (0x10UL) /*!< OVF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_UNF_Pos (5UL) /*!< UNF (Bit 5) */ + #define R_GMAC_Status_UNF_Msk (0x20UL) /*!< UNF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RI_Pos (6UL) /*!< RI (Bit 6) */ + #define R_GMAC_Status_RI_Msk (0x40UL) /*!< RI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RU_Pos (7UL) /*!< RU (Bit 7) */ + #define R_GMAC_Status_RU_Msk (0x80UL) /*!< RU (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RPS_Pos (8UL) /*!< RPS (Bit 8) */ + #define R_GMAC_Status_RPS_Msk (0x100UL) /*!< RPS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RWT_Pos (9UL) /*!< RWT (Bit 9) */ + #define R_GMAC_Status_RWT_Msk (0x200UL) /*!< RWT (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_ETI_Pos (10UL) /*!< ETI (Bit 10) */ + #define R_GMAC_Status_ETI_Msk (0x400UL) /*!< ETI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_FBI_Pos (13UL) /*!< FBI (Bit 13) */ + #define R_GMAC_Status_FBI_Msk (0x2000UL) /*!< FBI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_ERI_Pos (14UL) /*!< ERI (Bit 14) */ + #define R_GMAC_Status_ERI_Msk (0x4000UL) /*!< ERI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_AIS_Pos (15UL) /*!< AIS (Bit 15) */ + #define R_GMAC_Status_AIS_Msk (0x8000UL) /*!< AIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_NIS_Pos (16UL) /*!< NIS (Bit 16) */ + #define R_GMAC_Status_NIS_Msk (0x10000UL) /*!< NIS (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_RS_Pos (17UL) /*!< RS (Bit 17) */ + #define R_GMAC_Status_RS_Msk (0xe0000UL) /*!< RS (Bitfield-Mask: 0x07) */ + #define R_GMAC_Status_TS_Pos (20UL) /*!< TS (Bit 20) */ + #define R_GMAC_Status_TS_Msk (0x700000UL) /*!< TS (Bitfield-Mask: 0x07) */ + #define R_GMAC_Status_EB_Pos (23UL) /*!< EB (Bit 23) */ + #define R_GMAC_Status_EB_Msk (0x3800000UL) /*!< EB (Bitfield-Mask: 0x07) */ + #define R_GMAC_Status_GMI_Pos (27UL) /*!< GMI (Bit 27) */ + #define R_GMAC_Status_GMI_Msk (0x8000000UL) /*!< GMI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_GPI_Pos (28UL) /*!< GPI (Bit 28) */ + #define R_GMAC_Status_GPI_Msk (0x10000000UL) /*!< GPI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_TTI_Pos (29UL) /*!< TTI (Bit 29) */ + #define R_GMAC_Status_TTI_Msk (0x20000000UL) /*!< TTI (Bitfield-Mask: 0x01) */ + #define R_GMAC_Status_GLPII_Pos (30UL) /*!< GLPII (Bit 30) */ + #define R_GMAC_Status_GLPII_Msk (0x40000000UL) /*!< GLPII (Bitfield-Mask: 0x01) */ +/* ==================================================== Operation_Mode ===================================================== */ + #define R_GMAC_Operation_Mode_SR_Pos (1UL) /*!< SR (Bit 1) */ + #define R_GMAC_Operation_Mode_SR_Msk (0x2UL) /*!< SR (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_OSF_Pos (2UL) /*!< OSF (Bit 2) */ + #define R_GMAC_Operation_Mode_OSF_Msk (0x4UL) /*!< OSF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_RTC_Pos (3UL) /*!< RTC (Bit 3) */ + #define R_GMAC_Operation_Mode_RTC_Msk (0x18UL) /*!< RTC (Bitfield-Mask: 0x03) */ + #define R_GMAC_Operation_Mode_DGF_Pos (5UL) /*!< DGF (Bit 5) */ + #define R_GMAC_Operation_Mode_DGF_Msk (0x20UL) /*!< DGF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_FUF_Pos (6UL) /*!< FUF (Bit 6) */ + #define R_GMAC_Operation_Mode_FUF_Msk (0x40UL) /*!< FUF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_FEF_Pos (7UL) /*!< FEF (Bit 7) */ + #define R_GMAC_Operation_Mode_FEF_Msk (0x80UL) /*!< FEF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_EFC_Pos (8UL) /*!< EFC (Bit 8) */ + #define R_GMAC_Operation_Mode_EFC_Msk (0x100UL) /*!< EFC (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_RFA_Pos (9UL) /*!< RFA (Bit 9) */ + #define R_GMAC_Operation_Mode_RFA_Msk (0x600UL) /*!< RFA (Bitfield-Mask: 0x03) */ + #define R_GMAC_Operation_Mode_RFD_Pos (11UL) /*!< RFD (Bit 11) */ + #define R_GMAC_Operation_Mode_RFD_Msk (0x1800UL) /*!< RFD (Bitfield-Mask: 0x03) */ + #define R_GMAC_Operation_Mode_ST_Pos (13UL) /*!< ST (Bit 13) */ + #define R_GMAC_Operation_Mode_ST_Msk (0x2000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_TTC_Pos (14UL) /*!< TTC (Bit 14) */ + #define R_GMAC_Operation_Mode_TTC_Msk (0x1c000UL) /*!< TTC (Bitfield-Mask: 0x07) */ + #define R_GMAC_Operation_Mode_FTF_Pos (20UL) /*!< FTF (Bit 20) */ + #define R_GMAC_Operation_Mode_FTF_Msk (0x100000UL) /*!< FTF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_TSF_Pos (21UL) /*!< TSF (Bit 21) */ + #define R_GMAC_Operation_Mode_TSF_Msk (0x200000UL) /*!< TSF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_RSF_Pos (25UL) /*!< RSF (Bit 25) */ + #define R_GMAC_Operation_Mode_RSF_Msk (0x2000000UL) /*!< RSF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Operation_Mode_DT_Pos (26UL) /*!< DT (Bit 26) */ + #define R_GMAC_Operation_Mode_DT_Msk (0x4000000UL) /*!< DT (Bitfield-Mask: 0x01) */ +/* =================================================== Interrupt_Enable ==================================================== */ + #define R_GMAC_Interrupt_Enable_TIE_Pos (0UL) /*!< TIE (Bit 0) */ + #define R_GMAC_Interrupt_Enable_TIE_Msk (0x1UL) /*!< TIE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_TSE_Pos (1UL) /*!< TSE (Bit 1) */ + #define R_GMAC_Interrupt_Enable_TSE_Msk (0x2UL) /*!< TSE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_TUE_Pos (2UL) /*!< TUE (Bit 2) */ + #define R_GMAC_Interrupt_Enable_TUE_Msk (0x4UL) /*!< TUE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_TJE_Pos (3UL) /*!< TJE (Bit 3) */ + #define R_GMAC_Interrupt_Enable_TJE_Msk (0x8UL) /*!< TJE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_OVE_Pos (4UL) /*!< OVE (Bit 4) */ + #define R_GMAC_Interrupt_Enable_OVE_Msk (0x10UL) /*!< OVE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_UNE_Pos (5UL) /*!< UNE (Bit 5) */ + #define R_GMAC_Interrupt_Enable_UNE_Msk (0x20UL) /*!< UNE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RIE_Pos (6UL) /*!< RIE (Bit 6) */ + #define R_GMAC_Interrupt_Enable_RIE_Msk (0x40UL) /*!< RIE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RUE_Pos (7UL) /*!< RUE (Bit 7) */ + #define R_GMAC_Interrupt_Enable_RUE_Msk (0x80UL) /*!< RUE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RSE_Pos (8UL) /*!< RSE (Bit 8) */ + #define R_GMAC_Interrupt_Enable_RSE_Msk (0x100UL) /*!< RSE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_RWE_Pos (9UL) /*!< RWE (Bit 9) */ + #define R_GMAC_Interrupt_Enable_RWE_Msk (0x200UL) /*!< RWE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_ETE_Pos (10UL) /*!< ETE (Bit 10) */ + #define R_GMAC_Interrupt_Enable_ETE_Msk (0x400UL) /*!< ETE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_FBE_Pos (13UL) /*!< FBE (Bit 13) */ + #define R_GMAC_Interrupt_Enable_FBE_Msk (0x2000UL) /*!< FBE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_ERE_Pos (14UL) /*!< ERE (Bit 14) */ + #define R_GMAC_Interrupt_Enable_ERE_Msk (0x4000UL) /*!< ERE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_AIE_Pos (15UL) /*!< AIE (Bit 15) */ + #define R_GMAC_Interrupt_Enable_AIE_Msk (0x8000UL) /*!< AIE (Bitfield-Mask: 0x01) */ + #define R_GMAC_Interrupt_Enable_NIE_Pos (16UL) /*!< NIE (Bit 16) */ + #define R_GMAC_Interrupt_Enable_NIE_Msk (0x10000UL) /*!< NIE (Bitfield-Mask: 0x01) */ +/* ======================================= Missed_Frame_And_Buffer_Overflow_Counter ======================================== */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISFRMCNT_Pos (0UL) /*!< MISFRMCNT (Bit 0) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISFRMCNT_Msk (0xffffUL) /*!< MISFRMCNT (Bitfield-Mask: 0xffff) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISCNTOVF_Pos (16UL) /*!< MISCNTOVF (Bit 16) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_MISCNTOVF_Msk (0x10000UL) /*!< MISCNTOVF (Bitfield-Mask: 0x01) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFFRMCNT_Pos (17UL) /*!< OVFFRMCNT (Bit 17) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFFRMCNT_Msk (0xffe0000UL) /*!< OVFFRMCNT (Bitfield-Mask: 0x7ff) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFCNTOVF_Pos (28UL) /*!< OVFCNTOVF (Bit 28) */ + #define R_GMAC_Missed_Frame_And_Buffer_Overflow_Counter_OVFCNTOVF_Msk (0x10000000UL) /*!< OVFCNTOVF (Bitfield-Mask: 0x01) */ +/* =========================================== Receive_Interrupt_Watchdog_Timer ============================================ */ + #define R_GMAC_Receive_Interrupt_Watchdog_Timer_RIWT_Pos (0UL) /*!< RIWT (Bit 0) */ + #define R_GMAC_Receive_Interrupt_Watchdog_Timer_RIWT_Msk (0xffUL) /*!< RIWT (Bitfield-Mask: 0xff) */ +/* ===================================================== AXI_Bus_Mode ====================================================== */ + #define R_GMAC_AXI_Bus_Mode_UNDEF_Pos (0UL) /*!< UNDEF (Bit 0) */ + #define R_GMAC_AXI_Bus_Mode_UNDEF_Msk (0x1UL) /*!< UNDEF (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_BLEN4_Pos (1UL) /*!< BLEN4 (Bit 1) */ + #define R_GMAC_AXI_Bus_Mode_BLEN4_Msk (0x2UL) /*!< BLEN4 (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_BLEN8_Pos (2UL) /*!< BLEN8 (Bit 2) */ + #define R_GMAC_AXI_Bus_Mode_BLEN8_Msk (0x4UL) /*!< BLEN8 (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_BLEN16_Pos (3UL) /*!< BLEN16 (Bit 3) */ + #define R_GMAC_AXI_Bus_Mode_BLEN16_Msk (0x8UL) /*!< BLEN16 (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_AXI_AAL_Pos (12UL) /*!< AXI_AAL (Bit 12) */ + #define R_GMAC_AXI_Bus_Mode_AXI_AAL_Msk (0x1000UL) /*!< AXI_AAL (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_ONEKBBE_Pos (13UL) /*!< ONEKBBE (Bit 13) */ + #define R_GMAC_AXI_Bus_Mode_ONEKBBE_Msk (0x2000UL) /*!< ONEKBBE (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_RD_OSR_LMT_Pos (16UL) /*!< RD_OSR_LMT (Bit 16) */ + #define R_GMAC_AXI_Bus_Mode_RD_OSR_LMT_Msk (0x30000UL) /*!< RD_OSR_LMT (Bitfield-Mask: 0x03) */ + #define R_GMAC_AXI_Bus_Mode_WR_OSR_LMT_Pos (20UL) /*!< WR_OSR_LMT (Bit 20) */ + #define R_GMAC_AXI_Bus_Mode_WR_OSR_LMT_Msk (0x300000UL) /*!< WR_OSR_LMT (Bitfield-Mask: 0x03) */ + #define R_GMAC_AXI_Bus_Mode_LPI_XIT_FRM_Pos (30UL) /*!< LPI_XIT_FRM (Bit 30) */ + #define R_GMAC_AXI_Bus_Mode_LPI_XIT_FRM_Msk (0x40000000UL) /*!< LPI_XIT_FRM (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Bus_Mode_EN_LPI_Pos (31UL) /*!< EN_LPI (Bit 31) */ + #define R_GMAC_AXI_Bus_Mode_EN_LPI_Msk (0x80000000UL) /*!< EN_LPI (Bitfield-Mask: 0x01) */ +/* ====================================================== AXI_Status ======================================================= */ + #define R_GMAC_AXI_Status_AXWHSTS_Pos (0UL) /*!< AXWHSTS (Bit 0) */ + #define R_GMAC_AXI_Status_AXWHSTS_Msk (0x1UL) /*!< AXWHSTS (Bitfield-Mask: 0x01) */ + #define R_GMAC_AXI_Status_AXIRDSTS_Pos (1UL) /*!< AXIRDSTS (Bit 1) */ + #define R_GMAC_AXI_Status_AXIRDSTS_Msk (0x2UL) /*!< AXIRDSTS (Bitfield-Mask: 0x01) */ +/* =========================================== Current_Host_Transmit_Descriptor ============================================ */ + #define R_GMAC_Current_Host_Transmit_Descriptor_CURTDESAPTR_Pos (0UL) /*!< CURTDESAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Transmit_Descriptor_CURTDESAPTR_Msk (0xffffffffUL) /*!< CURTDESAPTR (Bitfield-Mask: 0xffffffff) */ +/* ============================================ Current_Host_Receive_Descriptor ============================================ */ + #define R_GMAC_Current_Host_Receive_Descriptor_CURRDESAPTR_Pos (0UL) /*!< CURRDESAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Receive_Descriptor_CURRDESAPTR_Msk (0xffffffffUL) /*!< CURRDESAPTR (Bitfield-Mask: 0xffffffff) */ +/* ========================================= Current_Host_Transmit_Buffer_Address ========================================== */ + #define R_GMAC_Current_Host_Transmit_Buffer_Address_CURTBUFAPTR_Pos (0UL) /*!< CURTBUFAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Transmit_Buffer_Address_CURTBUFAPTR_Msk (0xffffffffUL) /*!< CURTBUFAPTR (Bitfield-Mask: 0xffffffff) */ +/* ========================================== Current_Host_Receive_Buffer_Address ========================================== */ + #define R_GMAC_Current_Host_Receive_Buffer_Address_CURRBUFAPTR_Pos (0UL) /*!< CURRBUFAPTR (Bit 0) */ + #define R_GMAC_Current_Host_Receive_Buffer_Address_CURRBUFAPTR_Msk (0xffffffffUL) /*!< CURRBUFAPTR (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== HW_Feature ======================================================= */ + #define R_GMAC_HW_Feature_MIISEL_Pos (0UL) /*!< MIISEL (Bit 0) */ + #define R_GMAC_HW_Feature_MIISEL_Msk (0x1UL) /*!< MIISEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_GMIISEL_Pos (1UL) /*!< GMIISEL (Bit 1) */ + #define R_GMAC_HW_Feature_GMIISEL_Msk (0x2UL) /*!< GMIISEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_HDSEL_Pos (2UL) /*!< HDSEL (Bit 2) */ + #define R_GMAC_HW_Feature_HDSEL_Msk (0x4UL) /*!< HDSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_EXTHASHEN_Pos (3UL) /*!< EXTHASHEN (Bit 3) */ + #define R_GMAC_HW_Feature_EXTHASHEN_Msk (0x8UL) /*!< EXTHASHEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_HASHSEL_Pos (4UL) /*!< HASHSEL (Bit 4) */ + #define R_GMAC_HW_Feature_HASHSEL_Msk (0x10UL) /*!< HASHSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_ADDMACADRSEL_Pos (5UL) /*!< ADDMACADRSEL (Bit 5) */ + #define R_GMAC_HW_Feature_ADDMACADRSEL_Msk (0x20UL) /*!< ADDMACADRSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_L3L4FLTREN_Pos (7UL) /*!< L3L4FLTREN (Bit 7) */ + #define R_GMAC_HW_Feature_L3L4FLTREN_Msk (0x80UL) /*!< L3L4FLTREN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_SMASEL_Pos (8UL) /*!< SMASEL (Bit 8) */ + #define R_GMAC_HW_Feature_SMASEL_Msk (0x100UL) /*!< SMASEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RWKSEL_Pos (9UL) /*!< RWKSEL (Bit 9) */ + #define R_GMAC_HW_Feature_RWKSEL_Msk (0x200UL) /*!< RWKSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_MGKSEL_Pos (10UL) /*!< MGKSEL (Bit 10) */ + #define R_GMAC_HW_Feature_MGKSEL_Msk (0x400UL) /*!< MGKSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_MMCSEL_Pos (11UL) /*!< MMCSEL (Bit 11) */ + #define R_GMAC_HW_Feature_MMCSEL_Msk (0x800UL) /*!< MMCSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_TSVER1SEL_Pos (12UL) /*!< TSVER1SEL (Bit 12) */ + #define R_GMAC_HW_Feature_TSVER1SEL_Msk (0x1000UL) /*!< TSVER1SEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_TSVER2SEL_Pos (13UL) /*!< TSVER2SEL (Bit 13) */ + #define R_GMAC_HW_Feature_TSVER2SEL_Msk (0x2000UL) /*!< TSVER2SEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_EEESEL_Pos (14UL) /*!< EEESEL (Bit 14) */ + #define R_GMAC_HW_Feature_EEESEL_Msk (0x4000UL) /*!< EEESEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_AVSEL_Pos (15UL) /*!< AVSEL (Bit 15) */ + #define R_GMAC_HW_Feature_AVSEL_Msk (0x8000UL) /*!< AVSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_TXCOESEL_Pos (16UL) /*!< TXCOESEL (Bit 16) */ + #define R_GMAC_HW_Feature_TXCOESEL_Msk (0x10000UL) /*!< TXCOESEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXTYP1COE_Pos (17UL) /*!< RXTYP1COE (Bit 17) */ + #define R_GMAC_HW_Feature_RXTYP1COE_Msk (0x20000UL) /*!< RXTYP1COE (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXTYP2COE_Pos (18UL) /*!< RXTYP2COE (Bit 18) */ + #define R_GMAC_HW_Feature_RXTYP2COE_Msk (0x40000UL) /*!< RXTYP2COE (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXFIFOSIZE_Pos (19UL) /*!< RXFIFOSIZE (Bit 19) */ + #define R_GMAC_HW_Feature_RXFIFOSIZE_Msk (0x80000UL) /*!< RXFIFOSIZE (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_RXCHCNT_Pos (20UL) /*!< RXCHCNT (Bit 20) */ + #define R_GMAC_HW_Feature_RXCHCNT_Msk (0x300000UL) /*!< RXCHCNT (Bitfield-Mask: 0x03) */ + #define R_GMAC_HW_Feature_TXCHCNT_Pos (22UL) /*!< TXCHCNT (Bit 22) */ + #define R_GMAC_HW_Feature_TXCHCNT_Msk (0xc00000UL) /*!< TXCHCNT (Bitfield-Mask: 0x03) */ + #define R_GMAC_HW_Feature_ENHDESSEL_Pos (24UL) /*!< ENHDESSEL (Bit 24) */ + #define R_GMAC_HW_Feature_ENHDESSEL_Msk (0x1000000UL) /*!< ENHDESSEL (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_INTTSEN_Pos (25UL) /*!< INTTSEN (Bit 25) */ + #define R_GMAC_HW_Feature_INTTSEN_Msk (0x2000000UL) /*!< INTTSEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_FLEXIPPSEN_Pos (26UL) /*!< FLEXIPPSEN (Bit 26) */ + #define R_GMAC_HW_Feature_FLEXIPPSEN_Msk (0x4000000UL) /*!< FLEXIPPSEN (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_SAVLANINS_Pos (27UL) /*!< SAVLANINS (Bit 27) */ + #define R_GMAC_HW_Feature_SAVLANINS_Msk (0x8000000UL) /*!< SAVLANINS (Bitfield-Mask: 0x01) */ + #define R_GMAC_HW_Feature_ACTPHYIF_Pos (28UL) /*!< ACTPHYIF (Bit 28) */ + #define R_GMAC_HW_Feature_ACTPHYIF_Msk (0x70000000UL) /*!< ACTPHYIF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRCMD ========================================================= */ +/* ======================================================== MODCTRL ======================================================== */ + #define R_ETHSS_MODCTRL_SW_MODE_Pos (0UL) /*!< SW_MODE (Bit 0) */ + #define R_ETHSS_MODCTRL_SW_MODE_Msk (0x7UL) /*!< SW_MODE (Bitfield-Mask: 0x07) */ +/* ======================================================= PTPMCTRL ======================================================== */ + #define R_ETHSS_PTPMCTRL_PTP_MODE_Pos (0UL) /*!< PTP_MODE (Bit 0) */ + #define R_ETHSS_PTPMCTRL_PTP_MODE_Msk (0x1UL) /*!< PTP_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Pos (16UL) /*!< PTP_PLS_RSTn (Bit 16) */ + #define R_ETHSS_PTPMCTRL_PTP_PLS_RSTn_Msk (0x10000UL) /*!< PTP_PLS_RSTn (Bitfield-Mask: 0x01) */ +/* ======================================================== PHYLNK ========================================================= */ + #define R_ETHSS_PHYLNK_SWLINK_Pos (0UL) /*!< SWLINK (Bit 0) */ + #define R_ETHSS_PHYLNK_SWLINK_Msk (0x7UL) /*!< SWLINK (Bitfield-Mask: 0x07) */ + #define R_ETHSS_PHYLNK_CATLNK_Pos (4UL) /*!< CATLNK (Bit 4) */ + #define R_ETHSS_PHYLNK_CATLNK_Msk (0x70UL) /*!< CATLNK (Bitfield-Mask: 0x07) */ +/* ======================================================= CONVCTRL ======================================================== */ + #define R_ETHSS_CONVCTRL_CONV_MODE_Pos (0UL) /*!< CONV_MODE (Bit 0) */ + #define R_ETHSS_CONVCTRL_CONV_MODE_Msk (0x1fUL) /*!< CONV_MODE (Bitfield-Mask: 0x1f) */ + #define R_ETHSS_CONVCTRL_FULLD_Pos (8UL) /*!< FULLD (Bit 8) */ + #define R_ETHSS_CONVCTRL_FULLD_Msk (0x100UL) /*!< FULLD (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Pos (9UL) /*!< RMII_RX_ER_EN (Bit 9) */ + #define R_ETHSS_CONVCTRL_RMII_RX_ER_EN_Msk (0x200UL) /*!< RMII_RX_ER_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Pos (10UL) /*!< RMII_CRS_MODE (Bit 10) */ + #define R_ETHSS_CONVCTRL_RMII_CRS_MODE_Msk (0x400UL) /*!< RMII_CRS_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RGMII_LINK_Pos (12UL) /*!< RGMII_LINK (Bit 12) */ + #define R_ETHSS_CONVCTRL_RGMII_LINK_Msk (0x1000UL) /*!< RGMII_LINK (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Pos (13UL) /*!< RGMII_DUPLEX (Bit 13) */ + #define R_ETHSS_CONVCTRL_RGMII_DUPLEX_Msk (0x2000UL) /*!< RGMII_DUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CONVCTRL_RGMII_SPEED_Pos (14UL) /*!< RGMII_SPEED (Bit 14) */ + #define R_ETHSS_CONVCTRL_RGMII_SPEED_Msk (0xc000UL) /*!< RGMII_SPEED (Bitfield-Mask: 0x03) */ +/* ======================================================== CONVRST ======================================================== */ + #define R_ETHSS_CONVRST_PHYIR_Pos (0UL) /*!< PHYIR (Bit 0) */ + #define R_ETHSS_CONVRST_PHYIR_Msk (0x7UL) /*!< PHYIR (Bitfield-Mask: 0x07) */ +/* ======================================================== SWCTRL ========================================================= */ + #define R_ETHSS_SWCTRL_SET10_Pos (0UL) /*!< SET10 (Bit 0) */ + #define R_ETHSS_SWCTRL_SET10_Msk (0x7UL) /*!< SET10 (Bitfield-Mask: 0x07) */ + #define R_ETHSS_SWCTRL_SET1000_Pos (4UL) /*!< SET1000 (Bit 4) */ + #define R_ETHSS_SWCTRL_SET1000_Msk (0x70UL) /*!< SET1000 (Bitfield-Mask: 0x07) */ + #define R_ETHSS_SWCTRL_STRAP_SX_ENB_Pos (16UL) /*!< STRAP_SX_ENB (Bit 16) */ + #define R_ETHSS_SWCTRL_STRAP_SX_ENB_Msk (0x10000UL) /*!< STRAP_SX_ENB (Bitfield-Mask: 0x01) */ + #define R_ETHSS_SWCTRL_STRAP_HUB_ENB_Pos (17UL) /*!< STRAP_HUB_ENB (Bit 17) */ + #define R_ETHSS_SWCTRL_STRAP_HUB_ENB_Msk (0x20000UL) /*!< STRAP_HUB_ENB (Bitfield-Mask: 0x01) */ +/* ======================================================== SWDUPC ========================================================= */ + #define R_ETHSS_SWDUPC_PHY_DUPLEX_Pos (0UL) /*!< PHY_DUPLEX (Bit 0) */ + #define R_ETHSS_SWDUPC_PHY_DUPLEX_Msk (0x7UL) /*!< PHY_DUPLEX (Bitfield-Mask: 0x07) */ +/* ========================================================= CDCR ========================================================== */ + #define R_ETHSS_CDCR_RXDLYEN_Pos (0UL) /*!< RXDLYEN (Bit 0) */ + #define R_ETHSS_CDCR_RXDLYEN_Msk (0x1UL) /*!< RXDLYEN (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CDCR_TXDLYEN_Pos (1UL) /*!< TXDLYEN (Bit 1) */ + #define R_ETHSS_CDCR_TXDLYEN_Msk (0x2UL) /*!< TXDLYEN (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CDCR_OSCCLKEN_Pos (2UL) /*!< OSCCLKEN (Bit 2) */ + #define R_ETHSS_CDCR_OSCCLKEN_Msk (0x4UL) /*!< OSCCLKEN (Bitfield-Mask: 0x01) */ + #define R_ETHSS_CDCR_CLKINEN_Pos (3UL) /*!< CLKINEN (Bit 3) */ + #define R_ETHSS_CDCR_CLKINEN_Msk (0x8UL) /*!< CLKINEN (Bitfield-Mask: 0x01) */ +/* ======================================================== RXFCNT ========================================================= */ + #define R_ETHSS_RXFCNT_RXFCNT_Pos (0UL) /*!< RXFCNT (Bit 0) */ + #define R_ETHSS_RXFCNT_RXFCNT_Msk (0xffffUL) /*!< RXFCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================== TXFCNT ========================================================= */ + #define R_ETHSS_TXFCNT_TXFCNT_Pos (0UL) /*!< TXFCNT (Bit 0) */ + #define R_ETHSS_TXFCNT_TXFCNT_Msk (0xffffUL) /*!< TXFCNT (Bitfield-Mask: 0xffff) */ +/* ======================================================= RXTAPSEL ======================================================== */ + #define R_ETHSS_RXTAPSEL_RXTAPSEL_Pos (0UL) /*!< RXTAPSEL (Bit 0) */ + #define R_ETHSS_RXTAPSEL_RXTAPSEL_Msk (0x7fUL) /*!< RXTAPSEL (Bitfield-Mask: 0x7f) */ +/* ======================================================= TXTAPSEL ======================================================== */ + #define R_ETHSS_TXTAPSEL_TXTAPSEL_Pos (0UL) /*!< TXTAPSEL (Bit 0) */ + #define R_ETHSS_TXTAPSEL_TXTAPSEL_Msk (0x7fUL) /*!< TXTAPSEL (Bitfield-Mask: 0x7f) */ +/* ======================================================== MIIMCR ========================================================= */ + #define R_ETHSS_MIIMCR_MIIM2MEN_Pos (0UL) /*!< MIIM2MEN (Bit 0) */ + #define R_ETHSS_MIIMCR_MIIM2MEN_Msk (0x1UL) /*!< MIIM2MEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC_INI ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== ECATOFFADR ======================================================= */ + #define R_ESC_INI_ECATOFFADR_OADD_Pos (0UL) /*!< OADD (Bit 0) */ + #define R_ESC_INI_ECATOFFADR_OADD_Msk (0x1fUL) /*!< OADD (Bitfield-Mask: 0x1f) */ +/* ======================================================= ECATOPMOD ======================================================= */ + #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Pos (0UL) /*!< EEPROMSIZE (Bit 0) */ + #define R_ESC_INI_ECATOPMOD_EEPROMSIZE_Msk (0x1UL) /*!< EEPROMSIZE (Bitfield-Mask: 0x01) */ +/* ======================================================= ECATDBGC ======================================================== */ + #define R_ESC_INI_ECATDBGC_TXSFT0_Pos (0UL) /*!< TXSFT0 (Bit 0) */ + #define R_ESC_INI_ECATDBGC_TXSFT0_Msk (0x3UL) /*!< TXSFT0 (Bitfield-Mask: 0x03) */ + #define R_ESC_INI_ECATDBGC_TXSFT1_Pos (2UL) /*!< TXSFT1 (Bit 2) */ + #define R_ESC_INI_ECATDBGC_TXSFT1_Msk (0xcUL) /*!< TXSFT1 (Bitfield-Mask: 0x03) */ + #define R_ESC_INI_ECATDBGC_TXSFT2_Pos (4UL) /*!< TXSFT2 (Bit 4) */ + #define R_ESC_INI_ECATDBGC_TXSFT2_Msk (0x30UL) /*!< TXSFT2 (Bitfield-Mask: 0x03) */ +/* ====================================================== ECATTRGSEL ======================================================= */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Pos (0UL) /*!< TRGSEL0 (Bit 0) */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL0_Msk (0x1UL) /*!< TRGSEL0 (Bitfield-Mask: 0x01) */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Pos (1UL) /*!< TRGSEL1 (Bit 1) */ + #define R_ESC_INI_ECATTRGSEL_TRGSEL1_Msk (0x2UL) /*!< TRGSEL1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSW_PTP ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== SWPTPOUTSEL ====================================================== */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL0_Pos (0UL) /*!< IOSEL0 (Bit 0) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL0_Msk (0x1UL) /*!< IOSEL0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL1_Pos (1UL) /*!< IOSEL1 (Bit 1) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL1_Msk (0x2UL) /*!< IOSEL1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL2_Pos (2UL) /*!< IOSEL2 (Bit 2) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL2_Msk (0x4UL) /*!< IOSEL2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL3_Pos (3UL) /*!< IOSEL3 (Bit 3) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_IOSEL3_Msk (0x8UL) /*!< IOSEL3 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL0_Pos (4UL) /*!< EVTSEL0 (Bit 4) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL0_Msk (0x10UL) /*!< EVTSEL0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL1_Pos (5UL) /*!< EVTSEL1 (Bit 5) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL1_Msk (0x20UL) /*!< EVTSEL1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL2_Pos (6UL) /*!< EVTSEL2 (Bit 6) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL2_Msk (0x40UL) /*!< EVTSEL2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL3_Pos (7UL) /*!< EVTSEL3 (Bit 7) */ + #define R_ETHSW_PTP_SWPTPOUTSEL_EVTSEL3_Msk (0x80UL) /*!< EVTSEL3 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ETHSW ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= REVISION ======================================================== */ + #define R_ETHSW_REVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ETHSW_REVISION_REV_Msk (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SCRATCH ======================================================== */ + #define R_ETHSW_SCRATCH_SCRATCH_Pos (0UL) /*!< SCRATCH (Bit 0) */ + #define R_ETHSW_SCRATCH_SCRATCH_Msk (0xffffffffUL) /*!< SCRATCH (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= PORT_ENA ======================================================== */ + #define R_ETHSW_PORT_ENA_TXENA_Pos (0UL) /*!< TXENA (Bit 0) */ + #define R_ETHSW_PORT_ENA_TXENA_Msk (0xfUL) /*!< TXENA (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_PORT_ENA_RXENA_Pos (16UL) /*!< RXENA (Bit 16) */ + #define R_ETHSW_PORT_ENA_RXENA_Msk (0xf0000UL) /*!< RXENA (Bitfield-Mask: 0x0f) */ +/* ================================================== UCAST_DEFAULT_MASK0 ================================================== */ + #define R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Pos (0UL) /*!< UCASTDM (Bit 0) */ + #define R_ETHSW_UCAST_DEFAULT_MASK0_UCASTDM_Msk (0xfUL) /*!< UCASTDM (Bitfield-Mask: 0x0f) */ +/* ====================================================== VLAN_VERIFY ====================================================== */ + #define R_ETHSW_VLAN_VERIFY_VLANVERI_Pos (0UL) /*!< VLANVERI (Bit 0) */ + #define R_ETHSW_VLAN_VERIFY_VLANVERI_Msk (0xfUL) /*!< VLANVERI (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_VLAN_VERIFY_VLANDISC_Pos (16UL) /*!< VLANDISC (Bit 16) */ + #define R_ETHSW_VLAN_VERIFY_VLANDISC_Msk (0xf0000UL) /*!< VLANDISC (Bitfield-Mask: 0x0f) */ +/* ================================================== BCAST_DEFAULT_MASK0 ================================================== */ + #define R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Pos (0UL) /*!< BCASTDM (Bit 0) */ + #define R_ETHSW_BCAST_DEFAULT_MASK0_BCASTDM_Msk (0xfUL) /*!< BCASTDM (Bitfield-Mask: 0x0f) */ +/* ================================================== MCAST_DEFAULT_MASK0 ================================================== */ + #define R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Pos (0UL) /*!< MCASTDM (Bit 0) */ + #define R_ETHSW_MCAST_DEFAULT_MASK0_MCASTDM_Msk (0xfUL) /*!< MCASTDM (Bitfield-Mask: 0x0f) */ +/* =================================================== INPUT_LEARN_BLOCK =================================================== */ + #define R_ETHSW_INPUT_LEARN_BLOCK_BLOCKEN_Pos (0UL) /*!< BLOCKEN (Bit 0) */ + #define R_ETHSW_INPUT_LEARN_BLOCK_BLOCKEN_Msk (0xfUL) /*!< BLOCKEN (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_INPUT_LEARN_BLOCK_LEARNDIS_Pos (16UL) /*!< LEARNDIS (Bit 16) */ + #define R_ETHSW_INPUT_LEARN_BLOCK_LEARNDIS_Msk (0xf0000UL) /*!< LEARNDIS (Bitfield-Mask: 0x0f) */ +/* ====================================================== MGMT_CONFIG ====================================================== */ + #define R_ETHSW_MGMT_CONFIG_PORT_Pos (0UL) /*!< PORT (Bit 0) */ + #define R_ETHSW_MGMT_CONFIG_PORT_Msk (0xfUL) /*!< PORT (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MGMT_CONFIG_MSG_TRANS_Pos (5UL) /*!< MSG_TRANS (Bit 5) */ + #define R_ETHSW_MGMT_CONFIG_MSG_TRANS_Msk (0x20UL) /*!< MSG_TRANS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_CONFIG_ENABLE_Pos (6UL) /*!< ENABLE (Bit 6) */ + #define R_ETHSW_MGMT_CONFIG_ENABLE_Msk (0x40UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_CONFIG_DISCARD_Pos (7UL) /*!< DISCARD (Bit 7) */ + #define R_ETHSW_MGMT_CONFIG_DISCARD_Msk (0x80UL) /*!< DISCARD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_CONFIG_MGMT_EN_Pos (8UL) /*!< MGMT_EN (Bit 8) */ + #define R_ETHSW_MGMT_CONFIG_MGMT_EN_Msk (0x100UL) /*!< MGMT_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_CONFIG_MGMT_DISC_Pos (9UL) /*!< MGMT_DISC (Bit 9) */ + #define R_ETHSW_MGMT_CONFIG_MGMT_DISC_Msk (0x200UL) /*!< MGMT_DISC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_CONFIG_PRIORITY_Pos (13UL) /*!< PRIORITY (Bit 13) */ + #define R_ETHSW_MGMT_CONFIG_PRIORITY_Msk (0xe000UL) /*!< PRIORITY (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MGMT_CONFIG_PORTMASK_Pos (16UL) /*!< PORTMASK (Bit 16) */ + #define R_ETHSW_MGMT_CONFIG_PORTMASK_Msk (0xf0000UL) /*!< PORTMASK (Bitfield-Mask: 0x0f) */ +/* ====================================================== MODE_CONFIG ====================================================== */ + #define R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Pos (8UL) /*!< CUT_THRU_EN (Bit 8) */ + #define R_ETHSW_MODE_CONFIG_CUT_THRU_EN_Msk (0xf00UL) /*!< CUT_THRU_EN (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MODE_CONFIG_STATSRESET_Pos (31UL) /*!< STATSRESET (Bit 31) */ + #define R_ETHSW_MODE_CONFIG_STATSRESET_Msk (0x80000000UL) /*!< STATSRESET (Bitfield-Mask: 0x01) */ +/* ===================================================== VLAN_IN_MODE ====================================================== */ + #define R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Pos (0UL) /*!< P0VLANINMD (Bit 0) */ + #define R_ETHSW_VLAN_IN_MODE_P0VLANINMD_Msk (0x3UL) /*!< P0VLANINMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Pos (2UL) /*!< P1VLANINMD (Bit 2) */ + #define R_ETHSW_VLAN_IN_MODE_P1VLANINMD_Msk (0xcUL) /*!< P1VLANINMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Pos (4UL) /*!< P2VLANINMD (Bit 4) */ + #define R_ETHSW_VLAN_IN_MODE_P2VLANINMD_Msk (0x30UL) /*!< P2VLANINMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Pos (6UL) /*!< P3VLANINMD (Bit 6) */ + #define R_ETHSW_VLAN_IN_MODE_P3VLANINMD_Msk (0xc0UL) /*!< P3VLANINMD (Bitfield-Mask: 0x03) */ +/* ===================================================== VLAN_OUT_MODE ===================================================== */ + #define R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Pos (0UL) /*!< P0VLANOUTMD (Bit 0) */ + #define R_ETHSW_VLAN_OUT_MODE_P0VLANOUTMD_Msk (0x3UL) /*!< P0VLANOUTMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Pos (2UL) /*!< P1VLANOUTMD (Bit 2) */ + #define R_ETHSW_VLAN_OUT_MODE_P1VLANOUTMD_Msk (0xcUL) /*!< P1VLANOUTMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Pos (4UL) /*!< P2VLANOUTMD (Bit 4) */ + #define R_ETHSW_VLAN_OUT_MODE_P2VLANOUTMD_Msk (0x30UL) /*!< P2VLANOUTMD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Pos (6UL) /*!< P3VLANOUTMD (Bit 6) */ + #define R_ETHSW_VLAN_OUT_MODE_P3VLANOUTMD_Msk (0xc0UL) /*!< P3VLANOUTMD (Bitfield-Mask: 0x03) */ +/* =================================================== VLAN_IN_MODE_ENA ==================================================== */ + #define R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Pos (0UL) /*!< VLANINMDEN (Bit 0) */ + #define R_ETHSW_VLAN_IN_MODE_ENA_VLANINMDEN_Msk (0xfUL) /*!< VLANINMDEN (Bitfield-Mask: 0x0f) */ +/* ====================================================== VLAN_TAG_ID ====================================================== */ + #define R_ETHSW_VLAN_TAG_ID_VLANTAGID_Pos (0UL) /*!< VLANTAGID (Bit 0) */ + #define R_ETHSW_VLAN_TAG_ID_VLANTAGID_Msk (0xffffUL) /*!< VLANTAGID (Bitfield-Mask: 0xffff) */ +/* =================================================== BCAST_STORM_LIMIT =================================================== */ + #define R_ETHSW_BCAST_STORM_LIMIT_TMOUT_Pos (0UL) /*!< TMOUT (Bit 0) */ + #define R_ETHSW_BCAST_STORM_LIMIT_TMOUT_Msk (0xffffUL) /*!< TMOUT (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_BCAST_STORM_LIMIT_BCASTLIMIT_Pos (16UL) /*!< BCASTLIMIT (Bit 16) */ + #define R_ETHSW_BCAST_STORM_LIMIT_BCASTLIMIT_Msk (0xffff0000UL) /*!< BCASTLIMIT (Bitfield-Mask: 0xffff) */ +/* =================================================== MCAST_STORM_LIMIT =================================================== */ + #define R_ETHSW_MCAST_STORM_LIMIT_MCASTLIMIT_Pos (16UL) /*!< MCASTLIMIT (Bit 16) */ + #define R_ETHSW_MCAST_STORM_LIMIT_MCASTLIMIT_Msk (0xffff0000UL) /*!< MCASTLIMIT (Bitfield-Mask: 0xffff) */ +/* ==================================================== MIRROR_CONTROL ===================================================== */ + #define R_ETHSW_MIRROR_CONTROL_PORT_Pos (0UL) /*!< PORT (Bit 0) */ + #define R_ETHSW_MIRROR_CONTROL_PORT_Msk (0x3UL) /*!< PORT (Bitfield-Mask: 0x03) */ + #define R_ETHSW_MIRROR_CONTROL_MIRROR_EN_Pos (4UL) /*!< MIRROR_EN (Bit 4) */ + #define R_ETHSW_MIRROR_CONTROL_MIRROR_EN_Msk (0x10UL) /*!< MIRROR_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_ING_MAP_EN_Pos (5UL) /*!< ING_MAP_EN (Bit 5) */ + #define R_ETHSW_MIRROR_CONTROL_ING_MAP_EN_Msk (0x20UL) /*!< ING_MAP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_EG_MAP_EN_Pos (6UL) /*!< EG_MAP_EN (Bit 6) */ + #define R_ETHSW_MIRROR_CONTROL_EG_MAP_EN_Msk (0x40UL) /*!< EG_MAP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_ING_SA_MATCH_Pos (7UL) /*!< ING_SA_MATCH (Bit 7) */ + #define R_ETHSW_MIRROR_CONTROL_ING_SA_MATCH_Msk (0x80UL) /*!< ING_SA_MATCH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_ING_DA_MATCH_Pos (8UL) /*!< ING_DA_MATCH (Bit 8) */ + #define R_ETHSW_MIRROR_CONTROL_ING_DA_MATCH_Msk (0x100UL) /*!< ING_DA_MATCH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_EG_SA_MATCH_Pos (9UL) /*!< EG_SA_MATCH (Bit 9) */ + #define R_ETHSW_MIRROR_CONTROL_EG_SA_MATCH_Msk (0x200UL) /*!< EG_SA_MATCH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MIRROR_CONTROL_EG_DA_MATCH_Pos (10UL) /*!< EG_DA_MATCH (Bit 10) */ + #define R_ETHSW_MIRROR_CONTROL_EG_DA_MATCH_Msk (0x400UL) /*!< EG_DA_MATCH (Bitfield-Mask: 0x01) */ +/* ===================================================== MIRROR_EG_MAP ===================================================== */ + #define R_ETHSW_MIRROR_EG_MAP_EMAP_Pos (0UL) /*!< EMAP (Bit 0) */ + #define R_ETHSW_MIRROR_EG_MAP_EMAP_Msk (0xfUL) /*!< EMAP (Bitfield-Mask: 0x0f) */ +/* ==================================================== MIRROR_ING_MAP ===================================================== */ + #define R_ETHSW_MIRROR_ING_MAP_IMAP_Pos (0UL) /*!< IMAP (Bit 0) */ + #define R_ETHSW_MIRROR_ING_MAP_IMAP_Msk (0xfUL) /*!< IMAP (Bitfield-Mask: 0x0f) */ +/* ===================================================== MIRROR_ISRC_0 ===================================================== */ + #define R_ETHSW_MIRROR_ISRC_0_ISRC_Pos (0UL) /*!< ISRC (Bit 0) */ + #define R_ETHSW_MIRROR_ISRC_0_ISRC_Msk (0xffffffffUL) /*!< ISRC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MIRROR_ISRC_1 ===================================================== */ + #define R_ETHSW_MIRROR_ISRC_1_ISRC_Pos (0UL) /*!< ISRC (Bit 0) */ + #define R_ETHSW_MIRROR_ISRC_1_ISRC_Msk (0xffffUL) /*!< ISRC (Bitfield-Mask: 0xffff) */ +/* ===================================================== MIRROR_IDST_0 ===================================================== */ + #define R_ETHSW_MIRROR_IDST_0_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_ETHSW_MIRROR_IDST_0_IDST_Msk (0xffffffffUL) /*!< IDST (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MIRROR_IDST_1 ===================================================== */ + #define R_ETHSW_MIRROR_IDST_1_IDST_Pos (0UL) /*!< IDST (Bit 0) */ + #define R_ETHSW_MIRROR_IDST_1_IDST_Msk (0xffffUL) /*!< IDST (Bitfield-Mask: 0xffff) */ +/* ===================================================== MIRROR_ESRC_0 ===================================================== */ + #define R_ETHSW_MIRROR_ESRC_0_ESRC_Pos (0UL) /*!< ESRC (Bit 0) */ + #define R_ETHSW_MIRROR_ESRC_0_ESRC_Msk (0xffffffffUL) /*!< ESRC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MIRROR_ESRC_1 ===================================================== */ + #define R_ETHSW_MIRROR_ESRC_1_ESRC_Pos (0UL) /*!< ESRC (Bit 0) */ + #define R_ETHSW_MIRROR_ESRC_1_ESRC_Msk (0xffffUL) /*!< ESRC (Bitfield-Mask: 0xffff) */ +/* ===================================================== MIRROR_EDST_0 ===================================================== */ + #define R_ETHSW_MIRROR_EDST_0_EDST_Pos (0UL) /*!< EDST (Bit 0) */ + #define R_ETHSW_MIRROR_EDST_0_EDST_Msk (0xffffffffUL) /*!< EDST (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MIRROR_EDST_1 ===================================================== */ + #define R_ETHSW_MIRROR_EDST_1_EDST_Pos (0UL) /*!< EDST (Bit 0) */ + #define R_ETHSW_MIRROR_EDST_1_EDST_Msk (0xffffUL) /*!< EDST (Bitfield-Mask: 0xffff) */ +/* ====================================================== MIRROR_CNT ======================================================= */ + #define R_ETHSW_MIRROR_CNT_CNT_Pos (0UL) /*!< CNT (Bit 0) */ + #define R_ETHSW_MIRROR_CNT_CNT_Msk (0xffUL) /*!< CNT (Bitfield-Mask: 0xff) */ +/* ================================================== UCAST_DEFAULT_MASK1 ================================================== */ + #define R_ETHSW_UCAST_DEFAULT_MASK1_UCASTDM1_Pos (0UL) /*!< UCASTDM1 (Bit 0) */ + #define R_ETHSW_UCAST_DEFAULT_MASK1_UCASTDM1_Msk (0xfUL) /*!< UCASTDM1 (Bitfield-Mask: 0x0f) */ +/* ================================================== BCAST_DEFAULT_MASK1 ================================================== */ + #define R_ETHSW_BCAST_DEFAULT_MASK1_BCASTDM1_Pos (0UL) /*!< BCASTDM1 (Bit 0) */ + #define R_ETHSW_BCAST_DEFAULT_MASK1_BCASTDM1_Msk (0xfUL) /*!< BCASTDM1 (Bitfield-Mask: 0x0f) */ +/* ================================================== MCAST_DEFAULT_MASK1 ================================================== */ + #define R_ETHSW_MCAST_DEFAULT_MASK1_MCASTDM1_Pos (0UL) /*!< MCASTDM1 (Bit 0) */ + #define R_ETHSW_MCAST_DEFAULT_MASK1_MCASTDM1_Msk (0xfUL) /*!< MCASTDM1 (Bitfield-Mask: 0x0f) */ +/* ================================================== PORT_XCAST_MASK_SEL ================================================== */ + #define R_ETHSW_PORT_XCAST_MASK_SEL_MSEL_Pos (0UL) /*!< MSEL (Bit 0) */ + #define R_ETHSW_PORT_XCAST_MASK_SEL_MSEL_Msk (0xfUL) /*!< MSEL (Bitfield-Mask: 0x0f) */ +/* =================================================== QMGR_ST_MINCELLS ==================================================== */ + #define R_ETHSW_QMGR_ST_MINCELLS_STMINCELLS_Pos (0UL) /*!< STMINCELLS (Bit 0) */ + #define R_ETHSW_QMGR_ST_MINCELLS_STMINCELLS_Msk (0x7ffUL) /*!< STMINCELLS (Bitfield-Mask: 0x7ff) */ +/* ===================================================== QMGR_RED_MIN4 ===================================================== */ + #define R_ETHSW_QMGR_RED_MIN4_CFGRED_MINTH4_Pos (0UL) /*!< CFGRED_MINTH4 (Bit 0) */ + #define R_ETHSW_QMGR_RED_MIN4_CFGRED_MINTH4_Msk (0xffffffffUL) /*!< CFGRED_MINTH4 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== QMGR_RED_MAX4 ===================================================== */ + #define R_ETHSW_QMGR_RED_MAX4_CFGRED_MAXTH4_Pos (0UL) /*!< CFGRED_MAXTH4 (Bit 0) */ + #define R_ETHSW_QMGR_RED_MAX4_CFGRED_MAXTH4_Msk (0xffffffffUL) /*!< CFGRED_MAXTH4 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== QMGR_RED_CONFIG ==================================================== */ + #define R_ETHSW_QMGR_RED_CONFIG_QUEUE_RED_EN_Pos (0UL) /*!< QUEUE_RED_EN (Bit 0) */ + #define R_ETHSW_QMGR_RED_CONFIG_QUEUE_RED_EN_Msk (0xfUL) /*!< QUEUE_RED_EN (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_QMGR_RED_CONFIG_GACTIVITY_EN_Pos (8UL) /*!< GACTIVITY_EN (Bit 8) */ + #define R_ETHSW_QMGR_RED_CONFIG_GACTIVITY_EN_Msk (0x100UL) /*!< GACTIVITY_EN (Bitfield-Mask: 0x01) */ +/* ====================================================== IMC_STATUS ======================================================= */ + #define R_ETHSW_IMC_STATUS_CELLS_AVAILABLE_Pos (0UL) /*!< CELLS_AVAILABLE (Bit 0) */ + #define R_ETHSW_IMC_STATUS_CELLS_AVAILABLE_Msk (0xffffffUL) /*!< CELLS_AVAILABLE (Bitfield-Mask: 0xffffff) */ + #define R_ETHSW_IMC_STATUS_CF_ERR_Pos (24UL) /*!< CF_ERR (Bit 24) */ + #define R_ETHSW_IMC_STATUS_CF_ERR_Msk (0x1000000UL) /*!< CF_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IMC_STATUS_DE_ERR_Pos (25UL) /*!< DE_ERR (Bit 25) */ + #define R_ETHSW_IMC_STATUS_DE_ERR_Msk (0x2000000UL) /*!< DE_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IMC_STATUS_DE_INIT_Pos (26UL) /*!< DE_INIT (Bit 26) */ + #define R_ETHSW_IMC_STATUS_DE_INIT_Msk (0x4000000UL) /*!< DE_INIT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IMC_STATUS_MEM_FULL_Pos (27UL) /*!< MEM_FULL (Bit 27) */ + #define R_ETHSW_IMC_STATUS_MEM_FULL_Msk (0x8000000UL) /*!< MEM_FULL (Bitfield-Mask: 0x01) */ +/* ===================================================== IMC_ERR_FULL ====================================================== */ + #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_FULL_Pos (0UL) /*!< IPC_ERR_FULL (Bit 0) */ + #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_FULL_Msk (0xfUL) /*!< IPC_ERR_FULL (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_TRUNC_Pos (16UL) /*!< IPC_ERR_TRUNC (Bit 16) */ + #define R_ETHSW_IMC_ERR_FULL_IPC_ERR_TRUNC_Msk (0xf0000UL) /*!< IPC_ERR_TRUNC (Bitfield-Mask: 0x0f) */ +/* ===================================================== IMC_ERR_IFACE ===================================================== */ + #define R_ETHSW_IMC_ERR_IFACE_IPC_ERR_IFACE_Pos (0UL) /*!< IPC_ERR_IFACE (Bit 0) */ + #define R_ETHSW_IMC_ERR_IFACE_IPC_ERR_IFACE_Msk (0xfUL) /*!< IPC_ERR_IFACE (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_ERR_IFACE_WBUF_OVF_Pos (16UL) /*!< WBUF_OVF (Bit 16) */ + #define R_ETHSW_IMC_ERR_IFACE_WBUF_OVF_Msk (0xf0000UL) /*!< WBUF_OVF (Bitfield-Mask: 0x0f) */ +/* ==================================================== IMC_ERR_QOFLOW ===================================================== */ + #define R_ETHSW_IMC_ERR_QOFLOW_OP_ERR_Pos (0UL) /*!< OP_ERR (Bit 0) */ + #define R_ETHSW_IMC_ERR_QOFLOW_OP_ERR_Msk (0xfUL) /*!< OP_ERR (Bitfield-Mask: 0x0f) */ +/* ====================================================== IMC_CONFIG ======================================================= */ + #define R_ETHSW_IMC_CONFIG_WFQ_EN_Pos (0UL) /*!< WFQ_EN (Bit 0) */ + #define R_ETHSW_IMC_CONFIG_WFQ_EN_Msk (0x1UL) /*!< WFQ_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IMC_CONFIG_RSV_ENA_Pos (1UL) /*!< RSV_ENA (Bit 1) */ + #define R_ETHSW_IMC_CONFIG_RSV_ENA_Msk (0x2UL) /*!< RSV_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IMC_CONFIG_SPEED_HIPRI_THR_Pos (2UL) /*!< SPEED_HIPRI_THR (Bit 2) */ + #define R_ETHSW_IMC_CONFIG_SPEED_HIPRI_THR_Msk (0x1cUL) /*!< SPEED_HIPRI_THR (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IMC_CONFIG_CTFL_EMPTY_MD_Pos (5UL) /*!< CTFL_EMPTY_MD (Bit 5) */ + #define R_ETHSW_IMC_CONFIG_CTFL_EMPTY_MD_Msk (0x20UL) /*!< CTFL_EMPTY_MD (Bitfield-Mask: 0x01) */ +/* ===================================================== IMC_ERR_ALLOC ===================================================== */ + #define R_ETHSW_IMC_ERR_ALLOC_DISC_FULL_Pos (0UL) /*!< DISC_FULL (Bit 0) */ + #define R_ETHSW_IMC_ERR_ALLOC_DISC_FULL_Msk (0xfUL) /*!< DISC_FULL (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_ERR_ALLOC_DISC_LATE_Pos (16UL) /*!< DISC_LATE (Bit 16) */ + #define R_ETHSW_IMC_ERR_ALLOC_DISC_LATE_Msk (0xf0000UL) /*!< DISC_LATE (Bitfield-Mask: 0x0f) */ +/* ======================================================= GPARSER0 ======================================================== */ + #define R_ETHSW_GPARSER0_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER0_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER0_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER0_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER0_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER0_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER0_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER0_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER0_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER0_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER0_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER0_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER0_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER0_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER0_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER0_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER1 ======================================================== */ + #define R_ETHSW_GPARSER1_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER1_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER1_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER1_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER1_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER1_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER1_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER1_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER1_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER1_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER1_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER1_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER1_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER1_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER1_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER1_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER2 ======================================================== */ + #define R_ETHSW_GPARSER2_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER2_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER2_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER2_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER2_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER2_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER2_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER2_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER2_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER2_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER2_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER2_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER2_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER2_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER2_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER2_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER3 ======================================================== */ + #define R_ETHSW_GPARSER3_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER3_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER3_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER3_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER3_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER3_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER3_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER3_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER3_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER3_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER3_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER3_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER3_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER3_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER3_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER3_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================== GARITH0 ======================================================== */ + #define R_ETHSW_GARITH0_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH0_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH0_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH0_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH0_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH0_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH0_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH0_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH0_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH0_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH0_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH0_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH0_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH0_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH0_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH0_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH1 ======================================================== */ + #define R_ETHSW_GARITH1_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH1_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH1_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH1_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH1_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH1_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH1_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH1_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH1_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH1_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH1_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH1_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH1_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH1_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH1_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH1_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH2 ======================================================== */ + #define R_ETHSW_GARITH2_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH2_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH2_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH2_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH2_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH2_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH2_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH2_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH2_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH2_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH2_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH2_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH2_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH2_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH2_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH2_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH3 ======================================================== */ + #define R_ETHSW_GARITH3_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH3_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH3_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH3_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH3_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH3_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH3_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH3_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH3_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH3_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH3_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH3_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH3_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH3_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH3_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH3_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================= GPARSER4 ======================================================== */ + #define R_ETHSW_GPARSER4_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER4_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER4_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER4_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER4_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER4_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER4_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER4_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER4_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER4_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER4_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER4_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER4_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER4_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER4_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER4_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER5 ======================================================== */ + #define R_ETHSW_GPARSER5_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER5_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER5_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER5_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER5_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER5_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER5_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER5_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER5_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER5_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER5_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER5_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER5_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER5_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER5_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER5_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER6 ======================================================== */ + #define R_ETHSW_GPARSER6_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER6_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER6_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER6_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER6_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER6_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER6_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER6_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER6_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER6_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER6_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER6_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER6_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER6_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER6_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER6_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================= GPARSER7 ======================================================== */ + #define R_ETHSW_GPARSER7_MASK_VAL2_Pos (0UL) /*!< MASK_VAL2 (Bit 0) */ + #define R_ETHSW_GPARSER7_MASK_VAL2_Msk (0xffUL) /*!< MASK_VAL2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER7_COMPARE_VAL_Pos (8UL) /*!< COMPARE_VAL (Bit 8) */ + #define R_ETHSW_GPARSER7_COMPARE_VAL_Msk (0xff00UL) /*!< COMPARE_VAL (Bitfield-Mask: 0xff) */ + #define R_ETHSW_GPARSER7_OFFSET_Pos (16UL) /*!< OFFSET (Bit 16) */ + #define R_ETHSW_GPARSER7_OFFSET_Msk (0x3f0000UL) /*!< OFFSET (Bitfield-Mask: 0x3f) */ + #define R_ETHSW_GPARSER7_OFFSET_DA_Pos (23UL) /*!< OFFSET_DA (Bit 23) */ + #define R_ETHSW_GPARSER7_OFFSET_DA_Msk (0x800000UL) /*!< OFFSET_DA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_VALID_Pos (24UL) /*!< VALID (Bit 24) */ + #define R_ETHSW_GPARSER7_VALID_Msk (0x1000000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_SKIPVLAN_Pos (25UL) /*!< SKIPVLAN (Bit 25) */ + #define R_ETHSW_GPARSER7_SKIPVLAN_Msk (0x2000000UL) /*!< SKIPVLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_IPDATA_Pos (26UL) /*!< IPDATA (Bit 26) */ + #define R_ETHSW_GPARSER7_IPDATA_Msk (0x4000000UL) /*!< IPDATA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_IPPROTOCOL_Pos (27UL) /*!< IPPROTOCOL (Bit 27) */ + #define R_ETHSW_GPARSER7_IPPROTOCOL_Msk (0x8000000UL) /*!< IPPROTOCOL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_CMP16_Pos (28UL) /*!< CMP16 (Bit 28) */ + #define R_ETHSW_GPARSER7_CMP16_Msk (0x10000000UL) /*!< CMP16 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_OFFSET_PLUS2_Pos (29UL) /*!< OFFSET_PLUS2 (Bit 29) */ + #define R_ETHSW_GPARSER7_OFFSET_PLUS2_Msk (0x20000000UL) /*!< OFFSET_PLUS2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GPARSER7_CMP_MASK_OR_Pos (30UL) /*!< CMP_MASK_OR (Bit 30) */ + #define R_ETHSW_GPARSER7_CMP_MASK_OR_Msk (0x40000000UL) /*!< CMP_MASK_OR (Bitfield-Mask: 0x01) */ +/* ======================================================== GARITH4 ======================================================== */ + #define R_ETHSW_GARITH4_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH4_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH4_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH4_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH4_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH4_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH4_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH4_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH4_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH4_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH4_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH4_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH4_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH4_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH4_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH4_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH5 ======================================================== */ + #define R_ETHSW_GARITH5_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH5_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH5_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH5_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH5_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH5_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH5_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH5_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH5_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH5_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH5_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH5_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH5_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH5_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH5_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH5_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH6 ======================================================== */ + #define R_ETHSW_GARITH6_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH6_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH6_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH6_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH6_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH6_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH6_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH6_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH6_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH6_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH6_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH6_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH6_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH6_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH6_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH6_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ======================================================== GARITH7 ======================================================== */ + #define R_ETHSW_GARITH7_NOT_INP_Pos (0UL) /*!< NOT_INP (Bit 0) */ + #define R_ETHSW_GARITH7_NOT_INP_Msk (0xfUL) /*!< NOT_INP (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH7_SEL_MATCH_Pos (8UL) /*!< SEL_MATCH (Bit 8) */ + #define R_ETHSW_GARITH7_SEL_MATCH_Msk (0xf00UL) /*!< SEL_MATCH (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_GARITH7_SEL_ARITH0_Pos (12UL) /*!< SEL_ARITH0 (Bit 12) */ + #define R_ETHSW_GARITH7_SEL_ARITH0_Msk (0x1000UL) /*!< SEL_ARITH0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH7_SEL_ARITH1_Pos (13UL) /*!< SEL_ARITH1 (Bit 13) */ + #define R_ETHSW_GARITH7_SEL_ARITH1_Msk (0x2000UL) /*!< SEL_ARITH1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH7_SEL_ARITH2_Pos (14UL) /*!< SEL_ARITH2 (Bit 14) */ + #define R_ETHSW_GARITH7_SEL_ARITH2_Msk (0x4000UL) /*!< SEL_ARITH2 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH7_OP_Pos (16UL) /*!< OP (Bit 16) */ + #define R_ETHSW_GARITH7_OP_Msk (0x10000UL) /*!< OP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH7_RESULT_INV_Pos (17UL) /*!< RESULT_INV (Bit 17) */ + #define R_ETHSW_GARITH7_RESULT_INV_Msk (0x20000UL) /*!< RESULT_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_GARITH7_SNP_MD_Pos (20UL) /*!< SNP_MD (Bit 20) */ + #define R_ETHSW_GARITH7_SNP_MD_Msk (0x300000UL) /*!< SNP_MD (Bitfield-Mask: 0x03) */ +/* ===================================================== VLAN_PRIORITY ===================================================== */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY0_Pos (0UL) /*!< PRIORITY0 (Bit 0) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY0_Msk (0x7UL) /*!< PRIORITY0 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY1_Pos (3UL) /*!< PRIORITY1 (Bit 3) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY1_Msk (0x38UL) /*!< PRIORITY1 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY2_Pos (6UL) /*!< PRIORITY2 (Bit 6) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY2_Msk (0x1c0UL) /*!< PRIORITY2 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY3_Pos (9UL) /*!< PRIORITY3 (Bit 9) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY3_Msk (0xe00UL) /*!< PRIORITY3 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY4_Pos (12UL) /*!< PRIORITY4 (Bit 12) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY4_Msk (0x7000UL) /*!< PRIORITY4 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY5_Pos (15UL) /*!< PRIORITY5 (Bit 15) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY5_Msk (0x38000UL) /*!< PRIORITY5 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY6_Pos (18UL) /*!< PRIORITY6 (Bit 18) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY6_Msk (0x1c0000UL) /*!< PRIORITY6 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY7_Pos (21UL) /*!< PRIORITY7 (Bit 21) */ + #define R_ETHSW_VLAN_PRIORITY_PRIORITY7_Msk (0xe00000UL) /*!< PRIORITY7 (Bitfield-Mask: 0x07) */ +/* ====================================================== IP_PRIORITY ====================================================== */ + #define R_ETHSW_IP_PRIORITY_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ + #define R_ETHSW_IP_PRIORITY_ADDRESS_Msk (0xffUL) /*!< ADDRESS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_IP_PRIORITY_IPV6SELECT_Pos (8UL) /*!< IPV6SELECT (Bit 8) */ + #define R_ETHSW_IP_PRIORITY_IPV6SELECT_Msk (0x100UL) /*!< IPV6SELECT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IP_PRIORITY_PRIORITY_Pos (9UL) /*!< PRIORITY (Bit 9) */ + #define R_ETHSW_IP_PRIORITY_PRIORITY_Msk (0xe00UL) /*!< PRIORITY (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IP_PRIORITY_READ_Pos (31UL) /*!< READ (Bit 31) */ + #define R_ETHSW_IP_PRIORITY_READ_Msk (0x80000000UL) /*!< READ (Bitfield-Mask: 0x01) */ +/* ===================================================== PRIORITY_CFG ====================================================== */ + #define R_ETHSW_PRIORITY_CFG_VLANEN_Pos (0UL) /*!< VLANEN (Bit 0) */ + #define R_ETHSW_PRIORITY_CFG_VLANEN_Msk (0x1UL) /*!< VLANEN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_CFG_IPEN_Pos (1UL) /*!< IPEN (Bit 1) */ + #define R_ETHSW_PRIORITY_CFG_IPEN_Msk (0x2UL) /*!< IPEN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_CFG_MACEN_Pos (2UL) /*!< MACEN (Bit 2) */ + #define R_ETHSW_PRIORITY_CFG_MACEN_Msk (0x4UL) /*!< MACEN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_CFG_TYPE_EN_Pos (3UL) /*!< TYPE_EN (Bit 3) */ + #define R_ETHSW_PRIORITY_CFG_TYPE_EN_Msk (0x8UL) /*!< TYPE_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Pos (4UL) /*!< DEFAULTPRI (Bit 4) */ + #define R_ETHSW_PRIORITY_CFG_DEFAULTPRI_Msk (0x70UL) /*!< DEFAULTPRI (Bitfield-Mask: 0x07) */ + #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_DIS_Pos (7UL) /*!< PCP_REMAP_DIS (Bit 7) */ + #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_DIS_Msk (0x80UL) /*!< PCP_REMAP_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_Pos (8UL) /*!< PCP_REMAP (Bit 8) */ + #define R_ETHSW_PRIORITY_CFG_PCP_REMAP_Msk (0xffffff00UL) /*!< PCP_REMAP (Bitfield-Mask: 0xffffff) */ +/* ==================================================== PRIORITY_TYPE1 ===================================================== */ + #define R_ETHSW_PRIORITY_TYPE1_TYPEVAL_Pos (0UL) /*!< TYPEVAL (Bit 0) */ + #define R_ETHSW_PRIORITY_TYPE1_TYPEVAL_Msk (0xffffUL) /*!< TYPEVAL (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_PRIORITY_TYPE1_VALID_Pos (16UL) /*!< VALID (Bit 16) */ + #define R_ETHSW_PRIORITY_TYPE1_VALID_Msk (0x10000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_TYPE1_PRIORITY_Pos (17UL) /*!< PRIORITY (Bit 17) */ + #define R_ETHSW_PRIORITY_TYPE1_PRIORITY_Msk (0xe0000UL) /*!< PRIORITY (Bitfield-Mask: 0x07) */ +/* ==================================================== PRIORITY_TYPE2 ===================================================== */ + #define R_ETHSW_PRIORITY_TYPE2_TYPEVAL_Pos (0UL) /*!< TYPEVAL (Bit 0) */ + #define R_ETHSW_PRIORITY_TYPE2_TYPEVAL_Msk (0xffffUL) /*!< TYPEVAL (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_PRIORITY_TYPE2_VALID_Pos (16UL) /*!< VALID (Bit 16) */ + #define R_ETHSW_PRIORITY_TYPE2_VALID_Msk (0x10000UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRIORITY_TYPE2_PRIORITY_Pos (17UL) /*!< PRIORITY (Bit 17) */ + #define R_ETHSW_PRIORITY_TYPE2_PRIORITY_Msk (0xe0000UL) /*!< PRIORITY (Bitfield-Mask: 0x07) */ +/* ====================================================== SRCFLT_ENA ======================================================= */ + #define R_ETHSW_SRCFLT_ENA_SRCENA_Pos (0UL) /*!< SRCENA (Bit 0) */ + #define R_ETHSW_SRCFLT_ENA_SRCENA_Msk (0x7UL) /*!< SRCENA (Bitfield-Mask: 0x07) */ + #define R_ETHSW_SRCFLT_ENA_DSTENA_Pos (16UL) /*!< DSTENA (Bit 16) */ + #define R_ETHSW_SRCFLT_ENA_DSTENA_Msk (0xf0000UL) /*!< DSTENA (Bitfield-Mask: 0x0f) */ +/* ==================================================== SRCFLT_CONTROL ===================================================== */ + #define R_ETHSW_SRCFLT_CONTROL_MGMT_FWD_Pos (0UL) /*!< MGMT_FWD (Bit 0) */ + #define R_ETHSW_SRCFLT_CONTROL_MGMT_FWD_Msk (0x1UL) /*!< MGMT_FWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_ENA_Pos (1UL) /*!< WATCHDOG_ENA (Bit 1) */ + #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_ENA_Msk (0x2UL) /*!< WATCHDOG_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_TIME_Pos (16UL) /*!< WATCHDOG_TIME (Bit 16) */ + #define R_ETHSW_SRCFLT_CONTROL_WATCHDOG_TIME_Msk (0xffff0000UL) /*!< WATCHDOG_TIME (Bitfield-Mask: 0xffff) */ +/* =================================================== SRCFLT_MACADDR_LO =================================================== */ + #define R_ETHSW_SRCFLT_MACADDR_LO_SRCFLT_MACADDR_Pos (0UL) /*!< SRCFLT_MACADDR (Bit 0) */ + #define R_ETHSW_SRCFLT_MACADDR_LO_SRCFLT_MACADDR_Msk (0xffffffffUL) /*!< SRCFLT_MACADDR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== SRCFLT_MACADDR_HI =================================================== */ + #define R_ETHSW_SRCFLT_MACADDR_HI_SRCFLT_MACADDR_Pos (0UL) /*!< SRCFLT_MACADDR (Bit 0) */ + #define R_ETHSW_SRCFLT_MACADDR_HI_SRCFLT_MACADDR_Msk (0xffffUL) /*!< SRCFLT_MACADDR (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_SRCFLT_MACADDR_HI_MASK_Pos (16UL) /*!< MASK (Bit 16) */ + #define R_ETHSW_SRCFLT_MACADDR_HI_MASK_Msk (0xffff0000UL) /*!< MASK (Bitfield-Mask: 0xffff) */ +/* ==================================================== PHY_FILTER_CFG ===================================================== */ + #define R_ETHSW_PHY_FILTER_CFG_FILTER_DURATION_Pos (0UL) /*!< FILTER_DURATION (Bit 0) */ + #define R_ETHSW_PHY_FILTER_CFG_FILTER_DURATION_Msk (0x1ffUL) /*!< FILTER_DURATION (Bitfield-Mask: 0x1ff) */ + #define R_ETHSW_PHY_FILTER_CFG_FLT_EN_Pos (16UL) /*!< FLT_EN (Bit 16) */ + #define R_ETHSW_PHY_FILTER_CFG_FLT_EN_Msk (0x70000UL) /*!< FLT_EN (Bitfield-Mask: 0x07) */ +/* ==================================================== SYSTEM_TAGINFO ===================================================== */ + #define R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Pos (0UL) /*!< SYSVLANINFO (Bit 0) */ + #define R_ETHSW_SYSTEM_TAGINFO_SYSVLANINFO_Msk (0xffffUL) /*!< SYSVLANINFO (Bitfield-Mask: 0xffff) */ +/* ======================================================= AUTH_PORT ======================================================= */ + #define R_ETHSW_AUTH_PORT_AUTH_Pos (0UL) /*!< AUTH (Bit 0) */ + #define R_ETHSW_AUTH_PORT_AUTH_Msk (0x1UL) /*!< AUTH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_CTRL_BOTH_Pos (1UL) /*!< CTRL_BOTH (Bit 1) */ + #define R_ETHSW_AUTH_PORT_CTRL_BOTH_Msk (0x2UL) /*!< CTRL_BOTH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_EAPOL_EN_Pos (2UL) /*!< EAPOL_EN (Bit 2) */ + #define R_ETHSW_AUTH_PORT_EAPOL_EN_Msk (0x4UL) /*!< EAPOL_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_GUEST_EN_Pos (3UL) /*!< GUEST_EN (Bit 3) */ + #define R_ETHSW_AUTH_PORT_GUEST_EN_Msk (0x8UL) /*!< GUEST_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_BPDU_EN_Pos (4UL) /*!< BPDU_EN (Bit 4) */ + #define R_ETHSW_AUTH_PORT_BPDU_EN_Msk (0x10UL) /*!< BPDU_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_EAPOL_UC_EN_Pos (5UL) /*!< EAPOL_UC_EN (Bit 5) */ + #define R_ETHSW_AUTH_PORT_EAPOL_UC_EN_Msk (0x20UL) /*!< EAPOL_UC_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_ACHG_UNAUTH_Pos (11UL) /*!< ACHG_UNAUTH (Bit 11) */ + #define R_ETHSW_AUTH_PORT_ACHG_UNAUTH_Msk (0x800UL) /*!< ACHG_UNAUTH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_AUTH_PORT_EAPOL_PNUM_Pos (12UL) /*!< EAPOL_PNUM (Bit 12) */ + #define R_ETHSW_AUTH_PORT_EAPOL_PNUM_Msk (0xf000UL) /*!< EAPOL_PNUM (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_AUTH_PORT_GUEST_MASK_Pos (16UL) /*!< GUEST_MASK (Bit 16) */ + #define R_ETHSW_AUTH_PORT_GUEST_MASK_Msk (0xf0000UL) /*!< GUEST_MASK (Bitfield-Mask: 0x0f) */ +/* ==================================================== VLAN_RES_TABLE ===================================================== */ + #define R_ETHSW_VLAN_RES_TABLE_PORTMASK_Pos (0UL) /*!< PORTMASK (Bit 0) */ + #define R_ETHSW_VLAN_RES_TABLE_PORTMASK_Msk (0xfUL) /*!< PORTMASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_VLAN_RES_TABLE_VLANID_Pos (4UL) /*!< VLANID (Bit 4) */ + #define R_ETHSW_VLAN_RES_TABLE_VLANID_Msk (0xfff0UL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_VLAN_RES_TABLE_RD_TAGMSK_Pos (28UL) /*!< RD_TAGMSK (Bit 28) */ + #define R_ETHSW_VLAN_RES_TABLE_RD_TAGMSK_Msk (0x10000000UL) /*!< RD_TAGMSK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_VLAN_RES_TABLE_WT_TAGMSK_Pos (29UL) /*!< WT_TAGMSK (Bit 29) */ + #define R_ETHSW_VLAN_RES_TABLE_WT_TAGMSK_Msk (0x20000000UL) /*!< WT_TAGMSK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_VLAN_RES_TABLE_WT_PRTMSK_Pos (30UL) /*!< WT_PRTMSK (Bit 30) */ + #define R_ETHSW_VLAN_RES_TABLE_WT_PRTMSK_Msk (0x40000000UL) /*!< WT_PRTMSK (Bitfield-Mask: 0x01) */ +/* ====================================================== TOTAL_DISC ======================================================= */ + #define R_ETHSW_TOTAL_DISC_TOTAL_DISC_Pos (0UL) /*!< TOTAL_DISC (Bit 0) */ + #define R_ETHSW_TOTAL_DISC_TOTAL_DISC_Msk (0xffffffffUL) /*!< TOTAL_DISC (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== TOTAL_BYT_DISC ===================================================== */ + #define R_ETHSW_TOTAL_BYT_DISC_TOTAL_BYT_DISC_Pos (0UL) /*!< TOTAL_BYT_DISC (Bit 0) */ + #define R_ETHSW_TOTAL_BYT_DISC_TOTAL_BYT_DISC_Msk (0xffffffffUL) /*!< TOTAL_BYT_DISC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TOTAL_FRM ======================================================= */ + #define R_ETHSW_TOTAL_FRM_TOTAL_FRM_Pos (0UL) /*!< TOTAL_FRM (Bit 0) */ + #define R_ETHSW_TOTAL_FRM_TOTAL_FRM_Msk (0xffffffffUL) /*!< TOTAL_FRM (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TOTAL_BYT_FRM ===================================================== */ + #define R_ETHSW_TOTAL_BYT_FRM_TOTAL_BYT_FRM_Pos (0UL) /*!< TOTAL_BYT_FRM (Bit 0) */ + #define R_ETHSW_TOTAL_BYT_FRM_TOTAL_BYT_FRM_Msk (0xffffffffUL) /*!< TOTAL_BYT_FRM (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IALK_CONTROL ====================================================== */ + #define R_ETHSW_IALK_CONTROL_IA_LKUP_ENA_Pos (0UL) /*!< IA_LKUP_ENA (Bit 0) */ + #define R_ETHSW_IALK_CONTROL_IA_LKUP_ENA_Msk (0xfUL) /*!< IA_LKUP_ENA (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IALK_CONTROL_CT_ENA_Pos (16UL) /*!< CT_ENA (Bit 16) */ + #define R_ETHSW_IALK_CONTROL_CT_ENA_Msk (0xf0000UL) /*!< CT_ENA (Bitfield-Mask: 0x0f) */ +/* ======================================================= IALK_OUI ======================================================== */ + #define R_ETHSW_IALK_OUI_IALK_OUI_Pos (0UL) /*!< IALK_OUI (Bit 0) */ + #define R_ETHSW_IALK_OUI_IALK_OUI_Msk (0xffffffUL) /*!< IALK_OUI (Bitfield-Mask: 0xffffff) */ +/* ====================================================== IALK_ID_MIN ====================================================== */ + #define R_ETHSW_IALK_ID_MIN_IALK_ID_MIN_Pos (0UL) /*!< IALK_ID_MIN (Bit 0) */ + #define R_ETHSW_IALK_ID_MIN_IALK_ID_MIN_Msk (0xffffffUL) /*!< IALK_ID_MIN (Bitfield-Mask: 0xffffff) */ +/* ====================================================== IALK_ID_MAX ====================================================== */ + #define R_ETHSW_IALK_ID_MAX_IALK_ID_MAX_Pos (0UL) /*!< IALK_ID_MAX (Bit 0) */ + #define R_ETHSW_IALK_ID_MAX_IALK_ID_MAX_Msk (0xffffffUL) /*!< IALK_ID_MAX (Bitfield-Mask: 0xffffff) */ +/* ====================================================== IALK_ID_SUB ====================================================== */ + #define R_ETHSW_IALK_ID_SUB_IALK_ID_SUB_Pos (0UL) /*!< IALK_ID_SUB (Bit 0) */ + #define R_ETHSW_IALK_ID_SUB_IALK_ID_SUB_Msk (0xffffffUL) /*!< IALK_ID_SUB (Bitfield-Mask: 0xffffff) */ +/* ==================================================== IALK_ID_CONFIG ===================================================== */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_Pos (0UL) /*!< INVLD_ID_FLOOD (Bit 0) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_Msk (0x1UL) /*!< INVLD_ID_FLOOD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_LRN_ENA_Pos (1UL) /*!< INVLD_ID_LRN_ENA (Bit 1) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_LRN_ENA_Msk (0x2UL) /*!< INVLD_ID_LRN_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_Pos (4UL) /*!< INVLD_ID_PRIO (Bit 4) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_Msk (0x70UL) /*!< INVLD_ID_PRIO (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_VLD_Pos (7UL) /*!< INVLD_ID_PRIO_VLD (Bit 7) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_PRIO_VLD_Msk (0x80UL) /*!< INVLD_ID_PRIO_VLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_MASK_Pos (16UL) /*!< INVLD_ID_FLOOD_MASK (Bit 16) */ + #define R_ETHSW_IALK_ID_CONFIG_INVLD_ID_FLOOD_MASK_Msk (0xf0000UL) /*!< INVLD_ID_FLOOD_MASK (Bitfield-Mask: 0x0f) */ +/* =================================================== IALK_VLAN_CONFIG ==================================================== */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_Pos (0UL) /*!< UNKWN_VLAN_FLOOD (Bit 0) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_Msk (0x1UL) /*!< UNKWN_VLAN_FLOOD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_LRN_ENA_Pos (1UL) /*!< UNKWN_VLAN_LRN_ENA (Bit 1) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_LRN_ENA_Msk (0x2UL) /*!< UNKWN_VLAN_LRN_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_Pos (4UL) /*!< UNKWN_VLAN_PRIO (Bit 4) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_Msk (0x70UL) /*!< UNKWN_VLAN_PRIO (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_VLD_Pos (7UL) /*!< UNKWN_VLAN_PRIO_VLD (Bit 7) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_PRIO_VLD_Msk (0x80UL) /*!< UNKWN_VLAN_PRIO_VLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_VLAN_CONFIG_VLANS_ENABLED_Pos (8UL) /*!< VLANS_ENABLED (Bit 8) */ + #define R_ETHSW_IALK_VLAN_CONFIG_VLANS_ENABLED_Msk (0x700UL) /*!< VLANS_ENABLED (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_MASK_Pos (16UL) /*!< UNKWN_VLAN_FLOOD_MASK (Bit 16) */ + #define R_ETHSW_IALK_VLAN_CONFIG_UNKWN_VLAN_FLOOD_MASK_Msk (0xf0000UL) /*!< UNKWN_VLAN_FLOOD_MASK (Bitfield-Mask: 0x0f) */ +/* ===================================================== IALK_TBL_ADDR ===================================================== */ + #define R_ETHSW_IALK_TBL_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ETHSW_IALK_TBL_ADDR_ADDR_Msk (0x1fffUL) /*!< ADDR (Bitfield-Mask: 0x1fff) */ + #define R_ETHSW_IALK_TBL_ADDR_AINC_Pos (28UL) /*!< AINC (Bit 28) */ + #define R_ETHSW_IALK_TBL_ADDR_AINC_Msk (0xf0000000UL) /*!< AINC (Bitfield-Mask: 0x0f) */ +/* ===================================================== IALK_TBL_DATA ===================================================== */ + #define R_ETHSW_IALK_TBL_DATA_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_ETHSW_IALK_TBL_DATA_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_TBL_DATA_FWD_MASK_Pos (1UL) /*!< FWD_MASK (Bit 1) */ + #define R_ETHSW_IALK_TBL_DATA_FWD_MASK_Msk (0x1eUL) /*!< FWD_MASK (Bitfield-Mask: 0x0f) */ +/* ====================================================== IALK_VLANID ====================================================== */ + #define R_ETHSW_IALK_VLANID_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_IALK_VLANID_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_IALK_VLANID_VLANID_ENA_Pos (12UL) /*!< VLANID_ENA (Bit 12) */ + #define R_ETHSW_IALK_VLANID_VLANID_ENA_Msk (0x1000UL) /*!< VLANID_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_VLANID_VLANID_LRN_ENA_Pos (13UL) /*!< VLANID_LRN_ENA (Bit 13) */ + #define R_ETHSW_IALK_VLANID_VLANID_LRN_ENA_Msk (0x2000UL) /*!< VLANID_LRN_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_IALK_VLANID_VLANID_FLOOD_MASK_Pos (16UL) /*!< VLANID_FLOOD_MASK (Bit 16) */ + #define R_ETHSW_IALK_VLANID_VLANID_FLOOD_MASK_Msk (0xf0000UL) /*!< VLANID_FLOOD_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IALK_VLANID_VLANID_PRIO_Pos (28UL) /*!< VLANID_PRIO (Bit 28) */ + #define R_ETHSW_IALK_VLANID_VLANID_PRIO_Msk (0x70000000UL) /*!< VLANID_PRIO (Bitfield-Mask: 0x07) */ + #define R_ETHSW_IALK_VLANID_VLANID_PRIO_VLD_Pos (31UL) /*!< VLANID_PRIO_VLD (Bit 31) */ + #define R_ETHSW_IALK_VLANID_VLANID_PRIO_VLD_Msk (0x80000000UL) /*!< VLANID_PRIO_VLD (Bitfield-Mask: 0x01) */ +/* ===================================================== IMC_QLEVEL_P ====================================================== */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE0_Pos (0UL) /*!< QUEUE0 (Bit 0) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE0_Msk (0xfUL) /*!< QUEUE0 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE1_Pos (4UL) /*!< QUEUE1 (Bit 4) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE1_Msk (0xf0UL) /*!< QUEUE1 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE2_Pos (8UL) /*!< QUEUE2 (Bit 8) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE2_Msk (0xf00UL) /*!< QUEUE2 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE3_Pos (12UL) /*!< QUEUE3 (Bit 12) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE3_Msk (0xf000UL) /*!< QUEUE3 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE4_Pos (16UL) /*!< QUEUE4 (Bit 16) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE4_Msk (0xf0000UL) /*!< QUEUE4 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE5_Pos (20UL) /*!< QUEUE5 (Bit 20) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE5_Msk (0xf00000UL) /*!< QUEUE5 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE6_Pos (24UL) /*!< QUEUE6 (Bit 24) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE6_Msk (0xf000000UL) /*!< QUEUE6 (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE7_Pos (28UL) /*!< QUEUE7 (Bit 28) */ + #define R_ETHSW_IMC_QLEVEL_P_QUEUE7_Msk (0xf0000000UL) /*!< QUEUE7 (Bitfield-Mask: 0x0f) */ +/* ======================================================== LK_CTRL ======================================================== */ + #define R_ETHSW_LK_CTRL_LKUP_EN_Pos (0UL) /*!< LKUP_EN (Bit 0) */ + #define R_ETHSW_LK_CTRL_LKUP_EN_Msk (0x1UL) /*!< LKUP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_LEARN_EN_Pos (1UL) /*!< LEARN_EN (Bit 1) */ + #define R_ETHSW_LK_CTRL_LEARN_EN_Msk (0x2UL) /*!< LEARN_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_AGING_EN_Pos (2UL) /*!< AGING_EN (Bit 2) */ + #define R_ETHSW_LK_CTRL_AGING_EN_Msk (0x4UL) /*!< AGING_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_ALW_MGRT_Pos (3UL) /*!< ALW_MGRT (Bit 3) */ + #define R_ETHSW_LK_CTRL_ALW_MGRT_Msk (0x8UL) /*!< ALW_MGRT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_DISC_UNK_DEST_Pos (4UL) /*!< DISC_UNK_DEST (Bit 4) */ + #define R_ETHSW_LK_CTRL_DISC_UNK_DEST_Msk (0x10UL) /*!< DISC_UNK_DEST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_CLRTBL_Pos (6UL) /*!< CLRTBL (Bit 6) */ + #define R_ETHSW_LK_CTRL_CLRTBL_Msk (0x40UL) /*!< CLRTBL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_IND_VLAN_Pos (7UL) /*!< IND_VLAN (Bit 7) */ + #define R_ETHSW_LK_CTRL_IND_VLAN_Msk (0x80UL) /*!< IND_VLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_CTRL_DISC_UNK_SRC_Pos (16UL) /*!< DISC_UNK_SRC (Bit 16) */ + #define R_ETHSW_LK_CTRL_DISC_UNK_SRC_Msk (0xf0000UL) /*!< DISC_UNK_SRC (Bitfield-Mask: 0x0f) */ +/* ======================================================= LK_STATUS ======================================================= */ + #define R_ETHSW_LK_STATUS_AGEADDR_Pos (0UL) /*!< AGEADDR (Bit 0) */ + #define R_ETHSW_LK_STATUS_AGEADDR_Msk (0xffffUL) /*!< AGEADDR (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_LK_STATUS_OVRF_Pos (16UL) /*!< OVRF (Bit 16) */ + #define R_ETHSW_LK_STATUS_OVRF_Msk (0x3fff0000UL) /*!< OVRF (Bitfield-Mask: 0x3fff) */ + #define R_ETHSW_LK_STATUS_LRNEVNT_Pos (31UL) /*!< LRNEVNT (Bit 31) */ + #define R_ETHSW_LK_STATUS_LRNEVNT_Msk (0x80000000UL) /*!< LRNEVNT (Bitfield-Mask: 0x01) */ +/* ===================================================== LK_ADDR_CTRL ====================================================== */ + #define R_ETHSW_LK_ADDR_CTRL_ADDR_MSK_Pos (0UL) /*!< ADDR_MSK (Bit 0) */ + #define R_ETHSW_LK_ADDR_CTRL_ADDR_MSK_Msk (0xfffUL) /*!< ADDR_MSK (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_LK_ADDR_CTRL_CLR_DYNAMIC_Pos (22UL) /*!< CLR_DYNAMIC (Bit 22) */ + #define R_ETHSW_LK_ADDR_CTRL_CLR_DYNAMIC_Msk (0x400000UL) /*!< CLR_DYNAMIC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_CLR_STATIC_Pos (23UL) /*!< CLR_STATIC (Bit 23) */ + #define R_ETHSW_LK_ADDR_CTRL_CLR_STATIC_Msk (0x800000UL) /*!< CLR_STATIC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_GETLASTNEW_Pos (24UL) /*!< GETLASTNEW (Bit 24) */ + #define R_ETHSW_LK_ADDR_CTRL_GETLASTNEW_Msk (0x1000000UL) /*!< GETLASTNEW (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_WRITE_Pos (25UL) /*!< WRITE (Bit 25) */ + #define R_ETHSW_LK_ADDR_CTRL_WRITE_Msk (0x2000000UL) /*!< WRITE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_READ_Pos (26UL) /*!< READ (Bit 26) */ + #define R_ETHSW_LK_ADDR_CTRL_READ_Msk (0x4000000UL) /*!< READ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_WAIT_COMP_Pos (27UL) /*!< WAIT_COMP (Bit 27) */ + #define R_ETHSW_LK_ADDR_CTRL_WAIT_COMP_Msk (0x8000000UL) /*!< WAIT_COMP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_LOOKUP_Pos (28UL) /*!< LOOKUP (Bit 28) */ + #define R_ETHSW_LK_ADDR_CTRL_LOOKUP_Msk (0x10000000UL) /*!< LOOKUP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_CLEAR_Pos (29UL) /*!< CLEAR (Bit 29) */ + #define R_ETHSW_LK_ADDR_CTRL_CLEAR_Msk (0x20000000UL) /*!< CLEAR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_DEL_PORT_Pos (30UL) /*!< DEL_PORT (Bit 30) */ + #define R_ETHSW_LK_ADDR_CTRL_DEL_PORT_Msk (0x40000000UL) /*!< DEL_PORT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_LK_ADDR_CTRL_BUSY_Pos (31UL) /*!< BUSY (Bit 31) */ + #define R_ETHSW_LK_ADDR_CTRL_BUSY_Msk (0x80000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ====================================================== LK_DATA_LO ======================================================= */ + #define R_ETHSW_LK_DATA_LO_MEMDATA_Pos (0UL) /*!< MEMDATA (Bit 0) */ + #define R_ETHSW_LK_DATA_LO_MEMDATA_Msk (0xffffffffUL) /*!< MEMDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== LK_DATA_HI ======================================================= */ + #define R_ETHSW_LK_DATA_HI_MEMDATA_Pos (0UL) /*!< MEMDATA (Bit 0) */ + #define R_ETHSW_LK_DATA_HI_MEMDATA_Msk (0x1ffffffUL) /*!< MEMDATA (Bitfield-Mask: 0x1ffffff) */ +/* ====================================================== LK_DATA_HI2 ====================================================== */ + #define R_ETHSW_LK_DATA_HI2_MEMDATA_Pos (8UL) /*!< MEMDATA (Bit 8) */ + #define R_ETHSW_LK_DATA_HI2_MEMDATA_Msk (0xfff00UL) /*!< MEMDATA (Bitfield-Mask: 0xfff) */ +/* ===================================================== LK_LEARNCOUNT ===================================================== */ + #define R_ETHSW_LK_LEARNCOUNT_LEARNCOUNT_Pos (0UL) /*!< LEARNCOUNT (Bit 0) */ + #define R_ETHSW_LK_LEARNCOUNT_LEARNCOUNT_Msk (0x1fffUL) /*!< LEARNCOUNT (Bitfield-Mask: 0x1fff) */ + #define R_ETHSW_LK_LEARNCOUNT_WRITE_MD_Pos (30UL) /*!< WRITE_MD (Bit 30) */ + #define R_ETHSW_LK_LEARNCOUNT_WRITE_MD_Msk (0xc0000000UL) /*!< WRITE_MD (Bitfield-Mask: 0x03) */ +/* ====================================================== LK_AGETIME ======================================================= */ + #define R_ETHSW_LK_AGETIME_AGETIME_Pos (0UL) /*!< AGETIME (Bit 0) */ + #define R_ETHSW_LK_AGETIME_AGETIME_Msk (0xffffffUL) /*!< AGETIME (Bitfield-Mask: 0xffffff) */ +/* ==================================================== MGMT_TAG_CONFIG ==================================================== */ + #define R_ETHSW_MGMT_TAG_CONFIG_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ETHSW_MGMT_TAG_CONFIG_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_TAG_CONFIG_AL_FRAMES_Pos (1UL) /*!< AL_FRAMES (Bit 1) */ + #define R_ETHSW_MGMT_TAG_CONFIG_AL_FRAMES_Msk (0x2UL) /*!< AL_FRAMES (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TYPE1_EN_Pos (4UL) /*!< TYPE1_EN (Bit 4) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TYPE1_EN_Msk (0x10UL) /*!< TYPE1_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TYPE2_EN_Pos (5UL) /*!< TYPE2_EN (Bit 5) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TYPE2_EN_Msk (0x20UL) /*!< TYPE2_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TAGFIELD_Pos (16UL) /*!< TAGFIELD (Bit 16) */ + #define R_ETHSW_MGMT_TAG_CONFIG_TAGFIELD_Msk (0xffff0000UL) /*!< TAGFIELD (Bitfield-Mask: 0xffff) */ +/* ====================================================== TSM_CONFIG ======================================================= */ + #define R_ETHSW_TSM_CONFIG_IRQ_EN_Pos (0UL) /*!< IRQ_EN (Bit 0) */ + #define R_ETHSW_TSM_CONFIG_IRQ_EN_Msk (0x1UL) /*!< IRQ_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TEST_Pos (1UL) /*!< IRQ_TEST (Bit 1) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TEST_Msk (0x2UL) /*!< IRQ_TEST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TSFIFO_OVR_Pos (2UL) /*!< IRQ_TSFIFO_OVR (Bit 2) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TSFIFO_OVR_Msk (0x4UL) /*!< IRQ_TSFIFO_OVR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_CONFIG_IRQ_EVT_OFFSET_Pos (4UL) /*!< IRQ_EVT_OFFSET (Bit 4) */ + #define R_ETHSW_TSM_CONFIG_IRQ_EVT_OFFSET_Msk (0x30UL) /*!< IRQ_EVT_OFFSET (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_CONFIG_IRQ_EVT_PERIOD_Pos (8UL) /*!< IRQ_EVT_PERIOD (Bit 8) */ + #define R_ETHSW_TSM_CONFIG_IRQ_EVT_PERIOD_Msk (0x300UL) /*!< IRQ_EVT_PERIOD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_CONFIG_IRQ_ATIME_OVER_Pos (12UL) /*!< IRQ_ATIME_OVER (Bit 12) */ + #define R_ETHSW_TSM_CONFIG_IRQ_ATIME_OVER_Msk (0x3000UL) /*!< IRQ_ATIME_OVER (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Pos (16UL) /*!< IRQ_TX_EN (Bit 16) */ + #define R_ETHSW_TSM_CONFIG_IRQ_TX_EN_Msk (0xf0000UL) /*!< IRQ_TX_EN (Bitfield-Mask: 0x0f) */ +/* =================================================== TSM_IRQ_STAT_ACK ==================================================== */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_STAT_Pos (0UL) /*!< IRQ_STAT (Bit 0) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_STAT_Msk (0x1UL) /*!< IRQ_STAT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TEST_Pos (1UL) /*!< IRQ_TEST (Bit 1) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TEST_Msk (0x2UL) /*!< IRQ_TEST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TSFIFO_OVR_Pos (2UL) /*!< IRQ_TSFIFO_OVR (Bit 2) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TSFIFO_OVR_Msk (0x4UL) /*!< IRQ_TSFIFO_OVR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_OFFSET_Pos (4UL) /*!< IRQ_EVT_OFFSET (Bit 4) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_OFFSET_Msk (0x30UL) /*!< IRQ_EVT_OFFSET (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_PERIOD_Pos (8UL) /*!< IRQ_EVT_PERIOD (Bit 8) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_EVT_PERIOD_Msk (0x300UL) /*!< IRQ_EVT_PERIOD (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_ATIME_OVER_Pos (12UL) /*!< IRQ_ATIME_OVER (Bit 12) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_ATIME_OVER_Msk (0x3000UL) /*!< IRQ_ATIME_OVER (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Pos (16UL) /*!< IRQ_TX (Bit 16) */ + #define R_ETHSW_TSM_IRQ_STAT_ACK_IRQ_TX_Msk (0xf0000UL) /*!< IRQ_TX (Bitfield-Mask: 0x0f) */ +/* ====================================================== PTP_DOMAIN ======================================================= */ + #define R_ETHSW_PTP_DOMAIN_DOMAIN0_Pos (0UL) /*!< DOMAIN0 (Bit 0) */ + #define R_ETHSW_PTP_DOMAIN_DOMAIN0_Msk (0xffUL) /*!< DOMAIN0 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTP_DOMAIN_DOMAIN1_Pos (8UL) /*!< DOMAIN1 (Bit 8) */ + #define R_ETHSW_PTP_DOMAIN_DOMAIN1_Msk (0xff00UL) /*!< DOMAIN1 (Bitfield-Mask: 0xff) */ +/* ==================================================== PEERDELAY_P0_T0 ==================================================== */ + #define R_ETHSW_PEERDELAY_P0_T0_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P0_T0_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P1_T0 ==================================================== */ + #define R_ETHSW_PEERDELAY_P1_T0_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P1_T0_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P2_T0 ==================================================== */ + #define R_ETHSW_PEERDELAY_P2_T0_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P2_T0_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P3_T0 ==================================================== */ + #define R_ETHSW_PEERDELAY_P3_T0_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P3_T0_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P0_T1 ==================================================== */ + #define R_ETHSW_PEERDELAY_P0_T1_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P0_T1_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P1_T1 ==================================================== */ + #define R_ETHSW_PEERDELAY_P1_T1_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P1_T1_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P2_T1 ==================================================== */ + #define R_ETHSW_PEERDELAY_P2_T1_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P2_T1_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== PEERDELAY_P3_T1 ==================================================== */ + #define R_ETHSW_PEERDELAY_P3_T1_PEERDELAY_Pos (0UL) /*!< PEERDELAY (Bit 0) */ + #define R_ETHSW_PEERDELAY_P3_T1_PEERDELAY_Msk (0x3fffffffUL) /*!< PEERDELAY (Bitfield-Mask: 0x3fffffff) */ +/* ==================================================== TS_FIFO_STATUS ===================================================== */ + #define R_ETHSW_TS_FIFO_STATUS_FF_VALID_Pos (0UL) /*!< FF_VALID (Bit 0) */ + #define R_ETHSW_TS_FIFO_STATUS_FF_VALID_Msk (0xfUL) /*!< FF_VALID (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_TS_FIFO_STATUS_FF_OVR_Pos (16UL) /*!< FF_OVR (Bit 16) */ + #define R_ETHSW_TS_FIFO_STATUS_FF_OVR_Msk (0xf0000UL) /*!< FF_OVR (Bitfield-Mask: 0x0f) */ +/* =================================================== TS_FIFO_READ_CTRL =================================================== */ + #define R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Pos (0UL) /*!< PORT_NUM (Bit 0) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_PORT_NUM_Msk (0x3UL) /*!< PORT_NUM (Bitfield-Mask: 0x03) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Pos (4UL) /*!< TS_VALID (Bit 4) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_VALID_Msk (0x10UL) /*!< TS_VALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Pos (6UL) /*!< TS_SEL (Bit 6) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_SEL_Msk (0x40UL) /*!< TS_SEL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Pos (8UL) /*!< TS_ID (Bit 8) */ + #define R_ETHSW_TS_FIFO_READ_CTRL_TS_ID_Msk (0x7f00UL) /*!< TS_ID (Bitfield-Mask: 0x7f) */ +/* ================================================ TS_FIFO_READ_TIMESTAMP ================================================= */ + #define R_ETHSW_TS_FIFO_READ_TIMESTAMP_TIMESTAMP_Pos (0UL) /*!< TIMESTAMP (Bit 0) */ + #define R_ETHSW_TS_FIFO_READ_TIMESTAMP_TIMESTAMP_Msk (0xffffffffUL) /*!< TIMESTAMP (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== INT_CONFIG ======================================================= */ + #define R_ETHSW_INT_CONFIG_IRQ_EN_Pos (0UL) /*!< IRQ_EN (Bit 0) */ + #define R_ETHSW_INT_CONFIG_IRQ_EN_Msk (0x1UL) /*!< IRQ_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_MDIO1_Pos (1UL) /*!< MDIO1 (Bit 1) */ + #define R_ETHSW_INT_CONFIG_MDIO1_Msk (0x2UL) /*!< MDIO1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_LK_NEW_SRC_Pos (3UL) /*!< LK_NEW_SRC (Bit 3) */ + #define R_ETHSW_INT_CONFIG_LK_NEW_SRC_Msk (0x8UL) /*!< LK_NEW_SRC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_IRQ_TEST_Pos (4UL) /*!< IRQ_TEST (Bit 4) */ + #define R_ETHSW_INT_CONFIG_IRQ_TEST_Msk (0x10UL) /*!< IRQ_TEST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_DLR_INT_Pos (5UL) /*!< DLR_INT (Bit 5) */ + #define R_ETHSW_INT_CONFIG_DLR_INT_Msk (0x20UL) /*!< DLR_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_PRP_INT_Pos (6UL) /*!< PRP_INT (Bit 6) */ + #define R_ETHSW_INT_CONFIG_PRP_INT_Msk (0x40UL) /*!< PRP_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_HUB_INT_Pos (7UL) /*!< HUB_INT (Bit 7) */ + #define R_ETHSW_INT_CONFIG_HUB_INT_Msk (0x80UL) /*!< HUB_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_IRQ_LINK_Pos (8UL) /*!< IRQ_LINK (Bit 8) */ + #define R_ETHSW_INT_CONFIG_IRQ_LINK_Msk (0x700UL) /*!< IRQ_LINK (Bitfield-Mask: 0x07) */ + #define R_ETHSW_INT_CONFIG_IRQ_MAC_EEE_Pos (16UL) /*!< IRQ_MAC_EEE (Bit 16) */ + #define R_ETHSW_INT_CONFIG_IRQ_MAC_EEE_Msk (0x70000UL) /*!< IRQ_MAC_EEE (Bitfield-Mask: 0x07) */ + #define R_ETHSW_INT_CONFIG_EFP_INT_Pos (27UL) /*!< EFP_INT (Bit 27) */ + #define R_ETHSW_INT_CONFIG_EFP_INT_Msk (0x8000000UL) /*!< EFP_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_SRCFLT_WD_INT_Pos (28UL) /*!< SRCFLT_WD_INT (Bit 28) */ + #define R_ETHSW_INT_CONFIG_SRCFLT_WD_INT_Msk (0x10000000UL) /*!< SRCFLT_WD_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_TSM_INT_Pos (29UL) /*!< TSM_INT (Bit 29) */ + #define R_ETHSW_INT_CONFIG_TSM_INT_Msk (0x20000000UL) /*!< TSM_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_TDMA_INT_Pos (30UL) /*!< TDMA_INT (Bit 30) */ + #define R_ETHSW_INT_CONFIG_TDMA_INT_Msk (0x40000000UL) /*!< TDMA_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_CONFIG_PATTERN_INT_Pos (31UL) /*!< PATTERN_INT (Bit 31) */ + #define R_ETHSW_INT_CONFIG_PATTERN_INT_Msk (0x80000000UL) /*!< PATTERN_INT (Bitfield-Mask: 0x01) */ +/* ===================================================== INT_STAT_ACK ====================================================== */ + #define R_ETHSW_INT_STAT_ACK_IRQ_PEND_Pos (0UL) /*!< IRQ_PEND (Bit 0) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_PEND_Msk (0x1UL) /*!< IRQ_PEND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_MDIO1_Pos (1UL) /*!< MDIO1 (Bit 1) */ + #define R_ETHSW_INT_STAT_ACK_MDIO1_Msk (0x2UL) /*!< MDIO1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_LK_NEW_SRC_Pos (3UL) /*!< LK_NEW_SRC (Bit 3) */ + #define R_ETHSW_INT_STAT_ACK_LK_NEW_SRC_Msk (0x8UL) /*!< LK_NEW_SRC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_TEST_Pos (4UL) /*!< IRQ_TEST (Bit 4) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_TEST_Msk (0x10UL) /*!< IRQ_TEST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_DLR_INT_Pos (5UL) /*!< DLR_INT (Bit 5) */ + #define R_ETHSW_INT_STAT_ACK_DLR_INT_Msk (0x20UL) /*!< DLR_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_PRP_INT_Pos (6UL) /*!< PRP_INT (Bit 6) */ + #define R_ETHSW_INT_STAT_ACK_PRP_INT_Msk (0x40UL) /*!< PRP_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_HUB_INT_Pos (7UL) /*!< HUB_INT (Bit 7) */ + #define R_ETHSW_INT_STAT_ACK_HUB_INT_Msk (0x80UL) /*!< HUB_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_LINK_Pos (8UL) /*!< IRQ_LINK (Bit 8) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_LINK_Msk (0x700UL) /*!< IRQ_LINK (Bitfield-Mask: 0x07) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_MAC_EEE_Pos (16UL) /*!< IRQ_MAC_EEE (Bit 16) */ + #define R_ETHSW_INT_STAT_ACK_IRQ_MAC_EEE_Msk (0x70000UL) /*!< IRQ_MAC_EEE (Bitfield-Mask: 0x07) */ + #define R_ETHSW_INT_STAT_ACK_EFP_INT_Pos (27UL) /*!< EFP_INT (Bit 27) */ + #define R_ETHSW_INT_STAT_ACK_EFP_INT_Msk (0x8000000UL) /*!< EFP_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_SRCFLT_WD_INT_Pos (28UL) /*!< SRCFLT_WD_INT (Bit 28) */ + #define R_ETHSW_INT_STAT_ACK_SRCFLT_WD_INT_Msk (0x10000000UL) /*!< SRCFLT_WD_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_TSM_INT_Pos (29UL) /*!< TSM_INT (Bit 29) */ + #define R_ETHSW_INT_STAT_ACK_TSM_INT_Msk (0x20000000UL) /*!< TSM_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_TDMA_INT_Pos (30UL) /*!< TDMA_INT (Bit 30) */ + #define R_ETHSW_INT_STAT_ACK_TDMA_INT_Msk (0x40000000UL) /*!< TDMA_INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_INT_STAT_ACK_PATTERN_INT_Pos (31UL) /*!< PATTERN_INT (Bit 31) */ + #define R_ETHSW_INT_STAT_ACK_PATTERN_INT_Msk (0x80000000UL) /*!< PATTERN_INT (Bitfield-Mask: 0x01) */ +/* ====================================================== ATIME_CTRL0 ====================================================== */ + #define R_ETHSW_ATIME_CTRL0_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ETHSW_ATIME_CTRL0_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_ONE_SHOT_Pos (1UL) /*!< ONE_SHOT (Bit 1) */ + #define R_ETHSW_ATIME_CTRL0_ONE_SHOT_Msk (0x2UL) /*!< ONE_SHOT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_EVT_OFFSET_ENA_Pos (2UL) /*!< EVT_OFFSET_ENA (Bit 2) */ + #define R_ETHSW_ATIME_CTRL0_EVT_OFFSET_ENA_Msk (0x4UL) /*!< EVT_OFFSET_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_ENA_Pos (4UL) /*!< EVT_PERIOD_ENA (Bit 4) */ + #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_ENA_Msk (0x10UL) /*!< EVT_PERIOD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_RST_Pos (5UL) /*!< EVT_PERIOD_RST (Bit 5) */ + #define R_ETHSW_ATIME_CTRL0_EVT_PERIOD_RST_Msk (0x20UL) /*!< EVT_PERIOD_RST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_RESTART_Pos (9UL) /*!< RESTART (Bit 9) */ + #define R_ETHSW_ATIME_CTRL0_RESTART_Msk (0x200UL) /*!< RESTART (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_CAPTURE_Pos (11UL) /*!< CAPTURE (Bit 11) */ + #define R_ETHSW_ATIME_CTRL0_CAPTURE_Msk (0x800UL) /*!< CAPTURE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL0_CAPTURE_ALL_Pos (12UL) /*!< CAPTURE_ALL (Bit 12) */ + #define R_ETHSW_ATIME_CTRL0_CAPTURE_ALL_Msk (0x1000UL) /*!< CAPTURE_ALL (Bitfield-Mask: 0x01) */ +/* ====================================================== ATIME_CTRL1 ====================================================== */ + #define R_ETHSW_ATIME_CTRL1_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ETHSW_ATIME_CTRL1_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_ONE_SHOT_Pos (1UL) /*!< ONE_SHOT (Bit 1) */ + #define R_ETHSW_ATIME_CTRL1_ONE_SHOT_Msk (0x2UL) /*!< ONE_SHOT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_EVT_OFFSET_ENA_Pos (2UL) /*!< EVT_OFFSET_ENA (Bit 2) */ + #define R_ETHSW_ATIME_CTRL1_EVT_OFFSET_ENA_Msk (0x4UL) /*!< EVT_OFFSET_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_ENA_Pos (4UL) /*!< EVT_PERIOD_ENA (Bit 4) */ + #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_ENA_Msk (0x10UL) /*!< EVT_PERIOD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_RST_Pos (5UL) /*!< EVT_PERIOD_RST (Bit 5) */ + #define R_ETHSW_ATIME_CTRL1_EVT_PERIOD_RST_Msk (0x20UL) /*!< EVT_PERIOD_RST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_RESTART_Pos (9UL) /*!< RESTART (Bit 9) */ + #define R_ETHSW_ATIME_CTRL1_RESTART_Msk (0x200UL) /*!< RESTART (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_CAPTURE_Pos (11UL) /*!< CAPTURE (Bit 11) */ + #define R_ETHSW_ATIME_CTRL1_CAPTURE_Msk (0x800UL) /*!< CAPTURE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ATIME_CTRL1_CAPTURE_ALL_Pos (12UL) /*!< CAPTURE_ALL (Bit 12) */ + #define R_ETHSW_ATIME_CTRL1_CAPTURE_ALL_Msk (0x1000UL) /*!< CAPTURE_ALL (Bitfield-Mask: 0x01) */ +/* ======================================================== ATIME0 ========================================================= */ + #define R_ETHSW_ATIME0_TIMER_VAL_Pos (0UL) /*!< TIMER_VAL (Bit 0) */ + #define R_ETHSW_ATIME0_TIMER_VAL_Msk (0xffffffffUL) /*!< TIMER_VAL (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ATIME1 ========================================================= */ + #define R_ETHSW_ATIME1_TIMER_VAL_Pos (0UL) /*!< TIMER_VAL (Bit 0) */ + #define R_ETHSW_ATIME1_TIMER_VAL_Msk (0xffffffffUL) /*!< TIMER_VAL (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ATIME_OFFSET0 ===================================================== */ + #define R_ETHSW_ATIME_OFFSET0_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_ETHSW_ATIME_OFFSET0_OFFSET_Msk (0xffffffffUL) /*!< OFFSET (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ATIME_OFFSET1 ===================================================== */ + #define R_ETHSW_ATIME_OFFSET1_OFFSET_Pos (0UL) /*!< OFFSET (Bit 0) */ + #define R_ETHSW_ATIME_OFFSET1_OFFSET_Msk (0xffffffffUL) /*!< OFFSET (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ATIME_EVT_PERIOD0 =================================================== */ + #define R_ETHSW_ATIME_EVT_PERIOD0_PERIOD_Pos (0UL) /*!< PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_EVT_PERIOD0_PERIOD_Msk (0xffffffffUL) /*!< PERIOD (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ATIME_EVT_PERIOD1 =================================================== */ + #define R_ETHSW_ATIME_EVT_PERIOD1_PERIOD_Pos (0UL) /*!< PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_EVT_PERIOD1_PERIOD_Msk (0xffffffffUL) /*!< PERIOD (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ATIME_CORR0 ====================================================== */ + #define R_ETHSW_ATIME_CORR0_CORR_PERIOD_Pos (0UL) /*!< CORR_PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_CORR0_CORR_PERIOD_Msk (0x7fffffffUL) /*!< CORR_PERIOD (Bitfield-Mask: 0x7fffffff) */ +/* ====================================================== ATIME_CORR1 ====================================================== */ + #define R_ETHSW_ATIME_CORR1_CORR_PERIOD_Pos (0UL) /*!< CORR_PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_CORR1_CORR_PERIOD_Msk (0x7fffffffUL) /*!< CORR_PERIOD (Bitfield-Mask: 0x7fffffff) */ +/* ====================================================== ATIME_INC0 ======================================================= */ + #define R_ETHSW_ATIME_INC0_CLK_PERIOD_Pos (0UL) /*!< CLK_PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_INC0_CLK_PERIOD_Msk (0x7fUL) /*!< CLK_PERIOD (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_ATIME_INC0_CORR_INC_Pos (8UL) /*!< CORR_INC (Bit 8) */ + #define R_ETHSW_ATIME_INC0_CORR_INC_Msk (0x7f00UL) /*!< CORR_INC (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Pos (16UL) /*!< OFFS_CORR_INC (Bit 16) */ + #define R_ETHSW_ATIME_INC0_OFFS_CORR_INC_Msk (0x7f0000UL) /*!< OFFS_CORR_INC (Bitfield-Mask: 0x7f) */ +/* ====================================================== ATIME_INC1 ======================================================= */ + #define R_ETHSW_ATIME_INC1_CLK_PERIOD_Pos (0UL) /*!< CLK_PERIOD (Bit 0) */ + #define R_ETHSW_ATIME_INC1_CLK_PERIOD_Msk (0x7fUL) /*!< CLK_PERIOD (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_ATIME_INC1_CORR_INC_Pos (8UL) /*!< CORR_INC (Bit 8) */ + #define R_ETHSW_ATIME_INC1_CORR_INC_Msk (0x7f00UL) /*!< CORR_INC (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Pos (16UL) /*!< OFFS_CORR_INC (Bit 16) */ + #define R_ETHSW_ATIME_INC1_OFFS_CORR_INC_Msk (0x7f0000UL) /*!< OFFS_CORR_INC (Bitfield-Mask: 0x7f) */ +/* ====================================================== ATIME_SEC0 ======================================================= */ + #define R_ETHSW_ATIME_SEC0_SEC_TIME_Pos (0UL) /*!< SEC_TIME (Bit 0) */ + #define R_ETHSW_ATIME_SEC0_SEC_TIME_Msk (0xffffffffUL) /*!< SEC_TIME (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== ATIME_SEC1 ======================================================= */ + #define R_ETHSW_ATIME_SEC1_SEC_TIME_Pos (0UL) /*!< SEC_TIME (Bit 0) */ + #define R_ETHSW_ATIME_SEC1_SEC_TIME_Msk (0xffffffffUL) /*!< SEC_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ATIME_OFFS_CORR0 ==================================================== */ + #define R_ETHSW_ATIME_OFFS_CORR0_OFFS_CORR_CNT_Pos (0UL) /*!< OFFS_CORR_CNT (Bit 0) */ + #define R_ETHSW_ATIME_OFFS_CORR0_OFFS_CORR_CNT_Msk (0xffffffffUL) /*!< OFFS_CORR_CNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ATIME_OFFS_CORR1 ==================================================== */ + #define R_ETHSW_ATIME_OFFS_CORR1_OFFS_CORR_CNT_Pos (0UL) /*!< OFFS_CORR_CNT (Bit 0) */ + #define R_ETHSW_ATIME_OFFS_CORR1_OFFS_CORR_CNT_Msk (0xffffffffUL) /*!< OFFS_CORR_CNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== MDIO_CFG_STATUS ==================================================== */ + #define R_ETHSW_MDIO_CFG_STATUS_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_ETHSW_MDIO_CFG_STATUS_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MDIO_CFG_STATUS_READERR_Pos (1UL) /*!< READERR (Bit 1) */ + #define R_ETHSW_MDIO_CFG_STATUS_READERR_Msk (0x2UL) /*!< READERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MDIO_CFG_STATUS_HOLD_Pos (2UL) /*!< HOLD (Bit 2) */ + #define R_ETHSW_MDIO_CFG_STATUS_HOLD_Msk (0x1cUL) /*!< HOLD (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MDIO_CFG_STATUS_DISPREAM_Pos (5UL) /*!< DISPREAM (Bit 5) */ + #define R_ETHSW_MDIO_CFG_STATUS_DISPREAM_Msk (0x20UL) /*!< DISPREAM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MDIO_CFG_STATUS_CLKDIV_Pos (7UL) /*!< CLKDIV (Bit 7) */ + #define R_ETHSW_MDIO_CFG_STATUS_CLKDIV_Msk (0xff80UL) /*!< CLKDIV (Bitfield-Mask: 0x1ff) */ +/* ===================================================== MDIO_COMMAND ====================================================== */ + #define R_ETHSW_MDIO_COMMAND_REGADDR_Pos (0UL) /*!< REGADDR (Bit 0) */ + #define R_ETHSW_MDIO_COMMAND_REGADDR_Msk (0x1fUL) /*!< REGADDR (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_MDIO_COMMAND_PHYADDR_Pos (5UL) /*!< PHYADDR (Bit 5) */ + #define R_ETHSW_MDIO_COMMAND_PHYADDR_Msk (0x3e0UL) /*!< PHYADDR (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_MDIO_COMMAND_TRANINIT_Pos (15UL) /*!< TRANINIT (Bit 15) */ + #define R_ETHSW_MDIO_COMMAND_TRANINIT_Msk (0x8000UL) /*!< TRANINIT (Bitfield-Mask: 0x01) */ +/* ======================================================= MDIO_DATA ======================================================= */ + #define R_ETHSW_MDIO_DATA_MDIO_DATA_Pos (0UL) /*!< MDIO_DATA (Bit 0) */ + #define R_ETHSW_MDIO_DATA_MDIO_DATA_Msk (0xffffUL) /*!< MDIO_DATA (Bitfield-Mask: 0xffff) */ +/* ======================================================== REV_P0 ========================================================= */ + #define R_ETHSW_REV_P0_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ETHSW_REV_P0_REV_Msk (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== REV_P1 ========================================================= */ + #define R_ETHSW_REV_P1_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ETHSW_REV_P1_REV_Msk (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== REV_P2 ========================================================= */ + #define R_ETHSW_REV_P2_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ETHSW_REV_P2_REV_Msk (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== REV_P3 ========================================================= */ + #define R_ETHSW_REV_P3_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ETHSW_REV_P3_REV_Msk (0xffffffffUL) /*!< REV (Bitfield-Mask: 0xffffffff) */ +/* =================================================== COMMAND_CONFIG_P0 =================================================== */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_ENA_Pos (0UL) /*!< TX_ENA (Bit 0) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_ENA_Msk (0x1UL) /*!< TX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_RX_ENA_Pos (1UL) /*!< RX_ENA (Bit 1) */ + #define R_ETHSW_COMMAND_CONFIG_P0_RX_ENA_Msk (0x2UL) /*!< RX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TDMA_PREBUF_DIS_Pos (2UL) /*!< TDMA_PREBUF_DIS (Bit 2) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TDMA_PREBUF_DIS_Msk (0x4UL) /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_ETH_SPEED_Pos (3UL) /*!< ETH_SPEED (Bit 3) */ + #define R_ETHSW_COMMAND_CONFIG_P0_ETH_SPEED_Msk (0x8UL) /*!< ETH_SPEED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PROMIS_EN_Pos (4UL) /*!< PROMIS_EN (Bit 4) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PROMIS_EN_Msk (0x10UL) /*!< PROMIS_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAD_EN_Pos (5UL) /*!< PAD_EN (Bit 5) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAD_EN_Msk (0x20UL) /*!< PAD_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_FWD_Pos (7UL) /*!< PAUSE_FWD (Bit 7) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_FWD_Msk (0x80UL) /*!< PAUSE_FWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_IGNORE_Pos (8UL) /*!< PAUSE_IGNORE (Bit 8) */ + #define R_ETHSW_COMMAND_CONFIG_P0_PAUSE_IGNORE_Msk (0x100UL) /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_ADDR_INS_Pos (9UL) /*!< TX_ADDR_INS (Bit 9) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_ADDR_INS_Msk (0x200UL) /*!< TX_ADDR_INS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_HD_ENA_Pos (10UL) /*!< HD_ENA (Bit 10) */ + #define R_ETHSW_COMMAND_CONFIG_P0_HD_ENA_Msk (0x400UL) /*!< HD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_CRC_APPEND_Pos (11UL) /*!< TX_CRC_APPEND (Bit 11) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_CRC_APPEND_Msk (0x800UL) /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_SW_RESET_Pos (13UL) /*!< SW_RESET (Bit 13) */ + #define R_ETHSW_COMMAND_CONFIG_P0_SW_RESET_Msk (0x2000UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_CNTL_FRM_ENA_Pos (23UL) /*!< CNTL_FRM_ENA (Bit 23) */ + #define R_ETHSW_COMMAND_CONFIG_P0_CNTL_FRM_ENA_Msk (0x800000UL) /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_NO_LGTH_CHK_Pos (24UL) /*!< NO_LGTH_CHK (Bit 24) */ + #define R_ETHSW_COMMAND_CONFIG_P0_NO_LGTH_CHK_Msk (0x1000000UL) /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_ENA_10_Pos (25UL) /*!< ENA_10 (Bit 25) */ + #define R_ETHSW_COMMAND_CONFIG_P0_ENA_10_Msk (0x2000000UL) /*!< ENA_10 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Pos (26UL) /*!< EFPI_SELECT (Bit 26) */ + #define R_ETHSW_COMMAND_CONFIG_P0_EFPI_SELECT_Msk (0x4000000UL) /*!< EFPI_SELECT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_TRUNCATE_Pos (27UL) /*!< TX_TRUNCATE (Bit 27) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TX_TRUNCATE_Msk (0x8000000UL) /*!< TX_TRUNCATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TIMER_SEL_Pos (30UL) /*!< TIMER_SEL (Bit 30) */ + #define R_ETHSW_COMMAND_CONFIG_P0_TIMER_SEL_Msk (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ +/* =================================================== COMMAND_CONFIG_P1 =================================================== */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_ENA_Pos (0UL) /*!< TX_ENA (Bit 0) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_ENA_Msk (0x1UL) /*!< TX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_RX_ENA_Pos (1UL) /*!< RX_ENA (Bit 1) */ + #define R_ETHSW_COMMAND_CONFIG_P1_RX_ENA_Msk (0x2UL) /*!< RX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TDMA_PREBUF_DIS_Pos (2UL) /*!< TDMA_PREBUF_DIS (Bit 2) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TDMA_PREBUF_DIS_Msk (0x4UL) /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_ETH_SPEED_Pos (3UL) /*!< ETH_SPEED (Bit 3) */ + #define R_ETHSW_COMMAND_CONFIG_P1_ETH_SPEED_Msk (0x8UL) /*!< ETH_SPEED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PROMIS_EN_Pos (4UL) /*!< PROMIS_EN (Bit 4) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PROMIS_EN_Msk (0x10UL) /*!< PROMIS_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAD_EN_Pos (5UL) /*!< PAD_EN (Bit 5) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAD_EN_Msk (0x20UL) /*!< PAD_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_FWD_Pos (7UL) /*!< PAUSE_FWD (Bit 7) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_FWD_Msk (0x80UL) /*!< PAUSE_FWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_IGNORE_Pos (8UL) /*!< PAUSE_IGNORE (Bit 8) */ + #define R_ETHSW_COMMAND_CONFIG_P1_PAUSE_IGNORE_Msk (0x100UL) /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_ADDR_INS_Pos (9UL) /*!< TX_ADDR_INS (Bit 9) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_ADDR_INS_Msk (0x200UL) /*!< TX_ADDR_INS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_HD_ENA_Pos (10UL) /*!< HD_ENA (Bit 10) */ + #define R_ETHSW_COMMAND_CONFIG_P1_HD_ENA_Msk (0x400UL) /*!< HD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_CRC_APPEND_Pos (11UL) /*!< TX_CRC_APPEND (Bit 11) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_CRC_APPEND_Msk (0x800UL) /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_SW_RESET_Pos (13UL) /*!< SW_RESET (Bit 13) */ + #define R_ETHSW_COMMAND_CONFIG_P1_SW_RESET_Msk (0x2000UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_CNTL_FRM_ENA_Pos (23UL) /*!< CNTL_FRM_ENA (Bit 23) */ + #define R_ETHSW_COMMAND_CONFIG_P1_CNTL_FRM_ENA_Msk (0x800000UL) /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_NO_LGTH_CHK_Pos (24UL) /*!< NO_LGTH_CHK (Bit 24) */ + #define R_ETHSW_COMMAND_CONFIG_P1_NO_LGTH_CHK_Msk (0x1000000UL) /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_ENA_10_Pos (25UL) /*!< ENA_10 (Bit 25) */ + #define R_ETHSW_COMMAND_CONFIG_P1_ENA_10_Msk (0x2000000UL) /*!< ENA_10 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_EFPI_SELECT_Pos (26UL) /*!< EFPI_SELECT (Bit 26) */ + #define R_ETHSW_COMMAND_CONFIG_P1_EFPI_SELECT_Msk (0x4000000UL) /*!< EFPI_SELECT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_TRUNCATE_Pos (27UL) /*!< TX_TRUNCATE (Bit 27) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TX_TRUNCATE_Msk (0x8000000UL) /*!< TX_TRUNCATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TIMER_SEL_Pos (30UL) /*!< TIMER_SEL (Bit 30) */ + #define R_ETHSW_COMMAND_CONFIG_P1_TIMER_SEL_Msk (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ +/* =================================================== COMMAND_CONFIG_P2 =================================================== */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_ENA_Pos (0UL) /*!< TX_ENA (Bit 0) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_ENA_Msk (0x1UL) /*!< TX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_RX_ENA_Pos (1UL) /*!< RX_ENA (Bit 1) */ + #define R_ETHSW_COMMAND_CONFIG_P2_RX_ENA_Msk (0x2UL) /*!< RX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TDMA_PREBUF_DIS_Pos (2UL) /*!< TDMA_PREBUF_DIS (Bit 2) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TDMA_PREBUF_DIS_Msk (0x4UL) /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_ETH_SPEED_Pos (3UL) /*!< ETH_SPEED (Bit 3) */ + #define R_ETHSW_COMMAND_CONFIG_P2_ETH_SPEED_Msk (0x8UL) /*!< ETH_SPEED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PROMIS_EN_Pos (4UL) /*!< PROMIS_EN (Bit 4) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PROMIS_EN_Msk (0x10UL) /*!< PROMIS_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAD_EN_Pos (5UL) /*!< PAD_EN (Bit 5) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAD_EN_Msk (0x20UL) /*!< PAD_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_FWD_Pos (7UL) /*!< PAUSE_FWD (Bit 7) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_FWD_Msk (0x80UL) /*!< PAUSE_FWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_IGNORE_Pos (8UL) /*!< PAUSE_IGNORE (Bit 8) */ + #define R_ETHSW_COMMAND_CONFIG_P2_PAUSE_IGNORE_Msk (0x100UL) /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_ADDR_INS_Pos (9UL) /*!< TX_ADDR_INS (Bit 9) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_ADDR_INS_Msk (0x200UL) /*!< TX_ADDR_INS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_HD_ENA_Pos (10UL) /*!< HD_ENA (Bit 10) */ + #define R_ETHSW_COMMAND_CONFIG_P2_HD_ENA_Msk (0x400UL) /*!< HD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_CRC_APPEND_Pos (11UL) /*!< TX_CRC_APPEND (Bit 11) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_CRC_APPEND_Msk (0x800UL) /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_SW_RESET_Pos (13UL) /*!< SW_RESET (Bit 13) */ + #define R_ETHSW_COMMAND_CONFIG_P2_SW_RESET_Msk (0x2000UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_CNTL_FRM_ENA_Pos (23UL) /*!< CNTL_FRM_ENA (Bit 23) */ + #define R_ETHSW_COMMAND_CONFIG_P2_CNTL_FRM_ENA_Msk (0x800000UL) /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_NO_LGTH_CHK_Pos (24UL) /*!< NO_LGTH_CHK (Bit 24) */ + #define R_ETHSW_COMMAND_CONFIG_P2_NO_LGTH_CHK_Msk (0x1000000UL) /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_ENA_10_Pos (25UL) /*!< ENA_10 (Bit 25) */ + #define R_ETHSW_COMMAND_CONFIG_P2_ENA_10_Msk (0x2000000UL) /*!< ENA_10 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_EFPI_SELECT_Pos (26UL) /*!< EFPI_SELECT (Bit 26) */ + #define R_ETHSW_COMMAND_CONFIG_P2_EFPI_SELECT_Msk (0x4000000UL) /*!< EFPI_SELECT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_TRUNCATE_Pos (27UL) /*!< TX_TRUNCATE (Bit 27) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TX_TRUNCATE_Msk (0x8000000UL) /*!< TX_TRUNCATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TIMER_SEL_Pos (30UL) /*!< TIMER_SEL (Bit 30) */ + #define R_ETHSW_COMMAND_CONFIG_P2_TIMER_SEL_Msk (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ +/* =================================================== COMMAND_CONFIG_P3 =================================================== */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_ENA_Pos (0UL) /*!< TX_ENA (Bit 0) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_ENA_Msk (0x1UL) /*!< TX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_RX_ENA_Pos (1UL) /*!< RX_ENA (Bit 1) */ + #define R_ETHSW_COMMAND_CONFIG_P3_RX_ENA_Msk (0x2UL) /*!< RX_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TDMA_PREBUF_DIS_Pos (2UL) /*!< TDMA_PREBUF_DIS (Bit 2) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TDMA_PREBUF_DIS_Msk (0x4UL) /*!< TDMA_PREBUF_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_ETH_SPEED_Pos (3UL) /*!< ETH_SPEED (Bit 3) */ + #define R_ETHSW_COMMAND_CONFIG_P3_ETH_SPEED_Msk (0x8UL) /*!< ETH_SPEED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PROMIS_EN_Pos (4UL) /*!< PROMIS_EN (Bit 4) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PROMIS_EN_Msk (0x10UL) /*!< PROMIS_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAD_EN_Pos (5UL) /*!< PAD_EN (Bit 5) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAD_EN_Msk (0x20UL) /*!< PAD_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_FWD_Pos (7UL) /*!< PAUSE_FWD (Bit 7) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_FWD_Msk (0x80UL) /*!< PAUSE_FWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_IGNORE_Pos (8UL) /*!< PAUSE_IGNORE (Bit 8) */ + #define R_ETHSW_COMMAND_CONFIG_P3_PAUSE_IGNORE_Msk (0x100UL) /*!< PAUSE_IGNORE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_ADDR_INS_Pos (9UL) /*!< TX_ADDR_INS (Bit 9) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_ADDR_INS_Msk (0x200UL) /*!< TX_ADDR_INS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_HD_ENA_Pos (10UL) /*!< HD_ENA (Bit 10) */ + #define R_ETHSW_COMMAND_CONFIG_P3_HD_ENA_Msk (0x400UL) /*!< HD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_CRC_APPEND_Pos (11UL) /*!< TX_CRC_APPEND (Bit 11) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_CRC_APPEND_Msk (0x800UL) /*!< TX_CRC_APPEND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_SW_RESET_Pos (13UL) /*!< SW_RESET (Bit 13) */ + #define R_ETHSW_COMMAND_CONFIG_P3_SW_RESET_Msk (0x2000UL) /*!< SW_RESET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_CNTL_FRM_ENA_Pos (23UL) /*!< CNTL_FRM_ENA (Bit 23) */ + #define R_ETHSW_COMMAND_CONFIG_P3_CNTL_FRM_ENA_Msk (0x800000UL) /*!< CNTL_FRM_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_NO_LGTH_CHK_Pos (24UL) /*!< NO_LGTH_CHK (Bit 24) */ + #define R_ETHSW_COMMAND_CONFIG_P3_NO_LGTH_CHK_Msk (0x1000000UL) /*!< NO_LGTH_CHK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_ENA_10_Pos (25UL) /*!< ENA_10 (Bit 25) */ + #define R_ETHSW_COMMAND_CONFIG_P3_ENA_10_Msk (0x2000000UL) /*!< ENA_10 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_EFPI_SELECT_Pos (26UL) /*!< EFPI_SELECT (Bit 26) */ + #define R_ETHSW_COMMAND_CONFIG_P3_EFPI_SELECT_Msk (0x4000000UL) /*!< EFPI_SELECT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_TRUNCATE_Pos (27UL) /*!< TX_TRUNCATE (Bit 27) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TX_TRUNCATE_Msk (0x8000000UL) /*!< TX_TRUNCATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TIMER_SEL_Pos (30UL) /*!< TIMER_SEL (Bit 30) */ + #define R_ETHSW_COMMAND_CONFIG_P3_TIMER_SEL_Msk (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ +/* ===================================================== MAC_ADDR_0_P0 ===================================================== */ + #define R_ETHSW_MAC_ADDR_0_P0_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_0_P0_MAC_ADDR_Msk (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MAC_ADDR_0_P1 ===================================================== */ + #define R_ETHSW_MAC_ADDR_0_P1_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_0_P1_MAC_ADDR_Msk (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MAC_ADDR_0_P2 ===================================================== */ + #define R_ETHSW_MAC_ADDR_0_P2_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_0_P2_MAC_ADDR_Msk (0xffffffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== MAC_ADDR_1_P0 ===================================================== */ + #define R_ETHSW_MAC_ADDR_1_P0_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_1_P0_MAC_ADDR_Msk (0xffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== MAC_ADDR_1_P1 ===================================================== */ + #define R_ETHSW_MAC_ADDR_1_P1_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_1_P1_MAC_ADDR_Msk (0xffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== MAC_ADDR_1_P2 ===================================================== */ + #define R_ETHSW_MAC_ADDR_1_P2_MAC_ADDR_Pos (0UL) /*!< MAC_ADDR (Bit 0) */ + #define R_ETHSW_MAC_ADDR_1_P2_MAC_ADDR_Msk (0xffffUL) /*!< MAC_ADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== FRM_LENGTH_P0 ===================================================== */ + #define R_ETHSW_FRM_LENGTH_P0_FRM_LENGTH_Pos (0UL) /*!< FRM_LENGTH (Bit 0) */ + #define R_ETHSW_FRM_LENGTH_P0_FRM_LENGTH_Msk (0x3fffUL) /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff) */ +/* ===================================================== FRM_LENGTH_P1 ===================================================== */ + #define R_ETHSW_FRM_LENGTH_P1_FRM_LENGTH_Pos (0UL) /*!< FRM_LENGTH (Bit 0) */ + #define R_ETHSW_FRM_LENGTH_P1_FRM_LENGTH_Msk (0x3fffUL) /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff) */ +/* ===================================================== FRM_LENGTH_P2 ===================================================== */ + #define R_ETHSW_FRM_LENGTH_P2_FRM_LENGTH_Pos (0UL) /*!< FRM_LENGTH (Bit 0) */ + #define R_ETHSW_FRM_LENGTH_P2_FRM_LENGTH_Msk (0x3fffUL) /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff) */ +/* ===================================================== FRM_LENGTH_P3 ===================================================== */ + #define R_ETHSW_FRM_LENGTH_P3_FRM_LENGTH_Pos (0UL) /*!< FRM_LENGTH (Bit 0) */ + #define R_ETHSW_FRM_LENGTH_P3_FRM_LENGTH_Msk (0x3fffUL) /*!< FRM_LENGTH (Bitfield-Mask: 0x3fff) */ +/* ==================================================== PAUSE_QUANT_P0 ===================================================== */ + #define R_ETHSW_PAUSE_QUANT_P0_PAUSE_QUANT_Pos (0UL) /*!< PAUSE_QUANT (Bit 0) */ + #define R_ETHSW_PAUSE_QUANT_P0_PAUSE_QUANT_Msk (0xffffUL) /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff) */ +/* ==================================================== PAUSE_QUANT_P1 ===================================================== */ + #define R_ETHSW_PAUSE_QUANT_P1_PAUSE_QUANT_Pos (0UL) /*!< PAUSE_QUANT (Bit 0) */ + #define R_ETHSW_PAUSE_QUANT_P1_PAUSE_QUANT_Msk (0xffffUL) /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff) */ +/* ==================================================== PAUSE_QUANT_P2 ===================================================== */ + #define R_ETHSW_PAUSE_QUANT_P2_PAUSE_QUANT_Pos (0UL) /*!< PAUSE_QUANT (Bit 0) */ + #define R_ETHSW_PAUSE_QUANT_P2_PAUSE_QUANT_Msk (0xffffUL) /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff) */ +/* ==================================================== PAUSE_QUANT_P3 ===================================================== */ + #define R_ETHSW_PAUSE_QUANT_P3_PAUSE_QUANT_Pos (0UL) /*!< PAUSE_QUANT (Bit 0) */ + #define R_ETHSW_PAUSE_QUANT_P3_PAUSE_QUANT_Msk (0xffffUL) /*!< PAUSE_QUANT (Bitfield-Mask: 0xffff) */ +/* =================================================== MAC_LINK_QTRIG_P0 =================================================== */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_QUEUE_MASK_Pos (16UL) /*!< QUEUE_MASK (Bit 16) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_QUEUE_MASK_Msk (0xff0000UL) /*!< QUEUE_MASK (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_TRIGGERED_Pos (28UL) /*!< TRIGGERED (Bit 28) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_TRIGGERED_Msk (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_DLR_MODE_Pos (29UL) /*!< DLR_MODE (Bit 29) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_DLR_MODE_Msk (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_MODE_Pos (30UL) /*!< MODE (Bit 30) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_MODE_Msk (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ + #define R_ETHSW_MAC_LINK_QTRIG_P0_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== MAC_LINK_QTRIG_P1 =================================================== */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_QUEUE_MASK_Pos (16UL) /*!< QUEUE_MASK (Bit 16) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_QUEUE_MASK_Msk (0xff0000UL) /*!< QUEUE_MASK (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_TRIGGERED_Pos (28UL) /*!< TRIGGERED (Bit 28) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_TRIGGERED_Msk (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_DLR_MODE_Pos (29UL) /*!< DLR_MODE (Bit 29) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_DLR_MODE_Msk (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_MODE_Pos (30UL) /*!< MODE (Bit 30) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_MODE_Msk (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ + #define R_ETHSW_MAC_LINK_QTRIG_P1_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* =================================================== MAC_LINK_QTRIG_P2 =================================================== */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_QUEUE_MASK_Pos (16UL) /*!< QUEUE_MASK (Bit 16) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_QUEUE_MASK_Msk (0xff0000UL) /*!< QUEUE_MASK (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_TRIGGERED_Pos (28UL) /*!< TRIGGERED (Bit 28) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_TRIGGERED_Msk (0x10000000UL) /*!< TRIGGERED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_DLR_MODE_Pos (29UL) /*!< DLR_MODE (Bit 29) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_DLR_MODE_Msk (0x20000000UL) /*!< DLR_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_MODE_Pos (30UL) /*!< MODE (Bit 30) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_MODE_Msk (0x40000000UL) /*!< MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_ENABLE_Pos (31UL) /*!< ENABLE (Bit 31) */ + #define R_ETHSW_MAC_LINK_QTRIG_P2_ENABLE_Msk (0x80000000UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ================================================= PTPCLOCKIDENTITY1_P0 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY0_Pos (0UL) /*!< CLK_IDENTITY0 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY0_Msk (0xffUL) /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY1_Pos (8UL) /*!< CLK_IDENTITY1 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY1_Msk (0xff00UL) /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY2_Pos (16UL) /*!< CLK_IDENTITY2 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY2_Msk (0xff0000UL) /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY3_Pos (24UL) /*!< CLK_IDENTITY3 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P0_CLK_IDENTITY3_Msk (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff) */ +/* ================================================= PTPCLOCKIDENTITY1_P1 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY0_Pos (0UL) /*!< CLK_IDENTITY0 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY0_Msk (0xffUL) /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY1_Pos (8UL) /*!< CLK_IDENTITY1 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY1_Msk (0xff00UL) /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY2_Pos (16UL) /*!< CLK_IDENTITY2 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY2_Msk (0xff0000UL) /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY3_Pos (24UL) /*!< CLK_IDENTITY3 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P1_CLK_IDENTITY3_Msk (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff) */ +/* ================================================= PTPCLOCKIDENTITY1_P2 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY0_Pos (0UL) /*!< CLK_IDENTITY0 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY0_Msk (0xffUL) /*!< CLK_IDENTITY0 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY1_Pos (8UL) /*!< CLK_IDENTITY1 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY1_Msk (0xff00UL) /*!< CLK_IDENTITY1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY2_Pos (16UL) /*!< CLK_IDENTITY2 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY2_Msk (0xff0000UL) /*!< CLK_IDENTITY2 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY3_Pos (24UL) /*!< CLK_IDENTITY3 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY1_P2_CLK_IDENTITY3_Msk (0xff000000UL) /*!< CLK_IDENTITY3 (Bitfield-Mask: 0xff) */ +/* ================================================= PTPCLOCKIDENTITY2_P0 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY4_Pos (0UL) /*!< CLK_IDENTITY4 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY4_Msk (0xffUL) /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY5_Pos (8UL) /*!< CLK_IDENTITY5 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY5_Msk (0xff00UL) /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY6_Pos (16UL) /*!< CLK_IDENTITY6 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY6_Msk (0xff0000UL) /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY7_Pos (24UL) /*!< CLK_IDENTITY7 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P0_CLK_IDENTITY7_Msk (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff) */ +/* ================================================= PTPCLOCKIDENTITY2_P1 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY4_Pos (0UL) /*!< CLK_IDENTITY4 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY4_Msk (0xffUL) /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY5_Pos (8UL) /*!< CLK_IDENTITY5 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY5_Msk (0xff00UL) /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY6_Pos (16UL) /*!< CLK_IDENTITY6 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY6_Msk (0xff0000UL) /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY7_Pos (24UL) /*!< CLK_IDENTITY7 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P1_CLK_IDENTITY7_Msk (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff) */ +/* ================================================= PTPCLOCKIDENTITY2_P2 ================================================== */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY4_Pos (0UL) /*!< CLK_IDENTITY4 (Bit 0) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY4_Msk (0xffUL) /*!< CLK_IDENTITY4 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY5_Pos (8UL) /*!< CLK_IDENTITY5 (Bit 8) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY5_Msk (0xff00UL) /*!< CLK_IDENTITY5 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY6_Pos (16UL) /*!< CLK_IDENTITY6 (Bit 16) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY6_Msk (0xff0000UL) /*!< CLK_IDENTITY6 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY7_Pos (24UL) /*!< CLK_IDENTITY7 (Bit 24) */ + #define R_ETHSW_PTPCLOCKIDENTITY2_P2_CLK_IDENTITY7_Msk (0xff000000UL) /*!< CLK_IDENTITY7 (Bitfield-Mask: 0xff) */ +/* ================================================== PTPAUTORESPONSE_P0 =================================================== */ + #define R_ETHSW_PTPAUTORESPONSE_P0_ARSP_EN_Pos (0UL) /*!< ARSP_EN (Bit 0) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_ARSP_EN_Msk (0x1UL) /*!< ARSP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_D_TIMER_Pos (1UL) /*!< D_TIMER (Bit 1) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_D_TIMER_Msk (0x2UL) /*!< D_TIMER (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM1_Pos (16UL) /*!< PORTNUM1 (Bit 16) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM1_Msk (0xff0000UL) /*!< PORTNUM1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM0_Pos (24UL) /*!< PORTNUM0 (Bit 24) */ + #define R_ETHSW_PTPAUTORESPONSE_P0_PORTNUM0_Msk (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff) */ +/* ================================================== PTPAUTORESPONSE_P1 =================================================== */ + #define R_ETHSW_PTPAUTORESPONSE_P1_ARSP_EN_Pos (0UL) /*!< ARSP_EN (Bit 0) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_ARSP_EN_Msk (0x1UL) /*!< ARSP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_D_TIMER_Pos (1UL) /*!< D_TIMER (Bit 1) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_D_TIMER_Msk (0x2UL) /*!< D_TIMER (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM1_Pos (16UL) /*!< PORTNUM1 (Bit 16) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM1_Msk (0xff0000UL) /*!< PORTNUM1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM0_Pos (24UL) /*!< PORTNUM0 (Bit 24) */ + #define R_ETHSW_PTPAUTORESPONSE_P1_PORTNUM0_Msk (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff) */ +/* ================================================== PTPAUTORESPONSE_P2 =================================================== */ + #define R_ETHSW_PTPAUTORESPONSE_P2_ARSP_EN_Pos (0UL) /*!< ARSP_EN (Bit 0) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_ARSP_EN_Msk (0x1UL) /*!< ARSP_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_D_TIMER_Pos (1UL) /*!< D_TIMER (Bit 1) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_D_TIMER_Msk (0x2UL) /*!< D_TIMER (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM1_Pos (16UL) /*!< PORTNUM1 (Bit 16) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM1_Msk (0xff0000UL) /*!< PORTNUM1 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM0_Pos (24UL) /*!< PORTNUM0 (Bit 24) */ + #define R_ETHSW_PTPAUTORESPONSE_P2_PORTNUM0_Msk (0xff000000UL) /*!< PORTNUM0 (Bitfield-Mask: 0xff) */ +/* ======================================================= STATUS_P0 ======================================================= */ + #define R_ETHSW_STATUS_P0_PHYSPEED_Pos (0UL) /*!< PHYSPEED (Bit 0) */ + #define R_ETHSW_STATUS_P0_PHYSPEED_Msk (0x3UL) /*!< PHYSPEED (Bitfield-Mask: 0x03) */ + #define R_ETHSW_STATUS_P0_PHYLINK_Pos (2UL) /*!< PHYLINK (Bit 2) */ + #define R_ETHSW_STATUS_P0_PHYLINK_Msk (0x4UL) /*!< PHYLINK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P0_PHYDUPLEX_Pos (3UL) /*!< PHYDUPLEX (Bit 3) */ + #define R_ETHSW_STATUS_P0_PHYDUPLEX_Msk (0x8UL) /*!< PHYDUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P0_TX_UNDFLW_Pos (4UL) /*!< TX_UNDFLW (Bit 4) */ + #define R_ETHSW_STATUS_P0_TX_UNDFLW_Msk (0x10UL) /*!< TX_UNDFLW (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P0_LK_DST_ERR_Pos (5UL) /*!< LK_DST_ERR (Bit 5) */ + #define R_ETHSW_STATUS_P0_LK_DST_ERR_Msk (0x20UL) /*!< LK_DST_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P0_BR_VERIF_ST_Pos (6UL) /*!< BR_VERIF_ST (Bit 6) */ + #define R_ETHSW_STATUS_P0_BR_VERIF_ST_Msk (0x1c0UL) /*!< BR_VERIF_ST (Bitfield-Mask: 0x07) */ +/* ======================================================= STATUS_P1 ======================================================= */ + #define R_ETHSW_STATUS_P1_PHYSPEED_Pos (0UL) /*!< PHYSPEED (Bit 0) */ + #define R_ETHSW_STATUS_P1_PHYSPEED_Msk (0x3UL) /*!< PHYSPEED (Bitfield-Mask: 0x03) */ + #define R_ETHSW_STATUS_P1_PHYLINK_Pos (2UL) /*!< PHYLINK (Bit 2) */ + #define R_ETHSW_STATUS_P1_PHYLINK_Msk (0x4UL) /*!< PHYLINK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P1_PHYDUPLEX_Pos (3UL) /*!< PHYDUPLEX (Bit 3) */ + #define R_ETHSW_STATUS_P1_PHYDUPLEX_Msk (0x8UL) /*!< PHYDUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P1_TX_UNDFLW_Pos (4UL) /*!< TX_UNDFLW (Bit 4) */ + #define R_ETHSW_STATUS_P1_TX_UNDFLW_Msk (0x10UL) /*!< TX_UNDFLW (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P1_LK_DST_ERR_Pos (5UL) /*!< LK_DST_ERR (Bit 5) */ + #define R_ETHSW_STATUS_P1_LK_DST_ERR_Msk (0x20UL) /*!< LK_DST_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P1_BR_VERIF_ST_Pos (6UL) /*!< BR_VERIF_ST (Bit 6) */ + #define R_ETHSW_STATUS_P1_BR_VERIF_ST_Msk (0x1c0UL) /*!< BR_VERIF_ST (Bitfield-Mask: 0x07) */ +/* ======================================================= STATUS_P2 ======================================================= */ + #define R_ETHSW_STATUS_P2_PHYSPEED_Pos (0UL) /*!< PHYSPEED (Bit 0) */ + #define R_ETHSW_STATUS_P2_PHYSPEED_Msk (0x3UL) /*!< PHYSPEED (Bitfield-Mask: 0x03) */ + #define R_ETHSW_STATUS_P2_PHYLINK_Pos (2UL) /*!< PHYLINK (Bit 2) */ + #define R_ETHSW_STATUS_P2_PHYLINK_Msk (0x4UL) /*!< PHYLINK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P2_PHYDUPLEX_Pos (3UL) /*!< PHYDUPLEX (Bit 3) */ + #define R_ETHSW_STATUS_P2_PHYDUPLEX_Msk (0x8UL) /*!< PHYDUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P2_TX_UNDFLW_Pos (4UL) /*!< TX_UNDFLW (Bit 4) */ + #define R_ETHSW_STATUS_P2_TX_UNDFLW_Msk (0x10UL) /*!< TX_UNDFLW (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P2_LK_DST_ERR_Pos (5UL) /*!< LK_DST_ERR (Bit 5) */ + #define R_ETHSW_STATUS_P2_LK_DST_ERR_Msk (0x20UL) /*!< LK_DST_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P2_BR_VERIF_ST_Pos (6UL) /*!< BR_VERIF_ST (Bit 6) */ + #define R_ETHSW_STATUS_P2_BR_VERIF_ST_Msk (0x1c0UL) /*!< BR_VERIF_ST (Bitfield-Mask: 0x07) */ +/* ======================================================= STATUS_P3 ======================================================= */ + #define R_ETHSW_STATUS_P3_PHYSPEED_Pos (0UL) /*!< PHYSPEED (Bit 0) */ + #define R_ETHSW_STATUS_P3_PHYSPEED_Msk (0x3UL) /*!< PHYSPEED (Bitfield-Mask: 0x03) */ + #define R_ETHSW_STATUS_P3_PHYLINK_Pos (2UL) /*!< PHYLINK (Bit 2) */ + #define R_ETHSW_STATUS_P3_PHYLINK_Msk (0x4UL) /*!< PHYLINK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P3_PHYDUPLEX_Pos (3UL) /*!< PHYDUPLEX (Bit 3) */ + #define R_ETHSW_STATUS_P3_PHYDUPLEX_Msk (0x8UL) /*!< PHYDUPLEX (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P3_TX_UNDFLW_Pos (4UL) /*!< TX_UNDFLW (Bit 4) */ + #define R_ETHSW_STATUS_P3_TX_UNDFLW_Msk (0x10UL) /*!< TX_UNDFLW (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P3_LK_DST_ERR_Pos (5UL) /*!< LK_DST_ERR (Bit 5) */ + #define R_ETHSW_STATUS_P3_LK_DST_ERR_Msk (0x20UL) /*!< LK_DST_ERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATUS_P3_BR_VERIF_ST_Pos (6UL) /*!< BR_VERIF_ST (Bit 6) */ + #define R_ETHSW_STATUS_P3_BR_VERIF_ST_Msk (0x1c0UL) /*!< BR_VERIF_ST (Bitfield-Mask: 0x07) */ +/* =================================================== TX_IPG_LENGTH_P0 ==================================================== */ + #define R_ETHSW_TX_IPG_LENGTH_P0_TX_IPG_LENGTH_Pos (0UL) /*!< TX_IPG_LENGTH (Bit 0) */ + #define R_ETHSW_TX_IPG_LENGTH_P0_TX_IPG_LENGTH_Msk (0x1fUL) /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_TX_IPG_LENGTH_P0_MINRTC3GAP_Pos (16UL) /*!< MINRTC3GAP (Bit 16) */ + #define R_ETHSW_TX_IPG_LENGTH_P0_MINRTC3GAP_Msk (0x1f0000UL) /*!< MINRTC3GAP (Bitfield-Mask: 0x1f) */ +/* =================================================== TX_IPG_LENGTH_P1 ==================================================== */ + #define R_ETHSW_TX_IPG_LENGTH_P1_TX_IPG_LENGTH_Pos (0UL) /*!< TX_IPG_LENGTH (Bit 0) */ + #define R_ETHSW_TX_IPG_LENGTH_P1_TX_IPG_LENGTH_Msk (0x1fUL) /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_TX_IPG_LENGTH_P1_MINRTC3GAP_Pos (16UL) /*!< MINRTC3GAP (Bit 16) */ + #define R_ETHSW_TX_IPG_LENGTH_P1_MINRTC3GAP_Msk (0x1f0000UL) /*!< MINRTC3GAP (Bitfield-Mask: 0x1f) */ +/* =================================================== TX_IPG_LENGTH_P2 ==================================================== */ + #define R_ETHSW_TX_IPG_LENGTH_P2_TX_IPG_LENGTH_Pos (0UL) /*!< TX_IPG_LENGTH (Bit 0) */ + #define R_ETHSW_TX_IPG_LENGTH_P2_TX_IPG_LENGTH_Msk (0x1fUL) /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_TX_IPG_LENGTH_P2_MINRTC3GAP_Pos (16UL) /*!< MINRTC3GAP (Bit 16) */ + #define R_ETHSW_TX_IPG_LENGTH_P2_MINRTC3GAP_Msk (0x1f0000UL) /*!< MINRTC3GAP (Bitfield-Mask: 0x1f) */ +/* =================================================== TX_IPG_LENGTH_P3 ==================================================== */ + #define R_ETHSW_TX_IPG_LENGTH_P3_TX_IPG_LENGTH_Pos (0UL) /*!< TX_IPG_LENGTH (Bit 0) */ + #define R_ETHSW_TX_IPG_LENGTH_P3_TX_IPG_LENGTH_Msk (0x1fUL) /*!< TX_IPG_LENGTH (Bitfield-Mask: 0x1f) */ + #define R_ETHSW_TX_IPG_LENGTH_P3_MINRTC3GAP_Pos (16UL) /*!< MINRTC3GAP (Bit 16) */ + #define R_ETHSW_TX_IPG_LENGTH_P3_MINRTC3GAP_Msk (0x1f0000UL) /*!< MINRTC3GAP (Bitfield-Mask: 0x1f) */ +/* ==================================================== EEE_CTL_STAT_P0 ==================================================== */ + #define R_ETHSW_EEE_CTL_STAT_P0_EEE_AUTO_Pos (0UL) /*!< EEE_AUTO (Bit 0) */ + #define R_ETHSW_EEE_CTL_STAT_P0_EEE_AUTO_Msk (0x1UL) /*!< EEE_AUTO (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_LPI_REQ_Pos (1UL) /*!< LPI_REQ (Bit 1) */ + #define R_ETHSW_EEE_CTL_STAT_P0_LPI_REQ_Msk (0x2UL) /*!< LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_LPI_TXHOLD_Pos (2UL) /*!< LPI_TXHOLD (Bit 2) */ + #define R_ETHSW_EEE_CTL_STAT_P0_LPI_TXHOLD_Msk (0x4UL) /*!< LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_REQ_Pos (8UL) /*!< ST_LPI_REQ (Bit 8) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_REQ_Msk (0x100UL) /*!< ST_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_TXHOLD_Pos (9UL) /*!< ST_LPI_TXHOLD (Bit 9) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_TXHOLD_Msk (0x200UL) /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXBUSY_Pos (10UL) /*!< ST_TXBUSY (Bit 10) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXBUSY_Msk (0x400UL) /*!< ST_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXAVAIL_Pos (11UL) /*!< ST_TXAVAIL (Bit 11) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_TXAVAIL_Msk (0x800UL) /*!< ST_TXAVAIL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_IND_Pos (12UL) /*!< ST_LPI_IND (Bit 12) */ + #define R_ETHSW_EEE_CTL_STAT_P0_ST_LPI_IND_Msk (0x1000UL) /*!< ST_LPI_IND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_REQ_Pos (16UL) /*!< STLH_LPI_REQ (Bit 16) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_REQ_Msk (0x10000UL) /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_TXHOLD_Pos (17UL) /*!< STLH_LPI_TXHOLD (Bit 17) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_TXHOLD_Msk (0x20000UL) /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_TXBUSY_Pos (18UL) /*!< STLH_TXBUSY (Bit 18) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_TXBUSY_Msk (0x40000UL) /*!< STLH_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_IND_Pos (20UL) /*!< STLH_LPI_IND (Bit 20) */ + #define R_ETHSW_EEE_CTL_STAT_P0_STLH_LPI_IND_Msk (0x100000UL) /*!< STLH_LPI_IND (Bitfield-Mask: 0x01) */ +/* ==================================================== EEE_CTL_STAT_P1 ==================================================== */ + #define R_ETHSW_EEE_CTL_STAT_P1_EEE_AUTO_Pos (0UL) /*!< EEE_AUTO (Bit 0) */ + #define R_ETHSW_EEE_CTL_STAT_P1_EEE_AUTO_Msk (0x1UL) /*!< EEE_AUTO (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_LPI_REQ_Pos (1UL) /*!< LPI_REQ (Bit 1) */ + #define R_ETHSW_EEE_CTL_STAT_P1_LPI_REQ_Msk (0x2UL) /*!< LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_LPI_TXHOLD_Pos (2UL) /*!< LPI_TXHOLD (Bit 2) */ + #define R_ETHSW_EEE_CTL_STAT_P1_LPI_TXHOLD_Msk (0x4UL) /*!< LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_REQ_Pos (8UL) /*!< ST_LPI_REQ (Bit 8) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_REQ_Msk (0x100UL) /*!< ST_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_TXHOLD_Pos (9UL) /*!< ST_LPI_TXHOLD (Bit 9) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_TXHOLD_Msk (0x200UL) /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXBUSY_Pos (10UL) /*!< ST_TXBUSY (Bit 10) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXBUSY_Msk (0x400UL) /*!< ST_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXAVAIL_Pos (11UL) /*!< ST_TXAVAIL (Bit 11) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_TXAVAIL_Msk (0x800UL) /*!< ST_TXAVAIL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_IND_Pos (12UL) /*!< ST_LPI_IND (Bit 12) */ + #define R_ETHSW_EEE_CTL_STAT_P1_ST_LPI_IND_Msk (0x1000UL) /*!< ST_LPI_IND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_REQ_Pos (16UL) /*!< STLH_LPI_REQ (Bit 16) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_REQ_Msk (0x10000UL) /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_TXHOLD_Pos (17UL) /*!< STLH_LPI_TXHOLD (Bit 17) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_TXHOLD_Msk (0x20000UL) /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_TXBUSY_Pos (18UL) /*!< STLH_TXBUSY (Bit 18) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_TXBUSY_Msk (0x40000UL) /*!< STLH_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_IND_Pos (20UL) /*!< STLH_LPI_IND (Bit 20) */ + #define R_ETHSW_EEE_CTL_STAT_P1_STLH_LPI_IND_Msk (0x100000UL) /*!< STLH_LPI_IND (Bitfield-Mask: 0x01) */ +/* ==================================================== EEE_CTL_STAT_P2 ==================================================== */ + #define R_ETHSW_EEE_CTL_STAT_P2_EEE_AUTO_Pos (0UL) /*!< EEE_AUTO (Bit 0) */ + #define R_ETHSW_EEE_CTL_STAT_P2_EEE_AUTO_Msk (0x1UL) /*!< EEE_AUTO (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_LPI_REQ_Pos (1UL) /*!< LPI_REQ (Bit 1) */ + #define R_ETHSW_EEE_CTL_STAT_P2_LPI_REQ_Msk (0x2UL) /*!< LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_LPI_TXHOLD_Pos (2UL) /*!< LPI_TXHOLD (Bit 2) */ + #define R_ETHSW_EEE_CTL_STAT_P2_LPI_TXHOLD_Msk (0x4UL) /*!< LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_REQ_Pos (8UL) /*!< ST_LPI_REQ (Bit 8) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_REQ_Msk (0x100UL) /*!< ST_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_TXHOLD_Pos (9UL) /*!< ST_LPI_TXHOLD (Bit 9) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_TXHOLD_Msk (0x200UL) /*!< ST_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXBUSY_Pos (10UL) /*!< ST_TXBUSY (Bit 10) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXBUSY_Msk (0x400UL) /*!< ST_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXAVAIL_Pos (11UL) /*!< ST_TXAVAIL (Bit 11) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_TXAVAIL_Msk (0x800UL) /*!< ST_TXAVAIL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_IND_Pos (12UL) /*!< ST_LPI_IND (Bit 12) */ + #define R_ETHSW_EEE_CTL_STAT_P2_ST_LPI_IND_Msk (0x1000UL) /*!< ST_LPI_IND (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_REQ_Pos (16UL) /*!< STLH_LPI_REQ (Bit 16) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_REQ_Msk (0x10000UL) /*!< STLH_LPI_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_TXHOLD_Pos (17UL) /*!< STLH_LPI_TXHOLD (Bit 17) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_TXHOLD_Msk (0x20000UL) /*!< STLH_LPI_TXHOLD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_TXBUSY_Pos (18UL) /*!< STLH_TXBUSY (Bit 18) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_TXBUSY_Msk (0x40000UL) /*!< STLH_TXBUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_IND_Pos (20UL) /*!< STLH_LPI_IND (Bit 20) */ + #define R_ETHSW_EEE_CTL_STAT_P2_STLH_LPI_IND_Msk (0x100000UL) /*!< STLH_LPI_IND (Bitfield-Mask: 0x01) */ +/* =================================================== EEE_IDLE_TIME_P0 ==================================================== */ + #define R_ETHSW_EEE_IDLE_TIME_P0_EEE_IDLE_TIME_Pos (0UL) /*!< EEE_IDLE_TIME (Bit 0) */ + #define R_ETHSW_EEE_IDLE_TIME_P0_EEE_IDLE_TIME_Msk (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== EEE_IDLE_TIME_P1 ==================================================== */ + #define R_ETHSW_EEE_IDLE_TIME_P1_EEE_IDLE_TIME_Pos (0UL) /*!< EEE_IDLE_TIME (Bit 0) */ + #define R_ETHSW_EEE_IDLE_TIME_P1_EEE_IDLE_TIME_Msk (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== EEE_IDLE_TIME_P2 ==================================================== */ + #define R_ETHSW_EEE_IDLE_TIME_P2_EEE_IDLE_TIME_Pos (0UL) /*!< EEE_IDLE_TIME (Bit 0) */ + #define R_ETHSW_EEE_IDLE_TIME_P2_EEE_IDLE_TIME_Msk (0xffffffffUL) /*!< EEE_IDLE_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== EEE_TWSYS_TIME_P0 =================================================== */ + #define R_ETHSW_EEE_TWSYS_TIME_P0_EEE_WKUP_TIME_Pos (0UL) /*!< EEE_WKUP_TIME (Bit 0) */ + #define R_ETHSW_EEE_TWSYS_TIME_P0_EEE_WKUP_TIME_Msk (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== EEE_TWSYS_TIME_P1 =================================================== */ + #define R_ETHSW_EEE_TWSYS_TIME_P1_EEE_WKUP_TIME_Pos (0UL) /*!< EEE_WKUP_TIME (Bit 0) */ + #define R_ETHSW_EEE_TWSYS_TIME_P1_EEE_WKUP_TIME_Msk (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff) */ +/* =================================================== EEE_TWSYS_TIME_P2 =================================================== */ + #define R_ETHSW_EEE_TWSYS_TIME_P2_EEE_WKUP_TIME_Pos (0UL) /*!< EEE_WKUP_TIME (Bit 0) */ + #define R_ETHSW_EEE_TWSYS_TIME_P2_EEE_WKUP_TIME_Msk (0xffffffffUL) /*!< EEE_WKUP_TIME (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IDLE_SLOPE_P0 ===================================================== */ + #define R_ETHSW_IDLE_SLOPE_P0_IDLE_SLOPE_Pos (0UL) /*!< IDLE_SLOPE (Bit 0) */ + #define R_ETHSW_IDLE_SLOPE_P0_IDLE_SLOPE_Msk (0x7ffUL) /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff) */ +/* ===================================================== IDLE_SLOPE_P1 ===================================================== */ + #define R_ETHSW_IDLE_SLOPE_P1_IDLE_SLOPE_Pos (0UL) /*!< IDLE_SLOPE (Bit 0) */ + #define R_ETHSW_IDLE_SLOPE_P1_IDLE_SLOPE_Msk (0x7ffUL) /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff) */ +/* ===================================================== IDLE_SLOPE_P2 ===================================================== */ + #define R_ETHSW_IDLE_SLOPE_P2_IDLE_SLOPE_Pos (0UL) /*!< IDLE_SLOPE (Bit 0) */ + #define R_ETHSW_IDLE_SLOPE_P2_IDLE_SLOPE_Msk (0x7ffUL) /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff) */ +/* ===================================================== IDLE_SLOPE_P3 ===================================================== */ + #define R_ETHSW_IDLE_SLOPE_P3_IDLE_SLOPE_Pos (0UL) /*!< IDLE_SLOPE (Bit 0) */ + #define R_ETHSW_IDLE_SLOPE_P3_IDLE_SLOPE_Msk (0x7ffUL) /*!< IDLE_SLOPE (Bitfield-Mask: 0x7ff) */ +/* ====================================================== CT_DELAY_P0 ====================================================== */ + #define R_ETHSW_CT_DELAY_P0_CT_DELAY_Pos (0UL) /*!< CT_DELAY (Bit 0) */ + #define R_ETHSW_CT_DELAY_P0_CT_DELAY_Msk (0x1ffUL) /*!< CT_DELAY (Bitfield-Mask: 0x1ff) */ +/* ====================================================== CT_DELAY_P1 ====================================================== */ + #define R_ETHSW_CT_DELAY_P1_CT_DELAY_Pos (0UL) /*!< CT_DELAY (Bit 0) */ + #define R_ETHSW_CT_DELAY_P1_CT_DELAY_Msk (0x1ffUL) /*!< CT_DELAY (Bitfield-Mask: 0x1ff) */ +/* ====================================================== CT_DELAY_P2 ====================================================== */ + #define R_ETHSW_CT_DELAY_P2_CT_DELAY_Pos (0UL) /*!< CT_DELAY (Bit 0) */ + #define R_ETHSW_CT_DELAY_P2_CT_DELAY_Msk (0x1ffUL) /*!< CT_DELAY (Bitfield-Mask: 0x1ff) */ +/* ===================================================== BR_CONTROL_P0 ===================================================== */ + #define R_ETHSW_BR_CONTROL_P0_PREEMPT_ENA_Pos (0UL) /*!< PREEMPT_ENA (Bit 0) */ + #define R_ETHSW_BR_CONTROL_P0_PREEMPT_ENA_Msk (0x1UL) /*!< PREEMPT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_VERIFY_DIS_Pos (1UL) /*!< VERIFY_DIS (Bit 1) */ + #define R_ETHSW_BR_CONTROL_P0_VERIFY_DIS_Msk (0x2UL) /*!< VERIFY_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_RESPONSE_DIS_Pos (2UL) /*!< RESPONSE_DIS (Bit 2) */ + #define R_ETHSW_BR_CONTROL_P0_RESPONSE_DIS_Msk (0x4UL) /*!< RESPONSE_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Pos (4UL) /*!< ADDFRAGSIZE (Bit 4) */ + #define R_ETHSW_BR_CONTROL_P0_ADDFRAGSIZE_Msk (0x30UL) /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03) */ + #define R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Pos (8UL) /*!< TX_VERIFY_TIME (Bit 8) */ + #define R_ETHSW_BR_CONTROL_P0_TX_VERIFY_TIME_Msk (0x7f00UL) /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_PRE_Pos (16UL) /*!< RX_STRICT_PRE (Bit 16) */ + #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_PRE_Msk (0x10000UL) /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_RX_BR_SMD_DIS_Pos (17UL) /*!< RX_BR_SMD_DIS (Bit 17) */ + #define R_ETHSW_BR_CONTROL_P0_RX_BR_SMD_DIS_Msk (0x20000UL) /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_BR_CTL_Pos (18UL) /*!< RX_STRICT_BR_CTL (Bit 18) */ + #define R_ETHSW_BR_CONTROL_P0_RX_STRICT_BR_CTL_Msk (0x40000UL) /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_TX_MCRC_INV_Pos (19UL) /*!< TX_MCRC_INV (Bit 19) */ + #define R_ETHSW_BR_CONTROL_P0_TX_MCRC_INV_Msk (0x80000UL) /*!< TX_MCRC_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P0_RX_MCRC_INV_Pos (20UL) /*!< RX_MCRC_INV (Bit 20) */ + #define R_ETHSW_BR_CONTROL_P0_RX_MCRC_INV_Msk (0x100000UL) /*!< RX_MCRC_INV (Bitfield-Mask: 0x01) */ +/* ===================================================== BR_CONTROL_P1 ===================================================== */ + #define R_ETHSW_BR_CONTROL_P1_PREEMPT_ENA_Pos (0UL) /*!< PREEMPT_ENA (Bit 0) */ + #define R_ETHSW_BR_CONTROL_P1_PREEMPT_ENA_Msk (0x1UL) /*!< PREEMPT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_VERIFY_DIS_Pos (1UL) /*!< VERIFY_DIS (Bit 1) */ + #define R_ETHSW_BR_CONTROL_P1_VERIFY_DIS_Msk (0x2UL) /*!< VERIFY_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_RESPONSE_DIS_Pos (2UL) /*!< RESPONSE_DIS (Bit 2) */ + #define R_ETHSW_BR_CONTROL_P1_RESPONSE_DIS_Msk (0x4UL) /*!< RESPONSE_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_ADDFRAGSIZE_Pos (4UL) /*!< ADDFRAGSIZE (Bit 4) */ + #define R_ETHSW_BR_CONTROL_P1_ADDFRAGSIZE_Msk (0x30UL) /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03) */ + #define R_ETHSW_BR_CONTROL_P1_TX_VERIFY_TIME_Pos (8UL) /*!< TX_VERIFY_TIME (Bit 8) */ + #define R_ETHSW_BR_CONTROL_P1_TX_VERIFY_TIME_Msk (0x7f00UL) /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_PRE_Pos (16UL) /*!< RX_STRICT_PRE (Bit 16) */ + #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_PRE_Msk (0x10000UL) /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_RX_BR_SMD_DIS_Pos (17UL) /*!< RX_BR_SMD_DIS (Bit 17) */ + #define R_ETHSW_BR_CONTROL_P1_RX_BR_SMD_DIS_Msk (0x20000UL) /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_BR_CTL_Pos (18UL) /*!< RX_STRICT_BR_CTL (Bit 18) */ + #define R_ETHSW_BR_CONTROL_P1_RX_STRICT_BR_CTL_Msk (0x40000UL) /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_TX_MCRC_INV_Pos (19UL) /*!< TX_MCRC_INV (Bit 19) */ + #define R_ETHSW_BR_CONTROL_P1_TX_MCRC_INV_Msk (0x80000UL) /*!< TX_MCRC_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P1_RX_MCRC_INV_Pos (20UL) /*!< RX_MCRC_INV (Bit 20) */ + #define R_ETHSW_BR_CONTROL_P1_RX_MCRC_INV_Msk (0x100000UL) /*!< RX_MCRC_INV (Bitfield-Mask: 0x01) */ +/* ===================================================== BR_CONTROL_P2 ===================================================== */ + #define R_ETHSW_BR_CONTROL_P2_PREEMPT_ENA_Pos (0UL) /*!< PREEMPT_ENA (Bit 0) */ + #define R_ETHSW_BR_CONTROL_P2_PREEMPT_ENA_Msk (0x1UL) /*!< PREEMPT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_VERIFY_DIS_Pos (1UL) /*!< VERIFY_DIS (Bit 1) */ + #define R_ETHSW_BR_CONTROL_P2_VERIFY_DIS_Msk (0x2UL) /*!< VERIFY_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_RESPONSE_DIS_Pos (2UL) /*!< RESPONSE_DIS (Bit 2) */ + #define R_ETHSW_BR_CONTROL_P2_RESPONSE_DIS_Msk (0x4UL) /*!< RESPONSE_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_ADDFRAGSIZE_Pos (4UL) /*!< ADDFRAGSIZE (Bit 4) */ + #define R_ETHSW_BR_CONTROL_P2_ADDFRAGSIZE_Msk (0x30UL) /*!< ADDFRAGSIZE (Bitfield-Mask: 0x03) */ + #define R_ETHSW_BR_CONTROL_P2_TX_VERIFY_TIME_Pos (8UL) /*!< TX_VERIFY_TIME (Bit 8) */ + #define R_ETHSW_BR_CONTROL_P2_TX_VERIFY_TIME_Msk (0x7f00UL) /*!< TX_VERIFY_TIME (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_PRE_Pos (16UL) /*!< RX_STRICT_PRE (Bit 16) */ + #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_PRE_Msk (0x10000UL) /*!< RX_STRICT_PRE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_RX_BR_SMD_DIS_Pos (17UL) /*!< RX_BR_SMD_DIS (Bit 17) */ + #define R_ETHSW_BR_CONTROL_P2_RX_BR_SMD_DIS_Msk (0x20000UL) /*!< RX_BR_SMD_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_BR_CTL_Pos (18UL) /*!< RX_STRICT_BR_CTL (Bit 18) */ + #define R_ETHSW_BR_CONTROL_P2_RX_STRICT_BR_CTL_Msk (0x40000UL) /*!< RX_STRICT_BR_CTL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_TX_MCRC_INV_Pos (19UL) /*!< TX_MCRC_INV (Bit 19) */ + #define R_ETHSW_BR_CONTROL_P2_TX_MCRC_INV_Msk (0x80000UL) /*!< TX_MCRC_INV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_BR_CONTROL_P2_RX_MCRC_INV_Pos (20UL) /*!< RX_MCRC_INV (Bit 20) */ + #define R_ETHSW_BR_CONTROL_P2_RX_MCRC_INV_Msk (0x100000UL) /*!< RX_MCRC_INV (Bitfield-Mask: 0x01) */ +/* ================================================ AFRAMESTRANSMITTEDOK_P0 ================================================ */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P0_TXVALIDCOUNT_Pos (0UL) /*!< TXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P0_TXVALIDCOUNT_Msk (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AFRAMESTRANSMITTEDOK_P1 ================================================ */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P1_TXVALIDCOUNT_Pos (0UL) /*!< TXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P1_TXVALIDCOUNT_Msk (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AFRAMESTRANSMITTEDOK_P2 ================================================ */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P2_TXVALIDCOUNT_Pos (0UL) /*!< TXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P2_TXVALIDCOUNT_Msk (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AFRAMESTRANSMITTEDOK_P3 ================================================ */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P3_TXVALIDCOUNT_Pos (0UL) /*!< TXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESTRANSMITTEDOK_P3_TXVALIDCOUNT_Msk (0xffffffffUL) /*!< TXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AFRAMESRECEIVEDOK_P0 ================================================== */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P0_RXVALIDCOUNT_Pos (0UL) /*!< RXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P0_RXVALIDCOUNT_Msk (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AFRAMESRECEIVEDOK_P1 ================================================== */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P1_RXVALIDCOUNT_Pos (0UL) /*!< RXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P1_RXVALIDCOUNT_Msk (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AFRAMESRECEIVEDOK_P2 ================================================== */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P2_RXVALIDCOUNT_Pos (0UL) /*!< RXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P2_RXVALIDCOUNT_Msk (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AFRAMESRECEIVEDOK_P3 ================================================== */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P3_RXVALIDCOUNT_Pos (0UL) /*!< RXVALIDCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMESRECEIVEDOK_P3_RXVALIDCOUNT_Msk (0xffffffffUL) /*!< RXVALIDCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================= AFRAMECHECKSEQUENCEERRORS_P0 ============================================== */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P0_FCSERRCOUNT_Pos (0UL) /*!< FCSERRCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P0_FCSERRCOUNT_Msk (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================= AFRAMECHECKSEQUENCEERRORS_P1 ============================================== */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P1_FCSERRCOUNT_Pos (0UL) /*!< FCSERRCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P1_FCSERRCOUNT_Msk (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================= AFRAMECHECKSEQUENCEERRORS_P2 ============================================== */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P2_FCSERRCOUNT_Pos (0UL) /*!< FCSERRCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P2_FCSERRCOUNT_Msk (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================= AFRAMECHECKSEQUENCEERRORS_P3 ============================================== */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P3_FCSERRCOUNT_Pos (0UL) /*!< FCSERRCOUNT (Bit 0) */ + #define R_ETHSW_AFRAMECHECKSEQUENCEERRORS_P3_FCSERRCOUNT_Msk (0xffffffffUL) /*!< FCSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== AALIGNMENTERRORS_P0 ================================================== */ + #define R_ETHSW_AALIGNMENTERRORS_P0_ALGNERRCOUNT_Pos (0UL) /*!< ALGNERRCOUNT (Bit 0) */ + #define R_ETHSW_AALIGNMENTERRORS_P0_ALGNERRCOUNT_Msk (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== AALIGNMENTERRORS_P1 ================================================== */ + #define R_ETHSW_AALIGNMENTERRORS_P1_ALGNERRCOUNT_Pos (0UL) /*!< ALGNERRCOUNT (Bit 0) */ + #define R_ETHSW_AALIGNMENTERRORS_P1_ALGNERRCOUNT_Msk (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== AALIGNMENTERRORS_P2 ================================================== */ + #define R_ETHSW_AALIGNMENTERRORS_P2_ALGNERRCOUNT_Pos (0UL) /*!< ALGNERRCOUNT (Bit 0) */ + #define R_ETHSW_AALIGNMENTERRORS_P2_ALGNERRCOUNT_Msk (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== AALIGNMENTERRORS_P3 ================================================== */ + #define R_ETHSW_AALIGNMENTERRORS_P3_ALGNERRCOUNT_Pos (0UL) /*!< ALGNERRCOUNT (Bit 0) */ + #define R_ETHSW_AALIGNMENTERRORS_P3_ALGNERRCOUNT_Msk (0xffffffffUL) /*!< ALGNERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AOCTETSTRANSMITTEDOK_P0 ================================================ */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P0_TXVALIDOCTETS_Pos (0UL) /*!< TXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P0_TXVALIDOCTETS_Msk (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AOCTETSTRANSMITTEDOK_P1 ================================================ */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P1_TXVALIDOCTETS_Pos (0UL) /*!< TXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P1_TXVALIDOCTETS_Msk (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AOCTETSTRANSMITTEDOK_P2 ================================================ */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P2_TXVALIDOCTETS_Pos (0UL) /*!< TXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P2_TXVALIDOCTETS_Msk (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AOCTETSTRANSMITTEDOK_P3 ================================================ */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P3_TXVALIDOCTETS_Pos (0UL) /*!< TXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSTRANSMITTEDOK_P3_TXVALIDOCTETS_Msk (0xffffffffUL) /*!< TXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AOCTETSRECEIVEDOK_P0 ================================================== */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P0_RXVALIDOCTETS_Pos (0UL) /*!< RXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P0_RXVALIDOCTETS_Msk (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AOCTETSRECEIVEDOK_P1 ================================================== */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P1_RXVALIDOCTETS_Pos (0UL) /*!< RXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P1_RXVALIDOCTETS_Msk (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AOCTETSRECEIVEDOK_P2 ================================================== */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P2_RXVALIDOCTETS_Pos (0UL) /*!< RXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P2_RXVALIDOCTETS_Msk (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================= AOCTETSRECEIVEDOK_P3 ================================================== */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P3_RXVALIDOCTETS_Pos (0UL) /*!< RXVALIDOCTETS (Bit 0) */ + #define R_ETHSW_AOCTETSRECEIVEDOK_P3_RXVALIDOCTETS_Msk (0xffffffffUL) /*!< RXVALIDOCTETS (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ATXPAUSEMACCTRLFRAMES_P0 ================================================ */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P0_TXPAUSECOUNT_Pos (0UL) /*!< TXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P0_TXPAUSECOUNT_Msk (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ATXPAUSEMACCTRLFRAMES_P1 ================================================ */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P1_TXPAUSECOUNT_Pos (0UL) /*!< TXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P1_TXPAUSECOUNT_Msk (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ATXPAUSEMACCTRLFRAMES_P2 ================================================ */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P2_TXPAUSECOUNT_Pos (0UL) /*!< TXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P2_TXPAUSECOUNT_Msk (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ATXPAUSEMACCTRLFRAMES_P3 ================================================ */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P3_TXPAUSECOUNT_Pos (0UL) /*!< TXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ATXPAUSEMACCTRLFRAMES_P3_TXPAUSECOUNT_Msk (0xffffffffUL) /*!< TXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ARXPAUSEMACCTRLFRAMES_P0 ================================================ */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P0_RXPAUSECOUNT_Pos (0UL) /*!< RXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P0_RXPAUSECOUNT_Msk (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ARXPAUSEMACCTRLFRAMES_P1 ================================================ */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P1_RXPAUSECOUNT_Pos (0UL) /*!< RXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P1_RXPAUSECOUNT_Msk (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ARXPAUSEMACCTRLFRAMES_P2 ================================================ */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P2_RXPAUSECOUNT_Pos (0UL) /*!< RXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P2_RXPAUSECOUNT_Msk (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ARXPAUSEMACCTRLFRAMES_P3 ================================================ */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P3_RXPAUSECOUNT_Pos (0UL) /*!< RXPAUSECOUNT (Bit 0) */ + #define R_ETHSW_ARXPAUSEMACCTRLFRAMES_P3_RXPAUSECOUNT_Msk (0xffffffffUL) /*!< RXPAUSECOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IFINERRORS_P0 ===================================================== */ + #define R_ETHSW_IFINERRORS_P0_INERRCOUNT_Pos (0UL) /*!< INERRCOUNT (Bit 0) */ + #define R_ETHSW_IFINERRORS_P0_INERRCOUNT_Msk (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IFINERRORS_P1 ===================================================== */ + #define R_ETHSW_IFINERRORS_P1_INERRCOUNT_Pos (0UL) /*!< INERRCOUNT (Bit 0) */ + #define R_ETHSW_IFINERRORS_P1_INERRCOUNT_Msk (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IFINERRORS_P2 ===================================================== */ + #define R_ETHSW_IFINERRORS_P2_INERRCOUNT_Pos (0UL) /*!< INERRCOUNT (Bit 0) */ + #define R_ETHSW_IFINERRORS_P2_INERRCOUNT_Msk (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IFINERRORS_P3 ===================================================== */ + #define R_ETHSW_IFINERRORS_P3_INERRCOUNT_Pos (0UL) /*!< INERRCOUNT (Bit 0) */ + #define R_ETHSW_IFINERRORS_P3_INERRCOUNT_Msk (0xffffffffUL) /*!< INERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IFOUTERRORS_P0 ===================================================== */ + #define R_ETHSW_IFOUTERRORS_P0_OUTERRCOUNT_Pos (0UL) /*!< OUTERRCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTERRORS_P0_OUTERRCOUNT_Msk (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IFOUTERRORS_P1 ===================================================== */ + #define R_ETHSW_IFOUTERRORS_P1_OUTERRCOUNT_Pos (0UL) /*!< OUTERRCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTERRORS_P1_OUTERRCOUNT_Msk (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IFOUTERRORS_P2 ===================================================== */ + #define R_ETHSW_IFOUTERRORS_P2_OUTERRCOUNT_Pos (0UL) /*!< OUTERRCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTERRORS_P2_OUTERRCOUNT_Msk (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IFOUTERRORS_P3 ===================================================== */ + #define R_ETHSW_IFOUTERRORS_P3_OUTERRCOUNT_Pos (0UL) /*!< OUTERRCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTERRORS_P3_OUTERRCOUNT_Msk (0xffffffffUL) /*!< OUTERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFINUCASTPKTS_P0 ==================================================== */ + #define R_ETHSW_IFINUCASTPKTS_P0_RXUCASTCOUNT_Pos (0UL) /*!< RXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINUCASTPKTS_P0_RXUCASTCOUNT_Msk (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFINUCASTPKTS_P1 ==================================================== */ + #define R_ETHSW_IFINUCASTPKTS_P1_RXUCASTCOUNT_Pos (0UL) /*!< RXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINUCASTPKTS_P1_RXUCASTCOUNT_Msk (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFINUCASTPKTS_P2 ==================================================== */ + #define R_ETHSW_IFINUCASTPKTS_P2_RXUCASTCOUNT_Pos (0UL) /*!< RXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINUCASTPKTS_P2_RXUCASTCOUNT_Msk (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFINUCASTPKTS_P3 ==================================================== */ + #define R_ETHSW_IFINUCASTPKTS_P3_RXUCASTCOUNT_Pos (0UL) /*!< RXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINUCASTPKTS_P3_RXUCASTCOUNT_Msk (0xffffffffUL) /*!< RXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINMULTICASTPKTS_P0 ================================================== */ + #define R_ETHSW_IFINMULTICASTPKTS_P0_RXMCASTCOUNT_Pos (0UL) /*!< RXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINMULTICASTPKTS_P0_RXMCASTCOUNT_Msk (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINMULTICASTPKTS_P1 ================================================== */ + #define R_ETHSW_IFINMULTICASTPKTS_P1_RXMCASTCOUNT_Pos (0UL) /*!< RXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINMULTICASTPKTS_P1_RXMCASTCOUNT_Msk (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINMULTICASTPKTS_P2 ================================================== */ + #define R_ETHSW_IFINMULTICASTPKTS_P2_RXMCASTCOUNT_Pos (0UL) /*!< RXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINMULTICASTPKTS_P2_RXMCASTCOUNT_Msk (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINMULTICASTPKTS_P3 ================================================== */ + #define R_ETHSW_IFINMULTICASTPKTS_P3_RXMCASTCOUNT_Pos (0UL) /*!< RXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINMULTICASTPKTS_P3_RXMCASTCOUNT_Msk (0xffffffffUL) /*!< RXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINBROADCASTPKTS_P0 ================================================== */ + #define R_ETHSW_IFINBROADCASTPKTS_P0_RXBCASTCOUNT_Pos (0UL) /*!< RXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINBROADCASTPKTS_P0_RXBCASTCOUNT_Msk (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINBROADCASTPKTS_P1 ================================================== */ + #define R_ETHSW_IFINBROADCASTPKTS_P1_RXBCASTCOUNT_Pos (0UL) /*!< RXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINBROADCASTPKTS_P1_RXBCASTCOUNT_Msk (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINBROADCASTPKTS_P2 ================================================== */ + #define R_ETHSW_IFINBROADCASTPKTS_P2_RXBCASTCOUNT_Pos (0UL) /*!< RXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINBROADCASTPKTS_P2_RXBCASTCOUNT_Msk (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFINBROADCASTPKTS_P3 ================================================== */ + #define R_ETHSW_IFINBROADCASTPKTS_P3_RXBCASTCOUNT_Pos (0UL) /*!< RXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFINBROADCASTPKTS_P3_RXBCASTCOUNT_Msk (0xffffffffUL) /*!< RXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTDISCARDS_P0 ==================================================== */ + #define R_ETHSW_IFOUTDISCARDS_P0_DISCOBCOUNT_Pos (0UL) /*!< DISCOBCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTDISCARDS_P0_DISCOBCOUNT_Msk (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTDISCARDS_P1 ==================================================== */ + #define R_ETHSW_IFOUTDISCARDS_P1_DISCOBCOUNT_Pos (0UL) /*!< DISCOBCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTDISCARDS_P1_DISCOBCOUNT_Msk (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTDISCARDS_P2 ==================================================== */ + #define R_ETHSW_IFOUTDISCARDS_P2_DISCOBCOUNT_Pos (0UL) /*!< DISCOBCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTDISCARDS_P2_DISCOBCOUNT_Msk (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTDISCARDS_P3 ==================================================== */ + #define R_ETHSW_IFOUTDISCARDS_P3_DISCOBCOUNT_Pos (0UL) /*!< DISCOBCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTDISCARDS_P3_DISCOBCOUNT_Msk (0xffffffffUL) /*!< DISCOBCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTUCASTPKTS_P0 =================================================== */ + #define R_ETHSW_IFOUTUCASTPKTS_P0_TXUCASTCOUNT_Pos (0UL) /*!< TXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTUCASTPKTS_P0_TXUCASTCOUNT_Msk (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTUCASTPKTS_P1 =================================================== */ + #define R_ETHSW_IFOUTUCASTPKTS_P1_TXUCASTCOUNT_Pos (0UL) /*!< TXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTUCASTPKTS_P1_TXUCASTCOUNT_Msk (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTUCASTPKTS_P2 =================================================== */ + #define R_ETHSW_IFOUTUCASTPKTS_P2_TXUCASTCOUNT_Pos (0UL) /*!< TXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTUCASTPKTS_P2_TXUCASTCOUNT_Msk (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== IFOUTUCASTPKTS_P3 =================================================== */ + #define R_ETHSW_IFOUTUCASTPKTS_P3_TXUCASTCOUNT_Pos (0UL) /*!< TXUCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTUCASTPKTS_P3_TXUCASTCOUNT_Msk (0xffffffffUL) /*!< TXUCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTMULTICASTPKTS_P0 ================================================= */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P0_TXMCASTCOUNT_Pos (0UL) /*!< TXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P0_TXMCASTCOUNT_Msk (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTMULTICASTPKTS_P1 ================================================= */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P1_TXMCASTCOUNT_Pos (0UL) /*!< TXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P1_TXMCASTCOUNT_Msk (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTMULTICASTPKTS_P2 ================================================= */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P2_TXMCASTCOUNT_Pos (0UL) /*!< TXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P2_TXMCASTCOUNT_Msk (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTMULTICASTPKTS_P3 ================================================= */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P3_TXMCASTCOUNT_Pos (0UL) /*!< TXMCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTMULTICASTPKTS_P3_TXMCASTCOUNT_Msk (0xffffffffUL) /*!< TXMCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTBROADCASTPKTS_P0 ================================================= */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P0_TXBCASTCOUNT_Pos (0UL) /*!< TXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P0_TXBCASTCOUNT_Msk (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTBROADCASTPKTS_P1 ================================================= */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P1_TXBCASTCOUNT_Pos (0UL) /*!< TXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P1_TXBCASTCOUNT_Msk (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTBROADCASTPKTS_P2 ================================================= */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P2_TXBCASTCOUNT_Pos (0UL) /*!< TXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P2_TXBCASTCOUNT_Msk (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= IFOUTBROADCASTPKTS_P3 ================================================= */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P3_TXBCASTCOUNT_Pos (0UL) /*!< TXBCASTCOUNT (Bit 0) */ + #define R_ETHSW_IFOUTBROADCASTPKTS_P3_TXBCASTCOUNT_Msk (0xffffffffUL) /*!< TXBCASTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSDROPEVENTS_P0 ================================================ */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P0_DROPCOUNT_Pos (0UL) /*!< DROPCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P0_DROPCOUNT_Msk (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSDROPEVENTS_P1 ================================================ */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P1_DROPCOUNT_Pos (0UL) /*!< DROPCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P1_DROPCOUNT_Msk (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSDROPEVENTS_P2 ================================================ */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P2_DROPCOUNT_Pos (0UL) /*!< DROPCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P2_DROPCOUNT_Msk (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSDROPEVENTS_P3 ================================================ */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P3_DROPCOUNT_Pos (0UL) /*!< DROPCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSDROPEVENTS_P3_DROPCOUNT_Msk (0xffffffffUL) /*!< DROPCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ETHERSTATSOCTETS_P0 ================================================== */ + #define R_ETHSW_ETHERSTATSOCTETS_P0_ALLOCTETS_Pos (0UL) /*!< ALLOCTETS (Bit 0) */ + #define R_ETHSW_ETHERSTATSOCTETS_P0_ALLOCTETS_Msk (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ETHERSTATSOCTETS_P1 ================================================== */ + #define R_ETHSW_ETHERSTATSOCTETS_P1_ALLOCTETS_Pos (0UL) /*!< ALLOCTETS (Bit 0) */ + #define R_ETHSW_ETHERSTATSOCTETS_P1_ALLOCTETS_Msk (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ETHERSTATSOCTETS_P2 ================================================== */ + #define R_ETHSW_ETHERSTATSOCTETS_P2_ALLOCTETS_Pos (0UL) /*!< ALLOCTETS (Bit 0) */ + #define R_ETHSW_ETHERSTATSOCTETS_P2_ALLOCTETS_Msk (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ETHERSTATSOCTETS_P3 ================================================== */ + #define R_ETHSW_ETHERSTATSOCTETS_P3_ALLOCTETS_Pos (0UL) /*!< ALLOCTETS (Bit 0) */ + #define R_ETHSW_ETHERSTATSOCTETS_P3_ALLOCTETS_Msk (0xffffffffUL) /*!< ALLOCTETS (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ETHERSTATSPKTS_P0 =================================================== */ + #define R_ETHSW_ETHERSTATSPKTS_P0_ALLCOUNT_Pos (0UL) /*!< ALLCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS_P0_ALLCOUNT_Msk (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ETHERSTATSPKTS_P1 =================================================== */ + #define R_ETHSW_ETHERSTATSPKTS_P1_ALLCOUNT_Pos (0UL) /*!< ALLCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS_P1_ALLCOUNT_Msk (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ETHERSTATSPKTS_P2 =================================================== */ + #define R_ETHSW_ETHERSTATSPKTS_P2_ALLCOUNT_Pos (0UL) /*!< ALLCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS_P2_ALLCOUNT_Msk (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== ETHERSTATSPKTS_P3 =================================================== */ + #define R_ETHSW_ETHERSTATSPKTS_P3_ALLCOUNT_Pos (0UL) /*!< ALLCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS_P3_ALLCOUNT_Msk (0xffffffffUL) /*!< ALLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ETHERSTATSUNDERSIZEPKTS_P0 =============================================== */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P0_TOOSHRTCOUNT_Pos (0UL) /*!< TOOSHRTCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P0_TOOSHRTCOUNT_Msk (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ETHERSTATSUNDERSIZEPKTS_P1 =============================================== */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P1_TOOSHRTCOUNT_Pos (0UL) /*!< TOOSHRTCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P1_TOOSHRTCOUNT_Msk (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ETHERSTATSUNDERSIZEPKTS_P2 =============================================== */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P2_TOOSHRTCOUNT_Pos (0UL) /*!< TOOSHRTCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P2_TOOSHRTCOUNT_Msk (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ============================================== ETHERSTATSUNDERSIZEPKTS_P3 =============================================== */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P3_TOOSHRTCOUNT_Pos (0UL) /*!< TOOSHRTCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSUNDERSIZEPKTS_P3_TOOSHRTCOUNT_Msk (0xffffffffUL) /*!< TOOSHRTCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSOVERSIZEPKTS_P0 =============================================== */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P0_TOOLONGCOUNT_Pos (0UL) /*!< TOOLONGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P0_TOOLONGCOUNT_Msk (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSOVERSIZEPKTS_P1 =============================================== */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P1_TOOLONGCOUNT_Pos (0UL) /*!< TOOLONGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P1_TOOLONGCOUNT_Msk (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSOVERSIZEPKTS_P2 =============================================== */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P2_TOOLONGCOUNT_Pos (0UL) /*!< TOOLONGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P2_TOOLONGCOUNT_Msk (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSOVERSIZEPKTS_P3 =============================================== */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P3_TOOLONGCOUNT_Pos (0UL) /*!< TOOLONGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSOVERSIZEPKTS_P3_TOOLONGCOUNT_Msk (0xffffffffUL) /*!< TOOLONGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSPKTS64OCTETS_P0 =============================================== */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P0_OCTCNT64_Pos (0UL) /*!< OCTCNT64 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P0_OCTCNT64_Msk (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSPKTS64OCTETS_P1 =============================================== */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P1_OCTCNT64_Pos (0UL) /*!< OCTCNT64 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P1_OCTCNT64_Msk (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSPKTS64OCTETS_P2 =============================================== */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P2_OCTCNT64_Pos (0UL) /*!< OCTCNT64 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P2_OCTCNT64_Msk (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff) */ +/* =============================================== ETHERSTATSPKTS64OCTETS_P3 =============================================== */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P3_OCTCNT64_Pos (0UL) /*!< OCTCNT64 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS64OCTETS_P3_OCTCNT64_Msk (0xffffffffUL) /*!< OCTCNT64 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS65TO127OCTETS_P0 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P0_OCTCNT65T127_Pos (0UL) /*!< OCTCNT65T127 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P0_OCTCNT65T127_Msk (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS65TO127OCTETS_P1 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P1_OCTCNT65T127_Pos (0UL) /*!< OCTCNT65T127 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P1_OCTCNT65T127_Msk (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS65TO127OCTETS_P2 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P2_OCTCNT65T127_Pos (0UL) /*!< OCTCNT65T127 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P2_OCTCNT65T127_Msk (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS65TO127OCTETS_P3 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P3_OCTCNT65T127_Pos (0UL) /*!< OCTCNT65T127 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS65TO127OCTETS_P3_OCTCNT65T127_Msk (0xffffffffUL) /*!< OCTCNT65T127 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS128TO255OCTETS_P0 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P0_OCTCNT128T255_Pos (0UL) /*!< OCTCNT128T255 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P0_OCTCNT128T255_Msk (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS128TO255OCTETS_P1 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P1_OCTCNT128T255_Pos (0UL) /*!< OCTCNT128T255 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P1_OCTCNT128T255_Msk (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS128TO255OCTETS_P2 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P2_OCTCNT128T255_Pos (0UL) /*!< OCTCNT128T255 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P2_OCTCNT128T255_Msk (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS128TO255OCTETS_P3 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P3_OCTCNT128T255_Pos (0UL) /*!< OCTCNT128T255 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS128TO255OCTETS_P3_OCTCNT128T255_Msk (0xffffffffUL) /*!< OCTCNT128T255 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS256TO511OCTETS_P0 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P0_OCTCNT256T511_Pos (0UL) /*!< OCTCNT256T511 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P0_OCTCNT256T511_Msk (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS256TO511OCTETS_P1 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P1_OCTCNT256T511_Pos (0UL) /*!< OCTCNT256T511 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P1_OCTCNT256T511_Msk (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS256TO511OCTETS_P2 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P2_OCTCNT256T511_Pos (0UL) /*!< OCTCNT256T511 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P2_OCTCNT256T511_Msk (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS256TO511OCTETS_P3 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P3_OCTCNT256T511_Pos (0UL) /*!< OCTCNT256T511 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS256TO511OCTETS_P3_OCTCNT256T511_Msk (0xffffffffUL) /*!< OCTCNT256T511 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS512TO1023OCTETS_P0 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P0_OCTCNT512T1023_Pos (0UL) /*!< OCTCNT512T1023 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P0_OCTCNT512T1023_Msk (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS512TO1023OCTETS_P1 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P1_OCTCNT512T1023_Pos (0UL) /*!< OCTCNT512T1023 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P1_OCTCNT512T1023_Msk (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS512TO1023OCTETS_P2 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P2_OCTCNT512T1023_Pos (0UL) /*!< OCTCNT512T1023 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P2_OCTCNT512T1023_Msk (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS512TO1023OCTETS_P3 ============================================ */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P3_OCTCNT512T1023_Pos (0UL) /*!< OCTCNT512T1023 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS512TO1023OCTETS_P3_OCTCNT512T1023_Msk (0xffffffffUL) /*!< OCTCNT512T1023 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS1024TO1518OCTETS_P0 =========================================== */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P0_OCTCNT1024T1518_Pos (0UL) /*!< OCTCNT1024T1518 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P0_OCTCNT1024T1518_Msk (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS1024TO1518OCTETS_P1 =========================================== */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P1_OCTCNT1024T1518_Pos (0UL) /*!< OCTCNT1024T1518 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P1_OCTCNT1024T1518_Msk (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS1024TO1518OCTETS_P2 =========================================== */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P2_OCTCNT1024T1518_Pos (0UL) /*!< OCTCNT1024T1518 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P2_OCTCNT1024T1518_Msk (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */ +/* =========================================== ETHERSTATSPKTS1024TO1518OCTETS_P3 =========================================== */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P3_OCTCNT1024T1518_Pos (0UL) /*!< OCTCNT1024T1518 (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1024TO1518OCTETS_P3_OCTCNT1024T1518_Msk (0xffffffffUL) /*!< OCTCNT1024T1518 (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS1519TOXOCTETS_P0 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P0_OCTCNT1519TX_Pos (0UL) /*!< OCTCNT1519TX (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P0_OCTCNT1519TX_Msk (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS1519TOXOCTETS_P1 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P1_OCTCNT1519TX_Pos (0UL) /*!< OCTCNT1519TX (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P1_OCTCNT1519TX_Msk (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS1519TOXOCTETS_P2 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P2_OCTCNT1519TX_Pos (0UL) /*!< OCTCNT1519TX (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P2_OCTCNT1519TX_Msk (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff) */ +/* ============================================ ETHERSTATSPKTS1519TOXOCTETS_P3 ============================================= */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P3_OCTCNT1519TX_Pos (0UL) /*!< OCTCNT1519TX (Bit 0) */ + #define R_ETHSW_ETHERSTATSPKTS1519TOXOCTETS_P3_OCTCNT1519TX_Msk (0xffffffffUL) /*!< OCTCNT1519TX (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ETHERSTATSJABBERS_P0 ================================================== */ + #define R_ETHSW_ETHERSTATSJABBERS_P0_JABBERCOUNT_Pos (0UL) /*!< JABBERCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSJABBERS_P0_JABBERCOUNT_Msk (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ETHERSTATSJABBERS_P1 ================================================== */ + #define R_ETHSW_ETHERSTATSJABBERS_P1_JABBERCOUNT_Pos (0UL) /*!< JABBERCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSJABBERS_P1_JABBERCOUNT_Msk (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ETHERSTATSJABBERS_P2 ================================================== */ + #define R_ETHSW_ETHERSTATSJABBERS_P2_JABBERCOUNT_Pos (0UL) /*!< JABBERCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSJABBERS_P2_JABBERCOUNT_Msk (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ETHERSTATSJABBERS_P3 ================================================== */ + #define R_ETHSW_ETHERSTATSJABBERS_P3_JABBERCOUNT_Pos (0UL) /*!< JABBERCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSJABBERS_P3_JABBERCOUNT_Msk (0xffffffffUL) /*!< JABBERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSFRAGMENTS_P0 ================================================= */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P0_FRAGCOUNT_Pos (0UL) /*!< FRAGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P0_FRAGCOUNT_Msk (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSFRAGMENTS_P1 ================================================= */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P1_FRAGCOUNT_Pos (0UL) /*!< FRAGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P1_FRAGCOUNT_Msk (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSFRAGMENTS_P2 ================================================= */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P2_FRAGCOUNT_Pos (0UL) /*!< FRAGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P2_FRAGCOUNT_Msk (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ETHERSTATSFRAGMENTS_P3 ================================================= */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P3_FRAGCOUNT_Pos (0UL) /*!< FRAGCOUNT (Bit 0) */ + #define R_ETHSW_ETHERSTATSFRAGMENTS_P3_FRAGCOUNT_Msk (0xffffffffUL) /*!< FRAGCOUNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== VLANRECEIVEDOK_P0 =================================================== */ + #define R_ETHSW_VLANRECEIVEDOK_P0_RXVLANTAGCNT_Pos (0UL) /*!< RXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANRECEIVEDOK_P0_RXVLANTAGCNT_Msk (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== VLANRECEIVEDOK_P1 =================================================== */ + #define R_ETHSW_VLANRECEIVEDOK_P1_RXVLANTAGCNT_Pos (0UL) /*!< RXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANRECEIVEDOK_P1_RXVLANTAGCNT_Msk (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== VLANRECEIVEDOK_P2 =================================================== */ + #define R_ETHSW_VLANRECEIVEDOK_P2_RXVLANTAGCNT_Pos (0UL) /*!< RXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANRECEIVEDOK_P2_RXVLANTAGCNT_Msk (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== VLANRECEIVEDOK_P3 =================================================== */ + #define R_ETHSW_VLANRECEIVEDOK_P3_RXVLANTAGCNT_Pos (0UL) /*!< RXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANRECEIVEDOK_P3_RXVLANTAGCNT_Msk (0xffffffffUL) /*!< RXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= VLANTRANSMITTEDOK_P0 ================================================== */ + #define R_ETHSW_VLANTRANSMITTEDOK_P0_TXVLANTAGCNT_Pos (0UL) /*!< TXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANTRANSMITTEDOK_P0_TXVLANTAGCNT_Msk (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= VLANTRANSMITTEDOK_P1 ================================================== */ + #define R_ETHSW_VLANTRANSMITTEDOK_P1_TXVLANTAGCNT_Pos (0UL) /*!< TXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANTRANSMITTEDOK_P1_TXVLANTAGCNT_Msk (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= VLANTRANSMITTEDOK_P2 ================================================== */ + #define R_ETHSW_VLANTRANSMITTEDOK_P2_TXVLANTAGCNT_Pos (0UL) /*!< TXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANTRANSMITTEDOK_P2_TXVLANTAGCNT_Msk (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================= VLANTRANSMITTEDOK_P3 ================================================== */ + #define R_ETHSW_VLANTRANSMITTEDOK_P3_TXVLANTAGCNT_Pos (0UL) /*!< TXVLANTAGCNT (Bit 0) */ + #define R_ETHSW_VLANTRANSMITTEDOK_P3_TXVLANTAGCNT_Msk (0xffffffffUL) /*!< TXVLANTAGCNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ FRAMESRETRANSMITTED_P0 ================================================= */ + #define R_ETHSW_FRAMESRETRANSMITTED_P0_RETXCOUNT_Pos (0UL) /*!< RETXCOUNT (Bit 0) */ + #define R_ETHSW_FRAMESRETRANSMITTED_P0_RETXCOUNT_Msk (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ FRAMESRETRANSMITTED_P1 ================================================= */ + #define R_ETHSW_FRAMESRETRANSMITTED_P1_RETXCOUNT_Pos (0UL) /*!< RETXCOUNT (Bit 0) */ + #define R_ETHSW_FRAMESRETRANSMITTED_P1_RETXCOUNT_Msk (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ FRAMESRETRANSMITTED_P2 ================================================= */ + #define R_ETHSW_FRAMESRETRANSMITTED_P2_RETXCOUNT_Pos (0UL) /*!< RETXCOUNT (Bit 0) */ + #define R_ETHSW_FRAMESRETRANSMITTED_P2_RETXCOUNT_Msk (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ FRAMESRETRANSMITTED_P3 ================================================= */ + #define R_ETHSW_FRAMESRETRANSMITTED_P3_RETXCOUNT_Pos (0UL) /*!< RETXCOUNT (Bit 0) */ + #define R_ETHSW_FRAMESRETRANSMITTED_P3_RETXCOUNT_Msk (0xffffffffUL) /*!< RETXCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== STATS_HIWORD_P0 ==================================================== */ + #define R_ETHSW_STATS_HIWORD_P0_STATS_HIWORD_Pos (0UL) /*!< STATS_HIWORD (Bit 0) */ + #define R_ETHSW_STATS_HIWORD_P0_STATS_HIWORD_Msk (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== STATS_HIWORD_P1 ==================================================== */ + #define R_ETHSW_STATS_HIWORD_P1_STATS_HIWORD_Pos (0UL) /*!< STATS_HIWORD (Bit 0) */ + #define R_ETHSW_STATS_HIWORD_P1_STATS_HIWORD_Msk (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== STATS_HIWORD_P2 ==================================================== */ + #define R_ETHSW_STATS_HIWORD_P2_STATS_HIWORD_Pos (0UL) /*!< STATS_HIWORD (Bit 0) */ + #define R_ETHSW_STATS_HIWORD_P2_STATS_HIWORD_Msk (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== STATS_HIWORD_P3 ==================================================== */ + #define R_ETHSW_STATS_HIWORD_P3_STATS_HIWORD_Pos (0UL) /*!< STATS_HIWORD (Bit 0) */ + #define R_ETHSW_STATS_HIWORD_P3_STATS_HIWORD_Msk (0xffffffffUL) /*!< STATS_HIWORD (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== STATS_CTRL_P0 ===================================================== */ + #define R_ETHSW_STATS_CTRL_P0_CLRALL_Pos (0UL) /*!< CLRALL (Bit 0) */ + #define R_ETHSW_STATS_CTRL_P0_CLRALL_Msk (0x1UL) /*!< CLRALL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATS_CTRL_P0_CLRBUSY_Pos (1UL) /*!< CLRBUSY (Bit 1) */ + #define R_ETHSW_STATS_CTRL_P0_CLRBUSY_Msk (0x2UL) /*!< CLRBUSY (Bitfield-Mask: 0x01) */ +/* ===================================================== STATS_CTRL_P1 ===================================================== */ + #define R_ETHSW_STATS_CTRL_P1_CLRALL_Pos (0UL) /*!< CLRALL (Bit 0) */ + #define R_ETHSW_STATS_CTRL_P1_CLRALL_Msk (0x1UL) /*!< CLRALL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATS_CTRL_P1_CLRBUSY_Pos (1UL) /*!< CLRBUSY (Bit 1) */ + #define R_ETHSW_STATS_CTRL_P1_CLRBUSY_Msk (0x2UL) /*!< CLRBUSY (Bitfield-Mask: 0x01) */ +/* ===================================================== STATS_CTRL_P2 ===================================================== */ + #define R_ETHSW_STATS_CTRL_P2_CLRALL_Pos (0UL) /*!< CLRALL (Bit 0) */ + #define R_ETHSW_STATS_CTRL_P2_CLRALL_Msk (0x1UL) /*!< CLRALL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATS_CTRL_P2_CLRBUSY_Pos (1UL) /*!< CLRBUSY (Bit 1) */ + #define R_ETHSW_STATS_CTRL_P2_CLRBUSY_Msk (0x2UL) /*!< CLRBUSY (Bitfield-Mask: 0x01) */ +/* ===================================================== STATS_CTRL_P3 ===================================================== */ + #define R_ETHSW_STATS_CTRL_P3_CLRALL_Pos (0UL) /*!< CLRALL (Bit 0) */ + #define R_ETHSW_STATS_CTRL_P3_CLRALL_Msk (0x1UL) /*!< CLRALL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATS_CTRL_P3_CLRBUSY_Pos (1UL) /*!< CLRBUSY (Bit 1) */ + #define R_ETHSW_STATS_CTRL_P3_CLRBUSY_Msk (0x2UL) /*!< CLRBUSY (Bitfield-Mask: 0x01) */ +/* ================================================ STATS_CLEAR_VALUELO_P0 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P0_STATS_CLEAR_VALUELO_Pos (0UL) /*!< STATS_CLEAR_VALUELO (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P0_STATS_CLEAR_VALUELO_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUELO_P1 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P1_STATS_CLEAR_VALUELO_Pos (0UL) /*!< STATS_CLEAR_VALUELO (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P1_STATS_CLEAR_VALUELO_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUELO_P2 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P2_STATS_CLEAR_VALUELO_Pos (0UL) /*!< STATS_CLEAR_VALUELO (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P2_STATS_CLEAR_VALUELO_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUELO_P3 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P3_STATS_CLEAR_VALUELO_Pos (0UL) /*!< STATS_CLEAR_VALUELO (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUELO_P3_STATS_CLEAR_VALUELO_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUELO (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUEHI_P0 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P0_STATS_CLEAR_VALUEHI_Pos (0UL) /*!< STATS_CLEAR_VALUEHI (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P0_STATS_CLEAR_VALUEHI_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUEHI_P1 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P1_STATS_CLEAR_VALUEHI_Pos (0UL) /*!< STATS_CLEAR_VALUEHI (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P1_STATS_CLEAR_VALUEHI_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUEHI_P2 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P2_STATS_CLEAR_VALUEHI_Pos (0UL) /*!< STATS_CLEAR_VALUEHI (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P2_STATS_CLEAR_VALUEHI_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */ +/* ================================================ STATS_CLEAR_VALUEHI_P3 ================================================= */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P3_STATS_CLEAR_VALUEHI_Pos (0UL) /*!< STATS_CLEAR_VALUEHI (Bit 0) */ + #define R_ETHSW_STATS_CLEAR_VALUEHI_P3_STATS_CLEAR_VALUEHI_Msk (0xffffffffUL) /*!< STATS_CLEAR_VALUEHI (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ADEFERRED_P0 ====================================================== */ + #define R_ETHSW_ADEFERRED_P0_DEFERCOUNT_Pos (0UL) /*!< DEFERCOUNT (Bit 0) */ + #define R_ETHSW_ADEFERRED_P0_DEFERCOUNT_Msk (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ADEFERRED_P1 ====================================================== */ + #define R_ETHSW_ADEFERRED_P1_DEFERCOUNT_Pos (0UL) /*!< DEFERCOUNT (Bit 0) */ + #define R_ETHSW_ADEFERRED_P1_DEFERCOUNT_Msk (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ADEFERRED_P2 ====================================================== */ + #define R_ETHSW_ADEFERRED_P2_DEFERCOUNT_Pos (0UL) /*!< DEFERCOUNT (Bit 0) */ + #define R_ETHSW_ADEFERRED_P2_DEFERCOUNT_Msk (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ADEFERRED_P3 ====================================================== */ + #define R_ETHSW_ADEFERRED_P3_DEFERCOUNT_Pos (0UL) /*!< DEFERCOUNT (Bit 0) */ + #define R_ETHSW_ADEFERRED_P3_DEFERCOUNT_Msk (0xffffffffUL) /*!< DEFERCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AMULTIPLECOLLISIONS_P0 ================================================= */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P0_COUNTAFTMLTCOLL_Pos (0UL) /*!< COUNTAFTMLTCOLL (Bit 0) */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P0_COUNTAFTMLTCOLL_Msk (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AMULTIPLECOLLISIONS_P1 ================================================= */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P1_COUNTAFTMLTCOLL_Pos (0UL) /*!< COUNTAFTMLTCOLL (Bit 0) */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P1_COUNTAFTMLTCOLL_Msk (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AMULTIPLECOLLISIONS_P2 ================================================= */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P2_COUNTAFTMLTCOLL_Pos (0UL) /*!< COUNTAFTMLTCOLL (Bit 0) */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P2_COUNTAFTMLTCOLL_Msk (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AMULTIPLECOLLISIONS_P3 ================================================= */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P3_COUNTAFTMLTCOLL_Pos (0UL) /*!< COUNTAFTMLTCOLL (Bit 0) */ + #define R_ETHSW_AMULTIPLECOLLISIONS_P3_COUNTAFTMLTCOLL_Msk (0xffffffffUL) /*!< COUNTAFTMLTCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ASINGLECOLLISIONS_P0 ================================================== */ + #define R_ETHSW_ASINGLECOLLISIONS_P0_COUNTAFTSNGLCOLL_Pos (0UL) /*!< COUNTAFTSNGLCOLL (Bit 0) */ + #define R_ETHSW_ASINGLECOLLISIONS_P0_COUNTAFTSNGLCOLL_Msk (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ASINGLECOLLISIONS_P1 ================================================== */ + #define R_ETHSW_ASINGLECOLLISIONS_P1_COUNTAFTSNGLCOLL_Pos (0UL) /*!< COUNTAFTSNGLCOLL (Bit 0) */ + #define R_ETHSW_ASINGLECOLLISIONS_P1_COUNTAFTSNGLCOLL_Msk (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ASINGLECOLLISIONS_P2 ================================================== */ + #define R_ETHSW_ASINGLECOLLISIONS_P2_COUNTAFTSNGLCOLL_Pos (0UL) /*!< COUNTAFTSNGLCOLL (Bit 0) */ + #define R_ETHSW_ASINGLECOLLISIONS_P2_COUNTAFTSNGLCOLL_Msk (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================= ASINGLECOLLISIONS_P3 ================================================== */ + #define R_ETHSW_ASINGLECOLLISIONS_P3_COUNTAFTSNGLCOLL_Pos (0UL) /*!< COUNTAFTSNGLCOLL (Bit 0) */ + #define R_ETHSW_ASINGLECOLLISIONS_P3_COUNTAFTSNGLCOLL_Msk (0xffffffffUL) /*!< COUNTAFTSNGLCOLL (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ALATECOLLISIONS_P0 =================================================== */ + #define R_ETHSW_ALATECOLLISIONS_P0_LATECOLLCOUNT_Pos (0UL) /*!< LATECOLLCOUNT (Bit 0) */ + #define R_ETHSW_ALATECOLLISIONS_P0_LATECOLLCOUNT_Msk (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ALATECOLLISIONS_P1 =================================================== */ + #define R_ETHSW_ALATECOLLISIONS_P1_LATECOLLCOUNT_Pos (0UL) /*!< LATECOLLCOUNT (Bit 0) */ + #define R_ETHSW_ALATECOLLISIONS_P1_LATECOLLCOUNT_Msk (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ALATECOLLISIONS_P2 =================================================== */ + #define R_ETHSW_ALATECOLLISIONS_P2_LATECOLLCOUNT_Pos (0UL) /*!< LATECOLLCOUNT (Bit 0) */ + #define R_ETHSW_ALATECOLLISIONS_P2_LATECOLLCOUNT_Msk (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================== ALATECOLLISIONS_P3 =================================================== */ + #define R_ETHSW_ALATECOLLISIONS_P3_LATECOLLCOUNT_Pos (0UL) /*!< LATECOLLCOUNT (Bit 0) */ + #define R_ETHSW_ALATECOLLISIONS_P3_LATECOLLCOUNT_Msk (0xffffffffUL) /*!< LATECOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AEXCESSIVECOLLISIONS_P0 ================================================ */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P0_EXCCOLLCOUNT_Pos (0UL) /*!< EXCCOLLCOUNT (Bit 0) */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P0_EXCCOLLCOUNT_Msk (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AEXCESSIVECOLLISIONS_P1 ================================================ */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P1_EXCCOLLCOUNT_Pos (0UL) /*!< EXCCOLLCOUNT (Bit 0) */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P1_EXCCOLLCOUNT_Msk (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AEXCESSIVECOLLISIONS_P2 ================================================ */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P2_EXCCOLLCOUNT_Pos (0UL) /*!< EXCCOLLCOUNT (Bit 0) */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P2_EXCCOLLCOUNT_Msk (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ AEXCESSIVECOLLISIONS_P3 ================================================ */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P3_EXCCOLLCOUNT_Pos (0UL) /*!< EXCCOLLCOUNT (Bit 0) */ + #define R_ETHSW_AEXCESSIVECOLLISIONS_P3_EXCCOLLCOUNT_Msk (0xffffffffUL) /*!< EXCCOLLCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ACARRIERSENSEERRORS_P0 ================================================= */ + #define R_ETHSW_ACARRIERSENSEERRORS_P0_CSERRCOUNT_Pos (0UL) /*!< CSERRCOUNT (Bit 0) */ + #define R_ETHSW_ACARRIERSENSEERRORS_P0_CSERRCOUNT_Msk (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ACARRIERSENSEERRORS_P1 ================================================= */ + #define R_ETHSW_ACARRIERSENSEERRORS_P1_CSERRCOUNT_Pos (0UL) /*!< CSERRCOUNT (Bit 0) */ + #define R_ETHSW_ACARRIERSENSEERRORS_P1_CSERRCOUNT_Msk (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ACARRIERSENSEERRORS_P2 ================================================= */ + #define R_ETHSW_ACARRIERSENSEERRORS_P2_CSERRCOUNT_Pos (0UL) /*!< CSERRCOUNT (Bit 0) */ + #define R_ETHSW_ACARRIERSENSEERRORS_P2_CSERRCOUNT_Msk (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ================================================ ACARRIERSENSEERRORS_P3 ================================================= */ + #define R_ETHSW_ACARRIERSENSEERRORS_P3_CSERRCOUNT_Pos (0UL) /*!< CSERRCOUNT (Bit 0) */ + #define R_ETHSW_ACARRIERSENSEERRORS_P3_CSERRCOUNT_Msk (0xffffffffUL) /*!< CSERRCOUNT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMACU0 ====================================================== */ + #define R_ETHSW_P0_QSTMACU0_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACU0_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P0_QSTMACU0_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P0_QSTMACU0_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSTMACU1 ====================================================== */ + #define R_ETHSW_P0_QSTMACU1_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACU1_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P0_QSTMACU1_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P0_QSTMACU1_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSTMACU2 ====================================================== */ + #define R_ETHSW_P0_QSTMACU2_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACU2_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P0_QSTMACU2_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P0_QSTMACU2_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSTMACU3 ====================================================== */ + #define R_ETHSW_P0_QSTMACU3_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACU3_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P0_QSTMACU3_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P0_QSTMACU3_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSTMACU4 ====================================================== */ + #define R_ETHSW_P0_QSTMACU4_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACU4_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P0_QSTMACU4_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P0_QSTMACU4_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSTMACU5 ====================================================== */ + #define R_ETHSW_P0_QSTMACU5_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACU5_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P0_QSTMACU5_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P0_QSTMACU5_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSTMACU6 ====================================================== */ + #define R_ETHSW_P0_QSTMACU6_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACU6_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P0_QSTMACU6_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P0_QSTMACU6_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSTMACU7 ====================================================== */ + #define R_ETHSW_P0_QSTMACU7_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACU7_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P0_QSTMACU7_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P0_QSTMACU7_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSTMACD0 ====================================================== */ + #define R_ETHSW_P0_QSTMACD0_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACD0_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMACD1 ====================================================== */ + #define R_ETHSW_P0_QSTMACD1_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACD1_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMACD2 ====================================================== */ + #define R_ETHSW_P0_QSTMACD2_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACD2_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMACD3 ====================================================== */ + #define R_ETHSW_P0_QSTMACD3_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACD3_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMACD4 ====================================================== */ + #define R_ETHSW_P0_QSTMACD4_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACD4_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMACD5 ====================================================== */ + #define R_ETHSW_P0_QSTMACD5_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACD5_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMACD6 ====================================================== */ + #define R_ETHSW_P0_QSTMACD6_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACD6_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMACD7 ====================================================== */ + #define R_ETHSW_P0_QSTMACD7_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P0_QSTMACD7_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMAMU0 ====================================================== */ + #define R_ETHSW_P0_QSTMAMU0_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMU0_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QSTMAMU1 ====================================================== */ + #define R_ETHSW_P0_QSTMAMU1_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMU1_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QSTMAMU2 ====================================================== */ + #define R_ETHSW_P0_QSTMAMU2_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMU2_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QSTMAMU3 ====================================================== */ + #define R_ETHSW_P0_QSTMAMU3_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMU3_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QSTMAMU4 ====================================================== */ + #define R_ETHSW_P0_QSTMAMU4_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMU4_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QSTMAMU5 ====================================================== */ + #define R_ETHSW_P0_QSTMAMU5_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMU5_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QSTMAMU6 ====================================================== */ + #define R_ETHSW_P0_QSTMAMU6_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMU6_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QSTMAMU7 ====================================================== */ + #define R_ETHSW_P0_QSTMAMU7_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMU7_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QSTMAMD0 ====================================================== */ + #define R_ETHSW_P0_QSTMAMD0_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMD0_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMAMD1 ====================================================== */ + #define R_ETHSW_P0_QSTMAMD1_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMD1_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMAMD2 ====================================================== */ + #define R_ETHSW_P0_QSTMAMD2_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMD2_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMAMD3 ====================================================== */ + #define R_ETHSW_P0_QSTMAMD3_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMD3_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMAMD4 ====================================================== */ + #define R_ETHSW_P0_QSTMAMD4_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMD4_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMAMD5 ====================================================== */ + #define R_ETHSW_P0_QSTMAMD5_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMD5_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMAMD6 ====================================================== */ + #define R_ETHSW_P0_QSTMAMD6_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMD6_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSTMAMD7 ====================================================== */ + #define R_ETHSW_P0_QSTMAMD7_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P0_QSTMAMD7_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P0_QSFTVL0 ======================================================= */ + #define R_ETHSW_P0_QSFTVL0_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P0_QSFTVL0_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVL0_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P0_QSFTVL0_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVL0_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P0_QSFTVL0_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTVL0_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P0_QSFTVL0_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P0_QSFTVL1 ======================================================= */ + #define R_ETHSW_P0_QSFTVL1_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P0_QSFTVL1_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVL1_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P0_QSFTVL1_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVL1_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P0_QSFTVL1_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTVL1_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P0_QSFTVL1_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P0_QSFTVL2 ======================================================= */ + #define R_ETHSW_P0_QSFTVL2_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P0_QSFTVL2_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVL2_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P0_QSFTVL2_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVL2_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P0_QSFTVL2_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTVL2_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P0_QSFTVL2_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P0_QSFTVL3 ======================================================= */ + #define R_ETHSW_P0_QSFTVL3_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P0_QSFTVL3_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVL3_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P0_QSFTVL3_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVL3_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P0_QSFTVL3_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTVL3_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P0_QSFTVL3_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P0_QSFTVL4 ======================================================= */ + #define R_ETHSW_P0_QSFTVL4_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P0_QSFTVL4_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVL4_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P0_QSFTVL4_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVL4_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P0_QSFTVL4_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTVL4_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P0_QSFTVL4_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P0_QSFTVL5 ======================================================= */ + #define R_ETHSW_P0_QSFTVL5_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P0_QSFTVL5_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVL5_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P0_QSFTVL5_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVL5_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P0_QSFTVL5_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTVL5_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P0_QSFTVL5_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P0_QSFTVL6 ======================================================= */ + #define R_ETHSW_P0_QSFTVL6_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P0_QSFTVL6_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVL6_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P0_QSFTVL6_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVL6_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P0_QSFTVL6_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTVL6_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P0_QSFTVL6_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P0_QSFTVL7 ======================================================= */ + #define R_ETHSW_P0_QSFTVL7_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P0_QSFTVL7_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVL7_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P0_QSFTVL7_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVL7_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P0_QSFTVL7_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTVL7_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P0_QSFTVL7_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P0_QSFTVLM0 ====================================================== */ + #define R_ETHSW_P0_QSFTVLM0_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P0_QSFTVLM0_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVLM0_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P0_QSFTVLM0_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVLM0_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P0_QSFTVLM0_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P0_QSFTVLM1 ====================================================== */ + #define R_ETHSW_P0_QSFTVLM1_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P0_QSFTVLM1_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVLM1_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P0_QSFTVLM1_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVLM1_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P0_QSFTVLM1_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P0_QSFTVLM2 ====================================================== */ + #define R_ETHSW_P0_QSFTVLM2_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P0_QSFTVLM2_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVLM2_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P0_QSFTVLM2_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVLM2_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P0_QSFTVLM2_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P0_QSFTVLM3 ====================================================== */ + #define R_ETHSW_P0_QSFTVLM3_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P0_QSFTVLM3_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVLM3_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P0_QSFTVLM3_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVLM3_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P0_QSFTVLM3_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P0_QSFTVLM4 ====================================================== */ + #define R_ETHSW_P0_QSFTVLM4_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P0_QSFTVLM4_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVLM4_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P0_QSFTVLM4_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVLM4_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P0_QSFTVLM4_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P0_QSFTVLM5 ====================================================== */ + #define R_ETHSW_P0_QSFTVLM5_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P0_QSFTVLM5_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVLM5_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P0_QSFTVLM5_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVLM5_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P0_QSFTVLM5_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P0_QSFTVLM6 ====================================================== */ + #define R_ETHSW_P0_QSFTVLM6_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P0_QSFTVLM6_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVLM6_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P0_QSFTVLM6_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVLM6_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P0_QSFTVLM6_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P0_QSFTVLM7 ====================================================== */ + #define R_ETHSW_P0_QSFTVLM7_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P0_QSFTVLM7_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_QSFTVLM7_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P0_QSFTVLM7_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTVLM7_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P0_QSFTVLM7_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P0_QSFTBL0 ======================================================= */ + #define R_ETHSW_P0_QSFTBL0_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P0_QSFTBL0_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL0_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P0_QSFTBL0_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL0_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P0_QSFTBL0_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL0_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P0_QSFTBL0_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL0_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P0_QSFTBL0_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL0_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P0_QSFTBL0_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P0_QSFTBL0_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P0_QSFTBL0_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL0_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P0_QSFTBL0_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSFTBL1 ======================================================= */ + #define R_ETHSW_P0_QSFTBL1_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P0_QSFTBL1_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL1_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P0_QSFTBL1_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL1_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P0_QSFTBL1_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL1_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P0_QSFTBL1_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL1_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P0_QSFTBL1_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL1_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P0_QSFTBL1_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P0_QSFTBL1_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P0_QSFTBL1_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL1_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P0_QSFTBL1_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSFTBL2 ======================================================= */ + #define R_ETHSW_P0_QSFTBL2_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P0_QSFTBL2_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL2_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P0_QSFTBL2_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL2_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P0_QSFTBL2_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL2_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P0_QSFTBL2_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL2_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P0_QSFTBL2_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL2_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P0_QSFTBL2_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P0_QSFTBL2_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P0_QSFTBL2_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL2_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P0_QSFTBL2_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSFTBL3 ======================================================= */ + #define R_ETHSW_P0_QSFTBL3_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P0_QSFTBL3_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL3_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P0_QSFTBL3_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL3_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P0_QSFTBL3_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL3_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P0_QSFTBL3_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL3_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P0_QSFTBL3_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL3_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P0_QSFTBL3_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P0_QSFTBL3_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P0_QSFTBL3_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL3_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P0_QSFTBL3_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSFTBL4 ======================================================= */ + #define R_ETHSW_P0_QSFTBL4_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P0_QSFTBL4_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL4_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P0_QSFTBL4_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL4_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P0_QSFTBL4_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL4_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P0_QSFTBL4_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL4_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P0_QSFTBL4_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL4_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P0_QSFTBL4_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P0_QSFTBL4_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P0_QSFTBL4_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL4_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P0_QSFTBL4_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSFTBL5 ======================================================= */ + #define R_ETHSW_P0_QSFTBL5_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P0_QSFTBL5_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL5_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P0_QSFTBL5_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL5_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P0_QSFTBL5_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL5_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P0_QSFTBL5_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL5_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P0_QSFTBL5_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL5_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P0_QSFTBL5_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P0_QSFTBL5_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P0_QSFTBL5_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL5_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P0_QSFTBL5_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSFTBL6 ======================================================= */ + #define R_ETHSW_P0_QSFTBL6_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P0_QSFTBL6_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL6_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P0_QSFTBL6_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL6_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P0_QSFTBL6_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL6_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P0_QSFTBL6_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL6_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P0_QSFTBL6_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL6_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P0_QSFTBL6_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P0_QSFTBL6_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P0_QSFTBL6_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL6_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P0_QSFTBL6_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QSFTBL7 ======================================================= */ + #define R_ETHSW_P0_QSFTBL7_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P0_QSFTBL7_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL7_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P0_QSFTBL7_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL7_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P0_QSFTBL7_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL7_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P0_QSFTBL7_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_QSFTBL7_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P0_QSFTBL7_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL7_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P0_QSFTBL7_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P0_QSFTBL7_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P0_QSFTBL7_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QSFTBL7_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P0_QSFTBL7_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ======================================================= P0_QSMFC0 ======================================================= */ + #define R_ETHSW_P0_QSMFC0_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P0_QSMFC0_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QSMFC1 ======================================================= */ + #define R_ETHSW_P0_QSMFC1_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P0_QSMFC1_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QSMFC2 ======================================================= */ + #define R_ETHSW_P0_QSMFC2_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P0_QSMFC2_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QSMFC3 ======================================================= */ + #define R_ETHSW_P0_QSMFC3_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P0_QSMFC3_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QSMFC4 ======================================================= */ + #define R_ETHSW_P0_QSMFC4_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P0_QSMFC4_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QSMFC5 ======================================================= */ + #define R_ETHSW_P0_QSMFC5_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P0_QSMFC5_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QSMFC6 ======================================================= */ + #define R_ETHSW_P0_QSMFC6_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P0_QSMFC6_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QSMFC7 ======================================================= */ + #define R_ETHSW_P0_QSMFC7_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P0_QSMFC7_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSPPC0 ======================================================= */ + #define R_ETHSW_P0_QMSPPC0_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P0_QMSPPC0_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSPPC1 ======================================================= */ + #define R_ETHSW_P0_QMSPPC1_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P0_QMSPPC1_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSPPC2 ======================================================= */ + #define R_ETHSW_P0_QMSPPC2_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P0_QMSPPC2_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSPPC3 ======================================================= */ + #define R_ETHSW_P0_QMSPPC3_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P0_QMSPPC3_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSPPC4 ======================================================= */ + #define R_ETHSW_P0_QMSPPC4_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P0_QMSPPC4_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSPPC5 ======================================================= */ + #define R_ETHSW_P0_QMSPPC5_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P0_QMSPPC5_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSPPC6 ======================================================= */ + #define R_ETHSW_P0_QMSPPC6_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P0_QMSPPC6_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSPPC7 ======================================================= */ + #define R_ETHSW_P0_QMSPPC7_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P0_QMSPPC7_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSRPC0 ======================================================= */ + #define R_ETHSW_P0_QMSRPC0_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P0_QMSRPC0_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSRPC1 ======================================================= */ + #define R_ETHSW_P0_QMSRPC1_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P0_QMSRPC1_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSRPC2 ======================================================= */ + #define R_ETHSW_P0_QMSRPC2_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P0_QMSRPC2_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSRPC3 ======================================================= */ + #define R_ETHSW_P0_QMSRPC3_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P0_QMSRPC3_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSRPC4 ======================================================= */ + #define R_ETHSW_P0_QMSRPC4_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P0_QMSRPC4_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSRPC5 ======================================================= */ + #define R_ETHSW_P0_QMSRPC5_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P0_QMSRPC5_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSRPC6 ======================================================= */ + #define R_ETHSW_P0_QMSRPC6_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P0_QMSRPC6_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P0_QMSRPC7 ======================================================= */ + #define R_ETHSW_P0_QMSRPC7_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P0_QMSRPC7_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QSEIS ======================================================== */ + #define R_ETHSW_P0_QSEIS_QSMOIS_Pos (0UL) /*!< QSMOIS (Bit 0) */ + #define R_ETHSW_P0_QSEIS_QSMOIS_Msk (0xffUL) /*!< QSMOIS (Bitfield-Mask: 0xff) */ +/* ======================================================= P1_QSEIS ======================================================== */ + #define R_ETHSW_P1_QSEIS_QSMOIS_Pos (0UL) /*!< QSMOIS (Bit 0) */ + #define R_ETHSW_P1_QSEIS_QSMOIS_Msk (0xffUL) /*!< QSMOIS (Bitfield-Mask: 0xff) */ +/* ======================================================= P2_QSEIS ======================================================== */ + #define R_ETHSW_P2_QSEIS_QSMOIS_Pos (0UL) /*!< QSMOIS (Bit 0) */ + #define R_ETHSW_P2_QSEIS_QSMOIS_Msk (0xffUL) /*!< QSMOIS (Bitfield-Mask: 0xff) */ +/* ======================================================= P0_QSEIE ======================================================== */ + #define R_ETHSW_P0_QSEIE_QSMOIE_Pos (0UL) /*!< QSMOIE (Bit 0) */ + #define R_ETHSW_P0_QSEIE_QSMOIE_Msk (0xffUL) /*!< QSMOIE (Bitfield-Mask: 0xff) */ +/* ======================================================= P1_QSEIE ======================================================== */ + #define R_ETHSW_P1_QSEIE_QSMOIE_Pos (0UL) /*!< QSMOIE (Bit 0) */ + #define R_ETHSW_P1_QSEIE_QSMOIE_Msk (0xffUL) /*!< QSMOIE (Bitfield-Mask: 0xff) */ +/* ======================================================= P2_QSEIE ======================================================== */ + #define R_ETHSW_P2_QSEIE_QSMOIE_Pos (0UL) /*!< QSMOIE (Bit 0) */ + #define R_ETHSW_P2_QSEIE_QSMOIE_Msk (0xffUL) /*!< QSMOIE (Bitfield-Mask: 0xff) */ +/* ======================================================= P0_QSEID ======================================================== */ + #define R_ETHSW_P0_QSEID_QSMOID_Pos (0UL) /*!< QSMOID (Bit 0) */ + #define R_ETHSW_P0_QSEID_QSMOID_Msk (0xffUL) /*!< QSMOID (Bitfield-Mask: 0xff) */ +/* ======================================================= P1_QSEID ======================================================== */ + #define R_ETHSW_P1_QSEID_QSMOID_Pos (0UL) /*!< QSMOID (Bit 0) */ + #define R_ETHSW_P1_QSEID_QSMOID_Msk (0xffUL) /*!< QSMOID (Bitfield-Mask: 0xff) */ +/* ======================================================= P2_QSEID ======================================================== */ + #define R_ETHSW_P2_QSEID_QSMOID_Pos (0UL) /*!< QSMOID (Bit 0) */ + #define R_ETHSW_P2_QSEID_QSMOID_Msk (0xffUL) /*!< QSMOID (Bitfield-Mask: 0xff) */ +/* ======================================================= P0_QGMOD ======================================================== */ + #define R_ETHSW_P0_QGMOD_QGMOD_Pos (0UL) /*!< QGMOD (Bit 0) */ + #define R_ETHSW_P0_QGMOD_QGMOD_Msk (0xffUL) /*!< QGMOD (Bitfield-Mask: 0xff) */ +/* ======================================================= P1_QGMOD ======================================================== */ + #define R_ETHSW_P1_QGMOD_QGMOD_Pos (0UL) /*!< QGMOD (Bit 0) */ + #define R_ETHSW_P1_QGMOD_QGMOD_Msk (0xffUL) /*!< QGMOD (Bitfield-Mask: 0xff) */ +/* ======================================================= P2_QGMOD ======================================================== */ + #define R_ETHSW_P2_QGMOD_QGMOD_Pos (0UL) /*!< QGMOD (Bit 0) */ + #define R_ETHSW_P2_QGMOD_QGMOD_Msk (0xffUL) /*!< QGMOD (Bitfield-Mask: 0xff) */ +/* ======================================================= P0_QGPPC ======================================================== */ + #define R_ETHSW_P0_QGPPC_QGPPC_Pos (0UL) /*!< QGPPC (Bit 0) */ + #define R_ETHSW_P0_QGPPC_QGPPC_Msk (0xffffUL) /*!< QGPPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QGPPC ======================================================== */ + #define R_ETHSW_P1_QGPPC_QGPPC_Pos (0UL) /*!< QGPPC (Bit 0) */ + #define R_ETHSW_P1_QGPPC_QGPPC_Msk (0xffffUL) /*!< QGPPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QGPPC ======================================================== */ + #define R_ETHSW_P2_QGPPC_QGPPC_Pos (0UL) /*!< QGPPC (Bit 0) */ + #define R_ETHSW_P2_QGPPC_QGPPC_Msk (0xffffUL) /*!< QGPPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QGDPC0 ======================================================= */ + #define R_ETHSW_P0_QGDPC0_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P0_QGDPC0_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QGDPC1 ======================================================= */ + #define R_ETHSW_P0_QGDPC1_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P0_QGDPC1_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QGDPC2 ======================================================= */ + #define R_ETHSW_P0_QGDPC2_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P0_QGDPC2_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QGDPC3 ======================================================= */ + #define R_ETHSW_P0_QGDPC3_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P0_QGDPC3_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QGDPC4 ======================================================= */ + #define R_ETHSW_P0_QGDPC4_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P0_QGDPC4_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QGDPC5 ======================================================= */ + #define R_ETHSW_P0_QGDPC5_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P0_QGDPC5_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QGDPC6 ======================================================= */ + #define R_ETHSW_P0_QGDPC6_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P0_QGDPC6_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QGDPC7 ======================================================= */ + #define R_ETHSW_P0_QGDPC7_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P0_QGDPC7_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QGEIS ======================================================== */ + #define R_ETHSW_P0_QGEIS_QGMOIS_Pos (0UL) /*!< QGMOIS (Bit 0) */ + #define R_ETHSW_P0_QGEIS_QGMOIS_Msk (0xffUL) /*!< QGMOIS (Bitfield-Mask: 0xff) */ +/* ======================================================= P1_QGEIS ======================================================== */ + #define R_ETHSW_P1_QGEIS_QGMOIS_Pos (0UL) /*!< QGMOIS (Bit 0) */ + #define R_ETHSW_P1_QGEIS_QGMOIS_Msk (0xffUL) /*!< QGMOIS (Bitfield-Mask: 0xff) */ +/* ======================================================= P2_QGEIS ======================================================== */ + #define R_ETHSW_P2_QGEIS_QGMOIS_Pos (0UL) /*!< QGMOIS (Bit 0) */ + #define R_ETHSW_P2_QGEIS_QGMOIS_Msk (0xffUL) /*!< QGMOIS (Bitfield-Mask: 0xff) */ +/* ======================================================= P0_QGEIE ======================================================== */ + #define R_ETHSW_P0_QGEIE_QGMOIE_Pos (0UL) /*!< QGMOIE (Bit 0) */ + #define R_ETHSW_P0_QGEIE_QGMOIE_Msk (0xffUL) /*!< QGMOIE (Bitfield-Mask: 0xff) */ +/* ======================================================= P1_QGEIE ======================================================== */ + #define R_ETHSW_P1_QGEIE_QGMOIE_Pos (0UL) /*!< QGMOIE (Bit 0) */ + #define R_ETHSW_P1_QGEIE_QGMOIE_Msk (0xffUL) /*!< QGMOIE (Bitfield-Mask: 0xff) */ +/* ======================================================= P2_QGEIE ======================================================== */ + #define R_ETHSW_P2_QGEIE_QGMOIE_Pos (0UL) /*!< QGMOIE (Bit 0) */ + #define R_ETHSW_P2_QGEIE_QGMOIE_Msk (0xffUL) /*!< QGMOIE (Bitfield-Mask: 0xff) */ +/* ======================================================= P0_QGEID ======================================================== */ + #define R_ETHSW_P0_QGEID_QGMOID_Pos (0UL) /*!< QGMOID (Bit 0) */ + #define R_ETHSW_P0_QGEID_QGMOID_Msk (0xffUL) /*!< QGMOID (Bitfield-Mask: 0xff) */ +/* ======================================================= P1_QGEID ======================================================== */ + #define R_ETHSW_P1_QGEID_QGMOID_Pos (0UL) /*!< QGMOID (Bit 0) */ + #define R_ETHSW_P1_QGEID_QGMOID_Msk (0xffUL) /*!< QGMOID (Bitfield-Mask: 0xff) */ +/* ======================================================= P2_QGEID ======================================================== */ + #define R_ETHSW_P2_QGEID_QGMOID_Pos (0UL) /*!< QGMOID (Bit 0) */ + #define R_ETHSW_P2_QGEID_QGMOID_Msk (0xffUL) /*!< QGMOID (Bitfield-Mask: 0xff) */ +/* ====================================================== P0_QMDESC0 ======================================================= */ + #define R_ETHSW_P0_QMDESC0_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P0_QMDESC0_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC0_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P0_QMDESC0_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC0_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P0_QMDESC0_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QMDESC1 ======================================================= */ + #define R_ETHSW_P0_QMDESC1_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P0_QMDESC1_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC1_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P0_QMDESC1_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC1_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P0_QMDESC1_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QMDESC2 ======================================================= */ + #define R_ETHSW_P0_QMDESC2_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P0_QMDESC2_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC2_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P0_QMDESC2_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC2_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P0_QMDESC2_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QMDESC3 ======================================================= */ + #define R_ETHSW_P0_QMDESC3_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P0_QMDESC3_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC3_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P0_QMDESC3_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC3_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P0_QMDESC3_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QMDESC4 ======================================================= */ + #define R_ETHSW_P0_QMDESC4_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P0_QMDESC4_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC4_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P0_QMDESC4_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC4_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P0_QMDESC4_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QMDESC5 ======================================================= */ + #define R_ETHSW_P0_QMDESC5_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P0_QMDESC5_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC5_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P0_QMDESC5_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC5_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P0_QMDESC5_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QMDESC6 ======================================================= */ + #define R_ETHSW_P0_QMDESC6_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P0_QMDESC6_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC6_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P0_QMDESC6_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC6_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P0_QMDESC6_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QMDESC7 ======================================================= */ + #define R_ETHSW_P0_QMDESC7_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P0_QMDESC7_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC7_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P0_QMDESC7_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_QMDESC7_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P0_QMDESC7_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P0_QMCBSC0 ======================================================= */ + #define R_ETHSW_P0_QMCBSC0_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P0_QMCBSC0_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P0_QMCBSC1 ======================================================= */ + #define R_ETHSW_P0_QMCBSC1_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P0_QMCBSC1_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P0_QMCBSC2 ======================================================= */ + #define R_ETHSW_P0_QMCBSC2_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P0_QMCBSC2_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P0_QMCBSC3 ======================================================= */ + #define R_ETHSW_P0_QMCBSC3_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P0_QMCBSC3_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P0_QMCBSC4 ======================================================= */ + #define R_ETHSW_P0_QMCBSC4_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P0_QMCBSC4_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P0_QMCBSC5 ======================================================= */ + #define R_ETHSW_P0_QMCBSC5_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P0_QMCBSC5_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P0_QMCBSC6 ======================================================= */ + #define R_ETHSW_P0_QMCBSC6_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P0_QMCBSC6_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P0_QMCBSC7 ======================================================= */ + #define R_ETHSW_P0_QMCBSC7_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P0_QMCBSC7_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P0_QMCIRC0 ======================================================= */ + #define R_ETHSW_P0_QMCIRC0_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P0_QMCIRC0_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P0_QMCIRC1 ======================================================= */ + #define R_ETHSW_P0_QMCIRC1_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P0_QMCIRC1_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P0_QMCIRC2 ======================================================= */ + #define R_ETHSW_P0_QMCIRC2_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P0_QMCIRC2_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P0_QMCIRC3 ======================================================= */ + #define R_ETHSW_P0_QMCIRC3_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P0_QMCIRC3_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P0_QMCIRC4 ======================================================= */ + #define R_ETHSW_P0_QMCIRC4_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P0_QMCIRC4_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P0_QMCIRC5 ======================================================= */ + #define R_ETHSW_P0_QMCIRC5_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P0_QMCIRC5_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P0_QMCIRC6 ======================================================= */ + #define R_ETHSW_P0_QMCIRC6_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P0_QMCIRC6_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P0_QMCIRC7 ======================================================= */ + #define R_ETHSW_P0_QMCIRC7_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P0_QMCIRC7_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= P0_QMGPC0 ======================================================= */ + #define R_ETHSW_P0_QMGPC0_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P0_QMGPC0_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMGPC1 ======================================================= */ + #define R_ETHSW_P0_QMGPC1_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P0_QMGPC1_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMGPC2 ======================================================= */ + #define R_ETHSW_P0_QMGPC2_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P0_QMGPC2_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMGPC3 ======================================================= */ + #define R_ETHSW_P0_QMGPC3_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P0_QMGPC3_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMGPC4 ======================================================= */ + #define R_ETHSW_P0_QMGPC4_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P0_QMGPC4_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMGPC5 ======================================================= */ + #define R_ETHSW_P0_QMGPC5_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P0_QMGPC5_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMGPC6 ======================================================= */ + #define R_ETHSW_P0_QMGPC6_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P0_QMGPC6_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMGPC7 ======================================================= */ + #define R_ETHSW_P0_QMGPC7_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P0_QMGPC7_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMRPC0 ======================================================= */ + #define R_ETHSW_P0_QMRPC0_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P0_QMRPC0_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMRPC1 ======================================================= */ + #define R_ETHSW_P0_QMRPC1_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P0_QMRPC1_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMRPC2 ======================================================= */ + #define R_ETHSW_P0_QMRPC2_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P0_QMRPC2_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMRPC3 ======================================================= */ + #define R_ETHSW_P0_QMRPC3_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P0_QMRPC3_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMRPC4 ======================================================= */ + #define R_ETHSW_P0_QMRPC4_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P0_QMRPC4_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMRPC5 ======================================================= */ + #define R_ETHSW_P0_QMRPC5_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P0_QMRPC5_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMRPC6 ======================================================= */ + #define R_ETHSW_P0_QMRPC6_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P0_QMRPC6_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P0_QMRPC7 ======================================================= */ + #define R_ETHSW_P0_QMRPC7_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P0_QMRPC7_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================== P0_QMEC ======================================================== */ + #define R_ETHSW_P0_QMEC_ME_Pos (0UL) /*!< ME (Bit 0) */ + #define R_ETHSW_P0_QMEC_ME_Msk (0xffUL) /*!< ME (Bitfield-Mask: 0xff) */ +/* ======================================================== P1_QMEC ======================================================== */ + #define R_ETHSW_P1_QMEC_ME_Pos (0UL) /*!< ME (Bit 0) */ + #define R_ETHSW_P1_QMEC_ME_Msk (0xffUL) /*!< ME (Bitfield-Mask: 0xff) */ +/* ======================================================== P2_QMEC ======================================================== */ + #define R_ETHSW_P2_QMEC_ME_Pos (0UL) /*!< ME (Bit 0) */ + #define R_ETHSW_P2_QMEC_ME_Msk (0xffUL) /*!< ME (Bitfield-Mask: 0xff) */ +/* ======================================================= P0_QMEIS ======================================================== */ + #define R_ETHSW_P0_QMEIS_QRFIS_Pos (0UL) /*!< QRFIS (Bit 0) */ + #define R_ETHSW_P0_QMEIS_QRFIS_Msk (0xffUL) /*!< QRFIS (Bitfield-Mask: 0xff) */ +/* ======================================================= P1_QMEIS ======================================================== */ + #define R_ETHSW_P1_QMEIS_QRFIS_Pos (0UL) /*!< QRFIS (Bit 0) */ + #define R_ETHSW_P1_QMEIS_QRFIS_Msk (0xffUL) /*!< QRFIS (Bitfield-Mask: 0xff) */ +/* ======================================================= P2_QMEIS ======================================================== */ + #define R_ETHSW_P2_QMEIS_QRFIS_Pos (0UL) /*!< QRFIS (Bit 0) */ + #define R_ETHSW_P2_QMEIS_QRFIS_Msk (0xffUL) /*!< QRFIS (Bitfield-Mask: 0xff) */ +/* ======================================================= P0_QMEIE ======================================================== */ + #define R_ETHSW_P0_QMEIE_QRFIE_Pos (0UL) /*!< QRFIE (Bit 0) */ + #define R_ETHSW_P0_QMEIE_QRFIE_Msk (0xffUL) /*!< QRFIE (Bitfield-Mask: 0xff) */ +/* ======================================================= P1_QMEIE ======================================================== */ + #define R_ETHSW_P1_QMEIE_QRFIE_Pos (0UL) /*!< QRFIE (Bit 0) */ + #define R_ETHSW_P1_QMEIE_QRFIE_Msk (0xffUL) /*!< QRFIE (Bitfield-Mask: 0xff) */ +/* ======================================================= P2_QMEIE ======================================================== */ + #define R_ETHSW_P2_QMEIE_QRFIE_Pos (0UL) /*!< QRFIE (Bit 0) */ + #define R_ETHSW_P2_QMEIE_QRFIE_Msk (0xffUL) /*!< QRFIE (Bitfield-Mask: 0xff) */ +/* ======================================================= P0_QMEID ======================================================== */ + #define R_ETHSW_P0_QMEID_QRFID_Pos (0UL) /*!< QRFID (Bit 0) */ + #define R_ETHSW_P0_QMEID_QRFID_Msk (0xffUL) /*!< QRFID (Bitfield-Mask: 0xff) */ +/* ======================================================= P1_QMEID ======================================================== */ + #define R_ETHSW_P1_QMEID_QRFID_Pos (0UL) /*!< QRFID (Bit 0) */ + #define R_ETHSW_P1_QMEID_QRFID_Msk (0xffUL) /*!< QRFID (Bitfield-Mask: 0xff) */ +/* ======================================================= P2_QMEID ======================================================== */ + #define R_ETHSW_P2_QMEID_QRFID_Pos (0UL) /*!< QRFID (Bit 0) */ + #define R_ETHSW_P2_QMEID_QRFID_Msk (0xffUL) /*!< QRFID (Bitfield-Mask: 0xff) */ +/* ===================================================== P0_PCP_REMAP ====================================================== */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP0_Pos (0UL) /*!< PCP_REMAP0 (Bit 0) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP0_Msk (0x7UL) /*!< PCP_REMAP0 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP1_Pos (3UL) /*!< PCP_REMAP1 (Bit 3) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP1_Msk (0x38UL) /*!< PCP_REMAP1 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP2_Pos (6UL) /*!< PCP_REMAP2 (Bit 6) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP2_Msk (0x1c0UL) /*!< PCP_REMAP2 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP3_Pos (9UL) /*!< PCP_REMAP3 (Bit 9) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP3_Msk (0xe00UL) /*!< PCP_REMAP3 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP4_Pos (12UL) /*!< PCP_REMAP4 (Bit 12) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP4_Msk (0x7000UL) /*!< PCP_REMAP4 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP5_Pos (15UL) /*!< PCP_REMAP5 (Bit 15) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP5_Msk (0x38000UL) /*!< PCP_REMAP5 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP6_Pos (18UL) /*!< PCP_REMAP6 (Bit 18) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP6_Msk (0x1c0000UL) /*!< PCP_REMAP6 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP7_Pos (21UL) /*!< PCP_REMAP7 (Bit 21) */ + #define R_ETHSW_P0_PCP_REMAP_PCP_REMAP7_Msk (0xe00000UL) /*!< PCP_REMAP7 (Bitfield-Mask: 0x07) */ +/* ===================================================== P1_PCP_REMAP ====================================================== */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP0_Pos (0UL) /*!< PCP_REMAP0 (Bit 0) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP0_Msk (0x7UL) /*!< PCP_REMAP0 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP1_Pos (3UL) /*!< PCP_REMAP1 (Bit 3) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP1_Msk (0x38UL) /*!< PCP_REMAP1 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP2_Pos (6UL) /*!< PCP_REMAP2 (Bit 6) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP2_Msk (0x1c0UL) /*!< PCP_REMAP2 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP3_Pos (9UL) /*!< PCP_REMAP3 (Bit 9) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP3_Msk (0xe00UL) /*!< PCP_REMAP3 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP4_Pos (12UL) /*!< PCP_REMAP4 (Bit 12) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP4_Msk (0x7000UL) /*!< PCP_REMAP4 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP5_Pos (15UL) /*!< PCP_REMAP5 (Bit 15) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP5_Msk (0x38000UL) /*!< PCP_REMAP5 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP6_Pos (18UL) /*!< PCP_REMAP6 (Bit 18) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP6_Msk (0x1c0000UL) /*!< PCP_REMAP6 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP7_Pos (21UL) /*!< PCP_REMAP7 (Bit 21) */ + #define R_ETHSW_P1_PCP_REMAP_PCP_REMAP7_Msk (0xe00000UL) /*!< PCP_REMAP7 (Bitfield-Mask: 0x07) */ +/* ===================================================== P2_PCP_REMAP ====================================================== */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP0_Pos (0UL) /*!< PCP_REMAP0 (Bit 0) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP0_Msk (0x7UL) /*!< PCP_REMAP0 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP1_Pos (3UL) /*!< PCP_REMAP1 (Bit 3) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP1_Msk (0x38UL) /*!< PCP_REMAP1 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP2_Pos (6UL) /*!< PCP_REMAP2 (Bit 6) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP2_Msk (0x1c0UL) /*!< PCP_REMAP2 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP3_Pos (9UL) /*!< PCP_REMAP3 (Bit 9) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP3_Msk (0xe00UL) /*!< PCP_REMAP3 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP4_Pos (12UL) /*!< PCP_REMAP4 (Bit 12) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP4_Msk (0x7000UL) /*!< PCP_REMAP4 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP5_Pos (15UL) /*!< PCP_REMAP5 (Bit 15) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP5_Msk (0x38000UL) /*!< PCP_REMAP5 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP6_Pos (18UL) /*!< PCP_REMAP6 (Bit 18) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP6_Msk (0x1c0000UL) /*!< PCP_REMAP6 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP7_Pos (21UL) /*!< PCP_REMAP7 (Bit 21) */ + #define R_ETHSW_P2_PCP_REMAP_PCP_REMAP7_Msk (0xe00000UL) /*!< PCP_REMAP7 (Bitfield-Mask: 0x07) */ +/* ====================================================== P0_VLAN_TAG ====================================================== */ + #define R_ETHSW_P0_VLAN_TAG_VID_Pos (0UL) /*!< VID (Bit 0) */ + #define R_ETHSW_P0_VLAN_TAG_VID_Msk (0xfffUL) /*!< VID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P0_VLAN_TAG_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P0_VLAN_TAG_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_VLAN_TAG_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P0_VLAN_TAG_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P0_VLAN_TAG_TPID_Pos (16UL) /*!< TPID (Bit 16) */ + #define R_ETHSW_P0_VLAN_TAG_TPID_Msk (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_VLAN_TAG ====================================================== */ + #define R_ETHSW_P1_VLAN_TAG_VID_Pos (0UL) /*!< VID (Bit 0) */ + #define R_ETHSW_P1_VLAN_TAG_VID_Msk (0xfffUL) /*!< VID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_VLAN_TAG_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P1_VLAN_TAG_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_VLAN_TAG_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P1_VLAN_TAG_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_VLAN_TAG_TPID_Pos (16UL) /*!< TPID (Bit 16) */ + #define R_ETHSW_P1_VLAN_TAG_TPID_Msk (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_VLAN_TAG ====================================================== */ + #define R_ETHSW_P2_VLAN_TAG_VID_Pos (0UL) /*!< VID (Bit 0) */ + #define R_ETHSW_P2_VLAN_TAG_VID_Msk (0xfffUL) /*!< VID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_VLAN_TAG_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P2_VLAN_TAG_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_VLAN_TAG_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P2_VLAN_TAG_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_VLAN_TAG_TPID_Pos (16UL) /*!< TPID (Bit 16) */ + #define R_ETHSW_P2_VLAN_TAG_TPID_Msk (0xffff0000UL) /*!< TPID (Bitfield-Mask: 0xffff) */ +/* ===================================================== P0_VLAN_MODE ====================================================== */ + #define R_ETHSW_P0_VLAN_MODE_VITM_Pos (0UL) /*!< VITM (Bit 0) */ + #define R_ETHSW_P0_VLAN_MODE_VITM_Msk (0x3UL) /*!< VITM (Bitfield-Mask: 0x03) */ + #define R_ETHSW_P0_VLAN_MODE_VICM_Pos (2UL) /*!< VICM (Bit 2) */ + #define R_ETHSW_P0_VLAN_MODE_VICM_Msk (0xcUL) /*!< VICM (Bitfield-Mask: 0x03) */ +/* ===================================================== P1_VLAN_MODE ====================================================== */ + #define R_ETHSW_P1_VLAN_MODE_VITM_Pos (0UL) /*!< VITM (Bit 0) */ + #define R_ETHSW_P1_VLAN_MODE_VITM_Msk (0x3UL) /*!< VITM (Bitfield-Mask: 0x03) */ + #define R_ETHSW_P1_VLAN_MODE_VICM_Pos (2UL) /*!< VICM (Bit 2) */ + #define R_ETHSW_P1_VLAN_MODE_VICM_Msk (0xcUL) /*!< VICM (Bitfield-Mask: 0x03) */ +/* ===================================================== P2_VLAN_MODE ====================================================== */ + #define R_ETHSW_P2_VLAN_MODE_VITM_Pos (0UL) /*!< VITM (Bit 0) */ + #define R_ETHSW_P2_VLAN_MODE_VITM_Msk (0x3UL) /*!< VITM (Bitfield-Mask: 0x03) */ + #define R_ETHSW_P2_VLAN_MODE_VICM_Pos (2UL) /*!< VICM (Bit 2) */ + #define R_ETHSW_P2_VLAN_MODE_VICM_Msk (0xcUL) /*!< VICM (Bitfield-Mask: 0x03) */ +/* ==================================================== P0_VIC_DROP_CNT ==================================================== */ + #define R_ETHSW_P0_VIC_DROP_CNT_VIC_DROP_CNT_Pos (0UL) /*!< VIC_DROP_CNT (Bit 0) */ + #define R_ETHSW_P0_VIC_DROP_CNT_VIC_DROP_CNT_Msk (0xffffUL) /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== P1_VIC_DROP_CNT ==================================================== */ + #define R_ETHSW_P1_VIC_DROP_CNT_VIC_DROP_CNT_Pos (0UL) /*!< VIC_DROP_CNT (Bit 0) */ + #define R_ETHSW_P1_VIC_DROP_CNT_VIC_DROP_CNT_Msk (0xffffUL) /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== P2_VIC_DROP_CNT ==================================================== */ + #define R_ETHSW_P2_VIC_DROP_CNT_VIC_DROP_CNT_Pos (0UL) /*!< VIC_DROP_CNT (Bit 0) */ + #define R_ETHSW_P2_VIC_DROP_CNT_VIC_DROP_CNT_Msk (0xffffUL) /*!< VIC_DROP_CNT (Bitfield-Mask: 0xffff) */ +/* =================================================== P0_LOOKUP_HIT_CNT =================================================== */ + #define R_ETHSW_P0_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos (0UL) /*!< LOOKUP_HIT_CNT (Bit 0) */ + #define R_ETHSW_P0_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk (0xffffffUL) /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff) */ +/* =================================================== P1_LOOKUP_HIT_CNT =================================================== */ + #define R_ETHSW_P1_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos (0UL) /*!< LOOKUP_HIT_CNT (Bit 0) */ + #define R_ETHSW_P1_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk (0xffffffUL) /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff) */ +/* =================================================== P2_LOOKUP_HIT_CNT =================================================== */ + #define R_ETHSW_P2_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Pos (0UL) /*!< LOOKUP_HIT_CNT (Bit 0) */ + #define R_ETHSW_P2_LOOKUP_HIT_CNT_LOOKUP_HIT_CNT_Msk (0xffffffUL) /*!< LOOKUP_HIT_CNT (Bitfield-Mask: 0xffffff) */ +/* ==================================================== P0_ERROR_STATUS ==================================================== */ + #define R_ETHSW_P0_ERROR_STATUS_SOPERR_Pos (0UL) /*!< SOPERR (Bit 0) */ + #define R_ETHSW_P0_ERROR_STATUS_SOPERR_Msk (0x1UL) /*!< SOPERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_ERROR_STATUS_PUNDSZ_Pos (1UL) /*!< PUNDSZ (Bit 1) */ + #define R_ETHSW_P0_ERROR_STATUS_PUNDSZ_Msk (0x2UL) /*!< PUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_ERROR_STATUS_POVRSZ_Pos (2UL) /*!< POVRSZ (Bit 2) */ + #define R_ETHSW_P0_ERROR_STATUS_POVRSZ_Msk (0x4UL) /*!< POVRSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_ERROR_STATUS_EUNDSZ_Pos (3UL) /*!< EUNDSZ (Bit 3) */ + #define R_ETHSW_P0_ERROR_STATUS_EUNDSZ_Msk (0x8UL) /*!< EUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_ERROR_STATUS_EOVRSZ_Pos (4UL) /*!< EOVRSZ (Bit 4) */ + #define R_ETHSW_P0_ERROR_STATUS_EOVRSZ_Msk (0x10UL) /*!< EOVRSZ (Bitfield-Mask: 0x01) */ +/* ==================================================== P1_ERROR_STATUS ==================================================== */ + #define R_ETHSW_P1_ERROR_STATUS_SOPERR_Pos (0UL) /*!< SOPERR (Bit 0) */ + #define R_ETHSW_P1_ERROR_STATUS_SOPERR_Msk (0x1UL) /*!< SOPERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_ERROR_STATUS_PUNDSZ_Pos (1UL) /*!< PUNDSZ (Bit 1) */ + #define R_ETHSW_P1_ERROR_STATUS_PUNDSZ_Msk (0x2UL) /*!< PUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_ERROR_STATUS_POVRSZ_Pos (2UL) /*!< POVRSZ (Bit 2) */ + #define R_ETHSW_P1_ERROR_STATUS_POVRSZ_Msk (0x4UL) /*!< POVRSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_ERROR_STATUS_EUNDSZ_Pos (3UL) /*!< EUNDSZ (Bit 3) */ + #define R_ETHSW_P1_ERROR_STATUS_EUNDSZ_Msk (0x8UL) /*!< EUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_ERROR_STATUS_EOVRSZ_Pos (4UL) /*!< EOVRSZ (Bit 4) */ + #define R_ETHSW_P1_ERROR_STATUS_EOVRSZ_Msk (0x10UL) /*!< EOVRSZ (Bitfield-Mask: 0x01) */ +/* ==================================================== P2_ERROR_STATUS ==================================================== */ + #define R_ETHSW_P2_ERROR_STATUS_SOPERR_Pos (0UL) /*!< SOPERR (Bit 0) */ + #define R_ETHSW_P2_ERROR_STATUS_SOPERR_Msk (0x1UL) /*!< SOPERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_ERROR_STATUS_PUNDSZ_Pos (1UL) /*!< PUNDSZ (Bit 1) */ + #define R_ETHSW_P2_ERROR_STATUS_PUNDSZ_Msk (0x2UL) /*!< PUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_ERROR_STATUS_POVRSZ_Pos (2UL) /*!< POVRSZ (Bit 2) */ + #define R_ETHSW_P2_ERROR_STATUS_POVRSZ_Msk (0x4UL) /*!< POVRSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_ERROR_STATUS_EUNDSZ_Pos (3UL) /*!< EUNDSZ (Bit 3) */ + #define R_ETHSW_P2_ERROR_STATUS_EUNDSZ_Msk (0x8UL) /*!< EUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_ERROR_STATUS_EOVRSZ_Pos (4UL) /*!< EOVRSZ (Bit 4) */ + #define R_ETHSW_P2_ERROR_STATUS_EOVRSZ_Msk (0x10UL) /*!< EOVRSZ (Bitfield-Mask: 0x01) */ +/* ===================================================== P0_ERROR_MASK ===================================================== */ + #define R_ETHSW_P0_ERROR_MASK_MSOPERR_Pos (0UL) /*!< MSOPERR (Bit 0) */ + #define R_ETHSW_P0_ERROR_MASK_MSOPERR_Msk (0x1UL) /*!< MSOPERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_ERROR_MASK_MPUNDSZ_Pos (1UL) /*!< MPUNDSZ (Bit 1) */ + #define R_ETHSW_P0_ERROR_MASK_MPUNDSZ_Msk (0x2UL) /*!< MPUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_ERROR_MASK_MPOVRSZ_Pos (2UL) /*!< MPOVRSZ (Bit 2) */ + #define R_ETHSW_P0_ERROR_MASK_MPOVRSZ_Msk (0x4UL) /*!< MPOVRSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_ERROR_MASK_MEUNDSZ_Pos (3UL) /*!< MEUNDSZ (Bit 3) */ + #define R_ETHSW_P0_ERROR_MASK_MEUNDSZ_Msk (0x8UL) /*!< MEUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P0_ERROR_MASK_MEOVRSZ_Pos (4UL) /*!< MEOVRSZ (Bit 4) */ + #define R_ETHSW_P0_ERROR_MASK_MEOVRSZ_Msk (0x10UL) /*!< MEOVRSZ (Bitfield-Mask: 0x01) */ +/* ===================================================== P1_ERROR_MASK ===================================================== */ + #define R_ETHSW_P1_ERROR_MASK_MSOPERR_Pos (0UL) /*!< MSOPERR (Bit 0) */ + #define R_ETHSW_P1_ERROR_MASK_MSOPERR_Msk (0x1UL) /*!< MSOPERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_ERROR_MASK_MPUNDSZ_Pos (1UL) /*!< MPUNDSZ (Bit 1) */ + #define R_ETHSW_P1_ERROR_MASK_MPUNDSZ_Msk (0x2UL) /*!< MPUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_ERROR_MASK_MPOVRSZ_Pos (2UL) /*!< MPOVRSZ (Bit 2) */ + #define R_ETHSW_P1_ERROR_MASK_MPOVRSZ_Msk (0x4UL) /*!< MPOVRSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_ERROR_MASK_MEUNDSZ_Pos (3UL) /*!< MEUNDSZ (Bit 3) */ + #define R_ETHSW_P1_ERROR_MASK_MEUNDSZ_Msk (0x8UL) /*!< MEUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_ERROR_MASK_MEOVRSZ_Pos (4UL) /*!< MEOVRSZ (Bit 4) */ + #define R_ETHSW_P1_ERROR_MASK_MEOVRSZ_Msk (0x10UL) /*!< MEOVRSZ (Bitfield-Mask: 0x01) */ +/* ===================================================== P2_ERROR_MASK ===================================================== */ + #define R_ETHSW_P2_ERROR_MASK_MSOPERR_Pos (0UL) /*!< MSOPERR (Bit 0) */ + #define R_ETHSW_P2_ERROR_MASK_MSOPERR_Msk (0x1UL) /*!< MSOPERR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_ERROR_MASK_MPUNDSZ_Pos (1UL) /*!< MPUNDSZ (Bit 1) */ + #define R_ETHSW_P2_ERROR_MASK_MPUNDSZ_Msk (0x2UL) /*!< MPUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_ERROR_MASK_MPOVRSZ_Pos (2UL) /*!< MPOVRSZ (Bit 2) */ + #define R_ETHSW_P2_ERROR_MASK_MPOVRSZ_Msk (0x4UL) /*!< MPOVRSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_ERROR_MASK_MEUNDSZ_Pos (3UL) /*!< MEUNDSZ (Bit 3) */ + #define R_ETHSW_P2_ERROR_MASK_MEUNDSZ_Msk (0x8UL) /*!< MEUNDSZ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_ERROR_MASK_MEOVRSZ_Pos (4UL) /*!< MEOVRSZ (Bit 4) */ + #define R_ETHSW_P2_ERROR_MASK_MEOVRSZ_Msk (0x10UL) /*!< MEOVRSZ (Bitfield-Mask: 0x01) */ +/* ===================================================== CHANNEL_STATE ===================================================== */ + #define R_ETHSW_CHANNEL_STATE_CH0ACT_Pos (0UL) /*!< CH0ACT (Bit 0) */ + #define R_ETHSW_CHANNEL_STATE_CH0ACT_Msk (0x1UL) /*!< CH0ACT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_CHANNEL_STATE_CH1ACT_Pos (1UL) /*!< CH1ACT (Bit 1) */ + #define R_ETHSW_CHANNEL_STATE_CH1ACT_Msk (0x2UL) /*!< CH1ACT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_CHANNEL_STATE_CH2ACT_Pos (2UL) /*!< CH2ACT (Bit 2) */ + #define R_ETHSW_CHANNEL_STATE_CH2ACT_Msk (0x4UL) /*!< CH2ACT (Bitfield-Mask: 0x01) */ +/* ==================================================== CHANNEL_ENABLE ===================================================== */ + #define R_ETHSW_CHANNEL_ENABLE_CH0ENA_Pos (0UL) /*!< CH0ENA (Bit 0) */ + #define R_ETHSW_CHANNEL_ENABLE_CH0ENA_Msk (0x1UL) /*!< CH0ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_CHANNEL_ENABLE_CH1ENA_Pos (1UL) /*!< CH1ENA (Bit 1) */ + #define R_ETHSW_CHANNEL_ENABLE_CH1ENA_Msk (0x2UL) /*!< CH1ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_CHANNEL_ENABLE_CH2ENA_Pos (2UL) /*!< CH2ENA (Bit 2) */ + #define R_ETHSW_CHANNEL_ENABLE_CH2ENA_Msk (0x4UL) /*!< CH2ENA (Bitfield-Mask: 0x01) */ +/* ==================================================== CHANNEL_DISABLE ==================================================== */ + #define R_ETHSW_CHANNEL_DISABLE_CH0DIS_Pos (0UL) /*!< CH0DIS (Bit 0) */ + #define R_ETHSW_CHANNEL_DISABLE_CH0DIS_Msk (0x1UL) /*!< CH0DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_CHANNEL_DISABLE_CH1DIS_Pos (1UL) /*!< CH1DIS (Bit 1) */ + #define R_ETHSW_CHANNEL_DISABLE_CH1DIS_Msk (0x2UL) /*!< CH1DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_CHANNEL_DISABLE_CH2DIS_Pos (2UL) /*!< CH2DIS (Bit 2) */ + #define R_ETHSW_CHANNEL_DISABLE_CH2DIS_Msk (0x4UL) /*!< CH2DIS (Bitfield-Mask: 0x01) */ +/* ===================================================== ASI_MEM_WDATA ===================================================== */ + #define R_ETHSW_ASI_MEM_WDATA_WDATA_Pos (0UL) /*!< WDATA (Bit 0) */ + #define R_ETHSW_ASI_MEM_WDATA_WDATA_Msk (0xffffffffUL) /*!< WDATA (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== ASI_MEM_ADDR ====================================================== */ + #define R_ETHSW_ASI_MEM_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ETHSW_ASI_MEM_ADDR_ADDR_Msk (0x7fUL) /*!< ADDR (Bitfield-Mask: 0x7f) */ + #define R_ETHSW_ASI_MEM_ADDR_MEM_WEN_Pos (7UL) /*!< MEM_WEN (Bit 7) */ + #define R_ETHSW_ASI_MEM_ADDR_MEM_WEN_Msk (0x80UL) /*!< MEM_WEN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Pos (8UL) /*!< MEM_REQ (Bit 8) */ + #define R_ETHSW_ASI_MEM_ADDR_MEM_REQ_Msk (0x700UL) /*!< MEM_REQ (Bitfield-Mask: 0x07) */ +/* ===================================================== ASI_MEM_RDATA ===================================================== */ + #define R_ETHSW_ASI_MEM_RDATA_RDATA_Pos (0UL) /*!< RDATA (Bit 0) */ + #define R_ETHSW_ASI_MEM_RDATA_RDATA_Msk (0xffffffffUL) /*!< RDATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMACU0 ====================================================== */ + #define R_ETHSW_P1_QSTMACU0_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACU0_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P1_QSTMACU0_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P1_QSTMACU0_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSTMACU1 ====================================================== */ + #define R_ETHSW_P1_QSTMACU1_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACU1_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P1_QSTMACU1_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P1_QSTMACU1_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSTMACU2 ====================================================== */ + #define R_ETHSW_P1_QSTMACU2_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACU2_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P1_QSTMACU2_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P1_QSTMACU2_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSTMACU3 ====================================================== */ + #define R_ETHSW_P1_QSTMACU3_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACU3_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P1_QSTMACU3_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P1_QSTMACU3_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSTMACU4 ====================================================== */ + #define R_ETHSW_P1_QSTMACU4_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACU4_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P1_QSTMACU4_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P1_QSTMACU4_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSTMACU5 ====================================================== */ + #define R_ETHSW_P1_QSTMACU5_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACU5_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P1_QSTMACU5_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P1_QSTMACU5_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSTMACU6 ====================================================== */ + #define R_ETHSW_P1_QSTMACU6_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACU6_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P1_QSTMACU6_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P1_QSTMACU6_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSTMACU7 ====================================================== */ + #define R_ETHSW_P1_QSTMACU7_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACU7_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P1_QSTMACU7_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P1_QSTMACU7_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSTMACD0 ====================================================== */ + #define R_ETHSW_P1_QSTMACD0_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACD0_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMACD1 ====================================================== */ + #define R_ETHSW_P1_QSTMACD1_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACD1_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMACD2 ====================================================== */ + #define R_ETHSW_P1_QSTMACD2_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACD2_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMACD3 ====================================================== */ + #define R_ETHSW_P1_QSTMACD3_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACD3_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMACD4 ====================================================== */ + #define R_ETHSW_P1_QSTMACD4_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACD4_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMACD5 ====================================================== */ + #define R_ETHSW_P1_QSTMACD5_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACD5_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMACD6 ====================================================== */ + #define R_ETHSW_P1_QSTMACD6_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACD6_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMACD7 ====================================================== */ + #define R_ETHSW_P1_QSTMACD7_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P1_QSTMACD7_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMAMU0 ====================================================== */ + #define R_ETHSW_P1_QSTMAMU0_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMU0_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QSTMAMU1 ====================================================== */ + #define R_ETHSW_P1_QSTMAMU1_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMU1_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QSTMAMU2 ====================================================== */ + #define R_ETHSW_P1_QSTMAMU2_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMU2_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QSTMAMU3 ====================================================== */ + #define R_ETHSW_P1_QSTMAMU3_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMU3_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QSTMAMU4 ====================================================== */ + #define R_ETHSW_P1_QSTMAMU4_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMU4_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QSTMAMU5 ====================================================== */ + #define R_ETHSW_P1_QSTMAMU5_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMU5_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QSTMAMU6 ====================================================== */ + #define R_ETHSW_P1_QSTMAMU6_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMU6_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QSTMAMU7 ====================================================== */ + #define R_ETHSW_P1_QSTMAMU7_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMU7_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QSTMAMD0 ====================================================== */ + #define R_ETHSW_P1_QSTMAMD0_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMD0_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMAMD1 ====================================================== */ + #define R_ETHSW_P1_QSTMAMD1_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMD1_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMAMD2 ====================================================== */ + #define R_ETHSW_P1_QSTMAMD2_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMD2_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMAMD3 ====================================================== */ + #define R_ETHSW_P1_QSTMAMD3_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMD3_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMAMD4 ====================================================== */ + #define R_ETHSW_P1_QSTMAMD4_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMD4_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMAMD5 ====================================================== */ + #define R_ETHSW_P1_QSTMAMD5_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMD5_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMAMD6 ====================================================== */ + #define R_ETHSW_P1_QSTMAMD6_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMD6_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSTMAMD7 ====================================================== */ + #define R_ETHSW_P1_QSTMAMD7_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P1_QSTMAMD7_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P1_QSFTVL0 ======================================================= */ + #define R_ETHSW_P1_QSFTVL0_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P1_QSFTVL0_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVL0_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P1_QSFTVL0_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVL0_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P1_QSFTVL0_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTVL0_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P1_QSFTVL0_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P1_QSFTVL1 ======================================================= */ + #define R_ETHSW_P1_QSFTVL1_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P1_QSFTVL1_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVL1_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P1_QSFTVL1_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVL1_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P1_QSFTVL1_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTVL1_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P1_QSFTVL1_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P1_QSFTVL2 ======================================================= */ + #define R_ETHSW_P1_QSFTVL2_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P1_QSFTVL2_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVL2_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P1_QSFTVL2_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVL2_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P1_QSFTVL2_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTVL2_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P1_QSFTVL2_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P1_QSFTVL3 ======================================================= */ + #define R_ETHSW_P1_QSFTVL3_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P1_QSFTVL3_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVL3_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P1_QSFTVL3_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVL3_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P1_QSFTVL3_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTVL3_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P1_QSFTVL3_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P1_QSFTVL4 ======================================================= */ + #define R_ETHSW_P1_QSFTVL4_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P1_QSFTVL4_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVL4_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P1_QSFTVL4_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVL4_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P1_QSFTVL4_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTVL4_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P1_QSFTVL4_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P1_QSFTVL5 ======================================================= */ + #define R_ETHSW_P1_QSFTVL5_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P1_QSFTVL5_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVL5_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P1_QSFTVL5_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVL5_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P1_QSFTVL5_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTVL5_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P1_QSFTVL5_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P1_QSFTVL6 ======================================================= */ + #define R_ETHSW_P1_QSFTVL6_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P1_QSFTVL6_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVL6_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P1_QSFTVL6_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVL6_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P1_QSFTVL6_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTVL6_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P1_QSFTVL6_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P1_QSFTVL7 ======================================================= */ + #define R_ETHSW_P1_QSFTVL7_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P1_QSFTVL7_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVL7_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P1_QSFTVL7_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVL7_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P1_QSFTVL7_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTVL7_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P1_QSFTVL7_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P1_QSFTVLM0 ====================================================== */ + #define R_ETHSW_P1_QSFTVLM0_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P1_QSFTVLM0_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVLM0_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P1_QSFTVLM0_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVLM0_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P1_QSFTVLM0_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P1_QSFTVLM1 ====================================================== */ + #define R_ETHSW_P1_QSFTVLM1_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P1_QSFTVLM1_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVLM1_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P1_QSFTVLM1_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVLM1_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P1_QSFTVLM1_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P1_QSFTVLM2 ====================================================== */ + #define R_ETHSW_P1_QSFTVLM2_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P1_QSFTVLM2_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVLM2_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P1_QSFTVLM2_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVLM2_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P1_QSFTVLM2_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P1_QSFTVLM3 ====================================================== */ + #define R_ETHSW_P1_QSFTVLM3_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P1_QSFTVLM3_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVLM3_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P1_QSFTVLM3_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVLM3_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P1_QSFTVLM3_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P1_QSFTVLM4 ====================================================== */ + #define R_ETHSW_P1_QSFTVLM4_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P1_QSFTVLM4_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVLM4_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P1_QSFTVLM4_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVLM4_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P1_QSFTVLM4_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P1_QSFTVLM5 ====================================================== */ + #define R_ETHSW_P1_QSFTVLM5_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P1_QSFTVLM5_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVLM5_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P1_QSFTVLM5_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVLM5_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P1_QSFTVLM5_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P1_QSFTVLM6 ====================================================== */ + #define R_ETHSW_P1_QSFTVLM6_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P1_QSFTVLM6_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVLM6_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P1_QSFTVLM6_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVLM6_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P1_QSFTVLM6_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P1_QSFTVLM7 ====================================================== */ + #define R_ETHSW_P1_QSFTVLM7_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P1_QSFTVLM7_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P1_QSFTVLM7_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P1_QSFTVLM7_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTVLM7_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P1_QSFTVLM7_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P1_QSFTBL0 ======================================================= */ + #define R_ETHSW_P1_QSFTBL0_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P1_QSFTBL0_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL0_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P1_QSFTBL0_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL0_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P1_QSFTBL0_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL0_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P1_QSFTBL0_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL0_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P1_QSFTBL0_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL0_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P1_QSFTBL0_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P1_QSFTBL0_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P1_QSFTBL0_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL0_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P1_QSFTBL0_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSFTBL1 ======================================================= */ + #define R_ETHSW_P1_QSFTBL1_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P1_QSFTBL1_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL1_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P1_QSFTBL1_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL1_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P1_QSFTBL1_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL1_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P1_QSFTBL1_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL1_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P1_QSFTBL1_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL1_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P1_QSFTBL1_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P1_QSFTBL1_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P1_QSFTBL1_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL1_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P1_QSFTBL1_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSFTBL2 ======================================================= */ + #define R_ETHSW_P1_QSFTBL2_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P1_QSFTBL2_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL2_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P1_QSFTBL2_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL2_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P1_QSFTBL2_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL2_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P1_QSFTBL2_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL2_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P1_QSFTBL2_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL2_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P1_QSFTBL2_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P1_QSFTBL2_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P1_QSFTBL2_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL2_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P1_QSFTBL2_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSFTBL3 ======================================================= */ + #define R_ETHSW_P1_QSFTBL3_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P1_QSFTBL3_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL3_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P1_QSFTBL3_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL3_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P1_QSFTBL3_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL3_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P1_QSFTBL3_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL3_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P1_QSFTBL3_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL3_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P1_QSFTBL3_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P1_QSFTBL3_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P1_QSFTBL3_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL3_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P1_QSFTBL3_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSFTBL4 ======================================================= */ + #define R_ETHSW_P1_QSFTBL4_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P1_QSFTBL4_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL4_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P1_QSFTBL4_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL4_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P1_QSFTBL4_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL4_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P1_QSFTBL4_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL4_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P1_QSFTBL4_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL4_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P1_QSFTBL4_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P1_QSFTBL4_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P1_QSFTBL4_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL4_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P1_QSFTBL4_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSFTBL5 ======================================================= */ + #define R_ETHSW_P1_QSFTBL5_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P1_QSFTBL5_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL5_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P1_QSFTBL5_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL5_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P1_QSFTBL5_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL5_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P1_QSFTBL5_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL5_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P1_QSFTBL5_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL5_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P1_QSFTBL5_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P1_QSFTBL5_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P1_QSFTBL5_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL5_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P1_QSFTBL5_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSFTBL6 ======================================================= */ + #define R_ETHSW_P1_QSFTBL6_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P1_QSFTBL6_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL6_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P1_QSFTBL6_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL6_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P1_QSFTBL6_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL6_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P1_QSFTBL6_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL6_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P1_QSFTBL6_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL6_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P1_QSFTBL6_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P1_QSFTBL6_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P1_QSFTBL6_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL6_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P1_QSFTBL6_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QSFTBL7 ======================================================= */ + #define R_ETHSW_P1_QSFTBL7_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P1_QSFTBL7_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL7_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P1_QSFTBL7_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL7_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P1_QSFTBL7_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL7_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P1_QSFTBL7_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P1_QSFTBL7_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P1_QSFTBL7_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL7_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P1_QSFTBL7_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P1_QSFTBL7_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P1_QSFTBL7_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QSFTBL7_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P1_QSFTBL7_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ======================================================= P1_QSMFC0 ======================================================= */ + #define R_ETHSW_P1_QSMFC0_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P1_QSMFC0_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QSMFC1 ======================================================= */ + #define R_ETHSW_P1_QSMFC1_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P1_QSMFC1_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QSMFC2 ======================================================= */ + #define R_ETHSW_P1_QSMFC2_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P1_QSMFC2_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QSMFC3 ======================================================= */ + #define R_ETHSW_P1_QSMFC3_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P1_QSMFC3_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QSMFC4 ======================================================= */ + #define R_ETHSW_P1_QSMFC4_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P1_QSMFC4_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QSMFC5 ======================================================= */ + #define R_ETHSW_P1_QSMFC5_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P1_QSMFC5_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QSMFC6 ======================================================= */ + #define R_ETHSW_P1_QSMFC6_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P1_QSMFC6_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QSMFC7 ======================================================= */ + #define R_ETHSW_P1_QSMFC7_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P1_QSMFC7_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSPPC0 ======================================================= */ + #define R_ETHSW_P1_QMSPPC0_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P1_QMSPPC0_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSPPC1 ======================================================= */ + #define R_ETHSW_P1_QMSPPC1_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P1_QMSPPC1_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSPPC2 ======================================================= */ + #define R_ETHSW_P1_QMSPPC2_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P1_QMSPPC2_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSPPC3 ======================================================= */ + #define R_ETHSW_P1_QMSPPC3_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P1_QMSPPC3_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSPPC4 ======================================================= */ + #define R_ETHSW_P1_QMSPPC4_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P1_QMSPPC4_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSPPC5 ======================================================= */ + #define R_ETHSW_P1_QMSPPC5_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P1_QMSPPC5_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSPPC6 ======================================================= */ + #define R_ETHSW_P1_QMSPPC6_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P1_QMSPPC6_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSPPC7 ======================================================= */ + #define R_ETHSW_P1_QMSPPC7_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P1_QMSPPC7_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSRPC0 ======================================================= */ + #define R_ETHSW_P1_QMSRPC0_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P1_QMSRPC0_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSRPC1 ======================================================= */ + #define R_ETHSW_P1_QMSRPC1_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P1_QMSRPC1_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSRPC2 ======================================================= */ + #define R_ETHSW_P1_QMSRPC2_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P1_QMSRPC2_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSRPC3 ======================================================= */ + #define R_ETHSW_P1_QMSRPC3_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P1_QMSRPC3_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSRPC4 ======================================================= */ + #define R_ETHSW_P1_QMSRPC4_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P1_QMSRPC4_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSRPC5 ======================================================= */ + #define R_ETHSW_P1_QMSRPC5_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P1_QMSRPC5_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSRPC6 ======================================================= */ + #define R_ETHSW_P1_QMSRPC6_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P1_QMSRPC6_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMSRPC7 ======================================================= */ + #define R_ETHSW_P1_QMSRPC7_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P1_QMSRPC7_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QGDPC0 ======================================================= */ + #define R_ETHSW_P1_QGDPC0_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P1_QGDPC0_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QGDPC1 ======================================================= */ + #define R_ETHSW_P1_QGDPC1_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P1_QGDPC1_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QGDPC2 ======================================================= */ + #define R_ETHSW_P1_QGDPC2_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P1_QGDPC2_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QGDPC3 ======================================================= */ + #define R_ETHSW_P1_QGDPC3_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P1_QGDPC3_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QGDPC4 ======================================================= */ + #define R_ETHSW_P1_QGDPC4_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P1_QGDPC4_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QGDPC5 ======================================================= */ + #define R_ETHSW_P1_QGDPC5_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P1_QGDPC5_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QGDPC6 ======================================================= */ + #define R_ETHSW_P1_QGDPC6_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P1_QGDPC6_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QGDPC7 ======================================================= */ + #define R_ETHSW_P1_QGDPC7_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P1_QGDPC7_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P1_QMDESC0 ======================================================= */ + #define R_ETHSW_P1_QMDESC0_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P1_QMDESC0_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC0_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P1_QMDESC0_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC0_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P1_QMDESC0_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QMDESC1 ======================================================= */ + #define R_ETHSW_P1_QMDESC1_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P1_QMDESC1_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC1_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P1_QMDESC1_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC1_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P1_QMDESC1_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QMDESC2 ======================================================= */ + #define R_ETHSW_P1_QMDESC2_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P1_QMDESC2_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC2_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P1_QMDESC2_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC2_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P1_QMDESC2_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QMDESC3 ======================================================= */ + #define R_ETHSW_P1_QMDESC3_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P1_QMDESC3_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC3_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P1_QMDESC3_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC3_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P1_QMDESC3_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QMDESC4 ======================================================= */ + #define R_ETHSW_P1_QMDESC4_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P1_QMDESC4_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC4_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P1_QMDESC4_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC4_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P1_QMDESC4_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QMDESC5 ======================================================= */ + #define R_ETHSW_P1_QMDESC5_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P1_QMDESC5_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC5_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P1_QMDESC5_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC5_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P1_QMDESC5_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QMDESC6 ======================================================= */ + #define R_ETHSW_P1_QMDESC6_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P1_QMDESC6_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC6_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P1_QMDESC6_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC6_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P1_QMDESC6_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QMDESC7 ======================================================= */ + #define R_ETHSW_P1_QMDESC7_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P1_QMDESC7_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC7_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P1_QMDESC7_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P1_QMDESC7_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P1_QMDESC7_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P1_QMCBSC0 ======================================================= */ + #define R_ETHSW_P1_QMCBSC0_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P1_QMCBSC0_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P1_QMCBSC1 ======================================================= */ + #define R_ETHSW_P1_QMCBSC1_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P1_QMCBSC1_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P1_QMCBSC2 ======================================================= */ + #define R_ETHSW_P1_QMCBSC2_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P1_QMCBSC2_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P1_QMCBSC3 ======================================================= */ + #define R_ETHSW_P1_QMCBSC3_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P1_QMCBSC3_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P1_QMCBSC4 ======================================================= */ + #define R_ETHSW_P1_QMCBSC4_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P1_QMCBSC4_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P1_QMCBSC5 ======================================================= */ + #define R_ETHSW_P1_QMCBSC5_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P1_QMCBSC5_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P1_QMCBSC6 ======================================================= */ + #define R_ETHSW_P1_QMCBSC6_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P1_QMCBSC6_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P1_QMCBSC7 ======================================================= */ + #define R_ETHSW_P1_QMCBSC7_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P1_QMCBSC7_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P1_QMCIRC0 ======================================================= */ + #define R_ETHSW_P1_QMCIRC0_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P1_QMCIRC0_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P1_QMCIRC1 ======================================================= */ + #define R_ETHSW_P1_QMCIRC1_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P1_QMCIRC1_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P1_QMCIRC2 ======================================================= */ + #define R_ETHSW_P1_QMCIRC2_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P1_QMCIRC2_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P1_QMCIRC3 ======================================================= */ + #define R_ETHSW_P1_QMCIRC3_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P1_QMCIRC3_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P1_QMCIRC4 ======================================================= */ + #define R_ETHSW_P1_QMCIRC4_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P1_QMCIRC4_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P1_QMCIRC5 ======================================================= */ + #define R_ETHSW_P1_QMCIRC5_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P1_QMCIRC5_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P1_QMCIRC6 ======================================================= */ + #define R_ETHSW_P1_QMCIRC6_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P1_QMCIRC6_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P1_QMCIRC7 ======================================================= */ + #define R_ETHSW_P1_QMCIRC7_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P1_QMCIRC7_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= P1_QMGPC0 ======================================================= */ + #define R_ETHSW_P1_QMGPC0_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P1_QMGPC0_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMGPC1 ======================================================= */ + #define R_ETHSW_P1_QMGPC1_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P1_QMGPC1_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMGPC2 ======================================================= */ + #define R_ETHSW_P1_QMGPC2_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P1_QMGPC2_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMGPC3 ======================================================= */ + #define R_ETHSW_P1_QMGPC3_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P1_QMGPC3_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMGPC4 ======================================================= */ + #define R_ETHSW_P1_QMGPC4_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P1_QMGPC4_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMGPC5 ======================================================= */ + #define R_ETHSW_P1_QMGPC5_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P1_QMGPC5_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMGPC6 ======================================================= */ + #define R_ETHSW_P1_QMGPC6_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P1_QMGPC6_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMGPC7 ======================================================= */ + #define R_ETHSW_P1_QMGPC7_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P1_QMGPC7_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMRPC0 ======================================================= */ + #define R_ETHSW_P1_QMRPC0_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P1_QMRPC0_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMRPC1 ======================================================= */ + #define R_ETHSW_P1_QMRPC1_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P1_QMRPC1_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMRPC2 ======================================================= */ + #define R_ETHSW_P1_QMRPC2_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P1_QMRPC2_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMRPC3 ======================================================= */ + #define R_ETHSW_P1_QMRPC3_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P1_QMRPC3_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMRPC4 ======================================================= */ + #define R_ETHSW_P1_QMRPC4_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P1_QMRPC4_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMRPC5 ======================================================= */ + #define R_ETHSW_P1_QMRPC5_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P1_QMRPC5_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMRPC6 ======================================================= */ + #define R_ETHSW_P1_QMRPC6_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P1_QMRPC6_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P1_QMRPC7 ======================================================= */ + #define R_ETHSW_P1_QMRPC7_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P1_QMRPC7_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QSTMACU0 ====================================================== */ + #define R_ETHSW_P2_QSTMACU0_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACU0_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P2_QSTMACU0_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P2_QSTMACU0_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSTMACU1 ====================================================== */ + #define R_ETHSW_P2_QSTMACU1_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACU1_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P2_QSTMACU1_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P2_QSTMACU1_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSTMACU2 ====================================================== */ + #define R_ETHSW_P2_QSTMACU2_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACU2_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P2_QSTMACU2_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P2_QSTMACU2_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSTMACU3 ====================================================== */ + #define R_ETHSW_P2_QSTMACU3_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACU3_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P2_QSTMACU3_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P2_QSTMACU3_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSTMACU4 ====================================================== */ + #define R_ETHSW_P2_QSTMACU4_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACU4_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P2_QSTMACU4_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P2_QSTMACU4_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSTMACU5 ====================================================== */ + #define R_ETHSW_P2_QSTMACU5_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACU5_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P2_QSTMACU5_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P2_QSTMACU5_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSTMACU6 ====================================================== */ + #define R_ETHSW_P2_QSTMACU6_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACU6_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P2_QSTMACU6_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P2_QSTMACU6_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSTMACU7 ====================================================== */ + #define R_ETHSW_P2_QSTMACU7_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACU7_MACA_Msk (0xffffUL) /*!< MACA (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_P2_QSTMACU7_DASA_Pos (16UL) /*!< DASA (Bit 16) */ + #define R_ETHSW_P2_QSTMACU7_DASA_Msk (0x10000UL) /*!< DASA (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSTMACD0 ====================================================== */ + #define R_ETHSW_P2_QSTMACD0_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACD0_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMACD1 ====================================================== */ + #define R_ETHSW_P2_QSTMACD1_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACD1_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMACD2 ====================================================== */ + #define R_ETHSW_P2_QSTMACD2_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACD2_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMACD3 ====================================================== */ + #define R_ETHSW_P2_QSTMACD3_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACD3_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMACD4 ====================================================== */ + #define R_ETHSW_P2_QSTMACD4_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACD4_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMACD5 ====================================================== */ + #define R_ETHSW_P2_QSTMACD5_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACD5_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMACD6 ====================================================== */ + #define R_ETHSW_P2_QSTMACD6_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACD6_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMACD7 ====================================================== */ + #define R_ETHSW_P2_QSTMACD7_MACA_Pos (0UL) /*!< MACA (Bit 0) */ + #define R_ETHSW_P2_QSTMACD7_MACA_Msk (0xffffffffUL) /*!< MACA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMAMU0 ====================================================== */ + #define R_ETHSW_P2_QSTMAMU0_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMU0_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QSTMAMU1 ====================================================== */ + #define R_ETHSW_P2_QSTMAMU1_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMU1_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QSTMAMU2 ====================================================== */ + #define R_ETHSW_P2_QSTMAMU2_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMU2_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QSTMAMU3 ====================================================== */ + #define R_ETHSW_P2_QSTMAMU3_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMU3_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QSTMAMU4 ====================================================== */ + #define R_ETHSW_P2_QSTMAMU4_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMU4_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QSTMAMU5 ====================================================== */ + #define R_ETHSW_P2_QSTMAMU5_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMU5_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QSTMAMU6 ====================================================== */ + #define R_ETHSW_P2_QSTMAMU6_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMU6_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QSTMAMU7 ====================================================== */ + #define R_ETHSW_P2_QSTMAMU7_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMU7_MACAM_Msk (0xffffUL) /*!< MACAM (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QSTMAMD0 ====================================================== */ + #define R_ETHSW_P2_QSTMAMD0_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMD0_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMAMD1 ====================================================== */ + #define R_ETHSW_P2_QSTMAMD1_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMD1_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMAMD2 ====================================================== */ + #define R_ETHSW_P2_QSTMAMD2_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMD2_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMAMD3 ====================================================== */ + #define R_ETHSW_P2_QSTMAMD3_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMD3_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMAMD4 ====================================================== */ + #define R_ETHSW_P2_QSTMAMD4_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMD4_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMAMD5 ====================================================== */ + #define R_ETHSW_P2_QSTMAMD5_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMD5_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMAMD6 ====================================================== */ + #define R_ETHSW_P2_QSTMAMD6_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMD6_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSTMAMD7 ====================================================== */ + #define R_ETHSW_P2_QSTMAMD7_MACAM_Pos (0UL) /*!< MACAM (Bit 0) */ + #define R_ETHSW_P2_QSTMAMD7_MACAM_Msk (0xffffffffUL) /*!< MACAM (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== P2_QSFTVL0 ======================================================= */ + #define R_ETHSW_P2_QSFTVL0_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P2_QSFTVL0_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVL0_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P2_QSFTVL0_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVL0_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P2_QSFTVL0_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTVL0_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P2_QSFTVL0_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P2_QSFTVL1 ======================================================= */ + #define R_ETHSW_P2_QSFTVL1_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P2_QSFTVL1_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVL1_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P2_QSFTVL1_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVL1_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P2_QSFTVL1_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTVL1_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P2_QSFTVL1_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P2_QSFTVL2 ======================================================= */ + #define R_ETHSW_P2_QSFTVL2_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P2_QSFTVL2_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVL2_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P2_QSFTVL2_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVL2_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P2_QSFTVL2_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTVL2_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P2_QSFTVL2_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P2_QSFTVL3 ======================================================= */ + #define R_ETHSW_P2_QSFTVL3_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P2_QSFTVL3_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVL3_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P2_QSFTVL3_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVL3_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P2_QSFTVL3_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTVL3_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P2_QSFTVL3_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P2_QSFTVL4 ======================================================= */ + #define R_ETHSW_P2_QSFTVL4_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P2_QSFTVL4_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVL4_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P2_QSFTVL4_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVL4_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P2_QSFTVL4_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTVL4_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P2_QSFTVL4_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P2_QSFTVL5 ======================================================= */ + #define R_ETHSW_P2_QSFTVL5_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P2_QSFTVL5_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVL5_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P2_QSFTVL5_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVL5_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P2_QSFTVL5_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTVL5_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P2_QSFTVL5_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P2_QSFTVL6 ======================================================= */ + #define R_ETHSW_P2_QSFTVL6_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P2_QSFTVL6_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVL6_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P2_QSFTVL6_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVL6_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P2_QSFTVL6_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTVL6_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P2_QSFTVL6_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P2_QSFTVL7 ======================================================= */ + #define R_ETHSW_P2_QSFTVL7_VLANID_Pos (0UL) /*!< VLANID (Bit 0) */ + #define R_ETHSW_P2_QSFTVL7_VLANID_Msk (0xfffUL) /*!< VLANID (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVL7_DEI_Pos (12UL) /*!< DEI (Bit 12) */ + #define R_ETHSW_P2_QSFTVL7_DEI_Msk (0x1000UL) /*!< DEI (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVL7_PCP_Pos (13UL) /*!< PCP (Bit 13) */ + #define R_ETHSW_P2_QSFTVL7_PCP_Msk (0xe000UL) /*!< PCP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTVL7_TAGMD_Pos (16UL) /*!< TAGMD (Bit 16) */ + #define R_ETHSW_P2_QSFTVL7_TAGMD_Msk (0x30000UL) /*!< TAGMD (Bitfield-Mask: 0x03) */ +/* ====================================================== P2_QSFTVLM0 ====================================================== */ + #define R_ETHSW_P2_QSFTVLM0_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P2_QSFTVLM0_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVLM0_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P2_QSFTVLM0_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVLM0_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P2_QSFTVLM0_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P2_QSFTVLM1 ====================================================== */ + #define R_ETHSW_P2_QSFTVLM1_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P2_QSFTVLM1_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVLM1_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P2_QSFTVLM1_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVLM1_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P2_QSFTVLM1_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P2_QSFTVLM2 ====================================================== */ + #define R_ETHSW_P2_QSFTVLM2_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P2_QSFTVLM2_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVLM2_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P2_QSFTVLM2_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVLM2_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P2_QSFTVLM2_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P2_QSFTVLM3 ====================================================== */ + #define R_ETHSW_P2_QSFTVLM3_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P2_QSFTVLM3_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVLM3_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P2_QSFTVLM3_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVLM3_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P2_QSFTVLM3_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P2_QSFTVLM4 ====================================================== */ + #define R_ETHSW_P2_QSFTVLM4_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P2_QSFTVLM4_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVLM4_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P2_QSFTVLM4_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVLM4_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P2_QSFTVLM4_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P2_QSFTVLM5 ====================================================== */ + #define R_ETHSW_P2_QSFTVLM5_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P2_QSFTVLM5_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVLM5_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P2_QSFTVLM5_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVLM5_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P2_QSFTVLM5_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P2_QSFTVLM6 ====================================================== */ + #define R_ETHSW_P2_QSFTVLM6_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P2_QSFTVLM6_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVLM6_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P2_QSFTVLM6_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVLM6_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P2_QSFTVLM6_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P2_QSFTVLM7 ====================================================== */ + #define R_ETHSW_P2_QSFTVLM7_VLANIDM_Pos (0UL) /*!< VLANIDM (Bit 0) */ + #define R_ETHSW_P2_QSFTVLM7_VLANIDM_Msk (0xfffUL) /*!< VLANIDM (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_P2_QSFTVLM7_DEIM_Pos (12UL) /*!< DEIM (Bit 12) */ + #define R_ETHSW_P2_QSFTVLM7_DEIM_Msk (0x1000UL) /*!< DEIM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTVLM7_PCPM_Pos (13UL) /*!< PCPM (Bit 13) */ + #define R_ETHSW_P2_QSFTVLM7_PCPM_Msk (0xe000UL) /*!< PCPM (Bitfield-Mask: 0x07) */ +/* ====================================================== P2_QSFTBL0 ======================================================= */ + #define R_ETHSW_P2_QSFTBL0_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P2_QSFTBL0_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL0_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P2_QSFTBL0_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL0_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P2_QSFTBL0_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL0_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P2_QSFTBL0_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL0_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P2_QSFTBL0_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL0_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P2_QSFTBL0_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P2_QSFTBL0_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P2_QSFTBL0_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL0_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P2_QSFTBL0_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSFTBL1 ======================================================= */ + #define R_ETHSW_P2_QSFTBL1_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P2_QSFTBL1_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL1_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P2_QSFTBL1_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL1_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P2_QSFTBL1_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL1_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P2_QSFTBL1_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL1_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P2_QSFTBL1_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL1_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P2_QSFTBL1_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P2_QSFTBL1_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P2_QSFTBL1_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL1_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P2_QSFTBL1_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSFTBL2 ======================================================= */ + #define R_ETHSW_P2_QSFTBL2_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P2_QSFTBL2_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL2_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P2_QSFTBL2_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL2_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P2_QSFTBL2_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL2_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P2_QSFTBL2_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL2_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P2_QSFTBL2_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL2_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P2_QSFTBL2_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P2_QSFTBL2_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P2_QSFTBL2_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL2_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P2_QSFTBL2_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSFTBL3 ======================================================= */ + #define R_ETHSW_P2_QSFTBL3_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P2_QSFTBL3_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL3_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P2_QSFTBL3_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL3_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P2_QSFTBL3_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL3_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P2_QSFTBL3_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL3_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P2_QSFTBL3_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL3_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P2_QSFTBL3_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P2_QSFTBL3_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P2_QSFTBL3_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL3_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P2_QSFTBL3_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSFTBL4 ======================================================= */ + #define R_ETHSW_P2_QSFTBL4_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P2_QSFTBL4_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL4_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P2_QSFTBL4_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL4_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P2_QSFTBL4_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL4_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P2_QSFTBL4_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL4_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P2_QSFTBL4_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL4_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P2_QSFTBL4_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P2_QSFTBL4_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P2_QSFTBL4_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL4_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P2_QSFTBL4_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSFTBL5 ======================================================= */ + #define R_ETHSW_P2_QSFTBL5_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P2_QSFTBL5_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL5_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P2_QSFTBL5_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL5_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P2_QSFTBL5_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL5_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P2_QSFTBL5_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL5_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P2_QSFTBL5_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL5_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P2_QSFTBL5_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P2_QSFTBL5_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P2_QSFTBL5_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL5_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P2_QSFTBL5_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSFTBL6 ======================================================= */ + #define R_ETHSW_P2_QSFTBL6_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P2_QSFTBL6_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL6_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P2_QSFTBL6_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL6_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P2_QSFTBL6_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL6_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P2_QSFTBL6_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL6_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P2_QSFTBL6_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL6_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P2_QSFTBL6_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P2_QSFTBL6_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P2_QSFTBL6_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL6_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P2_QSFTBL6_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QSFTBL7 ======================================================= */ + #define R_ETHSW_P2_QSFTBL7_QSTE_Pos (0UL) /*!< QSTE (Bit 0) */ + #define R_ETHSW_P2_QSFTBL7_QSTE_Msk (0x1UL) /*!< QSTE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL7_GAID_Pos (4UL) /*!< GAID (Bit 4) */ + #define R_ETHSW_P2_QSFTBL7_GAID_Msk (0x70UL) /*!< GAID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL7_GAIDV_Pos (7UL) /*!< GAIDV (Bit 7) */ + #define R_ETHSW_P2_QSFTBL7_GAIDV_Msk (0x80UL) /*!< GAIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL7_MEID_Pos (8UL) /*!< MEID (Bit 8) */ + #define R_ETHSW_P2_QSFTBL7_MEID_Msk (0x700UL) /*!< MEID (Bitfield-Mask: 0x07) */ + #define R_ETHSW_P2_QSFTBL7_MEIDV_Pos (12UL) /*!< MEIDV (Bit 12) */ + #define R_ETHSW_P2_QSFTBL7_MEIDV_Msk (0x1000UL) /*!< MEIDV (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL7_MSDU_Pos (16UL) /*!< MSDU (Bit 16) */ + #define R_ETHSW_P2_QSFTBL7_MSDU_Msk (0x7ff0000UL) /*!< MSDU (Bitfield-Mask: 0x7ff) */ + #define R_ETHSW_P2_QSFTBL7_MSDUE_Pos (27UL) /*!< MSDUE (Bit 27) */ + #define R_ETHSW_P2_QSFTBL7_MSDUE_Msk (0x8000000UL) /*!< MSDUE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QSFTBL7_QSMSM_Pos (28UL) /*!< QSMSM (Bit 28) */ + #define R_ETHSW_P2_QSFTBL7_QSMSM_Msk (0x10000000UL) /*!< QSMSM (Bitfield-Mask: 0x01) */ +/* ======================================================= P2_QSMFC0 ======================================================= */ + #define R_ETHSW_P2_QSMFC0_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P2_QSMFC0_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QSMFC1 ======================================================= */ + #define R_ETHSW_P2_QSMFC1_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P2_QSMFC1_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QSMFC2 ======================================================= */ + #define R_ETHSW_P2_QSMFC2_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P2_QSMFC2_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QSMFC3 ======================================================= */ + #define R_ETHSW_P2_QSMFC3_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P2_QSMFC3_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QSMFC4 ======================================================= */ + #define R_ETHSW_P2_QSMFC4_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P2_QSMFC4_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QSMFC5 ======================================================= */ + #define R_ETHSW_P2_QSMFC5_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P2_QSMFC5_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QSMFC6 ======================================================= */ + #define R_ETHSW_P2_QSMFC6_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P2_QSMFC6_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QSMFC7 ======================================================= */ + #define R_ETHSW_P2_QSMFC7_QSMFC_Pos (0UL) /*!< QSMFC (Bit 0) */ + #define R_ETHSW_P2_QSMFC7_QSMFC_Msk (0xffffUL) /*!< QSMFC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSPPC0 ======================================================= */ + #define R_ETHSW_P2_QMSPPC0_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P2_QMSPPC0_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSPPC1 ======================================================= */ + #define R_ETHSW_P2_QMSPPC1_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P2_QMSPPC1_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSPPC2 ======================================================= */ + #define R_ETHSW_P2_QMSPPC2_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P2_QMSPPC2_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSPPC3 ======================================================= */ + #define R_ETHSW_P2_QMSPPC3_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P2_QMSPPC3_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSPPC4 ======================================================= */ + #define R_ETHSW_P2_QMSPPC4_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P2_QMSPPC4_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSPPC5 ======================================================= */ + #define R_ETHSW_P2_QMSPPC5_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P2_QMSPPC5_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSPPC6 ======================================================= */ + #define R_ETHSW_P2_QMSPPC6_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P2_QMSPPC6_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSPPC7 ======================================================= */ + #define R_ETHSW_P2_QMSPPC7_QMSPPC_Pos (0UL) /*!< QMSPPC (Bit 0) */ + #define R_ETHSW_P2_QMSPPC7_QMSPPC_Msk (0xffffUL) /*!< QMSPPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSRPC0 ======================================================= */ + #define R_ETHSW_P2_QMSRPC0_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P2_QMSRPC0_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSRPC1 ======================================================= */ + #define R_ETHSW_P2_QMSRPC1_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P2_QMSRPC1_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSRPC2 ======================================================= */ + #define R_ETHSW_P2_QMSRPC2_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P2_QMSRPC2_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSRPC3 ======================================================= */ + #define R_ETHSW_P2_QMSRPC3_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P2_QMSRPC3_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSRPC4 ======================================================= */ + #define R_ETHSW_P2_QMSRPC4_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P2_QMSRPC4_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSRPC5 ======================================================= */ + #define R_ETHSW_P2_QMSRPC5_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P2_QMSRPC5_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSRPC6 ======================================================= */ + #define R_ETHSW_P2_QMSRPC6_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P2_QMSRPC6_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMSRPC7 ======================================================= */ + #define R_ETHSW_P2_QMSRPC7_QMSRPC_Pos (0UL) /*!< QMSRPC (Bit 0) */ + #define R_ETHSW_P2_QMSRPC7_QMSRPC_Msk (0xffffUL) /*!< QMSRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QGDPC0 ======================================================= */ + #define R_ETHSW_P2_QGDPC0_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P2_QGDPC0_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QGDPC1 ======================================================= */ + #define R_ETHSW_P2_QGDPC1_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P2_QGDPC1_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QGDPC2 ======================================================= */ + #define R_ETHSW_P2_QGDPC2_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P2_QGDPC2_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QGDPC3 ======================================================= */ + #define R_ETHSW_P2_QGDPC3_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P2_QGDPC3_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QGDPC4 ======================================================= */ + #define R_ETHSW_P2_QGDPC4_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P2_QGDPC4_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QGDPC5 ======================================================= */ + #define R_ETHSW_P2_QGDPC5_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P2_QGDPC5_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QGDPC6 ======================================================= */ + #define R_ETHSW_P2_QGDPC6_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P2_QGDPC6_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QGDPC7 ======================================================= */ + #define R_ETHSW_P2_QGDPC7_QGDPC_Pos (0UL) /*!< QGDPC (Bit 0) */ + #define R_ETHSW_P2_QGDPC7_QGDPC_Msk (0xffffUL) /*!< QGDPC (Bitfield-Mask: 0xffff) */ +/* ====================================================== P2_QMDESC0 ======================================================= */ + #define R_ETHSW_P2_QMDESC0_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P2_QMDESC0_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC0_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P2_QMDESC0_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC0_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P2_QMDESC0_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QMDESC1 ======================================================= */ + #define R_ETHSW_P2_QMDESC1_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P2_QMDESC1_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC1_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P2_QMDESC1_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC1_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P2_QMDESC1_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QMDESC2 ======================================================= */ + #define R_ETHSW_P2_QMDESC2_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P2_QMDESC2_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC2_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P2_QMDESC2_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC2_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P2_QMDESC2_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QMDESC3 ======================================================= */ + #define R_ETHSW_P2_QMDESC3_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P2_QMDESC3_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC3_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P2_QMDESC3_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC3_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P2_QMDESC3_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QMDESC4 ======================================================= */ + #define R_ETHSW_P2_QMDESC4_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P2_QMDESC4_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC4_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P2_QMDESC4_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC4_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P2_QMDESC4_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QMDESC5 ======================================================= */ + #define R_ETHSW_P2_QMDESC5_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P2_QMDESC5_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC5_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P2_QMDESC5_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC5_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P2_QMDESC5_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QMDESC6 ======================================================= */ + #define R_ETHSW_P2_QMDESC6_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P2_QMDESC6_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC6_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P2_QMDESC6_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC6_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P2_QMDESC6_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QMDESC7 ======================================================= */ + #define R_ETHSW_P2_QMDESC7_RFD_Pos (0UL) /*!< RFD (Bit 0) */ + #define R_ETHSW_P2_QMDESC7_RFD_Msk (0x1UL) /*!< RFD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC7_MM_Pos (1UL) /*!< MM (Bit 1) */ + #define R_ETHSW_P2_QMDESC7_MM_Msk (0x2UL) /*!< MM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_P2_QMDESC7_CF_Pos (2UL) /*!< CF (Bit 2) */ + #define R_ETHSW_P2_QMDESC7_CF_Msk (0x4UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ====================================================== P2_QMCBSC0 ======================================================= */ + #define R_ETHSW_P2_QMCBSC0_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P2_QMCBSC0_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P2_QMCBSC1 ======================================================= */ + #define R_ETHSW_P2_QMCBSC1_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P2_QMCBSC1_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P2_QMCBSC2 ======================================================= */ + #define R_ETHSW_P2_QMCBSC2_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P2_QMCBSC2_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P2_QMCBSC3 ======================================================= */ + #define R_ETHSW_P2_QMCBSC3_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P2_QMCBSC3_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P2_QMCBSC4 ======================================================= */ + #define R_ETHSW_P2_QMCBSC4_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P2_QMCBSC4_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P2_QMCBSC5 ======================================================= */ + #define R_ETHSW_P2_QMCBSC5_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P2_QMCBSC5_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P2_QMCBSC6 ======================================================= */ + #define R_ETHSW_P2_QMCBSC6_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P2_QMCBSC6_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P2_QMCBSC7 ======================================================= */ + #define R_ETHSW_P2_QMCBSC7_CBS_Pos (0UL) /*!< CBS (Bit 0) */ + #define R_ETHSW_P2_QMCBSC7_CBS_Msk (0x3ffffUL) /*!< CBS (Bitfield-Mask: 0x3ffff) */ +/* ====================================================== P2_QMCIRC0 ======================================================= */ + #define R_ETHSW_P2_QMCIRC0_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P2_QMCIRC0_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P2_QMCIRC1 ======================================================= */ + #define R_ETHSW_P2_QMCIRC1_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P2_QMCIRC1_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P2_QMCIRC2 ======================================================= */ + #define R_ETHSW_P2_QMCIRC2_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P2_QMCIRC2_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P2_QMCIRC3 ======================================================= */ + #define R_ETHSW_P2_QMCIRC3_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P2_QMCIRC3_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P2_QMCIRC4 ======================================================= */ + #define R_ETHSW_P2_QMCIRC4_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P2_QMCIRC4_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P2_QMCIRC5 ======================================================= */ + #define R_ETHSW_P2_QMCIRC5_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P2_QMCIRC5_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P2_QMCIRC6 ======================================================= */ + #define R_ETHSW_P2_QMCIRC6_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P2_QMCIRC6_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ====================================================== P2_QMCIRC7 ======================================================= */ + #define R_ETHSW_P2_QMCIRC7_CIR_Pos (0UL) /*!< CIR (Bit 0) */ + #define R_ETHSW_P2_QMCIRC7_CIR_Msk (0x1ffffUL) /*!< CIR (Bitfield-Mask: 0x1ffff) */ +/* ======================================================= P2_QMGPC0 ======================================================= */ + #define R_ETHSW_P2_QMGPC0_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P2_QMGPC0_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMGPC1 ======================================================= */ + #define R_ETHSW_P2_QMGPC1_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P2_QMGPC1_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMGPC2 ======================================================= */ + #define R_ETHSW_P2_QMGPC2_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P2_QMGPC2_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMGPC3 ======================================================= */ + #define R_ETHSW_P2_QMGPC3_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P2_QMGPC3_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMGPC4 ======================================================= */ + #define R_ETHSW_P2_QMGPC4_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P2_QMGPC4_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMGPC5 ======================================================= */ + #define R_ETHSW_P2_QMGPC5_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P2_QMGPC5_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMGPC6 ======================================================= */ + #define R_ETHSW_P2_QMGPC6_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P2_QMGPC6_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMGPC7 ======================================================= */ + #define R_ETHSW_P2_QMGPC7_QMGPC_Pos (0UL) /*!< QMGPC (Bit 0) */ + #define R_ETHSW_P2_QMGPC7_QMGPC_Msk (0xffffUL) /*!< QMGPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMRPC0 ======================================================= */ + #define R_ETHSW_P2_QMRPC0_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P2_QMRPC0_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMRPC1 ======================================================= */ + #define R_ETHSW_P2_QMRPC1_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P2_QMRPC1_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMRPC2 ======================================================= */ + #define R_ETHSW_P2_QMRPC2_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P2_QMRPC2_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMRPC3 ======================================================= */ + #define R_ETHSW_P2_QMRPC3_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P2_QMRPC3_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMRPC4 ======================================================= */ + #define R_ETHSW_P2_QMRPC4_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P2_QMRPC4_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMRPC5 ======================================================= */ + #define R_ETHSW_P2_QMRPC5_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P2_QMRPC5_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMRPC6 ======================================================= */ + #define R_ETHSW_P2_QMRPC6_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P2_QMRPC6_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ======================================================= P2_QMRPC7 ======================================================= */ + #define R_ETHSW_P2_QMRPC7_QMRPC_Pos (0UL) /*!< QMRPC (Bit 0) */ + #define R_ETHSW_P2_QMRPC7_QMRPC_Msk (0xffffUL) /*!< QMRPC (Bitfield-Mask: 0xffff) */ +/* ===================================================== STATN_STATUS ====================================================== */ + #define R_ETHSW_STATN_STATUS_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_ETHSW_STATN_STATUS_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ===================================================== STATN_CONFIG ====================================================== */ + #define R_ETHSW_STATN_CONFIG_CLEAR_ON_READ_Pos (1UL) /*!< CLEAR_ON_READ (Bit 1) */ + #define R_ETHSW_STATN_CONFIG_CLEAR_ON_READ_Msk (0x2UL) /*!< CLEAR_ON_READ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATN_CONFIG_RESET_Pos (31UL) /*!< RESET (Bit 31) */ + #define R_ETHSW_STATN_CONFIG_RESET_Msk (0x80000000UL) /*!< RESET (Bitfield-Mask: 0x01) */ +/* ===================================================== STATN_CONTROL ===================================================== */ + #define R_ETHSW_STATN_CONTROL_CHANMASK_Pos (0UL) /*!< CHANMASK (Bit 0) */ + #define R_ETHSW_STATN_CONTROL_CHANMASK_Msk (0xfUL) /*!< CHANMASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_STATN_CONTROL_CLEAR_PRE_Pos (29UL) /*!< CLEAR_PRE (Bit 29) */ + #define R_ETHSW_STATN_CONTROL_CLEAR_PRE_Msk (0x20000000UL) /*!< CLEAR_PRE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_STATN_CONTROL_CMD_CLEAR_Pos (31UL) /*!< CMD_CLEAR (Bit 31) */ + #define R_ETHSW_STATN_CONTROL_CMD_CLEAR_Msk (0x80000000UL) /*!< CMD_CLEAR (Bitfield-Mask: 0x01) */ +/* ================================================== STATN_CLEARVALUE_LO ================================================== */ + #define R_ETHSW_STATN_CLEARVALUE_LO_STATN_CLEARVALUE_LO_Pos (0UL) /*!< STATN_CLEARVALUE_LO (Bit 0) */ + #define R_ETHSW_STATN_CLEARVALUE_LO_STATN_CLEARVALUE_LO_Msk (0xffffffffUL) /*!< STATN_CLEARVALUE_LO (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ODISC0 ========================================================= */ + #define R_ETHSW_ODISC0_ODISC_Pos (0UL) /*!< ODISC (Bit 0) */ + #define R_ETHSW_ODISC0_ODISC_Msk (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ODISC1 ========================================================= */ + #define R_ETHSW_ODISC1_ODISC_Pos (0UL) /*!< ODISC (Bit 0) */ + #define R_ETHSW_ODISC1_ODISC_Msk (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ODISC2 ========================================================= */ + #define R_ETHSW_ODISC2_ODISC_Pos (0UL) /*!< ODISC (Bit 0) */ + #define R_ETHSW_ODISC2_ODISC_Msk (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== ODISC3 ========================================================= */ + #define R_ETHSW_ODISC3_ODISC_Pos (0UL) /*!< ODISC (Bit 0) */ + #define R_ETHSW_ODISC3_ODISC_Msk (0xffffffffUL) /*!< ODISC (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_VLAN0 ====================================================== */ + #define R_ETHSW_IDISC_VLAN0_IDISC_VLAN_Pos (0UL) /*!< IDISC_VLAN (Bit 0) */ + #define R_ETHSW_IDISC_VLAN0_IDISC_VLAN_Msk (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_VLAN1 ====================================================== */ + #define R_ETHSW_IDISC_VLAN1_IDISC_VLAN_Pos (0UL) /*!< IDISC_VLAN (Bit 0) */ + #define R_ETHSW_IDISC_VLAN1_IDISC_VLAN_Msk (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_VLAN2 ====================================================== */ + #define R_ETHSW_IDISC_VLAN2_IDISC_VLAN_Pos (0UL) /*!< IDISC_VLAN (Bit 0) */ + #define R_ETHSW_IDISC_VLAN2_IDISC_VLAN_Msk (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_VLAN3 ====================================================== */ + #define R_ETHSW_IDISC_VLAN3_IDISC_VLAN_Pos (0UL) /*!< IDISC_VLAN (Bit 0) */ + #define R_ETHSW_IDISC_VLAN3_IDISC_VLAN_Msk (0xffffffffUL) /*!< IDISC_VLAN (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_UNTAGGED0 ==================================================== */ + #define R_ETHSW_IDISC_UNTAGGED0_IDISC_UNTAGGED_Pos (0UL) /*!< IDISC_UNTAGGED (Bit 0) */ + #define R_ETHSW_IDISC_UNTAGGED0_IDISC_UNTAGGED_Msk (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_UNTAGGED1 ==================================================== */ + #define R_ETHSW_IDISC_UNTAGGED1_IDISC_UNTAGGED_Pos (0UL) /*!< IDISC_UNTAGGED (Bit 0) */ + #define R_ETHSW_IDISC_UNTAGGED1_IDISC_UNTAGGED_Msk (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_UNTAGGED2 ==================================================== */ + #define R_ETHSW_IDISC_UNTAGGED2_IDISC_UNTAGGED_Pos (0UL) /*!< IDISC_UNTAGGED (Bit 0) */ + #define R_ETHSW_IDISC_UNTAGGED2_IDISC_UNTAGGED_Msk (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_UNTAGGED3 ==================================================== */ + #define R_ETHSW_IDISC_UNTAGGED3_IDISC_UNTAGGED_Pos (0UL) /*!< IDISC_UNTAGGED (Bit 0) */ + #define R_ETHSW_IDISC_UNTAGGED3_IDISC_UNTAGGED_Msk (0xffffffffUL) /*!< IDISC_UNTAGGED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_BLOCKED0 ===================================================== */ + #define R_ETHSW_IDISC_BLOCKED0_IDISC_BLOCKED_Pos (0UL) /*!< IDISC_BLOCKED (Bit 0) */ + #define R_ETHSW_IDISC_BLOCKED0_IDISC_BLOCKED_Msk (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_BLOCKED1 ===================================================== */ + #define R_ETHSW_IDISC_BLOCKED1_IDISC_BLOCKED_Pos (0UL) /*!< IDISC_BLOCKED (Bit 0) */ + #define R_ETHSW_IDISC_BLOCKED1_IDISC_BLOCKED_Msk (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_BLOCKED2 ===================================================== */ + #define R_ETHSW_IDISC_BLOCKED2_IDISC_BLOCKED_Pos (0UL) /*!< IDISC_BLOCKED (Bit 0) */ + #define R_ETHSW_IDISC_BLOCKED2_IDISC_BLOCKED_Msk (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== IDISC_BLOCKED3 ===================================================== */ + #define R_ETHSW_IDISC_BLOCKED3_IDISC_BLOCKED_Pos (0UL) /*!< IDISC_BLOCKED (Bit 0) */ + #define R_ETHSW_IDISC_BLOCKED3_IDISC_BLOCKED_Msk (0xffffffffUL) /*!< IDISC_BLOCKED (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_ANY0 ======================================================= */ + #define R_ETHSW_IDISC_ANY0_IDISC_ANY_Pos (0UL) /*!< IDISC_ANY (Bit 0) */ + #define R_ETHSW_IDISC_ANY0_IDISC_ANY_Msk (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_ANY1 ======================================================= */ + #define R_ETHSW_IDISC_ANY1_IDISC_ANY_Pos (0UL) /*!< IDISC_ANY (Bit 0) */ + #define R_ETHSW_IDISC_ANY1_IDISC_ANY_Msk (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_ANY2 ======================================================= */ + #define R_ETHSW_IDISC_ANY2_IDISC_ANY_Pos (0UL) /*!< IDISC_ANY (Bit 0) */ + #define R_ETHSW_IDISC_ANY2_IDISC_ANY_Msk (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== IDISC_ANY3 ======================================================= */ + #define R_ETHSW_IDISC_ANY3_IDISC_ANY_Pos (0UL) /*!< IDISC_ANY (Bit 0) */ + #define R_ETHSW_IDISC_ANY3_IDISC_ANY_Msk (0xffffffffUL) /*!< IDISC_ANY (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IDISC_SRCFLT0 ===================================================== */ + #define R_ETHSW_IDISC_SRCFLT0_IDISC_SRCFLT_Pos (0UL) /*!< IDISC_SRCFLT (Bit 0) */ + #define R_ETHSW_IDISC_SRCFLT0_IDISC_SRCFLT_Msk (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IDISC_SRCFLT1 ===================================================== */ + #define R_ETHSW_IDISC_SRCFLT1_IDISC_SRCFLT_Pos (0UL) /*!< IDISC_SRCFLT (Bit 0) */ + #define R_ETHSW_IDISC_SRCFLT1_IDISC_SRCFLT_Msk (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== IDISC_SRCFLT2 ===================================================== */ + #define R_ETHSW_IDISC_SRCFLT2_IDISC_SRCFLT_Pos (0UL) /*!< IDISC_SRCFLT (Bit 0) */ + #define R_ETHSW_IDISC_SRCFLT2_IDISC_SRCFLT_Msk (0xffffffffUL) /*!< IDISC_SRCFLT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TX_HOLD_REQ_CNT0 ==================================================== */ + #define R_ETHSW_TX_HOLD_REQ_CNT0_TX_HOLD_REQ_CNT_Pos (0UL) /*!< TX_HOLD_REQ_CNT (Bit 0) */ + #define R_ETHSW_TX_HOLD_REQ_CNT0_TX_HOLD_REQ_CNT_Msk (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TX_HOLD_REQ_CNT1 ==================================================== */ + #define R_ETHSW_TX_HOLD_REQ_CNT1_TX_HOLD_REQ_CNT_Pos (0UL) /*!< TX_HOLD_REQ_CNT (Bit 0) */ + #define R_ETHSW_TX_HOLD_REQ_CNT1_TX_HOLD_REQ_CNT_Msk (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TX_HOLD_REQ_CNT2 ==================================================== */ + #define R_ETHSW_TX_HOLD_REQ_CNT2_TX_HOLD_REQ_CNT_Pos (0UL) /*!< TX_HOLD_REQ_CNT (Bit 0) */ + #define R_ETHSW_TX_HOLD_REQ_CNT2_TX_HOLD_REQ_CNT_Msk (0xffffffffUL) /*!< TX_HOLD_REQ_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TX_FRAG_CNT0 ====================================================== */ + #define R_ETHSW_TX_FRAG_CNT0_TX_FRAG_CNT_Pos (0UL) /*!< TX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_TX_FRAG_CNT0_TX_FRAG_CNT_Msk (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TX_FRAG_CNT1 ====================================================== */ + #define R_ETHSW_TX_FRAG_CNT1_TX_FRAG_CNT_Pos (0UL) /*!< TX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_TX_FRAG_CNT1_TX_FRAG_CNT_Msk (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TX_FRAG_CNT2 ====================================================== */ + #define R_ETHSW_TX_FRAG_CNT2_TX_FRAG_CNT_Pos (0UL) /*!< TX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_TX_FRAG_CNT2_TX_FRAG_CNT_Msk (0xffffffffUL) /*!< TX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RX_FRAG_CNT0 ====================================================== */ + #define R_ETHSW_RX_FRAG_CNT0_RX_FRAG_CNT_Pos (0UL) /*!< RX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_RX_FRAG_CNT0_RX_FRAG_CNT_Msk (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RX_FRAG_CNT1 ====================================================== */ + #define R_ETHSW_RX_FRAG_CNT1_RX_FRAG_CNT_Pos (0UL) /*!< RX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_RX_FRAG_CNT1_RX_FRAG_CNT_Msk (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== RX_FRAG_CNT2 ====================================================== */ + #define R_ETHSW_RX_FRAG_CNT2_RX_FRAG_CNT_Pos (0UL) /*!< RX_FRAG_CNT (Bit 0) */ + #define R_ETHSW_RX_FRAG_CNT2_RX_FRAG_CNT_Msk (0xffffffffUL) /*!< RX_FRAG_CNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== RX_ASSY_OK_CNT0 ==================================================== */ + #define R_ETHSW_RX_ASSY_OK_CNT0_RX_ASSY_OK_CNT_Pos (0UL) /*!< RX_ASSY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_OK_CNT0_RX_ASSY_OK_CNT_Msk (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== RX_ASSY_OK_CNT1 ==================================================== */ + #define R_ETHSW_RX_ASSY_OK_CNT1_RX_ASSY_OK_CNT_Pos (0UL) /*!< RX_ASSY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_OK_CNT1_RX_ASSY_OK_CNT_Msk (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== RX_ASSY_OK_CNT2 ==================================================== */ + #define R_ETHSW_RX_ASSY_OK_CNT2_RX_ASSY_OK_CNT_Pos (0UL) /*!< RX_ASSY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_OK_CNT2_RX_ASSY_OK_CNT_Msk (0xffffffffUL) /*!< RX_ASSY_OK_CNT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== RX_ASSY_ERR_CNT0 ==================================================== */ + #define R_ETHSW_RX_ASSY_ERR_CNT0_RX_ASSY_ERR_CNT_Pos (0UL) /*!< RX_ASSY_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_ERR_CNT0_RX_ASSY_ERR_CNT_Msk (0xffffUL) /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* =================================================== RX_ASSY_ERR_CNT1 ==================================================== */ + #define R_ETHSW_RX_ASSY_ERR_CNT1_RX_ASSY_ERR_CNT_Pos (0UL) /*!< RX_ASSY_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_ERR_CNT1_RX_ASSY_ERR_CNT_Msk (0xffffUL) /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* =================================================== RX_ASSY_ERR_CNT2 ==================================================== */ + #define R_ETHSW_RX_ASSY_ERR_CNT2_RX_ASSY_ERR_CNT_Pos (0UL) /*!< RX_ASSY_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_ASSY_ERR_CNT2_RX_ASSY_ERR_CNT_Msk (0xffffUL) /*!< RX_ASSY_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== RX_SMD_ERR_CNT0 ==================================================== */ + #define R_ETHSW_RX_SMD_ERR_CNT0_RX_SMD_ERR_CNT_Pos (0UL) /*!< RX_SMD_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_SMD_ERR_CNT0_RX_SMD_ERR_CNT_Msk (0xffffUL) /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== RX_SMD_ERR_CNT1 ==================================================== */ + #define R_ETHSW_RX_SMD_ERR_CNT1_RX_SMD_ERR_CNT_Pos (0UL) /*!< RX_SMD_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_SMD_ERR_CNT1_RX_SMD_ERR_CNT_Msk (0xffffUL) /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* ==================================================== RX_SMD_ERR_CNT2 ==================================================== */ + #define R_ETHSW_RX_SMD_ERR_CNT2_RX_SMD_ERR_CNT_Pos (0UL) /*!< RX_SMD_ERR_CNT (Bit 0) */ + #define R_ETHSW_RX_SMD_ERR_CNT2_RX_SMD_ERR_CNT_Msk (0xffffUL) /*!< RX_SMD_ERR_CNT (Bitfield-Mask: 0xffff) */ +/* =================================================== TX_VERIFY_OK_CNT0 =================================================== */ + #define R_ETHSW_TX_VERIFY_OK_CNT0_TX_VERIFY_OK_CNT_Pos (0UL) /*!< TX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_VERIFY_OK_CNT0_TX_VERIFY_OK_CNT_Msk (0xffUL) /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== TX_VERIFY_OK_CNT1 =================================================== */ + #define R_ETHSW_TX_VERIFY_OK_CNT1_TX_VERIFY_OK_CNT_Pos (0UL) /*!< TX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_VERIFY_OK_CNT1_TX_VERIFY_OK_CNT_Msk (0xffUL) /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== TX_VERIFY_OK_CNT2 =================================================== */ + #define R_ETHSW_TX_VERIFY_OK_CNT2_TX_VERIFY_OK_CNT_Pos (0UL) /*!< TX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_VERIFY_OK_CNT2_TX_VERIFY_OK_CNT_Msk (0xffUL) /*!< TX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== TX_RESPONSE_OK_CNT0 ================================================== */ + #define R_ETHSW_TX_RESPONSE_OK_CNT0_TX_RESPONSE_OK_CNT_Pos (0UL) /*!< TX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_RESPONSE_OK_CNT0_TX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== TX_RESPONSE_OK_CNT1 ================================================== */ + #define R_ETHSW_TX_RESPONSE_OK_CNT1_TX_RESPONSE_OK_CNT_Pos (0UL) /*!< TX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_RESPONSE_OK_CNT1_TX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== TX_RESPONSE_OK_CNT2 ================================================== */ + #define R_ETHSW_TX_RESPONSE_OK_CNT2_TX_RESPONSE_OK_CNT_Pos (0UL) /*!< TX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_TX_RESPONSE_OK_CNT2_TX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< TX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== RX_VERIFY_OK_CNT0 =================================================== */ + #define R_ETHSW_RX_VERIFY_OK_CNT0_RX_VERIFY_OK_CNT_Pos (0UL) /*!< RX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_OK_CNT0_RX_VERIFY_OK_CNT_Msk (0xffUL) /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== RX_VERIFY_OK_CNT1 =================================================== */ + #define R_ETHSW_RX_VERIFY_OK_CNT1_RX_VERIFY_OK_CNT_Pos (0UL) /*!< RX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_OK_CNT1_RX_VERIFY_OK_CNT_Msk (0xffUL) /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* =================================================== RX_VERIFY_OK_CNT2 =================================================== */ + #define R_ETHSW_RX_VERIFY_OK_CNT2_RX_VERIFY_OK_CNT_Pos (0UL) /*!< RX_VERIFY_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_OK_CNT2_RX_VERIFY_OK_CNT_Msk (0xffUL) /*!< RX_VERIFY_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_RESPONSE_OK_CNT0 ================================================== */ + #define R_ETHSW_RX_RESPONSE_OK_CNT0_RX_RESPONSE_OK_CNT_Pos (0UL) /*!< RX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_OK_CNT0_RX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_RESPONSE_OK_CNT1 ================================================== */ + #define R_ETHSW_RX_RESPONSE_OK_CNT1_RX_RESPONSE_OK_CNT_Pos (0UL) /*!< RX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_OK_CNT1_RX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_RESPONSE_OK_CNT2 ================================================== */ + #define R_ETHSW_RX_RESPONSE_OK_CNT2_RX_RESPONSE_OK_CNT_Pos (0UL) /*!< RX_RESPONSE_OK_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_OK_CNT2_RX_RESPONSE_OK_CNT_Msk (0xffUL) /*!< RX_RESPONSE_OK_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_VERIFY_BAD_CNT0 =================================================== */ + #define R_ETHSW_RX_VERIFY_BAD_CNT0_RX_VERIFY_BAD_CNT_Pos (0UL) /*!< RX_VERIFY_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_BAD_CNT0_RX_VERIFY_BAD_CNT_Msk (0xffUL) /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_VERIFY_BAD_CNT1 =================================================== */ + #define R_ETHSW_RX_VERIFY_BAD_CNT1_RX_VERIFY_BAD_CNT_Pos (0UL) /*!< RX_VERIFY_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_BAD_CNT1_RX_VERIFY_BAD_CNT_Msk (0xffUL) /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ================================================== RX_VERIFY_BAD_CNT2 =================================================== */ + #define R_ETHSW_RX_VERIFY_BAD_CNT2_RX_VERIFY_BAD_CNT_Pos (0UL) /*!< RX_VERIFY_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_VERIFY_BAD_CNT2_RX_VERIFY_BAD_CNT_Msk (0xffUL) /*!< RX_VERIFY_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ================================================= RX_RESPONSE_BAD_CNT0 ================================================== */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT0_RX_RESPONSE_BAD_CNT_Pos (0UL) /*!< RX_RESPONSE_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT0_RX_RESPONSE_BAD_CNT_Msk (0xffUL) /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ================================================= RX_RESPONSE_BAD_CNT1 ================================================== */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT1_RX_RESPONSE_BAD_CNT_Pos (0UL) /*!< RX_RESPONSE_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT1_RX_RESPONSE_BAD_CNT_Msk (0xffUL) /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ================================================= RX_RESPONSE_BAD_CNT2 ================================================== */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT2_RX_RESPONSE_BAD_CNT_Pos (0UL) /*!< RX_RESPONSE_BAD_CNT (Bit 0) */ + #define R_ETHSW_RX_RESPONSE_BAD_CNT2_RX_RESPONSE_BAD_CNT_Msk (0xffUL) /*!< RX_RESPONSE_BAD_CNT (Bitfield-Mask: 0xff) */ +/* ===================================================== MMCTL_OUT_CT ====================================================== */ + #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_ENA_Pos (0UL) /*!< CT_OVR_ENA (Bit 0) */ + #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_ENA_Msk (0x7UL) /*!< CT_OVR_ENA (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_Pos (16UL) /*!< CT_OVR (Bit 16) */ + #define R_ETHSW_MMCTL_OUT_CT_CT_OVR_Msk (0x70000UL) /*!< CT_OVR (Bitfield-Mask: 0x07) */ +/* ================================================== MMCTL_CTFL_P0_3_ENA ================================================== */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P0_ENA_Pos (0UL) /*!< CTFL_P0_ENA (Bit 0) */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P0_ENA_Msk (0xffUL) /*!< CTFL_P0_ENA (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P1_ENA_Pos (8UL) /*!< CTFL_P1_ENA (Bit 8) */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P1_ENA_Msk (0xff00UL) /*!< CTFL_P1_ENA (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P2_ENA_Pos (16UL) /*!< CTFL_P2_ENA (Bit 16) */ + #define R_ETHSW_MMCTL_CTFL_P0_3_ENA_CTFL_P2_ENA_Msk (0xff0000UL) /*!< CTFL_P2_ENA (Bitfield-Mask: 0xff) */ +/* ============================================== MMCTL_YELLOW_BYTE_LENGTH_P =============================================== */ + #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Pos (2UL) /*!< YELLOW_LEN (Bit 2) */ + #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YELLOW_LEN_Msk (0xfffcUL) /*!< YELLOW_LEN (Bitfield-Mask: 0x3fff) */ + #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Pos (16UL) /*!< YLEN_EN (Bit 16) */ + #define R_ETHSW_MMCTL_YELLOW_BYTE_LENGTH_P_YLEN_EN_Msk (0x10000UL) /*!< YLEN_EN (Bitfield-Mask: 0x01) */ +/* ==================================================== MMCTL_POOL0_CTR ==================================================== */ + #define R_ETHSW_MMCTL_POOL0_CTR_CELLS_Pos (0UL) /*!< CELLS (Bit 0) */ + #define R_ETHSW_MMCTL_POOL0_CTR_CELLS_Msk (0x3ffUL) /*!< CELLS (Bitfield-Mask: 0x3ff) */ + #define R_ETHSW_MMCTL_POOL0_CTR_USED_Pos (16UL) /*!< USED (Bit 16) */ + #define R_ETHSW_MMCTL_POOL0_CTR_USED_Msk (0x3ff0000UL) /*!< USED (Bitfield-Mask: 0x3ff) */ +/* ==================================================== MMCTL_POOL1_CTR ==================================================== */ + #define R_ETHSW_MMCTL_POOL1_CTR_CELLS_Pos (0UL) /*!< CELLS (Bit 0) */ + #define R_ETHSW_MMCTL_POOL1_CTR_CELLS_Msk (0x3ffUL) /*!< CELLS (Bitfield-Mask: 0x3ff) */ + #define R_ETHSW_MMCTL_POOL1_CTR_USED_Pos (16UL) /*!< USED (Bit 16) */ + #define R_ETHSW_MMCTL_POOL1_CTR_USED_Msk (0x3ff0000UL) /*!< USED (Bitfield-Mask: 0x3ff) */ +/* =================================================== MMCTL_POOL_GLOBAL =================================================== */ + #define R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Pos (0UL) /*!< CELLS (Bit 0) */ + #define R_ETHSW_MMCTL_POOL_GLOBAL_CELLS_Msk (0x3ffUL) /*!< CELLS (Bitfield-Mask: 0x3ff) */ + #define R_ETHSW_MMCTL_POOL_GLOBAL_USED_Pos (16UL) /*!< USED (Bit 16) */ + #define R_ETHSW_MMCTL_POOL_GLOBAL_USED_Msk (0x3ff0000UL) /*!< USED (Bitfield-Mask: 0x3ff) */ +/* =================================================== MMCTL_POOL_STATUS =================================================== */ + #define R_ETHSW_MMCTL_POOL_STATUS_QUEUE_FULL_Pos (0UL) /*!< QUEUE_FULL (Bit 0) */ + #define R_ETHSW_MMCTL_POOL_STATUS_QUEUE_FULL_Msk (0xffUL) /*!< QUEUE_FULL (Bitfield-Mask: 0xff) */ +/* ==================================================== MMCTL_POOL_QMAP ==================================================== */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Pos (0UL) /*!< Q0_MAP (Bit 0) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q0_MAP_Msk (0x1UL) /*!< Q0_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Pos (3UL) /*!< Q0_ENA (Bit 3) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q0_ENA_Msk (0x8UL) /*!< Q0_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q1_MAP_Pos (4UL) /*!< Q1_MAP (Bit 4) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q1_MAP_Msk (0x10UL) /*!< Q1_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q1_ENA_Pos (7UL) /*!< Q1_ENA (Bit 7) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q1_ENA_Msk (0x80UL) /*!< Q1_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q2_MAP_Pos (8UL) /*!< Q2_MAP (Bit 8) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q2_MAP_Msk (0x100UL) /*!< Q2_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q2_ENA_Pos (11UL) /*!< Q2_ENA (Bit 11) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q2_ENA_Msk (0x800UL) /*!< Q2_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q3_MAP_Pos (12UL) /*!< Q3_MAP (Bit 12) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q3_MAP_Msk (0x1000UL) /*!< Q3_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q3_ENA_Pos (15UL) /*!< Q3_ENA (Bit 15) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q3_ENA_Msk (0x8000UL) /*!< Q3_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q4_MAP_Pos (16UL) /*!< Q4_MAP (Bit 16) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q4_MAP_Msk (0x10000UL) /*!< Q4_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q4_ENA_Pos (19UL) /*!< Q4_ENA (Bit 19) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q4_ENA_Msk (0x80000UL) /*!< Q4_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q5_MAP_Pos (20UL) /*!< Q5_MAP (Bit 20) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q5_MAP_Msk (0x100000UL) /*!< Q5_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q5_ENA_Pos (23UL) /*!< Q5_ENA (Bit 23) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q5_ENA_Msk (0x800000UL) /*!< Q5_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q6_MAP_Pos (24UL) /*!< Q6_MAP (Bit 24) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q6_MAP_Msk (0x1000000UL) /*!< Q6_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q6_ENA_Pos (27UL) /*!< Q6_ENA (Bit 27) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q6_ENA_Msk (0x8000000UL) /*!< Q6_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q7_MAP_Pos (28UL) /*!< Q7_MAP (Bit 28) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q7_MAP_Msk (0x10000000UL) /*!< Q7_MAP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q7_ENA_Pos (31UL) /*!< Q7_ENA (Bit 31) */ + #define R_ETHSW_MMCTL_POOL_QMAP_Q7_ENA_Msk (0x80000000UL) /*!< Q7_ENA (Bitfield-Mask: 0x01) */ +/* ====================================================== MMCTL_QGATE ====================================================== */ + #define R_ETHSW_MMCTL_QGATE_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MMCTL_QGATE_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Pos (16UL) /*!< QUEUE_GATE (Bit 16) */ + #define R_ETHSW_MMCTL_QGATE_QUEUE_GATE_Msk (0xffff0000UL) /*!< QUEUE_GATE (Bitfield-Mask: 0xffff) */ +/* ====================================================== MMCTL_QTRIG ====================================================== */ + #define R_ETHSW_MMCTL_QTRIG_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MMCTL_QTRIG_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MMCTL_QTRIG_QUEUE_TRIG_Pos (16UL) /*!< QUEUE_TRIG (Bit 16) */ + #define R_ETHSW_MMCTL_QTRIG_QUEUE_TRIG_Msk (0xff0000UL) /*!< QUEUE_TRIG (Bitfield-Mask: 0xff) */ +/* ===================================================== MMCTL_QFLUSH ====================================================== */ + #define R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Pos (0UL) /*!< PORT_MASK (Bit 0) */ + #define R_ETHSW_MMCTL_QFLUSH_PORT_MASK_Msk (0xfUL) /*!< PORT_MASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Pos (16UL) /*!< QUEUE_MASK (Bit 16) */ + #define R_ETHSW_MMCTL_QFLUSH_QUEUE_MASK_Msk (0xff0000UL) /*!< QUEUE_MASK (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_QFLUSH_ACTION_Pos (24UL) /*!< ACTION (Bit 24) */ + #define R_ETHSW_MMCTL_QFLUSH_ACTION_Msk (0x3000000UL) /*!< ACTION (Bitfield-Mask: 0x03) */ +/* =============================================== MMCTL_QCLOSED_STATUS_P0_3 =============================================== */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P0_STATUS_Pos (0UL) /*!< P0_STATUS (Bit 0) */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P0_STATUS_Msk (0xffUL) /*!< P0_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P1_STATUS_Pos (8UL) /*!< P1_STATUS (Bit 8) */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P1_STATUS_Msk (0xff00UL) /*!< P1_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P2_STATUS_Pos (16UL) /*!< P2_STATUS (Bit 16) */ + #define R_ETHSW_MMCTL_QCLOSED_STATUS_P0_3_P2_STATUS_Msk (0xff0000UL) /*!< P2_STATUS (Bitfield-Mask: 0xff) */ +/* ================================================== MMCTL_1FRAME_MODE_P ================================================== */ + #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_1FRAME_ENA_Pos (0UL) /*!< Q_1FRAME_ENA (Bit 0) */ + #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_1FRAME_ENA_Msk (0xffUL) /*!< Q_1FRAME_ENA (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_BUF_ENA_Pos (16UL) /*!< Q_BUF_ENA (Bit 16) */ + #define R_ETHSW_MMCTL_1FRAME_MODE_P_Q_BUF_ENA_Msk (0xff0000UL) /*!< Q_BUF_ENA (Bitfield-Mask: 0xff) */ +/* ================================================ MMCTL_P0_3_QUEUE_STATUS ================================================ */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P0_Q_STATUS_Pos (0UL) /*!< P0_Q_STATUS (Bit 0) */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P0_Q_STATUS_Msk (0xffUL) /*!< P0_Q_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P1_Q_STATUS_Pos (8UL) /*!< P1_Q_STATUS (Bit 8) */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P1_Q_STATUS_Msk (0xff00UL) /*!< P1_Q_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P2_Q_STATUS_Pos (16UL) /*!< P2_Q_STATUS (Bit 16) */ + #define R_ETHSW_MMCTL_P0_3_QUEUE_STATUS_P2_Q_STATUS_Msk (0xff0000UL) /*!< P2_Q_STATUS (Bitfield-Mask: 0xff) */ +/* ================================================ MMCTL_P0_3_FLUSH_STATUS ================================================ */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P0_F_STATUS_Pos (0UL) /*!< P0_F_STATUS (Bit 0) */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P0_F_STATUS_Msk (0xffUL) /*!< P0_F_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P1_F_STATUS_Pos (8UL) /*!< P1_F_STATUS (Bit 8) */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P1_F_STATUS_Msk (0xff00UL) /*!< P1_F_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P2_F_STATUS_Pos (16UL) /*!< P2_F_STATUS (Bit 16) */ + #define R_ETHSW_MMCTL_P0_3_FLUSH_STATUS_P2_F_STATUS_Msk (0xff0000UL) /*!< P2_F_STATUS (Bitfield-Mask: 0xff) */ +/* ================================================ MMCTL_DLY_QTRIGGER_CTRL ================================================ */ + #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_DELAY_TIME_Pos (0UL) /*!< DELAY_TIME (Bit 0) */ + #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_DELAY_TIME_Msk (0x3fffffffUL) /*!< DELAY_TIME (Bitfield-Mask: 0x3fffffff) */ + #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_TIMER_SEL_Pos (30UL) /*!< TIMER_SEL (Bit 30) */ + #define R_ETHSW_MMCTL_DLY_QTRIGGER_CTRL_TIMER_SEL_Msk (0x40000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ +/* ================================================= MMCTL_PREEMPT_QUEUES ================================================== */ + #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ENA_Pos (0UL) /*!< PREEMPT_ENA (Bit 0) */ + #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ENA_Msk (0xffUL) /*!< PREEMPT_ENA (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ON_QCLOSE_Pos (8UL) /*!< PREEMPT_ON_QCLOSE (Bit 8) */ + #define R_ETHSW_MMCTL_PREEMPT_QUEUES_PREEMPT_ON_QCLOSE_Msk (0xff00UL) /*!< PREEMPT_ON_QCLOSE (Bitfield-Mask: 0xff) */ +/* ================================================== MMCTL_HOLD_CONTROL =================================================== */ + #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Pos (0UL) /*!< Q_HOLD_REQ_FORCE (Bit 0) */ + #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_FORCE_Msk (0x7UL) /*!< Q_HOLD_REQ_FORCE (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Pos (16UL) /*!< Q_HOLD_REQ_RELEASE (Bit 16) */ + #define R_ETHSW_MMCTL_HOLD_CONTROL_Q_HOLD_REQ_RELEASE_Msk (0x70000UL) /*!< Q_HOLD_REQ_RELEASE (Bitfield-Mask: 0x07) */ +/* ================================================= MMCTL_PREEMPT_STATUS ================================================== */ + #define R_ETHSW_MMCTL_PREEMPT_STATUS_PREEMPT_STATE_Pos (0UL) /*!< PREEMPT_STATE (Bit 0) */ + #define R_ETHSW_MMCTL_PREEMPT_STATUS_PREEMPT_STATE_Msk (0x7UL) /*!< PREEMPT_STATE (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MMCTL_PREEMPT_STATUS_HOLD_REQ_STATE_Pos (16UL) /*!< HOLD_REQ_STATE (Bit 16) */ + #define R_ETHSW_MMCTL_PREEMPT_STATUS_HOLD_REQ_STATE_Msk (0x70000UL) /*!< HOLD_REQ_STATE (Bitfield-Mask: 0x07) */ +/* =================================================== MMCTL_CQF_CTRL_P ==================================================== */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_PRIO_ENABLE0_Pos (0UL) /*!< PRIO_ENABLE0 (Bit 0) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_PRIO_ENABLE0_Msk (0xffUL) /*!< PRIO_ENABLE0 (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Pos (8UL) /*!< QUEUE_SEL0 (Bit 8) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_QUEUE_SEL0_Msk (0x700UL) /*!< QUEUE_SEL0 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Pos (11UL) /*!< GATE_SEL0 (Bit 11) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_GATE_SEL0_Msk (0x3800UL) /*!< GATE_SEL0 (Bitfield-Mask: 0x07) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_USE_SOP0_Pos (14UL) /*!< USE_SOP0 (Bit 14) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_USE_SOP0_Msk (0x4000UL) /*!< USE_SOP0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_REF_SEL0_Pos (15UL) /*!< REF_SEL0 (Bit 15) */ + #define R_ETHSW_MMCTL_CQF_CTRL_P_REF_SEL0_Msk (0x8000UL) /*!< REF_SEL0 (Bitfield-Mask: 0x01) */ +/* ============================================== MMCTL_P0_3_QCLOSED_NONEMPTY ============================================== */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Pos (0UL) /*!< P0_Q_STATUS (Bit 0) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P0_Q_STATUS_Msk (0xffUL) /*!< P0_Q_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Pos (8UL) /*!< P1_Q_STATUS (Bit 8) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P1_Q_STATUS_Msk (0xff00UL) /*!< P1_Q_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Pos (16UL) /*!< P2_Q_STATUS (Bit 16) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P2_Q_STATUS_Msk (0xff0000UL) /*!< P2_Q_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Pos (24UL) /*!< P3_Q_STATUS (Bit 24) */ + #define R_ETHSW_MMCTL_P0_3_QCLOSED_NONEMPTY_P3_Q_STATUS_Msk (0xff000000UL) /*!< P3_Q_STATUS (Bitfield-Mask: 0xff) */ +/* ================================================== MMCTL_PREEMPT_EXTRA ================================================== */ + #define R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Pos (0UL) /*!< MIN_PFRM_ADJ (Bit 0) */ + #define R_ETHSW_MMCTL_PREEMPT_EXTRA_MIN_PFRM_ADJ_Msk (0xfUL) /*!< MIN_PFRM_ADJ (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Pos (4UL) /*!< LAST_PFRM_ADJ (Bit 4) */ + #define R_ETHSW_MMCTL_PREEMPT_EXTRA_LAST_PFRM_ADJ_Msk (0xf0UL) /*!< LAST_PFRM_ADJ (Bitfield-Mask: 0x0f) */ +/* ====================================================== DLR_CONTROL ====================================================== */ + #define R_ETHSW_DLR_CONTROL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ETHSW_DLR_CONTROL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_CONTROL_AUTOFLUSH_Pos (1UL) /*!< AUTOFLUSH (Bit 1) */ + #define R_ETHSW_DLR_CONTROL_AUTOFLUSH_Msk (0x2UL) /*!< AUTOFLUSH (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_CONTROL_LOOP_FILTER_ENA_Pos (2UL) /*!< LOOP_FILTER_ENA (Bit 2) */ + #define R_ETHSW_DLR_CONTROL_LOOP_FILTER_ENA_Msk (0x4UL) /*!< LOOP_FILTER_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_CONTROL_IGNORE_INVTM_Pos (4UL) /*!< IGNORE_INVTM (Bit 4) */ + #define R_ETHSW_DLR_CONTROL_IGNORE_INVTM_Msk (0x10UL) /*!< IGNORE_INVTM (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_CONTROL_US_TIME_Pos (8UL) /*!< US_TIME (Bit 8) */ + #define R_ETHSW_DLR_CONTROL_US_TIME_Msk (0xfff00UL) /*!< US_TIME (Bitfield-Mask: 0xfff) */ +/* ====================================================== DLR_STATUS ======================================================= */ + #define R_ETHSW_DLR_STATUS_LastBcnRcvPort_Pos (0UL) /*!< LastBcnRcvPort (Bit 0) */ + #define R_ETHSW_DLR_STATUS_LastBcnRcvPort_Msk (0x3UL) /*!< LastBcnRcvPort (Bitfield-Mask: 0x03) */ + #define R_ETHSW_DLR_STATUS_NODE_STATE_Pos (8UL) /*!< NODE_STATE (Bit 8) */ + #define R_ETHSW_DLR_STATUS_NODE_STATE_Msk (0xff00UL) /*!< NODE_STATE (Bitfield-Mask: 0xff) */ + #define R_ETHSW_DLR_STATUS_LINK_STATUS_Pos (16UL) /*!< LINK_STATUS (Bit 16) */ + #define R_ETHSW_DLR_STATUS_LINK_STATUS_Msk (0x30000UL) /*!< LINK_STATUS (Bitfield-Mask: 0x03) */ + #define R_ETHSW_DLR_STATUS_TOPOLOGY_Pos (24UL) /*!< TOPOLOGY (Bit 24) */ + #define R_ETHSW_DLR_STATUS_TOPOLOGY_Msk (0xff000000UL) /*!< TOPOLOGY (Bitfield-Mask: 0xff) */ +/* ====================================================== DLR_ETH_TYP ====================================================== */ + #define R_ETHSW_DLR_ETH_TYP_DLR_ETH_TYP_Pos (0UL) /*!< DLR_ETH_TYP (Bit 0) */ + #define R_ETHSW_DLR_ETH_TYP_DLR_ETH_TYP_Msk (0xffffUL) /*!< DLR_ETH_TYP (Bitfield-Mask: 0xffff) */ +/* ==================================================== DLR_IRQ_CONTROL ==================================================== */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Pos (0UL) /*!< IRQ_state_chng_ena (Bit 0) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_state_chng_ena_Msk (0x1UL) /*!< IRQ_state_chng_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_flush_macaddr_ena_Pos (1UL) /*!< IRQ_flush_macaddr_ena (Bit 1) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_flush_macaddr_ena_Msk (0x2UL) /*!< IRQ_flush_macaddr_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk0_ena_Pos (2UL) /*!< IRQ_stop_nbchk0_ena (Bit 2) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk0_ena_Msk (0x4UL) /*!< IRQ_stop_nbchk0_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk1_ena_Pos (3UL) /*!< IRQ_stop_nbchk1_ena (Bit 3) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_stop_nbchk1_ena_Msk (0x8UL) /*!< IRQ_stop_nbchk1_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Pos (4UL) /*!< IRQ_bec_tmr0_exp_ena (Bit 4) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr0_exp_ena_Msk (0x10UL) /*!< IRQ_bec_tmr0_exp_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Pos (5UL) /*!< IRQ_bec_tmr1_exp_ena (Bit 5) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_tmr1_exp_ena_Msk (0x20UL) /*!< IRQ_bec_tmr1_exp_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Pos (6UL) /*!< IRQ_supr_chng_ena (Bit 6) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_supr_chng_ena_Msk (0x40UL) /*!< IRQ_supr_chng_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Pos (7UL) /*!< IRQ_link_chng0_ena (Bit 7) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng0_ena_Msk (0x80UL) /*!< IRQ_link_chng0_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Pos (8UL) /*!< IRQ_link_chng1_ena (Bit 8) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_link_chng1_ena_Msk (0x100UL) /*!< IRQ_link_chng1_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_sup_ignord_ena_Pos (9UL) /*!< IRQ_sup_ignord_ena (Bit 9) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_sup_ignord_ena_Msk (0x200UL) /*!< IRQ_sup_ignord_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_ip_addr_chng_ena_Pos (10UL) /*!< IRQ_ip_addr_chng_ena (Bit 10) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_ip_addr_chng_ena_Msk (0x400UL) /*!< IRQ_ip_addr_chng_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_invalid_tmr_ena_Pos (11UL) /*!< IRQ_invalid_tmr_ena (Bit 11) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_invalid_tmr_ena_Msk (0x800UL) /*!< IRQ_invalid_tmr_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Pos (12UL) /*!< IRQ_bec_rcv0_ena (Bit 12) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv0_ena_Msk (0x1000UL) /*!< IRQ_bec_rcv0_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Pos (13UL) /*!< IRQ_bec_rcv1_ena (Bit 13) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_bec_rcv1_ena_Msk (0x2000UL) /*!< IRQ_bec_rcv1_ena (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Pos (14UL) /*!< IRQ_frm_dscrd0 (Bit 14) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd0_Msk (0x4000UL) /*!< IRQ_frm_dscrd0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Pos (15UL) /*!< IRQ_frm_dscrd1 (Bit 15) */ + #define R_ETHSW_DLR_IRQ_CONTROL_IRQ_frm_dscrd1_Msk (0x8000UL) /*!< IRQ_frm_dscrd1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_low_int_en_Pos (29UL) /*!< low_int_en (Bit 29) */ + #define R_ETHSW_DLR_IRQ_CONTROL_low_int_en_Msk (0x20000000UL) /*!< low_int_en (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_atomic_OR_Pos (30UL) /*!< atomic_OR (Bit 30) */ + #define R_ETHSW_DLR_IRQ_CONTROL_atomic_OR_Msk (0x40000000UL) /*!< atomic_OR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_CONTROL_atomic_AND_Pos (31UL) /*!< atomic_AND (Bit 31) */ + #define R_ETHSW_DLR_IRQ_CONTROL_atomic_AND_Msk (0x80000000UL) /*!< atomic_AND (Bitfield-Mask: 0x01) */ +/* =================================================== DLR_IRQ_STAT_ACK ==================================================== */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_state_chng_IRQ_pending_Pos (0UL) /*!< state_chng_IRQ_pending (Bit 0) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_state_chng_IRQ_pending_Msk (0x1UL) /*!< state_chng_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_flush_IRQ_pending_Pos (1UL) /*!< flush_IRQ_pending (Bit 1) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_flush_IRQ_pending_Msk (0x2UL) /*!< flush_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk0_IRQ_pending_Pos (2UL) /*!< nbchk0_IRQ_pending (Bit 2) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk0_IRQ_pending_Msk (0x4UL) /*!< nbchk0_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk1_IRQ_pending_Pos (3UL) /*!< nbchk1_IRQ_pending (Bit 3) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_nbchk1_IRQ_pending_Msk (0x8UL) /*!< nbchk1_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr0_IRQ_pending_Pos (4UL) /*!< bec_tmr0_IRQ_pending (Bit 4) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr0_IRQ_pending_Msk (0x10UL) /*!< bec_tmr0_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr1_IRQ_pending_Pos (5UL) /*!< bec_tmr1_IRQ_pending (Bit 5) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_tmr1_IRQ_pending_Msk (0x20UL) /*!< bec_tmr1_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_supr_chng_IRQ_pending_Pos (6UL) /*!< supr_chng_IRQ_pending (Bit 6) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_supr_chng_IRQ_pending_Msk (0x40UL) /*!< supr_chng_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_Link0_IRQ_pending_Pos (7UL) /*!< Link0_IRQ_pending (Bit 7) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_Link0_IRQ_pending_Msk (0x80UL) /*!< Link0_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_Link1_IRQ_pending_Pos (8UL) /*!< Link1_IRQ_pending (Bit 8) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_Link1_IRQ_pending_Msk (0x100UL) /*!< Link1_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_sup_ignord_IRQ_pending_Pos (9UL) /*!< sup_ignord_IRQ_pending (Bit 9) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_sup_ignord_IRQ_pending_Msk (0x200UL) /*!< sup_ignord_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_ip_chng_IRQ_pending_Pos (10UL) /*!< ip_chng_IRQ_pending (Bit 10) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_ip_chng_IRQ_pending_Msk (0x400UL) /*!< ip_chng_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_invalid_tmr_IRQ_pending_Pos (11UL) /*!< invalid_tmr_IRQ_pending (Bit 11) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_invalid_tmr_IRQ_pending_Msk (0x800UL) /*!< invalid_tmr_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv0_IRQ_pending_Pos (12UL) /*!< bec_rcv0_IRQ_pending (Bit 12) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv0_IRQ_pending_Msk (0x1000UL) /*!< bec_rcv0_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv1_IRQ_pending_Pos (13UL) /*!< bec_rcv1_IRQ_pending (Bit 13) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_bec_rcv1_IRQ_pending_Msk (0x2000UL) /*!< bec_rcv1_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd0_IRQ_pending_Pos (14UL) /*!< frm_dscrd0_IRQ_pending (Bit 14) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd0_IRQ_pending_Msk (0x4000UL) /*!< frm_dscrd0_IRQ_pending (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd1_IRQ_pending_Pos (15UL) /*!< frm_dscrd1_IRQ_pending (Bit 15) */ + #define R_ETHSW_DLR_IRQ_STAT_ACK_frm_dscrd1_IRQ_pending_Msk (0x8000UL) /*!< frm_dscrd1_IRQ_pending (Bitfield-Mask: 0x01) */ +/* ===================================================== DLR_LOC_MAClo ===================================================== */ + #define R_ETHSW_DLR_LOC_MAClo_LOC_MAC_Pos (0UL) /*!< LOC_MAC (Bit 0) */ + #define R_ETHSW_DLR_LOC_MAClo_LOC_MAC_Msk (0xffffffffUL) /*!< LOC_MAC (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DLR_LOC_MAChi ===================================================== */ + #define R_ETHSW_DLR_LOC_MAChi_LOC_MAC_Pos (0UL) /*!< LOC_MAC (Bit 0) */ + #define R_ETHSW_DLR_LOC_MAChi_LOC_MAC_Msk (0xffffUL) /*!< LOC_MAC (Bitfield-Mask: 0xffff) */ +/* ==================================================== DLR_SUPR_MAClo ===================================================== */ + #define R_ETHSW_DLR_SUPR_MAClo_SUPR_MAC_Pos (0UL) /*!< SUPR_MAC (Bit 0) */ + #define R_ETHSW_DLR_SUPR_MAClo_SUPR_MAC_Msk (0xffffffffUL) /*!< SUPR_MAC (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DLR_SUPR_MAChi ===================================================== */ + #define R_ETHSW_DLR_SUPR_MAChi_SUPR_MAC_Pos (0UL) /*!< SUPR_MAC (Bit 0) */ + #define R_ETHSW_DLR_SUPR_MAChi_SUPR_MAC_Msk (0xffffUL) /*!< SUPR_MAC (Bitfield-Mask: 0xffff) */ + #define R_ETHSW_DLR_SUPR_MAChi_PRECE_Pos (16UL) /*!< PRECE (Bit 16) */ + #define R_ETHSW_DLR_SUPR_MAChi_PRECE_Msk (0xff0000UL) /*!< PRECE (Bitfield-Mask: 0xff) */ +/* ==================================================== DLR_STATE_VLAN ===================================================== */ + #define R_ETHSW_DLR_STATE_VLAN_RINGSTAT_Pos (0UL) /*!< RINGSTAT (Bit 0) */ + #define R_ETHSW_DLR_STATE_VLAN_RINGSTAT_Msk (0xffUL) /*!< RINGSTAT (Bitfield-Mask: 0xff) */ + #define R_ETHSW_DLR_STATE_VLAN_VLANVALID_Pos (8UL) /*!< VLANVALID (Bit 8) */ + #define R_ETHSW_DLR_STATE_VLAN_VLANVALID_Msk (0x100UL) /*!< VLANVALID (Bitfield-Mask: 0x01) */ + #define R_ETHSW_DLR_STATE_VLAN_VLANINFO_Pos (16UL) /*!< VLANINFO (Bit 16) */ + #define R_ETHSW_DLR_STATE_VLAN_VLANINFO_Msk (0xffff0000UL) /*!< VLANINFO (Bitfield-Mask: 0xffff) */ +/* ===================================================== DLR_BEC_TMOUT ===================================================== */ + #define R_ETHSW_DLR_BEC_TMOUT_BEC_TMOUT_Pos (0UL) /*!< BEC_TMOUT (Bit 0) */ + #define R_ETHSW_DLR_BEC_TMOUT_BEC_TMOUT_Msk (0xffffffffUL) /*!< BEC_TMOUT (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DLR_BEC_INTRVL ===================================================== */ + #define R_ETHSW_DLR_BEC_INTRVL_BEC_INTRVL_Pos (0UL) /*!< BEC_INTRVL (Bit 0) */ + #define R_ETHSW_DLR_BEC_INTRVL_BEC_INTRVL_Msk (0xffffffffUL) /*!< BEC_INTRVL (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DLR_SUPR_IPADR ===================================================== */ + #define R_ETHSW_DLR_SUPR_IPADR_SUPR_IPADR_Pos (0UL) /*!< SUPR_IPADR (Bit 0) */ + #define R_ETHSW_DLR_SUPR_IPADR_SUPR_IPADR_Msk (0xffffffffUL) /*!< SUPR_IPADR (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DLR_ETH_STYP_VER ==================================================== */ + #define R_ETHSW_DLR_ETH_STYP_VER_SUBTYPE_Pos (0UL) /*!< SUBTYPE (Bit 0) */ + #define R_ETHSW_DLR_ETH_STYP_VER_SUBTYPE_Msk (0xffUL) /*!< SUBTYPE (Bitfield-Mask: 0xff) */ + #define R_ETHSW_DLR_ETH_STYP_VER_PROTVER_Pos (8UL) /*!< PROTVER (Bit 8) */ + #define R_ETHSW_DLR_ETH_STYP_VER_PROTVER_Msk (0xff00UL) /*!< PROTVER (Bitfield-Mask: 0xff) */ + #define R_ETHSW_DLR_ETH_STYP_VER_SPORT_Pos (16UL) /*!< SPORT (Bit 16) */ + #define R_ETHSW_DLR_ETH_STYP_VER_SPORT_Msk (0xff0000UL) /*!< SPORT (Bitfield-Mask: 0xff) */ +/* ===================================================== DLR_INV_TMOUT ===================================================== */ + #define R_ETHSW_DLR_INV_TMOUT_INV_TMOUT_Pos (0UL) /*!< INV_TMOUT (Bit 0) */ + #define R_ETHSW_DLR_INV_TMOUT_INV_TMOUT_Msk (0xffffffffUL) /*!< INV_TMOUT (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== DLR_SEQ_ID ======================================================= */ + #define R_ETHSW_DLR_SEQ_ID_SEQ_ID_Pos (0UL) /*!< SEQ_ID (Bit 0) */ + #define R_ETHSW_DLR_SEQ_ID_SEQ_ID_Msk (0xffffffffUL) /*!< SEQ_ID (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DLR_DSTlo ======================================================= */ + #define R_ETHSW_DLR_DSTlo_DLR_DST_Pos (0UL) /*!< DLR_DST (Bit 0) */ + #define R_ETHSW_DLR_DSTlo_DLR_DST_Msk (0xffffffffUL) /*!< DLR_DST (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= DLR_DSThi ======================================================= */ + #define R_ETHSW_DLR_DSThi_DLR_DST_Pos (0UL) /*!< DLR_DST (Bit 0) */ + #define R_ETHSW_DLR_DSThi_DLR_DST_Msk (0xffffUL) /*!< DLR_DST (Bitfield-Mask: 0xffff) */ +/* ===================================================== DLR_RX_STAT0 ====================================================== */ + #define R_ETHSW_DLR_RX_STAT0_RX_STAT0_Pos (0UL) /*!< RX_STAT0 (Bit 0) */ + #define R_ETHSW_DLR_RX_STAT0_RX_STAT0_Msk (0xffffffffUL) /*!< RX_STAT0 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DLR_RX_ERR_STAT0 ==================================================== */ + #define R_ETHSW_DLR_RX_ERR_STAT0_RX_ERR_STAT0_Pos (0UL) /*!< RX_ERR_STAT0 (Bit 0) */ + #define R_ETHSW_DLR_RX_ERR_STAT0_RX_ERR_STAT0_Msk (0xffffffffUL) /*!< RX_ERR_STAT0 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DLR_RX_LF_STAT0 ==================================================== */ + #define R_ETHSW_DLR_RX_LF_STAT0_RX_LF_STAT0_Pos (0UL) /*!< RX_LF_STAT0 (Bit 0) */ + #define R_ETHSW_DLR_RX_LF_STAT0_RX_LF_STAT0_Msk (0xffUL) /*!< RX_LF_STAT0 (Bitfield-Mask: 0xff) */ +/* ===================================================== DLR_RX_STAT1 ====================================================== */ + #define R_ETHSW_DLR_RX_STAT1_RX_STAT1_Pos (0UL) /*!< RX_STAT1 (Bit 0) */ + #define R_ETHSW_DLR_RX_STAT1_RX_STAT1_Msk (0xffffffffUL) /*!< RX_STAT1 (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DLR_RX_ERR_STAT1 ==================================================== */ + #define R_ETHSW_DLR_RX_ERR_STAT1_RX_ERR_STAT1_Pos (0UL) /*!< RX_ERR_STAT1 (Bit 0) */ + #define R_ETHSW_DLR_RX_ERR_STAT1_RX_ERR_STAT1_Msk (0xffffffffUL) /*!< RX_ERR_STAT1 (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DLR_RX_LF_STAT1 ==================================================== */ + #define R_ETHSW_DLR_RX_LF_STAT1_RX_LF_STAT1_Pos (0UL) /*!< RX_LF_STAT1 (Bit 0) */ + #define R_ETHSW_DLR_RX_LF_STAT1_RX_LF_STAT1_Msk (0xffUL) /*!< RX_LF_STAT1 (Bitfield-Mask: 0xff) */ +/* ====================================================== PRP_CONFIG ======================================================= */ + #define R_ETHSW_PRP_CONFIG_PRP_ENA_Pos (0UL) /*!< PRP_ENA (Bit 0) */ + #define R_ETHSW_PRP_CONFIG_PRP_ENA_Msk (0x1UL) /*!< PRP_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_RX_DUP_ACCEPT_Pos (1UL) /*!< RX_DUP_ACCEPT (Bit 1) */ + #define R_ETHSW_PRP_CONFIG_RX_DUP_ACCEPT_Msk (0x2UL) /*!< RX_DUP_ACCEPT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_RX_REMOVE_RCT_Pos (2UL) /*!< RX_REMOVE_RCT (Bit 2) */ + #define R_ETHSW_PRP_CONFIG_RX_REMOVE_RCT_Msk (0x4UL) /*!< RX_REMOVE_RCT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_MODE_Pos (3UL) /*!< TX_RCT_MODE (Bit 3) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_MODE_Msk (0x18UL) /*!< TX_RCT_MODE (Bitfield-Mask: 0x03) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_BROADCAST_Pos (5UL) /*!< TX_RCT_BROADCAST (Bit 5) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_BROADCAST_Msk (0x20UL) /*!< TX_RCT_BROADCAST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_MULTICAST_Pos (6UL) /*!< TX_RCT_MULTICAST (Bit 6) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_MULTICAST_Msk (0x40UL) /*!< TX_RCT_MULTICAST (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_UNKNOWN_Pos (7UL) /*!< TX_RCT_UNKNOWN (Bit 7) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_UNKNOWN_Msk (0x80UL) /*!< TX_RCT_UNKNOWN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_1588_Pos (8UL) /*!< TX_RCT_1588 (Bit 8) */ + #define R_ETHSW_PRP_CONFIG_TX_RCT_1588_Msk (0x100UL) /*!< TX_RCT_1588 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_RCT_LEN_CHK_DIS_Pos (9UL) /*!< RCT_LEN_CHK_DIS (Bit 9) */ + #define R_ETHSW_PRP_CONFIG_RCT_LEN_CHK_DIS_Msk (0x200UL) /*!< RCT_LEN_CHK_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_CONFIG_PRP_AGE_ENA_Pos (16UL) /*!< PRP_AGE_ENA (Bit 16) */ + #define R_ETHSW_PRP_CONFIG_PRP_AGE_ENA_Msk (0x10000UL) /*!< PRP_AGE_ENA (Bitfield-Mask: 0x01) */ +/* ======================================================= PRP_GROUP ======================================================= */ + #define R_ETHSW_PRP_GROUP_PRP_GROUP_Pos (0UL) /*!< PRP_GROUP (Bit 0) */ + #define R_ETHSW_PRP_GROUP_PRP_GROUP_Msk (0x7UL) /*!< PRP_GROUP (Bitfield-Mask: 0x07) */ + #define R_ETHSW_PRP_GROUP_LANB_MASK_Pos (16UL) /*!< LANB_MASK (Bit 16) */ + #define R_ETHSW_PRP_GROUP_LANB_MASK_Msk (0x70000UL) /*!< LANB_MASK (Bitfield-Mask: 0x07) */ +/* ====================================================== PRP_SUFFIX ======================================================= */ + #define R_ETHSW_PRP_SUFFIX_PRP_SUFFIX_Pos (0UL) /*!< PRP_SUFFIX (Bit 0) */ + #define R_ETHSW_PRP_SUFFIX_PRP_SUFFIX_Msk (0xffffUL) /*!< PRP_SUFFIX (Bitfield-Mask: 0xffff) */ +/* ======================================================= PRP_LANID ======================================================= */ + #define R_ETHSW_PRP_LANID_LANAID_Pos (0UL) /*!< LANAID (Bit 0) */ + #define R_ETHSW_PRP_LANID_LANAID_Msk (0xfUL) /*!< LANAID (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_PRP_LANID_LANBID_Pos (4UL) /*!< LANBID (Bit 4) */ + #define R_ETHSW_PRP_LANID_LANBID_Msk (0xf0UL) /*!< LANBID (Bitfield-Mask: 0x0f) */ +/* ========================================================= DUP_W ========================================================= */ + #define R_ETHSW_DUP_W_DUP_W_Pos (0UL) /*!< DUP_W (Bit 0) */ + #define R_ETHSW_DUP_W_DUP_W_Msk (0xffUL) /*!< DUP_W (Bitfield-Mask: 0xff) */ +/* ====================================================== PRP_AGETIME ====================================================== */ + #define R_ETHSW_PRP_AGETIME_PRP_AGETIME_Pos (0UL) /*!< PRP_AGETIME (Bit 0) */ + #define R_ETHSW_PRP_AGETIME_PRP_AGETIME_Msk (0xffffffUL) /*!< PRP_AGETIME (Bitfield-Mask: 0xffffff) */ +/* ==================================================== PRP_IRQ_CONTROL ==================================================== */ + #define R_ETHSW_PRP_IRQ_CONTROL_MEMTOOLATE_Pos (0UL) /*!< MEMTOOLATE (Bit 0) */ + #define R_ETHSW_PRP_IRQ_CONTROL_MEMTOOLATE_Msk (0x1UL) /*!< MEMTOOLATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_CONTROL_WRONGLAN_Pos (1UL) /*!< WRONGLAN (Bit 1) */ + #define R_ETHSW_PRP_IRQ_CONTROL_WRONGLAN_Msk (0x2UL) /*!< WRONGLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_CONTROL_OUTOFSEQ_Pos (2UL) /*!< OUTOFSEQ (Bit 2) */ + #define R_ETHSW_PRP_IRQ_CONTROL_OUTOFSEQ_Msk (0x4UL) /*!< OUTOFSEQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_CONTROL_SEQMISSING_Pos (3UL) /*!< SEQMISSING (Bit 3) */ + #define R_ETHSW_PRP_IRQ_CONTROL_SEQMISSING_Msk (0x8UL) /*!< SEQMISSING (Bitfield-Mask: 0x01) */ +/* =================================================== PRP_IRQ_STAT_ACK ==================================================== */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_MEMTOOLATE_Pos (0UL) /*!< MEMTOOLATE (Bit 0) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_MEMTOOLATE_Msk (0x1UL) /*!< MEMTOOLATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_WRONGLAN_Pos (1UL) /*!< WRONGLAN (Bit 1) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_WRONGLAN_Msk (0x2UL) /*!< WRONGLAN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_OUTOFSEQ_Pos (2UL) /*!< OUTOFSEQ (Bit 2) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_OUTOFSEQ_Msk (0x4UL) /*!< OUTOFSEQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_SEQMISSING_Pos (3UL) /*!< SEQMISSING (Bit 3) */ + #define R_ETHSW_PRP_IRQ_STAT_ACK_SEQMISSING_Msk (0x8UL) /*!< SEQMISSING (Bitfield-Mask: 0x01) */ +/* ===================================================== RM_ADDR_CTRL ====================================================== */ + #define R_ETHSW_RM_ADDR_CTRL_address_Pos (0UL) /*!< address (Bit 0) */ + #define R_ETHSW_RM_ADDR_CTRL_address_Msk (0xfffUL) /*!< address (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_DYNAMIC_Pos (22UL) /*!< CLEAR_DYNAMIC (Bit 22) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_DYNAMIC_Msk (0x400000UL) /*!< CLEAR_DYNAMIC (Bitfield-Mask: 0x01) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_MEMORY_Pos (23UL) /*!< CLEAR_MEMORY (Bit 23) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_MEMORY_Msk (0x800000UL) /*!< CLEAR_MEMORY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_RM_ADDR_CTRL_WRITE_Pos (25UL) /*!< WRITE (Bit 25) */ + #define R_ETHSW_RM_ADDR_CTRL_WRITE_Msk (0x2000000UL) /*!< WRITE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_RM_ADDR_CTRL_READ_Pos (26UL) /*!< READ (Bit 26) */ + #define R_ETHSW_RM_ADDR_CTRL_READ_Msk (0x4000000UL) /*!< READ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_Pos (29UL) /*!< CLEAR (Bit 29) */ + #define R_ETHSW_RM_ADDR_CTRL_CLEAR_Msk (0x20000000UL) /*!< CLEAR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_RM_ADDR_CTRL_BUSY_Pos (31UL) /*!< BUSY (Bit 31) */ + #define R_ETHSW_RM_ADDR_CTRL_BUSY_Msk (0x80000000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== RM_DATA ======================================================== */ + #define R_ETHSW_RM_DATA_RM_DATA_Pos (0UL) /*!< RM_DATA (Bit 0) */ + #define R_ETHSW_RM_DATA_RM_DATA_Msk (0xffffffffUL) /*!< RM_DATA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== RM_DATA_HI ======================================================= */ + #define R_ETHSW_RM_DATA_HI_RM_DATA_HI_Pos (0UL) /*!< RM_DATA_HI (Bit 0) */ + #define R_ETHSW_RM_DATA_HI_RM_DATA_HI_Msk (0xffffffffUL) /*!< RM_DATA_HI (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= RM_STATUS ======================================================= */ + #define R_ETHSW_RM_STATUS_ageaddress_Pos (0UL) /*!< ageaddress (Bit 0) */ + #define R_ETHSW_RM_STATUS_ageaddress_Msk (0xfffUL) /*!< ageaddress (Bitfield-Mask: 0xfff) */ +/* ===================================================== TxSeqTooLate ====================================================== */ + #define R_ETHSW_TxSeqTooLate_TxSeqTooLate_Pos (0UL) /*!< TxSeqTooLate (Bit 0) */ + #define R_ETHSW_TxSeqTooLate_TxSeqTooLate_Msk (0xfUL) /*!< TxSeqTooLate (Bitfield-Mask: 0x0f) */ +/* ==================================================== CntErrWrongLanA ==================================================== */ + #define R_ETHSW_CntErrWrongLanA_CntErrWrongLanA_Pos (0UL) /*!< CntErrWrongLanA (Bit 0) */ + #define R_ETHSW_CntErrWrongLanA_CntErrWrongLanA_Msk (0xffffffffUL) /*!< CntErrWrongLanA (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CntErrWrongLanB ==================================================== */ + #define R_ETHSW_CntErrWrongLanB_CntErrWrongLanB_Pos (0UL) /*!< CntErrWrongLanB (Bit 0) */ + #define R_ETHSW_CntErrWrongLanB_CntErrWrongLanB_Msk (0xffffffffUL) /*!< CntErrWrongLanB (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CntDupLanA ======================================================= */ + #define R_ETHSW_CntDupLanA_CntDupLanA_Pos (0UL) /*!< CntDupLanA (Bit 0) */ + #define R_ETHSW_CntDupLanA_CntDupLanA_Msk (0xffffffffUL) /*!< CntDupLanA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CntDupLanB ======================================================= */ + #define R_ETHSW_CntDupLanB_CntDupLanB_Pos (0UL) /*!< CntDupLanB (Bit 0) */ + #define R_ETHSW_CntDupLanB_CntDupLanB_Msk (0xffffffffUL) /*!< CntDupLanB (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CntOutOfSeqLowA ==================================================== */ + #define R_ETHSW_CntOutOfSeqLowA_CntOutOfSeqLowA_Pos (0UL) /*!< CntOutOfSeqLowA (Bit 0) */ + #define R_ETHSW_CntOutOfSeqLowA_CntOutOfSeqLowA_Msk (0xffffffffUL) /*!< CntOutOfSeqLowA (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== CntOutOfSeqLowB ==================================================== */ + #define R_ETHSW_CntOutOfSeqLowB_CntOutOfSeqLowB_Pos (0UL) /*!< CntOutOfSeqLowB (Bit 0) */ + #define R_ETHSW_CntOutOfSeqLowB_CntOutOfSeqLowB_Msk (0xffffffffUL) /*!< CntOutOfSeqLowB (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CntOutOfSeqA ====================================================== */ + #define R_ETHSW_CntOutOfSeqA_CntOutOfSeqA_Pos (0UL) /*!< CntOutOfSeqA (Bit 0) */ + #define R_ETHSW_CntOutOfSeqA_CntOutOfSeqA_Msk (0xffffffffUL) /*!< CntOutOfSeqA (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== CntOutOfSeqB ====================================================== */ + #define R_ETHSW_CntOutOfSeqB_CntOutOfSeqB_Pos (0UL) /*!< CntOutOfSeqB (Bit 0) */ + #define R_ETHSW_CntOutOfSeqB_CntOutOfSeqB_Msk (0xffffffffUL) /*!< CntOutOfSeqB (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CntAcceptA ======================================================= */ + #define R_ETHSW_CntAcceptA_CntAcceptA_Pos (0UL) /*!< CntAcceptA (Bit 0) */ + #define R_ETHSW_CntAcceptA_CntAcceptA_Msk (0xffffffffUL) /*!< CntAcceptA (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CntAcceptB ======================================================= */ + #define R_ETHSW_CntAcceptB_CntAcceptB_Pos (0UL) /*!< CntAcceptB (Bit 0) */ + #define R_ETHSW_CntAcceptB_CntAcceptB_Msk (0xffffffffUL) /*!< CntAcceptB (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== CntMissing ======================================================= */ + #define R_ETHSW_CntMissing_CntMissing_Pos (0UL) /*!< CntMissing (Bit 0) */ + #define R_ETHSW_CntMissing_CntMissing_Msk (0xffffffffUL) /*!< CntMissing (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== HUB_CONFIG ======================================================= */ + #define R_ETHSW_HUB_CONFIG_HUB_ENA_Pos (0UL) /*!< HUB_ENA (Bit 0) */ + #define R_ETHSW_HUB_CONFIG_HUB_ENA_Msk (0x1UL) /*!< HUB_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_RETRANSMIT_ENA_Pos (1UL) /*!< RETRANSMIT_ENA (Bit 1) */ + #define R_ETHSW_HUB_CONFIG_RETRANSMIT_ENA_Msk (0x2UL) /*!< RETRANSMIT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_TRIGGER_MODE_Pos (2UL) /*!< TRIGGER_MODE (Bit 2) */ + #define R_ETHSW_HUB_CONFIG_TRIGGER_MODE_Msk (0x4UL) /*!< TRIGGER_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_HUB_ISOLATE_Pos (3UL) /*!< HUB_ISOLATE (Bit 3) */ + #define R_ETHSW_HUB_CONFIG_HUB_ISOLATE_Msk (0x8UL) /*!< HUB_ISOLATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_TIMER_SEL_Pos (4UL) /*!< TIMER_SEL (Bit 4) */ + #define R_ETHSW_HUB_CONFIG_TIMER_SEL_Msk (0x10UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_IPG_WAIT_Pos (6UL) /*!< IPG_WAIT (Bit 6) */ + #define R_ETHSW_HUB_CONFIG_IPG_WAIT_Msk (0x1c0UL) /*!< IPG_WAIT (Bitfield-Mask: 0x07) */ + #define R_ETHSW_HUB_CONFIG_CRS_GEN_Pos (9UL) /*!< CRS_GEN (Bit 9) */ + #define R_ETHSW_HUB_CONFIG_CRS_GEN_Msk (0x200UL) /*!< CRS_GEN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_PRMB_GEN_DIS_Pos (10UL) /*!< PRMB_GEN_DIS (Bit 10) */ + #define R_ETHSW_HUB_CONFIG_PRMB_GEN_DIS_Msk (0x400UL) /*!< PRMB_GEN_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_CONFIG_JAM_WAIT_IDLE_Pos (11UL) /*!< JAM_WAIT_IDLE (Bit 11) */ + #define R_ETHSW_HUB_CONFIG_JAM_WAIT_IDLE_Msk (0x800UL) /*!< JAM_WAIT_IDLE (Bitfield-Mask: 0x01) */ +/* ======================================================= HUB_GROUP ======================================================= */ + #define R_ETHSW_HUB_GROUP_HUB_GROUP_Pos (0UL) /*!< HUB_GROUP (Bit 0) */ + #define R_ETHSW_HUB_GROUP_HUB_GROUP_Msk (0x7UL) /*!< HUB_GROUP (Bitfield-Mask: 0x07) */ +/* ====================================================== HUB_DEFPORT ====================================================== */ + #define R_ETHSW_HUB_DEFPORT_HUB_DEFPORT_Pos (0UL) /*!< HUB_DEFPORT (Bit 0) */ + #define R_ETHSW_HUB_DEFPORT_HUB_DEFPORT_Msk (0x7UL) /*!< HUB_DEFPORT (Bitfield-Mask: 0x07) */ +/* ================================================= HUB_TRIGGER_IMMEDIATE ================================================= */ + #define R_ETHSW_HUB_TRIGGER_IMMEDIATE_HUB_TRIGGER_IMMEDIATE_Pos (0UL) /*!< HUB_TRIGGER_IMMEDIATE (Bit 0) */ + #define R_ETHSW_HUB_TRIGGER_IMMEDIATE_HUB_TRIGGER_IMMEDIATE_Msk (0x7UL) /*!< HUB_TRIGGER_IMMEDIATE (Bitfield-Mask: 0x07) */ +/* ==================================================== HUB_TRIGGER_AT ===================================================== */ + #define R_ETHSW_HUB_TRIGGER_AT_HUB_TRIGGER_AT_Pos (0UL) /*!< HUB_TRIGGER_AT (Bit 0) */ + #define R_ETHSW_HUB_TRIGGER_AT_HUB_TRIGGER_AT_Msk (0x7UL) /*!< HUB_TRIGGER_AT (Bitfield-Mask: 0x07) */ +/* ======================================================= HUB_TTIME ======================================================= */ + #define R_ETHSW_HUB_TTIME_HUB_TTIME_Pos (0UL) /*!< HUB_TTIME (Bit 0) */ + #define R_ETHSW_HUB_TTIME_HUB_TTIME_Msk (0xffffffffUL) /*!< HUB_TTIME (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== HUB_IRQ_CONTROL ==================================================== */ + #define R_ETHSW_HUB_IRQ_CONTROL_RX_TRIGGER_Pos (0UL) /*!< RX_TRIGGER (Bit 0) */ + #define R_ETHSW_HUB_IRQ_CONTROL_RX_TRIGGER_Msk (0x7UL) /*!< RX_TRIGGER (Bitfield-Mask: 0x07) */ + #define R_ETHSW_HUB_IRQ_CONTROL_CHANGE_DET_Pos (3UL) /*!< CHANGE_DET (Bit 3) */ + #define R_ETHSW_HUB_IRQ_CONTROL_CHANGE_DET_Msk (0x8UL) /*!< CHANGE_DET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_IMMEDIATE_Pos (4UL) /*!< TRIGGER_IMMEDIATE (Bit 4) */ + #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_IMMEDIATE_Msk (0x10UL) /*!< TRIGGER_IMMEDIATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_TIMER_Pos (5UL) /*!< TRIGGER_TIMER (Bit 5) */ + #define R_ETHSW_HUB_IRQ_CONTROL_TRIGGER_TIMER_Msk (0x20UL) /*!< TRIGGER_TIMER (Bitfield-Mask: 0x01) */ +/* =================================================== HUB_IRQ_STAT_ACK ==================================================== */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_RX_TRIGGER_Pos (0UL) /*!< RX_TRIGGER (Bit 0) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_RX_TRIGGER_Msk (0x7UL) /*!< RX_TRIGGER (Bitfield-Mask: 0x07) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_CHANGE_DET_Pos (3UL) /*!< CHANGE_DET (Bit 3) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_CHANGE_DET_Msk (0x8UL) /*!< CHANGE_DET (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_IMMEDIATE_Pos (4UL) /*!< TRIGGER_IMMEDIATE (Bit 4) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_IMMEDIATE_Msk (0x10UL) /*!< TRIGGER_IMMEDIATE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_TIMER_Pos (5UL) /*!< TRIGGER_TIMER (Bit 5) */ + #define R_ETHSW_HUB_IRQ_STAT_ACK_TRIGGER_TIMER_Msk (0x20UL) /*!< TRIGGER_TIMER (Bitfield-Mask: 0x01) */ +/* ====================================================== HUB_STATUS ======================================================= */ + #define R_ETHSW_HUB_STATUS_PORTS_ACTIVE_Pos (0UL) /*!< PORTS_ACTIVE (Bit 0) */ + #define R_ETHSW_HUB_STATUS_PORTS_ACTIVE_Msk (0x7UL) /*!< PORTS_ACTIVE (Bitfield-Mask: 0x07) */ + #define R_ETHSW_HUB_STATUS_TX_ACTIVE_Pos (9UL) /*!< TX_ACTIVE (Bit 9) */ + #define R_ETHSW_HUB_STATUS_TX_ACTIVE_Msk (0x200UL) /*!< TX_ACTIVE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_STATUS_TX_BUSY_Pos (10UL) /*!< TX_BUSY (Bit 10) */ + #define R_ETHSW_HUB_STATUS_TX_BUSY_Msk (0x400UL) /*!< TX_BUSY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_STATUS_Speed_OK_Pos (11UL) /*!< Speed_OK (Bit 11) */ + #define R_ETHSW_HUB_STATUS_Speed_OK_Msk (0x800UL) /*!< Speed_OK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_HUB_STATUS_TX_Change_Pending_Pos (12UL) /*!< TX_Change_Pending (Bit 12) */ + #define R_ETHSW_HUB_STATUS_TX_Change_Pending_Msk (0x1000UL) /*!< TX_Change_Pending (Bitfield-Mask: 0x01) */ +/* =================================================== HUB_OPORT_STATUS ==================================================== */ + #define R_ETHSW_HUB_OPORT_STATUS_HUB_OPORT_STATUS_Pos (0UL) /*!< HUB_OPORT_STATUS (Bit 0) */ + #define R_ETHSW_HUB_OPORT_STATUS_HUB_OPORT_STATUS_Msk (0x7UL) /*!< HUB_OPORT_STATUS (Bitfield-Mask: 0x07) */ +/* ====================================================== TDMA_CONFIG ====================================================== */ + #define R_ETHSW_TDMA_CONFIG_TDMA_ENA_Pos (0UL) /*!< TDMA_ENA (Bit 0) */ + #define R_ETHSW_TDMA_CONFIG_TDMA_ENA_Msk (0x1UL) /*!< TDMA_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_WAIT_START_Pos (1UL) /*!< WAIT_START (Bit 1) */ + #define R_ETHSW_TDMA_CONFIG_WAIT_START_Msk (0x2UL) /*!< WAIT_START (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_Pos (2UL) /*!< TIMER_SEL (Bit 2) */ + #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_Msk (0x4UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_RED_PERIOD_Pos (4UL) /*!< RED_PERIOD (Bit 4) */ + #define R_ETHSW_TDMA_CONFIG_RED_PERIOD_Msk (0x10UL) /*!< RED_PERIOD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_RED_OVRD_ENA_Pos (5UL) /*!< RED_OVRD_ENA (Bit 5) */ + #define R_ETHSW_TDMA_CONFIG_RED_OVRD_ENA_Msk (0x20UL) /*!< RED_OVRD_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_RED_OVRD_Pos (6UL) /*!< RED_OVRD (Bit 6) */ + #define R_ETHSW_TDMA_CONFIG_RED_OVRD_Msk (0x40UL) /*!< RED_OVRD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_IN_CT_WREN_Pos (7UL) /*!< IN_CT_WREN (Bit 7) */ + #define R_ETHSW_TDMA_CONFIG_IN_CT_WREN_Msk (0x80UL) /*!< IN_CT_WREN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_OUT_CT_WREN_Pos (8UL) /*!< OUT_CT_WREN (Bit 8) */ + #define R_ETHSW_TDMA_CONFIG_OUT_CT_WREN_Msk (0x100UL) /*!< OUT_CT_WREN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_HOLD_REQ_CLR_Pos (9UL) /*!< HOLD_REQ_CLR (Bit 9) */ + #define R_ETHSW_TDMA_CONFIG_HOLD_REQ_CLR_Msk (0x200UL) /*!< HOLD_REQ_CLR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_ACTIVE_Pos (12UL) /*!< TIMER_SEL_ACTIVE (Bit 12) */ + #define R_ETHSW_TDMA_CONFIG_TIMER_SEL_ACTIVE_Msk (0x1000UL) /*!< TIMER_SEL_ACTIVE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CONFIG_IN_CT_ENA_Pos (16UL) /*!< IN_CT_ENA (Bit 16) */ + #define R_ETHSW_TDMA_CONFIG_IN_CT_ENA_Msk (0xf0000UL) /*!< IN_CT_ENA (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_TDMA_CONFIG_OUT_CT_ENA_Pos (24UL) /*!< OUT_CT_ENA (Bit 24) */ + #define R_ETHSW_TDMA_CONFIG_OUT_CT_ENA_Msk (0xf000000UL) /*!< OUT_CT_ENA (Bitfield-Mask: 0x0f) */ +/* ===================================================== TDMA_ENA_CTRL ===================================================== */ + #define R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Pos (0UL) /*!< PORT_ENA (Bit 0) */ + #define R_ETHSW_TDMA_ENA_CTRL_PORT_ENA_Msk (0xfUL) /*!< PORT_ENA (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_TDMA_ENA_CTRL_QGATE_DIS_Pos (16UL) /*!< QGATE_DIS (Bit 16) */ + #define R_ETHSW_TDMA_ENA_CTRL_QGATE_DIS_Msk (0xff0000UL) /*!< QGATE_DIS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TDMA_ENA_CTRL_QTRIG_DIS_Pos (24UL) /*!< QTRIG_DIS (Bit 24) */ + #define R_ETHSW_TDMA_ENA_CTRL_QTRIG_DIS_Msk (0xff000000UL) /*!< QTRIG_DIS (Bitfield-Mask: 0xff) */ +/* ====================================================== TDMA_START ======================================================= */ + #define R_ETHSW_TDMA_START_TDMA_START_Pos (0UL) /*!< TDMA_START (Bit 0) */ + #define R_ETHSW_TDMA_START_TDMA_START_Msk (0xffffffffUL) /*!< TDMA_START (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TDMA_MODULO ====================================================== */ + #define R_ETHSW_TDMA_MODULO_TDMA_MODULO_Pos (0UL) /*!< TDMA_MODULO (Bit 0) */ + #define R_ETHSW_TDMA_MODULO_TDMA_MODULO_Msk (0xffffffffUL) /*!< TDMA_MODULO (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TDMA_CYCLE ======================================================= */ + #define R_ETHSW_TDMA_CYCLE_TDMA_CYCLE_Pos (0UL) /*!< TDMA_CYCLE (Bit 0) */ + #define R_ETHSW_TDMA_CYCLE_TDMA_CYCLE_Msk (0xffffffffUL) /*!< TDMA_CYCLE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== TCV_SEQ_ADDR ====================================================== */ + #define R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Pos (0UL) /*!< TCV_S_ADDR (Bit 0) */ + #define R_ETHSW_TCV_SEQ_ADDR_TCV_S_ADDR_Msk (0xfffUL) /*!< TCV_S_ADDR (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_TCV_SEQ_ADDR_ADDR_AINC_Pos (31UL) /*!< ADDR_AINC (Bit 31) */ + #define R_ETHSW_TCV_SEQ_ADDR_ADDR_AINC_Msk (0x80000000UL) /*!< ADDR_AINC (Bitfield-Mask: 0x01) */ +/* ===================================================== TCV_SEQ_CTRL ====================================================== */ + #define R_ETHSW_TCV_SEQ_CTRL_START_Pos (0UL) /*!< START (Bit 0) */ + #define R_ETHSW_TCV_SEQ_CTRL_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_SEQ_CTRL_INT_Pos (1UL) /*!< INT (Bit 1) */ + #define R_ETHSW_TCV_SEQ_CTRL_INT_Msk (0x2UL) /*!< INT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Pos (2UL) /*!< TCV_D_IDX (Bit 2) */ + #define R_ETHSW_TCV_SEQ_CTRL_TCV_D_IDX_Msk (0x7fcUL) /*!< TCV_D_IDX (Bitfield-Mask: 0x1ff) */ + #define R_ETHSW_TCV_SEQ_CTRL_GPIO_Pos (22UL) /*!< GPIO (Bit 22) */ + #define R_ETHSW_TCV_SEQ_CTRL_GPIO_Msk (0x3fc00000UL) /*!< GPIO (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TCV_SEQ_CTRL_READ_MODE_Pos (31UL) /*!< READ_MODE (Bit 31) */ + #define R_ETHSW_TCV_SEQ_CTRL_READ_MODE_Msk (0x80000000UL) /*!< READ_MODE (Bitfield-Mask: 0x01) */ +/* ===================================================== TCV_SEQ_LAST ====================================================== */ + #define R_ETHSW_TCV_SEQ_LAST_LAST_Pos (0UL) /*!< LAST (Bit 0) */ + #define R_ETHSW_TCV_SEQ_LAST_LAST_Msk (0xfffUL) /*!< LAST (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_TCV_SEQ_LAST_ACTIVE_Pos (16UL) /*!< ACTIVE (Bit 16) */ + #define R_ETHSW_TCV_SEQ_LAST_ACTIVE_Msk (0xfff0000UL) /*!< ACTIVE (Bitfield-Mask: 0xfff) */ +/* ====================================================== TCV_D_ADDR ======================================================= */ + #define R_ETHSW_TCV_D_ADDR_ADDR_Pos (0UL) /*!< ADDR (Bit 0) */ + #define R_ETHSW_TCV_D_ADDR_ADDR_Msk (0x1ffUL) /*!< ADDR (Bitfield-Mask: 0x1ff) */ + #define R_ETHSW_TCV_D_ADDR_AINC_WR_ENA_Pos (31UL) /*!< AINC_WR_ENA (Bit 31) */ + #define R_ETHSW_TCV_D_ADDR_AINC_WR_ENA_Msk (0x80000000UL) /*!< AINC_WR_ENA (Bitfield-Mask: 0x01) */ +/* ===================================================== TCV_D_OFFSET ====================================================== */ + #define R_ETHSW_TCV_D_OFFSET_TCV_D_OFFSET_Pos (0UL) /*!< TCV_D_OFFSET (Bit 0) */ + #define R_ETHSW_TCV_D_OFFSET_TCV_D_OFFSET_Msk (0xffffffffUL) /*!< TCV_D_OFFSET (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== TCV_D_CTRL ======================================================= */ + #define R_ETHSW_TCV_D_CTRL_INC_CTR0_Pos (0UL) /*!< INC_CTR0 (Bit 0) */ + #define R_ETHSW_TCV_D_CTRL_INC_CTR0_Msk (0x1UL) /*!< INC_CTR0 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_INC_CTR1_Pos (1UL) /*!< INC_CTR1 (Bit 1) */ + #define R_ETHSW_TCV_D_CTRL_INC_CTR1_Msk (0x2UL) /*!< INC_CTR1 (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_RED_PERIOD_Pos (2UL) /*!< RED_PERIOD (Bit 2) */ + #define R_ETHSW_TCV_D_CTRL_RED_PERIOD_Msk (0x4UL) /*!< RED_PERIOD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_OUT_CT_ENA_Pos (3UL) /*!< OUT_CT_ENA (Bit 3) */ + #define R_ETHSW_TCV_D_CTRL_OUT_CT_ENA_Msk (0x8UL) /*!< OUT_CT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_IN_CT_ENA_Pos (4UL) /*!< IN_CT_ENA (Bit 4) */ + #define R_ETHSW_TCV_D_CTRL_IN_CT_ENA_Msk (0x10UL) /*!< IN_CT_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_TRIGGER_MODE_Pos (5UL) /*!< TRIGGER_MODE (Bit 5) */ + #define R_ETHSW_TCV_D_CTRL_TRIGGER_MODE_Msk (0x20UL) /*!< TRIGGER_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_GATE_MODE_Pos (6UL) /*!< GATE_MODE (Bit 6) */ + #define R_ETHSW_TCV_D_CTRL_GATE_MODE_Msk (0x40UL) /*!< GATE_MODE (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_HOLD_REQ_Pos (7UL) /*!< HOLD_REQ (Bit 7) */ + #define R_ETHSW_TCV_D_CTRL_HOLD_REQ_Msk (0x80UL) /*!< HOLD_REQ (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TCV_D_CTRL_QGATE_Pos (8UL) /*!< QGATE (Bit 8) */ + #define R_ETHSW_TCV_D_CTRL_QGATE_Msk (0xff00UL) /*!< QGATE (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TCV_D_CTRL_PMASK_Pos (16UL) /*!< PMASK (Bit 16) */ + #define R_ETHSW_TCV_D_CTRL_PMASK_Msk (0xf0000UL) /*!< PMASK (Bitfield-Mask: 0x0f) */ +/* ======================================================= TDMA_CTR0 ======================================================= */ + #define R_ETHSW_TDMA_CTR0_TDMA_CTR0_Pos (0UL) /*!< TDMA_CTR0 (Bit 0) */ + #define R_ETHSW_TDMA_CTR0_TDMA_CTR0_Msk (0xffffffffUL) /*!< TDMA_CTR0 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TDMA_CTR1 ======================================================= */ + #define R_ETHSW_TDMA_CTR1_VALUE_Pos (0UL) /*!< VALUE (Bit 0) */ + #define R_ETHSW_TDMA_CTR1_VALUE_Msk (0xffUL) /*!< VALUE (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TDMA_CTR1_WRITE_ENA_Pos (8UL) /*!< WRITE_ENA (Bit 8) */ + #define R_ETHSW_TDMA_CTR1_WRITE_ENA_Msk (0x100UL) /*!< WRITE_ENA (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_CTR1_MAX_Pos (16UL) /*!< MAX (Bit 16) */ + #define R_ETHSW_TDMA_CTR1_MAX_Msk (0xff0000UL) /*!< MAX (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TDMA_CTR1_INT_VALUE_Pos (24UL) /*!< INT_VALUE (Bit 24) */ + #define R_ETHSW_TDMA_CTR1_INT_VALUE_Msk (0xff000000UL) /*!< INT_VALUE (Bitfield-Mask: 0xff) */ +/* ==================================================== TDMA_TCV_START ===================================================== */ + #define R_ETHSW_TDMA_TCV_START_TDMA_TCV_START_Pos (0UL) /*!< TDMA_TCV_START (Bit 0) */ + #define R_ETHSW_TDMA_TCV_START_TDMA_TCV_START_Msk (0xfffUL) /*!< TDMA_TCV_START (Bitfield-Mask: 0xfff) */ +/* ==================================================== TIME_LOAD_NEXT ===================================================== */ + #define R_ETHSW_TIME_LOAD_NEXT_TIME_LOAD_NEXT_Pos (0UL) /*!< TIME_LOAD_NEXT (Bit 0) */ + #define R_ETHSW_TIME_LOAD_NEXT_TIME_LOAD_NEXT_Msk (0xffffffffUL) /*!< TIME_LOAD_NEXT (Bitfield-Mask: 0xffffffff) */ +/* =================================================== TDMA_IRQ_CONTROL ==================================================== */ + #define R_ETHSW_TDMA_IRQ_CONTROL_TCV_INT_EN_Pos (0UL) /*!< TCV_INT_EN (Bit 0) */ + #define R_ETHSW_TDMA_IRQ_CONTROL_TCV_INT_EN_Msk (0x1UL) /*!< TCV_INT_EN (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_IRQ_CONTROL_CTR1_INT_EN_Pos (13UL) /*!< CTR1_INT_EN (Bit 13) */ + #define R_ETHSW_TDMA_IRQ_CONTROL_CTR1_INT_EN_Msk (0x2000UL) /*!< CTR1_INT_EN (Bitfield-Mask: 0x01) */ +/* =================================================== TDMA_IRQ_STAT_ACK =================================================== */ + #define R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Pos (0UL) /*!< TCV_ACK (Bit 0) */ + #define R_ETHSW_TDMA_IRQ_STAT_ACK_TCV_ACK_Msk (0x1UL) /*!< TCV_ACK (Bitfield-Mask: 0x01) */ + #define R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Pos (13UL) /*!< CTR1_ACK (Bit 13) */ + #define R_ETHSW_TDMA_IRQ_STAT_ACK_CTR1_ACK_Msk (0x2000UL) /*!< CTR1_ACK (Bitfield-Mask: 0x01) */ +/* ======================================================= TDMA_GPIO ======================================================= */ + #define R_ETHSW_TDMA_GPIO_GPIO_STATUS_Pos (0UL) /*!< GPIO_STATUS (Bit 0) */ + #define R_ETHSW_TDMA_GPIO_GPIO_STATUS_Msk (0xffUL) /*!< GPIO_STATUS (Bitfield-Mask: 0xff) */ + #define R_ETHSW_TDMA_GPIO_GPIO_MODE_Pos (16UL) /*!< GPIO_MODE (Bit 16) */ + #define R_ETHSW_TDMA_GPIO_GPIO_MODE_Msk (0xffff0000UL) /*!< GPIO_MODE (Bitfield-Mask: 0xffff) */ +/* ==================================================== RXMATCH_CONFIG ===================================================== */ + #define R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Pos (0UL) /*!< PATTERN_EN (Bit 0) */ + #define R_ETHSW_RXMATCH_CONFIG_PATTERN_EN_Msk (0xfffUL) /*!< PATTERN_EN (Bitfield-Mask: 0xfff) */ +/* ===================================================== PATTERN_CTRL ====================================================== */ + #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_Pos (0UL) /*!< MATCH_NOT (Bit 0) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_Msk (0x1UL) /*!< MATCH_NOT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_MGMTFWD_Pos (1UL) /*!< MGMTFWD (Bit 1) */ + #define R_ETHSW_PATTERN_CTRL_MGMTFWD_Msk (0x2UL) /*!< MGMTFWD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_DISCARD_Pos (2UL) /*!< DISCARD (Bit 2) */ + #define R_ETHSW_PATTERN_CTRL_DISCARD_Msk (0x4UL) /*!< DISCARD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_SET_PRIO_Pos (3UL) /*!< SET_PRIO (Bit 3) */ + #define R_ETHSW_PATTERN_CTRL_SET_PRIO_Msk (0x8UL) /*!< SET_PRIO (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_MODE_Pos (4UL) /*!< MODE (Bit 4) */ + #define R_ETHSW_PATTERN_CTRL_MODE_Msk (0x30UL) /*!< MODE (Bitfield-Mask: 0x03) */ + #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Pos (6UL) /*!< TIMER_SEL_OVR (Bit 6) */ + #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_OVR_Msk (0x40UL) /*!< TIMER_SEL_OVR (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Pos (7UL) /*!< FORCE_FORWARD (Bit 7) */ + #define R_ETHSW_PATTERN_CTRL_FORCE_FORWARD_Msk (0x80UL) /*!< FORCE_FORWARD (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Pos (8UL) /*!< HUBTRIGGER (Bit 8) */ + #define R_ETHSW_PATTERN_CTRL_HUBTRIGGER_Msk (0x100UL) /*!< HUBTRIGGER (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_RED_Pos (9UL) /*!< MATCH_RED (Bit 9) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_RED_Msk (0x200UL) /*!< MATCH_RED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Pos (10UL) /*!< MATCH_NOT_RED (Bit 10) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_NOT_RED_Msk (0x400UL) /*!< MATCH_NOT_RED (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Pos (11UL) /*!< VLAN_SKIP (Bit 11) */ + #define R_ETHSW_PATTERN_CTRL_VLAN_SKIP_Msk (0x800UL) /*!< VLAN_SKIP (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_PRIORITY_Pos (12UL) /*!< PRIORITY (Bit 12) */ + #define R_ETHSW_PATTERN_CTRL_PRIORITY_Msk (0x7000UL) /*!< PRIORITY (Bitfield-Mask: 0x07) */ + #define R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Pos (15UL) /*!< LEARNING_DIS (Bit 15) */ + #define R_ETHSW_PATTERN_CTRL_LEARNING_DIS_Msk (0x8000UL) /*!< LEARNING_DIS (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_PORTMASK_Pos (16UL) /*!< PORTMASK (Bit 16) */ + #define R_ETHSW_PATTERN_CTRL_PORTMASK_Msk (0xf0000UL) /*!< PORTMASK (Bitfield-Mask: 0x0f) */ + #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Pos (22UL) /*!< IMC_TRIGGER (Bit 22) */ + #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_Msk (0x400000UL) /*!< IMC_TRIGGER (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Pos (23UL) /*!< IMC_TRIGGER_DLY (Bit 23) */ + #define R_ETHSW_PATTERN_CTRL_IMC_TRIGGER_DLY_Msk (0x800000UL) /*!< IMC_TRIGGER_DLY (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Pos (24UL) /*!< SWAP_BYTES (Bit 24) */ + #define R_ETHSW_PATTERN_CTRL_SWAP_BYTES_Msk (0x1000000UL) /*!< SWAP_BYTES (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_LT_Pos (25UL) /*!< MATCH_LT (Bit 25) */ + #define R_ETHSW_PATTERN_CTRL_MATCH_LT_Msk (0x2000000UL) /*!< MATCH_LT (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_Pos (26UL) /*!< TIMER_SEL (Bit 26) */ + #define R_ETHSW_PATTERN_CTRL_TIMER_SEL_Msk (0x4000000UL) /*!< TIMER_SEL (Bitfield-Mask: 0x01) */ + #define R_ETHSW_PATTERN_CTRL_QUEUESEL_Pos (28UL) /*!< QUEUESEL (Bit 28) */ + #define R_ETHSW_PATTERN_CTRL_QUEUESEL_Msk (0xf0000000UL) /*!< QUEUESEL (Bitfield-Mask: 0x0f) */ +/* ================================================== PATTERN_IRQ_CONTROL ================================================== */ + #define R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Pos (0UL) /*!< MATCHINT (Bit 0) */ + #define R_ETHSW_PATTERN_IRQ_CONTROL_MATCHINT_Msk (0xfffUL) /*!< MATCHINT (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_PATTERN_IRQ_CONTROL_ERROR_INT_Pos (16UL) /*!< ERROR_INT (Bit 16) */ + #define R_ETHSW_PATTERN_IRQ_CONTROL_ERROR_INT_Msk (0xf0000UL) /*!< ERROR_INT (Bitfield-Mask: 0x0f) */ +/* ================================================= PATTERN_IRQ_STAT_ACK ================================================== */ + #define R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Pos (0UL) /*!< MATCHINT (Bit 0) */ + #define R_ETHSW_PATTERN_IRQ_STAT_ACK_MATCHINT_Msk (0xfffUL) /*!< MATCHINT (Bitfield-Mask: 0xfff) */ + #define R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Pos (16UL) /*!< ERROR_INT (Bit 16) */ + #define R_ETHSW_PATTERN_IRQ_STAT_ACK_ERROR_INT_Msk (0xf0000UL) /*!< ERROR_INT (Bitfield-Mask: 0x0f) */ +/* ====================================================== PTRN_VLANID ====================================================== */ + #define R_ETHSW_PTRN_VLANID_PTRN_VLANID_Pos (0UL) /*!< PTRN_VLANID (Bit 0) */ + #define R_ETHSW_PTRN_VLANID_PTRN_VLANID_Msk (0xffffUL) /*!< PTRN_VLANID (Bitfield-Mask: 0xffff) */ +/* ====================================================== PATTERN_SEL ====================================================== */ + #define R_ETHSW_PATTERN_SEL_PATTERN_SEL_Pos (0UL) /*!< PATTERN_SEL (Bit 0) */ + #define R_ETHSW_PATTERN_SEL_PATTERN_SEL_Msk (0xfUL) /*!< PATTERN_SEL (Bitfield-Mask: 0x0f) */ +/* ====================================================== PTRN_CMP_30 ====================================================== */ + #define R_ETHSW_PTRN_CMP_30_PTRN_CMP_30_Pos (0UL) /*!< PTRN_CMP_30 (Bit 0) */ + #define R_ETHSW_PTRN_CMP_30_PTRN_CMP_30_Msk (0xffffffffUL) /*!< PTRN_CMP_30 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTRN_CMP_74 ====================================================== */ + #define R_ETHSW_PTRN_CMP_74_PTRN_CMP_74_Pos (0UL) /*!< PTRN_CMP_74 (Bit 0) */ + #define R_ETHSW_PTRN_CMP_74_PTRN_CMP_74_Msk (0xffffffffUL) /*!< PTRN_CMP_74 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PTRN_CMP_118 ====================================================== */ + #define R_ETHSW_PTRN_CMP_118_PTRN_CMP_118_Pos (0UL) /*!< PTRN_CMP_118 (Bit 0) */ + #define R_ETHSW_PTRN_CMP_118_PTRN_CMP_118_Msk (0xffffffffUL) /*!< PTRN_CMP_118 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTRN_MSK_30 ====================================================== */ + #define R_ETHSW_PTRN_MSK_30_PTRN_MSK_30_Pos (0UL) /*!< PTRN_MSK_30 (Bit 0) */ + #define R_ETHSW_PTRN_MSK_30_PTRN_MSK_30_Msk (0xffffffffUL) /*!< PTRN_MSK_30 (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== PTRN_MSK_74 ====================================================== */ + #define R_ETHSW_PTRN_MSK_74_PTRN_MSK_74_Pos (0UL) /*!< PTRN_MSK_74 (Bit 0) */ + #define R_ETHSW_PTRN_MSK_74_PTRN_MSK_74_Msk (0xffffffffUL) /*!< PTRN_MSK_74 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PTRN_MSK_118 ====================================================== */ + #define R_ETHSW_PTRN_MSK_118_PTRN_MSK_118_Pos (0UL) /*!< PTRN_MSK_118 (Bit 0) */ + #define R_ETHSW_PTRN_MSK_118_PTRN_MSK_118_Msk (0xffffffffUL) /*!< PTRN_MSK_118 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_ESC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TYPE ========================================================== */ + #define R_ESC_TYPE_TYPE_Pos (0UL) /*!< TYPE (Bit 0) */ + #define R_ESC_TYPE_TYPE_Msk (0xffUL) /*!< TYPE (Bitfield-Mask: 0xff) */ +/* ======================================================= REVISION ======================================================== */ + #define R_ESC_REVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_ESC_REVISION_REV_Msk (0xffUL) /*!< REV (Bitfield-Mask: 0xff) */ +/* ========================================================= BUILD ========================================================= */ + #define R_ESC_BUILD_BUILD_Pos (0UL) /*!< BUILD (Bit 0) */ + #define R_ESC_BUILD_BUILD_Msk (0xffUL) /*!< BUILD (Bitfield-Mask: 0xff) */ +/* ======================================================= FMMU_NUM ======================================================== */ + #define R_ESC_FMMU_NUM_NUMFMMU_Pos (0UL) /*!< NUMFMMU (Bit 0) */ + #define R_ESC_FMMU_NUM_NUMFMMU_Msk (0xffUL) /*!< NUMFMMU (Bitfield-Mask: 0xff) */ +/* ===================================================== SYNC_MANAGER ====================================================== */ + #define R_ESC_SYNC_MANAGER_NUMSYNC_Pos (0UL) /*!< NUMSYNC (Bit 0) */ + #define R_ESC_SYNC_MANAGER_NUMSYNC_Msk (0xffUL) /*!< NUMSYNC (Bitfield-Mask: 0xff) */ +/* ======================================================= RAM_SIZE ======================================================== */ + #define R_ESC_RAM_SIZE_RAMSIZE_Pos (0UL) /*!< RAMSIZE (Bit 0) */ + #define R_ESC_RAM_SIZE_RAMSIZE_Msk (0xffUL) /*!< RAMSIZE (Bitfield-Mask: 0xff) */ +/* ======================================================= PORT_DESC ======================================================= */ + #define R_ESC_PORT_DESC_P0_Pos (0UL) /*!< P0 (Bit 0) */ + #define R_ESC_PORT_DESC_P0_Msk (0x3UL) /*!< P0 (Bitfield-Mask: 0x03) */ + #define R_ESC_PORT_DESC_P1_Pos (2UL) /*!< P1 (Bit 2) */ + #define R_ESC_PORT_DESC_P1_Msk (0xcUL) /*!< P1 (Bitfield-Mask: 0x03) */ + #define R_ESC_PORT_DESC_P2_Pos (4UL) /*!< P2 (Bit 4) */ + #define R_ESC_PORT_DESC_P2_Msk (0x30UL) /*!< P2 (Bitfield-Mask: 0x03) */ + #define R_ESC_PORT_DESC_P3_Pos (6UL) /*!< P3 (Bit 6) */ + #define R_ESC_PORT_DESC_P3_Msk (0xc0UL) /*!< P3 (Bitfield-Mask: 0x03) */ +/* ======================================================== FEATURE ======================================================== */ + #define R_ESC_FEATURE_FMMU_Pos (0UL) /*!< FMMU (Bit 0) */ + #define R_ESC_FEATURE_FMMU_Msk (0x1UL) /*!< FMMU (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_DC_Pos (2UL) /*!< DC (Bit 2) */ + #define R_ESC_FEATURE_DC_Msk (0x4UL) /*!< DC (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_DCWID_Pos (3UL) /*!< DCWID (Bit 3) */ + #define R_ESC_FEATURE_DCWID_Msk (0x8UL) /*!< DCWID (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_LINKDECMII_Pos (6UL) /*!< LINKDECMII (Bit 6) */ + #define R_ESC_FEATURE_LINKDECMII_Msk (0x40UL) /*!< LINKDECMII (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_FCS_Pos (7UL) /*!< FCS (Bit 7) */ + #define R_ESC_FEATURE_FCS_Msk (0x80UL) /*!< FCS (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_DCSYNC_Pos (8UL) /*!< DCSYNC (Bit 8) */ + #define R_ESC_FEATURE_DCSYNC_Msk (0x100UL) /*!< DCSYNC (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_LRW_Pos (9UL) /*!< LRW (Bit 9) */ + #define R_ESC_FEATURE_LRW_Msk (0x200UL) /*!< LRW (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_RWSUPP_Pos (10UL) /*!< RWSUPP (Bit 10) */ + #define R_ESC_FEATURE_RWSUPP_Msk (0x400UL) /*!< RWSUPP (Bitfield-Mask: 0x01) */ + #define R_ESC_FEATURE_FSCONFIG_Pos (11UL) /*!< FSCONFIG (Bit 11) */ + #define R_ESC_FEATURE_FSCONFIG_Msk (0x800UL) /*!< FSCONFIG (Bitfield-Mask: 0x01) */ +/* ====================================================== STATION_ADR ====================================================== */ + #define R_ESC_STATION_ADR_NODADDR_Pos (0UL) /*!< NODADDR (Bit 0) */ + #define R_ESC_STATION_ADR_NODADDR_Msk (0xffffUL) /*!< NODADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== STATION_ALIAS ===================================================== */ + #define R_ESC_STATION_ALIAS_NODALIADDR_Pos (0UL) /*!< NODALIADDR (Bit 0) */ + #define R_ESC_STATION_ALIAS_NODALIADDR_Msk (0xffffUL) /*!< NODALIADDR (Bitfield-Mask: 0xffff) */ +/* ===================================================== WR_REG_ENABLE ===================================================== */ + #define R_ESC_WR_REG_ENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ESC_WR_REG_ENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== WR_REG_PROTECT ===================================================== */ + #define R_ESC_WR_REG_PROTECT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_ESC_WR_REG_PROTECT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* ===================================================== ESC_WR_ENABLE ===================================================== */ + #define R_ESC_ESC_WR_ENABLE_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_ESC_ESC_WR_ENABLE_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ==================================================== ESC_WR_PROTECT ===================================================== */ + #define R_ESC_ESC_WR_PROTECT_PROTECT_Pos (0UL) /*!< PROTECT (Bit 0) */ + #define R_ESC_ESC_WR_PROTECT_PROTECT_Msk (0x1UL) /*!< PROTECT (Bitfield-Mask: 0x01) */ +/* =================================================== ESC_RESET_ECAT_R ==================================================== */ + #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Pos (0UL) /*!< RESET_ECAT (Bit 0) */ + #define R_ESC_ESC_RESET_ECAT_R_RESET_ECAT_Msk (0x3UL) /*!< RESET_ECAT (Bitfield-Mask: 0x03) */ +/* =================================================== ESC_RESET_ECAT_W ==================================================== */ + #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Pos (0UL) /*!< RESET_ECAT (Bit 0) */ + #define R_ESC_ESC_RESET_ECAT_W_RESET_ECAT_Msk (0xffUL) /*!< RESET_ECAT (Bitfield-Mask: 0xff) */ +/* ==================================================== ESC_RESET_PDI_R ==================================================== */ + #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Pos (0UL) /*!< RESET_PDI (Bit 0) */ + #define R_ESC_ESC_RESET_PDI_R_RESET_PDI_Msk (0x3UL) /*!< RESET_PDI (Bitfield-Mask: 0x03) */ +/* ==================================================== ESC_RESET_PDI_W ==================================================== */ + #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Pos (0UL) /*!< RESET_PDI (Bit 0) */ + #define R_ESC_ESC_RESET_PDI_W_RESET_PDI_Msk (0xffUL) /*!< RESET_PDI (Bitfield-Mask: 0xff) */ +/* ==================================================== ESC_DL_CONTROL ===================================================== */ + #define R_ESC_ESC_DL_CONTROL_FWDRULE_Pos (0UL) /*!< FWDRULE (Bit 0) */ + #define R_ESC_ESC_DL_CONTROL_FWDRULE_Msk (0x1UL) /*!< FWDRULE (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Pos (1UL) /*!< TEMPUSE (Bit 1) */ + #define R_ESC_ESC_DL_CONTROL_TEMPUSE_Msk (0x2UL) /*!< TEMPUSE (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_CONTROL_LP0_Pos (8UL) /*!< LP0 (Bit 8) */ + #define R_ESC_ESC_DL_CONTROL_LP0_Msk (0x300UL) /*!< LP0 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_LP1_Pos (10UL) /*!< LP1 (Bit 10) */ + #define R_ESC_ESC_DL_CONTROL_LP1_Msk (0xc00UL) /*!< LP1 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_LP2_Pos (12UL) /*!< LP2 (Bit 12) */ + #define R_ESC_ESC_DL_CONTROL_LP2_Msk (0x3000UL) /*!< LP2 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_LP3_Pos (14UL) /*!< LP3 (Bit 14) */ + #define R_ESC_ESC_DL_CONTROL_LP3_Msk (0xc000UL) /*!< LP3 (Bitfield-Mask: 0x03) */ + #define R_ESC_ESC_DL_CONTROL_RXFIFO_Pos (16UL) /*!< RXFIFO (Bit 16) */ + #define R_ESC_ESC_DL_CONTROL_RXFIFO_Msk (0x70000UL) /*!< RXFIFO (Bitfield-Mask: 0x07) */ + #define R_ESC_ESC_DL_CONTROL_STAALIAS_Pos (24UL) /*!< STAALIAS (Bit 24) */ + #define R_ESC_ESC_DL_CONTROL_STAALIAS_Msk (0x1000000UL) /*!< STAALIAS (Bitfield-Mask: 0x01) */ +/* ================================================== PHYSICAL_RW_OFFSET =================================================== */ + #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Pos (0UL) /*!< RWOFFSET (Bit 0) */ + #define R_ESC_PHYSICAL_RW_OFFSET_RWOFFSET_Msk (0xffffUL) /*!< RWOFFSET (Bitfield-Mask: 0xffff) */ +/* ===================================================== ESC_DL_STATUS ===================================================== */ + #define R_ESC_ESC_DL_STATUS_PDIOPE_Pos (0UL) /*!< PDIOPE (Bit 0) */ + #define R_ESC_ESC_DL_STATUS_PDIOPE_Msk (0x1UL) /*!< PDIOPE (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PDIWDST_Pos (1UL) /*!< PDIWDST (Bit 1) */ + #define R_ESC_ESC_DL_STATUS_PDIWDST_Msk (0x2UL) /*!< PDIWDST (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_ENHLINKD_Pos (2UL) /*!< ENHLINKD (Bit 2) */ + #define R_ESC_ESC_DL_STATUS_ENHLINKD_Msk (0x4UL) /*!< ENHLINKD (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP0_Pos (4UL) /*!< PHYP0 (Bit 4) */ + #define R_ESC_ESC_DL_STATUS_PHYP0_Msk (0x10UL) /*!< PHYP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP1_Pos (5UL) /*!< PHYP1 (Bit 5) */ + #define R_ESC_ESC_DL_STATUS_PHYP1_Msk (0x20UL) /*!< PHYP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP2_Pos (6UL) /*!< PHYP2 (Bit 6) */ + #define R_ESC_ESC_DL_STATUS_PHYP2_Msk (0x40UL) /*!< PHYP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_PHYP3_Pos (7UL) /*!< PHYP3 (Bit 7) */ + #define R_ESC_ESC_DL_STATUS_PHYP3_Msk (0x80UL) /*!< PHYP3 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP0_Pos (8UL) /*!< LP0 (Bit 8) */ + #define R_ESC_ESC_DL_STATUS_LP0_Msk (0x100UL) /*!< LP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP0_Pos (9UL) /*!< COMP0 (Bit 9) */ + #define R_ESC_ESC_DL_STATUS_COMP0_Msk (0x200UL) /*!< COMP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP1_Pos (10UL) /*!< LP1 (Bit 10) */ + #define R_ESC_ESC_DL_STATUS_LP1_Msk (0x400UL) /*!< LP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP1_Pos (11UL) /*!< COMP1 (Bit 11) */ + #define R_ESC_ESC_DL_STATUS_COMP1_Msk (0x800UL) /*!< COMP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP2_Pos (12UL) /*!< LP2 (Bit 12) */ + #define R_ESC_ESC_DL_STATUS_LP2_Msk (0x1000UL) /*!< LP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP2_Pos (13UL) /*!< COMP2 (Bit 13) */ + #define R_ESC_ESC_DL_STATUS_COMP2_Msk (0x2000UL) /*!< COMP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_LP3_Pos (14UL) /*!< LP3 (Bit 14) */ + #define R_ESC_ESC_DL_STATUS_LP3_Msk (0x4000UL) /*!< LP3 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_DL_STATUS_COMP3_Pos (15UL) /*!< COMP3 (Bit 15) */ + #define R_ESC_ESC_DL_STATUS_COMP3_Msk (0x8000UL) /*!< COMP3 (Bitfield-Mask: 0x01) */ +/* ====================================================== AL_CONTROL ======================================================= */ + #define R_ESC_AL_CONTROL_INISTATE_Pos (0UL) /*!< INISTATE (Bit 0) */ + #define R_ESC_AL_CONTROL_INISTATE_Msk (0xfUL) /*!< INISTATE (Bitfield-Mask: 0x0f) */ + #define R_ESC_AL_CONTROL_ERRINDACK_Pos (4UL) /*!< ERRINDACK (Bit 4) */ + #define R_ESC_AL_CONTROL_ERRINDACK_Msk (0x10UL) /*!< ERRINDACK (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_CONTROL_DEVICEID_Pos (5UL) /*!< DEVICEID (Bit 5) */ + #define R_ESC_AL_CONTROL_DEVICEID_Msk (0x20UL) /*!< DEVICEID (Bitfield-Mask: 0x01) */ +/* ======================================================= AL_STATUS ======================================================= */ + #define R_ESC_AL_STATUS_ACTSTATE_Pos (0UL) /*!< ACTSTATE (Bit 0) */ + #define R_ESC_AL_STATUS_ACTSTATE_Msk (0xfUL) /*!< ACTSTATE (Bitfield-Mask: 0x0f) */ + #define R_ESC_AL_STATUS_ERR_Pos (4UL) /*!< ERR (Bit 4) */ + #define R_ESC_AL_STATUS_ERR_Msk (0x10UL) /*!< ERR (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_STATUS_DEVICEID_Pos (5UL) /*!< DEVICEID (Bit 5) */ + #define R_ESC_AL_STATUS_DEVICEID_Msk (0x20UL) /*!< DEVICEID (Bitfield-Mask: 0x01) */ +/* ==================================================== AL_STATUS_CODE ===================================================== */ + #define R_ESC_AL_STATUS_CODE_STATUSCODE_Pos (0UL) /*!< STATUSCODE (Bit 0) */ + #define R_ESC_AL_STATUS_CODE_STATUSCODE_Msk (0xffffUL) /*!< STATUSCODE (Bitfield-Mask: 0xffff) */ +/* =================================================== RUN_LED_OVERRIDE ==================================================== */ + #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Pos (0UL) /*!< LEDCODE (Bit 0) */ + #define R_ESC_RUN_LED_OVERRIDE_LEDCODE_Msk (0xfUL) /*!< LEDCODE (Bitfield-Mask: 0x0f) */ + #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Pos (4UL) /*!< OVERRIDEEN (Bit 4) */ + #define R_ESC_RUN_LED_OVERRIDE_OVERRIDEEN_Msk (0x10UL) /*!< OVERRIDEEN (Bitfield-Mask: 0x01) */ +/* =================================================== ERR_LED_OVERRIDE ==================================================== */ + #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Pos (0UL) /*!< LEDCODE (Bit 0) */ + #define R_ESC_ERR_LED_OVERRIDE_LEDCODE_Msk (0xfUL) /*!< LEDCODE (Bitfield-Mask: 0x0f) */ + #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Pos (4UL) /*!< OVERRIDEEN (Bit 4) */ + #define R_ESC_ERR_LED_OVERRIDE_OVERRIDEEN_Msk (0x10UL) /*!< OVERRIDEEN (Bitfield-Mask: 0x01) */ +/* ====================================================== PDI_CONTROL ====================================================== */ + #define R_ESC_PDI_CONTROL_PDI_Pos (0UL) /*!< PDI (Bit 0) */ + #define R_ESC_PDI_CONTROL_PDI_Msk (0xffUL) /*!< PDI (Bitfield-Mask: 0xff) */ +/* ====================================================== ESC_CONFIG ======================================================= */ + #define R_ESC_ESC_CONFIG_DEVEMU_Pos (0UL) /*!< DEVEMU (Bit 0) */ + #define R_ESC_ESC_CONFIG_DEVEMU_Msk (0x1UL) /*!< DEVEMU (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLALLP_Pos (1UL) /*!< ENLALLP (Bit 1) */ + #define R_ESC_ESC_CONFIG_ENLALLP_Msk (0x2UL) /*!< ENLALLP (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_DCSYNC_Pos (2UL) /*!< DCSYNC (Bit 2) */ + #define R_ESC_ESC_CONFIG_DCSYNC_Msk (0x4UL) /*!< DCSYNC (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_DCLATCH_Pos (3UL) /*!< DCLATCH (Bit 3) */ + #define R_ESC_ESC_CONFIG_DCLATCH_Msk (0x8UL) /*!< DCLATCH (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP0_Pos (4UL) /*!< ENLP0 (Bit 4) */ + #define R_ESC_ESC_CONFIG_ENLP0_Msk (0x10UL) /*!< ENLP0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP1_Pos (5UL) /*!< ENLP1 (Bit 5) */ + #define R_ESC_ESC_CONFIG_ENLP1_Msk (0x20UL) /*!< ENLP1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP2_Pos (6UL) /*!< ENLP2 (Bit 6) */ + #define R_ESC_ESC_CONFIG_ENLP2_Msk (0x40UL) /*!< ENLP2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ESC_CONFIG_ENLP3_Pos (7UL) /*!< ENLP3 (Bit 7) */ + #define R_ESC_ESC_CONFIG_ENLP3_Msk (0x80UL) /*!< ENLP3 (Bitfield-Mask: 0x01) */ +/* ====================================================== PDI_CONFIG ======================================================= */ + #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Pos (0UL) /*!< ONCHIPBUSCLK (Bit 0) */ + #define R_ESC_PDI_CONFIG_ONCHIPBUSCLK_Msk (0x1fUL) /*!< ONCHIPBUSCLK (Bitfield-Mask: 0x1f) */ + #define R_ESC_PDI_CONFIG_ONCHIPBUS_Pos (5UL) /*!< ONCHIPBUS (Bit 5) */ + #define R_ESC_PDI_CONFIG_ONCHIPBUS_Msk (0xe0UL) /*!< ONCHIPBUS (Bitfield-Mask: 0x07) */ +/* =================================================== SYNC_LATCH_CONFIG =================================================== */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Pos (0UL) /*!< SYNC0OUT (Bit 0) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0OUT_Msk (0x3UL) /*!< SYNC0OUT (Bitfield-Mask: 0x03) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Pos (2UL) /*!< SYNCLAT0 (Bit 2) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT0_Msk (0x4UL) /*!< SYNCLAT0 (Bitfield-Mask: 0x01) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Pos (3UL) /*!< SYNC0MAP (Bit 3) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC0MAP_Msk (0x8UL) /*!< SYNC0MAP (Bitfield-Mask: 0x01) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Pos (4UL) /*!< SYNC1OUT (Bit 4) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1OUT_Msk (0x30UL) /*!< SYNC1OUT (Bitfield-Mask: 0x03) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Pos (6UL) /*!< SYNCLAT1 (Bit 6) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNCLAT1_Msk (0x40UL) /*!< SYNCLAT1 (Bitfield-Mask: 0x01) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Pos (7UL) /*!< SYNC1MAP (Bit 7) */ + #define R_ESC_SYNC_LATCH_CONFIG_SYNC1MAP_Msk (0x80UL) /*!< SYNC1MAP (Bitfield-Mask: 0x01) */ +/* ==================================================== EXT_PDI_CONFIG ===================================================== */ + #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Pos (0UL) /*!< DATABUSWID (Bit 0) */ + #define R_ESC_EXT_PDI_CONFIG_DATABUSWID_Msk (0x3UL) /*!< DATABUSWID (Bitfield-Mask: 0x03) */ +/* ==================================================== ECAT_EVENT_MASK ==================================================== */ + #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Pos (0UL) /*!< ECATEVMASK (Bit 0) */ + #define R_ESC_ECAT_EVENT_MASK_ECATEVMASK_Msk (0xffffUL) /*!< ECATEVMASK (Bitfield-Mask: 0xffff) */ +/* ===================================================== AL_EVENT_MASK ===================================================== */ + #define R_ESC_AL_EVENT_MASK_ALEVMASK_Pos (0UL) /*!< ALEVMASK (Bit 0) */ + #define R_ESC_AL_EVENT_MASK_ALEVMASK_Msk (0xffffffffUL) /*!< ALEVMASK (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== ECAT_EVENT_REQ ===================================================== */ + #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Pos (0UL) /*!< DCLATCH (Bit 0) */ + #define R_ESC_ECAT_EVENT_REQ_DCLATCH_Msk (0x1UL) /*!< DCLATCH (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_DLSTA_Pos (2UL) /*!< DLSTA (Bit 2) */ + #define R_ESC_ECAT_EVENT_REQ_DLSTA_Msk (0x4UL) /*!< DLSTA (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_ALSTA_Pos (3UL) /*!< ALSTA (Bit 3) */ + #define R_ESC_ECAT_EVENT_REQ_ALSTA_Msk (0x8UL) /*!< ALSTA (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Pos (4UL) /*!< SMSTA0 (Bit 4) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA0_Msk (0x10UL) /*!< SMSTA0 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Pos (5UL) /*!< SMSTA1 (Bit 5) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA1_Msk (0x20UL) /*!< SMSTA1 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Pos (6UL) /*!< SMSTA2 (Bit 6) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA2_Msk (0x40UL) /*!< SMSTA2 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Pos (7UL) /*!< SMSTA3 (Bit 7) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA3_Msk (0x80UL) /*!< SMSTA3 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Pos (8UL) /*!< SMSTA4 (Bit 8) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA4_Msk (0x100UL) /*!< SMSTA4 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Pos (9UL) /*!< SMSTA5 (Bit 9) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA5_Msk (0x200UL) /*!< SMSTA5 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Pos (10UL) /*!< SMSTA6 (Bit 10) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA6_Msk (0x400UL) /*!< SMSTA6 (Bitfield-Mask: 0x01) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Pos (11UL) /*!< SMSTA7 (Bit 11) */ + #define R_ESC_ECAT_EVENT_REQ_SMSTA7_Msk (0x800UL) /*!< SMSTA7 (Bitfield-Mask: 0x01) */ +/* ===================================================== AL_EVENT_REQ ====================================================== */ + #define R_ESC_AL_EVENT_REQ_ALCTRL_Pos (0UL) /*!< ALCTRL (Bit 0) */ + #define R_ESC_AL_EVENT_REQ_ALCTRL_Msk (0x1UL) /*!< ALCTRL (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_DCLATCH_Pos (1UL) /*!< DCLATCH (Bit 1) */ + #define R_ESC_AL_EVENT_REQ_DCLATCH_Msk (0x2UL) /*!< DCLATCH (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Pos (2UL) /*!< DCSYNC0STA (Bit 2) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC0STA_Msk (0x4UL) /*!< DCSYNC0STA (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Pos (3UL) /*!< DCSYNC1STA (Bit 3) */ + #define R_ESC_AL_EVENT_REQ_DCSYNC1STA_Msk (0x8UL) /*!< DCSYNC1STA (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SYNCACT_Pos (4UL) /*!< SYNCACT (Bit 4) */ + #define R_ESC_AL_EVENT_REQ_SYNCACT_Msk (0x10UL) /*!< SYNCACT (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_WDPD_Pos (6UL) /*!< WDPD (Bit 6) */ + #define R_ESC_AL_EVENT_REQ_WDPD_Msk (0x40UL) /*!< WDPD (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT0_Pos (8UL) /*!< SMINT0 (Bit 8) */ + #define R_ESC_AL_EVENT_REQ_SMINT0_Msk (0x100UL) /*!< SMINT0 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT1_Pos (9UL) /*!< SMINT1 (Bit 9) */ + #define R_ESC_AL_EVENT_REQ_SMINT1_Msk (0x200UL) /*!< SMINT1 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT2_Pos (10UL) /*!< SMINT2 (Bit 10) */ + #define R_ESC_AL_EVENT_REQ_SMINT2_Msk (0x400UL) /*!< SMINT2 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT3_Pos (11UL) /*!< SMINT3 (Bit 11) */ + #define R_ESC_AL_EVENT_REQ_SMINT3_Msk (0x800UL) /*!< SMINT3 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT4_Pos (12UL) /*!< SMINT4 (Bit 12) */ + #define R_ESC_AL_EVENT_REQ_SMINT4_Msk (0x1000UL) /*!< SMINT4 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT5_Pos (13UL) /*!< SMINT5 (Bit 13) */ + #define R_ESC_AL_EVENT_REQ_SMINT5_Msk (0x2000UL) /*!< SMINT5 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT6_Pos (14UL) /*!< SMINT6 (Bit 14) */ + #define R_ESC_AL_EVENT_REQ_SMINT6_Msk (0x4000UL) /*!< SMINT6 (Bitfield-Mask: 0x01) */ + #define R_ESC_AL_EVENT_REQ_SMINT7_Pos (15UL) /*!< SMINT7 (Bit 15) */ + #define R_ESC_AL_EVENT_REQ_SMINT7_Msk (0x8000UL) /*!< SMINT7 (Bitfield-Mask: 0x01) */ +/* ===================================================== RX_ERR_COUNT ====================================================== */ + #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Pos (0UL) /*!< INVFRMCNT (Bit 0) */ + #define R_ESC_RX_ERR_COUNT_INVFRMCNT_Msk (0xffUL) /*!< INVFRMCNT (Bitfield-Mask: 0xff) */ + #define R_ESC_RX_ERR_COUNT_RXERRCNT_Pos (8UL) /*!< RXERRCNT (Bit 8) */ + #define R_ESC_RX_ERR_COUNT_RXERRCNT_Msk (0xff00UL) /*!< RXERRCNT (Bitfield-Mask: 0xff) */ +/* =================================================== FWD_RX_ERR_COUNT ==================================================== */ + #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Pos (0UL) /*!< FWDERRCNT (Bit 0) */ + #define R_ESC_FWD_RX_ERR_COUNT_FWDERRCNT_Msk (0xffUL) /*!< FWDERRCNT (Bitfield-Mask: 0xff) */ +/* ================================================== ECAT_PROC_ERR_COUNT ================================================== */ + #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Pos (0UL) /*!< EPUERRCNT (Bit 0) */ + #define R_ESC_ECAT_PROC_ERR_COUNT_EPUERRCNT_Msk (0xffUL) /*!< EPUERRCNT (Bitfield-Mask: 0xff) */ +/* ===================================================== PDI_ERR_COUNT ===================================================== */ + #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Pos (0UL) /*!< PDIERRCNT (Bit 0) */ + #define R_ESC_PDI_ERR_COUNT_PDIERRCNT_Msk (0xffUL) /*!< PDIERRCNT (Bitfield-Mask: 0xff) */ +/* ==================================================== LOST_LINK_COUNT ==================================================== */ + #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Pos (0UL) /*!< LOSTLINKCNT (Bit 0) */ + #define R_ESC_LOST_LINK_COUNT_LOSTLINKCNT_Msk (0xffUL) /*!< LOSTLINKCNT (Bitfield-Mask: 0xff) */ +/* ======================================================= WD_DIVIDE ======================================================= */ + #define R_ESC_WD_DIVIDE_WDDIV_Pos (0UL) /*!< WDDIV (Bit 0) */ + #define R_ESC_WD_DIVIDE_WDDIV_Msk (0xffffUL) /*!< WDDIV (Bitfield-Mask: 0xffff) */ +/* ======================================================== WDT_PDI ======================================================== */ + #define R_ESC_WDT_PDI_WDTIMPDI_Pos (0UL) /*!< WDTIMPDI (Bit 0) */ + #define R_ESC_WDT_PDI_WDTIMPDI_Msk (0xffffUL) /*!< WDTIMPDI (Bitfield-Mask: 0xffff) */ +/* ======================================================= WDT_DATA ======================================================== */ + #define R_ESC_WDT_DATA_WDTIMPD_Pos (0UL) /*!< WDTIMPD (Bit 0) */ + #define R_ESC_WDT_DATA_WDTIMPD_Msk (0xffffUL) /*!< WDTIMPD (Bitfield-Mask: 0xffff) */ +/* ======================================================= WDS_DATA ======================================================== */ + #define R_ESC_WDS_DATA_WDSTAPD_Pos (0UL) /*!< WDSTAPD (Bit 0) */ + #define R_ESC_WDS_DATA_WDSTAPD_Msk (0x1UL) /*!< WDSTAPD (Bitfield-Mask: 0x01) */ +/* ======================================================= WDC_DATA ======================================================== */ + #define R_ESC_WDC_DATA_WDCNTPD_Pos (0UL) /*!< WDCNTPD (Bit 0) */ + #define R_ESC_WDC_DATA_WDCNTPD_Msk (0xffUL) /*!< WDCNTPD (Bitfield-Mask: 0xff) */ +/* ======================================================== WDC_PDI ======================================================== */ + #define R_ESC_WDC_PDI_WDCNTPDI_Pos (0UL) /*!< WDCNTPDI (Bit 0) */ + #define R_ESC_WDC_PDI_WDCNTPDI_Msk (0xffUL) /*!< WDCNTPDI (Bitfield-Mask: 0xff) */ +/* ======================================================= EEP_CONF ======================================================== */ + #define R_ESC_EEP_CONF_CTRLPDI_Pos (0UL) /*!< CTRLPDI (Bit 0) */ + #define R_ESC_EEP_CONF_CTRLPDI_Msk (0x1UL) /*!< CTRLPDI (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONF_FORCEECAT_Pos (1UL) /*!< FORCEECAT (Bit 1) */ + #define R_ESC_EEP_CONF_FORCEECAT_Msk (0x2UL) /*!< FORCEECAT (Bitfield-Mask: 0x01) */ +/* ======================================================= EEP_STATE ======================================================= */ + #define R_ESC_EEP_STATE_PDIACCESS_Pos (0UL) /*!< PDIACCESS (Bit 0) */ + #define R_ESC_EEP_STATE_PDIACCESS_Msk (0x1UL) /*!< PDIACCESS (Bitfield-Mask: 0x01) */ +/* ===================================================== EEP_CONT_STAT ===================================================== */ + #define R_ESC_EEP_CONT_STAT_ECATWREN_Pos (0UL) /*!< ECATWREN (Bit 0) */ + #define R_ESC_EEP_CONT_STAT_ECATWREN_Msk (0x1UL) /*!< ECATWREN (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_READBYTE_Pos (6UL) /*!< READBYTE (Bit 6) */ + #define R_ESC_EEP_CONT_STAT_READBYTE_Msk (0x40UL) /*!< READBYTE (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_PROMSIZE_Pos (7UL) /*!< PROMSIZE (Bit 7) */ + #define R_ESC_EEP_CONT_STAT_PROMSIZE_Msk (0x80UL) /*!< PROMSIZE (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_COMMAND_Pos (8UL) /*!< COMMAND (Bit 8) */ + #define R_ESC_EEP_CONT_STAT_COMMAND_Msk (0x700UL) /*!< COMMAND (Bitfield-Mask: 0x07) */ + #define R_ESC_EEP_CONT_STAT_CKSUMERR_Pos (11UL) /*!< CKSUMERR (Bit 11) */ + #define R_ESC_EEP_CONT_STAT_CKSUMERR_Msk (0x800UL) /*!< CKSUMERR (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_LOADSTA_Pos (12UL) /*!< LOADSTA (Bit 12) */ + #define R_ESC_EEP_CONT_STAT_LOADSTA_Msk (0x1000UL) /*!< LOADSTA (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Pos (13UL) /*!< ACKCMDERR (Bit 13) */ + #define R_ESC_EEP_CONT_STAT_ACKCMDERR_Msk (0x2000UL) /*!< ACKCMDERR (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_WRENERR_Pos (14UL) /*!< WRENERR (Bit 14) */ + #define R_ESC_EEP_CONT_STAT_WRENERR_Msk (0x4000UL) /*!< WRENERR (Bitfield-Mask: 0x01) */ + #define R_ESC_EEP_CONT_STAT_BUSY_Pos (15UL) /*!< BUSY (Bit 15) */ + #define R_ESC_EEP_CONT_STAT_BUSY_Msk (0x8000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== EEP_ADR ======================================================== */ + #define R_ESC_EEP_ADR_ADDRESS_Pos (0UL) /*!< ADDRESS (Bit 0) */ + #define R_ESC_EEP_ADR_ADDRESS_Msk (0xffffffffUL) /*!< ADDRESS (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= EEP_DATA ======================================================== */ + #define R_ESC_EEP_DATA_LODATA_Pos (0UL) /*!< LODATA (Bit 0) */ + #define R_ESC_EEP_DATA_LODATA_Msk (0xffffUL) /*!< LODATA (Bitfield-Mask: 0xffff) */ + #define R_ESC_EEP_DATA_HIDATA_Pos (16UL) /*!< HIDATA (Bit 16) */ + #define R_ESC_EEP_DATA_HIDATA_Msk (0xffff0000UL) /*!< HIDATA (Bitfield-Mask: 0xffff) */ +/* ===================================================== MII_CONT_STAT ===================================================== */ + #define R_ESC_MII_CONT_STAT_WREN_Pos (0UL) /*!< WREN (Bit 0) */ + #define R_ESC_MII_CONT_STAT_WREN_Msk (0x1UL) /*!< WREN (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_PDICTRL_Pos (1UL) /*!< PDICTRL (Bit 1) */ + #define R_ESC_MII_CONT_STAT_PDICTRL_Msk (0x2UL) /*!< PDICTRL (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_MILINK_Pos (2UL) /*!< MILINK (Bit 2) */ + #define R_ESC_MII_CONT_STAT_MILINK_Msk (0x4UL) /*!< MILINK (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_PHYOFFSET_Pos (3UL) /*!< PHYOFFSET (Bit 3) */ + #define R_ESC_MII_CONT_STAT_PHYOFFSET_Msk (0xf8UL) /*!< PHYOFFSET (Bitfield-Mask: 0x1f) */ + #define R_ESC_MII_CONT_STAT_COMMAND_Pos (8UL) /*!< COMMAND (Bit 8) */ + #define R_ESC_MII_CONT_STAT_COMMAND_Msk (0x300UL) /*!< COMMAND (Bitfield-Mask: 0x03) */ + #define R_ESC_MII_CONT_STAT_READERR_Pos (13UL) /*!< READERR (Bit 13) */ + #define R_ESC_MII_CONT_STAT_READERR_Msk (0x2000UL) /*!< READERR (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_CMDERR_Pos (14UL) /*!< CMDERR (Bit 14) */ + #define R_ESC_MII_CONT_STAT_CMDERR_Msk (0x4000UL) /*!< CMDERR (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_CONT_STAT_BUSY_Pos (15UL) /*!< BUSY (Bit 15) */ + #define R_ESC_MII_CONT_STAT_BUSY_Msk (0x8000UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ======================================================== PHY_ADR ======================================================== */ + #define R_ESC_PHY_ADR_PHYADDR_Pos (0UL) /*!< PHYADDR (Bit 0) */ + #define R_ESC_PHY_ADR_PHYADDR_Msk (0x1fUL) /*!< PHYADDR (Bitfield-Mask: 0x1f) */ +/* ====================================================== PHY_REG_ADR ====================================================== */ + #define R_ESC_PHY_REG_ADR_PHYREGADDR_Pos (0UL) /*!< PHYREGADDR (Bit 0) */ + #define R_ESC_PHY_REG_ADR_PHYREGADDR_Msk (0x1fUL) /*!< PHYREGADDR (Bitfield-Mask: 0x1f) */ +/* ======================================================= PHY_DATA ======================================================== */ + #define R_ESC_PHY_DATA_PHYREGDATA_Pos (0UL) /*!< PHYREGDATA (Bit 0) */ + #define R_ESC_PHY_DATA_PHYREGDATA_Msk (0xffffUL) /*!< PHYREGDATA (Bitfield-Mask: 0xffff) */ +/* =================================================== MII_ECAT_ACS_STAT =================================================== */ + #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Pos (0UL) /*!< ACSMII (Bit 0) */ + #define R_ESC_MII_ECAT_ACS_STAT_ACSMII_Msk (0x1UL) /*!< ACSMII (Bitfield-Mask: 0x01) */ +/* =================================================== MII_PDI_ACS_STAT ==================================================== */ + #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Pos (0UL) /*!< ACSMII (Bit 0) */ + #define R_ESC_MII_PDI_ACS_STAT_ACSMII_Msk (0x1UL) /*!< ACSMII (Bitfield-Mask: 0x01) */ + #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Pos (1UL) /*!< FORPDI (Bit 1) */ + #define R_ESC_MII_PDI_ACS_STAT_FORPDI_Msk (0x2UL) /*!< FORPDI (Bitfield-Mask: 0x01) */ +/* =================================================== DC_RCV_TIME_PORT ==================================================== */ + #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Pos (0UL) /*!< RCVTIME0 (Bit 0) */ + #define R_ESC_DC_RCV_TIME_PORT_RCVTIME0_Msk (0xffffffffUL) /*!< RCVTIME0 (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== DC_SYS_TIME_L ===================================================== */ +/* ===================================================== DC_SYS_TIME_H ===================================================== */ +/* ================================================== DC_RCV_TIME_UNIT_L =================================================== */ +/* ================================================== DC_RCV_TIME_UNIT_H =================================================== */ +/* ================================================= DC_SYS_TIME_OFFSET_L ================================================== */ +/* ================================================= DC_SYS_TIME_OFFSET_H ================================================== */ +/* =================================================== DC_SYS_TIME_DELAY =================================================== */ + #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Pos (0UL) /*!< SYSTIMDLY (Bit 0) */ + #define R_ESC_DC_SYS_TIME_DELAY_SYSTIMDLY_Msk (0xffffffffUL) /*!< SYSTIMDLY (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DC_SYS_TIME_DIFF ==================================================== */ + #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Pos (0UL) /*!< DIFF (Bit 0) */ + #define R_ESC_DC_SYS_TIME_DIFF_DIFF_Msk (0x7fffffffUL) /*!< DIFF (Bitfield-Mask: 0x7fffffff) */ + #define R_ESC_DC_SYS_TIME_DIFF_LCP_Pos (31UL) /*!< LCP (Bit 31) */ + #define R_ESC_DC_SYS_TIME_DIFF_LCP_Msk (0x80000000UL) /*!< LCP (Bitfield-Mask: 0x01) */ +/* ================================================= DC_SPEED_COUNT_START ================================================== */ + #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Pos (0UL) /*!< SPDCNTSTRT (Bit 0) */ + #define R_ESC_DC_SPEED_COUNT_START_SPDCNTSTRT_Msk (0x7fffUL) /*!< SPDCNTSTRT (Bitfield-Mask: 0x7fff) */ +/* ================================================== DC_SPEED_COUNT_DIFF ================================================== */ + #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Pos (0UL) /*!< SPDCNTDIFF (Bit 0) */ + #define R_ESC_DC_SPEED_COUNT_DIFF_SPDCNTDIFF_Msk (0xffffUL) /*!< SPDCNTDIFF (Bitfield-Mask: 0xffff) */ +/* ============================================== DC_SYS_TIME_DIFF_FIL_DEPTH =============================================== */ + #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Pos (0UL) /*!< SYSTIMDEP (Bit 0) */ + #define R_ESC_DC_SYS_TIME_DIFF_FIL_DEPTH_SYSTIMDEP_Msk (0xfUL) /*!< SYSTIMDEP (Bitfield-Mask: 0x0f) */ +/* =============================================== DC_SPEED_COUNT_FIL_DEPTH ================================================ */ + #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Pos (0UL) /*!< CLKPERDEP (Bit 0) */ + #define R_ESC_DC_SPEED_COUNT_FIL_DEPTH_CLKPERDEP_Msk (0xfUL) /*!< CLKPERDEP (Bitfield-Mask: 0x0f) */ +/* ====================================================== DC_CYC_CONT ====================================================== */ + #define R_ESC_DC_CYC_CONT_SYNCOUT_Pos (0UL) /*!< SYNCOUT (Bit 0) */ + #define R_ESC_DC_CYC_CONT_SYNCOUT_Msk (0x1UL) /*!< SYNCOUT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_CYC_CONT_LATCH0_Pos (4UL) /*!< LATCH0 (Bit 4) */ + #define R_ESC_DC_CYC_CONT_LATCH0_Msk (0x10UL) /*!< LATCH0 (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_CYC_CONT_LATCH1_Pos (5UL) /*!< LATCH1 (Bit 5) */ + #define R_ESC_DC_CYC_CONT_LATCH1_Msk (0x20UL) /*!< LATCH1 (Bitfield-Mask: 0x01) */ +/* ======================================================== DC_ACT ========================================================= */ + #define R_ESC_DC_ACT_SYNCACT_Pos (0UL) /*!< SYNCACT (Bit 0) */ + #define R_ESC_DC_ACT_SYNCACT_Msk (0x1UL) /*!< SYNCACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_SYNC0_Pos (1UL) /*!< SYNC0 (Bit 1) */ + #define R_ESC_DC_ACT_SYNC0_Msk (0x2UL) /*!< SYNC0 (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_SYNC1_Pos (2UL) /*!< SYNC1 (Bit 2) */ + #define R_ESC_DC_ACT_SYNC1_Msk (0x4UL) /*!< SYNC1 (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_AUTOACT_Pos (3UL) /*!< AUTOACT (Bit 3) */ + #define R_ESC_DC_ACT_AUTOACT_Msk (0x8UL) /*!< AUTOACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_EXTSTARTTIME_Pos (4UL) /*!< EXTSTARTTIME (Bit 4) */ + #define R_ESC_DC_ACT_EXTSTARTTIME_Msk (0x10UL) /*!< EXTSTARTTIME (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_STARTTIME_Pos (5UL) /*!< STARTTIME (Bit 5) */ + #define R_ESC_DC_ACT_STARTTIME_Msk (0x20UL) /*!< STARTTIME (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_NEARFUTURE_Pos (6UL) /*!< NEARFUTURE (Bit 6) */ + #define R_ESC_DC_ACT_NEARFUTURE_Msk (0x40UL) /*!< NEARFUTURE (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_DBGPULSE_Pos (7UL) /*!< DBGPULSE (Bit 7) */ + #define R_ESC_DC_ACT_DBGPULSE_Msk (0x80UL) /*!< DBGPULSE (Bitfield-Mask: 0x01) */ +/* ===================================================== DC_PULSE_LEN ====================================================== */ + #define R_ESC_DC_PULSE_LEN_PULSELEN_Pos (0UL) /*!< PULSELEN (Bit 0) */ + #define R_ESC_DC_PULSE_LEN_PULSELEN_Msk (0xffffUL) /*!< PULSELEN (Bitfield-Mask: 0xffff) */ +/* ====================================================== DC_ACT_STAT ====================================================== */ + #define R_ESC_DC_ACT_STAT_SYNC0ACT_Pos (0UL) /*!< SYNC0ACT (Bit 0) */ + #define R_ESC_DC_ACT_STAT_SYNC0ACT_Msk (0x1UL) /*!< SYNC0ACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_STAT_SYNC1ACT_Pos (1UL) /*!< SYNC1ACT (Bit 1) */ + #define R_ESC_DC_ACT_STAT_SYNC1ACT_Msk (0x2UL) /*!< SYNC1ACT (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_ACT_STAT_STARTTIME_Pos (2UL) /*!< STARTTIME (Bit 2) */ + #define R_ESC_DC_ACT_STAT_STARTTIME_Msk (0x4UL) /*!< STARTTIME (Bitfield-Mask: 0x01) */ +/* ===================================================== DC_SYNC0_STAT ===================================================== */ + #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Pos (0UL) /*!< SYNC0STA (Bit 0) */ + #define R_ESC_DC_SYNC0_STAT_SYNC0STA_Msk (0x1UL) /*!< SYNC0STA (Bitfield-Mask: 0x01) */ +/* ===================================================== DC_SYNC1_STAT ===================================================== */ + #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Pos (0UL) /*!< SYNC1STA (Bit 0) */ + #define R_ESC_DC_SYNC1_STAT_SYNC1STA_Msk (0x1UL) /*!< SYNC1STA (Bitfield-Mask: 0x01) */ +/* ================================================== DC_CYC_START_TIME_L ================================================== */ +/* ================================================== DC_CYC_START_TIME_H ================================================== */ +/* ================================================= DC_NEXT_SYNC1_PULSE_L ================================================= */ +/* ================================================= DC_NEXT_SYNC1_PULSE_H ================================================= */ +/* =================================================== DC_SYNC0_CYC_TIME =================================================== */ + #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Pos (0UL) /*!< SYNC0CYC (Bit 0) */ + #define R_ESC_DC_SYNC0_CYC_TIME_SYNC0CYC_Msk (0xffffffffUL) /*!< SYNC0CYC (Bitfield-Mask: 0xffffffff) */ +/* =================================================== DC_SYNC1_CYC_TIME =================================================== */ + #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Pos (0UL) /*!< SYNC1CYC (Bit 0) */ + #define R_ESC_DC_SYNC1_CYC_TIME_SYNC1CYC_Msk (0xffffffffUL) /*!< SYNC1CYC (Bitfield-Mask: 0xffffffff) */ +/* ==================================================== DC_LATCH0_CONT ===================================================== */ + #define R_ESC_DC_LATCH0_CONT_POSEDGE_Pos (0UL) /*!< POSEDGE (Bit 0) */ + #define R_ESC_DC_LATCH0_CONT_POSEDGE_Msk (0x1UL) /*!< POSEDGE (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Pos (1UL) /*!< NEGEDGE (Bit 1) */ + #define R_ESC_DC_LATCH0_CONT_NEGEDGE_Msk (0x2UL) /*!< NEGEDGE (Bitfield-Mask: 0x01) */ +/* ==================================================== DC_LATCH1_CONT ===================================================== */ + #define R_ESC_DC_LATCH1_CONT_POSEDGE_Pos (0UL) /*!< POSEDGE (Bit 0) */ + #define R_ESC_DC_LATCH1_CONT_POSEDGE_Msk (0x1UL) /*!< POSEDGE (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Pos (1UL) /*!< NEGEDGE (Bit 1) */ + #define R_ESC_DC_LATCH1_CONT_NEGEDGE_Msk (0x2UL) /*!< NEGEDGE (Bitfield-Mask: 0x01) */ +/* ==================================================== DC_LATCH0_STAT ===================================================== */ + #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Pos (0UL) /*!< EVENTPOS (Bit 0) */ + #define R_ESC_DC_LATCH0_STAT_EVENTPOS_Msk (0x1UL) /*!< EVENTPOS (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Pos (1UL) /*!< EVENTNEG (Bit 1) */ + #define R_ESC_DC_LATCH0_STAT_EVENTNEG_Msk (0x2UL) /*!< EVENTNEG (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH0_STAT_PINSTATE_Pos (2UL) /*!< PINSTATE (Bit 2) */ + #define R_ESC_DC_LATCH0_STAT_PINSTATE_Msk (0x4UL) /*!< PINSTATE (Bitfield-Mask: 0x01) */ +/* ==================================================== DC_LATCH1_STAT ===================================================== */ + #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Pos (0UL) /*!< EVENTPOS (Bit 0) */ + #define R_ESC_DC_LATCH1_STAT_EVENTPOS_Msk (0x1UL) /*!< EVENTPOS (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Pos (1UL) /*!< EVENTNEG (Bit 1) */ + #define R_ESC_DC_LATCH1_STAT_EVENTNEG_Msk (0x2UL) /*!< EVENTNEG (Bitfield-Mask: 0x01) */ + #define R_ESC_DC_LATCH1_STAT_PINSTATE_Pos (2UL) /*!< PINSTATE (Bit 2) */ + #define R_ESC_DC_LATCH1_STAT_PINSTATE_Msk (0x4UL) /*!< PINSTATE (Bitfield-Mask: 0x01) */ +/* ================================================= DC_LATCH0_TIME_POS_L ================================================== */ +/* ================================================= DC_LATCH0_TIME_POS_H ================================================== */ +/* ================================================= DC_LATCH0_TIME_NEG_L ================================================== */ +/* ================================================= DC_LATCH0_TIME_NEG_H ================================================== */ +/* ================================================= DC_LATCH1_TIME_POS_L ================================================== */ +/* ================================================= DC_LATCH1_TIME_POS_H ================================================== */ +/* ================================================= DC_LATCH1_TIME_NEG_L ================================================== */ +/* ================================================= DC_LATCH1_TIME_NEG_H ================================================== */ +/* ================================================== DC_ECAT_CNG_EV_TIME ================================================== */ + #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Pos (0UL) /*!< ECATCHANGE (Bit 0) */ + #define R_ESC_DC_ECAT_CNG_EV_TIME_ECATCHANGE_Msk (0xffffffffUL) /*!< ECATCHANGE (Bitfield-Mask: 0xffffffff) */ +/* ================================================= DC_PDI_START_EV_TIME ================================================== */ + #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Pos (0UL) /*!< PDISTART (Bit 0) */ + #define R_ESC_DC_PDI_START_EV_TIME_PDISTART_Msk (0xffffffffUL) /*!< PDISTART (Bitfield-Mask: 0xffffffff) */ +/* ================================================== DC_PDI_CNG_EV_TIME =================================================== */ + #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Pos (0UL) /*!< PDICHANGE (Bit 0) */ + #define R_ESC_DC_PDI_CNG_EV_TIME_PDICHANGE_Msk (0xffffffffUL) /*!< PDICHANGE (Bitfield-Mask: 0xffffffff) */ +/* ===================================================== PRODUCT_ID_L ====================================================== */ +/* ===================================================== PRODUCT_ID_H ====================================================== */ +/* ====================================================== VENDOR_ID_L ====================================================== */ + #define R_ESC_VENDOR_ID_L_VENDORID_Pos (0UL) /*!< VENDORID (Bit 0) */ + #define R_ESC_VENDOR_ID_L_VENDORID_Msk (0xffffffffUL) /*!< VENDORID (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_USBHC ================ */ +/* =========================================================================================================================== */ + +/* ====================================================== HCREVISION ======================================================= */ + #define R_USBHC_HCREVISION_REV_Pos (0UL) /*!< REV (Bit 0) */ + #define R_USBHC_HCREVISION_REV_Msk (0xffUL) /*!< REV (Bitfield-Mask: 0xff) */ +/* ======================================================= HCCONTROL ======================================================= */ + #define R_USBHC_HCCONTROL_CBSR_Pos (0UL) /*!< CBSR (Bit 0) */ + #define R_USBHC_HCCONTROL_CBSR_Msk (0x3UL) /*!< CBSR (Bitfield-Mask: 0x03) */ + #define R_USBHC_HCCONTROL_PLE_Pos (2UL) /*!< PLE (Bit 2) */ + #define R_USBHC_HCCONTROL_PLE_Msk (0x4UL) /*!< PLE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_IE_Pos (3UL) /*!< IE (Bit 3) */ + #define R_USBHC_HCCONTROL_IE_Msk (0x8UL) /*!< IE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_CLE_Pos (4UL) /*!< CLE (Bit 4) */ + #define R_USBHC_HCCONTROL_CLE_Msk (0x10UL) /*!< CLE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_BLE_Pos (5UL) /*!< BLE (Bit 5) */ + #define R_USBHC_HCCONTROL_BLE_Msk (0x20UL) /*!< BLE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_HCFS_Pos (6UL) /*!< HCFS (Bit 6) */ + #define R_USBHC_HCCONTROL_HCFS_Msk (0xc0UL) /*!< HCFS (Bitfield-Mask: 0x03) */ + #define R_USBHC_HCCONTROL_IR_Pos (8UL) /*!< IR (Bit 8) */ + #define R_USBHC_HCCONTROL_IR_Msk (0x100UL) /*!< IR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_RWC_Pos (9UL) /*!< RWC (Bit 9) */ + #define R_USBHC_HCCONTROL_RWC_Msk (0x200UL) /*!< RWC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCONTROL_RWE_Pos (10UL) /*!< RWE (Bit 10) */ + #define R_USBHC_HCCONTROL_RWE_Msk (0x400UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ==================================================== HCCOMMANDSTATUS ==================================================== */ + #define R_USBHC_HCCOMMANDSTATUS_HCR_Pos (0UL) /*!< HCR (Bit 0) */ + #define R_USBHC_HCCOMMANDSTATUS_HCR_Msk (0x1UL) /*!< HCR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_CLF_Pos (1UL) /*!< CLF (Bit 1) */ + #define R_USBHC_HCCOMMANDSTATUS_CLF_Msk (0x2UL) /*!< CLF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_BLF_Pos (2UL) /*!< BLF (Bit 2) */ + #define R_USBHC_HCCOMMANDSTATUS_BLF_Msk (0x4UL) /*!< BLF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_OCR_Pos (3UL) /*!< OCR (Bit 3) */ + #define R_USBHC_HCCOMMANDSTATUS_OCR_Msk (0x8UL) /*!< OCR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCOMMANDSTATUS_SOC_Pos (16UL) /*!< SOC (Bit 16) */ + #define R_USBHC_HCCOMMANDSTATUS_SOC_Msk (0x30000UL) /*!< SOC (Bitfield-Mask: 0x03) */ +/* =================================================== HCINTERRUPTSTATUS =================================================== */ + #define R_USBHC_HCINTERRUPTSTATUS_SO_Pos (0UL) /*!< SO (Bit 0) */ + #define R_USBHC_HCINTERRUPTSTATUS_SO_Msk (0x1UL) /*!< SO (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_WDH_Pos (1UL) /*!< WDH (Bit 1) */ + #define R_USBHC_HCINTERRUPTSTATUS_WDH_Msk (0x2UL) /*!< WDH (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_SF_Pos (2UL) /*!< SF (Bit 2) */ + #define R_USBHC_HCINTERRUPTSTATUS_SF_Msk (0x4UL) /*!< SF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_RD_Pos (3UL) /*!< RD (Bit 3) */ + #define R_USBHC_HCINTERRUPTSTATUS_RD_Msk (0x8UL) /*!< RD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_UE_Pos (4UL) /*!< UE (Bit 4) */ + #define R_USBHC_HCINTERRUPTSTATUS_UE_Msk (0x10UL) /*!< UE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_FNO_Pos (5UL) /*!< FNO (Bit 5) */ + #define R_USBHC_HCINTERRUPTSTATUS_FNO_Msk (0x20UL) /*!< FNO (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Pos (6UL) /*!< RHSC (Bit 6) */ + #define R_USBHC_HCINTERRUPTSTATUS_RHSC_Msk (0x40UL) /*!< RHSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTSTATUS_OC_Pos (30UL) /*!< OC (Bit 30) */ + #define R_USBHC_HCINTERRUPTSTATUS_OC_Msk (0x40000000UL) /*!< OC (Bitfield-Mask: 0x01) */ +/* =================================================== HCINTERRUPTENABLE =================================================== */ + #define R_USBHC_HCINTERRUPTENABLE_SOE_Pos (0UL) /*!< SOE (Bit 0) */ + #define R_USBHC_HCINTERRUPTENABLE_SOE_Msk (0x1UL) /*!< SOE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_WDHE_Pos (1UL) /*!< WDHE (Bit 1) */ + #define R_USBHC_HCINTERRUPTENABLE_WDHE_Msk (0x2UL) /*!< WDHE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_SFE_Pos (2UL) /*!< SFE (Bit 2) */ + #define R_USBHC_HCINTERRUPTENABLE_SFE_Msk (0x4UL) /*!< SFE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_RDE_Pos (3UL) /*!< RDE (Bit 3) */ + #define R_USBHC_HCINTERRUPTENABLE_RDE_Msk (0x8UL) /*!< RDE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_UEE_Pos (4UL) /*!< UEE (Bit 4) */ + #define R_USBHC_HCINTERRUPTENABLE_UEE_Msk (0x10UL) /*!< UEE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_FNOE_Pos (5UL) /*!< FNOE (Bit 5) */ + #define R_USBHC_HCINTERRUPTENABLE_FNOE_Msk (0x20UL) /*!< FNOE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Pos (6UL) /*!< RHSCE (Bit 6) */ + #define R_USBHC_HCINTERRUPTENABLE_RHSCE_Msk (0x40UL) /*!< RHSCE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_OCE_Pos (30UL) /*!< OCE (Bit 30) */ + #define R_USBHC_HCINTERRUPTENABLE_OCE_Msk (0x40000000UL) /*!< OCE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTENABLE_MIE_Pos (31UL) /*!< MIE (Bit 31) */ + #define R_USBHC_HCINTERRUPTENABLE_MIE_Msk (0x80000000UL) /*!< MIE (Bitfield-Mask: 0x01) */ +/* ================================================== HCINTERRUPTDISABLE =================================================== */ + #define R_USBHC_HCINTERRUPTDISABLE_SOD_Pos (0UL) /*!< SOD (Bit 0) */ + #define R_USBHC_HCINTERRUPTDISABLE_SOD_Msk (0x1UL) /*!< SOD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Pos (1UL) /*!< WDHD (Bit 1) */ + #define R_USBHC_HCINTERRUPTDISABLE_WDHD_Msk (0x2UL) /*!< WDHD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_SFD_Pos (2UL) /*!< SFD (Bit 2) */ + #define R_USBHC_HCINTERRUPTDISABLE_SFD_Msk (0x4UL) /*!< SFD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_RDD_Pos (3UL) /*!< RDD (Bit 3) */ + #define R_USBHC_HCINTERRUPTDISABLE_RDD_Msk (0x8UL) /*!< RDD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_UED_Pos (4UL) /*!< UED (Bit 4) */ + #define R_USBHC_HCINTERRUPTDISABLE_UED_Msk (0x10UL) /*!< UED (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Pos (5UL) /*!< FNOD (Bit 5) */ + #define R_USBHC_HCINTERRUPTDISABLE_FNOD_Msk (0x20UL) /*!< FNOD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Pos (6UL) /*!< RHSCD (Bit 6) */ + #define R_USBHC_HCINTERRUPTDISABLE_RHSCD_Msk (0x40UL) /*!< RHSCD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_OCD_Pos (30UL) /*!< OCD (Bit 30) */ + #define R_USBHC_HCINTERRUPTDISABLE_OCD_Msk (0x40000000UL) /*!< OCD (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCINTERRUPTDISABLE_MID_Pos (31UL) /*!< MID (Bit 31) */ + #define R_USBHC_HCINTERRUPTDISABLE_MID_Msk (0x80000000UL) /*!< MID (Bitfield-Mask: 0x01) */ +/* ======================================================== HCHCCA ========================================================= */ + #define R_USBHC_HCHCCA_RAMBA_Pos (8UL) /*!< RAMBA (Bit 8) */ + #define R_USBHC_HCHCCA_RAMBA_Msk (0xffffff00UL) /*!< RAMBA (Bitfield-Mask: 0xffffff) */ +/* ================================================== HCPERIODCCURRENTIED ================================================== */ + #define R_USBHC_HCPERIODCCURRENTIED_PCED_Pos (4UL) /*!< PCED (Bit 4) */ + #define R_USBHC_HCPERIODCCURRENTIED_PCED_Msk (0xfffffff0UL) /*!< PCED (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== HCCONTROLHEADED ==================================================== */ + #define R_USBHC_HCCONTROLHEADED_CHED_Pos (4UL) /*!< CHED (Bit 4) */ + #define R_USBHC_HCCONTROLHEADED_CHED_Msk (0xfffffff0UL) /*!< CHED (Bitfield-Mask: 0xfffffff) */ +/* ================================================== HCCONTROLCURRENTED =================================================== */ + #define R_USBHC_HCCONTROLCURRENTED_CCED_Pos (4UL) /*!< CCED (Bit 4) */ + #define R_USBHC_HCCONTROLCURRENTED_CCED_Msk (0xfffffff0UL) /*!< CCED (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== HCBULKHEADED ====================================================== */ + #define R_USBHC_HCBULKHEADED_BHED_Pos (4UL) /*!< BHED (Bit 4) */ + #define R_USBHC_HCBULKHEADED_BHED_Msk (0xfffffff0UL) /*!< BHED (Bitfield-Mask: 0xfffffff) */ +/* ==================================================== HCBULKCURRENTED ==================================================== */ + #define R_USBHC_HCBULKCURRENTED_BCED_Pos (4UL) /*!< BCED (Bit 4) */ + #define R_USBHC_HCBULKCURRENTED_BCED_Msk (0xfffffff0UL) /*!< BCED (Bitfield-Mask: 0xfffffff) */ +/* ====================================================== HCDONEHEAD ======================================================= */ + #define R_USBHC_HCDONEHEAD_DH_Pos (4UL) /*!< DH (Bit 4) */ + #define R_USBHC_HCDONEHEAD_DH_Msk (0xfffffff0UL) /*!< DH (Bitfield-Mask: 0xfffffff) */ +/* ===================================================== HCFMINTERVAL ====================================================== */ + #define R_USBHC_HCFMINTERVAL_FI_Pos (0UL) /*!< FI (Bit 0) */ + #define R_USBHC_HCFMINTERVAL_FI_Msk (0x3fffUL) /*!< FI (Bitfield-Mask: 0x3fff) */ + #define R_USBHC_HCFMINTERVAL_FSMPS_Pos (16UL) /*!< FSMPS (Bit 16) */ + #define R_USBHC_HCFMINTERVAL_FSMPS_Msk (0x7fff0000UL) /*!< FSMPS (Bitfield-Mask: 0x7fff) */ + #define R_USBHC_HCFMINTERVAL_FIT_Pos (31UL) /*!< FIT (Bit 31) */ + #define R_USBHC_HCFMINTERVAL_FIT_Msk (0x80000000UL) /*!< FIT (Bitfield-Mask: 0x01) */ +/* ===================================================== HCFNREMAINING ===================================================== */ + #define R_USBHC_HCFNREMAINING_FR_Pos (0UL) /*!< FR (Bit 0) */ + #define R_USBHC_HCFNREMAINING_FR_Msk (0x3fffUL) /*!< FR (Bitfield-Mask: 0x3fff) */ + #define R_USBHC_HCFNREMAINING_FRT_Pos (31UL) /*!< FRT (Bit 31) */ + #define R_USBHC_HCFNREMAINING_FRT_Msk (0x80000000UL) /*!< FRT (Bitfield-Mask: 0x01) */ +/* ====================================================== HCFMNUMBER ======================================================= */ + #define R_USBHC_HCFMNUMBER_FN_Pos (0UL) /*!< FN (Bit 0) */ + #define R_USBHC_HCFMNUMBER_FN_Msk (0xffffUL) /*!< FN (Bitfield-Mask: 0xffff) */ +/* ===================================================== HCPERIODSTART ===================================================== */ + #define R_USBHC_HCPERIODSTART_PS_Pos (0UL) /*!< PS (Bit 0) */ + #define R_USBHC_HCPERIODSTART_PS_Msk (0x3fffUL) /*!< PS (Bitfield-Mask: 0x3fff) */ +/* ===================================================== HCLSTHRESHOLD ===================================================== */ + #define R_USBHC_HCLSTHRESHOLD_LS_Pos (0UL) /*!< LS (Bit 0) */ + #define R_USBHC_HCLSTHRESHOLD_LS_Msk (0xfffUL) /*!< LS (Bitfield-Mask: 0xfff) */ +/* ==================================================== HCRHDESCRIPTORA ==================================================== */ + #define R_USBHC_HCRHDESCRIPTORA_NDP_Pos (0UL) /*!< NDP (Bit 0) */ + #define R_USBHC_HCRHDESCRIPTORA_NDP_Msk (0xffUL) /*!< NDP (Bitfield-Mask: 0xff) */ + #define R_USBHC_HCRHDESCRIPTORA_PSM_Pos (8UL) /*!< PSM (Bit 8) */ + #define R_USBHC_HCRHDESCRIPTORA_PSM_Msk (0x100UL) /*!< PSM (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_NPS_Pos (9UL) /*!< NPS (Bit 9) */ + #define R_USBHC_HCRHDESCRIPTORA_NPS_Msk (0x200UL) /*!< NPS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_DT_Pos (10UL) /*!< DT (Bit 10) */ + #define R_USBHC_HCRHDESCRIPTORA_DT_Msk (0x400UL) /*!< DT (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_OCPM_Pos (11UL) /*!< OCPM (Bit 11) */ + #define R_USBHC_HCRHDESCRIPTORA_OCPM_Msk (0x800UL) /*!< OCPM (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_NOCP_Pos (12UL) /*!< NOCP (Bit 12) */ + #define R_USBHC_HCRHDESCRIPTORA_NOCP_Msk (0x1000UL) /*!< NOCP (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Pos (24UL) /*!< POTPGT (Bit 24) */ + #define R_USBHC_HCRHDESCRIPTORA_POTPGT_Msk (0xff000000UL) /*!< POTPGT (Bitfield-Mask: 0xff) */ +/* ==================================================== HCRHDESCRIPTORB ==================================================== */ + #define R_USBHC_HCRHDESCRIPTORB_DR_Pos (0UL) /*!< DR (Bit 0) */ + #define R_USBHC_HCRHDESCRIPTORB_DR_Msk (0xffffUL) /*!< DR (Bitfield-Mask: 0xffff) */ + #define R_USBHC_HCRHDESCRIPTORB_PPCM_Pos (16UL) /*!< PPCM (Bit 16) */ + #define R_USBHC_HCRHDESCRIPTORB_PPCM_Msk (0xffff0000UL) /*!< PPCM (Bitfield-Mask: 0xffff) */ +/* ====================================================== HCRHSTATUS ======================================================= */ + #define R_USBHC_HCRHSTATUS_LPS_Pos (0UL) /*!< LPS (Bit 0) */ + #define R_USBHC_HCRHSTATUS_LPS_Msk (0x1UL) /*!< LPS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_OCI_Pos (1UL) /*!< OCI (Bit 1) */ + #define R_USBHC_HCRHSTATUS_OCI_Msk (0x2UL) /*!< OCI (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_DRWE_Pos (15UL) /*!< DRWE (Bit 15) */ + #define R_USBHC_HCRHSTATUS_DRWE_Msk (0x8000UL) /*!< DRWE (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_LPSC_Pos (16UL) /*!< LPSC (Bit 16) */ + #define R_USBHC_HCRHSTATUS_LPSC_Msk (0x10000UL) /*!< LPSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_OCIC_Pos (17UL) /*!< OCIC (Bit 17) */ + #define R_USBHC_HCRHSTATUS_OCIC_Msk (0x20000UL) /*!< OCIC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHSTATUS_CRWE_Pos (31UL) /*!< CRWE (Bit 31) */ + #define R_USBHC_HCRHSTATUS_CRWE_Msk (0x80000000UL) /*!< CRWE (Bitfield-Mask: 0x01) */ +/* ==================================================== HCRHPORTSTATUS1 ==================================================== */ + #define R_USBHC_HCRHPORTSTATUS1_CCS_Pos (0UL) /*!< CCS (Bit 0) */ + #define R_USBHC_HCRHPORTSTATUS1_CCS_Msk (0x1UL) /*!< CCS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PES_Pos (1UL) /*!< PES (Bit 1) */ + #define R_USBHC_HCRHPORTSTATUS1_PES_Msk (0x2UL) /*!< PES (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PSS_Pos (2UL) /*!< PSS (Bit 2) */ + #define R_USBHC_HCRHPORTSTATUS1_PSS_Msk (0x4UL) /*!< PSS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_POCI_Pos (3UL) /*!< POCI (Bit 3) */ + #define R_USBHC_HCRHPORTSTATUS1_POCI_Msk (0x8UL) /*!< POCI (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PRS_Pos (4UL) /*!< PRS (Bit 4) */ + #define R_USBHC_HCRHPORTSTATUS1_PRS_Msk (0x10UL) /*!< PRS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PPS_Pos (8UL) /*!< PPS (Bit 8) */ + #define R_USBHC_HCRHPORTSTATUS1_PPS_Msk (0x100UL) /*!< PPS (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_LSDA_Pos (9UL) /*!< LSDA (Bit 9) */ + #define R_USBHC_HCRHPORTSTATUS1_LSDA_Msk (0x200UL) /*!< LSDA (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_CSC_Pos (16UL) /*!< CSC (Bit 16) */ + #define R_USBHC_HCRHPORTSTATUS1_CSC_Msk (0x10000UL) /*!< CSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PESC_Pos (17UL) /*!< PESC (Bit 17) */ + #define R_USBHC_HCRHPORTSTATUS1_PESC_Msk (0x20000UL) /*!< PESC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PSSC_Pos (18UL) /*!< PSSC (Bit 18) */ + #define R_USBHC_HCRHPORTSTATUS1_PSSC_Msk (0x40000UL) /*!< PSSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_OCIC_Pos (19UL) /*!< OCIC (Bit 19) */ + #define R_USBHC_HCRHPORTSTATUS1_OCIC_Msk (0x80000UL) /*!< OCIC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCRHPORTSTATUS1_PRSC_Pos (20UL) /*!< PRSC (Bit 20) */ + #define R_USBHC_HCRHPORTSTATUS1_PRSC_Msk (0x100000UL) /*!< PRSC (Bitfield-Mask: 0x01) */ +/* ===================================================== CAPL_VERSION ====================================================== */ + #define R_USBHC_CAPL_VERSION_CRL_Pos (0UL) /*!< CRL (Bit 0) */ + #define R_USBHC_CAPL_VERSION_CRL_Msk (0xffUL) /*!< CRL (Bitfield-Mask: 0xff) */ + #define R_USBHC_CAPL_VERSION_HCIVN_Pos (16UL) /*!< HCIVN (Bit 16) */ + #define R_USBHC_CAPL_VERSION_HCIVN_Msk (0xffff0000UL) /*!< HCIVN (Bitfield-Mask: 0xffff) */ +/* ======================================================= HCSPARAMS ======================================================= */ + #define R_USBHC_HCSPARAMS_N_PORTS_Pos (0UL) /*!< N_PORTS (Bit 0) */ + #define R_USBHC_HCSPARAMS_N_PORTS_Msk (0xfUL) /*!< N_PORTS (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCSPARAMS_PPC_Pos (4UL) /*!< PPC (Bit 4) */ + #define R_USBHC_HCSPARAMS_PPC_Msk (0x10UL) /*!< PPC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCSPARAMS_PTRR_Pos (7UL) /*!< PTRR (Bit 7) */ + #define R_USBHC_HCSPARAMS_PTRR_Msk (0x80UL) /*!< PTRR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCSPARAMS_N_PCC_Pos (8UL) /*!< N_PCC (Bit 8) */ + #define R_USBHC_HCSPARAMS_N_PCC_Msk (0xf00UL) /*!< N_PCC (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCSPARAMS_N_CC_Pos (12UL) /*!< N_CC (Bit 12) */ + #define R_USBHC_HCSPARAMS_N_CC_Msk (0xf000UL) /*!< N_CC (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCSPARAMS_P_INDICATOR_Pos (16UL) /*!< P_INDICATOR (Bit 16) */ + #define R_USBHC_HCSPARAMS_P_INDICATOR_Msk (0x10000UL) /*!< P_INDICATOR (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCSPARAMS_DBGPTNUM_Pos (20UL) /*!< DBGPTNUM (Bit 20) */ + #define R_USBHC_HCSPARAMS_DBGPTNUM_Msk (0xf00000UL) /*!< DBGPTNUM (Bitfield-Mask: 0x0f) */ +/* ======================================================= HCCPARAMS ======================================================= */ + #define R_USBHC_HCCPARAMS_AC64_Pos (0UL) /*!< AC64 (Bit 0) */ + #define R_USBHC_HCCPARAMS_AC64_Msk (0x1UL) /*!< AC64 (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_PFLF_Pos (1UL) /*!< PFLF (Bit 1) */ + #define R_USBHC_HCCPARAMS_PFLF_Msk (0x2UL) /*!< PFLF (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_ASPC_Pos (2UL) /*!< ASPC (Bit 2) */ + #define R_USBHC_HCCPARAMS_ASPC_Msk (0x4UL) /*!< ASPC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_IST_Pos (4UL) /*!< IST (Bit 4) */ + #define R_USBHC_HCCPARAMS_IST_Msk (0xf0UL) /*!< IST (Bitfield-Mask: 0x0f) */ + #define R_USBHC_HCCPARAMS_EECP_Pos (8UL) /*!< EECP (Bit 8) */ + #define R_USBHC_HCCPARAMS_EECP_Msk (0xff00UL) /*!< EECP (Bitfield-Mask: 0xff) */ + #define R_USBHC_HCCPARAMS_HP_Pos (16UL) /*!< HP (Bit 16) */ + #define R_USBHC_HCCPARAMS_HP_Msk (0x10000UL) /*!< HP (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_LPMC_Pos (17UL) /*!< LPMC (Bit 17) */ + #define R_USBHC_HCCPARAMS_LPMC_Msk (0x20000UL) /*!< LPMC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_PCEC_Pos (18UL) /*!< PCEC (Bit 18) */ + #define R_USBHC_HCCPARAMS_PCEC_Msk (0x40000UL) /*!< PCEC (Bitfield-Mask: 0x01) */ + #define R_USBHC_HCCPARAMS_PL32_Pos (19UL) /*!< PL32 (Bit 19) */ + #define R_USBHC_HCCPARAMS_PL32_Msk (0x80000UL) /*!< PL32 (Bitfield-Mask: 0x01) */ +/* ==================================================== HCSP_PORTROUTE ===================================================== */ +/* ======================================================== USBCMD ========================================================= */ + #define R_USBHC_USBCMD_RS_Pos (0UL) /*!< RS (Bit 0) */ + #define R_USBHC_USBCMD_RS_Msk (0x1UL) /*!< RS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_HCRESET_Pos (1UL) /*!< HCRESET (Bit 1) */ + #define R_USBHC_USBCMD_HCRESET_Msk (0x2UL) /*!< HCRESET (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_FLS_Pos (2UL) /*!< FLS (Bit 2) */ + #define R_USBHC_USBCMD_FLS_Msk (0xcUL) /*!< FLS (Bitfield-Mask: 0x03) */ + #define R_USBHC_USBCMD_PSE_Pos (4UL) /*!< PSE (Bit 4) */ + #define R_USBHC_USBCMD_PSE_Msk (0x10UL) /*!< PSE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_ASYNSE_Pos (5UL) /*!< ASYNSE (Bit 5) */ + #define R_USBHC_USBCMD_ASYNSE_Msk (0x20UL) /*!< ASYNSE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_IAAD_Pos (6UL) /*!< IAAD (Bit 6) */ + #define R_USBHC_USBCMD_IAAD_Msk (0x40UL) /*!< IAAD (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_LHCR_Pos (7UL) /*!< LHCR (Bit 7) */ + #define R_USBHC_USBCMD_LHCR_Msk (0x80UL) /*!< LHCR (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_ASPMC_Pos (8UL) /*!< ASPMC (Bit 8) */ + #define R_USBHC_USBCMD_ASPMC_Msk (0x300UL) /*!< ASPMC (Bitfield-Mask: 0x03) */ + #define R_USBHC_USBCMD_ASPME_Pos (11UL) /*!< ASPME (Bit 11) */ + #define R_USBHC_USBCMD_ASPME_Msk (0x800UL) /*!< ASPME (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_PPCEE_Pos (15UL) /*!< PPCEE (Bit 15) */ + #define R_USBHC_USBCMD_PPCEE_Msk (0x8000UL) /*!< PPCEE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCMD_ITC_Pos (16UL) /*!< ITC (Bit 16) */ + #define R_USBHC_USBCMD_ITC_Msk (0xff0000UL) /*!< ITC (Bitfield-Mask: 0xff) */ + #define R_USBHC_USBCMD_HIRD_Pos (24UL) /*!< HIRD (Bit 24) */ + #define R_USBHC_USBCMD_HIRD_Msk (0xf000000UL) /*!< HIRD (Bitfield-Mask: 0x0f) */ +/* ======================================================== USBSTS ========================================================= */ + #define R_USBHC_USBSTS_USBINT_Pos (0UL) /*!< USBINT (Bit 0) */ + #define R_USBHC_USBSTS_USBINT_Msk (0x1UL) /*!< USBINT (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_USBERRINT_Pos (1UL) /*!< USBERRINT (Bit 1) */ + #define R_USBHC_USBSTS_USBERRINT_Msk (0x2UL) /*!< USBERRINT (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_PTCGDET_Pos (2UL) /*!< PTCGDET (Bit 2) */ + #define R_USBHC_USBSTS_PTCGDET_Msk (0x4UL) /*!< PTCGDET (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_FLROV_Pos (3UL) /*!< FLROV (Bit 3) */ + #define R_USBHC_USBSTS_FLROV_Msk (0x8UL) /*!< FLROV (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_HSYSE_Pos (4UL) /*!< HSYSE (Bit 4) */ + #define R_USBHC_USBSTS_HSYSE_Msk (0x10UL) /*!< HSYSE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_IAAIS_Pos (5UL) /*!< IAAIS (Bit 5) */ + #define R_USBHC_USBSTS_IAAIS_Msk (0x20UL) /*!< IAAIS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_EHCSTS_Pos (12UL) /*!< EHCSTS (Bit 12) */ + #define R_USBHC_USBSTS_EHCSTS_Msk (0x1000UL) /*!< EHCSTS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_RECLAM_Pos (13UL) /*!< RECLAM (Bit 13) */ + #define R_USBHC_USBSTS_RECLAM_Msk (0x2000UL) /*!< RECLAM (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_PSCHSTS_Pos (14UL) /*!< PSCHSTS (Bit 14) */ + #define R_USBHC_USBSTS_PSCHSTS_Msk (0x4000UL) /*!< PSCHSTS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_ASS_Pos (15UL) /*!< ASS (Bit 15) */ + #define R_USBHC_USBSTS_ASS_Msk (0x8000UL) /*!< ASS (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBSTS_PTCGDETC_Pos (16UL) /*!< PTCGDETC (Bit 16) */ + #define R_USBHC_USBSTS_PTCGDETC_Msk (0xffff0000UL) /*!< PTCGDETC (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINTR ======================================================== */ + #define R_USBHC_USBINTR_USBIE_Pos (0UL) /*!< USBIE (Bit 0) */ + #define R_USBHC_USBINTR_USBIE_Msk (0x1UL) /*!< USBIE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_USBEIE_Pos (1UL) /*!< USBEIE (Bit 1) */ + #define R_USBHC_USBINTR_USBEIE_Msk (0x2UL) /*!< USBEIE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_PTCGIE_Pos (2UL) /*!< PTCGIE (Bit 2) */ + #define R_USBHC_USBINTR_PTCGIE_Msk (0x4UL) /*!< PTCGIE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_FMLSTROE_Pos (3UL) /*!< FMLSTROE (Bit 3) */ + #define R_USBHC_USBINTR_FMLSTROE_Msk (0x8UL) /*!< FMLSTROE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_HSEE_Pos (4UL) /*!< HSEE (Bit 4) */ + #define R_USBHC_USBINTR_HSEE_Msk (0x10UL) /*!< HSEE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_INTAADVE_Pos (5UL) /*!< INTAADVE (Bit 5) */ + #define R_USBHC_USBINTR_INTAADVE_Msk (0x20UL) /*!< INTAADVE (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBINTR_PCGIE_Pos (16UL) /*!< PCGIE (Bit 16) */ + #define R_USBHC_USBINTR_PCGIE_Msk (0xffff0000UL) /*!< PCGIE (Bitfield-Mask: 0xffff) */ +/* ======================================================== FRINDEX ======================================================== */ + #define R_USBHC_FRINDEX_FRAMEINDEX_Pos (0UL) /*!< FRAMEINDEX (Bit 0) */ + #define R_USBHC_FRINDEX_FRAMEINDEX_Msk (0x3fffUL) /*!< FRAMEINDEX (Bitfield-Mask: 0x3fff) */ +/* ===================================================== CTRLDSSEGMENT ===================================================== */ +/* =================================================== PERIODICLISTBASE ==================================================== */ + #define R_USBHC_PERIODICLISTBASE_PFLSA_Pos (12UL) /*!< PFLSA (Bit 12) */ + #define R_USBHC_PERIODICLISTBASE_PFLSA_Msk (0xfffff000UL) /*!< PFLSA (Bitfield-Mask: 0xfffff) */ +/* ===================================================== ASYNCLISTADDR ===================================================== */ + #define R_USBHC_ASYNCLISTADDR_LPL_Pos (5UL) /*!< LPL (Bit 5) */ + #define R_USBHC_ASYNCLISTADDR_LPL_Msk (0xffffffe0UL) /*!< LPL (Bitfield-Mask: 0x7ffffff) */ +/* ====================================================== CONFIGFLAG ======================================================= */ + #define R_USBHC_CONFIGFLAG_CF_Pos (0UL) /*!< CF (Bit 0) */ + #define R_USBHC_CONFIGFLAG_CF_Msk (0x1UL) /*!< CF (Bitfield-Mask: 0x01) */ +/* ======================================================== PORTSC1 ======================================================== */ + #define R_USBHC_PORTSC1_CCSTS_Pos (0UL) /*!< CCSTS (Bit 0) */ + #define R_USBHC_PORTSC1_CCSTS_Msk (0x1UL) /*!< CCSTS (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_CSC_Pos (1UL) /*!< CSC (Bit 1) */ + #define R_USBHC_PORTSC1_CSC_Msk (0x2UL) /*!< CSC (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTE_Pos (2UL) /*!< PTE (Bit 2) */ + #define R_USBHC_PORTSC1_PTE_Msk (0x4UL) /*!< PTE (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTESC_Pos (3UL) /*!< PTESC (Bit 3) */ + #define R_USBHC_PORTSC1_PTESC_Msk (0x8UL) /*!< PTESC (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_OVCACT_Pos (4UL) /*!< OVCACT (Bit 4) */ + #define R_USBHC_PORTSC1_OVCACT_Msk (0x10UL) /*!< OVCACT (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_OVCC_Pos (5UL) /*!< OVCC (Bit 5) */ + #define R_USBHC_PORTSC1_OVCC_Msk (0x20UL) /*!< OVCC (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_FRCPTRSM_Pos (6UL) /*!< FRCPTRSM (Bit 6) */ + #define R_USBHC_PORTSC1_FRCPTRSM_Msk (0x40UL) /*!< FRCPTRSM (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_SUSPEND_Pos (7UL) /*!< SUSPEND (Bit 7) */ + #define R_USBHC_PORTSC1_SUSPEND_Msk (0x80UL) /*!< SUSPEND (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTRST_Pos (8UL) /*!< PTRST (Bit 8) */ + #define R_USBHC_PORTSC1_PTRST_Msk (0x100UL) /*!< PTRST (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_LPMCTL_Pos (9UL) /*!< LPMCTL (Bit 9) */ + #define R_USBHC_PORTSC1_LPMCTL_Msk (0x200UL) /*!< LPMCTL (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_LINESTS_Pos (10UL) /*!< LINESTS (Bit 10) */ + #define R_USBHC_PORTSC1_LINESTS_Msk (0xc00UL) /*!< LINESTS (Bitfield-Mask: 0x03) */ + #define R_USBHC_PORTSC1_PP_Pos (12UL) /*!< PP (Bit 12) */ + #define R_USBHC_PORTSC1_PP_Msk (0x1000UL) /*!< PP (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTOWNR_Pos (13UL) /*!< PTOWNR (Bit 13) */ + #define R_USBHC_PORTSC1_PTOWNR_Msk (0x2000UL) /*!< PTOWNR (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_PTINDCTL_Pos (14UL) /*!< PTINDCTL (Bit 14) */ + #define R_USBHC_PORTSC1_PTINDCTL_Msk (0xc000UL) /*!< PTINDCTL (Bitfield-Mask: 0x03) */ + #define R_USBHC_PORTSC1_PTTST_Pos (16UL) /*!< PTTST (Bit 16) */ + #define R_USBHC_PORTSC1_PTTST_Msk (0xf0000UL) /*!< PTTST (Bitfield-Mask: 0x0f) */ + #define R_USBHC_PORTSC1_WKCNNT_E_Pos (20UL) /*!< WKCNNT_E (Bit 20) */ + #define R_USBHC_PORTSC1_WKCNNT_E_Msk (0x100000UL) /*!< WKCNNT_E (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_WKDSCNNT_E_Pos (21UL) /*!< WKDSCNNT_E (Bit 21) */ + #define R_USBHC_PORTSC1_WKDSCNNT_E_Msk (0x200000UL) /*!< WKDSCNNT_E (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_WKOC_E_Pos (22UL) /*!< WKOC_E (Bit 22) */ + #define R_USBHC_PORTSC1_WKOC_E_Msk (0x400000UL) /*!< WKOC_E (Bitfield-Mask: 0x01) */ + #define R_USBHC_PORTSC1_SUSPSTS_Pos (23UL) /*!< SUSPSTS (Bit 23) */ + #define R_USBHC_PORTSC1_SUSPSTS_Msk (0x1800000UL) /*!< SUSPSTS (Bitfield-Mask: 0x03) */ + #define R_USBHC_PORTSC1_DVADDR_Pos (25UL) /*!< DVADDR (Bit 25) */ + #define R_USBHC_PORTSC1_DVADDR_Msk (0xfe000000UL) /*!< DVADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================= INTENABLE ======================================================= */ + #define R_USBHC_INTENABLE_AHB_INTEN_Pos (0UL) /*!< AHB_INTEN (Bit 0) */ + #define R_USBHC_INTENABLE_AHB_INTEN_Msk (0x1UL) /*!< AHB_INTEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_USBH_INTAEN_Pos (1UL) /*!< USBH_INTAEN (Bit 1) */ + #define R_USBHC_INTENABLE_USBH_INTAEN_Msk (0x2UL) /*!< USBH_INTAEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_USBH_INTBEN_Pos (2UL) /*!< USBH_INTBEN (Bit 2) */ + #define R_USBHC_INTENABLE_USBH_INTBEN_Msk (0x4UL) /*!< USBH_INTBEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_UCOM_INTEN_Pos (3UL) /*!< UCOM_INTEN (Bit 3) */ + #define R_USBHC_INTENABLE_UCOM_INTEN_Msk (0x8UL) /*!< UCOM_INTEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTENABLE_WAKEON_INTEN_Pos (4UL) /*!< WAKEON_INTEN (Bit 4) */ + #define R_USBHC_INTENABLE_WAKEON_INTEN_Msk (0x10UL) /*!< WAKEON_INTEN (Bitfield-Mask: 0x01) */ +/* ======================================================= INTSTATUS ======================================================= */ + #define R_USBHC_INTSTATUS_AHB_INT_Pos (0UL) /*!< AHB_INT (Bit 0) */ + #define R_USBHC_INTSTATUS_AHB_INT_Msk (0x1UL) /*!< AHB_INT (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_USBH_INTA_Pos (1UL) /*!< USBH_INTA (Bit 1) */ + #define R_USBHC_INTSTATUS_USBH_INTA_Msk (0x2UL) /*!< USBH_INTA (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_USBH_INTB_Pos (2UL) /*!< USBH_INTB (Bit 2) */ + #define R_USBHC_INTSTATUS_USBH_INTB_Msk (0x4UL) /*!< USBH_INTB (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_UCOM_INT_Pos (3UL) /*!< UCOM_INT (Bit 3) */ + #define R_USBHC_INTSTATUS_UCOM_INT_Msk (0x8UL) /*!< UCOM_INT (Bitfield-Mask: 0x01) */ + #define R_USBHC_INTSTATUS_WAKEON_INT_Pos (4UL) /*!< WAKEON_INT (Bit 4) */ + #define R_USBHC_INTSTATUS_WAKEON_INT_Msk (0x10UL) /*!< WAKEON_INT (Bitfield-Mask: 0x01) */ +/* ======================================================= AHBBUSCTR ======================================================= */ + #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Pos (0UL) /*!< MAX_BURST_LEN (Bit 0) */ + #define R_USBHC_AHBBUSCTR_MAX_BURST_LEN_Msk (0x3UL) /*!< MAX_BURST_LEN (Bitfield-Mask: 0x03) */ + #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Pos (4UL) /*!< ALIGN_ADDRESS (Bit 4) */ + #define R_USBHC_AHBBUSCTR_ALIGN_ADDRESS_Msk (0x30UL) /*!< ALIGN_ADDRESS (Bitfield-Mask: 0x03) */ + #define R_USBHC_AHBBUSCTR_PROT_MODE_Pos (8UL) /*!< PROT_MODE (Bit 8) */ + #define R_USBHC_AHBBUSCTR_PROT_MODE_Msk (0x100UL) /*!< PROT_MODE (Bitfield-Mask: 0x01) */ + #define R_USBHC_AHBBUSCTR_PROT_TYPE_Pos (12UL) /*!< PROT_TYPE (Bit 12) */ + #define R_USBHC_AHBBUSCTR_PROT_TYPE_Msk (0xf000UL) /*!< PROT_TYPE (Bitfield-Mask: 0x0f) */ +/* ======================================================== USBCTR ========================================================= */ + #define R_USBHC_USBCTR_USBH_RST_Pos (0UL) /*!< USBH_RST (Bit 0) */ + #define R_USBHC_USBCTR_USBH_RST_Msk (0x1UL) /*!< USBH_RST (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCTR_PLL_RST_Pos (1UL) /*!< PLL_RST (Bit 1) */ + #define R_USBHC_USBCTR_PLL_RST_Msk (0x2UL) /*!< PLL_RST (Bitfield-Mask: 0x01) */ + #define R_USBHC_USBCTR_DIRPD_Pos (2UL) /*!< DIRPD (Bit 2) */ + #define R_USBHC_USBCTR_DIRPD_Msk (0x4UL) /*!< DIRPD (Bitfield-Mask: 0x01) */ +/* ========================================================= REVID ========================================================= */ + #define R_USBHC_REVID_MINV_Pos (0UL) /*!< MINV (Bit 0) */ + #define R_USBHC_REVID_MINV_Msk (0xffUL) /*!< MINV (Bitfield-Mask: 0xff) */ + #define R_USBHC_REVID_MAJV_Pos (8UL) /*!< MAJV (Bit 8) */ + #define R_USBHC_REVID_MAJV_Msk (0xff00UL) /*!< MAJV (Bitfield-Mask: 0xff) */ + #define R_USBHC_REVID_COREID_Pos (24UL) /*!< COREID (Bit 24) */ + #define R_USBHC_REVID_COREID_Msk (0xff000000UL) /*!< COREID (Bitfield-Mask: 0xff) */ +/* ====================================================== OCSLPTIMSET ====================================================== */ + #define R_USBHC_OCSLPTIMSET_TIMER_OC_Pos (0UL) /*!< TIMER_OC (Bit 0) */ + #define R_USBHC_OCSLPTIMSET_TIMER_OC_Msk (0xfffffUL) /*!< TIMER_OC (Bitfield-Mask: 0xfffff) */ + #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Pos (20UL) /*!< TIMER_SLEEP (Bit 20) */ + #define R_USBHC_OCSLPTIMSET_TIMER_SLEEP_Msk (0x1ff00000UL) /*!< TIMER_SLEEP (Bitfield-Mask: 0x1ff) */ +/* ======================================================= COMMCTRL ======================================================== */ + #define R_USBHC_COMMCTRL_PERI_Pos (31UL) /*!< PERI (Bit 31) */ + #define R_USBHC_COMMCTRL_PERI_Msk (0x80000000UL) /*!< PERI (Bitfield-Mask: 0x01) */ +/* ======================================================= OBINTSTA ======================================================== */ + #define R_USBHC_OBINTSTA_IDCHG_STA_Pos (0UL) /*!< IDCHG_STA (Bit 0) */ + #define R_USBHC_OBINTSTA_IDCHG_STA_Msk (0x1UL) /*!< IDCHG_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_OCINT_STA_Pos (1UL) /*!< OCINT_STA (Bit 1) */ + #define R_USBHC_OBINTSTA_OCINT_STA_Msk (0x2UL) /*!< OCINT_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_VBSTACHG_STA_Pos (2UL) /*!< VBSTACHG_STA (Bit 2) */ + #define R_USBHC_OBINTSTA_VBSTACHG_STA_Msk (0x4UL) /*!< VBSTACHG_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_VBSTAINT_STA_Pos (3UL) /*!< VBSTAINT_STA (Bit 3) */ + #define R_USBHC_OBINTSTA_VBSTAINT_STA_Msk (0x8UL) /*!< VBSTAINT_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_DMMONCHG_STA_Pos (16UL) /*!< DMMONCHG_STA (Bit 16) */ + #define R_USBHC_OBINTSTA_DMMONCHG_STA_Msk (0x10000UL) /*!< DMMONCHG_STA (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTSTA_DPMONCHG_STA_Pos (17UL) /*!< DPMONCHG_STA (Bit 17) */ + #define R_USBHC_OBINTSTA_DPMONCHG_STA_Msk (0x20000UL) /*!< DPMONCHG_STA (Bitfield-Mask: 0x01) */ +/* ======================================================== OBINTEN ======================================================== */ + #define R_USBHC_OBINTEN_IDCHG_EN_Pos (0UL) /*!< IDCHG_EN (Bit 0) */ + #define R_USBHC_OBINTEN_IDCHG_EN_Msk (0x1UL) /*!< IDCHG_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_OCINT_EN_Pos (1UL) /*!< OCINT_EN (Bit 1) */ + #define R_USBHC_OBINTEN_OCINT_EN_Msk (0x2UL) /*!< OCINT_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_VBSTACHG_EN_Pos (2UL) /*!< VBSTACHG_EN (Bit 2) */ + #define R_USBHC_OBINTEN_VBSTACHG_EN_Msk (0x4UL) /*!< VBSTACHG_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_VBSTAINT_EN_Pos (3UL) /*!< VBSTAINT_EN (Bit 3) */ + #define R_USBHC_OBINTEN_VBSTAINT_EN_Msk (0x8UL) /*!< VBSTAINT_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_DMMONCHG_EN_Pos (16UL) /*!< DMMONCHG_EN (Bit 16) */ + #define R_USBHC_OBINTEN_DMMONCHG_EN_Msk (0x10000UL) /*!< DMMONCHG_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_OBINTEN_DPMONCHG_EN_Pos (17UL) /*!< DPMONCHG_EN (Bit 17) */ + #define R_USBHC_OBINTEN_DPMONCHG_EN_Msk (0x20000UL) /*!< DPMONCHG_EN (Bitfield-Mask: 0x01) */ +/* ======================================================== VBCTRL ========================================================= */ + #define R_USBHC_VBCTRL_VBOUT_Pos (0UL) /*!< VBOUT (Bit 0) */ + #define R_USBHC_VBCTRL_VBOUT_Msk (0x1UL) /*!< VBOUT (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_VBUSENSEL_Pos (1UL) /*!< VBUSENSEL (Bit 1) */ + #define R_USBHC_VBCTRL_VBUSENSEL_Msk (0x2UL) /*!< VBUSENSEL (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_VGPUO_Pos (4UL) /*!< VGPUO (Bit 4) */ + #define R_USBHC_VBCTRL_VGPUO_Msk (0x10UL) /*!< VGPUO (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_OCCLRIEN_Pos (16UL) /*!< OCCLRIEN (Bit 16) */ + #define R_USBHC_VBCTRL_OCCLRIEN_Msk (0x10000UL) /*!< OCCLRIEN (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_OCISEL_Pos (17UL) /*!< OCISEL (Bit 17) */ + #define R_USBHC_VBCTRL_OCISEL_Msk (0x20000UL) /*!< OCISEL (Bitfield-Mask: 0x01) */ + #define R_USBHC_VBCTRL_VBLVL_Pos (20UL) /*!< VBLVL (Bit 20) */ + #define R_USBHC_VBCTRL_VBLVL_Msk (0xf00000UL) /*!< VBLVL (Bitfield-Mask: 0x0f) */ + #define R_USBHC_VBCTRL_VBSTA_Pos (28UL) /*!< VBSTA (Bit 28) */ + #define R_USBHC_VBCTRL_VBSTA_Msk (0xf0000000UL) /*!< VBSTA (Bitfield-Mask: 0x0f) */ +/* ======================================================= LINECTRL1 ======================================================= */ + #define R_USBHC_LINECTRL1_IDMON_Pos (0UL) /*!< IDMON (Bit 0) */ + #define R_USBHC_LINECTRL1_IDMON_Msk (0x1UL) /*!< IDMON (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DMMON_Pos (2UL) /*!< DMMON (Bit 2) */ + #define R_USBHC_LINECTRL1_DMMON_Msk (0x4UL) /*!< DMMON (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DPMON_Pos (3UL) /*!< DPMON (Bit 3) */ + #define R_USBHC_LINECTRL1_DPMON_Msk (0x8UL) /*!< DPMON (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DM_RPD_Pos (16UL) /*!< DM_RPD (Bit 16) */ + #define R_USBHC_LINECTRL1_DM_RPD_Msk (0x10000UL) /*!< DM_RPD (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DMRPD_EN_Pos (17UL) /*!< DMRPD_EN (Bit 17) */ + #define R_USBHC_LINECTRL1_DMRPD_EN_Msk (0x20000UL) /*!< DMRPD_EN (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DP_RPD_Pos (18UL) /*!< DP_RPD (Bit 18) */ + #define R_USBHC_LINECTRL1_DP_RPD_Msk (0x40000UL) /*!< DP_RPD (Bitfield-Mask: 0x01) */ + #define R_USBHC_LINECTRL1_DPRPD_EN_Pos (19UL) /*!< DPRPD_EN (Bit 19) */ + #define R_USBHC_LINECTRL1_DPRPD_EN_Msk (0x80000UL) /*!< DPRPD_EN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_USBF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SYSCFG0 ======================================================== */ + #define R_USBF_SYSCFG0_USBE_Pos (0UL) /*!< USBE (Bit 0) */ + #define R_USBF_SYSCFG0_USBE_Msk (0x1UL) /*!< USBE (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_DPRPU_Pos (4UL) /*!< DPRPU (Bit 4) */ + #define R_USBF_SYSCFG0_DPRPU_Msk (0x10UL) /*!< DPRPU (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_DRPD_Pos (5UL) /*!< DRPD (Bit 5) */ + #define R_USBF_SYSCFG0_DRPD_Msk (0x20UL) /*!< DRPD (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_HSE_Pos (7UL) /*!< HSE (Bit 7) */ + #define R_USBF_SYSCFG0_HSE_Msk (0x80UL) /*!< HSE (Bitfield-Mask: 0x01) */ + #define R_USBF_SYSCFG0_CNEN_Pos (8UL) /*!< CNEN (Bit 8) */ + #define R_USBF_SYSCFG0_CNEN_Msk (0x100UL) /*!< CNEN (Bitfield-Mask: 0x01) */ +/* ======================================================== SYSCFG1 ======================================================== */ + #define R_USBF_SYSCFG1_BWAIT_Pos (0UL) /*!< BWAIT (Bit 0) */ + #define R_USBF_SYSCFG1_BWAIT_Msk (0x3fUL) /*!< BWAIT (Bitfield-Mask: 0x3f) */ + #define R_USBF_SYSCFG1_AWAIT_Pos (8UL) /*!< AWAIT (Bit 8) */ + #define R_USBF_SYSCFG1_AWAIT_Msk (0x3f00UL) /*!< AWAIT (Bitfield-Mask: 0x3f) */ +/* ======================================================== SYSSTS0 ======================================================== */ + #define R_USBF_SYSSTS0_LNST_Pos (0UL) /*!< LNST (Bit 0) */ + #define R_USBF_SYSSTS0_LNST_Msk (0x3UL) /*!< LNST (Bitfield-Mask: 0x03) */ +/* ======================================================= DVSTCTR0 ======================================================== */ + #define R_USBF_DVSTCTR0_RHST_Pos (0UL) /*!< RHST (Bit 0) */ + #define R_USBF_DVSTCTR0_RHST_Msk (0x7UL) /*!< RHST (Bitfield-Mask: 0x07) */ + #define R_USBF_DVSTCTR0_WKUP_Pos (8UL) /*!< WKUP (Bit 8) */ + #define R_USBF_DVSTCTR0_WKUP_Msk (0x100UL) /*!< WKUP (Bitfield-Mask: 0x01) */ +/* ======================================================= TESTMODE ======================================================== */ + #define R_USBF_TESTMODE_UTST_Pos (0UL) /*!< UTST (Bit 0) */ + #define R_USBF_TESTMODE_UTST_Msk (0xfUL) /*!< UTST (Bitfield-Mask: 0x0f) */ +/* ========================================================= CFIFO ========================================================= */ + #define R_USBF_CFIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_CFIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CFIFOL ========================================================= */ +/* ======================================================== CFIFOLL ======================================================== */ +/* ======================================================== CFIFOH ========================================================= */ + #define R_USBF_CFIFOH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_CFIFOH_FIFOPORT_Msk (0xffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffff) */ +/* ======================================================== CFIFOHH ======================================================== */ + #define R_USBF_CFIFOHH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_CFIFOHH_FIFOPORT_Msk (0xffUL) /*!< FIFOPORT (Bitfield-Mask: 0xff) */ +/* ======================================================== D0FIFO ========================================================= */ + #define R_USBF_D0FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D0FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D0FIFOL ======================================================== */ +/* ======================================================= D0FIFOLL ======================================================== */ +/* ======================================================== D0FIFOH ======================================================== */ + #define R_USBF_D0FIFOH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D0FIFOH_FIFOPORT_Msk (0xffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffff) */ +/* ======================================================= D0FIFOHH ======================================================== */ + #define R_USBF_D0FIFOHH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D0FIFOHH_FIFOPORT_Msk (0xffUL) /*!< FIFOPORT (Bitfield-Mask: 0xff) */ +/* ======================================================== D1FIFO ========================================================= */ + #define R_USBF_D1FIFO_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D1FIFO_FIFOPORT_Msk (0xffffffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== D1FIFOL ======================================================== */ +/* ======================================================= D1FIFOLL ======================================================== */ +/* ======================================================== D1FIFOH ======================================================== */ + #define R_USBF_D1FIFOH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D1FIFOH_FIFOPORT_Msk (0xffffUL) /*!< FIFOPORT (Bitfield-Mask: 0xffff) */ +/* ======================================================= D1FIFOHH ======================================================== */ + #define R_USBF_D1FIFOHH_FIFOPORT_Pos (0UL) /*!< FIFOPORT (Bit 0) */ + #define R_USBF_D1FIFOHH_FIFOPORT_Msk (0xffUL) /*!< FIFOPORT (Bitfield-Mask: 0xff) */ +/* ======================================================= CFIFOSEL ======================================================== */ + #define R_USBF_CFIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USBF_CFIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ + #define R_USBF_CFIFOSEL_ISEL_Pos (5UL) /*!< ISEL (Bit 5) */ + #define R_USBF_CFIFOSEL_ISEL_Msk (0x20UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USBF_CFIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USBF_CFIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USBF_CFIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USBF_CFIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USBF_CFIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ +/* ======================================================= CFIFOCTR ======================================================== */ + #define R_USBF_CFIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USBF_CFIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ + #define R_USBF_CFIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USBF_CFIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USBF_CFIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_CFIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USBF_CFIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ +/* ======================================================= D0FIFOSEL ======================================================= */ + #define R_USBF_D0FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USBF_D0FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ + #define R_USBF_D0FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USBF_D0FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USBF_D0FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USBF_D0FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USBF_D0FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USBF_D0FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USBF_D0FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USBF_D0FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ +/* ======================================================= D1FIFOSEL ======================================================= */ + #define R_USBF_D1FIFOSEL_CURPIPE_Pos (0UL) /*!< CURPIPE (Bit 0) */ + #define R_USBF_D1FIFOSEL_CURPIPE_Msk (0xfUL) /*!< CURPIPE (Bitfield-Mask: 0x0f) */ + #define R_USBF_D1FIFOSEL_BIGEND_Pos (8UL) /*!< BIGEND (Bit 8) */ + #define R_USBF_D1FIFOSEL_BIGEND_Msk (0x100UL) /*!< BIGEND (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_MBW_Pos (10UL) /*!< MBW (Bit 10) */ + #define R_USBF_D1FIFOSEL_MBW_Msk (0xc00UL) /*!< MBW (Bitfield-Mask: 0x03) */ + #define R_USBF_D1FIFOSEL_DREQE_Pos (12UL) /*!< DREQE (Bit 12) */ + #define R_USBF_D1FIFOSEL_DREQE_Msk (0x1000UL) /*!< DREQE (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_DCLRM_Pos (13UL) /*!< DCLRM (Bit 13) */ + #define R_USBF_D1FIFOSEL_DCLRM_Msk (0x2000UL) /*!< DCLRM (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_REW_Pos (14UL) /*!< REW (Bit 14) */ + #define R_USBF_D1FIFOSEL_REW_Msk (0x4000UL) /*!< REW (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOSEL_RCNT_Pos (15UL) /*!< RCNT (Bit 15) */ + #define R_USBF_D1FIFOSEL_RCNT_Msk (0x8000UL) /*!< RCNT (Bitfield-Mask: 0x01) */ +/* ======================================================= D0FIFOCTR ======================================================= */ + #define R_USBF_D0FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USBF_D0FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ + #define R_USBF_D0FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USBF_D0FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USBF_D0FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_D0FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USBF_D0FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ +/* ======================================================= D1FIFOCTR ======================================================= */ + #define R_USBF_D1FIFOCTR_DTLN_Pos (0UL) /*!< DTLN (Bit 0) */ + #define R_USBF_D1FIFOCTR_DTLN_Msk (0xfffUL) /*!< DTLN (Bitfield-Mask: 0xfff) */ + #define R_USBF_D1FIFOCTR_FRDY_Pos (13UL) /*!< FRDY (Bit 13) */ + #define R_USBF_D1FIFOCTR_FRDY_Msk (0x2000UL) /*!< FRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOCTR_BCLR_Pos (14UL) /*!< BCLR (Bit 14) */ + #define R_USBF_D1FIFOCTR_BCLR_Msk (0x4000UL) /*!< BCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_D1FIFOCTR_BVAL_Pos (15UL) /*!< BVAL (Bit 15) */ + #define R_USBF_D1FIFOCTR_BVAL_Msk (0x8000UL) /*!< BVAL (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB0 ======================================================== */ + #define R_USBF_INTENB0_BRDYE_Pos (8UL) /*!< BRDYE (Bit 8) */ + #define R_USBF_INTENB0_BRDYE_Msk (0x100UL) /*!< BRDYE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_NRDYE_Pos (9UL) /*!< NRDYE (Bit 9) */ + #define R_USBF_INTENB0_NRDYE_Msk (0x200UL) /*!< NRDYE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_BEMPE_Pos (10UL) /*!< BEMPE (Bit 10) */ + #define R_USBF_INTENB0_BEMPE_Msk (0x400UL) /*!< BEMPE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_CTRE_Pos (11UL) /*!< CTRE (Bit 11) */ + #define R_USBF_INTENB0_CTRE_Msk (0x800UL) /*!< CTRE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_DVSE_Pos (12UL) /*!< DVSE (Bit 12) */ + #define R_USBF_INTENB0_DVSE_Msk (0x1000UL) /*!< DVSE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_SOFE_Pos (13UL) /*!< SOFE (Bit 13) */ + #define R_USBF_INTENB0_SOFE_Msk (0x2000UL) /*!< SOFE (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_RSME_Pos (14UL) /*!< RSME (Bit 14) */ + #define R_USBF_INTENB0_RSME_Msk (0x4000UL) /*!< RSME (Bitfield-Mask: 0x01) */ + #define R_USBF_INTENB0_VBSE_Pos (15UL) /*!< VBSE (Bit 15) */ + #define R_USBF_INTENB0_VBSE_Msk (0x8000UL) /*!< VBSE (Bitfield-Mask: 0x01) */ +/* ======================================================== INTENB1 ======================================================== */ + #define R_USBF_INTENB1_PDDETINTE_Pos (0UL) /*!< PDDETINTE (Bit 0) */ + #define R_USBF_INTENB1_PDDETINTE_Msk (0x1UL) /*!< PDDETINTE (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYENB ======================================================== */ + #define R_USBF_BRDYENB_PIPEBRDYE_Pos (0UL) /*!< PIPEBRDYE (Bit 0) */ + #define R_USBF_BRDYENB_PIPEBRDYE_Msk (0x3ffUL) /*!< PIPEBRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYENB ======================================================== */ + #define R_USBF_NRDYENB_PIPENRDYE_Pos (0UL) /*!< PIPENRDYE (Bit 0) */ + #define R_USBF_NRDYENB_PIPENRDYE_Msk (0x3ffUL) /*!< PIPENRDYE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPENB ======================================================== */ + #define R_USBF_BEMPENB_PIPEBEMPE_Pos (0UL) /*!< PIPEBEMPE (Bit 0) */ + #define R_USBF_BEMPENB_PIPEBEMPE_Msk (0x3ffUL) /*!< PIPEBEMPE (Bitfield-Mask: 0x3ff) */ +/* ======================================================== SOFCFG ========================================================= */ + #define R_USBF_SOFCFG_EDGESTS_Pos (4UL) /*!< EDGESTS (Bit 4) */ + #define R_USBF_SOFCFG_EDGESTS_Msk (0x10UL) /*!< EDGESTS (Bitfield-Mask: 0x01) */ + #define R_USBF_SOFCFG_INTL_Pos (5UL) /*!< INTL (Bit 5) */ + #define R_USBF_SOFCFG_INTL_Msk (0x20UL) /*!< INTL (Bitfield-Mask: 0x01) */ + #define R_USBF_SOFCFG_BRDYM_Pos (6UL) /*!< BRDYM (Bit 6) */ + #define R_USBF_SOFCFG_BRDYM_Msk (0x40UL) /*!< BRDYM (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS0 ======================================================== */ + #define R_USBF_INTSTS0_CTSQ_Pos (0UL) /*!< CTSQ (Bit 0) */ + #define R_USBF_INTSTS0_CTSQ_Msk (0x7UL) /*!< CTSQ (Bitfield-Mask: 0x07) */ + #define R_USBF_INTSTS0_VALID_Pos (3UL) /*!< VALID (Bit 3) */ + #define R_USBF_INTSTS0_VALID_Msk (0x8UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_DVSQ_Pos (4UL) /*!< DVSQ (Bit 4) */ + #define R_USBF_INTSTS0_DVSQ_Msk (0x70UL) /*!< DVSQ (Bitfield-Mask: 0x07) */ + #define R_USBF_INTSTS0_VBSTS_Pos (7UL) /*!< VBSTS (Bit 7) */ + #define R_USBF_INTSTS0_VBSTS_Msk (0x80UL) /*!< VBSTS (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_BRDY_Pos (8UL) /*!< BRDY (Bit 8) */ + #define R_USBF_INTSTS0_BRDY_Msk (0x100UL) /*!< BRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_NRDY_Pos (9UL) /*!< NRDY (Bit 9) */ + #define R_USBF_INTSTS0_NRDY_Msk (0x200UL) /*!< NRDY (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_BEMP_Pos (10UL) /*!< BEMP (Bit 10) */ + #define R_USBF_INTSTS0_BEMP_Msk (0x400UL) /*!< BEMP (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_CTRT_Pos (11UL) /*!< CTRT (Bit 11) */ + #define R_USBF_INTSTS0_CTRT_Msk (0x800UL) /*!< CTRT (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_DVST_Pos (12UL) /*!< DVST (Bit 12) */ + #define R_USBF_INTSTS0_DVST_Msk (0x1000UL) /*!< DVST (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_SOFR_Pos (13UL) /*!< SOFR (Bit 13) */ + #define R_USBF_INTSTS0_SOFR_Msk (0x2000UL) /*!< SOFR (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_RESM_Pos (14UL) /*!< RESM (Bit 14) */ + #define R_USBF_INTSTS0_RESM_Msk (0x4000UL) /*!< RESM (Bitfield-Mask: 0x01) */ + #define R_USBF_INTSTS0_VBINT_Pos (15UL) /*!< VBINT (Bit 15) */ + #define R_USBF_INTSTS0_VBINT_Msk (0x8000UL) /*!< VBINT (Bitfield-Mask: 0x01) */ +/* ======================================================== INTSTS1 ======================================================== */ + #define R_USBF_INTSTS1_PDDETINT_Pos (0UL) /*!< PDDETINT (Bit 0) */ + #define R_USBF_INTSTS1_PDDETINT_Msk (0x1UL) /*!< PDDETINT (Bitfield-Mask: 0x01) */ +/* ======================================================== BRDYSTS ======================================================== */ + #define R_USBF_BRDYSTS_PIPEBRDY_Pos (0UL) /*!< PIPEBRDY (Bit 0) */ + #define R_USBF_BRDYSTS_PIPEBRDY_Msk (0x3ffUL) /*!< PIPEBRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== NRDYSTS ======================================================== */ + #define R_USBF_NRDYSTS_PIPENRDY_Pos (0UL) /*!< PIPENRDY (Bit 0) */ + #define R_USBF_NRDYSTS_PIPENRDY_Msk (0x3ffUL) /*!< PIPENRDY (Bitfield-Mask: 0x3ff) */ +/* ======================================================== BEMPSTS ======================================================== */ + #define R_USBF_BEMPSTS_PIPEBEMP_Pos (0UL) /*!< PIPEBEMP (Bit 0) */ + #define R_USBF_BEMPSTS_PIPEBEMP_Msk (0x3ffUL) /*!< PIPEBEMP (Bitfield-Mask: 0x3ff) */ +/* ======================================================== FRMNUM ========================================================= */ + #define R_USBF_FRMNUM_FRNM_Pos (0UL) /*!< FRNM (Bit 0) */ + #define R_USBF_FRMNUM_FRNM_Msk (0x7ffUL) /*!< FRNM (Bitfield-Mask: 0x7ff) */ + #define R_USBF_FRMNUM_CRCE_Pos (14UL) /*!< CRCE (Bit 14) */ + #define R_USBF_FRMNUM_CRCE_Msk (0x4000UL) /*!< CRCE (Bitfield-Mask: 0x01) */ + #define R_USBF_FRMNUM_OVRN_Pos (15UL) /*!< OVRN (Bit 15) */ + #define R_USBF_FRMNUM_OVRN_Msk (0x8000UL) /*!< OVRN (Bitfield-Mask: 0x01) */ +/* ======================================================== UFRMNUM ======================================================== */ + #define R_USBF_UFRMNUM_UFRNM_Pos (0UL) /*!< UFRNM (Bit 0) */ + #define R_USBF_UFRMNUM_UFRNM_Msk (0x7UL) /*!< UFRNM (Bitfield-Mask: 0x07) */ +/* ======================================================== USBADDR ======================================================== */ + #define R_USBF_USBADDR_USBADDR_Pos (0UL) /*!< USBADDR (Bit 0) */ + #define R_USBF_USBADDR_USBADDR_Msk (0x7fUL) /*!< USBADDR (Bitfield-Mask: 0x7f) */ +/* ======================================================== USBREQ ========================================================= */ + #define R_USBF_USBREQ_BMREQUESTTYPE_Pos (0UL) /*!< BMREQUESTTYPE (Bit 0) */ + #define R_USBF_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /*!< BMREQUESTTYPE (Bitfield-Mask: 0xff) */ + #define R_USBF_USBREQ_BREQUEST_Pos (8UL) /*!< BREQUEST (Bit 8) */ + #define R_USBF_USBREQ_BREQUEST_Msk (0xff00UL) /*!< BREQUEST (Bitfield-Mask: 0xff) */ +/* ======================================================== USBVAL ========================================================= */ + #define R_USBF_USBVAL_WVALUE_Pos (0UL) /*!< WVALUE (Bit 0) */ + #define R_USBF_USBVAL_WVALUE_Msk (0xffffUL) /*!< WVALUE (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBINDX ======================================================== */ + #define R_USBF_USBINDX_WINDEX_Pos (0UL) /*!< WINDEX (Bit 0) */ + #define R_USBF_USBINDX_WINDEX_Msk (0xffffUL) /*!< WINDEX (Bitfield-Mask: 0xffff) */ +/* ======================================================== USBLENG ======================================================== */ + #define R_USBF_USBLENG_WLENGTH_Pos (0UL) /*!< WLENGTH (Bit 0) */ + #define R_USBF_USBLENG_WLENGTH_Msk (0xffffUL) /*!< WLENGTH (Bitfield-Mask: 0xffff) */ +/* ======================================================== DCPCFG ========================================================= */ + #define R_USBF_DCPCFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USBF_DCPCFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USBF_DCPCFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ +/* ======================================================== DCPMAXP ======================================================== */ + #define R_USBF_DCPMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USBF_DCPMAXP_MXPS_Msk (0x7fUL) /*!< MXPS (Bitfield-Mask: 0x7f) */ +/* ======================================================== DCPCTR ========================================================= */ + #define R_USBF_DCPCTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USBF_DCPCTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ + #define R_USBF_DCPCTR_CCPL_Pos (2UL) /*!< CCPL (Bit 2) */ + #define R_USBF_DCPCTR_CCPL_Msk (0x4UL) /*!< CCPL (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USBF_DCPCTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USBF_DCPCTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USBF_DCPCTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USBF_DCPCTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_DCPCTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USBF_DCPCTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ +/* ======================================================== PIPESEL ======================================================== */ + #define R_USBF_PIPESEL_PIPESEL_Pos (0UL) /*!< PIPESEL (Bit 0) */ + #define R_USBF_PIPESEL_PIPESEL_Msk (0xfUL) /*!< PIPESEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== PIPECFG ======================================================== */ + #define R_USBF_PIPECFG_EPNUM_Pos (0UL) /*!< EPNUM (Bit 0) */ + #define R_USBF_PIPECFG_EPNUM_Msk (0xfUL) /*!< EPNUM (Bitfield-Mask: 0x0f) */ + #define R_USBF_PIPECFG_DIR_Pos (4UL) /*!< DIR (Bit 4) */ + #define R_USBF_PIPECFG_DIR_Msk (0x10UL) /*!< DIR (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_SHTNAK_Pos (7UL) /*!< SHTNAK (Bit 7) */ + #define R_USBF_PIPECFG_SHTNAK_Msk (0x80UL) /*!< SHTNAK (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_CNTMD_Pos (8UL) /*!< CNTMD (Bit 8) */ + #define R_USBF_PIPECFG_CNTMD_Msk (0x100UL) /*!< CNTMD (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_DBLB_Pos (9UL) /*!< DBLB (Bit 9) */ + #define R_USBF_PIPECFG_DBLB_Msk (0x200UL) /*!< DBLB (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_BFRE_Pos (10UL) /*!< BFRE (Bit 10) */ + #define R_USBF_PIPECFG_BFRE_Msk (0x400UL) /*!< BFRE (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPECFG_TYPE_Pos (14UL) /*!< TYPE (Bit 14) */ + #define R_USBF_PIPECFG_TYPE_Msk (0xc000UL) /*!< TYPE (Bitfield-Mask: 0x03) */ +/* ======================================================== PIPEBUF ======================================================== */ + #define R_USBF_PIPEBUF_BUFNMB_Pos (0UL) /*!< BUFNMB (Bit 0) */ + #define R_USBF_PIPEBUF_BUFNMB_Msk (0xffUL) /*!< BUFNMB (Bitfield-Mask: 0xff) */ + #define R_USBF_PIPEBUF_BUFSIZE_Pos (10UL) /*!< BUFSIZE (Bit 10) */ + #define R_USBF_PIPEBUF_BUFSIZE_Msk (0x7c00UL) /*!< BUFSIZE (Bitfield-Mask: 0x1f) */ +/* ======================================================= PIPEMAXP ======================================================== */ + #define R_USBF_PIPEMAXP_MXPS_Pos (0UL) /*!< MXPS (Bit 0) */ + #define R_USBF_PIPEMAXP_MXPS_Msk (0x7ffUL) /*!< MXPS (Bitfield-Mask: 0x7ff) */ +/* ======================================================= PIPEPERI ======================================================== */ + #define R_USBF_PIPEPERI_IITV_Pos (0UL) /*!< IITV (Bit 0) */ + #define R_USBF_PIPEPERI_IITV_Msk (0x7UL) /*!< IITV (Bitfield-Mask: 0x07) */ + #define R_USBF_PIPEPERI_IFIS_Pos (12UL) /*!< IFIS (Bit 12) */ + #define R_USBF_PIPEPERI_IFIS_Msk (0x1000UL) /*!< IFIS (Bitfield-Mask: 0x01) */ +/* ======================================================= PIPE_CTR ======================================================== */ + #define R_USBF_PIPE_CTR_PID_Pos (0UL) /*!< PID (Bit 0) */ + #define R_USBF_PIPE_CTR_PID_Msk (0x3UL) /*!< PID (Bitfield-Mask: 0x03) */ + #define R_USBF_PIPE_CTR_PBUSY_Pos (5UL) /*!< PBUSY (Bit 5) */ + #define R_USBF_PIPE_CTR_PBUSY_Msk (0x20UL) /*!< PBUSY (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_SQMON_Pos (6UL) /*!< SQMON (Bit 6) */ + #define R_USBF_PIPE_CTR_SQMON_Msk (0x40UL) /*!< SQMON (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_SQSET_Pos (7UL) /*!< SQSET (Bit 7) */ + #define R_USBF_PIPE_CTR_SQSET_Msk (0x80UL) /*!< SQSET (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_SQCLR_Pos (8UL) /*!< SQCLR (Bit 8) */ + #define R_USBF_PIPE_CTR_SQCLR_Msk (0x100UL) /*!< SQCLR (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_ACLRM_Pos (9UL) /*!< ACLRM (Bit 9) */ + #define R_USBF_PIPE_CTR_ACLRM_Msk (0x200UL) /*!< ACLRM (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_ATREPM_Pos (10UL) /*!< ATREPM (Bit 10) */ + #define R_USBF_PIPE_CTR_ATREPM_Msk (0x400UL) /*!< ATREPM (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_INBUFM_Pos (14UL) /*!< INBUFM (Bit 14) */ + #define R_USBF_PIPE_CTR_INBUFM_Msk (0x4000UL) /*!< INBUFM (Bitfield-Mask: 0x01) */ + #define R_USBF_PIPE_CTR_BSTS_Pos (15UL) /*!< BSTS (Bit 15) */ + #define R_USBF_PIPE_CTR_BSTS_Msk (0x8000UL) /*!< BSTS (Bitfield-Mask: 0x01) */ +/* ========================================================= LPSTS ========================================================= */ + #define R_USBF_LPSTS_SUSPM_Pos (14UL) /*!< SUSPM (Bit 14) */ + #define R_USBF_LPSTS_SUSPM_Msk (0x4000UL) /*!< SUSPM (Bitfield-Mask: 0x01) */ +/* ========================================================= DCTRL ========================================================= */ + #define R_USBF_DCTRL_PR_Pos (0UL) /*!< PR (Bit 0) */ + #define R_USBF_DCTRL_PR_Msk (0x1UL) /*!< PR (Bitfield-Mask: 0x01) */ + #define R_USBF_DCTRL_LDPR_Pos (16UL) /*!< LDPR (Bit 16) */ + #define R_USBF_DCTRL_LDPR_Msk (0xf0000UL) /*!< LDPR (Bitfield-Mask: 0x0f) */ + #define R_USBF_DCTRL_LWPR_Pos (24UL) /*!< LWPR (Bit 24) */ + #define R_USBF_DCTRL_LWPR_Msk (0xf000000UL) /*!< LWPR (Bitfield-Mask: 0x0f) */ +/* ======================================================== DSCITVL ======================================================== */ + #define R_USBF_DSCITVL_DITVL_Pos (8UL) /*!< DITVL (Bit 8) */ + #define R_USBF_DSCITVL_DITVL_Msk (0xff00UL) /*!< DITVL (Bitfield-Mask: 0xff) */ +/* ======================================================= DSTAT_EN ======================================================== */ + #define R_USBF_DSTAT_EN_EN0_Pos (0UL) /*!< EN0 (Bit 0) */ + #define R_USBF_DSTAT_EN_EN0_Msk (0x1UL) /*!< EN0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_EN_EN1_Pos (1UL) /*!< EN1 (Bit 1) */ + #define R_USBF_DSTAT_EN_EN1_Msk (0x2UL) /*!< EN1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_ER ======================================================== */ + #define R_USBF_DSTAT_ER_ER0_Pos (0UL) /*!< ER0 (Bit 0) */ + #define R_USBF_DSTAT_ER_ER0_Msk (0x1UL) /*!< ER0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_ER_ER1_Pos (1UL) /*!< ER1 (Bit 1) */ + #define R_USBF_DSTAT_ER_ER1_Msk (0x2UL) /*!< ER1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_END ======================================================= */ + #define R_USBF_DSTAT_END_END0_Pos (0UL) /*!< END0 (Bit 0) */ + #define R_USBF_DSTAT_END_END0_Msk (0x1UL) /*!< END0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_END_END1_Pos (1UL) /*!< END1 (Bit 1) */ + #define R_USBF_DSTAT_END_END1_Msk (0x2UL) /*!< END1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_TC ======================================================== */ + #define R_USBF_DSTAT_TC_TC0_Pos (0UL) /*!< TC0 (Bit 0) */ + #define R_USBF_DSTAT_TC_TC0_Msk (0x1UL) /*!< TC0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_TC_TC1_Pos (1UL) /*!< TC1 (Bit 1) */ + #define R_USBF_DSTAT_TC_TC1_Msk (0x2UL) /*!< TC1 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSTAT_SUS ======================================================= */ + #define R_USBF_DSTAT_SUS_SUS0_Pos (0UL) /*!< SUS0 (Bit 0) */ + #define R_USBF_DSTAT_SUS_SUS0_Msk (0x1UL) /*!< SUS0 (Bitfield-Mask: 0x01) */ + #define R_USBF_DSTAT_SUS_SUS1_Pos (1UL) /*!< SUS1 (Bit 1) */ + #define R_USBF_DSTAT_SUS_SUS1_Msk (0x2UL) /*!< SUS1 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_BSC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CMNCR ========================================================= */ + #define R_BSC_CMNCR_DPRTY_Pos (9UL) /*!< DPRTY (Bit 9) */ + #define R_BSC_CMNCR_DPRTY_Msk (0x600UL) /*!< DPRTY (Bitfield-Mask: 0x03) */ + #define R_BSC_CMNCR_AL_Pos (24UL) /*!< AL (Bit 24) */ + #define R_BSC_CMNCR_AL_Msk (0x1000000UL) /*!< AL (Bitfield-Mask: 0x01) */ + #define R_BSC_CMNCR_TL_Pos (28UL) /*!< TL (Bit 28) */ + #define R_BSC_CMNCR_TL_Msk (0x10000000UL) /*!< TL (Bitfield-Mask: 0x01) */ +/* ======================================================== CSnBCR ========================================================= */ + #define R_BSC_CSnBCR_BSZ_Pos (9UL) /*!< BSZ (Bit 9) */ + #define R_BSC_CSnBCR_BSZ_Msk (0x600UL) /*!< BSZ (Bitfield-Mask: 0x03) */ + #define R_BSC_CSnBCR_TYPE_Pos (12UL) /*!< TYPE (Bit 12) */ + #define R_BSC_CSnBCR_TYPE_Msk (0x7000UL) /*!< TYPE (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRRS_Pos (16UL) /*!< IWRRS (Bit 16) */ + #define R_BSC_CSnBCR_IWRRS_Msk (0x70000UL) /*!< IWRRS (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRRD_Pos (19UL) /*!< IWRRD (Bit 19) */ + #define R_BSC_CSnBCR_IWRRD_Msk (0x380000UL) /*!< IWRRD (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRWS_Pos (22UL) /*!< IWRWS (Bit 22) */ + #define R_BSC_CSnBCR_IWRWS_Msk (0x1c00000UL) /*!< IWRWS (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWRWD_Pos (25UL) /*!< IWRWD (Bit 25) */ + #define R_BSC_CSnBCR_IWRWD_Msk (0xe000000UL) /*!< IWRWD (Bitfield-Mask: 0x07) */ + #define R_BSC_CSnBCR_IWW_Pos (28UL) /*!< IWW (Bit 28) */ + #define R_BSC_CSnBCR_IWW_Msk (0x70000000UL) /*!< IWW (Bitfield-Mask: 0x07) */ +/* ======================================================= CS0WCR_0 ======================================================== */ + #define R_BSC_CS0WCR_0_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_BSC_CS0WCR_0_HW_Msk (0x3UL) /*!< HW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS0WCR_0_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS0WCR_0_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS0WCR_0_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS0WCR_0_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS0WCR_0_SW_Pos (11UL) /*!< SW (Bit 11) */ + #define R_BSC_CS0WCR_0_SW_Msk (0x1800UL) /*!< SW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS0WCR_0_BAS_Pos (20UL) /*!< BAS (Bit 20) */ + #define R_BSC_CS0WCR_0_BAS_Msk (0x100000UL) /*!< BAS (Bitfield-Mask: 0x01) */ +/* ======================================================= CS0WCR_1 ======================================================== */ + #define R_BSC_CS0WCR_1_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS0WCR_1_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS0WCR_1_W_Pos (7UL) /*!< W (Bit 7) */ + #define R_BSC_CS0WCR_1_W_Msk (0x780UL) /*!< W (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS0WCR_1_BW_Pos (16UL) /*!< BW (Bit 16) */ + #define R_BSC_CS0WCR_1_BW_Msk (0x30000UL) /*!< BW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS0WCR_1_BST_Pos (20UL) /*!< BST (Bit 20) */ + #define R_BSC_CS0WCR_1_BST_Msk (0x300000UL) /*!< BST (Bitfield-Mask: 0x03) */ +/* ======================================================= CS0WCR_2 ======================================================== */ + #define R_BSC_CS0WCR_2_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS0WCR_2_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS0WCR_2_W_Pos (7UL) /*!< W (Bit 7) */ + #define R_BSC_CS0WCR_2_W_Msk (0x780UL) /*!< W (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS0WCR_2_BW_Pos (16UL) /*!< BW (Bit 16) */ + #define R_BSC_CS0WCR_2_BW_Msk (0x30000UL) /*!< BW (Bitfield-Mask: 0x03) */ +/* ======================================================= CS2WCR_0 ======================================================== */ + #define R_BSC_CS2WCR_0_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS2WCR_0_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS2WCR_0_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS2WCR_0_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS2WCR_0_BAS_Pos (20UL) /*!< BAS (Bit 20) */ + #define R_BSC_CS2WCR_0_BAS_Msk (0x100000UL) /*!< BAS (Bitfield-Mask: 0x01) */ +/* ======================================================= CS2WCR_1 ======================================================== */ + #define R_BSC_CS2WCR_1_A2CL_Pos (7UL) /*!< A2CL (Bit 7) */ + #define R_BSC_CS2WCR_1_A2CL_Msk (0x180UL) /*!< A2CL (Bitfield-Mask: 0x03) */ +/* ======================================================= CS3WCR_0 ======================================================== */ + #define R_BSC_CS3WCR_0_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS3WCR_0_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS3WCR_0_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS3WCR_0_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS3WCR_0_BAS_Pos (20UL) /*!< BAS (Bit 20) */ + #define R_BSC_CS3WCR_0_BAS_Msk (0x100000UL) /*!< BAS (Bitfield-Mask: 0x01) */ +/* ======================================================= CS3WCR_1 ======================================================== */ + #define R_BSC_CS3WCR_1_WTRC_Pos (0UL) /*!< WTRC (Bit 0) */ + #define R_BSC_CS3WCR_1_WTRC_Msk (0x3UL) /*!< WTRC (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_TRWL_Pos (3UL) /*!< TRWL (Bit 3) */ + #define R_BSC_CS3WCR_1_TRWL_Msk (0x18UL) /*!< TRWL (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_A3CL_Pos (7UL) /*!< A3CL (Bit 7) */ + #define R_BSC_CS3WCR_1_A3CL_Msk (0x180UL) /*!< A3CL (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_WTRCD_Pos (10UL) /*!< WTRCD (Bit 10) */ + #define R_BSC_CS3WCR_1_WTRCD_Msk (0xc00UL) /*!< WTRCD (Bitfield-Mask: 0x03) */ + #define R_BSC_CS3WCR_1_WTRP_Pos (13UL) /*!< WTRP (Bit 13) */ + #define R_BSC_CS3WCR_1_WTRP_Msk (0x6000UL) /*!< WTRP (Bitfield-Mask: 0x03) */ +/* ======================================================== CS5WCR ========================================================= */ + #define R_BSC_CS5WCR_HW_Pos (0UL) /*!< HW (Bit 0) */ + #define R_BSC_CS5WCR_HW_Msk (0x3UL) /*!< HW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS5WCR_WM_Pos (6UL) /*!< WM (Bit 6) */ + #define R_BSC_CS5WCR_WM_Msk (0x40UL) /*!< WM (Bitfield-Mask: 0x01) */ + #define R_BSC_CS5WCR_WR_Pos (7UL) /*!< WR (Bit 7) */ + #define R_BSC_CS5WCR_WR_Msk (0x780UL) /*!< WR (Bitfield-Mask: 0x0f) */ + #define R_BSC_CS5WCR_SW_Pos (11UL) /*!< SW (Bit 11) */ + #define R_BSC_CS5WCR_SW_Msk (0x1800UL) /*!< SW (Bitfield-Mask: 0x03) */ + #define R_BSC_CS5WCR_WW_Pos (16UL) /*!< WW (Bit 16) */ + #define R_BSC_CS5WCR_WW_Msk (0x70000UL) /*!< WW (Bitfield-Mask: 0x07) */ + #define R_BSC_CS5WCR_MPXWSBAS_Pos (20UL) /*!< MPXWSBAS (Bit 20) */ + #define R_BSC_CS5WCR_MPXWSBAS_Msk (0x100000UL) /*!< MPXWSBAS (Bitfield-Mask: 0x01) */ + #define R_BSC_CS5WCR_SZSEL_Pos (21UL) /*!< SZSEL (Bit 21) */ + #define R_BSC_CS5WCR_SZSEL_Msk (0x200000UL) /*!< SZSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= SDCR ========================================================== */ + #define R_BSC_SDCR_A3COL_Pos (0UL) /*!< A3COL (Bit 0) */ + #define R_BSC_SDCR_A3COL_Msk (0x3UL) /*!< A3COL (Bitfield-Mask: 0x03) */ + #define R_BSC_SDCR_A3ROW_Pos (3UL) /*!< A3ROW (Bit 3) */ + #define R_BSC_SDCR_A3ROW_Msk (0x18UL) /*!< A3ROW (Bitfield-Mask: 0x03) */ + #define R_BSC_SDCR_BACTV_Pos (8UL) /*!< BACTV (Bit 8) */ + #define R_BSC_SDCR_BACTV_Msk (0x100UL) /*!< BACTV (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_PDOWN_Pos (9UL) /*!< PDOWN (Bit 9) */ + #define R_BSC_SDCR_PDOWN_Msk (0x200UL) /*!< PDOWN (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_RMODE_Pos (10UL) /*!< RMODE (Bit 10) */ + #define R_BSC_SDCR_RMODE_Msk (0x400UL) /*!< RMODE (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_RFSH_Pos (11UL) /*!< RFSH (Bit 11) */ + #define R_BSC_SDCR_RFSH_Msk (0x800UL) /*!< RFSH (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_DEEP_Pos (13UL) /*!< DEEP (Bit 13) */ + #define R_BSC_SDCR_DEEP_Msk (0x2000UL) /*!< DEEP (Bitfield-Mask: 0x01) */ + #define R_BSC_SDCR_A2COL_Pos (16UL) /*!< A2COL (Bit 16) */ + #define R_BSC_SDCR_A2COL_Msk (0x30000UL) /*!< A2COL (Bitfield-Mask: 0x03) */ + #define R_BSC_SDCR_A2ROW_Pos (19UL) /*!< A2ROW (Bit 19) */ + #define R_BSC_SDCR_A2ROW_Msk (0x180000UL) /*!< A2ROW (Bitfield-Mask: 0x03) */ +/* ========================================================= RTCSR ========================================================= */ +/* ========================================================= RTCNT ========================================================= */ +/* ========================================================= RTCOR ========================================================= */ +/* ======================================================== TOSCOR ========================================================= */ + #define R_BSC_TOSCOR_TOCNUM_Pos (0UL) /*!< TOCNUM (Bit 0) */ + #define R_BSC_TOSCOR_TOCNUM_Msk (0xffffUL) /*!< TOCNUM (Bitfield-Mask: 0xffff) */ +/* ========================================================= TOSTR ========================================================= */ + #define R_BSC_TOSTR_CS0TOSTF_Pos (0UL) /*!< CS0TOSTF (Bit 0) */ + #define R_BSC_TOSTR_CS0TOSTF_Msk (0x1UL) /*!< CS0TOSTF (Bitfield-Mask: 0x01) */ + #define R_BSC_TOSTR_CS2TOSTF_Pos (2UL) /*!< CS2TOSTF (Bit 2) */ + #define R_BSC_TOSTR_CS2TOSTF_Msk (0x4UL) /*!< CS2TOSTF (Bitfield-Mask: 0x01) */ + #define R_BSC_TOSTR_CS3TOSTF_Pos (3UL) /*!< CS3TOSTF (Bit 3) */ + #define R_BSC_TOSTR_CS3TOSTF_Msk (0x8UL) /*!< CS3TOSTF (Bitfield-Mask: 0x01) */ + #define R_BSC_TOSTR_CS5TOSTF_Pos (5UL) /*!< CS5TOSTF (Bit 5) */ + #define R_BSC_TOSTR_CS5TOSTF_Msk (0x20UL) /*!< CS5TOSTF (Bitfield-Mask: 0x01) */ +/* ========================================================= TOENR ========================================================= */ + #define R_BSC_TOENR_CS0TOEN_Pos (0UL) /*!< CS0TOEN (Bit 0) */ + #define R_BSC_TOENR_CS0TOEN_Msk (0x1UL) /*!< CS0TOEN (Bitfield-Mask: 0x01) */ + #define R_BSC_TOENR_CS2TOEN_Pos (2UL) /*!< CS2TOEN (Bit 2) */ + #define R_BSC_TOENR_CS2TOEN_Msk (0x4UL) /*!< CS2TOEN (Bitfield-Mask: 0x01) */ + #define R_BSC_TOENR_CS3TOEN_Pos (3UL) /*!< CS3TOEN (Bit 3) */ + #define R_BSC_TOENR_CS3TOEN_Msk (0x8UL) /*!< CS3TOEN (Bitfield-Mask: 0x01) */ + #define R_BSC_TOENR_CS5TOEN_Pos (5UL) /*!< CS5TOEN (Bit 5) */ + #define R_BSC_TOENR_CS5TOEN_Msk (0x20UL) /*!< CS5TOEN (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_XSPI0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== WRAPCFG ======================================================== */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Pos (8UL) /*!< DSSFTCS0 (Bit 8) */ + #define R_XSPI0_WRAPCFG_DSSFTCS0_Msk (0x1f00UL) /*!< DSSFTCS0 (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Pos (24UL) /*!< DSSFTCS1 (Bit 24) */ + #define R_XSPI0_WRAPCFG_DSSFTCS1_Msk (0x1f000000UL) /*!< DSSFTCS1 (Bitfield-Mask: 0x1f) */ +/* ======================================================== COMCFG ========================================================= */ + #define R_XSPI0_COMCFG_OEASTEX_Pos (16UL) /*!< OEASTEX (Bit 16) */ + #define R_XSPI0_COMCFG_OEASTEX_Msk (0x10000UL) /*!< OEASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMCFG_OENEGEX_Pos (17UL) /*!< OENEGEX (Bit 17) */ + #define R_XSPI0_COMCFG_OENEGEX_Msk (0x20000UL) /*!< OENEGEX (Bitfield-Mask: 0x01) */ +/* ========================================================= BMCFG ========================================================= */ + #define R_XSPI0_BMCFG_WRMD_Pos (0UL) /*!< WRMD (Bit 0) */ + #define R_XSPI0_BMCFG_WRMD_Msk (0x1UL) /*!< WRMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFG_MWRCOMB_Pos (7UL) /*!< MWRCOMB (Bit 7) */ + #define R_XSPI0_BMCFG_MWRCOMB_Msk (0x80UL) /*!< MWRCOMB (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCFG_MWRSIZE_Pos (8UL) /*!< MWRSIZE (Bit 8) */ + #define R_XSPI0_BMCFG_MWRSIZE_Msk (0xff00UL) /*!< MWRSIZE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_BMCFG_PREEN_Pos (16UL) /*!< PREEN (Bit 16) */ + #define R_XSPI0_BMCFG_PREEN_Msk (0x10000UL) /*!< PREEN (Bitfield-Mask: 0x01) */ +/* ======================================================= LIOCFGCS ======================================================== */ + #define R_XSPI0_LIOCFGCS_PRTMD_Pos (0UL) /*!< PRTMD (Bit 0) */ + #define R_XSPI0_LIOCFGCS_PRTMD_Msk (0x3ffUL) /*!< PRTMD (Bitfield-Mask: 0x3ff) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Pos (10UL) /*!< LATEMD (Bit 10) */ + #define R_XSPI0_LIOCFGCS_LATEMD_Msk (0x400UL) /*!< LATEMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Pos (11UL) /*!< WRMSKMD (Bit 11) */ + #define R_XSPI0_LIOCFGCS_WRMSKMD_Msk (0x800UL) /*!< WRMSKMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Pos (16UL) /*!< CSMIN (Bit 16) */ + #define R_XSPI0_LIOCFGCS_CSMIN_Msk (0xf0000UL) /*!< CSMIN (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Pos (20UL) /*!< CSASTEX (Bit 20) */ + #define R_XSPI0_LIOCFGCS_CSASTEX_Msk (0x100000UL) /*!< CSASTEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Pos (21UL) /*!< CSNEGEX (Bit 21) */ + #define R_XSPI0_LIOCFGCS_CSNEGEX_Msk (0x200000UL) /*!< CSNEGEX (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Pos (22UL) /*!< SDRDRV (Bit 22) */ + #define R_XSPI0_LIOCFGCS_SDRDRV_Msk (0x400000UL) /*!< SDRDRV (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Pos (23UL) /*!< SDRSMPMD (Bit 23) */ + #define R_XSPI0_LIOCFGCS_SDRSMPMD_Msk (0x800000UL) /*!< SDRSMPMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Pos (24UL) /*!< SDRSMPSFT (Bit 24) */ + #define R_XSPI0_LIOCFGCS_SDRSMPSFT_Msk (0xf000000UL) /*!< SDRSMPSFT (Bitfield-Mask: 0x0f) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Pos (28UL) /*!< DDRSMPEX (Bit 28) */ + #define R_XSPI0_LIOCFGCS_DDRSMPEX_Msk (0xf0000000UL) /*!< DDRSMPEX (Bitfield-Mask: 0x0f) */ +/* ======================================================== BMCTL0 ========================================================= */ + #define R_XSPI0_BMCTL0_CS0ACC_Pos (0UL) /*!< CS0ACC (Bit 0) */ + #define R_XSPI0_BMCTL0_CS0ACC_Msk (0x3UL) /*!< CS0ACC (Bitfield-Mask: 0x03) */ + #define R_XSPI0_BMCTL0_CS1ACC_Pos (2UL) /*!< CS1ACC (Bit 2) */ + #define R_XSPI0_BMCTL0_CS1ACC_Msk (0xcUL) /*!< CS1ACC (Bitfield-Mask: 0x03) */ +/* ======================================================== BMCTL1 ========================================================= */ + #define R_XSPI0_BMCTL1_MWRPUSH_Pos (8UL) /*!< MWRPUSH (Bit 8) */ + #define R_XSPI0_BMCTL1_MWRPUSH_Msk (0x100UL) /*!< MWRPUSH (Bitfield-Mask: 0x01) */ + #define R_XSPI0_BMCTL1_PBUFCLR_Pos (10UL) /*!< PBUFCLR (Bit 10) */ + #define R_XSPI0_BMCTL1_PBUFCLR_Msk (0x400UL) /*!< PBUFCLR (Bitfield-Mask: 0x01) */ +/* ========================================================= CMCTL ========================================================= */ + #define R_XSPI0_CMCTL_XIPENCODE_Pos (0UL) /*!< XIPENCODE (Bit 0) */ + #define R_XSPI0_CMCTL_XIPENCODE_Msk (0xffUL) /*!< XIPENCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTL_XIPEXCODE_Pos (8UL) /*!< XIPEXCODE (Bit 8) */ + #define R_XSPI0_CMCTL_XIPEXCODE_Msk (0xff00UL) /*!< XIPEXCODE (Bitfield-Mask: 0xff) */ + #define R_XSPI0_CMCTL_XIPEN_Pos (16UL) /*!< XIPEN (Bit 16) */ + #define R_XSPI0_CMCTL_XIPEN_Msk (0x10000UL) /*!< XIPEN (Bitfield-Mask: 0x01) */ +/* ======================================================== CSSCTL ========================================================= */ + #define R_XSPI0_CSSCTL_CS0SIZE_Pos (0UL) /*!< CS0SIZE (Bit 0) */ + #define R_XSPI0_CSSCTL_CS0SIZE_Msk (0x3fUL) /*!< CS0SIZE (Bitfield-Mask: 0x3f) */ + #define R_XSPI0_CSSCTL_CS1SIZE_Pos (8UL) /*!< CS1SIZE (Bit 8) */ + #define R_XSPI0_CSSCTL_CS1SIZE_Msk (0x3f00UL) /*!< CS1SIZE (Bitfield-Mask: 0x3f) */ +/* ======================================================== CDCTL0 ========================================================= */ + #define R_XSPI0_CDCTL0_TRREQ_Pos (0UL) /*!< TRREQ (Bit 0) */ + #define R_XSPI0_CDCTL0_TRREQ_Msk (0x1UL) /*!< TRREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_PERMD_Pos (1UL) /*!< PERMD (Bit 1) */ + #define R_XSPI0_CDCTL0_PERMD_Msk (0x2UL) /*!< PERMD (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_CDCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_CDCTL0_TRNUM_Pos (4UL) /*!< TRNUM (Bit 4) */ + #define R_XSPI0_CDCTL0_TRNUM_Msk (0x30UL) /*!< TRNUM (Bitfield-Mask: 0x03) */ + #define R_XSPI0_CDCTL0_PERITV_Pos (16UL) /*!< PERITV (Bit 16) */ + #define R_XSPI0_CDCTL0_PERITV_Msk (0x1f0000UL) /*!< PERITV (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_CDCTL0_PERREP_Pos (24UL) /*!< PERREP (Bit 24) */ + #define R_XSPI0_CDCTL0_PERREP_Msk (0xf000000UL) /*!< PERREP (Bitfield-Mask: 0x0f) */ +/* ======================================================== CDCTL1 ========================================================= */ + #define R_XSPI0_CDCTL1_PEREXP_Pos (0UL) /*!< PEREXP (Bit 0) */ + #define R_XSPI0_CDCTL1_PEREXP_Msk (0xffffffffUL) /*!< PEREXP (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CDCTL2 ========================================================= */ + #define R_XSPI0_CDCTL2_PERMSK_Pos (0UL) /*!< PERMSK (Bit 0) */ + #define R_XSPI0_CDCTL2_PERMSK_Msk (0xffffffffUL) /*!< PERMSK (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== LPCTL0 ========================================================= */ + #define R_XSPI0_LPCTL0_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL0_PATREQ_Msk (0x1UL) /*!< PATREQ (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL0_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XDPIN_Pos (4UL) /*!< XDPIN (Bit 4) */ + #define R_XSPI0_LPCTL0_XDPIN_Msk (0x30UL) /*!< XDPIN (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL0_XD1LEN_Pos (16UL) /*!< XD1LEN (Bit 16) */ + #define R_XSPI0_LPCTL0_XD1LEN_Msk (0x1f0000UL) /*!< XD1LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD1VAL_Pos (23UL) /*!< XD1VAL (Bit 23) */ + #define R_XSPI0_LPCTL0_XD1VAL_Msk (0x800000UL) /*!< XD1VAL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL0_XD2LEN_Pos (24UL) /*!< XD2LEN (Bit 24) */ + #define R_XSPI0_LPCTL0_XD2LEN_Msk (0x1f000000UL) /*!< XD2LEN (Bitfield-Mask: 0x1f) */ + #define R_XSPI0_LPCTL0_XD2VAL_Pos (31UL) /*!< XD2VAL (Bit 31) */ + #define R_XSPI0_LPCTL0_XD2VAL_Msk (0x80000000UL) /*!< XD2VAL (Bitfield-Mask: 0x01) */ +/* ======================================================== LPCTL1 ========================================================= */ + #define R_XSPI0_LPCTL1_PATREQ_Pos (0UL) /*!< PATREQ (Bit 0) */ + #define R_XSPI0_LPCTL1_PATREQ_Msk (0x3UL) /*!< PATREQ (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_CSSEL_Pos (3UL) /*!< CSSEL (Bit 3) */ + #define R_XSPI0_LPCTL1_CSSEL_Msk (0x8UL) /*!< CSSEL (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LPCTL1_RSTREP_Pos (4UL) /*!< RSTREP (Bit 4) */ + #define R_XSPI0_LPCTL1_RSTREP_Msk (0x30UL) /*!< RSTREP (Bitfield-Mask: 0x03) */ + #define R_XSPI0_LPCTL1_RSTWID_Pos (8UL) /*!< RSTWID (Bit 8) */ + #define R_XSPI0_LPCTL1_RSTWID_Msk (0x700UL) /*!< RSTWID (Bitfield-Mask: 0x07) */ + #define R_XSPI0_LPCTL1_RSTSU_Pos (12UL) /*!< RSTSU (Bit 12) */ + #define R_XSPI0_LPCTL1_RSTSU_Msk (0x7000UL) /*!< RSTSU (Bitfield-Mask: 0x07) */ +/* ======================================================== LIOCTL ========================================================= */ + #define R_XSPI0_LIOCTL_WPCS0_Pos (0UL) /*!< WPCS0 (Bit 0) */ + #define R_XSPI0_LIOCTL_WPCS0_Msk (0x1UL) /*!< WPCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_WPCS1_Pos (1UL) /*!< WPCS1 (Bit 1) */ + #define R_XSPI0_LIOCTL_WPCS1_Msk (0x2UL) /*!< WPCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS0_Pos (16UL) /*!< RSTCS0 (Bit 16) */ + #define R_XSPI0_LIOCTL_RSTCS0_Msk (0x10000UL) /*!< RSTCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_LIOCTL_RSTCS1_Pos (17UL) /*!< RSTCS1 (Bit 17) */ + #define R_XSPI0_LIOCTL_RSTCS1_Msk (0x20000UL) /*!< RSTCS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== VERSTT ========================================================= */ + #define R_XSPI0_VERSTT_VER_Pos (0UL) /*!< VER (Bit 0) */ + #define R_XSPI0_VERSTT_VER_Msk (0xffffffffUL) /*!< VER (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== COMSTT ========================================================= */ + #define R_XSPI0_COMSTT_MEMACC_Pos (0UL) /*!< MEMACC (Bit 0) */ + #define R_XSPI0_COMSTT_MEMACC_Msk (0x1UL) /*!< MEMACC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_PBUFNE_Pos (4UL) /*!< PBUFNE (Bit 4) */ + #define R_XSPI0_COMSTT_PBUFNE_Msk (0x10UL) /*!< PBUFNE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_WRBUFNE_Pos (6UL) /*!< WRBUFNE (Bit 6) */ + #define R_XSPI0_COMSTT_WRBUFNE_Msk (0x40UL) /*!< WRBUFNE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS0_Pos (16UL) /*!< ECSCS0 (Bit 16) */ + #define R_XSPI0_COMSTT_ECSCS0_Msk (0x10000UL) /*!< ECSCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS0_Pos (17UL) /*!< INTCS0 (Bit 17) */ + #define R_XSPI0_COMSTT_INTCS0_Msk (0x20000UL) /*!< INTCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS0_Pos (18UL) /*!< RSTOCS0 (Bit 18) */ + #define R_XSPI0_COMSTT_RSTOCS0_Msk (0x40000UL) /*!< RSTOCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_ECSCS1_Pos (20UL) /*!< ECSCS1 (Bit 20) */ + #define R_XSPI0_COMSTT_ECSCS1_Msk (0x100000UL) /*!< ECSCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_INTCS1_Pos (21UL) /*!< INTCS1 (Bit 21) */ + #define R_XSPI0_COMSTT_INTCS1_Msk (0x200000UL) /*!< INTCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_COMSTT_RSTOCS1_Pos (22UL) /*!< RSTOCS1 (Bit 22) */ + #define R_XSPI0_COMSTT_RSTOCS1_Msk (0x400000UL) /*!< RSTOCS1 (Bitfield-Mask: 0x01) */ +/* ======================================================== CASTTCS ======================================================== */ + #define R_XSPI0_CASTTCS_CASUC_Pos (0UL) /*!< CASUC (Bit 0) */ + #define R_XSPI0_CASTTCS_CASUC_Msk (0xffffffffUL) /*!< CASUC (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= INTS ========================================================== */ + #define R_XSPI0_INTS_CMDCMP_Pos (0UL) /*!< CMDCMP (Bit 0) */ + #define R_XSPI0_INTS_CMDCMP_Msk (0x1UL) /*!< CMDCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PATCMP_Pos (1UL) /*!< PATCMP (Bit 1) */ + #define R_XSPI0_INTS_PATCMP_Msk (0x2UL) /*!< PATCMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INICMP_Pos (2UL) /*!< INICMP (Bit 2) */ + #define R_XSPI0_INTS_INICMP_Msk (0x4UL) /*!< INICMP (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_PERTO_Pos (3UL) /*!< PERTO (Bit 3) */ + #define R_XSPI0_INTS_PERTO_Msk (0x8UL) /*!< PERTO (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS0_Pos (4UL) /*!< DSTOCS0 (Bit 4) */ + #define R_XSPI0_INTS_DSTOCS0_Msk (0x10UL) /*!< DSTOCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_DSTOCS1_Pos (5UL) /*!< DSTOCS1 (Bit 5) */ + #define R_XSPI0_INTS_DSTOCS1_Msk (0x20UL) /*!< DSTOCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS0_Pos (8UL) /*!< ECSCS0 (Bit 8) */ + #define R_XSPI0_INTS_ECSCS0_Msk (0x100UL) /*!< ECSCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_ECSCS1_Pos (9UL) /*!< ECSCS1 (Bit 9) */ + #define R_XSPI0_INTS_ECSCS1_Msk (0x200UL) /*!< ECSCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS0_Pos (12UL) /*!< INTCS0 (Bit 12) */ + #define R_XSPI0_INTS_INTCS0_Msk (0x1000UL) /*!< INTCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_INTCS1_Pos (13UL) /*!< INTCS1 (Bit 13) */ + #define R_XSPI0_INTS_INTCS1_Msk (0x2000UL) /*!< INTCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGOF_Pos (16UL) /*!< BRGOF (Bit 16) */ + #define R_XSPI0_INTS_BRGOF_Msk (0x10000UL) /*!< BRGOF (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BRGUF_Pos (18UL) /*!< BRGUF (Bit 18) */ + #define R_XSPI0_INTS_BRGUF_Msk (0x40000UL) /*!< BRGUF (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_BUSERR_Pos (20UL) /*!< BUSERR (Bit 20) */ + #define R_XSPI0_INTS_BUSERR_Msk (0x100000UL) /*!< BUSERR (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS0_Pos (28UL) /*!< CAFAILCS0 (Bit 28) */ + #define R_XSPI0_INTS_CAFAILCS0_Msk (0x10000000UL) /*!< CAFAILCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CAFAILCS1_Pos (29UL) /*!< CAFAILCS1 (Bit 29) */ + #define R_XSPI0_INTS_CAFAILCS1_Msk (0x20000000UL) /*!< CAFAILCS1 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS0_Pos (30UL) /*!< CASUCCS0 (Bit 30) */ + #define R_XSPI0_INTS_CASUCCS0_Msk (0x40000000UL) /*!< CASUCCS0 (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTS_CASUCCS1_Pos (31UL) /*!< CASUCCS1 (Bit 31) */ + #define R_XSPI0_INTS_CASUCCS1_Msk (0x80000000UL) /*!< CASUCCS1 (Bitfield-Mask: 0x01) */ +/* ========================================================= INTC ========================================================== */ + #define R_XSPI0_INTC_CMDCMPC_Pos (0UL) /*!< CMDCMPC (Bit 0) */ + #define R_XSPI0_INTC_CMDCMPC_Msk (0x1UL) /*!< CMDCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PATCMPC_Pos (1UL) /*!< PATCMPC (Bit 1) */ + #define R_XSPI0_INTC_PATCMPC_Msk (0x2UL) /*!< PATCMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INICMPC_Pos (2UL) /*!< INICMPC (Bit 2) */ + #define R_XSPI0_INTC_INICMPC_Msk (0x4UL) /*!< INICMPC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_PERTOC_Pos (3UL) /*!< PERTOC (Bit 3) */ + #define R_XSPI0_INTC_PERTOC_Msk (0x8UL) /*!< PERTOC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCS0C_Pos (4UL) /*!< DSTOCS0C (Bit 4) */ + #define R_XSPI0_INTC_DSTOCS0C_Msk (0x10UL) /*!< DSTOCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_DSTOCS1C_Pos (5UL) /*!< DSTOCS1C (Bit 5) */ + #define R_XSPI0_INTC_DSTOCS1C_Msk (0x20UL) /*!< DSTOCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCS0C_Pos (8UL) /*!< ECSCS0C (Bit 8) */ + #define R_XSPI0_INTC_ECSCS0C_Msk (0x100UL) /*!< ECSCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_ECSCS1C_Pos (9UL) /*!< ECSCS1C (Bit 9) */ + #define R_XSPI0_INTC_ECSCS1C_Msk (0x200UL) /*!< ECSCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCS0C_Pos (12UL) /*!< INTCS0C (Bit 12) */ + #define R_XSPI0_INTC_INTCS0C_Msk (0x1000UL) /*!< INTCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_INTCS1C_Pos (13UL) /*!< INTCS1C (Bit 13) */ + #define R_XSPI0_INTC_INTCS1C_Msk (0x2000UL) /*!< INTCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGOFC_Pos (16UL) /*!< BRGOFC (Bit 16) */ + #define R_XSPI0_INTC_BRGOFC_Msk (0x10000UL) /*!< BRGOFC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BRGUFC_Pos (18UL) /*!< BRGUFC (Bit 18) */ + #define R_XSPI0_INTC_BRGUFC_Msk (0x40000UL) /*!< BRGUFC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_BUSERRC_Pos (20UL) /*!< BUSERRC (Bit 20) */ + #define R_XSPI0_INTC_BUSERRC_Msk (0x100000UL) /*!< BUSERRC (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCS0C_Pos (28UL) /*!< CAFAILCS0C (Bit 28) */ + #define R_XSPI0_INTC_CAFAILCS0C_Msk (0x10000000UL) /*!< CAFAILCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CAFAILCS1C_Pos (29UL) /*!< CAFAILCS1C (Bit 29) */ + #define R_XSPI0_INTC_CAFAILCS1C_Msk (0x20000000UL) /*!< CAFAILCS1C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCS0C_Pos (30UL) /*!< CASUCCS0C (Bit 30) */ + #define R_XSPI0_INTC_CASUCCS0C_Msk (0x40000000UL) /*!< CASUCCS0C (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTC_CASUCCS1C_Pos (31UL) /*!< CASUCCS1C (Bit 31) */ + #define R_XSPI0_INTC_CASUCCS1C_Msk (0x80000000UL) /*!< CASUCCS1C (Bitfield-Mask: 0x01) */ +/* ========================================================= INTE ========================================================== */ + #define R_XSPI0_INTE_CMDCMPE_Pos (0UL) /*!< CMDCMPE (Bit 0) */ + #define R_XSPI0_INTE_CMDCMPE_Msk (0x1UL) /*!< CMDCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PATCMPE_Pos (1UL) /*!< PATCMPE (Bit 1) */ + #define R_XSPI0_INTE_PATCMPE_Msk (0x2UL) /*!< PATCMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INICMPE_Pos (2UL) /*!< INICMPE (Bit 2) */ + #define R_XSPI0_INTE_INICMPE_Msk (0x4UL) /*!< INICMPE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_PERTOE_Pos (3UL) /*!< PERTOE (Bit 3) */ + #define R_XSPI0_INTE_PERTOE_Msk (0x8UL) /*!< PERTOE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCS0E_Pos (4UL) /*!< DSTOCS0E (Bit 4) */ + #define R_XSPI0_INTE_DSTOCS0E_Msk (0x10UL) /*!< DSTOCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_DSTOCS1E_Pos (5UL) /*!< DSTOCS1E (Bit 5) */ + #define R_XSPI0_INTE_DSTOCS1E_Msk (0x20UL) /*!< DSTOCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCS0E_Pos (8UL) /*!< ECSCS0E (Bit 8) */ + #define R_XSPI0_INTE_ECSCS0E_Msk (0x100UL) /*!< ECSCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_ECSCS1E_Pos (9UL) /*!< ECSCS1E (Bit 9) */ + #define R_XSPI0_INTE_ECSCS1E_Msk (0x200UL) /*!< ECSCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCS0E_Pos (12UL) /*!< INTCS0E (Bit 12) */ + #define R_XSPI0_INTE_INTCS0E_Msk (0x1000UL) /*!< INTCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_INTCS1E_Pos (13UL) /*!< INTCS1E (Bit 13) */ + #define R_XSPI0_INTE_INTCS1E_Msk (0x2000UL) /*!< INTCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGOFE_Pos (16UL) /*!< BRGOFE (Bit 16) */ + #define R_XSPI0_INTE_BRGOFE_Msk (0x10000UL) /*!< BRGOFE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BRGUFE_Pos (18UL) /*!< BRGUFE (Bit 18) */ + #define R_XSPI0_INTE_BRGUFE_Msk (0x40000UL) /*!< BRGUFE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_BUSERRE_Pos (20UL) /*!< BUSERRE (Bit 20) */ + #define R_XSPI0_INTE_BUSERRE_Msk (0x100000UL) /*!< BUSERRE (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCS0E_Pos (28UL) /*!< CAFAILCS0E (Bit 28) */ + #define R_XSPI0_INTE_CAFAILCS0E_Msk (0x10000000UL) /*!< CAFAILCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CAFAILCS1E_Pos (29UL) /*!< CAFAILCS1E (Bit 29) */ + #define R_XSPI0_INTE_CAFAILCS1E_Msk (0x20000000UL) /*!< CAFAILCS1E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCS0E_Pos (30UL) /*!< CASUCCS0E (Bit 30) */ + #define R_XSPI0_INTE_CASUCCS0E_Msk (0x40000000UL) /*!< CASUCCS0E (Bitfield-Mask: 0x01) */ + #define R_XSPI0_INTE_CASUCCS1E_Pos (31UL) /*!< CASUCCS1E (Bit 31) */ + #define R_XSPI0_INTE_CASUCCS1E_Msk (0x80000000UL) /*!< CASUCCS1E (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MBXSEM ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== SEM ========================================================== */ + #define R_MBXSEM_SEM_SEM_Pos (0UL) /*!< SEM (Bit 0) */ + #define R_MBXSEM_SEM_SEM_Msk (0x1UL) /*!< SEM (Bitfield-Mask: 0x01) */ +/* ======================================================== SEMRCEN ======================================================== */ + #define R_MBXSEM_SEMRCEN_SEMRCEN0_Pos (0UL) /*!< SEMRCEN0 (Bit 0) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN0_Msk (0x1UL) /*!< SEMRCEN0 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN1_Pos (1UL) /*!< SEMRCEN1 (Bit 1) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN1_Msk (0x2UL) /*!< SEMRCEN1 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN2_Pos (2UL) /*!< SEMRCEN2 (Bit 2) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN2_Msk (0x4UL) /*!< SEMRCEN2 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN3_Pos (3UL) /*!< SEMRCEN3 (Bit 3) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN3_Msk (0x8UL) /*!< SEMRCEN3 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN4_Pos (4UL) /*!< SEMRCEN4 (Bit 4) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN4_Msk (0x10UL) /*!< SEMRCEN4 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN5_Pos (5UL) /*!< SEMRCEN5 (Bit 5) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN5_Msk (0x20UL) /*!< SEMRCEN5 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN6_Pos (6UL) /*!< SEMRCEN6 (Bit 6) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN6_Msk (0x40UL) /*!< SEMRCEN6 (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN7_Pos (7UL) /*!< SEMRCEN7 (Bit 7) */ + #define R_MBXSEM_SEMRCEN_SEMRCEN7_Msk (0x80UL) /*!< SEMRCEN7 (Bitfield-Mask: 0x01) */ +/* ======================================================== MBXH2C ========================================================= */ + #define R_MBXSEM_MBXH2C_MBX_Pos (0UL) /*!< MBX (Bit 0) */ + #define R_MBXSEM_MBXH2C_MBX_Msk (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== MBXISETH2C ======================================================= */ + #define R_MBXSEM_MBXISETH2C_MBX_INT0S_Pos (0UL) /*!< MBX_INT0S (Bit 0) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT0S_Msk (0x1UL) /*!< MBX_INT0S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT1S_Pos (1UL) /*!< MBX_INT1S (Bit 1) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT1S_Msk (0x2UL) /*!< MBX_INT1S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT2S_Pos (2UL) /*!< MBX_INT2S (Bit 2) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT2S_Msk (0x4UL) /*!< MBX_INT2S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT3S_Pos (3UL) /*!< MBX_INT3S (Bit 3) */ + #define R_MBXSEM_MBXISETH2C_MBX_INT3S_Msk (0x8UL) /*!< MBX_INT3S (Bitfield-Mask: 0x01) */ +/* ====================================================== MBXICLRH2C ======================================================= */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT0C_Pos (0UL) /*!< MBX_INT0C (Bit 0) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT0C_Msk (0x1UL) /*!< MBX_INT0C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT1C_Pos (1UL) /*!< MBX_INT1C (Bit 1) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT1C_Msk (0x2UL) /*!< MBX_INT1C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT2C_Pos (2UL) /*!< MBX_INT2C (Bit 2) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT2C_Msk (0x4UL) /*!< MBX_INT2C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT3C_Pos (3UL) /*!< MBX_INT3C (Bit 3) */ + #define R_MBXSEM_MBXICLRH2C_MBX_INT3C_Msk (0x8UL) /*!< MBX_INT3C (Bitfield-Mask: 0x01) */ +/* ======================================================== MBXC2H ========================================================= */ + #define R_MBXSEM_MBXC2H_MBX_Pos (0UL) /*!< MBX (Bit 0) */ + #define R_MBXSEM_MBXC2H_MBX_Msk (0xffffffffUL) /*!< MBX (Bitfield-Mask: 0xffffffff) */ +/* ====================================================== MBXISETC2H ======================================================= */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT0S_Pos (0UL) /*!< MBX_HINT0S (Bit 0) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT0S_Msk (0x1UL) /*!< MBX_HINT0S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT1S_Pos (1UL) /*!< MBX_HINT1S (Bit 1) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT1S_Msk (0x2UL) /*!< MBX_HINT1S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT2S_Pos (2UL) /*!< MBX_HINT2S (Bit 2) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT2S_Msk (0x4UL) /*!< MBX_HINT2S (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT3S_Pos (3UL) /*!< MBX_HINT3S (Bit 3) */ + #define R_MBXSEM_MBXISETC2H_MBX_HINT3S_Msk (0x8UL) /*!< MBX_HINT3S (Bitfield-Mask: 0x01) */ +/* ====================================================== MBXICLRC2H ======================================================= */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT0C_Pos (0UL) /*!< MBX_HINT0C (Bit 0) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT0C_Msk (0x1UL) /*!< MBX_HINT0C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT1C_Pos (1UL) /*!< MBX_HINT1C (Bit 1) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT1C_Msk (0x2UL) /*!< MBX_HINT1C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT2C_Pos (2UL) /*!< MBX_HINT2C (Bit 2) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT2C_Msk (0x4UL) /*!< MBX_HINT2C (Bitfield-Mask: 0x01) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT3C_Pos (3UL) /*!< MBX_HINT3C (Bit 3) */ + #define R_MBXSEM_MBXICLRC2H_MBX_HINT3C_Msk (0x8UL) /*!< MBX_HINT3C (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SHOSTIF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== CTRLR0 ========================================================= */ + #define R_SHOSTIF_CTRLR0_SCPH_Pos (8UL) /*!< SCPH (Bit 8) */ + #define R_SHOSTIF_CTRLR0_SCPH_Msk (0x100UL) /*!< SCPH (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_CTRLR0_SCPOL_Pos (9UL) /*!< SCPOL (Bit 9) */ + #define R_SHOSTIF_CTRLR0_SCPOL_Msk (0x200UL) /*!< SCPOL (Bitfield-Mask: 0x01) */ +/* ========================================================== ENR ========================================================== */ + #define R_SHOSTIF_ENR_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ + #define R_SHOSTIF_ENR_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ +/* ======================================================== RXFBTR ========================================================= */ + #define R_SHOSTIF_RXFBTR_RXFBTL_Pos (0UL) /*!< RXFBTL (Bit 0) */ + #define R_SHOSTIF_RXFBTR_RXFBTL_Msk (0x3fUL) /*!< RXFBTL (Bitfield-Mask: 0x3f) */ +/* ======================================================== TXFTLR ========================================================= */ + #define R_SHOSTIF_TXFTLR_TFT_Pos (0UL) /*!< TFT (Bit 0) */ + #define R_SHOSTIF_TXFTLR_TFT_Msk (0x3fUL) /*!< TFT (Bitfield-Mask: 0x3f) */ +/* ======================================================== RXFTLR ========================================================= */ + #define R_SHOSTIF_RXFTLR_RFT_Pos (0UL) /*!< RFT (Bit 0) */ + #define R_SHOSTIF_RXFTLR_RFT_Msk (0x3fUL) /*!< RFT (Bitfield-Mask: 0x3f) */ +/* ========================================================== SR =========================================================== */ + #define R_SHOSTIF_SR_BUSY_Pos (0UL) /*!< BUSY (Bit 0) */ + #define R_SHOSTIF_SR_BUSY_Msk (0x1UL) /*!< BUSY (Bitfield-Mask: 0x01) */ +/* ========================================================== IMR ========================================================== */ + #define R_SHOSTIF_IMR_TXEIM_Pos (0UL) /*!< TXEIM (Bit 0) */ + #define R_SHOSTIF_IMR_TXEIM_Msk (0x1UL) /*!< TXEIM (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_IMR_RXOIM_Pos (3UL) /*!< RXOIM (Bit 3) */ + #define R_SHOSTIF_IMR_RXOIM_Msk (0x8UL) /*!< RXOIM (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_IMR_RXFIM_Pos (4UL) /*!< RXFIM (Bit 4) */ + #define R_SHOSTIF_IMR_RXFIM_Msk (0x10UL) /*!< RXFIM (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_IMR_TXUIM_Pos (7UL) /*!< TXUIM (Bit 7) */ + #define R_SHOSTIF_IMR_TXUIM_Msk (0x80UL) /*!< TXUIM (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_IMR_AHBEM_Pos (8UL) /*!< AHBEM (Bit 8) */ + #define R_SHOSTIF_IMR_AHBEM_Msk (0x100UL) /*!< AHBEM (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_IMR_SPIMEM_Pos (9UL) /*!< SPIMEM (Bit 9) */ + #define R_SHOSTIF_IMR_SPIMEM_Msk (0x200UL) /*!< SPIMEM (Bitfield-Mask: 0x01) */ +/* ========================================================== ISR ========================================================== */ + #define R_SHOSTIF_ISR_TXEIS_Pos (0UL) /*!< TXEIS (Bit 0) */ + #define R_SHOSTIF_ISR_TXEIS_Msk (0x1UL) /*!< TXEIS (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_ISR_RXOIS_Pos (3UL) /*!< RXOIS (Bit 3) */ + #define R_SHOSTIF_ISR_RXOIS_Msk (0x8UL) /*!< RXOIS (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_ISR_RXFIS_Pos (4UL) /*!< RXFIS (Bit 4) */ + #define R_SHOSTIF_ISR_RXFIS_Msk (0x10UL) /*!< RXFIS (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_ISR_TXUIS_Pos (7UL) /*!< TXUIS (Bit 7) */ + #define R_SHOSTIF_ISR_TXUIS_Msk (0x80UL) /*!< TXUIS (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_ISR_AHBES_Pos (8UL) /*!< AHBES (Bit 8) */ + #define R_SHOSTIF_ISR_AHBES_Msk (0x100UL) /*!< AHBES (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_ISR_SPIMES_Pos (9UL) /*!< SPIMES (Bit 9) */ + #define R_SHOSTIF_ISR_SPIMES_Msk (0x200UL) /*!< SPIMES (Bitfield-Mask: 0x01) */ +/* ========================================================= RISR ========================================================== */ + #define R_SHOSTIF_RISR_TXEIR_Pos (0UL) /*!< TXEIR (Bit 0) */ + #define R_SHOSTIF_RISR_TXEIR_Msk (0x1UL) /*!< TXEIR (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_RISR_RXOIR_Pos (3UL) /*!< RXOIR (Bit 3) */ + #define R_SHOSTIF_RISR_RXOIR_Msk (0x8UL) /*!< RXOIR (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_RISR_RXFIR_Pos (4UL) /*!< RXFIR (Bit 4) */ + #define R_SHOSTIF_RISR_RXFIR_Msk (0x10UL) /*!< RXFIR (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_RISR_TXUIR_Pos (7UL) /*!< TXUIR (Bit 7) */ + #define R_SHOSTIF_RISR_TXUIR_Msk (0x80UL) /*!< TXUIR (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_RISR_AHBER_Pos (8UL) /*!< AHBER (Bit 8) */ + #define R_SHOSTIF_RISR_AHBER_Msk (0x100UL) /*!< AHBER (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_RISR_SPIMER_Pos (9UL) /*!< SPIMER (Bit 9) */ + #define R_SHOSTIF_RISR_SPIMER_Msk (0x200UL) /*!< SPIMER (Bitfield-Mask: 0x01) */ +/* ======================================================== TXUICR ========================================================= */ + #define R_SHOSTIF_TXUICR_TXUICR_Pos (0UL) /*!< TXUICR (Bit 0) */ + #define R_SHOSTIF_TXUICR_TXUICR_Msk (0x1UL) /*!< TXUICR (Bitfield-Mask: 0x01) */ +/* ======================================================== RXOICR ========================================================= */ + #define R_SHOSTIF_RXOICR_RXOICR_Pos (0UL) /*!< RXOICR (Bit 0) */ + #define R_SHOSTIF_RXOICR_RXOICR_Msk (0x1UL) /*!< RXOICR (Bitfield-Mask: 0x01) */ +/* ======================================================== SPIMECR ======================================================== */ + #define R_SHOSTIF_SPIMECR_SPIMECR_Pos (0UL) /*!< SPIMECR (Bit 0) */ + #define R_SHOSTIF_SPIMECR_SPIMECR_Msk (0x1UL) /*!< SPIMECR (Bitfield-Mask: 0x01) */ +/* ======================================================== AHBECR ========================================================= */ + #define R_SHOSTIF_AHBECR_AHBECR_Pos (0UL) /*!< AHBECR (Bit 0) */ + #define R_SHOSTIF_AHBECR_AHBECR_Msk (0x1UL) /*!< AHBECR (Bitfield-Mask: 0x01) */ +/* ========================================================== ICR ========================================================== */ + #define R_SHOSTIF_ICR_ICR_Pos (0UL) /*!< ICR (Bit 0) */ + #define R_SHOSTIF_ICR_ICR_Msk (0x1UL) /*!< ICR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_PHOSTIF ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== HIFBCC ========================================================= */ + #define R_PHOSTIF_HIFBCC_RBUFON0_Pos (0UL) /*!< RBUFON0 (Bit 0) */ + #define R_PHOSTIF_HIFBCC_RBUFON0_Msk (0x1UL) /*!< RBUFON0 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFBCC_RBUFON1_Pos (1UL) /*!< RBUFON1 (Bit 1) */ + #define R_PHOSTIF_HIFBCC_RBUFON1_Msk (0x2UL) /*!< RBUFON1 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFBCC_RBUFON2_Pos (2UL) /*!< RBUFON2 (Bit 2) */ + #define R_PHOSTIF_HIFBCC_RBUFON2_Msk (0x4UL) /*!< RBUFON2 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFBCC_RBUFON3_Pos (3UL) /*!< RBUFON3 (Bit 3) */ + #define R_PHOSTIF_HIFBCC_RBUFON3_Msk (0x8UL) /*!< RBUFON3 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFBCC_RBUFON4_Pos (4UL) /*!< RBUFON4 (Bit 4) */ + #define R_PHOSTIF_HIFBCC_RBUFON4_Msk (0x10UL) /*!< RBUFON4 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFBCC_RBUFON5_Pos (5UL) /*!< RBUFON5 (Bit 5) */ + #define R_PHOSTIF_HIFBCC_RBUFON5_Msk (0x20UL) /*!< RBUFON5 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFBCC_RBUFONX_Pos (8UL) /*!< RBUFONX (Bit 8) */ + #define R_PHOSTIF_HIFBCC_RBUFONX_Msk (0x100UL) /*!< RBUFONX (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFBCC_BSTON_Pos (12UL) /*!< BSTON (Bit 12) */ + #define R_PHOSTIF_HIFBCC_BSTON_Msk (0x1000UL) /*!< BSTON (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFBCC_WRPON_Pos (13UL) /*!< WRPON (Bit 13) */ + #define R_PHOSTIF_HIFBCC_WRPON_Msk (0x2000UL) /*!< WRPON (Bitfield-Mask: 0x01) */ +/* ======================================================== HIFBTC ========================================================= */ + #define R_PHOSTIF_HIFBTC_WRSTD_Pos (0UL) /*!< WRSTD (Bit 0) */ + #define R_PHOSTIF_HIFBTC_WRSTD_Msk (0x7UL) /*!< WRSTD (Bitfield-Mask: 0x07) */ + #define R_PHOSTIF_HIFBTC_RDSTD_Pos (4UL) /*!< RDSTD (Bit 4) */ + #define R_PHOSTIF_HIFBTC_RDSTD_Msk (0x30UL) /*!< RDSTD (Bitfield-Mask: 0x03) */ + #define R_PHOSTIF_HIFBTC_PASTD_Pos (8UL) /*!< PASTD (Bit 8) */ + #define R_PHOSTIF_HIFBTC_PASTD_Msk (0x700UL) /*!< PASTD (Bitfield-Mask: 0x07) */ + #define R_PHOSTIF_HIFBTC_RDDTS_Pos (12UL) /*!< RDDTS (Bit 12) */ + #define R_PHOSTIF_HIFBTC_RDDTS_Msk (0x3000UL) /*!< RDDTS (Bitfield-Mask: 0x03) */ +/* ======================================================== HIFPRC ========================================================= */ + #define R_PHOSTIF_HIFPRC_PAGEON0_Pos (0UL) /*!< PAGEON0 (Bit 0) */ + #define R_PHOSTIF_HIFPRC_PAGEON0_Msk (0x1UL) /*!< PAGEON0 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFPRC_PAGEON1_Pos (1UL) /*!< PAGEON1 (Bit 1) */ + #define R_PHOSTIF_HIFPRC_PAGEON1_Msk (0x2UL) /*!< PAGEON1 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFPRC_PAGEON2_Pos (2UL) /*!< PAGEON2 (Bit 2) */ + #define R_PHOSTIF_HIFPRC_PAGEON2_Msk (0x4UL) /*!< PAGEON2 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFPRC_PAGEON3_Pos (3UL) /*!< PAGEON3 (Bit 3) */ + #define R_PHOSTIF_HIFPRC_PAGEON3_Msk (0x8UL) /*!< PAGEON3 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFPRC_PAGEON4_Pos (4UL) /*!< PAGEON4 (Bit 4) */ + #define R_PHOSTIF_HIFPRC_PAGEON4_Msk (0x10UL) /*!< PAGEON4 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFPRC_PAGEON5_Pos (5UL) /*!< PAGEON5 (Bit 5) */ + #define R_PHOSTIF_HIFPRC_PAGEON5_Msk (0x20UL) /*!< PAGEON5 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFPRC_PAGEONX_Pos (8UL) /*!< PAGEONX (Bit 8) */ + #define R_PHOSTIF_HIFPRC_PAGEONX_Msk (0x100UL) /*!< PAGEONX (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFPRC_PAGESZ_Pos (12UL) /*!< PAGESZ (Bit 12) */ + #define R_PHOSTIF_HIFPRC_PAGESZ_Msk (0x1000UL) /*!< PAGESZ (Bitfield-Mask: 0x01) */ +/* ======================================================== HIFIRC ========================================================= */ + #define R_PHOSTIF_HIFIRC_ERRRSP_Pos (0UL) /*!< ERRRSP (Bit 0) */ + #define R_PHOSTIF_HIFIRC_ERRRSP_Msk (0x1UL) /*!< ERRRSP (Bitfield-Mask: 0x01) */ +/* ======================================================== HIFECR0 ======================================================== */ + #define R_PHOSTIF_HIFECR0_ERRADDR_Pos (0UL) /*!< ERRADDR (Bit 0) */ + #define R_PHOSTIF_HIFECR0_ERRADDR_Msk (0xffffffffUL) /*!< ERRADDR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== HIFECR1 ======================================================== */ + #define R_PHOSTIF_HIFECR1_ERRSZ_Pos (0UL) /*!< ERRSZ (Bit 0) */ + #define R_PHOSTIF_HIFECR1_ERRSZ_Msk (0x7UL) /*!< ERRSZ (Bitfield-Mask: 0x07) */ + #define R_PHOSTIF_HIFECR1_ERRWR_Pos (3UL) /*!< ERRWR (Bit 3) */ + #define R_PHOSTIF_HIFECR1_ERRWR_Msk (0x8UL) /*!< ERRWR (Bitfield-Mask: 0x01) */ +/* ======================================================== HIFMON1 ======================================================== */ + #define R_PHOSTIF_HIFMON1_HIFRDY_Pos (0UL) /*!< HIFRDY (Bit 0) */ + #define R_PHOSTIF_HIFMON1_HIFRDY_Msk (0x1UL) /*!< HIFRDY (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFMON1_BUSSEL_Pos (1UL) /*!< BUSSEL (Bit 1) */ + #define R_PHOSTIF_HIFMON1_BUSSEL_Msk (0x2UL) /*!< BUSSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFMON1_HIFSYNC_Pos (3UL) /*!< HIFSYNC (Bit 3) */ + #define R_PHOSTIF_HIFMON1_HIFSYNC_Msk (0x8UL) /*!< HIFSYNC (Bitfield-Mask: 0x01) */ +/* ======================================================== HIFMON2 ======================================================== */ + #define R_PHOSTIF_HIFMON2_HIFBCC_Pos (0UL) /*!< HIFBCC (Bit 0) */ + #define R_PHOSTIF_HIFMON2_HIFBCC_Msk (0x1UL) /*!< HIFBCC (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFMON2_HIFBTC_Pos (1UL) /*!< HIFBTC (Bit 1) */ + #define R_PHOSTIF_HIFMON2_HIFBTC_Msk (0x2UL) /*!< HIFBTC (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFMON2_HIFPRC_Pos (2UL) /*!< HIFPRC (Bit 2) */ + #define R_PHOSTIF_HIFMON2_HIFPRC_Msk (0x4UL) /*!< HIFPRC (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFMON2_HIFIRC_Pos (3UL) /*!< HIFIRC (Bit 3) */ + #define R_PHOSTIF_HIFMON2_HIFIRC_Msk (0x8UL) /*!< HIFIRC (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFMON2_HIFXAL_Pos (4UL) /*!< HIFXAL (Bit 4) */ + #define R_PHOSTIF_HIFMON2_HIFXAL_Msk (0x10UL) /*!< HIFXAL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFMON2_HIFXAH_Pos (5UL) /*!< HIFXAH (Bit 5) */ + #define R_PHOSTIF_HIFMON2_HIFXAH_Msk (0x20UL) /*!< HIFXAH (Bitfield-Mask: 0x01) */ +/* ======================================================== HIFMON3 ======================================================== */ + #define R_PHOSTIF_HIFMON3_HIFEXT0_Pos (0UL) /*!< HIFEXT0 (Bit 0) */ + #define R_PHOSTIF_HIFMON3_HIFEXT0_Msk (0x1UL) /*!< HIFEXT0 (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFMON3_HIFEXT1_Pos (1UL) /*!< HIFEXT1 (Bit 1) */ + #define R_PHOSTIF_HIFMON3_HIFEXT1_Msk (0x2UL) /*!< HIFEXT1 (Bitfield-Mask: 0x01) */ +/* ======================================================== HIFXAL ========================================================= */ + #define R_PHOSTIF_HIFXAL_XADDRL_Pos (0UL) /*!< XADDRL (Bit 0) */ + #define R_PHOSTIF_HIFXAL_XADDRL_Msk (0x1ffUL) /*!< XADDRL (Bitfield-Mask: 0x1ff) */ +/* ======================================================== HIFXAH ========================================================= */ + #define R_PHOSTIF_HIFXAH_XADDRH_Pos (0UL) /*!< XADDRH (Bit 0) */ + #define R_PHOSTIF_HIFXAH_XADDRH_Msk (0x1ffUL) /*!< XADDRH (Bitfield-Mask: 0x1ff) */ +/* ======================================================== HIFEXT0 ======================================================== */ + #define R_PHOSTIF_HIFEXT0_KESSBI_Pos (0UL) /*!< KESSBI (Bit 0) */ + #define R_PHOSTIF_HIFEXT0_KESSBI_Msk (0x1UL) /*!< KESSBI (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFEXT0_KESDTI_Pos (2UL) /*!< KESDTI (Bit 2) */ + #define R_PHOSTIF_HIFEXT0_KESDTI_Msk (0x4UL) /*!< KESDTI (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFEXT0_KESAVI_Pos (3UL) /*!< KESAVI (Bit 3) */ + #define R_PHOSTIF_HIFEXT0_KESAVI_Msk (0x8UL) /*!< KESAVI (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFEXT0_KESDTO_Pos (4UL) /*!< KESDTO (Bit 4) */ + #define R_PHOSTIF_HIFEXT0_KESDTO_Msk (0x10UL) /*!< KESDTO (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFEXT0_KESWTO_Pos (5UL) /*!< KESWTO (Bit 5) */ + #define R_PHOSTIF_HIFEXT0_KESWTO_Msk (0x20UL) /*!< KESWTO (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFEXT0_CNDWEO_Pos (9UL) /*!< CNDWEO (Bit 9) */ + #define R_PHOSTIF_HIFEXT0_CNDWEO_Msk (0x200UL) /*!< CNDWEO (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_HIFEXT0_MODTRN_Pos (15UL) /*!< MODTRN (Bit 15) */ + #define R_PHOSTIF_HIFEXT0_MODTRN_Msk (0x8000UL) /*!< MODTRN (Bitfield-Mask: 0x01) */ +/* ======================================================== HIFEXT1 ======================================================== */ + #define R_PHOSTIF_HIFEXT1_DLYWA_Pos (0UL) /*!< DLYWA (Bit 0) */ + #define R_PHOSTIF_HIFEXT1_DLYWA_Msk (0xfUL) /*!< DLYWA (Bitfield-Mask: 0x0f) */ + #define R_PHOSTIF_HIFEXT1_DLYRA_Pos (8UL) /*!< DLYRA (Bit 8) */ + #define R_PHOSTIF_HIFEXT1_DLYRA_Msk (0xf00UL) /*!< DLYRA (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_NS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SCKCR ========================================================= */ + #define R_SYSC_NS_SCKCR_FSELXSPI0_Pos (0UL) /*!< FSELXSPI0 (Bit 0) */ + #define R_SYSC_NS_SCKCR_FSELXSPI0_Msk (0x7UL) /*!< FSELXSPI0 (Bitfield-Mask: 0x07) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Pos (6UL) /*!< DIVSELXSPI0 (Bit 6) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI0_Msk (0x40UL) /*!< DIVSELXSPI0 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_FSELXSPI1_Pos (8UL) /*!< FSELXSPI1 (Bit 8) */ + #define R_SYSC_NS_SCKCR_FSELXSPI1_Msk (0x700UL) /*!< FSELXSPI1 (Bitfield-Mask: 0x07) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Pos (14UL) /*!< DIVSELXSPI1 (Bit 14) */ + #define R_SYSC_NS_SCKCR_DIVSELXSPI1_Msk (0x4000UL) /*!< DIVSELXSPI1 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_CKIO_Pos (16UL) /*!< CKIO (Bit 16) */ + #define R_SYSC_NS_SCKCR_CKIO_Msk (0x70000UL) /*!< CKIO (Bitfield-Mask: 0x07) */ + #define R_SYSC_NS_SCKCR_FSELCANFD_Pos (20UL) /*!< FSELCANFD (Bit 20) */ + #define R_SYSC_NS_SCKCR_FSELCANFD_Msk (0x100000UL) /*!< FSELCANFD (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_PHYSEL_Pos (21UL) /*!< PHYSEL (Bit 21) */ + #define R_SYSC_NS_SCKCR_PHYSEL_Msk (0x200000UL) /*!< PHYSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_CLMASEL_Pos (22UL) /*!< CLMASEL (Bit 22) */ + #define R_SYSC_NS_SCKCR_CLMASEL_Msk (0x400000UL) /*!< CLMASEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SPI0ASYNCSEL_Pos (24UL) /*!< SPI0ASYNCSEL (Bit 24) */ + #define R_SYSC_NS_SCKCR_SPI0ASYNCSEL_Msk (0x1000000UL) /*!< SPI0ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SPI1ASYNCSEL_Pos (25UL) /*!< SPI1ASYNCSEL (Bit 25) */ + #define R_SYSC_NS_SCKCR_SPI1ASYNCSEL_Msk (0x2000000UL) /*!< SPI1ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SPI2ASYNCSEL_Pos (26UL) /*!< SPI2ASYNCSEL (Bit 26) */ + #define R_SYSC_NS_SCKCR_SPI2ASYNCSEL_Msk (0x4000000UL) /*!< SPI2ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI0ASYNCSEL_Pos (27UL) /*!< SCI0ASYNCSEL (Bit 27) */ + #define R_SYSC_NS_SCKCR_SCI0ASYNCSEL_Msk (0x8000000UL) /*!< SCI0ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI1ASYNCSEL_Pos (28UL) /*!< SCI1ASYNCSEL (Bit 28) */ + #define R_SYSC_NS_SCKCR_SCI1ASYNCSEL_Msk (0x10000000UL) /*!< SCI1ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI2ASYNCSEL_Pos (29UL) /*!< SCI2ASYNCSEL (Bit 29) */ + #define R_SYSC_NS_SCKCR_SCI2ASYNCSEL_Msk (0x20000000UL) /*!< SCI2ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI3ASYNCSEL_Pos (30UL) /*!< SCI3ASYNCSEL (Bit 30) */ + #define R_SYSC_NS_SCKCR_SCI3ASYNCSEL_Msk (0x40000000UL) /*!< SCI3ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_SCKCR_SCI4ASYNCSEL_Pos (31UL) /*!< SCI4ASYNCSEL (Bit 31) */ + #define R_SYSC_NS_SCKCR_SCI4ASYNCSEL_Msk (0x80000000UL) /*!< SCI4ASYNCSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== RSTSR0 ========================================================= */ + #define R_SYSC_NS_RSTSR0_TRF_Pos (1UL) /*!< TRF (Bit 1) */ + #define R_SYSC_NS_RSTSR0_TRF_Msk (0x2UL) /*!< TRF (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_RSTSR0_ERRF_Pos (2UL) /*!< ERRF (Bit 2) */ + #define R_SYSC_NS_RSTSR0_ERRF_Msk (0x4UL) /*!< ERRF (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_RSTSR0_SWRSF_Pos (3UL) /*!< SWRSF (Bit 3) */ + #define R_SYSC_NS_RSTSR0_SWRSF_Msk (0x8UL) /*!< SWRSF (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_RSTSR0_SWR0F_Pos (4UL) /*!< SWR0F (Bit 4) */ + #define R_SYSC_NS_RSTSR0_SWR0F_Msk (0x10UL) /*!< SWR0F (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCTLA ========================================================= */ + #define R_SYSC_NS_MRCTLA_MRCTLA04_Pos (4UL) /*!< MRCTLA04 (Bit 4) */ + #define R_SYSC_NS_MRCTLA_MRCTLA04_Msk (0x10UL) /*!< MRCTLA04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLA_MRCTLA05_Pos (5UL) /*!< MRCTLA05 (Bit 5) */ + #define R_SYSC_NS_MRCTLA_MRCTLA05_Msk (0x20UL) /*!< MRCTLA05 (Bitfield-Mask: 0x01) */ +/* ======================================================== MRCTLE ========================================================= */ + #define R_SYSC_NS_MRCTLE_MRCTLE00_Pos (0UL) /*!< MRCTLE00 (Bit 0) */ + #define R_SYSC_NS_MRCTLE_MRCTLE00_Msk (0x1UL) /*!< MRCTLE00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE01_Pos (1UL) /*!< MRCTLE01 (Bit 1) */ + #define R_SYSC_NS_MRCTLE_MRCTLE01_Msk (0x2UL) /*!< MRCTLE01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE02_Pos (2UL) /*!< MRCTLE02 (Bit 2) */ + #define R_SYSC_NS_MRCTLE_MRCTLE02_Msk (0x4UL) /*!< MRCTLE02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE03_Pos (3UL) /*!< MRCTLE03 (Bit 3) */ + #define R_SYSC_NS_MRCTLE_MRCTLE03_Msk (0x8UL) /*!< MRCTLE03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE04_Pos (4UL) /*!< MRCTLE04 (Bit 4) */ + #define R_SYSC_NS_MRCTLE_MRCTLE04_Msk (0x10UL) /*!< MRCTLE04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE05_Pos (5UL) /*!< MRCTLE05 (Bit 5) */ + #define R_SYSC_NS_MRCTLE_MRCTLE05_Msk (0x20UL) /*!< MRCTLE05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MRCTLE_MRCTLE06_Pos (6UL) /*!< MRCTLE06 (Bit 6) */ + #define R_SYSC_NS_MRCTLE_MRCTLE06_Msk (0x40UL) /*!< MRCTLE06 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRA ======================================================== */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Pos (0UL) /*!< MSTPCRA00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA00_Msk (0x1UL) /*!< MSTPCRA00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Pos (4UL) /*!< MSTPCRA04 (Bit 4) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA04_Msk (0x10UL) /*!< MSTPCRA04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Pos (5UL) /*!< MSTPCRA05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA05_Msk (0x20UL) /*!< MSTPCRA05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Pos (8UL) /*!< MSTPCRA08 (Bit 8) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA08_Msk (0x100UL) /*!< MSTPCRA08 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Pos (9UL) /*!< MSTPCRA09 (Bit 9) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA09_Msk (0x200UL) /*!< MSTPCRA09 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Pos (10UL) /*!< MSTPCRA10 (Bit 10) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA10_Msk (0x400UL) /*!< MSTPCRA10 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Pos (11UL) /*!< MSTPCRA11 (Bit 11) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA11_Msk (0x800UL) /*!< MSTPCRA11 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Pos (12UL) /*!< MSTPCRA12 (Bit 12) */ + #define R_SYSC_NS_MSTPCRA_MSTPCRA12_Msk (0x1000UL) /*!< MSTPCRA12 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRB ======================================================== */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Pos (0UL) /*!< MSTPCRB00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB00_Msk (0x1UL) /*!< MSTPCRB00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Pos (1UL) /*!< MSTPCRB01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB01_Msk (0x2UL) /*!< MSTPCRB01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Pos (4UL) /*!< MSTPCRB04 (Bit 4) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB04_Msk (0x10UL) /*!< MSTPCRB04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Pos (5UL) /*!< MSTPCRB05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB05_Msk (0x20UL) /*!< MSTPCRB05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Pos (6UL) /*!< MSTPCRB06 (Bit 6) */ + #define R_SYSC_NS_MSTPCRB_MSTPCRB06_Msk (0x40UL) /*!< MSTPCRB06 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRC ======================================================== */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Pos (0UL) /*!< MSTPCRC00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC00_Msk (0x1UL) /*!< MSTPCRC00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Pos (1UL) /*!< MSTPCRC01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC01_Msk (0x2UL) /*!< MSTPCRC01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Pos (2UL) /*!< MSTPCRC02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC02_Msk (0x4UL) /*!< MSTPCRC02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Pos (5UL) /*!< MSTPCRC05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC05_Msk (0x20UL) /*!< MSTPCRC05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Pos (6UL) /*!< MSTPCRC06 (Bit 6) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC06_Msk (0x40UL) /*!< MSTPCRC06 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Pos (7UL) /*!< MSTPCRC07 (Bit 7) */ + #define R_SYSC_NS_MSTPCRC_MSTPCRC07_Msk (0x80UL) /*!< MSTPCRC07 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRD ======================================================== */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Pos (0UL) /*!< MSTPCRD00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD00_Msk (0x1UL) /*!< MSTPCRD00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Pos (1UL) /*!< MSTPCRD01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD01_Msk (0x2UL) /*!< MSTPCRD01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Pos (2UL) /*!< MSTPCRD02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD02_Msk (0x4UL) /*!< MSTPCRD02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Pos (3UL) /*!< MSTPCRD03 (Bit 3) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD03_Msk (0x8UL) /*!< MSTPCRD03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Pos (4UL) /*!< MSTPCRD04 (Bit 4) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD04_Msk (0x10UL) /*!< MSTPCRD04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Pos (5UL) /*!< MSTPCRD05 (Bit 5) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD05_Msk (0x20UL) /*!< MSTPCRD05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Pos (6UL) /*!< MSTPCRD06 (Bit 6) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD06_Msk (0x40UL) /*!< MSTPCRD06 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Pos (7UL) /*!< MSTPCRD07 (Bit 7) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD07_Msk (0x80UL) /*!< MSTPCRD07 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Pos (8UL) /*!< MSTPCRD08 (Bit 8) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD08_Msk (0x100UL) /*!< MSTPCRD08 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Pos (9UL) /*!< MSTPCRD09 (Bit 9) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD09_Msk (0x200UL) /*!< MSTPCRD09 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Pos (10UL) /*!< MSTPCRD10 (Bit 10) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD10_Msk (0x400UL) /*!< MSTPCRD10 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Pos (11UL) /*!< MSTPCRD11 (Bit 11) */ + #define R_SYSC_NS_MSTPCRD_MSTPCRD11_Msk (0x800UL) /*!< MSTPCRD11 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRE ======================================================== */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Pos (0UL) /*!< MSTPCRE00 (Bit 0) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE00_Msk (0x1UL) /*!< MSTPCRE00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE01_Pos (1UL) /*!< MSTPCRE01 (Bit 1) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE01_Msk (0x2UL) /*!< MSTPCRE01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Pos (2UL) /*!< MSTPCRE02 (Bit 2) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE02_Msk (0x4UL) /*!< MSTPCRE02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Pos (3UL) /*!< MSTPCRE03 (Bit 3) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE03_Msk (0x8UL) /*!< MSTPCRE03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Pos (8UL) /*!< MSTPCRE08 (Bit 8) */ + #define R_SYSC_NS_MSTPCRE_MSTPCRE08_Msk (0x100UL) /*!< MSTPCRE08 (Bitfield-Mask: 0x01) */ +/* ======================================================== MD_MON ========================================================= */ + #define R_SYSC_NS_MD_MON_MDDMON_Pos (0UL) /*!< MDDMON (Bit 0) */ + #define R_SYSC_NS_MD_MON_MDDMON_Msk (0x1UL) /*!< MDDMON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDP_Pos (8UL) /*!< MDP (Bit 8) */ + #define R_SYSC_NS_MD_MON_MDP_Msk (0x100UL) /*!< MDP (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MD0MON_Pos (12UL) /*!< MD0MON (Bit 12) */ + #define R_SYSC_NS_MD_MON_MD0MON_Msk (0x1000UL) /*!< MD0MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MD1MON_Pos (13UL) /*!< MD1MON (Bit 13) */ + #define R_SYSC_NS_MD_MON_MD1MON_Msk (0x2000UL) /*!< MD1MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MD2MON_Pos (14UL) /*!< MD2MON (Bit 14) */ + #define R_SYSC_NS_MD_MON_MD2MON_Msk (0x4000UL) /*!< MD2MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV0MON_Pos (16UL) /*!< MDV0MON (Bit 16) */ + #define R_SYSC_NS_MD_MON_MDV0MON_Msk (0x10000UL) /*!< MDV0MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV1MON_Pos (17UL) /*!< MDV1MON (Bit 17) */ + #define R_SYSC_NS_MD_MON_MDV1MON_Msk (0x20000UL) /*!< MDV1MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV2MON_Pos (18UL) /*!< MDV2MON (Bit 18) */ + #define R_SYSC_NS_MD_MON_MDV2MON_Msk (0x40000UL) /*!< MDV2MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV3MON_Pos (19UL) /*!< MDV3MON (Bit 19) */ + #define R_SYSC_NS_MD_MON_MDV3MON_Msk (0x80000UL) /*!< MDV3MON (Bitfield-Mask: 0x01) */ + #define R_SYSC_NS_MD_MON_MDV4MON_Pos (20UL) /*!< MDV4MON (Bit 20) */ + #define R_SYSC_NS_MD_MON_MDV4MON_Msk (0x100000UL) /*!< MDV4MON (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_ELO ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ELOPA ========================================================= */ + #define R_ELO_ELOPA_MTU0MD_Pos (0UL) /*!< MTU0MD (Bit 0) */ + #define R_ELO_ELOPA_MTU0MD_Msk (0x3UL) /*!< MTU0MD (Bitfield-Mask: 0x03) */ + #define R_ELO_ELOPA_MTU3MD_Pos (6UL) /*!< MTU3MD (Bit 6) */ + #define R_ELO_ELOPA_MTU3MD_Msk (0xc0UL) /*!< MTU3MD (Bitfield-Mask: 0x03) */ +/* ========================================================= ELOPB ========================================================= */ + #define R_ELO_ELOPB_MTU4MD_Pos (0UL) /*!< MTU4MD (Bit 0) */ + #define R_ELO_ELOPB_MTU4MD_Msk (0x3UL) /*!< MTU4MD (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_NS ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRCRN ========================================================= */ + #define R_RWP_NS_PRCRN_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_RWP_NS_PRCRN_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_RWP_NS_PRCRN_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_RWP_NS_PRCRN_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_RWP_NS_PRCRN_PRC2_Pos (2UL) /*!< PRC2 (Bit 2) */ + #define R_RWP_NS_PRCRN_PRC2_Msk (0x4UL) /*!< PRC2 (Bitfield-Mask: 0x01) */ + #define R_RWP_NS_PRCRN_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_RWP_NS_PRCRN_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_RTC ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= RTCA0CTL0 ======================================================= */ + #define R_RTC_RTCA0CTL0_RTCA0SLSB_Pos (4UL) /*!< RTCA0SLSB (Bit 4) */ + #define R_RTC_RTCA0CTL0_RTCA0SLSB_Msk (0x10UL) /*!< RTCA0SLSB (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL0_RTCA0AMPM_Pos (5UL) /*!< RTCA0AMPM (Bit 5) */ + #define R_RTC_RTCA0CTL0_RTCA0AMPM_Msk (0x20UL) /*!< RTCA0AMPM (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL0_RTCA0CEST_Pos (6UL) /*!< RTCA0CEST (Bit 6) */ + #define R_RTC_RTCA0CTL0_RTCA0CEST_Msk (0x40UL) /*!< RTCA0CEST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL0_RTCA0CE_Pos (7UL) /*!< RTCA0CE (Bit 7) */ + #define R_RTC_RTCA0CTL0_RTCA0CE_Msk (0x80UL) /*!< RTCA0CE (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0CTL1 ======================================================= */ + #define R_RTC_RTCA0CTL1_RTCA0CT_Pos (0UL) /*!< RTCA0CT (Bit 0) */ + #define R_RTC_RTCA0CTL1_RTCA0CT_Msk (0x7UL) /*!< RTCA0CT (Bitfield-Mask: 0x07) */ + #define R_RTC_RTCA0CTL1_RTCA01SE_Pos (3UL) /*!< RTCA01SE (Bit 3) */ + #define R_RTC_RTCA0CTL1_RTCA01SE_Msk (0x8UL) /*!< RTCA01SE (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL1_RTCA0ALME_Pos (4UL) /*!< RTCA0ALME (Bit 4) */ + #define R_RTC_RTCA0CTL1_RTCA0ALME_Msk (0x10UL) /*!< RTCA0ALME (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL1_RTCA01HZE_Pos (5UL) /*!< RTCA01HZE (Bit 5) */ + #define R_RTC_RTCA0CTL1_RTCA01HZE_Msk (0x20UL) /*!< RTCA01HZE (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0CTL2 ======================================================= */ + #define R_RTC_RTCA0CTL2_RTCA0WAIT_Pos (0UL) /*!< RTCA0WAIT (Bit 0) */ + #define R_RTC_RTCA0CTL2_RTCA0WAIT_Msk (0x1UL) /*!< RTCA0WAIT (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0WST_Pos (1UL) /*!< RTCA0WST (Bit 1) */ + #define R_RTC_RTCA0CTL2_RTCA0WST_Msk (0x2UL) /*!< RTCA0WST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0RSUB_Pos (2UL) /*!< RTCA0RSUB (Bit 2) */ + #define R_RTC_RTCA0CTL2_RTCA0RSUB_Msk (0x4UL) /*!< RTCA0RSUB (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0RSST_Pos (3UL) /*!< RTCA0RSST (Bit 3) */ + #define R_RTC_RTCA0CTL2_RTCA0RSST_Msk (0x8UL) /*!< RTCA0RSST (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0CTL2_RTCA0WSST_Pos (4UL) /*!< RTCA0WSST (Bit 4) */ + #define R_RTC_RTCA0CTL2_RTCA0WSST_Msk (0x10UL) /*!< RTCA0WSST (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0SUBC ======================================================= */ + #define R_RTC_RTCA0SUBC_RTCA0SUBC_Pos (0UL) /*!< RTCA0SUBC (Bit 0) */ + #define R_RTC_RTCA0SUBC_RTCA0SUBC_Msk (0x3fffffUL) /*!< RTCA0SUBC (Bitfield-Mask: 0x3fffff) */ +/* ======================================================= RTCA0SRBU ======================================================= */ + #define R_RTC_RTCA0SRBU_RTCA0SRBU_Pos (0UL) /*!< RTCA0SRBU (Bit 0) */ + #define R_RTC_RTCA0SRBU_RTCA0SRBU_Msk (0x3fffffUL) /*!< RTCA0SRBU (Bitfield-Mask: 0x3fffff) */ +/* ======================================================= RTCA0SEC ======================================================== */ + #define R_RTC_RTCA0SEC_RTCA0SEC_Pos (0UL) /*!< RTCA0SEC (Bit 0) */ + #define R_RTC_RTCA0SEC_RTCA0SEC_Msk (0x7fUL) /*!< RTCA0SEC (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0MIN ======================================================== */ + #define R_RTC_RTCA0MIN_RTCA0MIN_Pos (0UL) /*!< RTCA0MIN (Bit 0) */ + #define R_RTC_RTCA0MIN_RTCA0MIN_Msk (0x7fUL) /*!< RTCA0MIN (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0HOUR ======================================================= */ + #define R_RTC_RTCA0HOUR_RTCA0HOUR_Pos (0UL) /*!< RTCA0HOUR (Bit 0) */ + #define R_RTC_RTCA0HOUR_RTCA0HOUR_Msk (0x3fUL) /*!< RTCA0HOUR (Bitfield-Mask: 0x3f) */ +/* ======================================================= RTCA0WEEK ======================================================= */ + #define R_RTC_RTCA0WEEK_RTCA0WEEK_Pos (0UL) /*!< RTCA0WEEK (Bit 0) */ + #define R_RTC_RTCA0WEEK_RTCA0WEEK_Msk (0x7UL) /*!< RTCA0WEEK (Bitfield-Mask: 0x07) */ +/* ======================================================= RTCA0DAY ======================================================== */ + #define R_RTC_RTCA0DAY_RTCA0DAY_Pos (0UL) /*!< RTCA0DAY (Bit 0) */ + #define R_RTC_RTCA0DAY_RTCA0DAY_Msk (0x3fUL) /*!< RTCA0DAY (Bitfield-Mask: 0x3f) */ +/* ====================================================== RTCA0MONTH ======================================================= */ + #define R_RTC_RTCA0MONTH_RTCA0MONTH_Pos (0UL) /*!< RTCA0MONTH (Bit 0) */ + #define R_RTC_RTCA0MONTH_RTCA0MONTH_Msk (0x1fUL) /*!< RTCA0MONTH (Bitfield-Mask: 0x1f) */ +/* ======================================================= RTCA0YEAR ======================================================= */ + #define R_RTC_RTCA0YEAR_RTCA0YEAR_Pos (0UL) /*!< RTCA0YEAR (Bit 0) */ + #define R_RTC_RTCA0YEAR_RTCA0YEAR_Msk (0xffUL) /*!< RTCA0YEAR (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0TIME ======================================================= */ + #define R_RTC_RTCA0TIME_RTCA0SEC_Pos (0UL) /*!< RTCA0SEC (Bit 0) */ + #define R_RTC_RTCA0TIME_RTCA0SEC_Msk (0xffUL) /*!< RTCA0SEC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIME_RTCA0MIN_Pos (8UL) /*!< RTCA0MIN (Bit 8) */ + #define R_RTC_RTCA0TIME_RTCA0MIN_Msk (0xff00UL) /*!< RTCA0MIN (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIME_RTCA0HOUR_Pos (16UL) /*!< RTCA0HOUR (Bit 16) */ + #define R_RTC_RTCA0TIME_RTCA0HOUR_Msk (0xff0000UL) /*!< RTCA0HOUR (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0CAL ======================================================== */ + #define R_RTC_RTCA0CAL_RTCA0WEEK_Pos (0UL) /*!< RTCA0WEEK (Bit 0) */ + #define R_RTC_RTCA0CAL_RTCA0WEEK_Msk (0xffUL) /*!< RTCA0WEEK (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CAL_RTCA0DAY_Pos (8UL) /*!< RTCA0DAY (Bit 8) */ + #define R_RTC_RTCA0CAL_RTCA0DAY_Msk (0xff00UL) /*!< RTCA0DAY (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CAL_RTCA0MONTH_Pos (16UL) /*!< RTCA0MONTH (Bit 16) */ + #define R_RTC_RTCA0CAL_RTCA0MONTH_Msk (0xff0000UL) /*!< RTCA0MONTH (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CAL_RTCA0YEAR_Pos (24UL) /*!< RTCA0YEAR (Bit 24) */ + #define R_RTC_RTCA0CAL_RTCA0YEAR_Msk (0xff000000UL) /*!< RTCA0YEAR (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0SCMP ======================================================= */ + #define R_RTC_RTCA0SCMP_RTCA0SCMP_Pos (0UL) /*!< RTCA0SCMP (Bit 0) */ + #define R_RTC_RTCA0SCMP_RTCA0SCMP_Msk (0x3fffffUL) /*!< RTCA0SCMP (Bitfield-Mask: 0x3fffff) */ +/* ======================================================= RTCA0ALM ======================================================== */ + #define R_RTC_RTCA0ALM_RTCA0ALM_Pos (0UL) /*!< RTCA0ALM (Bit 0) */ + #define R_RTC_RTCA0ALM_RTCA0ALM_Msk (0x7fUL) /*!< RTCA0ALM (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0ALH ======================================================== */ + #define R_RTC_RTCA0ALH_RTCA0ALH_Pos (0UL) /*!< RTCA0ALH (Bit 0) */ + #define R_RTC_RTCA0ALH_RTCA0ALH_Msk (0x3fUL) /*!< RTCA0ALH (Bitfield-Mask: 0x3f) */ +/* ======================================================= RTCA0ALW ======================================================== */ + #define R_RTC_RTCA0ALW_RTCA0ALW0_Pos (0UL) /*!< RTCA0ALW0 (Bit 0) */ + #define R_RTC_RTCA0ALW_RTCA0ALW0_Msk (0x1UL) /*!< RTCA0ALW0 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW1_Pos (1UL) /*!< RTCA0ALW1 (Bit 1) */ + #define R_RTC_RTCA0ALW_RTCA0ALW1_Msk (0x2UL) /*!< RTCA0ALW1 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW2_Pos (2UL) /*!< RTCA0ALW2 (Bit 2) */ + #define R_RTC_RTCA0ALW_RTCA0ALW2_Msk (0x4UL) /*!< RTCA0ALW2 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW3_Pos (3UL) /*!< RTCA0ALW3 (Bit 3) */ + #define R_RTC_RTCA0ALW_RTCA0ALW3_Msk (0x8UL) /*!< RTCA0ALW3 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW4_Pos (4UL) /*!< RTCA0ALW4 (Bit 4) */ + #define R_RTC_RTCA0ALW_RTCA0ALW4_Msk (0x10UL) /*!< RTCA0ALW4 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW5_Pos (5UL) /*!< RTCA0ALW5 (Bit 5) */ + #define R_RTC_RTCA0ALW_RTCA0ALW5_Msk (0x20UL) /*!< RTCA0ALW5 (Bitfield-Mask: 0x01) */ + #define R_RTC_RTCA0ALW_RTCA0ALW6_Pos (6UL) /*!< RTCA0ALW6 (Bit 6) */ + #define R_RTC_RTCA0ALW_RTCA0ALW6_Msk (0x40UL) /*!< RTCA0ALW6 (Bitfield-Mask: 0x01) */ +/* ======================================================= RTCA0SECC ======================================================= */ + #define R_RTC_RTCA0SECC_RTCA0SECC_Pos (0UL) /*!< RTCA0SECC (Bit 0) */ + #define R_RTC_RTCA0SECC_RTCA0SECC_Msk (0x7fUL) /*!< RTCA0SECC (Bitfield-Mask: 0x7f) */ +/* ======================================================= RTCA0MINC ======================================================= */ + #define R_RTC_RTCA0MINC_RTCA0MINC_Pos (0UL) /*!< RTCA0MINC (Bit 0) */ + #define R_RTC_RTCA0MINC_RTCA0MINC_Msk (0x7fUL) /*!< RTCA0MINC (Bitfield-Mask: 0x7f) */ +/* ====================================================== RTCA0HOURC ======================================================= */ + #define R_RTC_RTCA0HOURC_RTCA0HOURC_Pos (0UL) /*!< RTCA0HOURC (Bit 0) */ + #define R_RTC_RTCA0HOURC_RTCA0HOURC_Msk (0x3fUL) /*!< RTCA0HOURC (Bitfield-Mask: 0x3f) */ +/* ====================================================== RTCA0WEEKC ======================================================= */ + #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Pos (0UL) /*!< RTCA0WEEKC (Bit 0) */ + #define R_RTC_RTCA0WEEKC_RTCA0WEEKC_Msk (0x7UL) /*!< RTCA0WEEKC (Bitfield-Mask: 0x07) */ +/* ======================================================= RTCA0DAYC ======================================================= */ + #define R_RTC_RTCA0DAYC_RTCA0DAYC_Pos (0UL) /*!< RTCA0DAYC (Bit 0) */ + #define R_RTC_RTCA0DAYC_RTCA0DAYC_Msk (0x3fUL) /*!< RTCA0DAYC (Bitfield-Mask: 0x3f) */ +/* ======================================================= RTCA0MONC ======================================================= */ + #define R_RTC_RTCA0MONC_RTCA0MONC_Pos (0UL) /*!< RTCA0MONC (Bit 0) */ + #define R_RTC_RTCA0MONC_RTCA0MONC_Msk (0x1fUL) /*!< RTCA0MONC (Bitfield-Mask: 0x1f) */ +/* ====================================================== RTCA0YEARC ======================================================= */ + #define R_RTC_RTCA0YEARC_RTCA0YEARC_Pos (0UL) /*!< RTCA0YEARC (Bit 0) */ + #define R_RTC_RTCA0YEARC_RTCA0YEARC_Msk (0xffUL) /*!< RTCA0YEARC (Bitfield-Mask: 0xff) */ +/* ====================================================== RTCA0TIMEC ======================================================= */ + #define R_RTC_RTCA0TIMEC_RTCA0SECC_Pos (0UL) /*!< RTCA0SECC (Bit 0) */ + #define R_RTC_RTCA0TIMEC_RTCA0SECC_Msk (0xffUL) /*!< RTCA0SECC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIMEC_RTCA0MINC_Pos (8UL) /*!< RTCA0MINC (Bit 8) */ + #define R_RTC_RTCA0TIMEC_RTCA0MINC_Msk (0xff00UL) /*!< RTCA0MINC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Pos (16UL) /*!< RTCA0HOURC (Bit 16) */ + #define R_RTC_RTCA0TIMEC_RTCA0HOURC_Msk (0xff0000UL) /*!< RTCA0HOURC (Bitfield-Mask: 0xff) */ +/* ======================================================= RTCA0CALC ======================================================= */ + #define R_RTC_RTCA0CALC_RTCA0WEEKC_Pos (0UL) /*!< RTCA0WEEKC (Bit 0) */ + #define R_RTC_RTCA0CALC_RTCA0WEEKC_Msk (0xffUL) /*!< RTCA0WEEKC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CALC_RTCA0DAYC_Pos (8UL) /*!< RTCA0DAYC (Bit 8) */ + #define R_RTC_RTCA0CALC_RTCA0DAYC_Msk (0xff00UL) /*!< RTCA0DAYC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CALC_RTCA0MONC_Pos (16UL) /*!< RTCA0MONC (Bit 16) */ + #define R_RTC_RTCA0CALC_RTCA0MONC_Msk (0xff0000UL) /*!< RTCA0MONC (Bitfield-Mask: 0xff) */ + #define R_RTC_RTCA0CALC_RTCA0YEARC_Pos (24UL) /*!< RTCA0YEARC (Bit 24) */ + #define R_RTC_RTCA0CALC_RTCA0YEARC_Msk (0xff000000UL) /*!< RTCA0YEARC (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG2 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== POEG2GA ======================================================== */ + #define R_POEG2_POEG2GA_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GA_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GA_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GA_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GA_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GA_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GA_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GA_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GA_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GA_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GA_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GA_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GA_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG2GB ======================================================== */ + #define R_POEG2_POEG2GB_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GB_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GB_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GB_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GB_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GB_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GB_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GB_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GB_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GB_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GB_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GB_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GB_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG2GC ======================================================== */ + #define R_POEG2_POEG2GC_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GC_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GC_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GC_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GC_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GC_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GC_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GC_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GC_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GC_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GC_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GC_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GC_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG2GD ======================================================== */ + #define R_POEG2_POEG2GD_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG2_POEG2GD_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG2_POEG2GD_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG2_POEG2GD_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG2_POEG2GD_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG2_POEG2GD_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG2_POEG2GD_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG2_POEG2GD_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG2_POEG2GD_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG2_POEG2GD_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG2_POEG2GD_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG2_POEG2GD_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG2_POEG2GD_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_OTP ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== OTPPWR ========================================================= */ + #define R_OTP_OTPPWR_PWR_Pos (0UL) /*!< PWR (Bit 0) */ + #define R_OTP_OTPPWR_PWR_Msk (0x1UL) /*!< PWR (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPPWR_ACCL_Pos (4UL) /*!< ACCL (Bit 4) */ + #define R_OTP_OTPPWR_ACCL_Msk (0x10UL) /*!< ACCL (Bitfield-Mask: 0x01) */ +/* ======================================================== OTPSTR ========================================================= */ + #define R_OTP_OTPSTR_CMD_RDY_Pos (0UL) /*!< CMD_RDY (Bit 0) */ + #define R_OTP_OTPSTR_CMD_RDY_Msk (0x1UL) /*!< CMD_RDY (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_WR_Pos (1UL) /*!< ERR_WR (Bit 1) */ + #define R_OTP_OTPSTR_ERR_WR_Msk (0x6UL) /*!< ERR_WR (Bitfield-Mask: 0x03) */ + #define R_OTP_OTPSTR_ERR_WP_Pos (3UL) /*!< ERR_WP (Bit 3) */ + #define R_OTP_OTPSTR_ERR_WP_Msk (0x8UL) /*!< ERR_WP (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_RP_Pos (4UL) /*!< ERR_RP (Bit 4) */ + #define R_OTP_OTPSTR_ERR_RP_Msk (0x10UL) /*!< ERR_RP (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_RDY_WR_Pos (8UL) /*!< ERR_RDY_WR (Bit 8) */ + #define R_OTP_OTPSTR_ERR_RDY_WR_Msk (0x100UL) /*!< ERR_RDY_WR (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_ERR_RDY_RD_Pos (9UL) /*!< ERR_RDY_RD (Bit 9) */ + #define R_OTP_OTPSTR_ERR_RDY_RD_Msk (0x200UL) /*!< ERR_RDY_RD (Bitfield-Mask: 0x01) */ + #define R_OTP_OTPSTR_CNT_ST_IDLE_Pos (15UL) /*!< CNT_ST_IDLE (Bit 15) */ + #define R_OTP_OTPSTR_CNT_ST_IDLE_Msk (0x8000UL) /*!< CNT_ST_IDLE (Bitfield-Mask: 0x01) */ +/* ======================================================= OTPSTAWR ======================================================== */ + #define R_OTP_OTPSTAWR_STAWR_Pos (0UL) /*!< STAWR (Bit 0) */ + #define R_OTP_OTPSTAWR_STAWR_Msk (0x1UL) /*!< STAWR (Bitfield-Mask: 0x01) */ +/* ======================================================= OTPADRWR ======================================================== */ + #define R_OTP_OTPADRWR_ADRWR_Pos (0UL) /*!< ADRWR (Bit 0) */ + #define R_OTP_OTPADRWR_ADRWR_Msk (0x1ffUL) /*!< ADRWR (Bitfield-Mask: 0x1ff) */ +/* ======================================================= OTPDATAWR ======================================================= */ + #define R_OTP_OTPDATAWR_DATAWR_Pos (0UL) /*!< DATAWR (Bit 0) */ + #define R_OTP_OTPDATAWR_DATAWR_Msk (0xffffUL) /*!< DATAWR (Bitfield-Mask: 0xffff) */ +/* ======================================================= OTPADRRD ======================================================== */ + #define R_OTP_OTPADRRD_ADRRD_Pos (0UL) /*!< ADRRD (Bit 0) */ + #define R_OTP_OTPADRRD_ADRRD_Msk (0x1ffUL) /*!< ADRRD (Bitfield-Mask: 0x1ff) */ +/* ======================================================= OTPDATARD ======================================================= */ + #define R_OTP_OTPDATARD_DATARD_Pos (0UL) /*!< DATARD (Bit 0) */ + #define R_OTP_OTPDATARD_DATARD_Msk (0xffffUL) /*!< DATARD (Bitfield-Mask: 0xffff) */ + +/* =========================================================================================================================== */ +/* ================ R_PTADR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= RSELP ========================================================= */ + #define R_PTADR_RSELP_RS0_Pos (0UL) /*!< RS0 (Bit 0) */ + #define R_PTADR_RSELP_RS0_Msk (0x1UL) /*!< RS0 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS1_Pos (1UL) /*!< RS1 (Bit 1) */ + #define R_PTADR_RSELP_RS1_Msk (0x2UL) /*!< RS1 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS2_Pos (2UL) /*!< RS2 (Bit 2) */ + #define R_PTADR_RSELP_RS2_Msk (0x4UL) /*!< RS2 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS3_Pos (3UL) /*!< RS3 (Bit 3) */ + #define R_PTADR_RSELP_RS3_Msk (0x8UL) /*!< RS3 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS4_Pos (4UL) /*!< RS4 (Bit 4) */ + #define R_PTADR_RSELP_RS4_Msk (0x10UL) /*!< RS4 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS5_Pos (5UL) /*!< RS5 (Bit 5) */ + #define R_PTADR_RSELP_RS5_Msk (0x20UL) /*!< RS5 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS6_Pos (6UL) /*!< RS6 (Bit 6) */ + #define R_PTADR_RSELP_RS6_Msk (0x40UL) /*!< RS6 (Bitfield-Mask: 0x01) */ + #define R_PTADR_RSELP_RS7_Pos (7UL) /*!< RS7 (Bit 7) */ + #define R_PTADR_RSELP_RS7_Msk (0x80UL) /*!< RS7 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM0 ================ */ +/* =========================================================================================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_ICU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== S_SWINT ======================================================== */ + #define R_ICU_S_SWINT_IC6_Pos (0UL) /*!< IC6 (Bit 0) */ + #define R_ICU_S_SWINT_IC6_Msk (0x1UL) /*!< IC6 (Bitfield-Mask: 0x01) */ + #define R_ICU_S_SWINT_IC7_Pos (1UL) /*!< IC7 (Bit 1) */ + #define R_ICU_S_SWINT_IC7_Msk (0x2UL) /*!< IC7 (Bitfield-Mask: 0x01) */ +/* ==================================================== S_PORTNF_FLTSEL ==================================================== */ + #define R_ICU_S_PORTNF_FLTSEL_FLT14_Pos (0UL) /*!< FLT14 (Bit 0) */ + #define R_ICU_S_PORTNF_FLTSEL_FLT14_Msk (0x1UL) /*!< FLT14 (Bitfield-Mask: 0x01) */ + #define R_ICU_S_PORTNF_FLTSEL_FLT15_Pos (1UL) /*!< FLT15 (Bit 1) */ + #define R_ICU_S_PORTNF_FLTSEL_FLT15_Msk (0x2UL) /*!< FLT15 (Bitfield-Mask: 0x01) */ + #define R_ICU_S_PORTNF_FLTSEL_FLTNMI_Pos (2UL) /*!< FLTNMI (Bit 2) */ + #define R_ICU_S_PORTNF_FLTSEL_FLTNMI_Msk (0x4UL) /*!< FLTNMI (Bitfield-Mask: 0x01) */ +/* ==================================================== S_PORTNF_CLKSEL ==================================================== */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL14_Pos (0UL) /*!< CKSEL14 (Bit 0) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL14_Msk (0x3UL) /*!< CKSEL14 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL15_Pos (2UL) /*!< CKSEL15 (Bit 2) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSEL15_Msk (0xcUL) /*!< CKSEL15 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSELNMI_Pos (4UL) /*!< CKSELNMI (Bit 4) */ + #define R_ICU_S_PORTNF_CLKSEL_CKSELNMI_Msk (0x30UL) /*!< CKSELNMI (Bitfield-Mask: 0x03) */ +/* ====================================================== S_PORTNF_MD ====================================================== */ + #define R_ICU_S_PORTNF_MD_MD14_Pos (0UL) /*!< MD14 (Bit 0) */ + #define R_ICU_S_PORTNF_MD_MD14_Msk (0x3UL) /*!< MD14 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_MD_MD15_Pos (2UL) /*!< MD15 (Bit 2) */ + #define R_ICU_S_PORTNF_MD_MD15_Msk (0xcUL) /*!< MD15 (Bitfield-Mask: 0x03) */ + #define R_ICU_S_PORTNF_MD_MDNMI_Pos (4UL) /*!< MDNMI (Bit 4) */ + #define R_ICU_S_PORTNF_MD_MDNMI_Msk (0x30UL) /*!< MDNMI (Bitfield-Mask: 0x03) */ +/* ===================================================== CPU0ERR_STAT ====================================================== */ + #define R_ICU_CPU0ERR_STAT_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_CPU0ERR_STAT_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_CPU0ERR_STAT_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_CPU0ERR_STAT_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_CPU0ERR_STAT_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_CPU0ERR_STAT_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_CPU0ERR_STAT_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_CPU0ERR_STAT_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_CPU0ERR_STAT_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST8_Pos (8UL) /*!< ER_ST8 (Bit 8) */ + #define R_ICU_CPU0ERR_STAT_ER_ST8_Msk (0x100UL) /*!< ER_ST8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_CPU0ERR_STAT_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST10_Pos (10UL) /*!< ER_ST10 (Bit 10) */ + #define R_ICU_CPU0ERR_STAT_ER_ST10_Msk (0x400UL) /*!< ER_ST10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST11_Pos (11UL) /*!< ER_ST11 (Bit 11) */ + #define R_ICU_CPU0ERR_STAT_ER_ST11_Msk (0x800UL) /*!< ER_ST11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST12_Pos (12UL) /*!< ER_ST12 (Bit 12) */ + #define R_ICU_CPU0ERR_STAT_ER_ST12_Msk (0x1000UL) /*!< ER_ST12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_CPU0ERR_STAT_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST14_Pos (14UL) /*!< ER_ST14 (Bit 14) */ + #define R_ICU_CPU0ERR_STAT_ER_ST14_Msk (0x4000UL) /*!< ER_ST14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_CPU0ERR_STAT_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_CPU0ERR_STAT_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_CPU0ERR_STAT_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_CPU0ERR_STAT_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_CPU0ERR_STAT_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_CPU0ERR_STAT_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_CPU0ERR_STAT_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_CPU0ERR_STAT_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_CPU0ERR_STAT_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_CPU0ERR_STAT_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_STAT_ER_ST25_Pos (25UL) /*!< ER_ST25 (Bit 25) */ + #define R_ICU_CPU0ERR_STAT_ER_ST25_Msk (0x2000000UL) /*!< ER_ST25 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_STAT0 ===================================================== */ + #define R_ICU_PERIERR_STAT0_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_PERIERR_STAT0_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_PERIERR_STAT0_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_PERIERR_STAT0_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_PERIERR_STAT0_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_PERIERR_STAT0_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_PERIERR_STAT0_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_PERIERR_STAT0_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_PERIERR_STAT0_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_PERIERR_STAT0_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST10_Pos (10UL) /*!< ER_ST10 (Bit 10) */ + #define R_ICU_PERIERR_STAT0_ER_ST10_Msk (0x400UL) /*!< ER_ST10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST11_Pos (11UL) /*!< ER_ST11 (Bit 11) */ + #define R_ICU_PERIERR_STAT0_ER_ST11_Msk (0x800UL) /*!< ER_ST11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST12_Pos (12UL) /*!< ER_ST12 (Bit 12) */ + #define R_ICU_PERIERR_STAT0_ER_ST12_Msk (0x1000UL) /*!< ER_ST12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_PERIERR_STAT0_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST14_Pos (14UL) /*!< ER_ST14 (Bit 14) */ + #define R_ICU_PERIERR_STAT0_ER_ST14_Msk (0x4000UL) /*!< ER_ST14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_PERIERR_STAT0_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_PERIERR_STAT0_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_PERIERR_STAT0_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_PERIERR_STAT0_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_PERIERR_STAT0_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_PERIERR_STAT0_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_PERIERR_STAT0_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_PERIERR_STAT0_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_PERIERR_STAT0_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_PERIERR_STAT0_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST25_Pos (25UL) /*!< ER_ST25 (Bit 25) */ + #define R_ICU_PERIERR_STAT0_ER_ST25_Msk (0x2000000UL) /*!< ER_ST25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST26_Pos (26UL) /*!< ER_ST26 (Bit 26) */ + #define R_ICU_PERIERR_STAT0_ER_ST26_Msk (0x4000000UL) /*!< ER_ST26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST27_Pos (27UL) /*!< ER_ST27 (Bit 27) */ + #define R_ICU_PERIERR_STAT0_ER_ST27_Msk (0x8000000UL) /*!< ER_ST27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST28_Pos (28UL) /*!< ER_ST28 (Bit 28) */ + #define R_ICU_PERIERR_STAT0_ER_ST28_Msk (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST29_Pos (29UL) /*!< ER_ST29 (Bit 29) */ + #define R_ICU_PERIERR_STAT0_ER_ST29_Msk (0x20000000UL) /*!< ER_ST29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST30_Pos (30UL) /*!< ER_ST30 (Bit 30) */ + #define R_ICU_PERIERR_STAT0_ER_ST30_Msk (0x40000000UL) /*!< ER_ST30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT0_ER_ST31_Pos (31UL) /*!< ER_ST31 (Bit 31) */ + #define R_ICU_PERIERR_STAT0_ER_ST31_Msk (0x80000000UL) /*!< ER_ST31 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_STAT1 ===================================================== */ + #define R_ICU_PERIERR_STAT1_ER_ST0_Pos (0UL) /*!< ER_ST0 (Bit 0) */ + #define R_ICU_PERIERR_STAT1_ER_ST0_Msk (0x1UL) /*!< ER_ST0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST1_Pos (1UL) /*!< ER_ST1 (Bit 1) */ + #define R_ICU_PERIERR_STAT1_ER_ST1_Msk (0x2UL) /*!< ER_ST1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST2_Pos (2UL) /*!< ER_ST2 (Bit 2) */ + #define R_ICU_PERIERR_STAT1_ER_ST2_Msk (0x4UL) /*!< ER_ST2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST3_Pos (3UL) /*!< ER_ST3 (Bit 3) */ + #define R_ICU_PERIERR_STAT1_ER_ST3_Msk (0x8UL) /*!< ER_ST3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST4_Pos (4UL) /*!< ER_ST4 (Bit 4) */ + #define R_ICU_PERIERR_STAT1_ER_ST4_Msk (0x10UL) /*!< ER_ST4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST5_Pos (5UL) /*!< ER_ST5 (Bit 5) */ + #define R_ICU_PERIERR_STAT1_ER_ST5_Msk (0x20UL) /*!< ER_ST5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST6_Pos (6UL) /*!< ER_ST6 (Bit 6) */ + #define R_ICU_PERIERR_STAT1_ER_ST6_Msk (0x40UL) /*!< ER_ST6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST7_Pos (7UL) /*!< ER_ST7 (Bit 7) */ + #define R_ICU_PERIERR_STAT1_ER_ST7_Msk (0x80UL) /*!< ER_ST7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST8_Pos (8UL) /*!< ER_ST8 (Bit 8) */ + #define R_ICU_PERIERR_STAT1_ER_ST8_Msk (0x100UL) /*!< ER_ST8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST9_Pos (9UL) /*!< ER_ST9 (Bit 9) */ + #define R_ICU_PERIERR_STAT1_ER_ST9_Msk (0x200UL) /*!< ER_ST9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST13_Pos (13UL) /*!< ER_ST13 (Bit 13) */ + #define R_ICU_PERIERR_STAT1_ER_ST13_Msk (0x2000UL) /*!< ER_ST13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST15_Pos (15UL) /*!< ER_ST15 (Bit 15) */ + #define R_ICU_PERIERR_STAT1_ER_ST15_Msk (0x8000UL) /*!< ER_ST15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST16_Pos (16UL) /*!< ER_ST16 (Bit 16) */ + #define R_ICU_PERIERR_STAT1_ER_ST16_Msk (0x10000UL) /*!< ER_ST16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST17_Pos (17UL) /*!< ER_ST17 (Bit 17) */ + #define R_ICU_PERIERR_STAT1_ER_ST17_Msk (0x20000UL) /*!< ER_ST17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST18_Pos (18UL) /*!< ER_ST18 (Bit 18) */ + #define R_ICU_PERIERR_STAT1_ER_ST18_Msk (0x40000UL) /*!< ER_ST18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST19_Pos (19UL) /*!< ER_ST19 (Bit 19) */ + #define R_ICU_PERIERR_STAT1_ER_ST19_Msk (0x80000UL) /*!< ER_ST19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST20_Pos (20UL) /*!< ER_ST20 (Bit 20) */ + #define R_ICU_PERIERR_STAT1_ER_ST20_Msk (0x100000UL) /*!< ER_ST20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST21_Pos (21UL) /*!< ER_ST21 (Bit 21) */ + #define R_ICU_PERIERR_STAT1_ER_ST21_Msk (0x200000UL) /*!< ER_ST21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST22_Pos (22UL) /*!< ER_ST22 (Bit 22) */ + #define R_ICU_PERIERR_STAT1_ER_ST22_Msk (0x400000UL) /*!< ER_ST22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST23_Pos (23UL) /*!< ER_ST23 (Bit 23) */ + #define R_ICU_PERIERR_STAT1_ER_ST23_Msk (0x800000UL) /*!< ER_ST23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST24_Pos (24UL) /*!< ER_ST24 (Bit 24) */ + #define R_ICU_PERIERR_STAT1_ER_ST24_Msk (0x1000000UL) /*!< ER_ST24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST27_Pos (27UL) /*!< ER_ST27 (Bit 27) */ + #define R_ICU_PERIERR_STAT1_ER_ST27_Msk (0x8000000UL) /*!< ER_ST27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_STAT1_ER_ST28_Pos (28UL) /*!< ER_ST28 (Bit 28) */ + #define R_ICU_PERIERR_STAT1_ER_ST28_Msk (0x10000000UL) /*!< ER_ST28 (Bitfield-Mask: 0x01) */ +/* ====================================================== CPU0ERR_CLR ====================================================== */ + #define R_ICU_CPU0ERR_CLR_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_CPU0ERR_CLR_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_CPU0ERR_CLR_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_CPU0ERR_CLR_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_CPU0ERR_CLR_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_CPU0ERR_CLR_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_CPU0ERR_CLR_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_CPU0ERR_CLR_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_CPU0ERR_CLR_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL8_Pos (8UL) /*!< ER_CL8 (Bit 8) */ + #define R_ICU_CPU0ERR_CLR_ER_CL8_Msk (0x100UL) /*!< ER_CL8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_CPU0ERR_CLR_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL10_Pos (10UL) /*!< ER_CL10 (Bit 10) */ + #define R_ICU_CPU0ERR_CLR_ER_CL10_Msk (0x400UL) /*!< ER_CL10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL11_Pos (11UL) /*!< ER_CL11 (Bit 11) */ + #define R_ICU_CPU0ERR_CLR_ER_CL11_Msk (0x800UL) /*!< ER_CL11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL12_Pos (12UL) /*!< ER_CL12 (Bit 12) */ + #define R_ICU_CPU0ERR_CLR_ER_CL12_Msk (0x1000UL) /*!< ER_CL12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_CPU0ERR_CLR_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL14_Pos (14UL) /*!< ER_CL14 (Bit 14) */ + #define R_ICU_CPU0ERR_CLR_ER_CL14_Msk (0x4000UL) /*!< ER_CL14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_CPU0ERR_CLR_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_CPU0ERR_CLR_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_CPU0ERR_CLR_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_CPU0ERR_CLR_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_CPU0ERR_CLR_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_CPU0ERR_CLR_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_CPU0ERR_CLR_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_CPU0ERR_CLR_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_CPU0ERR_CLR_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_CPU0ERR_CLR_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_CLR_ER_CL25_Pos (25UL) /*!< ER_CL25 (Bit 25) */ + #define R_ICU_CPU0ERR_CLR_ER_CL25_Msk (0x2000000UL) /*!< ER_CL25 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_CLR0 ====================================================== */ + #define R_ICU_PERIERR_CLR0_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_PERIERR_CLR0_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_PERIERR_CLR0_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_PERIERR_CLR0_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_PERIERR_CLR0_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_PERIERR_CLR0_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_PERIERR_CLR0_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_PERIERR_CLR0_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_PERIERR_CLR0_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_PERIERR_CLR0_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL10_Pos (10UL) /*!< ER_CL10 (Bit 10) */ + #define R_ICU_PERIERR_CLR0_ER_CL10_Msk (0x400UL) /*!< ER_CL10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL11_Pos (11UL) /*!< ER_CL11 (Bit 11) */ + #define R_ICU_PERIERR_CLR0_ER_CL11_Msk (0x800UL) /*!< ER_CL11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL12_Pos (12UL) /*!< ER_CL12 (Bit 12) */ + #define R_ICU_PERIERR_CLR0_ER_CL12_Msk (0x1000UL) /*!< ER_CL12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_PERIERR_CLR0_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL14_Pos (14UL) /*!< ER_CL14 (Bit 14) */ + #define R_ICU_PERIERR_CLR0_ER_CL14_Msk (0x4000UL) /*!< ER_CL14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_PERIERR_CLR0_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_PERIERR_CLR0_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_PERIERR_CLR0_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_PERIERR_CLR0_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_PERIERR_CLR0_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_PERIERR_CLR0_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_PERIERR_CLR0_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_PERIERR_CLR0_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_PERIERR_CLR0_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_PERIERR_CLR0_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL25_Pos (25UL) /*!< ER_CL25 (Bit 25) */ + #define R_ICU_PERIERR_CLR0_ER_CL25_Msk (0x2000000UL) /*!< ER_CL25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL26_Pos (26UL) /*!< ER_CL26 (Bit 26) */ + #define R_ICU_PERIERR_CLR0_ER_CL26_Msk (0x4000000UL) /*!< ER_CL26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL27_Pos (27UL) /*!< ER_CL27 (Bit 27) */ + #define R_ICU_PERIERR_CLR0_ER_CL27_Msk (0x8000000UL) /*!< ER_CL27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL28_Pos (28UL) /*!< ER_CL28 (Bit 28) */ + #define R_ICU_PERIERR_CLR0_ER_CL28_Msk (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL29_Pos (29UL) /*!< ER_CL29 (Bit 29) */ + #define R_ICU_PERIERR_CLR0_ER_CL29_Msk (0x20000000UL) /*!< ER_CL29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL30_Pos (30UL) /*!< ER_CL30 (Bit 30) */ + #define R_ICU_PERIERR_CLR0_ER_CL30_Msk (0x40000000UL) /*!< ER_CL30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR0_ER_CL31_Pos (31UL) /*!< ER_CL31 (Bit 31) */ + #define R_ICU_PERIERR_CLR0_ER_CL31_Msk (0x80000000UL) /*!< ER_CL31 (Bitfield-Mask: 0x01) */ +/* ===================================================== PERIERR_CLR1 ====================================================== */ + #define R_ICU_PERIERR_CLR1_ER_CL0_Pos (0UL) /*!< ER_CL0 (Bit 0) */ + #define R_ICU_PERIERR_CLR1_ER_CL0_Msk (0x1UL) /*!< ER_CL0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL1_Pos (1UL) /*!< ER_CL1 (Bit 1) */ + #define R_ICU_PERIERR_CLR1_ER_CL1_Msk (0x2UL) /*!< ER_CL1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL2_Pos (2UL) /*!< ER_CL2 (Bit 2) */ + #define R_ICU_PERIERR_CLR1_ER_CL2_Msk (0x4UL) /*!< ER_CL2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL3_Pos (3UL) /*!< ER_CL3 (Bit 3) */ + #define R_ICU_PERIERR_CLR1_ER_CL3_Msk (0x8UL) /*!< ER_CL3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL4_Pos (4UL) /*!< ER_CL4 (Bit 4) */ + #define R_ICU_PERIERR_CLR1_ER_CL4_Msk (0x10UL) /*!< ER_CL4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL5_Pos (5UL) /*!< ER_CL5 (Bit 5) */ + #define R_ICU_PERIERR_CLR1_ER_CL5_Msk (0x20UL) /*!< ER_CL5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL6_Pos (6UL) /*!< ER_CL6 (Bit 6) */ + #define R_ICU_PERIERR_CLR1_ER_CL6_Msk (0x40UL) /*!< ER_CL6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL7_Pos (7UL) /*!< ER_CL7 (Bit 7) */ + #define R_ICU_PERIERR_CLR1_ER_CL7_Msk (0x80UL) /*!< ER_CL7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL8_Pos (8UL) /*!< ER_CL8 (Bit 8) */ + #define R_ICU_PERIERR_CLR1_ER_CL8_Msk (0x100UL) /*!< ER_CL8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL9_Pos (9UL) /*!< ER_CL9 (Bit 9) */ + #define R_ICU_PERIERR_CLR1_ER_CL9_Msk (0x200UL) /*!< ER_CL9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL13_Pos (13UL) /*!< ER_CL13 (Bit 13) */ + #define R_ICU_PERIERR_CLR1_ER_CL13_Msk (0x2000UL) /*!< ER_CL13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL15_Pos (15UL) /*!< ER_CL15 (Bit 15) */ + #define R_ICU_PERIERR_CLR1_ER_CL15_Msk (0x8000UL) /*!< ER_CL15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL16_Pos (16UL) /*!< ER_CL16 (Bit 16) */ + #define R_ICU_PERIERR_CLR1_ER_CL16_Msk (0x10000UL) /*!< ER_CL16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL17_Pos (17UL) /*!< ER_CL17 (Bit 17) */ + #define R_ICU_PERIERR_CLR1_ER_CL17_Msk (0x20000UL) /*!< ER_CL17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL18_Pos (18UL) /*!< ER_CL18 (Bit 18) */ + #define R_ICU_PERIERR_CLR1_ER_CL18_Msk (0x40000UL) /*!< ER_CL18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL19_Pos (19UL) /*!< ER_CL19 (Bit 19) */ + #define R_ICU_PERIERR_CLR1_ER_CL19_Msk (0x80000UL) /*!< ER_CL19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL20_Pos (20UL) /*!< ER_CL20 (Bit 20) */ + #define R_ICU_PERIERR_CLR1_ER_CL20_Msk (0x100000UL) /*!< ER_CL20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL21_Pos (21UL) /*!< ER_CL21 (Bit 21) */ + #define R_ICU_PERIERR_CLR1_ER_CL21_Msk (0x200000UL) /*!< ER_CL21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL22_Pos (22UL) /*!< ER_CL22 (Bit 22) */ + #define R_ICU_PERIERR_CLR1_ER_CL22_Msk (0x400000UL) /*!< ER_CL22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL23_Pos (23UL) /*!< ER_CL23 (Bit 23) */ + #define R_ICU_PERIERR_CLR1_ER_CL23_Msk (0x800000UL) /*!< ER_CL23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL24_Pos (24UL) /*!< ER_CL24 (Bit 24) */ + #define R_ICU_PERIERR_CLR1_ER_CL24_Msk (0x1000000UL) /*!< ER_CL24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL27_Pos (27UL) /*!< ER_CL27 (Bit 27) */ + #define R_ICU_PERIERR_CLR1_ER_CL27_Msk (0x8000000UL) /*!< ER_CL27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_CLR1_ER_CL28_Pos (28UL) /*!< ER_CL28 (Bit 28) */ + #define R_ICU_PERIERR_CLR1_ER_CL28_Msk (0x10000000UL) /*!< ER_CL28 (Bitfield-Mask: 0x01) */ +/* ==================================================== CPU0ERR_RSTMSK ===================================================== */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK8_Pos (8UL) /*!< RS_MK8 (Bit 8) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK8_Msk (0x100UL) /*!< RS_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK10_Pos (10UL) /*!< RS_MK10 (Bit 10) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK10_Msk (0x400UL) /*!< RS_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK11_Pos (11UL) /*!< RS_MK11 (Bit 11) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK11_Msk (0x800UL) /*!< RS_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK12_Pos (12UL) /*!< RS_MK12 (Bit 12) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK12_Msk (0x1000UL) /*!< RS_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK14_Pos (14UL) /*!< RS_MK14 (Bit 14) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK14_Msk (0x4000UL) /*!< RS_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK25_Pos (25UL) /*!< RS_MK25 (Bit 25) */ + #define R_ICU_CPU0ERR_RSTMSK_RS_MK25_Msk (0x2000000UL) /*!< RS_MK25 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_RSTMSK0 ==================================================== */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK10_Pos (10UL) /*!< RS_MK10 (Bit 10) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK10_Msk (0x400UL) /*!< RS_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK11_Pos (11UL) /*!< RS_MK11 (Bit 11) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK11_Msk (0x800UL) /*!< RS_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK12_Pos (12UL) /*!< RS_MK12 (Bit 12) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK12_Msk (0x1000UL) /*!< RS_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK14_Pos (14UL) /*!< RS_MK14 (Bit 14) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK14_Msk (0x4000UL) /*!< RS_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK25_Pos (25UL) /*!< RS_MK25 (Bit 25) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK25_Msk (0x2000000UL) /*!< RS_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK26_Pos (26UL) /*!< RS_MK26 (Bit 26) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK26_Msk (0x4000000UL) /*!< RS_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK27_Pos (27UL) /*!< RS_MK27 (Bit 27) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK27_Msk (0x8000000UL) /*!< RS_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK28_Pos (28UL) /*!< RS_MK28 (Bit 28) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK28_Msk (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK29_Pos (29UL) /*!< RS_MK29 (Bit 29) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK29_Msk (0x20000000UL) /*!< RS_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK30_Pos (30UL) /*!< RS_MK30 (Bit 30) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK30_Msk (0x40000000UL) /*!< RS_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK31_Pos (31UL) /*!< RS_MK31 (Bit 31) */ + #define R_ICU_PERIERR_RSTMSK0_RS_MK31_Msk (0x80000000UL) /*!< RS_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_RSTMSK1 ==================================================== */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK0_Pos (0UL) /*!< RS_MK0 (Bit 0) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK0_Msk (0x1UL) /*!< RS_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK1_Pos (1UL) /*!< RS_MK1 (Bit 1) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK1_Msk (0x2UL) /*!< RS_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK2_Pos (2UL) /*!< RS_MK2 (Bit 2) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK2_Msk (0x4UL) /*!< RS_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK3_Pos (3UL) /*!< RS_MK3 (Bit 3) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK3_Msk (0x8UL) /*!< RS_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK4_Pos (4UL) /*!< RS_MK4 (Bit 4) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK4_Msk (0x10UL) /*!< RS_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK5_Pos (5UL) /*!< RS_MK5 (Bit 5) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK5_Msk (0x20UL) /*!< RS_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK6_Pos (6UL) /*!< RS_MK6 (Bit 6) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK6_Msk (0x40UL) /*!< RS_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK7_Pos (7UL) /*!< RS_MK7 (Bit 7) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK7_Msk (0x80UL) /*!< RS_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK8_Pos (8UL) /*!< RS_MK8 (Bit 8) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK8_Msk (0x100UL) /*!< RS_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK9_Pos (9UL) /*!< RS_MK9 (Bit 9) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK9_Msk (0x200UL) /*!< RS_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK13_Pos (13UL) /*!< RS_MK13 (Bit 13) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK13_Msk (0x2000UL) /*!< RS_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK15_Pos (15UL) /*!< RS_MK15 (Bit 15) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK15_Msk (0x8000UL) /*!< RS_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK16_Pos (16UL) /*!< RS_MK16 (Bit 16) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK16_Msk (0x10000UL) /*!< RS_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK17_Pos (17UL) /*!< RS_MK17 (Bit 17) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK17_Msk (0x20000UL) /*!< RS_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK18_Pos (18UL) /*!< RS_MK18 (Bit 18) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK18_Msk (0x40000UL) /*!< RS_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK19_Pos (19UL) /*!< RS_MK19 (Bit 19) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK19_Msk (0x80000UL) /*!< RS_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK20_Pos (20UL) /*!< RS_MK20 (Bit 20) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK20_Msk (0x100000UL) /*!< RS_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK21_Pos (21UL) /*!< RS_MK21 (Bit 21) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK21_Msk (0x200000UL) /*!< RS_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK22_Pos (22UL) /*!< RS_MK22 (Bit 22) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK22_Msk (0x400000UL) /*!< RS_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK23_Pos (23UL) /*!< RS_MK23 (Bit 23) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK23_Msk (0x800000UL) /*!< RS_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK24_Pos (24UL) /*!< RS_MK24 (Bit 24) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK24_Msk (0x1000000UL) /*!< RS_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK27_Pos (27UL) /*!< RS_MK27 (Bit 27) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK27_Msk (0x8000000UL) /*!< RS_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK28_Pos (28UL) /*!< RS_MK28 (Bit 28) */ + #define R_ICU_PERIERR_RSTMSK1_RS_MK28_Msk (0x10000000UL) /*!< RS_MK28 (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0ERR_E0MSK ===================================================== */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK8_Pos (8UL) /*!< E0_MK8 (Bit 8) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK8_Msk (0x100UL) /*!< E0_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK10_Pos (10UL) /*!< E0_MK10 (Bit 10) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK10_Msk (0x400UL) /*!< E0_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK11_Pos (11UL) /*!< E0_MK11 (Bit 11) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK11_Msk (0x800UL) /*!< E0_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK12_Pos (12UL) /*!< E0_MK12 (Bit 12) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK12_Msk (0x1000UL) /*!< E0_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK14_Pos (14UL) /*!< E0_MK14 (Bit 14) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK14_Msk (0x4000UL) /*!< E0_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK25_Pos (25UL) /*!< E0_MK25 (Bit 25) */ + #define R_ICU_CPU0ERR_E0MSK_E0_MK25_Msk (0x2000000UL) /*!< E0_MK25 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E0MSK0 ===================================================== */ + #define R_ICU_PERIERR_E0MSK0_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK10_Pos (10UL) /*!< E0_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK10_Msk (0x400UL) /*!< E0_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK11_Pos (11UL) /*!< E0_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK11_Msk (0x800UL) /*!< E0_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK12_Pos (12UL) /*!< E0_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK12_Msk (0x1000UL) /*!< E0_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK14_Pos (14UL) /*!< E0_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK14_Msk (0x4000UL) /*!< E0_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK25_Pos (25UL) /*!< E0_MK25 (Bit 25) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK25_Msk (0x2000000UL) /*!< E0_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK26_Pos (26UL) /*!< E0_MK26 (Bit 26) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK26_Msk (0x4000000UL) /*!< E0_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK27_Pos (27UL) /*!< E0_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK27_Msk (0x8000000UL) /*!< E0_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK28_Pos (28UL) /*!< E0_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK28_Msk (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK29_Pos (29UL) /*!< E0_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK29_Msk (0x20000000UL) /*!< E0_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK30_Pos (30UL) /*!< E0_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK30_Msk (0x40000000UL) /*!< E0_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK31_Pos (31UL) /*!< E0_MK31 (Bit 31) */ + #define R_ICU_PERIERR_E0MSK0_E0_MK31_Msk (0x80000000UL) /*!< E0_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E0MSK1 ===================================================== */ + #define R_ICU_PERIERR_E0MSK1_E0_MK0_Pos (0UL) /*!< E0_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK0_Msk (0x1UL) /*!< E0_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK1_Pos (1UL) /*!< E0_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK1_Msk (0x2UL) /*!< E0_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK2_Pos (2UL) /*!< E0_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK2_Msk (0x4UL) /*!< E0_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK3_Pos (3UL) /*!< E0_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK3_Msk (0x8UL) /*!< E0_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK4_Pos (4UL) /*!< E0_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK4_Msk (0x10UL) /*!< E0_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK5_Pos (5UL) /*!< E0_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK5_Msk (0x20UL) /*!< E0_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK6_Pos (6UL) /*!< E0_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK6_Msk (0x40UL) /*!< E0_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK7_Pos (7UL) /*!< E0_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK7_Msk (0x80UL) /*!< E0_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK8_Pos (8UL) /*!< E0_MK8 (Bit 8) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK8_Msk (0x100UL) /*!< E0_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK9_Pos (9UL) /*!< E0_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK9_Msk (0x200UL) /*!< E0_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK13_Pos (13UL) /*!< E0_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK13_Msk (0x2000UL) /*!< E0_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK15_Pos (15UL) /*!< E0_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK15_Msk (0x8000UL) /*!< E0_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK16_Pos (16UL) /*!< E0_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK16_Msk (0x10000UL) /*!< E0_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK17_Pos (17UL) /*!< E0_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK17_Msk (0x20000UL) /*!< E0_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK18_Pos (18UL) /*!< E0_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK18_Msk (0x40000UL) /*!< E0_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK19_Pos (19UL) /*!< E0_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK19_Msk (0x80000UL) /*!< E0_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK20_Pos (20UL) /*!< E0_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK20_Msk (0x100000UL) /*!< E0_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK21_Pos (21UL) /*!< E0_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK21_Msk (0x200000UL) /*!< E0_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK22_Pos (22UL) /*!< E0_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK22_Msk (0x400000UL) /*!< E0_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK23_Pos (23UL) /*!< E0_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK23_Msk (0x800000UL) /*!< E0_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK24_Pos (24UL) /*!< E0_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK24_Msk (0x1000000UL) /*!< E0_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK27_Pos (27UL) /*!< E0_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK27_Msk (0x8000000UL) /*!< E0_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK28_Pos (28UL) /*!< E0_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E0MSK1_E0_MK28_Msk (0x10000000UL) /*!< E0_MK28 (Bitfield-Mask: 0x01) */ +/* ===================================================== CPU0ERR_E1MSK ===================================================== */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK8_Pos (8UL) /*!< E1_MK8 (Bit 8) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK8_Msk (0x100UL) /*!< E1_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK10_Pos (10UL) /*!< E1_MK10 (Bit 10) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK10_Msk (0x400UL) /*!< E1_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK11_Pos (11UL) /*!< E1_MK11 (Bit 11) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK11_Msk (0x800UL) /*!< E1_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK12_Pos (12UL) /*!< E1_MK12 (Bit 12) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK12_Msk (0x1000UL) /*!< E1_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK14_Pos (14UL) /*!< E1_MK14 (Bit 14) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK14_Msk (0x4000UL) /*!< E1_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK25_Pos (25UL) /*!< E1_MK25 (Bit 25) */ + #define R_ICU_CPU0ERR_E1MSK_E1_MK25_Msk (0x2000000UL) /*!< E1_MK25 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E1MSK0 ===================================================== */ + #define R_ICU_PERIERR_E1MSK0_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK10_Pos (10UL) /*!< E1_MK10 (Bit 10) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK10_Msk (0x400UL) /*!< E1_MK10 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK11_Pos (11UL) /*!< E1_MK11 (Bit 11) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK11_Msk (0x800UL) /*!< E1_MK11 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK12_Pos (12UL) /*!< E1_MK12 (Bit 12) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK12_Msk (0x1000UL) /*!< E1_MK12 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK14_Pos (14UL) /*!< E1_MK14 (Bit 14) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK14_Msk (0x4000UL) /*!< E1_MK14 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK25_Pos (25UL) /*!< E1_MK25 (Bit 25) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK25_Msk (0x2000000UL) /*!< E1_MK25 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK26_Pos (26UL) /*!< E1_MK26 (Bit 26) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK26_Msk (0x4000000UL) /*!< E1_MK26 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK27_Pos (27UL) /*!< E1_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK27_Msk (0x8000000UL) /*!< E1_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK28_Pos (28UL) /*!< E1_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK28_Msk (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK29_Pos (29UL) /*!< E1_MK29 (Bit 29) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK29_Msk (0x20000000UL) /*!< E1_MK29 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK30_Pos (30UL) /*!< E1_MK30 (Bit 30) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK30_Msk (0x40000000UL) /*!< E1_MK30 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK31_Pos (31UL) /*!< E1_MK31 (Bit 31) */ + #define R_ICU_PERIERR_E1MSK0_E1_MK31_Msk (0x80000000UL) /*!< E1_MK31 (Bitfield-Mask: 0x01) */ +/* ==================================================== PERIERR_E1MSK1 ===================================================== */ + #define R_ICU_PERIERR_E1MSK1_E1_MK0_Pos (0UL) /*!< E1_MK0 (Bit 0) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK0_Msk (0x1UL) /*!< E1_MK0 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK1_Pos (1UL) /*!< E1_MK1 (Bit 1) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK1_Msk (0x2UL) /*!< E1_MK1 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK2_Pos (2UL) /*!< E1_MK2 (Bit 2) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK2_Msk (0x4UL) /*!< E1_MK2 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK3_Pos (3UL) /*!< E1_MK3 (Bit 3) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK3_Msk (0x8UL) /*!< E1_MK3 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK4_Pos (4UL) /*!< E1_MK4 (Bit 4) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK4_Msk (0x10UL) /*!< E1_MK4 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK5_Pos (5UL) /*!< E1_MK5 (Bit 5) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK5_Msk (0x20UL) /*!< E1_MK5 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK6_Pos (6UL) /*!< E1_MK6 (Bit 6) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK6_Msk (0x40UL) /*!< E1_MK6 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK7_Pos (7UL) /*!< E1_MK7 (Bit 7) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK7_Msk (0x80UL) /*!< E1_MK7 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK8_Pos (8UL) /*!< E1_MK8 (Bit 8) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK8_Msk (0x100UL) /*!< E1_MK8 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK9_Pos (9UL) /*!< E1_MK9 (Bit 9) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK9_Msk (0x200UL) /*!< E1_MK9 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK13_Pos (13UL) /*!< E1_MK13 (Bit 13) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK13_Msk (0x2000UL) /*!< E1_MK13 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK15_Pos (15UL) /*!< E1_MK15 (Bit 15) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK15_Msk (0x8000UL) /*!< E1_MK15 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK16_Pos (16UL) /*!< E1_MK16 (Bit 16) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK16_Msk (0x10000UL) /*!< E1_MK16 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK17_Pos (17UL) /*!< E1_MK17 (Bit 17) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK17_Msk (0x20000UL) /*!< E1_MK17 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK18_Pos (18UL) /*!< E1_MK18 (Bit 18) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK18_Msk (0x40000UL) /*!< E1_MK18 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK19_Pos (19UL) /*!< E1_MK19 (Bit 19) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK19_Msk (0x80000UL) /*!< E1_MK19 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK20_Pos (20UL) /*!< E1_MK20 (Bit 20) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK20_Msk (0x100000UL) /*!< E1_MK20 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK21_Pos (21UL) /*!< E1_MK21 (Bit 21) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK21_Msk (0x200000UL) /*!< E1_MK21 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK22_Pos (22UL) /*!< E1_MK22 (Bit 22) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK22_Msk (0x400000UL) /*!< E1_MK22 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK23_Pos (23UL) /*!< E1_MK23 (Bit 23) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK23_Msk (0x800000UL) /*!< E1_MK23 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK24_Pos (24UL) /*!< E1_MK24 (Bit 24) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK24_Msk (0x1000000UL) /*!< E1_MK24 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK27_Pos (27UL) /*!< E1_MK27 (Bit 27) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK27_Msk (0x8000000UL) /*!< E1_MK27 (Bitfield-Mask: 0x01) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK28_Pos (28UL) /*!< E1_MK28 (Bit 28) */ + #define R_ICU_PERIERR_E1MSK1_E1_MK28_Msk (0x10000000UL) /*!< E1_MK28 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSC_S ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== SCKCR2 ========================================================= */ + #define R_SYSC_S_SCKCR2_FSELCPU0_Pos (0UL) /*!< FSELCPU0 (Bit 0) */ + #define R_SYSC_S_SCKCR2_FSELCPU0_Msk (0x1UL) /*!< FSELCPU0 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_SCKCR2_DIVSELSUB_Pos (5UL) /*!< DIVSELSUB (Bit 5) */ + #define R_SYSC_S_SCKCR2_DIVSELSUB_Msk (0x20UL) /*!< DIVSELSUB (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Pos (24UL) /*!< SPI3ASYNCSEL (Bit 24) */ + #define R_SYSC_S_SCKCR2_SPI3ASYNCSEL_Msk (0x1000000UL) /*!< SPI3ASYNCSEL (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Pos (25UL) /*!< SCI5ASYNCSEL (Bit 25) */ + #define R_SYSC_S_SCKCR2_SCI5ASYNCSEL_Msk (0x2000000UL) /*!< SCI5ASYNCSEL (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL0MON ======================================================== */ + #define R_SYSC_S_PLL0MON_PLL0MON_Pos (0UL) /*!< PLL0MON (Bit 0) */ + #define R_SYSC_S_PLL0MON_PLL0MON_Msk (0x1UL) /*!< PLL0MON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL1MON ======================================================== */ + #define R_SYSC_S_PLL1MON_PLL1MON_Pos (0UL) /*!< PLL1MON (Bit 0) */ + #define R_SYSC_S_PLL1MON_PLL1MON_Msk (0x1UL) /*!< PLL1MON (Bitfield-Mask: 0x01) */ +/* ======================================================== PLL1EN ========================================================= */ + #define R_SYSC_S_PLL1EN_PLL1EN_Pos (0UL) /*!< PLL1EN (Bit 0) */ + #define R_SYSC_S_PLL1EN_PLL1EN_Msk (0x1UL) /*!< PLL1EN (Bitfield-Mask: 0x01) */ +/* ======================================================== LOCOCR ========================================================= */ + #define R_SYSC_S_LOCOCR_LCSTP_Pos (0UL) /*!< LCSTP (Bit 0) */ + #define R_SYSC_S_LOCOCR_LCSTP_Msk (0x1UL) /*!< LCSTP (Bitfield-Mask: 0x01) */ +/* ======================================================= HIZCTRLEN ======================================================= */ + #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Pos (0UL) /*!< CLMA3MASK (Bit 0) */ + #define R_SYSC_S_HIZCTRLEN_CLMA3MASK_Msk (0x1UL) /*!< CLMA3MASK (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Pos (1UL) /*!< CLMA0MASK (Bit 1) */ + #define R_SYSC_S_HIZCTRLEN_CLMA0MASK_Msk (0x2UL) /*!< CLMA0MASK (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Pos (2UL) /*!< CLMA1MASK (Bit 2) */ + #define R_SYSC_S_HIZCTRLEN_CLMA1MASK_Msk (0x4UL) /*!< CLMA1MASK (Bitfield-Mask: 0x01) */ +/* ======================================================== SWRSYS ========================================================= */ + #define R_SYSC_S_SWRSYS_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_SYSC_S_SWRSYS_SWR_Msk (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== SWRCPU0 ======================================================== */ + #define R_SYSC_S_SWRCPU0_SWR_Pos (0UL) /*!< SWR (Bit 0) */ + #define R_SYSC_S_SWRCPU0_SWR_Msk (0xffffffffUL) /*!< SWR (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== MRCTLI ========================================================= */ + #define R_SYSC_S_MRCTLI_MRCTLI00_Pos (0UL) /*!< MRCTLI00 (Bit 0) */ + #define R_SYSC_S_MRCTLI_MRCTLI00_Msk (0x1UL) /*!< MRCTLI00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MRCTLI_MRCTLI01_Pos (1UL) /*!< MRCTLI01 (Bit 1) */ + #define R_SYSC_S_MRCTLI_MRCTLI01_Msk (0x2UL) /*!< MRCTLI01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MRCTLI_MRCTLI02_Pos (2UL) /*!< MRCTLI02 (Bit 2) */ + #define R_SYSC_S_MRCTLI_MRCTLI02_Msk (0x4UL) /*!< MRCTLI02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MRCTLI_MRCTLI03_Pos (3UL) /*!< MRCTLI03 (Bit 3) */ + #define R_SYSC_S_MRCTLI_MRCTLI03_Msk (0x8UL) /*!< MRCTLI03 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRF ======================================================== */ + #define R_SYSC_S_MSTPCRF_MSTPCRF00_Pos (0UL) /*!< MSTPCRF00 (Bit 0) */ + #define R_SYSC_S_MSTPCRF_MSTPCRF00_Msk (0x1UL) /*!< MSTPCRF00 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRG ======================================================== */ + #define R_SYSC_S_MSTPCRG_MSTPCRG00_Pos (0UL) /*!< MSTPCRG00 (Bit 0) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG00_Msk (0x1UL) /*!< MSTPCRG00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG01_Pos (1UL) /*!< MSTPCRG01 (Bit 1) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG01_Msk (0x2UL) /*!< MSTPCRG01 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG02_Pos (2UL) /*!< MSTPCRG02 (Bit 2) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG02_Msk (0x4UL) /*!< MSTPCRG02 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG03_Pos (3UL) /*!< MSTPCRG03 (Bit 3) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG03_Msk (0x8UL) /*!< MSTPCRG03 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG04_Pos (4UL) /*!< MSTPCRG04 (Bit 4) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG04_Msk (0x10UL) /*!< MSTPCRG04 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG05_Pos (5UL) /*!< MSTPCRG05 (Bit 5) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG05_Msk (0x20UL) /*!< MSTPCRG05 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG08_Pos (8UL) /*!< MSTPCRG08 (Bit 8) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG08_Msk (0x100UL) /*!< MSTPCRG08 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG09_Pos (9UL) /*!< MSTPCRG09 (Bit 9) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG09_Msk (0x200UL) /*!< MSTPCRG09 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG10_Pos (10UL) /*!< MSTPCRG10 (Bit 10) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG10_Msk (0x400UL) /*!< MSTPCRG10 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG11_Pos (11UL) /*!< MSTPCRG11 (Bit 11) */ + #define R_SYSC_S_MSTPCRG_MSTPCRG11_Msk (0x800UL) /*!< MSTPCRG11 (Bitfield-Mask: 0x01) */ +/* ======================================================== MSTPCRI ======================================================== */ + #define R_SYSC_S_MSTPCRI_MSTPCRI00_Pos (0UL) /*!< MSTPCRI00 (Bit 0) */ + #define R_SYSC_S_MSTPCRI_MSTPCRI00_Msk (0x1UL) /*!< MSTPCRI00 (Bitfield-Mask: 0x01) */ + #define R_SYSC_S_MSTPCRI_MSTPCRI01_Pos (1UL) /*!< MSTPCRI01 (Bit 1) */ + #define R_SYSC_S_MSTPCRI_MSTPCRI01_Msk (0x2UL) /*!< MSTPCRI01 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_CLMA0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CTL0 ========================================================== */ + #define R_CLMA0_CTL0_CLME_Pos (0UL) /*!< CLME (Bit 0) */ + #define R_CLMA0_CTL0_CLME_Msk (0x1UL) /*!< CLME (Bitfield-Mask: 0x01) */ +/* ========================================================= CMPL ========================================================== */ + #define R_CLMA0_CMPL_CMPL_Pos (0UL) /*!< CMPL (Bit 0) */ + #define R_CLMA0_CMPL_CMPL_Msk (0xfffUL) /*!< CMPL (Bitfield-Mask: 0xfff) */ +/* ========================================================= CMPH ========================================================== */ + #define R_CLMA0_CMPH_CMPH_Pos (0UL) /*!< CMPH (Bit 0) */ + #define R_CLMA0_CMPH_CMPH_Msk (0xfffUL) /*!< CMPH (Bitfield-Mask: 0xfff) */ +/* ========================================================= PCMD ========================================================== */ +/* ======================================================== PROTSR ========================================================= */ + #define R_CLMA0_PROTSR_PRERR_Pos (0UL) /*!< PRERR (Bit 0) */ + #define R_CLMA0_PROTSR_PRERR_Msk (0x1UL) /*!< PRERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================= ERRINF_R ======================================================== */ + #define R_MPU0_ERRINF_R_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_MPU0_ERRINF_R_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_R_RW_Pos (1UL) /*!< RW (Bit 1) */ + #define R_MPU0_ERRINF_R_RW_Msk (0x2UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_R_ERRADDR_Pos (2UL) /*!< ERRADDR (Bit 2) */ + #define R_MPU0_ERRINF_R_ERRADDR_Msk (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff) */ +/* ======================================================= ERRINF_W ======================================================== */ + #define R_MPU0_ERRINF_W_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_MPU0_ERRINF_W_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_W_RW_Pos (1UL) /*!< RW (Bit 1) */ + #define R_MPU0_ERRINF_W_RW_Msk (0x2UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_MPU0_ERRINF_W_ERRADDR_Pos (2UL) /*!< ERRADDR (Bit 2) */ + #define R_MPU0_ERRINF_W_ERRADDR_Msk (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_MPU3 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== ERRINF ========================================================= */ + #define R_MPU3_ERRINF_VALID_Pos (0UL) /*!< VALID (Bit 0) */ + #define R_MPU3_ERRINF_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ + #define R_MPU3_ERRINF_RW_Pos (1UL) /*!< RW (Bit 1) */ + #define R_MPU3_ERRINF_RW_Msk (0x2UL) /*!< RW (Bitfield-Mask: 0x01) */ + #define R_MPU3_ERRINF_ERRADDR_Pos (2UL) /*!< ERRADDR (Bit 2) */ + #define R_MPU3_ERRINF_ERRADDR_Msk (0xfffffffcUL) /*!< ERRADDR (Bitfield-Mask: 0x3fffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_SYSRAM_CTL ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== SYSRAM_CTRL0 ====================================================== */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Pos (0UL) /*!< VECEN (Bit 0) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VECEN_Msk (0x1UL) /*!< VECEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Pos (16UL) /*!< VRWEN (Bit 16) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VRWEN_Msk (0xf0000UL) /*!< VRWEN (Bitfield-Mask: 0x0f) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Pos (20UL) /*!< VCEN (Bit 20) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VCEN_Msk (0x100000UL) /*!< VCEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Pos (21UL) /*!< VLWEN (Bit 21) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_VLWEN_Msk (0x200000UL) /*!< VLWEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Pos (24UL) /*!< MKICCAXIERR (Bit 24) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL0_MKICCAXIERR_Msk (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01) */ +/* ===================================================== SYSRAM_CTRL1 ====================================================== */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Pos (0UL) /*!< VECEN (Bit 0) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VECEN_Msk (0x1UL) /*!< VECEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Pos (16UL) /*!< VRWEN (Bit 16) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VRWEN_Msk (0xf0000UL) /*!< VRWEN (Bitfield-Mask: 0x0f) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Pos (20UL) /*!< VCEN (Bit 20) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VCEN_Msk (0x100000UL) /*!< VCEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Pos (21UL) /*!< VLWEN (Bit 21) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_VLWEN_Msk (0x200000UL) /*!< VLWEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Pos (24UL) /*!< MKICCAXIERR (Bit 24) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL1_MKICCAXIERR_Msk (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01) */ +/* ===================================================== SYSRAM_CTRL2 ====================================================== */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VECEN_Pos (0UL) /*!< VECEN (Bit 0) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VECEN_Msk (0x1UL) /*!< VECEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VRWEN_Pos (16UL) /*!< VRWEN (Bit 16) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VRWEN_Msk (0xf0000UL) /*!< VRWEN (Bitfield-Mask: 0x0f) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VCEN_Pos (20UL) /*!< VCEN (Bit 20) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VCEN_Msk (0x100000UL) /*!< VCEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VLWEN_Pos (21UL) /*!< VLWEN (Bit 21) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_VLWEN_Msk (0x200000UL) /*!< VLWEN (Bitfield-Mask: 0x01) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_MKICCAXIERR_Pos (24UL) /*!< MKICCAXIERR (Bit 24) */ + #define R_SYSRAM_CTL_SYSRAM_CTRL2_MKICCAXIERR_Msk (0x1000000UL) /*!< MKICCAXIERR (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_SHOSTIF_CFG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= SHCFG ========================================================= */ + #define R_SHOSTIF_CFG_SHCFG_SPIMODE_Pos (0UL) /*!< SPIMODE (Bit 0) */ + #define R_SHOSTIF_CFG_SHCFG_SPIMODE_Msk (0x3UL) /*!< SPIMODE (Bitfield-Mask: 0x03) */ + #define R_SHOSTIF_CFG_SHCFG_BYTESWAP_Pos (2UL) /*!< BYTESWAP (Bit 2) */ + #define R_SHOSTIF_CFG_SHCFG_BYTESWAP_Msk (0x4UL) /*!< BYTESWAP (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_CFG_SHCFG_ADDRESSING_Pos (3UL) /*!< ADDRESSING (Bit 3) */ + #define R_SHOSTIF_CFG_SHCFG_ADDRESSING_Msk (0x8UL) /*!< ADDRESSING (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_CFG_SHCFG_SLEEP_Pos (4UL) /*!< SLEEP (Bit 4) */ + #define R_SHOSTIF_CFG_SHCFG_SLEEP_Msk (0x10UL) /*!< SLEEP (Bitfield-Mask: 0x01) */ + #define R_SHOSTIF_CFG_SHCFG_INTMASKI_Pos (16UL) /*!< INTMASKI (Bit 16) */ + #define R_SHOSTIF_CFG_SHCFG_INTMASKI_Msk (0x3f0000UL) /*!< INTMASKI (Bitfield-Mask: 0x3f) */ + #define R_SHOSTIF_CFG_SHCFG_INTMASKE_Pos (24UL) /*!< INTMASKE (Bit 24) */ + #define R_SHOSTIF_CFG_SHCFG_INTMASKE_Msk (0x3f000000UL) /*!< INTMASKE (Bitfield-Mask: 0x3f) */ + +/* =========================================================================================================================== */ +/* ================ R_PHOSTIF_CFG ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PHCFG ========================================================= */ + #define R_PHOSTIF_CFG_PHCFG_MEMIFSEL_Pos (0UL) /*!< MEMIFSEL (Bit 0) */ + #define R_PHOSTIF_CFG_PHCFG_MEMIFSEL_Msk (0x1UL) /*!< MEMIFSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHCFG_BUSSSEL_Pos (4UL) /*!< BUSSSEL (Bit 4) */ + #define R_PHOSTIF_CFG_PHCFG_BUSSSEL_Msk (0x10UL) /*!< BUSSSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHCFG_HIFSYNC_Pos (8UL) /*!< HIFSYNC (Bit 8) */ + #define R_PHOSTIF_CFG_PHCFG_HIFSYNC_Msk (0x100UL) /*!< HIFSYNC (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHCFG_MEMCSEL_Pos (12UL) /*!< MEMCSEL (Bit 12) */ + #define R_PHOSTIF_CFG_PHCFG_MEMCSEL_Msk (0x1000UL) /*!< MEMCSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHCFG_HWRZSEL_Pos (16UL) /*!< HWRZSEL (Bit 16) */ + #define R_PHOSTIF_CFG_PHCFG_HWRZSEL_Msk (0x10000UL) /*!< HWRZSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHCFG_ADMUXMODE_Pos (20UL) /*!< ADMUXMODE (Bit 20) */ + #define R_PHOSTIF_CFG_PHCFG_ADMUXMODE_Msk (0x100000UL) /*!< ADMUXMODE (Bitfield-Mask: 0x01) */ +/* ========================================================= PHACC ========================================================= */ + #define R_PHOSTIF_CFG_PHACC_HIFRDYSEL_Pos (0UL) /*!< HIFRDYSEL (Bit 0) */ + #define R_PHOSTIF_CFG_PHACC_HIFRDYSEL_Msk (0x1UL) /*!< HIFRDYSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHACC_HIFBCCSEL_Pos (8UL) /*!< HIFBCCSEL (Bit 8) */ + #define R_PHOSTIF_CFG_PHACC_HIFBCCSEL_Msk (0x100UL) /*!< HIFBCCSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHACC_HIFBTCSEL_Pos (9UL) /*!< HIFBTCSEL (Bit 9) */ + #define R_PHOSTIF_CFG_PHACC_HIFBTCSEL_Msk (0x200UL) /*!< HIFBTCSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHACC_HIFPRCSEL_Pos (10UL) /*!< HIFPRCSEL (Bit 10) */ + #define R_PHOSTIF_CFG_PHACC_HIFPRCSEL_Msk (0x400UL) /*!< HIFPRCSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHACC_HIFIRCSEL_Pos (11UL) /*!< HIFIRCSEL (Bit 11) */ + #define R_PHOSTIF_CFG_PHACC_HIFIRCSEL_Msk (0x800UL) /*!< HIFIRCSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHACC_HIFXALSEL_Pos (12UL) /*!< HIFXALSEL (Bit 12) */ + #define R_PHOSTIF_CFG_PHACC_HIFXALSEL_Msk (0x1000UL) /*!< HIFXALSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHACC_HIFXAHSEL_Pos (13UL) /*!< HIFXAHSEL (Bit 13) */ + #define R_PHOSTIF_CFG_PHACC_HIFXAHSEL_Msk (0x2000UL) /*!< HIFXAHSEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHACC_HIFEXT0SEL_Pos (14UL) /*!< HIFEXT0SEL (Bit 14) */ + #define R_PHOSTIF_CFG_PHACC_HIFEXT0SEL_Msk (0x4000UL) /*!< HIFEXT0SEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHACC_HIFEXT1SEL_Pos (15UL) /*!< HIFEXT1SEL (Bit 15) */ + #define R_PHOSTIF_CFG_PHACC_HIFEXT1SEL_Msk (0x8000UL) /*!< HIFEXT1SEL (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHACC_CSSWAP_Pos (16UL) /*!< CSSWAP (Bit 16) */ + #define R_PHOSTIF_CFG_PHACC_CSSWAP_Msk (0x10000UL) /*!< CSSWAP (Bitfield-Mask: 0x01) */ + #define R_PHOSTIF_CFG_PHACC_BSCADMUX_Pos (17UL) /*!< BSCADMUX (Bit 17) */ + #define R_PHOSTIF_CFG_PHACC_BSCADMUX_Msk (0x20000UL) /*!< BSCADMUX (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_RWP_S ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= PRCRS ========================================================= */ + #define R_RWP_S_PRCRS_PRC0_Pos (0UL) /*!< PRC0 (Bit 0) */ + #define R_RWP_S_PRCRS_PRC0_Msk (0x1UL) /*!< PRC0 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRC1_Pos (1UL) /*!< PRC1 (Bit 1) */ + #define R_RWP_S_PRCRS_PRC1_Msk (0x2UL) /*!< PRC1 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRC2_Pos (2UL) /*!< PRC2 (Bit 2) */ + #define R_RWP_S_PRCRS_PRC2_Msk (0x4UL) /*!< PRC2 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRC3_Pos (3UL) /*!< PRC3 (Bit 3) */ + #define R_RWP_S_PRCRS_PRC3_Msk (0x8UL) /*!< PRC3 (Bitfield-Mask: 0x01) */ + #define R_RWP_S_PRCRS_PRKEY_Pos (8UL) /*!< PRKEY (Bit 8) */ + #define R_RWP_S_PRCRS_PRKEY_Msk (0xff00UL) /*!< PRKEY (Bitfield-Mask: 0xff) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TOERA ========================================================= */ + #define R_MTU_TOERA_OE3B_Pos (0UL) /*!< OE3B (Bit 0) */ + #define R_MTU_TOERA_OE3B_Msk (0x1UL) /*!< OE3B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4A_Pos (1UL) /*!< OE4A (Bit 1) */ + #define R_MTU_TOERA_OE4A_Msk (0x2UL) /*!< OE4A (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4B_Pos (2UL) /*!< OE4B (Bit 2) */ + #define R_MTU_TOERA_OE4B_Msk (0x4UL) /*!< OE4B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE3D_Pos (3UL) /*!< OE3D (Bit 3) */ + #define R_MTU_TOERA_OE3D_Msk (0x8UL) /*!< OE3D (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4C_Pos (4UL) /*!< OE4C (Bit 4) */ + #define R_MTU_TOERA_OE4C_Msk (0x10UL) /*!< OE4C (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERA_OE4D_Pos (5UL) /*!< OE4D (Bit 5) */ + #define R_MTU_TOERA_OE4D_Msk (0x20UL) /*!< OE4D (Bitfield-Mask: 0x01) */ +/* ========================================================= TGCRA ========================================================= */ + #define R_MTU_TGCRA_UF_Pos (0UL) /*!< UF (Bit 0) */ + #define R_MTU_TGCRA_UF_Msk (0x1UL) /*!< UF (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_VF_Pos (1UL) /*!< VF (Bit 1) */ + #define R_MTU_TGCRA_VF_Msk (0x2UL) /*!< VF (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_WF_Pos (2UL) /*!< WF (Bit 2) */ + #define R_MTU_TGCRA_WF_Msk (0x4UL) /*!< WF (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_FB_Pos (3UL) /*!< FB (Bit 3) */ + #define R_MTU_TGCRA_FB_Msk (0x8UL) /*!< FB (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_P_Pos (4UL) /*!< P (Bit 4) */ + #define R_MTU_TGCRA_P_Msk (0x10UL) /*!< P (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_N_Pos (5UL) /*!< N (Bit 5) */ + #define R_MTU_TGCRA_N_Msk (0x20UL) /*!< N (Bitfield-Mask: 0x01) */ + #define R_MTU_TGCRA_BDC_Pos (6UL) /*!< BDC (Bit 6) */ + #define R_MTU_TGCRA_BDC_Msk (0x40UL) /*!< BDC (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR1A ========================================================= */ + #define R_MTU_TOCR1A_OLSP_Pos (0UL) /*!< OLSP (Bit 0) */ + #define R_MTU_TOCR1A_OLSP_Msk (0x1UL) /*!< OLSP (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_OLSN_Pos (1UL) /*!< OLSN (Bit 1) */ + #define R_MTU_TOCR1A_OLSN_Msk (0x2UL) /*!< OLSN (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_TOCS_Pos (2UL) /*!< TOCS (Bit 2) */ + #define R_MTU_TOCR1A_TOCS_Msk (0x4UL) /*!< TOCS (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_TOCL_Pos (3UL) /*!< TOCL (Bit 3) */ + #define R_MTU_TOCR1A_TOCL_Msk (0x8UL) /*!< TOCL (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1A_PSYE_Pos (6UL) /*!< PSYE (Bit 6) */ + #define R_MTU_TOCR1A_PSYE_Msk (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR2A ========================================================= */ + #define R_MTU_TOCR2A_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOCR2A_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOCR2A_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOCR2A_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOCR2A_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOCR2A_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOCR2A_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2A_BF_Pos (6UL) /*!< BF (Bit 6) */ + #define R_MTU_TOCR2A_BF_Msk (0xc0UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ========================================================= TCDRA ========================================================= */ +/* ========================================================= TDDRA ========================================================= */ +/* ======================================================== TCNTSA ========================================================= */ +/* ========================================================= TCBRA ========================================================= */ +/* ======================================================== TITCR1A ======================================================== */ + #define R_MTU_TITCR1A_T4VCOR_Pos (0UL) /*!< T4VCOR (Bit 0) */ + #define R_MTU_TITCR1A_T4VCOR_Msk (0x7UL) /*!< T4VCOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1A_T4VEN_Pos (3UL) /*!< T4VEN (Bit 3) */ + #define R_MTU_TITCR1A_T4VEN_Msk (0x8UL) /*!< T4VEN (Bitfield-Mask: 0x01) */ + #define R_MTU_TITCR1A_T3ACOR_Pos (4UL) /*!< T3ACOR (Bit 4) */ + #define R_MTU_TITCR1A_T3ACOR_Msk (0x70UL) /*!< T3ACOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1A_T3AEN_Pos (7UL) /*!< T3AEN (Bit 7) */ + #define R_MTU_TITCR1A_T3AEN_Msk (0x80UL) /*!< T3AEN (Bitfield-Mask: 0x01) */ +/* ======================================================= TITCNT1A ======================================================== */ + #define R_MTU_TITCNT1A_T4VCNT_Pos (0UL) /*!< T4VCNT (Bit 0) */ + #define R_MTU_TITCNT1A_T4VCNT_Msk (0x7UL) /*!< T4VCNT (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCNT1A_T3ACNT_Pos (4UL) /*!< T3ACNT (Bit 4) */ + #define R_MTU_TITCNT1A_T3ACNT_Msk (0x70UL) /*!< T3ACNT (Bitfield-Mask: 0x07) */ +/* ======================================================== TBTERA ========================================================= */ + #define R_MTU_TBTERA_BTE_Pos (0UL) /*!< BTE (Bit 0) */ + #define R_MTU_TBTERA_BTE_Msk (0x3UL) /*!< BTE (Bitfield-Mask: 0x03) */ +/* ========================================================= TDERA ========================================================= */ + #define R_MTU_TDERA_TDER_Pos (0UL) /*!< TDER (Bit 0) */ + #define R_MTU_TDERA_TDER_Msk (0x1UL) /*!< TDER (Bitfield-Mask: 0x01) */ +/* ======================================================== TOLBRA ========================================================= */ + #define R_MTU_TOLBRA_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOLBRA_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOLBRA_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOLBRA_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOLBRA_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOLBRA_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRA_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOLBRA_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ +/* ======================================================== TITMRA ========================================================= */ + #define R_MTU_TITMRA_TITM_Pos (0UL) /*!< TITM (Bit 0) */ + #define R_MTU_TITMRA_TITM_Msk (0x1UL) /*!< TITM (Bitfield-Mask: 0x01) */ +/* ======================================================== TITCR2A ======================================================== */ + #define R_MTU_TITCR2A_TRG4COR_Pos (0UL) /*!< TRG4COR (Bit 0) */ + #define R_MTU_TITCR2A_TRG4COR_Msk (0x7UL) /*!< TRG4COR (Bitfield-Mask: 0x07) */ +/* ======================================================= TITCNT2A ======================================================== */ + #define R_MTU_TITCNT2A_TRG4CNT_Pos (0UL) /*!< TRG4CNT (Bit 0) */ + #define R_MTU_TITCNT2A_TRG4CNT_Msk (0x7UL) /*!< TRG4CNT (Bitfield-Mask: 0x07) */ +/* ========================================================= TWCRA ========================================================= */ + #define R_MTU_TWCRA_WRE_Pos (0UL) /*!< WRE (Bit 0) */ + #define R_MTU_TWCRA_WRE_Msk (0x1UL) /*!< WRE (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRA_SCC_Pos (1UL) /*!< SCC (Bit 1) */ + #define R_MTU_TWCRA_SCC_Msk (0x2UL) /*!< SCC (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRA_CCE_Pos (7UL) /*!< CCE (Bit 7) */ + #define R_MTU_TWCRA_CCE_Msk (0x80UL) /*!< CCE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMDR2A ========================================================= */ + #define R_MTU_TMDR2A_DRS_Pos (0UL) /*!< DRS (Bit 0) */ + #define R_MTU_TMDR2A_DRS_Msk (0x1UL) /*!< DRS (Bitfield-Mask: 0x01) */ +/* ========================================================= TSTRA ========================================================= */ + #define R_MTU_TSTRA_CST0_Pos (0UL) /*!< CST0 (Bit 0) */ + #define R_MTU_TSTRA_CST0_Msk (0x1UL) /*!< CST0 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST1_Pos (1UL) /*!< CST1 (Bit 1) */ + #define R_MTU_TSTRA_CST1_Msk (0x2UL) /*!< CST1 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST2_Pos (2UL) /*!< CST2 (Bit 2) */ + #define R_MTU_TSTRA_CST2_Msk (0x4UL) /*!< CST2 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST8_Pos (3UL) /*!< CST8 (Bit 3) */ + #define R_MTU_TSTRA_CST8_Msk (0x8UL) /*!< CST8 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST3_Pos (6UL) /*!< CST3 (Bit 6) */ + #define R_MTU_TSTRA_CST3_Msk (0x40UL) /*!< CST3 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRA_CST4_Pos (7UL) /*!< CST4 (Bit 7) */ + #define R_MTU_TSTRA_CST4_Msk (0x80UL) /*!< CST4 (Bitfield-Mask: 0x01) */ +/* ========================================================= TSYRA ========================================================= */ + #define R_MTU_TSYRA_SYNC0_Pos (0UL) /*!< SYNC0 (Bit 0) */ + #define R_MTU_TSYRA_SYNC0_Msk (0x1UL) /*!< SYNC0 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC1_Pos (1UL) /*!< SYNC1 (Bit 1) */ + #define R_MTU_TSYRA_SYNC1_Msk (0x2UL) /*!< SYNC1 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC2_Pos (2UL) /*!< SYNC2 (Bit 2) */ + #define R_MTU_TSYRA_SYNC2_Msk (0x4UL) /*!< SYNC2 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC3_Pos (6UL) /*!< SYNC3 (Bit 6) */ + #define R_MTU_TSYRA_SYNC3_Msk (0x40UL) /*!< SYNC3 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRA_SYNC4_Pos (7UL) /*!< SYNC4 (Bit 7) */ + #define R_MTU_TSYRA_SYNC4_Msk (0x80UL) /*!< SYNC4 (Bitfield-Mask: 0x01) */ +/* ======================================================== TCSYSTR ======================================================== */ + #define R_MTU_TCSYSTR_SCH7_Pos (0UL) /*!< SCH7 (Bit 0) */ + #define R_MTU_TCSYSTR_SCH7_Msk (0x1UL) /*!< SCH7 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH6_Pos (1UL) /*!< SCH6 (Bit 1) */ + #define R_MTU_TCSYSTR_SCH6_Msk (0x2UL) /*!< SCH6 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH4_Pos (3UL) /*!< SCH4 (Bit 3) */ + #define R_MTU_TCSYSTR_SCH4_Msk (0x8UL) /*!< SCH4 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH3_Pos (4UL) /*!< SCH3 (Bit 4) */ + #define R_MTU_TCSYSTR_SCH3_Msk (0x10UL) /*!< SCH3 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH2_Pos (5UL) /*!< SCH2 (Bit 5) */ + #define R_MTU_TCSYSTR_SCH2_Msk (0x20UL) /*!< SCH2 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH1_Pos (6UL) /*!< SCH1 (Bit 6) */ + #define R_MTU_TCSYSTR_SCH1_Msk (0x40UL) /*!< SCH1 (Bitfield-Mask: 0x01) */ + #define R_MTU_TCSYSTR_SCH0_Pos (7UL) /*!< SCH0 (Bit 7) */ + #define R_MTU_TCSYSTR_SCH0_Msk (0x80UL) /*!< SCH0 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRWERA ========================================================= */ + #define R_MTU_TRWERA_RWE_Pos (0UL) /*!< RWE (Bit 0) */ + #define R_MTU_TRWERA_RWE_Msk (0x1UL) /*!< RWE (Bitfield-Mask: 0x01) */ +/* ========================================================= TOERB ========================================================= */ + #define R_MTU_TOERB_OE6B_Pos (0UL) /*!< OE6B (Bit 0) */ + #define R_MTU_TOERB_OE6B_Msk (0x1UL) /*!< OE6B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7A_Pos (1UL) /*!< OE7A (Bit 1) */ + #define R_MTU_TOERB_OE7A_Msk (0x2UL) /*!< OE7A (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7B_Pos (2UL) /*!< OE7B (Bit 2) */ + #define R_MTU_TOERB_OE7B_Msk (0x4UL) /*!< OE7B (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE6D_Pos (3UL) /*!< OE6D (Bit 3) */ + #define R_MTU_TOERB_OE6D_Msk (0x8UL) /*!< OE6D (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7C_Pos (4UL) /*!< OE7C (Bit 4) */ + #define R_MTU_TOERB_OE7C_Msk (0x10UL) /*!< OE7C (Bitfield-Mask: 0x01) */ + #define R_MTU_TOERB_OE7D_Pos (5UL) /*!< OE7D (Bit 5) */ + #define R_MTU_TOERB_OE7D_Msk (0x20UL) /*!< OE7D (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR1B ========================================================= */ + #define R_MTU_TOCR1B_OLSP_Pos (0UL) /*!< OLSP (Bit 0) */ + #define R_MTU_TOCR1B_OLSP_Msk (0x1UL) /*!< OLSP (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_OLSN_Pos (1UL) /*!< OLSN (Bit 1) */ + #define R_MTU_TOCR1B_OLSN_Msk (0x2UL) /*!< OLSN (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_TOCS_Pos (2UL) /*!< TOCS (Bit 2) */ + #define R_MTU_TOCR1B_TOCS_Msk (0x4UL) /*!< TOCS (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_TOCL_Pos (3UL) /*!< TOCL (Bit 3) */ + #define R_MTU_TOCR1B_TOCL_Msk (0x8UL) /*!< TOCL (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR1B_PSYE_Pos (6UL) /*!< PSYE (Bit 6) */ + #define R_MTU_TOCR1B_PSYE_Msk (0x40UL) /*!< PSYE (Bitfield-Mask: 0x01) */ +/* ======================================================== TOCR2B ========================================================= */ + #define R_MTU_TOCR2B_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOCR2B_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOCR2B_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOCR2B_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOCR2B_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOCR2B_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOCR2B_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOCR2B_BF_Pos (6UL) /*!< BF (Bit 6) */ + #define R_MTU_TOCR2B_BF_Msk (0xc0UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ========================================================= TCDRB ========================================================= */ +/* ========================================================= TDDRB ========================================================= */ +/* ======================================================== TCNTSB ========================================================= */ +/* ========================================================= TCBRB ========================================================= */ +/* ======================================================== TITCR1B ======================================================== */ + #define R_MTU_TITCR1B_T7VCOR_Pos (0UL) /*!< T7VCOR (Bit 0) */ + #define R_MTU_TITCR1B_T7VCOR_Msk (0x7UL) /*!< T7VCOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1B_T7VEN_Pos (3UL) /*!< T7VEN (Bit 3) */ + #define R_MTU_TITCR1B_T7VEN_Msk (0x8UL) /*!< T7VEN (Bitfield-Mask: 0x01) */ + #define R_MTU_TITCR1B_T6ACOR_Pos (4UL) /*!< T6ACOR (Bit 4) */ + #define R_MTU_TITCR1B_T6ACOR_Msk (0x70UL) /*!< T6ACOR (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCR1B_T6AEN_Pos (7UL) /*!< T6AEN (Bit 7) */ + #define R_MTU_TITCR1B_T6AEN_Msk (0x80UL) /*!< T6AEN (Bitfield-Mask: 0x01) */ +/* ======================================================= TITCNT1B ======================================================== */ + #define R_MTU_TITCNT1B_T7VCNT_Pos (0UL) /*!< T7VCNT (Bit 0) */ + #define R_MTU_TITCNT1B_T7VCNT_Msk (0x7UL) /*!< T7VCNT (Bitfield-Mask: 0x07) */ + #define R_MTU_TITCNT1B_T6ACNT_Pos (4UL) /*!< T6ACNT (Bit 4) */ + #define R_MTU_TITCNT1B_T6ACNT_Msk (0x70UL) /*!< T6ACNT (Bitfield-Mask: 0x07) */ +/* ======================================================== TBTERB ========================================================= */ + #define R_MTU_TBTERB_BTE_Pos (0UL) /*!< BTE (Bit 0) */ + #define R_MTU_TBTERB_BTE_Msk (0x3UL) /*!< BTE (Bitfield-Mask: 0x03) */ +/* ========================================================= TDERB ========================================================= */ + #define R_MTU_TDERB_TDER_Pos (0UL) /*!< TDER (Bit 0) */ + #define R_MTU_TDERB_TDER_Msk (0x1UL) /*!< TDER (Bitfield-Mask: 0x01) */ +/* ======================================================== TOLBRB ========================================================= */ + #define R_MTU_TOLBRB_OLS1P_Pos (0UL) /*!< OLS1P (Bit 0) */ + #define R_MTU_TOLBRB_OLS1P_Msk (0x1UL) /*!< OLS1P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS1N_Pos (1UL) /*!< OLS1N (Bit 1) */ + #define R_MTU_TOLBRB_OLS1N_Msk (0x2UL) /*!< OLS1N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS2P_Pos (2UL) /*!< OLS2P (Bit 2) */ + #define R_MTU_TOLBRB_OLS2P_Msk (0x4UL) /*!< OLS2P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS2N_Pos (3UL) /*!< OLS2N (Bit 3) */ + #define R_MTU_TOLBRB_OLS2N_Msk (0x8UL) /*!< OLS2N (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS3P_Pos (4UL) /*!< OLS3P (Bit 4) */ + #define R_MTU_TOLBRB_OLS3P_Msk (0x10UL) /*!< OLS3P (Bitfield-Mask: 0x01) */ + #define R_MTU_TOLBRB_OLS3N_Pos (5UL) /*!< OLS3N (Bit 5) */ + #define R_MTU_TOLBRB_OLS3N_Msk (0x20UL) /*!< OLS3N (Bitfield-Mask: 0x01) */ +/* ======================================================== TITMRB ========================================================= */ + #define R_MTU_TITMRB_TITM_Pos (0UL) /*!< TITM (Bit 0) */ + #define R_MTU_TITMRB_TITM_Msk (0x1UL) /*!< TITM (Bitfield-Mask: 0x01) */ +/* ======================================================== TITCR2B ======================================================== */ + #define R_MTU_TITCR2B_TRG7COR_Pos (0UL) /*!< TRG7COR (Bit 0) */ + #define R_MTU_TITCR2B_TRG7COR_Msk (0x7UL) /*!< TRG7COR (Bitfield-Mask: 0x07) */ +/* ======================================================= TITCNT2B ======================================================== */ + #define R_MTU_TITCNT2B_TRG7CNT_Pos (0UL) /*!< TRG7CNT (Bit 0) */ + #define R_MTU_TITCNT2B_TRG7CNT_Msk (0x7UL) /*!< TRG7CNT (Bitfield-Mask: 0x07) */ +/* ========================================================= TWCRB ========================================================= */ + #define R_MTU_TWCRB_WRE_Pos (0UL) /*!< WRE (Bit 0) */ + #define R_MTU_TWCRB_WRE_Msk (0x1UL) /*!< WRE (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRB_SCC_Pos (1UL) /*!< SCC (Bit 1) */ + #define R_MTU_TWCRB_SCC_Msk (0x2UL) /*!< SCC (Bitfield-Mask: 0x01) */ + #define R_MTU_TWCRB_CCE_Pos (7UL) /*!< CCE (Bit 7) */ + #define R_MTU_TWCRB_CCE_Msk (0x80UL) /*!< CCE (Bitfield-Mask: 0x01) */ +/* ======================================================== TMDR2B ========================================================= */ + #define R_MTU_TMDR2B_DRS_Pos (0UL) /*!< DRS (Bit 0) */ + #define R_MTU_TMDR2B_DRS_Msk (0x1UL) /*!< DRS (Bitfield-Mask: 0x01) */ +/* ========================================================= TSTRB ========================================================= */ + #define R_MTU_TSTRB_CST6_Pos (6UL) /*!< CST6 (Bit 6) */ + #define R_MTU_TSTRB_CST6_Msk (0x40UL) /*!< CST6 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSTRB_CST7_Pos (7UL) /*!< CST7 (Bit 7) */ + #define R_MTU_TSTRB_CST7_Msk (0x80UL) /*!< CST7 (Bitfield-Mask: 0x01) */ +/* ========================================================= TSYRB ========================================================= */ + #define R_MTU_TSYRB_SYNC6_Pos (6UL) /*!< SYNC6 (Bit 6) */ + #define R_MTU_TSYRB_SYNC6_Msk (0x40UL) /*!< SYNC6 (Bitfield-Mask: 0x01) */ + #define R_MTU_TSYRB_SYNC7_Pos (7UL) /*!< SYNC7 (Bit 7) */ + #define R_MTU_TSYRB_SYNC7_Msk (0x80UL) /*!< SYNC7 (Bitfield-Mask: 0x01) */ +/* ======================================================== TRWERB ========================================================= */ + #define R_MTU_TRWERB_RWE_Pos (0UL) /*!< RWE (Bit 0) */ + #define R_MTU_TRWERB_RWE_Msk (0x1UL) /*!< RWE (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU3 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU3_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU3_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU3_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU3_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU3_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU3_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU3_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU3_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU3_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU3_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU3_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU3_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU3_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU3_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU3_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU3_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU3_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU3_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU3_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU3_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU3_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU3_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU3_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU3_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU3_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU3_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU3_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU3_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU3_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU3_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU3_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU3_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU3_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU3_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU3_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU3_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU3_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU3_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU3_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU3_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU3_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU3_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TGRE ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU4 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU4_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU4_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU4_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU4_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU4_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU4_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU4_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU4_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU4_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU4_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU4_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU4_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU4_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU4_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU4_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU4_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU4_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU4_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU4_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU4_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU4_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU4_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU4_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU4_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU4_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TTGE2_Pos (6UL) /*!< TTGE2 (Bit 6) */ + #define R_MTU4_TIER_TTGE2_Msk (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01) */ + #define R_MTU4_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU4_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU4_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU4_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU4_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU4_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU4_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU4_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU4_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU4_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU4_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU4_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU4_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU4_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU4_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TADCR ========================================================= */ + #define R_MTU4_TADCR_ITB4VE_Pos (0UL) /*!< ITB4VE (Bit 0) */ + #define R_MTU4_TADCR_ITB4VE_Msk (0x1UL) /*!< ITB4VE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_ITB3AE_Pos (1UL) /*!< ITB3AE (Bit 1) */ + #define R_MTU4_TADCR_ITB3AE_Msk (0x2UL) /*!< ITB3AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_ITA4VE_Pos (2UL) /*!< ITA4VE (Bit 2) */ + #define R_MTU4_TADCR_ITA4VE_Msk (0x4UL) /*!< ITA4VE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_ITA3AE_Pos (3UL) /*!< ITA3AE (Bit 3) */ + #define R_MTU4_TADCR_ITA3AE_Msk (0x8UL) /*!< ITA3AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_DT4BE_Pos (4UL) /*!< DT4BE (Bit 4) */ + #define R_MTU4_TADCR_DT4BE_Msk (0x10UL) /*!< DT4BE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_UT4BE_Pos (5UL) /*!< UT4BE (Bit 5) */ + #define R_MTU4_TADCR_UT4BE_Msk (0x20UL) /*!< UT4BE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_DT4AE_Pos (6UL) /*!< DT4AE (Bit 6) */ + #define R_MTU4_TADCR_DT4AE_Msk (0x40UL) /*!< DT4AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_UT4AE_Pos (7UL) /*!< UT4AE (Bit 7) */ + #define R_MTU4_TADCR_UT4AE_Msk (0x80UL) /*!< UT4AE (Bitfield-Mask: 0x01) */ + #define R_MTU4_TADCR_BF_Pos (14UL) /*!< BF (Bit 14) */ + #define R_MTU4_TADCR_BF_Msk (0xc000UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ======================================================== TADCORA ======================================================== */ +/* ======================================================== TADCORB ======================================================== */ +/* ======================================================= TADCOBRA ======================================================== */ +/* ======================================================= TADCOBRB ======================================================== */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU4_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU4_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TGRE ========================================================== */ +/* ========================================================= TGRF ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU_NF ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= NFCR0 ========================================================= */ + #define R_MTU_NF_NFCR0_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR0_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR0_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR0_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR0_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR0_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR0_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR1 ========================================================= */ + #define R_MTU_NF_NFCR1_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR1_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR1_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR1_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR1_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR1_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR2 ========================================================= */ + #define R_MTU_NF_NFCR2_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR2_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR2_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR2_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR2_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR2_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR3 ========================================================= */ + #define R_MTU_NF_NFCR3_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR3_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR3_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR3_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR3_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR3_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR3_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR4 ========================================================= */ + #define R_MTU_NF_NFCR4_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR4_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR4_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR4_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR4_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR4_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR4_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR8 ========================================================= */ + #define R_MTU_NF_NFCR8_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR8_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR8_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR8_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR8_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR8_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR8_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCRC ========================================================= */ + #define R_MTU_NF_NFCRC_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCRC_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCRC_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCRC_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCRC_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCRC_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCRC_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR6 ========================================================= */ + #define R_MTU_NF_NFCR6_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR6_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR6_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR6_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR6_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR6_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR6_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR7 ========================================================= */ + #define R_MTU_NF_NFCR7_NFAEN_Pos (0UL) /*!< NFAEN (Bit 0) */ + #define R_MTU_NF_NFCR7_NFAEN_Msk (0x1UL) /*!< NFAEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFBEN_Pos (1UL) /*!< NFBEN (Bit 1) */ + #define R_MTU_NF_NFCR7_NFBEN_Msk (0x2UL) /*!< NFBEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFCEN_Pos (2UL) /*!< NFCEN (Bit 2) */ + #define R_MTU_NF_NFCR7_NFCEN_Msk (0x4UL) /*!< NFCEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFDEN_Pos (3UL) /*!< NFDEN (Bit 3) */ + #define R_MTU_NF_NFCR7_NFDEN_Msk (0x8UL) /*!< NFDEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR7_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR7_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ========================================================= NFCR5 ========================================================= */ + #define R_MTU_NF_NFCR5_NFUEN_Pos (0UL) /*!< NFUEN (Bit 0) */ + #define R_MTU_NF_NFCR5_NFUEN_Msk (0x1UL) /*!< NFUEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR5_NFVEN_Pos (1UL) /*!< NFVEN (Bit 1) */ + #define R_MTU_NF_NFCR5_NFVEN_Msk (0x2UL) /*!< NFVEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR5_NFWEN_Pos (2UL) /*!< NFWEN (Bit 2) */ + #define R_MTU_NF_NFCR5_NFWEN_Msk (0x4UL) /*!< NFWEN (Bitfield-Mask: 0x01) */ + #define R_MTU_NF_NFCR5_NFCS_Pos (4UL) /*!< NFCS (Bit 4) */ + #define R_MTU_NF_NFCR5_NFCS_Msk (0x30UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU0 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU0_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU0_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU0_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU0_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU0_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU0_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU0_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU0_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU0_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU0_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU0_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU0_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ + #define R_MTU0_TMDR1_BFE_Pos (6UL) /*!< BFE (Bit 6) */ + #define R_MTU0_TMDR1_BFE_Msk (0x40UL) /*!< BFE (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU0_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU0_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU0_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU0_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU0_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU0_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU0_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU0_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU0_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU0_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU0_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU0_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU0_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU0_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU0_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================= TGRE ========================================================== */ +/* ========================================================= TGRF ========================================================== */ +/* ========================================================= TIER2 ========================================================= */ + #define R_MTU0_TIER2_TGIEE_Pos (0UL) /*!< TGIEE (Bit 0) */ + #define R_MTU0_TIER2_TGIEE_Msk (0x1UL) /*!< TGIEE (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER2_TGIEF_Pos (1UL) /*!< TGIEF (Bit 1) */ + #define R_MTU0_TIER2_TGIEF_Msk (0x2UL) /*!< TGIEF (Bitfield-Mask: 0x01) */ + #define R_MTU0_TIER2_TTGE2_Pos (7UL) /*!< TTGE2 (Bit 7) */ + #define R_MTU0_TIER2_TTGE2_Msk (0x80UL) /*!< TTGE2 (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU0_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU0_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU0_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU0_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ + #define R_MTU0_TBTM_TTSE_Pos (2UL) /*!< TTSE (Bit 2) */ + #define R_MTU0_TBTM_TTSE_Msk (0x4UL) /*!< TTSE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU0_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU0_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU1 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU1_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU1_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU1_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU1_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU1_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU1_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU1_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU1_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIOR ========================================================== */ + #define R_MTU1_TIOR_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU1_TIOR_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU1_TIOR_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU1_TIOR_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU1_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU1_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU1_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU1_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TCIEU_Pos (5UL) /*!< TCIEU (Bit 5) */ + #define R_MTU1_TIER_TCIEU_Msk (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01) */ + #define R_MTU1_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU1_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU1_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU1_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU1_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU1_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU1_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU1_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU1_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU1_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU1_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TICCR ========================================================= */ + #define R_MTU1_TICCR_I1AE_Pos (0UL) /*!< I1AE (Bit 0) */ + #define R_MTU1_TICCR_I1AE_Msk (0x1UL) /*!< I1AE (Bitfield-Mask: 0x01) */ + #define R_MTU1_TICCR_I1BE_Pos (1UL) /*!< I1BE (Bit 1) */ + #define R_MTU1_TICCR_I1BE_Msk (0x2UL) /*!< I1BE (Bitfield-Mask: 0x01) */ + #define R_MTU1_TICCR_I2AE_Pos (2UL) /*!< I2AE (Bit 2) */ + #define R_MTU1_TICCR_I2AE_Msk (0x4UL) /*!< I2AE (Bitfield-Mask: 0x01) */ + #define R_MTU1_TICCR_I2BE_Pos (3UL) /*!< I2BE (Bit 3) */ + #define R_MTU1_TICCR_I2BE_Msk (0x8UL) /*!< I2BE (Bitfield-Mask: 0x01) */ +/* ========================================================= TMDR3 ========================================================= */ + #define R_MTU1_TMDR3_LWA_Pos (0UL) /*!< LWA (Bit 0) */ + #define R_MTU1_TMDR3_LWA_Msk (0x1UL) /*!< LWA (Bitfield-Mask: 0x01) */ + #define R_MTU1_TMDR3_PHCKSEL_Pos (1UL) /*!< PHCKSEL (Bit 1) */ + #define R_MTU1_TMDR3_PHCKSEL_Msk (0x2UL) /*!< PHCKSEL (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU1_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU1_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU1_TCR2_PCB_Pos (3UL) /*!< PCB (Bit 3) */ + #define R_MTU1_TCR2_PCB_Msk (0x18UL) /*!< PCB (Bitfield-Mask: 0x03) */ +/* ======================================================== TCNTLW ========================================================= */ +/* ======================================================== TGRALW ========================================================= */ +/* ======================================================== TGRBLW ========================================================= */ + +/* =========================================================================================================================== */ +/* ================ R_MTU2 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU2_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU2_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU2_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU2_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU2_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU2_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU2_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU2_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIOR ========================================================== */ + #define R_MTU2_TIOR_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU2_TIOR_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU2_TIOR_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU2_TIOR_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU2_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU2_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU2_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU2_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TCIEU_Pos (5UL) /*!< TCIEU (Bit 5) */ + #define R_MTU2_TIER_TCIEU_Msk (0x20UL) /*!< TCIEU (Bitfield-Mask: 0x01) */ + #define R_MTU2_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU2_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU2_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU2_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU2_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU2_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU2_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU2_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU2_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU2_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU2_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU2_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU2_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU2_TCR2_PCB_Pos (3UL) /*!< PCB (Bit 3) */ + #define R_MTU2_TCR2_PCB_Msk (0x18UL) /*!< PCB (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_MTU8 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU8_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU8_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU8_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU8_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU8_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU8_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU8_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU8_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU8_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU8_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU8_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU8_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU8_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU8_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU8_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU8_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU8_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU8_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU8_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU8_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU8_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU8_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU8_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU8_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU8_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU8_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU8_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU8_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU8_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU6 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU6_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU6_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU6_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU6_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU6_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU6_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU6_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU6_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU6_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU6_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU6_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU6_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU6_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU6_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU6_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU6_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU6_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU6_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU6_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU6_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU6_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU6_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU6_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU6_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU6_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU6_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU6_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU6_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU6_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU6_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU6_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU6_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU6_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU6_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU6_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU6_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU6_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU6_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU6_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU6_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU6_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TSYCR ========================================================= */ + #define R_MTU6_TSYCR_CE2B_Pos (0UL) /*!< CE2B (Bit 0) */ + #define R_MTU6_TSYCR_CE2B_Msk (0x1UL) /*!< CE2B (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE2A_Pos (1UL) /*!< CE2A (Bit 1) */ + #define R_MTU6_TSYCR_CE2A_Msk (0x2UL) /*!< CE2A (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE1B_Pos (2UL) /*!< CE1B (Bit 2) */ + #define R_MTU6_TSYCR_CE1B_Msk (0x4UL) /*!< CE1B (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE1A_Pos (3UL) /*!< CE1A (Bit 3) */ + #define R_MTU6_TSYCR_CE1A_Msk (0x8UL) /*!< CE1A (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0D_Pos (4UL) /*!< CE0D (Bit 4) */ + #define R_MTU6_TSYCR_CE0D_Msk (0x10UL) /*!< CE0D (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0C_Pos (5UL) /*!< CE0C (Bit 5) */ + #define R_MTU6_TSYCR_CE0C_Msk (0x20UL) /*!< CE0C (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0B_Pos (6UL) /*!< CE0B (Bit 6) */ + #define R_MTU6_TSYCR_CE0B_Msk (0x40UL) /*!< CE0B (Bitfield-Mask: 0x01) */ + #define R_MTU6_TSYCR_CE0A_Pos (7UL) /*!< CE0A (Bit 7) */ + #define R_MTU6_TSYCR_CE0A_Msk (0x80UL) /*!< CE0A (Bitfield-Mask: 0x01) */ +/* ========================================================= TGRE ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU7 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== TCR ========================================================== */ + #define R_MTU7_TCR_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU7_TCR_TPSC_Msk (0x7UL) /*!< TPSC (Bitfield-Mask: 0x07) */ + #define R_MTU7_TCR_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU7_TCR_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ + #define R_MTU7_TCR_CCLR_Pos (5UL) /*!< CCLR (Bit 5) */ + #define R_MTU7_TCR_CCLR_Msk (0xe0UL) /*!< CCLR (Bitfield-Mask: 0x07) */ +/* ========================================================= TMDR1 ========================================================= */ + #define R_MTU7_TMDR1_MD_Pos (0UL) /*!< MD (Bit 0) */ + #define R_MTU7_TMDR1_MD_Msk (0xfUL) /*!< MD (Bitfield-Mask: 0x0f) */ + #define R_MTU7_TMDR1_BFA_Pos (4UL) /*!< BFA (Bit 4) */ + #define R_MTU7_TMDR1_BFA_Msk (0x10UL) /*!< BFA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TMDR1_BFB_Pos (5UL) /*!< BFB (Bit 5) */ + #define R_MTU7_TMDR1_BFB_Msk (0x20UL) /*!< BFB (Bitfield-Mask: 0x01) */ +/* ========================================================= TIORH ========================================================= */ + #define R_MTU7_TIORH_IOA_Pos (0UL) /*!< IOA (Bit 0) */ + #define R_MTU7_TIORH_IOA_Msk (0xfUL) /*!< IOA (Bitfield-Mask: 0x0f) */ + #define R_MTU7_TIORH_IOB_Pos (4UL) /*!< IOB (Bit 4) */ + #define R_MTU7_TIORH_IOB_Msk (0xf0UL) /*!< IOB (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIORL ========================================================= */ + #define R_MTU7_TIORL_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU7_TIORL_IOC_Msk (0xfUL) /*!< IOC (Bitfield-Mask: 0x0f) */ + #define R_MTU7_TIORL_IOD_Pos (4UL) /*!< IOD (Bit 4) */ + #define R_MTU7_TIORL_IOD_Msk (0xf0UL) /*!< IOD (Bitfield-Mask: 0x0f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU7_TIER_TGIEA_Pos (0UL) /*!< TGIEA (Bit 0) */ + #define R_MTU7_TIER_TGIEA_Msk (0x1UL) /*!< TGIEA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TGIEB_Pos (1UL) /*!< TGIEB (Bit 1) */ + #define R_MTU7_TIER_TGIEB_Msk (0x2UL) /*!< TGIEB (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TGIEC_Pos (2UL) /*!< TGIEC (Bit 2) */ + #define R_MTU7_TIER_TGIEC_Msk (0x4UL) /*!< TGIEC (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TGIED_Pos (3UL) /*!< TGIED (Bit 3) */ + #define R_MTU7_TIER_TGIED_Msk (0x8UL) /*!< TGIED (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TCIEV_Pos (4UL) /*!< TCIEV (Bit 4) */ + #define R_MTU7_TIER_TCIEV_Msk (0x10UL) /*!< TCIEV (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TTGE2_Pos (6UL) /*!< TTGE2 (Bit 6) */ + #define R_MTU7_TIER_TTGE2_Msk (0x40UL) /*!< TTGE2 (Bitfield-Mask: 0x01) */ + #define R_MTU7_TIER_TTGE_Pos (7UL) /*!< TTGE (Bit 7) */ + #define R_MTU7_TIER_TTGE_Msk (0x80UL) /*!< TTGE (Bitfield-Mask: 0x01) */ +/* ========================================================= TCNT ========================================================== */ +/* ========================================================= TGRA ========================================================== */ +/* ========================================================= TGRB ========================================================== */ +/* ========================================================= TGRC ========================================================== */ +/* ========================================================= TGRD ========================================================== */ +/* ========================================================== TSR ========================================================== */ + #define R_MTU7_TSR_TGFA_Pos (0UL) /*!< TGFA (Bit 0) */ + #define R_MTU7_TSR_TGFA_Msk (0x1UL) /*!< TGFA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TGFB_Pos (1UL) /*!< TGFB (Bit 1) */ + #define R_MTU7_TSR_TGFB_Msk (0x2UL) /*!< TGFB (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TGFC_Pos (2UL) /*!< TGFC (Bit 2) */ + #define R_MTU7_TSR_TGFC_Msk (0x4UL) /*!< TGFC (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TGFD_Pos (3UL) /*!< TGFD (Bit 3) */ + #define R_MTU7_TSR_TGFD_Msk (0x8UL) /*!< TGFD (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TCFV_Pos (4UL) /*!< TCFV (Bit 4) */ + #define R_MTU7_TSR_TCFV_Msk (0x10UL) /*!< TCFV (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TCFU_Pos (5UL) /*!< TCFU (Bit 5) */ + #define R_MTU7_TSR_TCFU_Msk (0x20UL) /*!< TCFU (Bitfield-Mask: 0x01) */ + #define R_MTU7_TSR_TCFD_Pos (7UL) /*!< TCFD (Bit 7) */ + #define R_MTU7_TSR_TCFD_Msk (0x80UL) /*!< TCFD (Bitfield-Mask: 0x01) */ +/* ========================================================= TBTM ========================================================== */ + #define R_MTU7_TBTM_TTSA_Pos (0UL) /*!< TTSA (Bit 0) */ + #define R_MTU7_TBTM_TTSA_Msk (0x1UL) /*!< TTSA (Bitfield-Mask: 0x01) */ + #define R_MTU7_TBTM_TTSB_Pos (1UL) /*!< TTSB (Bit 1) */ + #define R_MTU7_TBTM_TTSB_Msk (0x2UL) /*!< TTSB (Bitfield-Mask: 0x01) */ +/* ========================================================= TADCR ========================================================= */ + #define R_MTU7_TADCR_ITB7VE_Pos (0UL) /*!< ITB7VE (Bit 0) */ + #define R_MTU7_TADCR_ITB7VE_Msk (0x1UL) /*!< ITB7VE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_ITB6AE_Pos (1UL) /*!< ITB6AE (Bit 1) */ + #define R_MTU7_TADCR_ITB6AE_Msk (0x2UL) /*!< ITB6AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_ITA7VE_Pos (2UL) /*!< ITA7VE (Bit 2) */ + #define R_MTU7_TADCR_ITA7VE_Msk (0x4UL) /*!< ITA7VE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_ITA6AE_Pos (3UL) /*!< ITA6AE (Bit 3) */ + #define R_MTU7_TADCR_ITA6AE_Msk (0x8UL) /*!< ITA6AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_DT7BE_Pos (4UL) /*!< DT7BE (Bit 4) */ + #define R_MTU7_TADCR_DT7BE_Msk (0x10UL) /*!< DT7BE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_UT7BE_Pos (5UL) /*!< UT7BE (Bit 5) */ + #define R_MTU7_TADCR_UT7BE_Msk (0x20UL) /*!< UT7BE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_DT7AE_Pos (6UL) /*!< DT7AE (Bit 6) */ + #define R_MTU7_TADCR_DT7AE_Msk (0x40UL) /*!< DT7AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_UT7AE_Pos (7UL) /*!< UT7AE (Bit 7) */ + #define R_MTU7_TADCR_UT7AE_Msk (0x80UL) /*!< UT7AE (Bitfield-Mask: 0x01) */ + #define R_MTU7_TADCR_BF_Pos (14UL) /*!< BF (Bit 14) */ + #define R_MTU7_TADCR_BF_Msk (0xc000UL) /*!< BF (Bitfield-Mask: 0x03) */ +/* ======================================================== TADCORA ======================================================== */ +/* ======================================================== TADCORB ======================================================== */ +/* ======================================================= TADCOBRA ======================================================== */ +/* ======================================================= TADCOBRB ======================================================== */ +/* ========================================================= TCR2 ========================================================== */ + #define R_MTU7_TCR2_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU7_TCR2_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ +/* ========================================================= TGRE ========================================================== */ +/* ========================================================= TGRF ========================================================== */ + +/* =========================================================================================================================== */ +/* ================ R_MTU5 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= TCNTU ========================================================= */ +/* ========================================================= TGRU ========================================================== */ +/* ========================================================= TCRU ========================================================== */ + #define R_MTU5_TCRU_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU5_TCRU_TPSC_Msk (0x3UL) /*!< TPSC (Bitfield-Mask: 0x03) */ +/* ========================================================= TCR2U ========================================================= */ + #define R_MTU5_TCR2U_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU5_TCR2U_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU5_TCR2U_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU5_TCR2U_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ +/* ========================================================= TIORU ========================================================= */ + #define R_MTU5_TIORU_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU5_TIORU_IOC_Msk (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f) */ +/* ========================================================= TCNTV ========================================================= */ +/* ========================================================= TGRV ========================================================== */ +/* ========================================================= TCRV ========================================================== */ + #define R_MTU5_TCRV_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU5_TCRV_TPSC_Msk (0x3UL) /*!< TPSC (Bitfield-Mask: 0x03) */ +/* ========================================================= TCR2V ========================================================= */ + #define R_MTU5_TCR2V_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU5_TCR2V_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU5_TCR2V_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU5_TCR2V_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ +/* ========================================================= TIORV ========================================================= */ + #define R_MTU5_TIORV_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU5_TIORV_IOC_Msk (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f) */ +/* ========================================================= TCNTW ========================================================= */ +/* ========================================================= TGRW ========================================================== */ +/* ========================================================= TCRW ========================================================== */ + #define R_MTU5_TCRW_TPSC_Pos (0UL) /*!< TPSC (Bit 0) */ + #define R_MTU5_TCRW_TPSC_Msk (0x3UL) /*!< TPSC (Bitfield-Mask: 0x03) */ +/* ========================================================= TCR2W ========================================================= */ + #define R_MTU5_TCR2W_TPSC2_Pos (0UL) /*!< TPSC2 (Bit 0) */ + #define R_MTU5_TCR2W_TPSC2_Msk (0x7UL) /*!< TPSC2 (Bitfield-Mask: 0x07) */ + #define R_MTU5_TCR2W_CKEG_Pos (3UL) /*!< CKEG (Bit 3) */ + #define R_MTU5_TCR2W_CKEG_Msk (0x18UL) /*!< CKEG (Bitfield-Mask: 0x03) */ +/* ========================================================= TIORW ========================================================= */ + #define R_MTU5_TIORW_IOC_Pos (0UL) /*!< IOC (Bit 0) */ + #define R_MTU5_TIORW_IOC_Msk (0x1fUL) /*!< IOC (Bitfield-Mask: 0x1f) */ +/* ========================================================= TIER ========================================================== */ + #define R_MTU5_TIER_TGIE5W_Pos (0UL) /*!< TGIE5W (Bit 0) */ + #define R_MTU5_TIER_TGIE5W_Msk (0x1UL) /*!< TGIE5W (Bitfield-Mask: 0x01) */ + #define R_MTU5_TIER_TGIE5V_Pos (1UL) /*!< TGIE5V (Bit 1) */ + #define R_MTU5_TIER_TGIE5V_Msk (0x2UL) /*!< TGIE5V (Bitfield-Mask: 0x01) */ + #define R_MTU5_TIER_TGIE5U_Pos (2UL) /*!< TGIE5U (Bit 2) */ + #define R_MTU5_TIER_TGIE5U_Msk (0x4UL) /*!< TGIE5U (Bitfield-Mask: 0x01) */ +/* ========================================================= TSTR ========================================================== */ + #define R_MTU5_TSTR_CSTW5_Pos (0UL) /*!< CSTW5 (Bit 0) */ + #define R_MTU5_TSTR_CSTW5_Msk (0x1UL) /*!< CSTW5 (Bitfield-Mask: 0x01) */ + #define R_MTU5_TSTR_CSTV5_Pos (1UL) /*!< CSTV5 (Bit 1) */ + #define R_MTU5_TSTR_CSTV5_Msk (0x2UL) /*!< CSTV5 (Bitfield-Mask: 0x01) */ + #define R_MTU5_TSTR_CSTU5_Pos (2UL) /*!< CSTU5 (Bit 2) */ + #define R_MTU5_TSTR_CSTU5_Msk (0x4UL) /*!< CSTU5 (Bitfield-Mask: 0x01) */ +/* ====================================================== TCNTCMPCLR ======================================================= */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Pos (0UL) /*!< CMPCLR5W (Bit 0) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5W_Msk (0x1UL) /*!< CMPCLR5W (Bitfield-Mask: 0x01) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Pos (1UL) /*!< CMPCLR5V (Bit 1) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5V_Msk (0x2UL) /*!< CMPCLR5V (Bitfield-Mask: 0x01) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Pos (2UL) /*!< CMPCLR5U (Bit 2) */ + #define R_MTU5_TCNTCMPCLR_CMPCLR5U_Msk (0x4UL) /*!< CMPCLR5U (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_TFU ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TRGSTS ========================================================= */ + #define R_TFU_TRGSTS_BSYF_Pos (0UL) /*!< BSYF (Bit 0) */ + #define R_TFU_TRGSTS_BSYF_Msk (0x1UL) /*!< BSYF (Bitfield-Mask: 0x01) */ + #define R_TFU_TRGSTS_ERRF_Pos (1UL) /*!< ERRF (Bit 1) */ + #define R_TFU_TRGSTS_ERRF_Msk (0x2UL) /*!< ERRF (Bitfield-Mask: 0x01) */ +/* ========================================================= SCDT0 ========================================================= */ + #define R_TFU_SCDT0_SCDT0_Pos (0UL) /*!< SCDT0 (Bit 0) */ + #define R_TFU_SCDT0_SCDT0_Msk (0xffffffffUL) /*!< SCDT0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= SCDT1 ========================================================= */ + #define R_TFU_SCDT1_SCDT1_Pos (0UL) /*!< SCDT1 (Bit 0) */ + #define R_TFU_SCDT1_SCDT1_Msk (0xffffffffUL) /*!< SCDT1 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ATDT0 ========================================================= */ + #define R_TFU_ATDT0_ATDT0_Pos (0UL) /*!< ATDT0 (Bit 0) */ + #define R_TFU_ATDT0_ATDT0_Msk (0xffffffffUL) /*!< ATDT0 (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ATDT1 ========================================================= */ + #define R_TFU_ATDT1_ATDT1_Pos (0UL) /*!< ATDT1 (Bit 0) */ + #define R_TFU_ATDT1_ATDT1_Msk (0xffffffffUL) /*!< ATDT1 (Bitfield-Mask: 0xffffffff) */ + +/* =========================================================================================================================== */ +/* ================ R_POE3 ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= ICSR1 ========================================================= */ + #define R_POE3_ICSR1_POE0M_Pos (0UL) /*!< POE0M (Bit 0) */ + #define R_POE3_ICSR1_POE0M_Msk (0x3UL) /*!< POE0M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR1_PIE1_Pos (8UL) /*!< PIE1 (Bit 8) */ + #define R_POE3_ICSR1_PIE1_Msk (0x100UL) /*!< PIE1 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR1_POE0F_Pos (12UL) /*!< POE0F (Bit 12) */ + #define R_POE3_ICSR1_POE0F_Msk (0x1000UL) /*!< POE0F (Bitfield-Mask: 0x01) */ +/* ========================================================= OCSR1 ========================================================= */ + #define R_POE3_OCSR1_OIE1_Pos (8UL) /*!< OIE1 (Bit 8) */ + #define R_POE3_OCSR1_OIE1_Msk (0x100UL) /*!< OIE1 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR1_OCE1_Pos (9UL) /*!< OCE1 (Bit 9) */ + #define R_POE3_OCSR1_OCE1_Msk (0x200UL) /*!< OCE1 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR1_OSF1_Pos (15UL) /*!< OSF1 (Bit 15) */ + #define R_POE3_OCSR1_OSF1_Msk (0x8000UL) /*!< OSF1 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR2 ========================================================= */ + #define R_POE3_ICSR2_POE4M_Pos (0UL) /*!< POE4M (Bit 0) */ + #define R_POE3_ICSR2_POE4M_Msk (0x3UL) /*!< POE4M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR2_PIE2_Pos (8UL) /*!< PIE2 (Bit 8) */ + #define R_POE3_ICSR2_PIE2_Msk (0x100UL) /*!< PIE2 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR2_POE4F_Pos (12UL) /*!< POE4F (Bit 12) */ + #define R_POE3_ICSR2_POE4F_Msk (0x1000UL) /*!< POE4F (Bitfield-Mask: 0x01) */ +/* ========================================================= OCSR2 ========================================================= */ + #define R_POE3_OCSR2_OIE2_Pos (8UL) /*!< OIE2 (Bit 8) */ + #define R_POE3_OCSR2_OIE2_Msk (0x100UL) /*!< OIE2 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR2_OCE2_Pos (9UL) /*!< OCE2 (Bit 9) */ + #define R_POE3_OCSR2_OCE2_Msk (0x200UL) /*!< OCE2 (Bitfield-Mask: 0x01) */ + #define R_POE3_OCSR2_OSF2_Pos (15UL) /*!< OSF2 (Bit 15) */ + #define R_POE3_OCSR2_OSF2_Msk (0x8000UL) /*!< OSF2 (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR3 ========================================================= */ + #define R_POE3_ICSR3_POE8M_Pos (0UL) /*!< POE8M (Bit 0) */ + #define R_POE3_ICSR3_POE8M_Msk (0x3UL) /*!< POE8M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR3_PIE3_Pos (8UL) /*!< PIE3 (Bit 8) */ + #define R_POE3_ICSR3_PIE3_Msk (0x100UL) /*!< PIE3 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR3_POE8E_Pos (9UL) /*!< POE8E (Bit 9) */ + #define R_POE3_ICSR3_POE8E_Msk (0x200UL) /*!< POE8E (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR3_POE8F_Pos (12UL) /*!< POE8F (Bit 12) */ + #define R_POE3_ICSR3_POE8F_Msk (0x1000UL) /*!< POE8F (Bitfield-Mask: 0x01) */ +/* ========================================================= SPOER ========================================================= */ + #define R_POE3_SPOER_MTUCH34HIZ_Pos (0UL) /*!< MTUCH34HIZ (Bit 0) */ + #define R_POE3_SPOER_MTUCH34HIZ_Msk (0x1UL) /*!< MTUCH34HIZ (Bitfield-Mask: 0x01) */ + #define R_POE3_SPOER_MTUCH67HIZ_Pos (1UL) /*!< MTUCH67HIZ (Bit 1) */ + #define R_POE3_SPOER_MTUCH67HIZ_Msk (0x2UL) /*!< MTUCH67HIZ (Bitfield-Mask: 0x01) */ + #define R_POE3_SPOER_MTUCH0HIZ_Pos (2UL) /*!< MTUCH0HIZ (Bit 2) */ + #define R_POE3_SPOER_MTUCH0HIZ_Msk (0x4UL) /*!< MTUCH0HIZ (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR1 ========================================================= */ + #define R_POE3_POECR1_MTU0AZE_Pos (0UL) /*!< MTU0AZE (Bit 0) */ + #define R_POE3_POECR1_MTU0AZE_Msk (0x1UL) /*!< MTU0AZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR1_MTU0BZE_Pos (1UL) /*!< MTU0BZE (Bit 1) */ + #define R_POE3_POECR1_MTU0BZE_Msk (0x2UL) /*!< MTU0BZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR1_MTU0CZE_Pos (2UL) /*!< MTU0CZE (Bit 2) */ + #define R_POE3_POECR1_MTU0CZE_Msk (0x4UL) /*!< MTU0CZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR1_MTU0DZE_Pos (3UL) /*!< MTU0DZE (Bit 3) */ + #define R_POE3_POECR1_MTU0DZE_Msk (0x8UL) /*!< MTU0DZE (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR2 ========================================================= */ + #define R_POE3_POECR2_MTU7BDZE_Pos (0UL) /*!< MTU7BDZE (Bit 0) */ + #define R_POE3_POECR2_MTU7BDZE_Msk (0x1UL) /*!< MTU7BDZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU7ACZE_Pos (1UL) /*!< MTU7ACZE (Bit 1) */ + #define R_POE3_POECR2_MTU7ACZE_Msk (0x2UL) /*!< MTU7ACZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU6BDZE_Pos (2UL) /*!< MTU6BDZE (Bit 2) */ + #define R_POE3_POECR2_MTU6BDZE_Msk (0x4UL) /*!< MTU6BDZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU4BDZE_Pos (8UL) /*!< MTU4BDZE (Bit 8) */ + #define R_POE3_POECR2_MTU4BDZE_Msk (0x100UL) /*!< MTU4BDZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU4ACZE_Pos (9UL) /*!< MTU4ACZE (Bit 9) */ + #define R_POE3_POECR2_MTU4ACZE_Msk (0x200UL) /*!< MTU4ACZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR2_MTU3BDZE_Pos (10UL) /*!< MTU3BDZE (Bit 10) */ + #define R_POE3_POECR2_MTU3BDZE_Msk (0x400UL) /*!< MTU3BDZE (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR4 ========================================================= */ + #define R_POE3_POECR4_IC2ADDMT34ZE_Pos (2UL) /*!< IC2ADDMT34ZE (Bit 2) */ + #define R_POE3_POECR4_IC2ADDMT34ZE_Msk (0x4UL) /*!< IC2ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC3ADDMT34ZE_Pos (3UL) /*!< IC3ADDMT34ZE (Bit 3) */ + #define R_POE3_POECR4_IC3ADDMT34ZE_Msk (0x8UL) /*!< IC3ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC4ADDMT34ZE_Pos (4UL) /*!< IC4ADDMT34ZE (Bit 4) */ + #define R_POE3_POECR4_IC4ADDMT34ZE_Msk (0x10UL) /*!< IC4ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC5ADDMT34ZE_Pos (5UL) /*!< IC5ADDMT34ZE (Bit 5) */ + #define R_POE3_POECR4_IC5ADDMT34ZE_Msk (0x20UL) /*!< IC5ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_DE0ADDMT34ZE_Pos (6UL) /*!< DE0ADDMT34ZE (Bit 6) */ + #define R_POE3_POECR4_DE0ADDMT34ZE_Msk (0x40UL) /*!< DE0ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_DE1ADDMT34ZE_Pos (7UL) /*!< DE1ADDMT34ZE (Bit 7) */ + #define R_POE3_POECR4_DE1ADDMT34ZE_Msk (0x80UL) /*!< DE1ADDMT34ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC1ADDMT67ZE_Pos (9UL) /*!< IC1ADDMT67ZE (Bit 9) */ + #define R_POE3_POECR4_IC1ADDMT67ZE_Msk (0x200UL) /*!< IC1ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC3ADDMT67ZE_Pos (11UL) /*!< IC3ADDMT67ZE (Bit 11) */ + #define R_POE3_POECR4_IC3ADDMT67ZE_Msk (0x800UL) /*!< IC3ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC4ADDMT67ZE_Pos (12UL) /*!< IC4ADDMT67ZE (Bit 12) */ + #define R_POE3_POECR4_IC4ADDMT67ZE_Msk (0x1000UL) /*!< IC4ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_IC5ADDMT67ZE_Pos (13UL) /*!< IC5ADDMT67ZE (Bit 13) */ + #define R_POE3_POECR4_IC5ADDMT67ZE_Msk (0x2000UL) /*!< IC5ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_DE0ADDMT67ZE_Pos (14UL) /*!< DE0ADDMT67ZE (Bit 14) */ + #define R_POE3_POECR4_DE0ADDMT67ZE_Msk (0x4000UL) /*!< DE0ADDMT67ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR4_DE1ADDMT67ZE_Pos (15UL) /*!< DE1ADDMT67ZE (Bit 15) */ + #define R_POE3_POECR4_DE1ADDMT67ZE_Msk (0x8000UL) /*!< DE1ADDMT67ZE (Bitfield-Mask: 0x01) */ +/* ======================================================== POECR5 ========================================================= */ + #define R_POE3_POECR5_IC1ADDMT0ZE_Pos (1UL) /*!< IC1ADDMT0ZE (Bit 1) */ + #define R_POE3_POECR5_IC1ADDMT0ZE_Msk (0x2UL) /*!< IC1ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_IC2ADDMT0ZE_Pos (2UL) /*!< IC2ADDMT0ZE (Bit 2) */ + #define R_POE3_POECR5_IC2ADDMT0ZE_Msk (0x4UL) /*!< IC2ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_IC4ADDMT0ZE_Pos (4UL) /*!< IC4ADDMT0ZE (Bit 4) */ + #define R_POE3_POECR5_IC4ADDMT0ZE_Msk (0x10UL) /*!< IC4ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_IC5ADDMT0ZE_Pos (5UL) /*!< IC5ADDMT0ZE (Bit 5) */ + #define R_POE3_POECR5_IC5ADDMT0ZE_Msk (0x20UL) /*!< IC5ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_DE0ADDMT0ZE_Pos (6UL) /*!< DE0ADDMT0ZE (Bit 6) */ + #define R_POE3_POECR5_DE0ADDMT0ZE_Msk (0x40UL) /*!< DE0ADDMT0ZE (Bitfield-Mask: 0x01) */ + #define R_POE3_POECR5_DE1ADDMT0ZE_Pos (7UL) /*!< DE1ADDMT0ZE (Bit 7) */ + #define R_POE3_POECR5_DE1ADDMT0ZE_Msk (0x80UL) /*!< DE1ADDMT0ZE (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR4 ========================================================= */ + #define R_POE3_ICSR4_POE10M_Pos (0UL) /*!< POE10M (Bit 0) */ + #define R_POE3_ICSR4_POE10M_Msk (0x3UL) /*!< POE10M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR4_PIE4_Pos (8UL) /*!< PIE4 (Bit 8) */ + #define R_POE3_ICSR4_PIE4_Msk (0x100UL) /*!< PIE4 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR4_POE10E_Pos (9UL) /*!< POE10E (Bit 9) */ + #define R_POE3_ICSR4_POE10E_Msk (0x200UL) /*!< POE10E (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR4_POE10F_Pos (12UL) /*!< POE10F (Bit 12) */ + #define R_POE3_ICSR4_POE10F_Msk (0x1000UL) /*!< POE10F (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR5 ========================================================= */ + #define R_POE3_ICSR5_POE11M_Pos (0UL) /*!< POE11M (Bit 0) */ + #define R_POE3_ICSR5_POE11M_Msk (0x3UL) /*!< POE11M (Bitfield-Mask: 0x03) */ + #define R_POE3_ICSR5_PIE5_Pos (8UL) /*!< PIE5 (Bit 8) */ + #define R_POE3_ICSR5_PIE5_Msk (0x100UL) /*!< PIE5 (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR5_POE11E_Pos (9UL) /*!< POE11E (Bit 9) */ + #define R_POE3_ICSR5_POE11E_Msk (0x200UL) /*!< POE11E (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR5_POE11F_Pos (12UL) /*!< POE11F (Bit 12) */ + #define R_POE3_ICSR5_POE11F_Msk (0x1000UL) /*!< POE11F (Bitfield-Mask: 0x01) */ +/* ========================================================= ALR1 ========================================================== */ + #define R_POE3_ALR1_OLSG0A_Pos (0UL) /*!< OLSG0A (Bit 0) */ + #define R_POE3_ALR1_OLSG0A_Msk (0x1UL) /*!< OLSG0A (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG0B_Pos (1UL) /*!< OLSG0B (Bit 1) */ + #define R_POE3_ALR1_OLSG0B_Msk (0x2UL) /*!< OLSG0B (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG1A_Pos (2UL) /*!< OLSG1A (Bit 2) */ + #define R_POE3_ALR1_OLSG1A_Msk (0x4UL) /*!< OLSG1A (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG1B_Pos (3UL) /*!< OLSG1B (Bit 3) */ + #define R_POE3_ALR1_OLSG1B_Msk (0x8UL) /*!< OLSG1B (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG2A_Pos (4UL) /*!< OLSG2A (Bit 4) */ + #define R_POE3_ALR1_OLSG2A_Msk (0x10UL) /*!< OLSG2A (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSG2B_Pos (5UL) /*!< OLSG2B (Bit 5) */ + #define R_POE3_ALR1_OLSG2B_Msk (0x20UL) /*!< OLSG2B (Bitfield-Mask: 0x01) */ + #define R_POE3_ALR1_OLSEN_Pos (7UL) /*!< OLSEN (Bit 7) */ + #define R_POE3_ALR1_OLSEN_Msk (0x80UL) /*!< OLSEN (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR6 ========================================================= */ + #define R_POE3_ICSR6_OSTSTE_Pos (9UL) /*!< OSTSTE (Bit 9) */ + #define R_POE3_ICSR6_OSTSTE_Msk (0x200UL) /*!< OSTSTE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR6_OSTSTF_Pos (12UL) /*!< OSTSTF (Bit 12) */ + #define R_POE3_ICSR6_OSTSTF_Msk (0x1000UL) /*!< OSTSTF (Bitfield-Mask: 0x01) */ +/* ========================================================= ICSR7 ========================================================= */ + #define R_POE3_ICSR7_DERR0IE_Pos (6UL) /*!< DERR0IE (Bit 6) */ + #define R_POE3_ICSR7_DERR0IE_Msk (0x40UL) /*!< DERR0IE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_DERR1IE_Pos (7UL) /*!< DERR1IE (Bit 7) */ + #define R_POE3_ICSR7_DERR1IE_Msk (0x80UL) /*!< DERR1IE (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_DERR0ST_Pos (13UL) /*!< DERR0ST (Bit 13) */ + #define R_POE3_ICSR7_DERR0ST_Msk (0x2000UL) /*!< DERR0ST (Bitfield-Mask: 0x01) */ + #define R_POE3_ICSR7_DERR1ST_Pos (14UL) /*!< DERR1ST (Bit 14) */ + #define R_POE3_ICSR7_DERR1ST_Msk (0x4000UL) /*!< DERR1ST (Bitfield-Mask: 0x01) */ +/* ======================================================== M0SELR1 ======================================================== */ + #define R_POE3_M0SELR1_M0ASEL_Pos (0UL) /*!< M0ASEL (Bit 0) */ + #define R_POE3_M0SELR1_M0ASEL_Msk (0xfUL) /*!< M0ASEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M0SELR1_M0BSEL_Pos (4UL) /*!< M0BSEL (Bit 4) */ + #define R_POE3_M0SELR1_M0BSEL_Msk (0xf0UL) /*!< M0BSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M0SELR2 ======================================================== */ + #define R_POE3_M0SELR2_M0CSEL_Pos (0UL) /*!< M0CSEL (Bit 0) */ + #define R_POE3_M0SELR2_M0CSEL_Msk (0xfUL) /*!< M0CSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M0SELR2_M0DSEL_Pos (4UL) /*!< M0DSEL (Bit 4) */ + #define R_POE3_M0SELR2_M0DSEL_Msk (0xf0UL) /*!< M0DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M3SELR ========================================================= */ + #define R_POE3_M3SELR_M3BSEL_Pos (0UL) /*!< M3BSEL (Bit 0) */ + #define R_POE3_M3SELR_M3BSEL_Msk (0xfUL) /*!< M3BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M3SELR_M3DSEL_Pos (4UL) /*!< M3DSEL (Bit 4) */ + #define R_POE3_M3SELR_M3DSEL_Msk (0xf0UL) /*!< M3DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M4SELR1 ======================================================== */ + #define R_POE3_M4SELR1_M4ASEL_Pos (0UL) /*!< M4ASEL (Bit 0) */ + #define R_POE3_M4SELR1_M4ASEL_Msk (0xfUL) /*!< M4ASEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M4SELR1_M4CSEL_Pos (4UL) /*!< M4CSEL (Bit 4) */ + #define R_POE3_M4SELR1_M4CSEL_Msk (0xf0UL) /*!< M4CSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M4SELR2 ======================================================== */ + #define R_POE3_M4SELR2_M4BSEL_Pos (0UL) /*!< M4BSEL (Bit 0) */ + #define R_POE3_M4SELR2_M4BSEL_Msk (0xfUL) /*!< M4BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M4SELR2_M4DSEL_Pos (4UL) /*!< M4DSEL (Bit 4) */ + #define R_POE3_M4SELR2_M4DSEL_Msk (0xf0UL) /*!< M4DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M6SELR ========================================================= */ + #define R_POE3_M6SELR_M6BSEL_Pos (0UL) /*!< M6BSEL (Bit 0) */ + #define R_POE3_M6SELR_M6BSEL_Msk (0xfUL) /*!< M6BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M6SELR_M6DSEL_Pos (4UL) /*!< M6DSEL (Bit 4) */ + #define R_POE3_M6SELR_M6DSEL_Msk (0xf0UL) /*!< M6DSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M7SELR1 ======================================================== */ + #define R_POE3_M7SELR1_M7ASEL_Pos (0UL) /*!< M7ASEL (Bit 0) */ + #define R_POE3_M7SELR1_M7ASEL_Msk (0xfUL) /*!< M7ASEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M7SELR1_M7CSEL_Pos (4UL) /*!< M7CSEL (Bit 4) */ + #define R_POE3_M7SELR1_M7CSEL_Msk (0xf0UL) /*!< M7CSEL (Bitfield-Mask: 0x0f) */ +/* ======================================================== M7SELR2 ======================================================== */ + #define R_POE3_M7SELR2_M7BSEL_Pos (0UL) /*!< M7BSEL (Bit 0) */ + #define R_POE3_M7SELR2_M7BSEL_Msk (0xfUL) /*!< M7BSEL (Bitfield-Mask: 0x0f) */ + #define R_POE3_M7SELR2_M7DSEL_Pos (4UL) /*!< M7DSEL (Bit 4) */ + #define R_POE3_M7SELR2_M7DSEL_Msk (0xf0UL) /*!< M7DSEL (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ R_POEG0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== POEG0GA ======================================================== */ + #define R_POEG0_POEG0GA_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GA_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GA_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GA_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GA_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GA_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GA_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GA_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GA_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_DERR0ST_Pos (24UL) /*!< DERR0ST (Bit 24) */ + #define R_POEG0_POEG0GA_DERR0ST_Msk (0x1000000UL) /*!< DERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_DERR1ST_Pos (25UL) /*!< DERR1ST (Bit 25) */ + #define R_POEG0_POEG0GA_DERR1ST_Msk (0x2000000UL) /*!< DERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_DERR0E_Pos (26UL) /*!< DERR0E (Bit 26) */ + #define R_POEG0_POEG0GA_DERR0E_Msk (0x4000000UL) /*!< DERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_DERR1E_Pos (27UL) /*!< DERR1E (Bit 27) */ + #define R_POEG0_POEG0GA_DERR1E_Msk (0x8000000UL) /*!< DERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GA_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GA_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GA_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GA_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG0GB ======================================================== */ + #define R_POEG0_POEG0GB_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GB_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GB_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GB_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GB_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GB_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GB_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GB_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GB_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_DERR0ST_Pos (24UL) /*!< DERR0ST (Bit 24) */ + #define R_POEG0_POEG0GB_DERR0ST_Msk (0x1000000UL) /*!< DERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_DERR1ST_Pos (25UL) /*!< DERR1ST (Bit 25) */ + #define R_POEG0_POEG0GB_DERR1ST_Msk (0x2000000UL) /*!< DERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_DERR0E_Pos (26UL) /*!< DERR0E (Bit 26) */ + #define R_POEG0_POEG0GB_DERR0E_Msk (0x4000000UL) /*!< DERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_DERR1E_Pos (27UL) /*!< DERR1E (Bit 27) */ + #define R_POEG0_POEG0GB_DERR1E_Msk (0x8000000UL) /*!< DERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GB_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GB_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GB_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GB_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG0GC ======================================================== */ + #define R_POEG0_POEG0GC_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GC_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GC_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GC_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GC_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GC_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GC_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GC_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GC_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_DERR0ST_Pos (24UL) /*!< DERR0ST (Bit 24) */ + #define R_POEG0_POEG0GC_DERR0ST_Msk (0x1000000UL) /*!< DERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_DERR1ST_Pos (25UL) /*!< DERR1ST (Bit 25) */ + #define R_POEG0_POEG0GC_DERR1ST_Msk (0x2000000UL) /*!< DERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_DERR0E_Pos (26UL) /*!< DERR0E (Bit 26) */ + #define R_POEG0_POEG0GC_DERR0E_Msk (0x4000000UL) /*!< DERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_DERR1E_Pos (27UL) /*!< DERR1E (Bit 27) */ + #define R_POEG0_POEG0GC_DERR1E_Msk (0x8000000UL) /*!< DERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GC_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GC_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GC_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GC_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ +/* ======================================================== POEG0GD ======================================================== */ + #define R_POEG0_POEG0GD_PIDF_Pos (0UL) /*!< PIDF (Bit 0) */ + #define R_POEG0_POEG0GD_PIDF_Msk (0x1UL) /*!< PIDF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_IOCF_Pos (1UL) /*!< IOCF (Bit 1) */ + #define R_POEG0_POEG0GD_IOCF_Msk (0x2UL) /*!< IOCF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_OSTPF_Pos (2UL) /*!< OSTPF (Bit 2) */ + #define R_POEG0_POEG0GD_OSTPF_Msk (0x4UL) /*!< OSTPF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_SSF_Pos (3UL) /*!< SSF (Bit 3) */ + #define R_POEG0_POEG0GD_SSF_Msk (0x8UL) /*!< SSF (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_PIDE_Pos (4UL) /*!< PIDE (Bit 4) */ + #define R_POEG0_POEG0GD_PIDE_Msk (0x10UL) /*!< PIDE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_IOCE_Pos (5UL) /*!< IOCE (Bit 5) */ + #define R_POEG0_POEG0GD_IOCE_Msk (0x20UL) /*!< IOCE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_OSTPE_Pos (6UL) /*!< OSTPE (Bit 6) */ + #define R_POEG0_POEG0GD_OSTPE_Msk (0x40UL) /*!< OSTPE (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_ST_Pos (16UL) /*!< ST (Bit 16) */ + #define R_POEG0_POEG0GD_ST_Msk (0x10000UL) /*!< ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_DERR0ST_Pos (24UL) /*!< DERR0ST (Bit 24) */ + #define R_POEG0_POEG0GD_DERR0ST_Msk (0x1000000UL) /*!< DERR0ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_DERR1ST_Pos (25UL) /*!< DERR1ST (Bit 25) */ + #define R_POEG0_POEG0GD_DERR1ST_Msk (0x2000000UL) /*!< DERR1ST (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_DERR0E_Pos (26UL) /*!< DERR0E (Bit 26) */ + #define R_POEG0_POEG0GD_DERR0E_Msk (0x4000000UL) /*!< DERR0E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_DERR1E_Pos (27UL) /*!< DERR1E (Bit 27) */ + #define R_POEG0_POEG0GD_DERR1E_Msk (0x8000000UL) /*!< DERR1E (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_INV_Pos (28UL) /*!< INV (Bit 28) */ + #define R_POEG0_POEG0GD_INV_Msk (0x10000000UL) /*!< INV (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_NFEN_Pos (29UL) /*!< NFEN (Bit 29) */ + #define R_POEG0_POEG0GD_NFEN_Msk (0x20000000UL) /*!< NFEN (Bitfield-Mask: 0x01) */ + #define R_POEG0_POEG0GD_NFCS_Pos (30UL) /*!< NFCS (Bit 30) */ + #define R_POEG0_POEG0GD_NFCS_Msk (0xc0000000UL) /*!< NFCS (Bitfield-Mask: 0x03) */ + +/* =========================================================================================================================== */ +/* ================ R_DSMIF0 ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== DSSEICR ======================================================== */ + #define R_DSMIF0_DSSEICR_ISEL_Pos (0UL) /*!< ISEL (Bit 0) */ + #define R_DSMIF0_DSSEICR_ISEL_Msk (0x1UL) /*!< ISEL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSSEICR_ISEH_Pos (1UL) /*!< ISEH (Bit 1) */ + #define R_DSMIF0_DSSEICR_ISEH_Msk (0x2UL) /*!< ISEH (Bitfield-Mask: 0x01) */ +/* ======================================================== DSSECSR ======================================================== */ + #define R_DSMIF0_DSSECSR_SEDM_Pos (0UL) /*!< SEDM (Bit 0) */ + #define R_DSMIF0_DSSECSR_SEDM_Msk (0x7UL) /*!< SEDM (Bitfield-Mask: 0x07) */ +/* ======================================================== DSSELTR ======================================================== */ + #define R_DSMIF0_DSSELTR_SCMPTBL_Pos (0UL) /*!< SCMPTBL (Bit 0) */ + #define R_DSMIF0_DSSELTR_SCMPTBL_Msk (0x3ffffUL) /*!< SCMPTBL (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== DSSEHTR ======================================================== */ + #define R_DSMIF0_DSSEHTR_SCMPTBH_Pos (0UL) /*!< SCMPTBH (Bit 0) */ + #define R_DSMIF0_DSSEHTR_SCMPTBH_Msk (0x3ffffUL) /*!< SCMPTBH (Bitfield-Mask: 0x3ffff) */ +/* ======================================================== DSSECR ========================================================= */ + #define R_DSMIF0_DSSECR_SEEL_Pos (0UL) /*!< SEEL (Bit 0) */ + #define R_DSMIF0_DSSECR_SEEL_Msk (0x1UL) /*!< SEEL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSSECR_SEEH_Pos (1UL) /*!< SEEH (Bit 1) */ + #define R_DSMIF0_DSSECR_SEEH_Msk (0x2UL) /*!< SEEH (Bitfield-Mask: 0x01) */ +/* ======================================================== DSSECDR ======================================================== */ + #define R_DSMIF0_DSSECDR_SECDR_Pos (0UL) /*!< SECDR (Bit 0) */ + #define R_DSMIF0_DSSECDR_SECDR_Msk (0xffffUL) /*!< SECDR (Bitfield-Mask: 0xffff) */ +/* ======================================================= DSCSTRTR ======================================================== */ + #define R_DSMIF0_DSCSTRTR_STRTRG0_Pos (0UL) /*!< STRTRG0 (Bit 0) */ + #define R_DSMIF0_DSCSTRTR_STRTRG0_Msk (0x1UL) /*!< STRTRG0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTRTR_STRTRG1_Pos (1UL) /*!< STRTRG1 (Bit 1) */ + #define R_DSMIF0_DSCSTRTR_STRTRG1_Msk (0x2UL) /*!< STRTRG1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTRTR_STRTRG2_Pos (2UL) /*!< STRTRG2 (Bit 2) */ + #define R_DSMIF0_DSCSTRTR_STRTRG2_Msk (0x4UL) /*!< STRTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================= DSCSTPTR ======================================================== */ + #define R_DSMIF0_DSCSTPTR_STPTRG0_Pos (0UL) /*!< STPTRG0 (Bit 0) */ + #define R_DSMIF0_DSCSTPTR_STPTRG0_Msk (0x1UL) /*!< STPTRG0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTPTR_STPTRG1_Pos (1UL) /*!< STPTRG1 (Bit 1) */ + #define R_DSMIF0_DSCSTPTR_STPTRG1_Msk (0x2UL) /*!< STPTRG1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSTPTR_STPTRG2_Pos (2UL) /*!< STPTRG2 (Bit 2) */ + #define R_DSMIF0_DSCSTPTR_STPTRG2_Msk (0x4UL) /*!< STPTRG2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCESR ========================================================= */ + #define R_DSMIF0_DSCESR_OCFL0_Pos (0UL) /*!< OCFL0 (Bit 0) */ + #define R_DSMIF0_DSCESR_OCFL0_Msk (0x1UL) /*!< OCFL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_OCFL1_Pos (1UL) /*!< OCFL1 (Bit 1) */ + #define R_DSMIF0_DSCESR_OCFL1_Msk (0x2UL) /*!< OCFL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_OCFL2_Pos (2UL) /*!< OCFL2 (Bit 2) */ + #define R_DSMIF0_DSCESR_OCFL2_Msk (0x4UL) /*!< OCFL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_OCFH0_Pos (4UL) /*!< OCFH0 (Bit 4) */ + #define R_DSMIF0_DSCESR_OCFH0_Msk (0x10UL) /*!< OCFH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_OCFH1_Pos (5UL) /*!< OCFH1 (Bit 5) */ + #define R_DSMIF0_DSCESR_OCFH1_Msk (0x20UL) /*!< OCFH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_OCFH2_Pos (6UL) /*!< OCFH2 (Bit 6) */ + #define R_DSMIF0_DSCESR_OCFH2_Msk (0x40UL) /*!< OCFH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SCF0_Pos (8UL) /*!< SCF0 (Bit 8) */ + #define R_DSMIF0_DSCESR_SCF0_Msk (0x100UL) /*!< SCF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SCF1_Pos (9UL) /*!< SCF1 (Bit 9) */ + #define R_DSMIF0_DSCESR_SCF1_Msk (0x200UL) /*!< SCF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SCF2_Pos (10UL) /*!< SCF2 (Bit 10) */ + #define R_DSMIF0_DSCESR_SCF2_Msk (0x400UL) /*!< SCF2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SUMERRL_Pos (16UL) /*!< SUMERRL (Bit 16) */ + #define R_DSMIF0_DSCESR_SUMERRL_Msk (0x10000UL) /*!< SUMERRL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESR_SUMERRH_Pos (17UL) /*!< SUMERRH (Bit 17) */ + #define R_DSMIF0_DSCESR_SUMERRH_Msk (0x20000UL) /*!< SUMERRH (Bitfield-Mask: 0x01) */ +/* ========================================================= DSCSR ========================================================= */ + #define R_DSMIF0_DSCSR_DUF0_Pos (0UL) /*!< DUF0 (Bit 0) */ + #define R_DSMIF0_DSCSR_DUF0_Msk (0x1UL) /*!< DUF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_DUF1_Pos (1UL) /*!< DUF1 (Bit 1) */ + #define R_DSMIF0_DSCSR_DUF1_Msk (0x2UL) /*!< DUF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSR_DUF2_Pos (2UL) /*!< DUF2 (Bit 2) */ + #define R_DSMIF0_DSCSR_DUF2_Msk (0x4UL) /*!< DUF2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCSSR ========================================================= */ + #define R_DSMIF0_DSCSSR_CHSTATE0_Pos (0UL) /*!< CHSTATE0 (Bit 0) */ + #define R_DSMIF0_DSCSSR_CHSTATE0_Msk (0x1UL) /*!< CHSTATE0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSSR_CHSTATE1_Pos (4UL) /*!< CHSTATE1 (Bit 4) */ + #define R_DSMIF0_DSCSSR_CHSTATE1_Msk (0x10UL) /*!< CHSTATE1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSSR_CHSTATE2_Pos (8UL) /*!< CHSTATE2 (Bit 8) */ + #define R_DSMIF0_DSCSSR_CHSTATE2_Msk (0x100UL) /*!< CHSTATE2 (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCESCR ======================================================== */ + #define R_DSMIF0_DSCESCR_CLROCFL0_Pos (0UL) /*!< CLROCFL0 (Bit 0) */ + #define R_DSMIF0_DSCESCR_CLROCFL0_Msk (0x1UL) /*!< CLROCFL0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLROCFL1_Pos (1UL) /*!< CLROCFL1 (Bit 1) */ + #define R_DSMIF0_DSCESCR_CLROCFL1_Msk (0x2UL) /*!< CLROCFL1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLROCFL2_Pos (2UL) /*!< CLROCFL2 (Bit 2) */ + #define R_DSMIF0_DSCESCR_CLROCFL2_Msk (0x4UL) /*!< CLROCFL2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLROCFH0_Pos (4UL) /*!< CLROCFH0 (Bit 4) */ + #define R_DSMIF0_DSCESCR_CLROCFH0_Msk (0x10UL) /*!< CLROCFH0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLROCFH1_Pos (5UL) /*!< CLROCFH1 (Bit 5) */ + #define R_DSMIF0_DSCESCR_CLROCFH1_Msk (0x20UL) /*!< CLROCFH1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLROCFH2_Pos (6UL) /*!< CLROCFH2 (Bit 6) */ + #define R_DSMIF0_DSCESCR_CLROCFH2_Msk (0x40UL) /*!< CLROCFH2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSCF0_Pos (8UL) /*!< CLRSCF0 (Bit 8) */ + #define R_DSMIF0_DSCESCR_CLRSCF0_Msk (0x100UL) /*!< CLRSCF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSCF1_Pos (9UL) /*!< CLRSCF1 (Bit 9) */ + #define R_DSMIF0_DSCESCR_CLRSCF1_Msk (0x200UL) /*!< CLRSCF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSCF2_Pos (10UL) /*!< CLRSCF2 (Bit 10) */ + #define R_DSMIF0_DSCESCR_CLRSCF2_Msk (0x400UL) /*!< CLRSCF2 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRL_Pos (16UL) /*!< CLRSUMERRL (Bit 16) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRL_Msk (0x10000UL) /*!< CLRSUMERRL (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRH_Pos (17UL) /*!< CLRSUMERRH (Bit 17) */ + #define R_DSMIF0_DSCESCR_CLRSUMERRH_Msk (0x20000UL) /*!< CLRSUMERRH (Bitfield-Mask: 0x01) */ +/* ======================================================== DSCSCR ========================================================= */ + #define R_DSMIF0_DSCSCR_CLRDUF0_Pos (0UL) /*!< CLRDUF0 (Bit 0) */ + #define R_DSMIF0_DSCSCR_CLRDUF0_Msk (0x1UL) /*!< CLRDUF0 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRDUF1_Pos (1UL) /*!< CLRDUF1 (Bit 1) */ + #define R_DSMIF0_DSCSCR_CLRDUF1_Msk (0x2UL) /*!< CLRDUF1 (Bitfield-Mask: 0x01) */ + #define R_DSMIF0_DSCSCR_CLRDUF2_Pos (2UL) /*!< CLRDUF2 (Bit 2) */ + #define R_DSMIF0_DSCSCR_CLRDUF2_Msk (0x4UL) /*!< CLRDUF2 (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ R_GSC ================ */ +/* =========================================================================================================================== */ + +/* ========================================================= CNTCR ========================================================= */ + #define R_GSC_CNTCR_EN_Pos (0UL) /*!< EN (Bit 0) */ + #define R_GSC_CNTCR_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ + #define R_GSC_CNTCR_HDBG_Pos (1UL) /*!< HDBG (Bit 1) */ + #define R_GSC_CNTCR_HDBG_Msk (0x2UL) /*!< HDBG (Bitfield-Mask: 0x01) */ +/* ========================================================= CNTSR ========================================================= */ + #define R_GSC_CNTSR_DBGH_Pos (1UL) /*!< DBGH (Bit 1) */ + #define R_GSC_CNTSR_DBGH_Msk (0x2UL) /*!< DBGH (Bitfield-Mask: 0x01) */ +/* ======================================================== CNTCVL ========================================================= */ + #define R_GSC_CNTCVL_CNTCVL_L_32_Pos (0UL) /*!< CNTCVL_L_32 (Bit 0) */ + #define R_GSC_CNTCVL_CNTCVL_L_32_Msk (0xffffffffUL) /*!< CNTCVL_L_32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CNTCVU ========================================================= */ + #define R_GSC_CNTCVU_CNTCVU_U_32_Pos (0UL) /*!< CNTCVU_U_32 (Bit 0) */ + #define R_GSC_CNTCVU_CNTCVU_U_32_Msk (0xffffffffUL) /*!< CNTCVU_U_32 (Bitfield-Mask: 0xffffffff) */ +/* ======================================================== CNTFID0 ======================================================== */ + #define R_GSC_CNTFID0_FREQ_Pos (0UL) /*!< FREQ (Bit 0) */ + #define R_GSC_CNTFID0_FREQ_Msk (0xffffffffUL) /*!< FREQ (Bitfield-Mask: 0xffffffff) */ + +/** @} */ /* End of group PosMask_peripherals */ + + #ifdef __cplusplus +} + #endif + +#endif /* R9A07G084_H */ + +/** @} */ /* End of group R9A07G084 */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h new file mode 100644 index 00000000000..5e369f1b4ee --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h @@ -0,0 +1,131 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/* Ensure Renesas MCU variation definitions are included to ensure MCU + * specific register variations are handled correctly. */ +#ifndef BSP_FEATURE_H + #error "INTERNAL ERROR: bsp_feature.h must be included before renesas.h." +#endif + +/** @addtogroup Renesas Electronics Corporation + * @{ + */ + +/** @addtogroup RZN2 + * @{ + */ + +#ifndef RZN2_H + #define RZN2_H + + #ifdef __cplusplus +extern "C" { + #endif + +/* Define compiler macros for CPU architecture, used in CMSIS 5. */ + #if defined(__ICCARM__) + #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ + +/* Macros already defined */ + #else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ + #endif + +/* Alternative core deduction for older ICCARM's */ + #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8R__) && (__CORE__ == __ARM8R__) + #define __ARM_ARCH_8R__ 1 + #else + #error "Unknown target." + #endif + #endif + #endif + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ +/* IRQn_Type is generated as part of an FSP project. It can be found in vector_data.h. */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + + #if __ARM_ARCH_7EM__ + #define RENESAS_CORTEX_M4 + #elif __ARM_ARCH_6M__ + #define RENESAS_CORTEX_M0PLUS + #elif __ARM_ARCH_8M_BASE__ + #define RENESAS_CORTEX_M23 + #elif __ARM_ARCH_8M_MAIN__ + #define RENESAS_CORTEX_M33 + #elif __ARM_ARCH_8R__ + #define RENESAS_CORTEX_R52 + #else + #warning Unsupported Architecture + #endif + + #if BSP_MCU_GROUP_RZN2L + #include "R9A07G084.h" + #else + #warning Unsupported MCU + #endif + + #ifdef __cplusplus +} + #endif + +#endif /* RZN2_H */ + +/** @} */ /* End of group RZN2 */ + +/** @} */ /* End of group Renesas Electronics Corporation */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h new file mode 100644 index 00000000000..2fafe6c0f68 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h @@ -0,0 +1,58 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef SYSTEM_RENESAS_ARM_H + #define SYSTEM_RENESAS_ARM_H + + #ifdef __cplusplus +extern "C" { + #endif + + #include + +extern uint32_t SystemCoreClock; /** System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + + #ifdef __cplusplus +} + #endif + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c new file mode 100644 index 00000000000..3347ca1d085 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c @@ -0,0 +1,364 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_HACTLR_BIT_L (0xB783) /* HACTLR EL1 access enable(0b1011 0111 1000 0011) */ +#define BSP_HCR_HCD_DISABLE (0x20000000) /* HCR.HCD = 1 : HVC disable */ +#define BSP_MODE_MASK (0x1F) /* Bit mask for mode bits in CPSR */ +#define BSP_SVC_MODE (0x13) /* Supervisor mode */ + +#if defined(__ICCARM__) + #define BSP_IRQ_STACK_END_ADDRESS __section_end(".irq_stack") + #define BSP_FIQ_STACK_END_ADDRESS __section_end(".fiq_stack") + #define BSP_SVC_STACK_END_ADDRESS __section_end(".svc_stack") + #define BSP_ABORT_STACK_END_ADDRESS __section_end(".abt_stack") + #define BSP_UNDEFINED_STACK_END_ADDRESS __section_end(".und_stack") + #define BSP_SYSTEM_STACK_END_ADDRESS __section_end(".sys_stack") + +#elif defined(__GNUC__) + #define BSP_IRQ_STACK_END_ADDRESS &__IrqStackLimit + #define BSP_FIQ_STACK_END_ADDRESS &__FiqStackLimit + #define BSP_SVC_STACK_END_ADDRESS &__SvcStackLimit + #define BSP_ABORT_STACK_END_ADDRESS &__AbtStackLimit + #define BSP_UNDEFINED_STACK_END_ADDRESS &__UndStackLimit + #define BSP_SYSTEM_STACK_END_ADDRESS &__SysStackLimit + +#endif + +#define BSP_IMP_BTCMREGIONR_MASK_L (0x1FFC) /* Masked out BASEADDRESS and ENABLEELx bits(L) */ +#define BSP_IMP_BTCMREGIONR_ENABLEEL_L (0x0003) /* Set base address and enable EL2, EL1, EL0 access(L) */ +#define BSP_IMP_BTCMREGIONR_ENABLEEL_H (0x0010) /* Set base address and enable EL2, EL1, EL0 access(H) */ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #pragma section=".irq_stack" + #pragma section=".fiq_stack" + #pragma section=".svc_stack" + #pragma section=".abt_stack" + #pragma section=".und_stack" + #pragma section=".sys_stack" + +#elif defined(__GNUC__) +extern void * __IrqStackLimit; +extern void * __FiqStackLimit; +extern void * __SvcStackLimit; +extern void * __AbtStackLimit; +extern void * __UndStackLimit; +extern void * __SysStackLimit; + +#endif + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if __FPU_USED +extern void bsp_fpu_advancedsimd_init(void); + +#endif + +extern void bsp_slavetcm_enable(void); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +int32_t main(void); + +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void system_init(void) BSP_PLACE_IN_SECTION(".loader_text"); +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void stack_init(void); +BSP_TARGET_ARM void fpu_slavetcm_init(void); + +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void __Vectors(void) BSP_PLACE_IN_SECTION(".intvec"); +__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void IRQ_Handler(void); +__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void Reset_Handler(void) BSP_PLACE_IN_SECTION(".reset_handler"); + +void Default_Handler(void); + +/* Stacks */ +BSP_DONT_REMOVE static uint8_t g_fiq_stack[BSP_CFG_STACK_FIQ_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_FIQ_STACK); +BSP_DONT_REMOVE static uint8_t g_irq_stack[BSP_CFG_STACK_IRQ_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_IRQ_STACK); +BSP_DONT_REMOVE static uint8_t g_abt_stack[BSP_CFG_STACK_ABT_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_ABT_STACK); +BSP_DONT_REMOVE static uint8_t g_und_stack[BSP_CFG_STACK_UND_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_UND_STACK); +BSP_DONT_REMOVE static uint8_t g_sys_stack[BSP_CFG_STACK_SYS_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_SYS_STACK); +BSP_DONT_REMOVE static uint8_t g_svc_stack[BSP_CFG_STACK_SVC_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) +BSP_PLACE_IN_SECTION(BSP_SECTION_SVC_STACK); + +/* Heap */ +#if (BSP_CFG_HEAP_BYTES > 0) + +BSP_DONT_REMOVE static uint8_t g_heap[BSP_CFG_HEAP_BYTES] BSP_ALIGN_VARIABLE(BSP_STACK_ALIGNMENT) \ + BSP_PLACE_IN_SECTION(BSP_SECTION_HEAP); +#endif + +#if defined(__GNUC__) +BSP_DONT_REMOVE static const void * g_bsp_dummy BSP_PLACE_IN_SECTION(".dummy"); + + #if BSP_CFG_RAM_EXECUTION +BSP_DONT_REMOVE static const void * g_bsp_loader_dummy BSP_PLACE_IN_SECTION(".loader_dummy"); + + #endif +#endif + +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void __Vectors (void) +{ + __asm volatile ( + " LDR pc,=Reset_Handler \n" + " LDR pc,=Undefined_Handler \n" + " LDR pc,=SVC_Handler \n" + " LDR pc,=Prefetch_Handler \n" + " LDR pc,=Abort_Handler \n" + " LDR pc,=Reserved_Handler \n" + " LDR pc,=IRQ_Handler \n" + " LDR pc,=FIQ_Handler \n" + ::: "memory"); +} + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Default exception handler. + **********************************************************************************************************************/ +void Default_Handler (void) +{ + /** A error has occurred. The user will need to investigate the cause. Common problems are stack corruption + * or use of an invalid pointer. Use the Fault Status window in e2 studio or manually check the fault status + * registers for more information. + */ + BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(0); +} + +/*******************************************************************************************************************//** + * After boot processing, LSI starts executing here. + **********************************************************************************************************************/ +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void system_init (void) +{ + __asm volatile ( + "set_hactlr: \n" + " MOVW r0, %[bsp_hactlr_bit_l] \n" /* Set HACTLR bits(L) */ + " MOVT r0, #0 \n" + " MCR p15, #4, r0, c1, c0, #1 \n" /* Write r0 to HACTLR */ + ::[bsp_hactlr_bit_l] "i" (BSP_HACTLR_BIT_L) : "memory"); + + __asm volatile ( + "set_hcr: \n" + " MRC p15, #4, r1, c1, c1, #0 \n" /* Read Hyp Configuration Register */ + " ORR r1, r1, %[bsp_hcr_hcd_disable] \n" /* HVC instruction disable */ + " MCR p15, #4, r1, c1, c1, #0 \n" /* Write Hyp Configuration Register */ + ::[bsp_hcr_hcd_disable] "i" (BSP_HCR_HCD_DISABLE) : "memory"); + + __asm volatile ( + "set_vbar: \n" + " LDR r0, =__Vectors \n" + " MCR p15, #0, r0, c12, c0, #0 \n" /* Write r0 to VBAR */ + ::: "memory"); + + __asm volatile ( + "LLPP_access_enable: \n" + + /* Enable PERIPHPREGIONR (LLPP) */ + " MRC p15, #0, r1, c15, c0,#0 \n" /* PERIPHPREGIONR */ + " ORR r1, r1, #(0x1 << 1) \n" /* Enable PERIPHPREGIONR EL2 */ + " ORR r1, r1, #(0x1) \n" /* Enable PERIPHPREGIONR EL1 and EL0 */ + " DSB \n" /* Ensuring memory access complete */ + " MCR p15, #0, r1, c15, c0,#0 \n" /* PERIPHREGIONR */ + " ISB \n" /* Ensuring Context-changing */ + ::: "memory"); + + __asm volatile ( + "cpsr_save: \n" + " MRS r0, CPSR \n" /* Original PSR value */ + " BIC r0, r0, %[bsp_mode_mask] \n" /* Clear the mode bits */ + " ORR r0, r0, %[bsp_svc_mode] \n" /* Set SVC mode bits */ + " MSR SPSR_hyp, r0 \n" + ::[bsp_mode_mask] "i" (BSP_MODE_MASK), [bsp_svc_mode] "i" (BSP_SVC_MODE) : "memory"); + + __asm volatile ( + "exception_return: \n" + " LDR r1, =stack_init \n" + " MSR ELR_hyp, r1 \n" + " ERET \n" /* Branch to stack_init and enter EL1 */ + ::: "memory"); +} + +/** @} (end addtogroup BSP_MCU) */ + +#if defined(__ICCARM__) + #define BSP_SYSTEMINIT_B_INSTRUCTION SystemInit(); + + #define WEAK_REF_ATTRIBUTE + + #pragma weak Undefined_Handler = Default_Handler + #pragma weak SVC_Handler = Default_Handler + #pragma weak Prefetch_Handler = Default_Handler + #pragma weak Abort_Handler = Default_Handler + #pragma weak Reserved_Handler = Default_Handler + #pragma weak FIQ_Handler = Default_Handler +#elif defined(__GNUC__) + + #define BSP_SYSTEMINIT_B_INSTRUCTION __asm volatile ("B SystemInit"); + + #define WEAK_REF_ATTRIBUTE __attribute__((weak, alias("Default_Handler"))) +#endif + +void Undefined_Handler(void) WEAK_REF_ATTRIBUTE; +void SVC_Handler(void) WEAK_REF_ATTRIBUTE; +void Prefetch_Handler(void) WEAK_REF_ATTRIBUTE; +void Abort_Handler(void) WEAK_REF_ATTRIBUTE; +void Reserved_Handler(void) WEAK_REF_ATTRIBUTE; +void FIQ_Handler(void) WEAK_REF_ATTRIBUTE; + +/*******************************************************************************************************************//** + * After system_init, EL1 settings start here. + **********************************************************************************************************************/ +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void stack_init (void) +{ + __asm volatile ( + "stack_initialization: \n" + + /* Stack setting for EL1 */ + " CPS #17 \n" /* FIQ mode */ + " MOV sp, %[bsp_fiq_stack_end_address] \n" + " CPS #18 \n" /* IRQ mode */ + " MOV sp, %[bsp_irq_stack_end_address] \n" + " CPS #23 \n" /* Abort mode */ + " MOV sp, %[bsp_abort_stack_end_address] \n" + " CPS #27 \n" /* Undefined mode */ + " MOV sp, %[bsp_undefined_stack_end_address] \n" + " CPS #31 \n" /* System mode */ + " MOV sp, %[bsp_system_stack_end_address] \n" + " CPS #19 \n" /* SVC mode */ + " MOV sp, %[bsp_svc_stack_end_address] \n" + + " B fpu_slavetcm_init \n" /* Branch to fpu_slavetcm_init */ + ::[bsp_fiq_stack_end_address] "r" (BSP_FIQ_STACK_END_ADDRESS), + [bsp_irq_stack_end_address] "r" (BSP_IRQ_STACK_END_ADDRESS), + [bsp_abort_stack_end_address] "r" (BSP_ABORT_STACK_END_ADDRESS), + [bsp_undefined_stack_end_address] "r" (BSP_UNDEFINED_STACK_END_ADDRESS), + [bsp_system_stack_end_address] "r" (BSP_SYSTEM_STACK_END_ADDRESS), + [bsp_svc_stack_end_address] "r" (BSP_SVC_STACK_END_ADDRESS) : "memory"); +} + +/*******************************************************************************************************************//** + * Enable FPU and enable privileged/unprivileged access for TCM. + **********************************************************************************************************************/ +BSP_TARGET_ARM void fpu_slavetcm_init (void) +{ +#if __FPU_USED + + /* Initialize FPU and Advanced SIMD setting */ + bsp_fpu_advancedsimd_init(); +#endif + + /* Enable SLAVEPCTLR TCM access lvl slaves */ + bsp_slavetcm_enable(); + + BSP_SYSTEMINIT_B_INSTRUCTION +} + +__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void IRQ_Handler (void) +{ + __asm volatile ( + "SUB lr, lr, #4 \n" + "SRSDB sp!, #31 \n" /* Store LR_irq and SPSR_irq in system mode stack. */ + "CPS #31 \n" /* Switch to system mode. */ + "PUSH {r0-r3, r12} \n" /* Store other AAPCS registers. */ + +#if __FPU_USED + "VMRS r0, FPSCR \n" + "STMDB sp!, {r0} \n" /* Store FPSCR register. */ + "SUB sp, sp, #4 \n" + "VPUSH {d0-d15} \n" /* Store FPU registers. */ + "VPUSH {d16-d31} \n" /* Store FPU registers. */ +#endif + + "MRC p15, #0, r3, c12, c12, #2 \n" /* Read HPPIR1 to r3. */ + "MRC p15, #0, r0, c12, c12, #0 \n" /* Read IAR1 to r0. */ + + "PUSH {r0} \n" /* Store the INTID. */ + "MOV r1, sp \n" /* Make alignment for stack. */ + "AND r1, r1, #4 \n" + "SUB sp, sp, r1 \n" + "PUSH {r1, lr} \n" + + "LDR r1,=bsp_common_interrupt_handler \n" + "BLX r1 \n" /* Jump to bsp_common_interrupt_handler, First argument (r0) = ICC_IAR1 read value. */ + + "POP {r1, lr} \n" + "ADD sp, sp, r1 \n" + "POP {r0} \n" /* Restore the INTID to r0. */ + + "MCR p15, #0, r0, c12, c12, #1 \n" /* Write INTID to EOIR. */ + +#if __FPU_USED + "VPOP {d16-d31} \n" /* Restore FPU registers. */ + "VPOP {d0-d15} \n" /* Restore FPU registers. */ + "ADD sp, sp, #4 \n" + "POP {r0} \n" + "VMSR FPSCR, r0 \n" /* Restore FPSCR register. */ +#endif + + "POP {r0-r3, r12} \n" /* Restore registers. */ + "RFEIA sp! \n" /* Return from system mode tack using RFE. */ + ::: "memory"); +} + +__WEAK BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void Reset_Handler (void) +{ + /* Enable access to BTCM */ + __asm volatile ( + "set_IMP_BTCMREGIONR: \n" + " MRC p15, #0, r0, c9, c1, #1 \n" /* Read IMP_BTCMREGIONR to r0 */ + " MOVW r1, %[bsp_imp_btcmregionr_mask_l] \n" + " MOVT r1, #0 \n" + " AND r0, r0, r1 \n" /* Masked out BASEADDRESS and ENABLEELx bits */ + " MOVW r1, %[bsp_imp_btcmregionr_enableel_l] \n" + " MOVT r1, %[bsp_imp_btcmregionr_enableel_h] \n" + " ORR r0, r0, r1 \n" /* Set base address and enable EL2, EL1, EL0 access */ + " DSB \n" /* Ensuring memory access complete */ + + " MCR p15, #0, r0, c9, c1, #1 \n" /* Write r0 to IMP_BTCMREGIONR */ + " ISB \n" /* Ensuring Context-changing */ + ::[bsp_imp_btcmregionr_mask_l] "i" (BSP_IMP_BTCMREGIONR_MASK_L), + [bsp_imp_btcmregionr_enableel_l] "i" (BSP_IMP_BTCMREGIONR_ENABLEEL_L), + [bsp_imp_btcmregionr_enableel_h] "i" (BSP_IMP_BTCMREGIONR_ENABLEEL_H) : "memory"); + + /* Branch to system_init */ + __asm volatile ("B system_init"); +} diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c new file mode 100644 index 00000000000..cc47895c3f8 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/system_core.c @@ -0,0 +1,617 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include +#include "bsp_api.h" + +#include "../../../../../mcu/all/bsp_clocks.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_CPCAR_CP_ENABLE (0x00F00000) +#define BSP_FPEXC_EN_ENABLE (0x40000000) +#define BSP_TCM_ALL_ACCESS_ENABLE (0x00000003) + +#define BSP_PRIORITY_MASK BSP_FEATURE_BSP_IRQ_PRIORITY_MASK /* Priority mask value for GIC */ +#define BSP_ENABLE_GROUP_INT (0x00000001) /* Enable Group1 interrupt value */ +#define BSP_ICC_CTLR (0x00000001) /* ICC_BPR0 is used for Group1 interrupt */ + +#define BSP_BG_REGION_ENABLE (0x00020000) /* Enable EL1 background region */ +#define BSP_BG_REGION_DISABLE (0x00000000) /* Disable EL1 background region */ +#define BSP_SCTLR_BR_BIT (BSP_CFG_SCTLR_BR_BIT) /* Enable EL1 background region */ + +#define BSP_ICACHE_ENABLE (0x00001000) +#define BSP_ICACHE_DISABLE (0x00000000) + +#define BSP_DATACACHE_ENABLE (0x00000004) +#define BSP_DATACACHE_DISABLE (0x00000000) + +#define BSP_WRITE_THROUGH_TRANSIENT (0x0003) /* Normal-Memory: Write-Through transient */ +#define BSP_NON_CACHEABLE (0x0004) /* Normal-Memory: Non-Cacheable */ +#define BSP_WRITE_BACK_TRANSIENT (0x0007) /* Normal-Memory: Write-Back transient */ +#define BSP_WRITE_NON_THROUGH (0x000B) /* Normal-Memory: Write-Through non-transient. */ +#define BSP_WRITE_BACK_NON_TRANSIENT (0x000F) /* Normal-Memory: Write-Back non-transient. */ + +#define BSP_TYPE_NORMAL_MEMORY (0) +#define BSP_TYPE_DEVICE_MEMORY (1) + +#define BSP_READ_ALLOCATE (0xFFFF) /* Read allocate (bit1=1, "1" mask except bit1) */ +#define BSP_READ_NOT_ALLOCATE (0xFFFD) /* Read not allocate (bit1=0, "1" mask except bit1) */ +#define BSP_WRITE_ALLOCATE (0xFFFF) /* Write allocate (bit0=1, "1" mask except bit0) */ +#define BSP_WRITE_NOT_ALLOCATE (0xFFFE) /* Write not allocate (bit0=0, "1" mask except bit0) */ + +#define BSP_DEVICE_NGNRNE (0x0000) /* Device-nGnRnE memory */ +#define BSP_DEVICE_NGNRE (0x0004) /* Device-nGnRE memory */ +#define BSP_DEVICE_NGRE (0x0008) /* Device-nGRE memory */ +#define BSP_DEVICE_GRE (0x000C) /* Device-GRE memory */ + +#define BSP_OFFSET_ATTR0_INNER (0) +#define BSP_OFFSET_ATTR0_OUTER (4) +#define BSP_OFFSET_ATTR0_DEVICE (0) +#define BSP_OFFSET_ATTR1_INNER (8) +#define BSP_OFFSET_ATTR1_OUTER (12) +#define BSP_OFFSET_ATTR1_DEVICE (8) + +#define BSP_OFFSET_ATTR2_INNER (16) +#define BSP_OFFSET_ATTR2_OUTER (20) +#define BSP_OFFSET_ATTR2_DEVICE (16) +#define BSP_OFFSET_ATTR3_INNER (24) +#define BSP_OFFSET_ATTR3_OUTER (28) +#define BSP_OFFSET_ATTR3_DEVICE (24) + +#define BSP_OFFSET_ATTR4_INNER (0) +#define BSP_OFFSET_ATTR4_OUTER (4) +#define BSP_OFFSET_ATTR4_DEVICE (0) +#define BSP_OFFSET_ATTR5_INNER (8) +#define BSP_OFFSET_ATTR5_OUTER (12) +#define BSP_OFFSET_ATTR5_DEVICE (8) + +#define BSP_OFFSET_ATTR6_INNER (16) +#define BSP_OFFSET_ATTR6_OUTER (20) +#define BSP_OFFSET_ATTR6_DEVICE (16) +#define BSP_OFFSET_ATTR7_INNER (24) +#define BSP_OFFSET_ATTR7_OUTER (28) +#define BSP_OFFSET_ATTR7_DEVICE (24) + +#define BSP_NON_SHAREABLE (0 << 3) +#define BSP_OUTER_SHAREABLE (2 << 3) +#define BSP_INNER_SHAREABLE (3 << 3) +#define BSP_EL1RW_EL0NO (0 << 1) +#define BSP_EL1RW_EL0RW (1 << 1) +#define BSP_EL1RO_EL0NO (2 << 1) +#define BSP_EL1RO_EL0RO (3 << 1) +#define BSP_EXECUTE_ENABLE (0) +#define BSP_EXECUTE_NEVER (1) +#define BSP_REGION_DISABLE (0) +#define BSP_REGION_ENABLE (1) +#define BSP_ATTRINDEX0 (0 << 1) +#define BSP_ATTRINDEX1 (1 << 1) +#define BSP_ATTRINDEX2 (2 << 1) +#define BSP_ATTRINDEX3 (3 << 1) +#define BSP_ATTRINDEX4 (4 << 1) +#define BSP_ATTRINDEX5 (5 << 1) +#define BSP_ATTRINDEX6 (6 << 1) +#define BSP_ATTRINDEX7 (7 << 1) + +/* Attr0 */ +#if BSP_CFG_CPU_MPU_ATTR0_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR0 (BSP_CFG_CPU_MPU_ATTR0_DEVICE_TYPE << BSP_OFFSET_ATTR0_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR0 (((BSP_CFG_CPU_MPU_ATTR0_INNER & \ + (BSP_CFG_CPU_MPU_ATTR0_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE)) << BSP_OFFSET_ATTR0_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR0_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR0_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE)) << BSP_OFFSET_ATTR0_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR0_TYPE */ + +/* Attr1 */ +#if BSP_CFG_CPU_MPU_ATTR1_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR1 (BSP_CFG_CPU_MPU_ATTR1_DEVICE_TYPE << BSP_OFFSET_ATTR1_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR1 (((BSP_CFG_CPU_MPU_ATTR1_INNER & \ + (BSP_CFG_CPU_MPU_ATTR1_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE)) << BSP_OFFSET_ATTR1_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR1_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR1_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE)) << BSP_OFFSET_ATTR1_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR1_TYPE */ + +/* Attr2 */ +#if BSP_CFG_CPU_MPU_ATTR2_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR2 (BSP_CFG_CPU_MPU_ATTR2_DEVICE_TYPE << BSP_OFFSET_ATTR2_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR2 (((BSP_CFG_CPU_MPU_ATTR2_INNER & \ + (BSP_CFG_CPU_MPU_ATTR2_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE)) << BSP_OFFSET_ATTR2_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR2_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR2_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE)) << BSP_OFFSET_ATTR2_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR2_TYPE */ + +/* Attr3 */ +#if BSP_CFG_CPU_MPU_ATTR3_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR3 (BSP_CFG_CPU_MPU_ATTR3_DEVICE_TYPE << BSP_OFFSET_ATTR3_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR3 (((BSP_CFG_CPU_MPU_ATTR3_INNER & \ + (BSP_CFG_CPU_MPU_ATTR3_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE)) << BSP_OFFSET_ATTR3_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR3_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR3_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE)) << BSP_OFFSET_ATTR3_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR3_TYPE */ + +/* Attr4 */ +#if BSP_CFG_CPU_MPU_ATTR4_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR4 (BSP_CFG_CPU_MPU_ATTR4_DEVICE_TYPE << BSP_OFFSET_ATTR4_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR4 (((BSP_CFG_CPU_MPU_ATTR4_INNER & \ + (BSP_CFG_CPU_MPU_ATTR4_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE)) << BSP_OFFSET_ATTR4_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR4_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR4_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE)) << BSP_OFFSET_ATTR4_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR4_TYPE */ + +/* Attr5 */ +#if BSP_CFG_CPU_MPU_ATTR5_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR5 (BSP_CFG_CPU_MPU_ATTR5_DEVICE_TYPE << BSP_OFFSET_ATTR5_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR5 (((BSP_CFG_CPU_MPU_ATTR5_INNER & \ + (BSP_CFG_CPU_MPU_ATTR5_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE)) << BSP_OFFSET_ATTR5_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR5_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR5_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE)) << BSP_OFFSET_ATTR5_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR5_TYPE */ + +/* Attr6 */ +#if BSP_CFG_CPU_MPU_ATTR6_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR6 (BSP_CFG_CPU_MPU_ATTR6_DEVICE_TYPE << BSP_OFFSET_ATTR6_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR6 (((BSP_CFG_CPU_MPU_ATTR6_INNER & \ + (BSP_CFG_CPU_MPU_ATTR6_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE)) << BSP_OFFSET_ATTR6_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR6_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR6_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE)) << BSP_OFFSET_ATTR6_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR6_TYPE */ + +/* Attr7 */ +#if BSP_CFG_CPU_MPU_ATTR7_TYPE == BSP_TYPE_DEVICE_MEMORY /* MEMORY TYPE == DEVICE */ + #define BSP_CFG_CPU_MPU_ATTR7 (BSP_CFG_CPU_MPU_ATTR7_DEVICE_TYPE << BSP_OFFSET_ATTR7_DEVICE) +#else /* MEMORY TYPE == NORMAL MEMORY */ + #define BSP_CFG_CPU_MPU_ATTR7 (((BSP_CFG_CPU_MPU_ATTR7_INNER & \ + (BSP_CFG_CPU_MPU_ATTR7_INNER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE)) << BSP_OFFSET_ATTR7_INNER) | \ + ((BSP_CFG_CPU_MPU_ATTR7_OUTER & \ + (BSP_CFG_CPU_MPU_ATTR7_OUTER_READ) & \ + (BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE)) << BSP_OFFSET_ATTR7_OUTER)) +#endif /* BSP_CFG_CPU_MPU_ATTR7_TYPE */ + +#define ATTR_3_2_1_0 (BSP_CFG_CPU_MPU_ATTR3 | BSP_CFG_CPU_MPU_ATTR2 | BSP_CFG_CPU_MPU_ATTR1 | \ + BSP_CFG_CPU_MPU_ATTR0) +#define ATTR_7_6_5_4 (BSP_CFG_CPU_MPU_ATTR7 | BSP_CFG_CPU_MPU_ATTR6 | BSP_CFG_CPU_MPU_ATTR5 | \ + BSP_CFG_CPU_MPU_ATTR4) + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR0_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR0_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR0_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR1_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR1_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR1_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR2_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR2_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR2_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR3_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR3_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR3_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR4_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR4_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR4_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR5_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR5_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR5_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR6_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR6_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR6_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +#if (BSP_TYPE_NORMAL_MEMORY == BSP_CFG_CPU_MPU_ATTR7_TYPE) + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR7_INNER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_INNER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif + #if ((BSP_WRITE_THROUGH_TRANSIENT == BSP_CFG_CPU_MPU_ATTR7_OUTER) && \ + (BSP_READ_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_OUTER_READ) && \ + (BSP_WRITE_NOT_ALLOCATE == BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE)) + #error "If you select Write-Through transient, set either Read or Write to allocate." + #endif +#endif + +/* Region template */ +#define EL1_MPU_REGION_COUNT (24) + +#define EL1_MPU_REGIONXX_BASE(n) ((BSP_CFG_EL1_MPU_REGION ## n ## _BASE & 0xFFFFFFC0) | \ + BSP_CFG_EL1_MPU_REGION ## n ## _SH | \ + BSP_CFG_EL1_MPU_REGION ## n ## _AP | \ + BSP_CFG_EL1_MPU_REGION ## n ## _XN) + +#define EL1_MPU_REGIONXX_LIMIT(n) ((BSP_CFG_EL1_MPU_REGION ## n ## _LIMIT & 0xFFFFFFC0) | \ + BSP_CFG_EL1_MPU_REGION ## n ## _ATTRINDEX | \ + BSP_CFG_EL1_MPU_REGION ## n ## _ENABLE) + +/* region 0 */ +#define EL1_MPU_REGION00_BASE EL1_MPU_REGIONXX_BASE(00) +#define EL1_MPU_REGION00_LIMIT EL1_MPU_REGIONXX_LIMIT(00) + +/* region 1 */ +#define EL1_MPU_REGION01_BASE EL1_MPU_REGIONXX_BASE(01) +#define EL1_MPU_REGION01_LIMIT EL1_MPU_REGIONXX_LIMIT(01) + +/* region 2 */ +#define EL1_MPU_REGION02_BASE EL1_MPU_REGIONXX_BASE(02) +#define EL1_MPU_REGION02_LIMIT EL1_MPU_REGIONXX_LIMIT(02) + +/* region 3 */ +#define EL1_MPU_REGION03_BASE EL1_MPU_REGIONXX_BASE(03) +#define EL1_MPU_REGION03_LIMIT EL1_MPU_REGIONXX_LIMIT(03) + +/* region 4 */ +#define EL1_MPU_REGION04_BASE EL1_MPU_REGIONXX_BASE(04) +#define EL1_MPU_REGION04_LIMIT EL1_MPU_REGIONXX_LIMIT(04) + +/* region 5 */ +#define EL1_MPU_REGION05_BASE EL1_MPU_REGIONXX_BASE(05) +#define EL1_MPU_REGION05_LIMIT EL1_MPU_REGIONXX_LIMIT(05) + +/* region 6 */ +#define EL1_MPU_REGION06_BASE EL1_MPU_REGIONXX_BASE(06) +#define EL1_MPU_REGION06_LIMIT EL1_MPU_REGIONXX_LIMIT(06) + +/* region 7 */ +#define EL1_MPU_REGION07_BASE EL1_MPU_REGIONXX_BASE(07) +#define EL1_MPU_REGION07_LIMIT EL1_MPU_REGIONXX_LIMIT(07) + +/* region 8 */ +#define EL1_MPU_REGION08_BASE EL1_MPU_REGIONXX_BASE(08) +#define EL1_MPU_REGION08_LIMIT EL1_MPU_REGIONXX_LIMIT(08) + +/* region 9 */ +#define EL1_MPU_REGION09_BASE EL1_MPU_REGIONXX_BASE(09) +#define EL1_MPU_REGION09_LIMIT EL1_MPU_REGIONXX_LIMIT(09) + +/* region 10 */ +#define EL1_MPU_REGION10_BASE EL1_MPU_REGIONXX_BASE(10) +#define EL1_MPU_REGION10_LIMIT EL1_MPU_REGIONXX_LIMIT(10) + +/* region 11 */ +#define EL1_MPU_REGION11_BASE EL1_MPU_REGIONXX_BASE(11) +#define EL1_MPU_REGION11_LIMIT EL1_MPU_REGIONXX_LIMIT(11) + +/* region 12 */ +#define EL1_MPU_REGION12_BASE EL1_MPU_REGIONXX_BASE(12) +#define EL1_MPU_REGION12_LIMIT EL1_MPU_REGIONXX_LIMIT(12) + +/* region 13 */ +#define EL1_MPU_REGION13_BASE EL1_MPU_REGIONXX_BASE(13) +#define EL1_MPU_REGION13_LIMIT EL1_MPU_REGIONXX_LIMIT(13) + +/* region 14 */ +#define EL1_MPU_REGION14_BASE EL1_MPU_REGIONXX_BASE(14) +#define EL1_MPU_REGION14_LIMIT EL1_MPU_REGIONXX_LIMIT(14) + +/* region 15 */ +#define EL1_MPU_REGION15_BASE EL1_MPU_REGIONXX_BASE(15) +#define EL1_MPU_REGION15_LIMIT EL1_MPU_REGIONXX_LIMIT(15) + +/* region 16 */ +#define EL1_MPU_REGION16_BASE EL1_MPU_REGIONXX_BASE(16) +#define EL1_MPU_REGION16_LIMIT EL1_MPU_REGIONXX_LIMIT(16) + +/* region 17 */ +#define EL1_MPU_REGION17_BASE EL1_MPU_REGIONXX_BASE(17) +#define EL1_MPU_REGION17_LIMIT EL1_MPU_REGIONXX_LIMIT(17) + +/* region 18 */ +#define EL1_MPU_REGION18_BASE EL1_MPU_REGIONXX_BASE(18) +#define EL1_MPU_REGION18_LIMIT EL1_MPU_REGIONXX_LIMIT(18) + +/* region 19 */ +#define EL1_MPU_REGION19_BASE EL1_MPU_REGIONXX_BASE(19) +#define EL1_MPU_REGION19_LIMIT EL1_MPU_REGIONXX_LIMIT(19) + +/* region 20 */ +#define EL1_MPU_REGION20_BASE EL1_MPU_REGIONXX_BASE(20) +#define EL1_MPU_REGION20_LIMIT EL1_MPU_REGIONXX_LIMIT(20) + +/* region 21 */ +#define EL1_MPU_REGION21_BASE EL1_MPU_REGIONXX_BASE(21) +#define EL1_MPU_REGION21_LIMIT EL1_MPU_REGIONXX_LIMIT(21) + +/* region 22 */ +#define EL1_MPU_REGION22_BASE EL1_MPU_REGIONXX_BASE(22) +#define EL1_MPU_REGION22_LIMIT EL1_MPU_REGIONXX_LIMIT(22) + +/* region 23 */ +#define EL1_MPU_REGION23_BASE EL1_MPU_REGIONXX_BASE(23) +#define EL1_MPU_REGION23_LIMIT EL1_MPU_REGIONXX_LIMIT(23) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_bsp_mpu_config +{ + uint32_t base; + uint32_t limit; +} bsp_mpu_config_t; + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +static const bsp_mpu_config_t g_bsp_el1_mpu[EL1_MPU_REGION_COUNT] = +{ + {EL1_MPU_REGION00_BASE, EL1_MPU_REGION00_LIMIT}, + {EL1_MPU_REGION01_BASE, EL1_MPU_REGION01_LIMIT}, + {EL1_MPU_REGION02_BASE, EL1_MPU_REGION02_LIMIT}, + {EL1_MPU_REGION03_BASE, EL1_MPU_REGION03_LIMIT}, + {EL1_MPU_REGION04_BASE, EL1_MPU_REGION04_LIMIT}, + {EL1_MPU_REGION05_BASE, EL1_MPU_REGION05_LIMIT}, + {EL1_MPU_REGION06_BASE, EL1_MPU_REGION06_LIMIT}, + {EL1_MPU_REGION07_BASE, EL1_MPU_REGION07_LIMIT}, + {EL1_MPU_REGION08_BASE, EL1_MPU_REGION08_LIMIT}, + {EL1_MPU_REGION09_BASE, EL1_MPU_REGION09_LIMIT}, + {EL1_MPU_REGION10_BASE, EL1_MPU_REGION10_LIMIT}, + {EL1_MPU_REGION11_BASE, EL1_MPU_REGION11_LIMIT}, + {EL1_MPU_REGION12_BASE, EL1_MPU_REGION12_LIMIT}, + {EL1_MPU_REGION13_BASE, EL1_MPU_REGION13_LIMIT}, + {EL1_MPU_REGION14_BASE, EL1_MPU_REGION14_LIMIT}, + {EL1_MPU_REGION15_BASE, EL1_MPU_REGION15_LIMIT}, + {EL1_MPU_REGION16_BASE, EL1_MPU_REGION16_LIMIT}, + {EL1_MPU_REGION17_BASE, EL1_MPU_REGION17_LIMIT}, + {EL1_MPU_REGION18_BASE, EL1_MPU_REGION18_LIMIT}, + {EL1_MPU_REGION19_BASE, EL1_MPU_REGION19_LIMIT}, + {EL1_MPU_REGION20_BASE, EL1_MPU_REGION20_LIMIT}, + {EL1_MPU_REGION21_BASE, EL1_MPU_REGION21_LIMIT}, + {EL1_MPU_REGION22_BASE, EL1_MPU_REGION22_LIMIT}, + {EL1_MPU_REGION23_BASE, EL1_MPU_REGION23_LIMIT}, +}; + +#if __FPU_USED +void bsp_fpu_advancedsimd_init(void); + +#endif + +void bsp_slavetcm_enable(void); +void bsp_memory_protect_setting(void); +void bsp_mpu_init(uint32_t region, uint32_t base, uint32_t limit); +void bsp_irq_cfg_common(void); + +#if __FPU_USED + +/*******************************************************************************************************************//** + * Initialize FPU and Advanced SIMD setting. + **********************************************************************************************************************/ +void bsp_fpu_advancedsimd_init (void) +{ + uint32_t apacr; + uint32_t fpexc; + + /* Enables cp10 and cp11 accessing */ + apacr = __get_CPACR(); + apacr |= BSP_CPCAR_CP_ENABLE; + __set_CPACR(apacr); + __ISB(); + + /* Enables the FPU */ + fpexc = __get_FPEXC(); + fpexc |= BSP_FPEXC_EN_ENABLE; + __set_FPEXC(fpexc); + __ISB(); +} + +#endif + +/*******************************************************************************************************************//** + * Settings the privilege level required for the AXIS to access the TCM. + **********************************************************************************************************************/ +void bsp_slavetcm_enable (void) +{ + uint32_t imp_slavepctlr; + + /* Enable TCM access privilege and non privilege */ + imp_slavepctlr = __get_IMP_SLAVEPCTLR(); + imp_slavepctlr |= BSP_TCM_ALL_ACCESS_ENABLE; + __DSB(); + + __set_IMP_SLAVEPCTLR(imp_slavepctlr); + __ISB(); +} + +/*******************************************************************************************************************//** + * Initialize memory protection settings. + **********************************************************************************************************************/ +void bsp_memory_protect_setting (void) +{ + uint32_t sctlr; + uint32_t mair0; + uint32_t mair1; + uint32_t region; + + /* Adopt EL1 default memory map as background map */ + sctlr = __get_SCTLR(); + sctlr |= BSP_SCTLR_BR_BIT; + __DSB(); + __set_SCTLR(sctlr); + __ISB(); + + /* Configure Memory Attribute Indirection Registers */ + mair0 = ATTR_3_2_1_0; + mair1 = ATTR_7_6_5_4; + __set_MAIR0(mair0); + __set_MAIR1(mair1); + __DSB(); + + /* Setup region. */ + for (region = 0; region < EL1_MPU_REGION_COUNT; region++) + { + bsp_mpu_init(region, g_bsp_el1_mpu[region].base, g_bsp_el1_mpu[region].limit); + } + + R_BSP_CacheInvalidateAll(); + + R_BSP_CacheEnableMemoryProtect(); + +#if (BSP_ICACHE_ENABLE == BSP_CFG_SCTLR_I_BIT) + R_BSP_CacheEnableInst(); +#else + R_BSP_CacheDisableInst(); +#endif + +#if (BSP_DATACACHE_ENABLE == BSP_CFG_SCTLR_C_BIT) + R_BSP_CacheEnableData(); +#else + R_BSP_CacheDisableData(); +#endif +} + +/*******************************************************************************************************************//** + * Core MPU initialization block. + **********************************************************************************************************************/ +void bsp_mpu_init (uint32_t region, uint32_t base, uint32_t limit) +{ + /* Selects the current EL1-controlled MPU region registers, PRBAR, and PRLAR */ + __set_PRSELR(region); + __DSB(); + + /* Set the base address and attributes of the MPU region controlled by EL1 */ + __set_PRBAR(base); + __DSB(); + + /* Set the limit address and attributes of the MPU region controlled by EL1 */ + __set_PRLAR(limit); + __DSB(); +} + +/*******************************************************************************************************************//** + * Initialize common configuration settings for interrupts + **********************************************************************************************************************/ +void bsp_irq_cfg_common (void) +{ + uint32_t icc_pmr; + uint32_t icc_igrpen1; + uint32_t icc_ctlr; + + /* Set priority mask level for CPU interface */ + icc_pmr = BSP_PRIORITY_MASK; + __set_ICC_PMR(icc_pmr); + + /* Enable group 1 interrupts */ + icc_igrpen1 = BSP_ENABLE_GROUP_INT; + __set_ICC_IGRPEN1(icc_igrpen1); + + /* Use ICC_BPR0 for interrupt preemption for both group 0 and group 1 interrupts */ + icc_ctlr = __get_ICC_CTLR(); + icc_ctlr |= BSP_ICC_CTLR; + __set_ICC_CTLR(icc_ctlr); + + __ISB(); +} diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c new file mode 100644 index 00000000000..72bd1de7517 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c @@ -0,0 +1,197 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +extern void bsp_master_mpu_init(void); +extern void bsp_global_system_counter_init(void); + +#if BSP_FEATURE_TFU_SUPPORTED +extern void bsp_tfu_init(void); + +#endif + +#if BSP_CFG_C_RUNTIME_INIT +extern void bsp_loader_data_init(void); +extern void bsp_loader_bss_init(void); +extern void bsp_static_constructor_init(void); + +#endif + +#if !(BSP_CFG_RAM_EXECUTION) +extern void bsp_copy_to_ram(void); +extern void bsp_application_bss_init(void); + +#endif + +#if !BSP_CFG_PORT_PROTECT +extern void bsp_release_port_protect(void); + +#endif + +extern void bsp_memory_protect_setting(void); +extern void bsp_irq_cfg_common(void); + +extern void R_BSP_WarmStart(bsp_warm_start_event_t event); + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +int32_t main(void); + +#if BSP_CFG_EARLY_INIT +static void bsp_init_uninitialized_vars(void); + +#endif + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize the MCU and the runtime environment. + **********************************************************************************************************************/ +void SystemInit (void) +{ +#if BSP_CFG_EARLY_INIT + + /* Initialize uninitialized BSP variables early for use in R_BSP_WarmStart. */ + bsp_init_uninitialized_vars(); +#endif + + /* Call before initializing clock and variables. */ + R_BSP_WarmStart(BSP_WARM_START_RESET); + + /* Configure system clocks. */ + bsp_clock_init(); + + /* Call post clock initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK); + +#if BSP_CFG_C_RUNTIME_INIT + + /* Copy the loader data from external Flash to internal RAM. */ + bsp_loader_data_init(); + + /* Clear loader bss section in internal RAM. */ + bsp_loader_bss_init(); +#endif + + /* Initialize SystemCoreClock variable. */ + SystemCoreClockUpdate(); + + /* Set memory attributes, etc. */ + bsp_memory_protect_setting(); + +#if !(BSP_CFG_RAM_EXECUTION) + + /* Copy the application program from external Flash to internal RAM. */ + bsp_copy_to_ram(); + + /* Clear bss section in internal RAM. */ + bsp_application_bss_init(); +#endif + +#if BSP_CFG_C_RUNTIME_INIT + + /* Initialize static constructors */ + bsp_static_constructor_init(); +#endif + +#if !BSP_CFG_PORT_PROTECT + + /* When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + bsp_release_port_protect(); +#endif + + /* Call Post C runtime initialization hook. */ + R_BSP_WarmStart(BSP_WARM_START_POST_C); + + /* Initialize the Master-MPU settings. */ + bsp_master_mpu_init(); + + /* Initialize global system counter. The counter is enabled and is incrementing. */ + bsp_global_system_counter_init(); + + /* GIC initialization */ + bsp_irq_cfg_common(); + + /* Initialize GIC interrupts. */ + bsp_irq_cfg(); + +#if BSP_FEATURE_TFU_SUPPORTED + + /* Initialize the TFU settings. */ + bsp_tfu_init(); +#endif + +#if defined(__GNUC__) + extern void entry(void); + entry(); +#elif defined(__ICCARM__) + extern void __low_level_init(void); + __low_level_init(); +#else + /* Jump to main. */ + main(); +#endif +} + +/** @} (end addtogroup BSP_MCU) */ + +#if BSP_CFG_EARLY_INIT + +/*******************************************************************************************************************//** + * Initialize BSP variables not handled by C runtime startup. + **********************************************************************************************************************/ +static void bsp_init_uninitialized_vars (void) +{ + g_protect_port_counter = 0; + + extern volatile uint16_t g_protect_counters[]; + for (uint32_t i = 0; i < 4; i++) + { + g_protect_counters[i] = 0; + } + + SystemCoreClockUpdate(); +} + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c new file mode 100644 index 00000000000..66d5fa642e4 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c @@ -0,0 +1,822 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_PRV_MASTER_MPU_REGION_NUM (8) + +#define BSP_PRV_MASTER_MPU_STADD(master, region) (BSP_CFG_MPU ## master ## _STADD ## region | \ + (BSP_CFG_MPU ## master ## _WRITE ## region << 1) | \ + BSP_CFG_MPU ## master ## _READ ## region) + +#define BSP_PRV_MASTER_MPU_ENDADD(master, region) (BSP_CFG_MPU ## master ## _ENDADD ## region) + +#if defined(__ICCARM__) + #if BSP_CFG_C_RUNTIME_INIT + #define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS __section_begin("LDR_DATA_RBLOCK") + #define BSP_PRV_SECTION_LDR_DATA_RAM_START __section_begin("LDR_DATA_WBLOCK") + #define BSP_PRV_SECTION_LDR_DATA_RAM_END __section_end("LDR_DATA_WBLOCK") + + #define BSP_PRV_SECTION_LDR_DATA_BSS_START __section_begin("LDR_DATA_ZBLOCK") + #define BSP_PRV_SECTION_LDR_DATA_BSS_END __section_end("LDR_DATA_ZBLOCK") + + #endif + + #if !(BSP_CFG_RAM_EXECUTION) + #define BSP_PRV_SECTION_VECTOR_ROM_ADDRESS __section_begin("VECTOR_RBLOCK") + #define BSP_PRV_SECTION_VECTOR_RAM_START __section_begin("VECTOR_WBLOCK") + #define BSP_PRV_SECTION_VECTOR_RAM_END __section_end("VECTOR_WBLOCK") + + #define BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS __section_begin("USER_PRG_RBLOCK") + #define BSP_PRV_SECTION_USER_PRG_RAM_START __section_begin("USER_PRG_WBLOCK") + #define BSP_PRV_SECTION_USER_PRG_RAM_END __section_end("USER_PRG_WBLOCK") + + #define BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS __section_begin("USER_DATA_RBLOCK") + #define BSP_PRV_SECTION_USER_DATA_RAM_START __section_begin("USER_DATA_WBLOCK") + #define BSP_PRV_SECTION_USER_DATA_RAM_END __section_end("USER_DATA_WBLOCK") + + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS __section_begin("USER_DATA_NONCACHE_RBLOCK") + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START __section_begin("USER_DATA_NONCACHE_WBLOCK") + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END __section_end("USER_DATA_NONCACHE_WBLOCK") + + #define BSP_PRV_SECTION_USER_DATA_BSS_START __section_begin("USER_DATA_ZBLOCK") + #define BSP_PRV_SECTION_USER_DATA_BSS_END __section_end("USER_DATA_ZBLOCK") + + #endif + + #if BSP_CFG_RAM_EXECUTION + #define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START __section_begin("NONCACHE_BUFFER_ZBLOCK") + #define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END __section_end("NONCACHE_BUFFER_ZBLOCK") + + #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START __section_begin("SHARED_NONCACHE_BUFFER_ZBLOCK") + #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END __section_end("SHARED_NONCACHE_BUFFER_ZBLOCK") + + #define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START __section_begin("DMAC_LINK_MODE_ZBLOCK") + #define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END __section_end("DMAC_LINK_MODE_ZBLOCK") + + #endif + +#elif defined(__GNUC__) + #if BSP_CFG_C_RUNTIME_INIT + #define BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS &_mloader_data + #define BSP_PRV_SECTION_LDR_DATA_RAM_START &__loader_data_start + #define BSP_PRV_SECTION_LDR_DATA_RAM_END &__loader_data_end + + #define BSP_PRV_SECTION_LDR_DATA_BSS_START &__loader_bss_start + #define BSP_PRV_SECTION_LDR_DATA_BSS_END &__loader_bss_end + + #endif + + #if !(BSP_CFG_RAM_EXECUTION) + #define BSP_PRV_SECTION_VECTOR_ROM_ADDRESS &_mfvector + #define BSP_PRV_SECTION_VECTOR_RAM_START &_fvector_start + #define BSP_PRV_SECTION_VECTOR_RAM_END &_fvector_end + + #define BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS &_mtext + #define BSP_PRV_SECTION_USER_PRG_RAM_START &_text_start + #define BSP_PRV_SECTION_USER_PRG_RAM_END &_text_end + + #define BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS &_mdata + #define BSP_PRV_SECTION_USER_DATA_RAM_START &_data_start + #define BSP_PRV_SECTION_USER_DATA_RAM_END &_data_end + + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS &_mdata_noncache + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START &_data_noncache_start + #define BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END &_data_noncache_end + + #endif + + #define BSP_PRV_SECTION_USER_DATA_BSS_START &__bss_start__ + #define BSP_PRV_SECTION_USER_DATA_BSS_END &__bss_end__ + + #if BSP_CFG_RAM_EXECUTION + #define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START &_ncbuffer_start + #define BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END &_ncbuffer_end + + #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START &_sncbuffer_start + #define BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END &_sncbuffer_end + + #define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START &_DmacLinkMode_start + #define BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END &_DmacLinkMode_end + + #endif + +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClock = 0U; + +/** @} (end addtogroup BSP_MCU) */ + +#if defined(__ICCARM__) + #if BSP_CFG_C_RUNTIME_INIT + #pragma section="LDR_DATA_RBLOCK" + #pragma section="LDR_DATA_WBLOCK" + #pragma section="LDR_DATA_ZBLOCK" + + #endif + + #if !(BSP_CFG_RAM_EXECUTION) + #pragma section="VECTOR_RBLOCK" + #pragma section="VECTOR_WBLOCK" + + #pragma section="USER_PRG_RBLOCK" + #pragma section="USER_PRG_WBLOCK" + + #pragma section="USER_DATA_RBLOCK" + #pragma section="USER_DATA_WBLOCK" + #pragma section="USER_DATA_ZBLOCK" + + #pragma section="USER_DATA_NONCACHE_RBLOCK" + #pragma section="USER_DATA_NONCACHE_WBLOCK" + + #endif + + #if BSP_CFG_RAM_EXECUTION + #pragma section="NONCACHE_BUFFER_ZBLOCK" + #pragma section="SHARED_NONCACHE_BUFFER_ZBLOCK" + #pragma section="DMAC_LINK_MODE_ZBLOCK" + + #endif + +#elif defined(__GNUC__) + #if BSP_CFG_C_RUNTIME_INIT +extern void * _mloader_data; +extern void * __loader_data_start; +extern void * __loader_data_end; + +extern void * __loader_bss_start; +extern void * __loader_bss_end; + +extern void (* __preinit_array_start[])(void); +extern void (* __preinit_array_end[])(void); +extern void (* __init_array_start[])(void); +extern void (* __init_array_end[])(void); + + #endif + + #if !(BSP_CFG_RAM_EXECUTION) +extern void * _mfvector; +extern void * _fvector_start; +extern void * _fvector_end; + +extern void * _mtext; +extern void * _text_start; +extern void * _text_end; + +extern void * _mdata; +extern void * _data_start; +extern void * _data_end; + +extern void * _mdata_noncache; +extern void * _data_noncache_start; +extern void * _data_noncache_end; + + #endif + +extern void * __bss_start__; +extern void * __bss_end__; + + #if BSP_CFG_RAM_EXECUTION +extern void * _ncbuffer_start; +extern void * _ncbuffer_end; + +extern void * _sncbuffer_start; +extern void * _sncbuffer_end; + +extern void * _DmacLinkMode_start; +extern void * _DmacLinkMode_end; + + #endif +#endif + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #if BSP_CFG_C_RUNTIME_INIT +extern void __iar_data_init3(void); + + #endif +#endif + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +#if (1 == BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED) +const uint32_t g_bsp_master_mpu0_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(0, 0), BSP_PRV_MASTER_MPU_ENDADD(0, 0)}, + {BSP_PRV_MASTER_MPU_STADD(0, 1), BSP_PRV_MASTER_MPU_ENDADD(0, 1)}, + {BSP_PRV_MASTER_MPU_STADD(0, 2), BSP_PRV_MASTER_MPU_ENDADD(0, 2)}, + {BSP_PRV_MASTER_MPU_STADD(0, 3), BSP_PRV_MASTER_MPU_ENDADD(0, 3)}, + {BSP_PRV_MASTER_MPU_STADD(0, 4), BSP_PRV_MASTER_MPU_ENDADD(0, 4)}, + {BSP_PRV_MASTER_MPU_STADD(0, 5), BSP_PRV_MASTER_MPU_ENDADD(0, 5)}, + {BSP_PRV_MASTER_MPU_STADD(0, 6), BSP_PRV_MASTER_MPU_ENDADD(0, 6)}, + {BSP_PRV_MASTER_MPU_STADD(0, 7), BSP_PRV_MASTER_MPU_ENDADD(0, 7)} +}; + +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED) +const uint32_t g_bsp_master_mpu1_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(1, 0), BSP_PRV_MASTER_MPU_ENDADD(1, 0)}, + {BSP_PRV_MASTER_MPU_STADD(1, 1), BSP_PRV_MASTER_MPU_ENDADD(1, 1)}, + {BSP_PRV_MASTER_MPU_STADD(1, 2), BSP_PRV_MASTER_MPU_ENDADD(1, 2)}, + {BSP_PRV_MASTER_MPU_STADD(1, 3), BSP_PRV_MASTER_MPU_ENDADD(1, 3)}, + {BSP_PRV_MASTER_MPU_STADD(1, 4), BSP_PRV_MASTER_MPU_ENDADD(1, 4)}, + {BSP_PRV_MASTER_MPU_STADD(1, 5), BSP_PRV_MASTER_MPU_ENDADD(1, 5)}, + {BSP_PRV_MASTER_MPU_STADD(1, 6), BSP_PRV_MASTER_MPU_ENDADD(1, 6)}, + {BSP_PRV_MASTER_MPU_STADD(1, 7), BSP_PRV_MASTER_MPU_ENDADD(1, 7)} +}; + +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED) +const uint32_t g_bsp_master_mpu2_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(2, 0), BSP_PRV_MASTER_MPU_ENDADD(2, 0)}, + {BSP_PRV_MASTER_MPU_STADD(2, 1), BSP_PRV_MASTER_MPU_ENDADD(2, 1)}, + {BSP_PRV_MASTER_MPU_STADD(2, 2), BSP_PRV_MASTER_MPU_ENDADD(2, 2)}, + {BSP_PRV_MASTER_MPU_STADD(2, 3), BSP_PRV_MASTER_MPU_ENDADD(2, 3)}, + {BSP_PRV_MASTER_MPU_STADD(2, 4), BSP_PRV_MASTER_MPU_ENDADD(2, 4)}, + {BSP_PRV_MASTER_MPU_STADD(2, 5), BSP_PRV_MASTER_MPU_ENDADD(2, 5)}, + {BSP_PRV_MASTER_MPU_STADD(2, 6), BSP_PRV_MASTER_MPU_ENDADD(2, 6)}, + {BSP_PRV_MASTER_MPU_STADD(2, 7), BSP_PRV_MASTER_MPU_ENDADD(2, 7)} +}; + +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED) +const uint32_t g_bsp_master_mpu3_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(3, 0), BSP_PRV_MASTER_MPU_ENDADD(3, 0)}, + {BSP_PRV_MASTER_MPU_STADD(3, 1), BSP_PRV_MASTER_MPU_ENDADD(3, 1)}, + {BSP_PRV_MASTER_MPU_STADD(3, 2), BSP_PRV_MASTER_MPU_ENDADD(3, 2)}, + {BSP_PRV_MASTER_MPU_STADD(3, 3), BSP_PRV_MASTER_MPU_ENDADD(3, 3)}, + {BSP_PRV_MASTER_MPU_STADD(3, 4), BSP_PRV_MASTER_MPU_ENDADD(3, 4)}, + {BSP_PRV_MASTER_MPU_STADD(3, 5), BSP_PRV_MASTER_MPU_ENDADD(3, 5)}, + {BSP_PRV_MASTER_MPU_STADD(3, 6), BSP_PRV_MASTER_MPU_ENDADD(3, 6)}, + {BSP_PRV_MASTER_MPU_STADD(3, 7), BSP_PRV_MASTER_MPU_ENDADD(3, 7)} +}; + +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED) +const uint32_t g_bsp_master_mpu4_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(4, 0), BSP_PRV_MASTER_MPU_ENDADD(4, 0)}, + {BSP_PRV_MASTER_MPU_STADD(4, 1), BSP_PRV_MASTER_MPU_ENDADD(4, 1)}, + {BSP_PRV_MASTER_MPU_STADD(4, 2), BSP_PRV_MASTER_MPU_ENDADD(4, 2)}, + {BSP_PRV_MASTER_MPU_STADD(4, 3), BSP_PRV_MASTER_MPU_ENDADD(4, 3)}, + {BSP_PRV_MASTER_MPU_STADD(4, 4), BSP_PRV_MASTER_MPU_ENDADD(4, 4)}, + {BSP_PRV_MASTER_MPU_STADD(4, 5), BSP_PRV_MASTER_MPU_ENDADD(4, 5)}, + {BSP_PRV_MASTER_MPU_STADD(4, 6), BSP_PRV_MASTER_MPU_ENDADD(4, 6)}, + {BSP_PRV_MASTER_MPU_STADD(4, 7), BSP_PRV_MASTER_MPU_ENDADD(4, 7)} +}; + +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED) +const uint32_t g_bsp_master_mpu6_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(6, 0), BSP_PRV_MASTER_MPU_ENDADD(6, 0)}, + {BSP_PRV_MASTER_MPU_STADD(6, 1), BSP_PRV_MASTER_MPU_ENDADD(6, 1)}, + {BSP_PRV_MASTER_MPU_STADD(6, 2), BSP_PRV_MASTER_MPU_ENDADD(6, 2)}, + {BSP_PRV_MASTER_MPU_STADD(6, 3), BSP_PRV_MASTER_MPU_ENDADD(6, 3)}, + {BSP_PRV_MASTER_MPU_STADD(6, 4), BSP_PRV_MASTER_MPU_ENDADD(6, 4)}, + {BSP_PRV_MASTER_MPU_STADD(6, 5), BSP_PRV_MASTER_MPU_ENDADD(6, 5)}, + {BSP_PRV_MASTER_MPU_STADD(6, 6), BSP_PRV_MASTER_MPU_ENDADD(6, 6)}, + {BSP_PRV_MASTER_MPU_STADD(6, 7), BSP_PRV_MASTER_MPU_ENDADD(6, 7)} +}; + +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED) +const uint32_t g_bsp_master_mpu7_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(7, 0), BSP_PRV_MASTER_MPU_ENDADD(7, 0)}, + {BSP_PRV_MASTER_MPU_STADD(7, 1), BSP_PRV_MASTER_MPU_ENDADD(7, 1)}, + {BSP_PRV_MASTER_MPU_STADD(7, 2), BSP_PRV_MASTER_MPU_ENDADD(7, 2)}, + {BSP_PRV_MASTER_MPU_STADD(7, 3), BSP_PRV_MASTER_MPU_ENDADD(7, 3)}, + {BSP_PRV_MASTER_MPU_STADD(7, 4), BSP_PRV_MASTER_MPU_ENDADD(7, 4)}, + {BSP_PRV_MASTER_MPU_STADD(7, 5), BSP_PRV_MASTER_MPU_ENDADD(7, 5)}, + {BSP_PRV_MASTER_MPU_STADD(7, 6), BSP_PRV_MASTER_MPU_ENDADD(7, 6)}, + {BSP_PRV_MASTER_MPU_STADD(7, 7), BSP_PRV_MASTER_MPU_ENDADD(7, 7)} +}; + +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU8_SUPPORTED) +const uint32_t g_bsp_master_mpu8_cfg[BSP_PRV_MASTER_MPU_REGION_NUM][2] = +{ + {BSP_PRV_MASTER_MPU_STADD(8, 0), BSP_PRV_MASTER_MPU_ENDADD(8, 0)}, + {BSP_PRV_MASTER_MPU_STADD(8, 1), BSP_PRV_MASTER_MPU_ENDADD(8, 1)}, + {BSP_PRV_MASTER_MPU_STADD(8, 2), BSP_PRV_MASTER_MPU_ENDADD(8, 2)}, + {BSP_PRV_MASTER_MPU_STADD(8, 3), BSP_PRV_MASTER_MPU_ENDADD(8, 3)}, + {BSP_PRV_MASTER_MPU_STADD(8, 4), BSP_PRV_MASTER_MPU_ENDADD(8, 4)}, + {BSP_PRV_MASTER_MPU_STADD(8, 5), BSP_PRV_MASTER_MPU_ENDADD(8, 5)}, + {BSP_PRV_MASTER_MPU_STADD(8, 6), BSP_PRV_MASTER_MPU_ENDADD(8, 6)}, + {BSP_PRV_MASTER_MPU_STADD(8, 7), BSP_PRV_MASTER_MPU_ENDADD(8, 7)} +}; + +#endif + +#if defined(__ICCARM__) + +void R_BSP_WarmStart(bsp_warm_start_event_t event); + + #pragma weak R_BSP_WarmStart + +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) + +void R_BSP_WarmStart(bsp_warm_start_event_t event) __attribute__((weak)); + +#endif + +#if BSP_CFG_C_RUNTIME_INIT +void bsp_loader_data_init(void); +void bsp_loader_bss_init(void); +void bsp_static_constructor_init(void); + +#endif + +void bsp_copy_multibyte(uintptr_t * src, uintptr_t * dst, uintptr_t bytesize); +void bsp_bss_init_multibyte(uintptr_t * src, uintptr_t bytesize); + +#if !(BSP_CFG_RAM_EXECUTION) +void bsp_copy_to_ram(void); +void bsp_application_bss_init(void); + +#endif + +void bsp_master_mpu_init(void); +void bsp_global_system_counter_init(void); + +#if BSP_FEATURE_TFU_SUPPORTED +void bsp_tfu_init(void); + +#endif + +#if !BSP_CFG_PORT_PROTECT +void bsp_release_port_protect(void); + +#endif + +/*******************************************************************************************************************//** + * Initialize the Master-MPU settings. + **********************************************************************************************************************/ +void bsp_master_mpu_init (void) +{ + /* Disable register protection for Master-MPU related registers. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SYSTEM); + + for (uint8_t region_num = 0; region_num < BSP_PRV_MASTER_MPU_REGION_NUM; region_num++) + { +#if (1 == BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED) + R_MPU0->RGN[region_num].STADD = g_bsp_master_mpu0_cfg[region_num][0]; + R_MPU0->RGN[region_num].ENDADD = g_bsp_master_mpu0_cfg[region_num][1]; +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED) + R_MPU1->RGN[region_num].STADD = g_bsp_master_mpu1_cfg[region_num][0]; + R_MPU1->RGN[region_num].ENDADD = g_bsp_master_mpu1_cfg[region_num][1]; +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED) + R_MPU2->RGN[region_num].STADD = g_bsp_master_mpu2_cfg[region_num][0]; + R_MPU2->RGN[region_num].ENDADD = g_bsp_master_mpu2_cfg[region_num][1]; +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED) + R_MPU3->RGN[region_num].STADD = g_bsp_master_mpu3_cfg[region_num][0]; + R_MPU3->RGN[region_num].ENDADD = g_bsp_master_mpu3_cfg[region_num][1]; +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED) + R_MPU4->RGN[region_num].STADD = g_bsp_master_mpu4_cfg[region_num][0]; + R_MPU4->RGN[region_num].ENDADD = g_bsp_master_mpu4_cfg[region_num][1]; +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED) + R_MPU6->RGN[region_num].STADD = g_bsp_master_mpu6_cfg[region_num][0]; + R_MPU6->RGN[region_num].ENDADD = g_bsp_master_mpu6_cfg[region_num][1]; +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED) + R_MPU7->RGN[region_num].STADD = g_bsp_master_mpu7_cfg[region_num][0]; + R_MPU7->RGN[region_num].ENDADD = g_bsp_master_mpu7_cfg[region_num][1]; +#endif +#if (1 == BSP_FEATURE_BSP_MASTER_MPU8_SUPPORTED) + R_MPU8->RGN[region_num].STADD = g_bsp_master_mpu8_cfg[region_num][0]; + R_MPU8->RGN[region_num].ENDADD = g_bsp_master_mpu8_cfg[region_num][1]; +#endif + } + + /* Enable register protection for Master-MPU related registers. */ + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SYSTEM); +} + +/*******************************************************************************************************************//** + * Initialize global system counter. The counter is enabled and is incrementing. + **********************************************************************************************************************/ +void bsp_global_system_counter_init (void) +{ + /* Initialize registers related the global system counter. */ + R_GSC->CNTCR &= (uint32_t) (~R_GSC_CNTCR_EN_Msk); + R_GSC->CNTFID0 = BSP_GLOBAL_SYSTEM_COUNTER_CLOCK_HZ; + R_GSC->CNTCVL = 0; + R_GSC->CNTCVU = 0; + R_GSC->CNTCR |= R_GSC_CNTCR_EN_Msk; +} + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. + * This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user + * implemented version. One of the main uses for this function is to call functional safety code during the startup + * process. To use this function just copy this function into your own code and modify it to meet your needs. + * + * @param[in] event Where the code currently is in the start up process + * + * + * @note All programs to be executed when BSP_WARM_START_RESET or BSP_WARM_START_POST_CLOCK event occurs should be + * placed in BTCM. These events occur before copying the application program in startup code is executed, and + * therefore the application program is located on ROM and cannot be executed at that time. + * Linker script for FSP specifies that .warm_start section is to be placed at BTCM. Adding the section + * designation to function or variable definition makes it easy to place at BTCM. + **********************************************************************************************************************/ +void R_BSP_WarmStart (bsp_warm_start_event_t event) +{ + if (BSP_WARM_START_RESET == event) + { + /* C runtime environment has not been setup so you cannot use globals. System clocks are not setup. */ + } + + if (BSP_WARM_START_POST_CLOCK == event) + { + /* C runtime environment has not been setup so you cannot use globals. Clocks have been initialized. */ + } + else if (BSP_WARM_START_POST_C == event) + { + /* C runtime environment, system clocks, and pins are all setup. */ + } + else + { + /* Do nothing */ + } +} + +/** @} (end addtogroup BSP_MCU) */ + +#if BSP_CFG_C_RUNTIME_INIT + +/*******************************************************************************************************************//** + * Copy the loader data block from external Flash to internal RAM. + **********************************************************************************************************************/ +void bsp_loader_data_init (void) +{ + #if (!defined(__GNUC__) || !(BSP_CFG_RAM_EXECUTION)) + + /* Define destination/source address pointer and block size */ + uintptr_t * src; + uintptr_t * dst; + uintptr_t size; + + /* Copy loader data block */ + src = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_ROM_ADDRESS; + dst = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_RAM_START; + size = (uintptr_t) BSP_PRV_SECTION_LDR_DATA_RAM_END - (uintptr_t) BSP_PRV_SECTION_LDR_DATA_RAM_START; + bsp_copy_multibyte(src, dst, size); + #endif +} + +/*******************************************************************************************************************//** + * Clear the loader bss block in internal RAM. + **********************************************************************************************************************/ +void bsp_loader_bss_init (void) +{ + /* Define source address pointer and block size */ + uintptr_t * src; + uintptr_t size; + + /* Clear loader bss block. */ + src = (uintptr_t *) BSP_PRV_SECTION_LDR_DATA_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_LDR_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_LDR_DATA_BSS_START; + bsp_bss_init_multibyte(src, size); + + #if BSP_CFG_RAM_EXECUTION + #if defined(__ICCARM__) + + /* Initialize the application data and clear the application bss. + * This code is for RAM Execution. If you want to boot with ROM, + * enable app_copy and app_bss_init, and disable this code. + * Also need to change icf file. */ + __iar_data_init3(); + #elif defined(__GNUC__) + + /* Clear application bss block. */ + src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_START; + bsp_bss_init_multibyte(src, size); + #endif + + /* Clear non-cache buffer block. */ + src = (uintptr_t *) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_END - + (uintptr_t) BSP_PRV_SECTION_NONCACHE_BUFFER_BSS_START; + bsp_bss_init_multibyte(src, size); + + /* Clear shared non-cache buffer block. */ + src = (uintptr_t *) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_END - + (uintptr_t) BSP_PRV_SECTION_SHARED_NONCACHE_BUFFER_BSS_START; + bsp_bss_init_multibyte(src, size); + + /* Clear DMAC link mode data block. */ + src = (uintptr_t *) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_END - + (uintptr_t) BSP_PRV_SECTION_DMAC_LINK_MODE_BSS_START; + bsp_bss_init_multibyte(src, size); + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Copy the memory block from Source address to Destination address by the multi byte unit. + **********************************************************************************************************************/ +void bsp_copy_multibyte (uintptr_t * src, uintptr_t * dst, uintptr_t bytesize) +{ + uintptr_t i; + uintptr_t cnt; + + uintptr_t src_mod; + uint8_t * src_single_byte; + uint8_t * dst_single_byte; + + if (0 != bytesize) + { + /* Copy Count in single byte unit */ + src_mod = (uintptr_t) src % sizeof(uintptr_t); + + if (0 != src_mod) + { + src_single_byte = (uint8_t *) src; + dst_single_byte = (uint8_t *) dst; + + for (i = 0; i < src_mod; i++) + { + *dst_single_byte++ = *src_single_byte++; + } + + dst = (uintptr_t *) dst_single_byte; + src = (uintptr_t *) src_single_byte; + bytesize -= src_mod; + } + else + { + /* Do nothing */ + } + + /* Copy Count in multi byte unit */ + cnt = (bytesize + (sizeof(uintptr_t) - 1)) / sizeof(uintptr_t); + + for (i = 0; i < cnt; i++) + { + *dst++ = *src++; + } + + /* Ensuring data-changing */ + __asm volatile ("DSB SY"); + } + else + { + /* Do nothing */ + } +} + +/*******************************************************************************************************************//** + * Clear the bss block by the multi byte unit. + **********************************************************************************************************************/ +void bsp_bss_init_multibyte (uintptr_t * src, uintptr_t bytesize) +{ + uintptr_t i; + uintptr_t cnt; + uintptr_t zero = 0; + + uintptr_t src_mod; + uint8_t * src_single_byte; + uint8_t zero_single_byte = 0; + + if (0 != bytesize) + { + /* Clear Count in single byte unit */ + src_mod = (uintptr_t) src % sizeof(uintptr_t); + + if (0 != src_mod) + { + src_single_byte = (uint8_t *) src; + + for (i = 0; i < src_mod; i++) + { + *src_single_byte++ = zero_single_byte; + } + + src = (uintptr_t *) src_single_byte; + bytesize -= src_mod; + } + else + { + /* Do nothing */ + } + + /* Clear Count in multi byte unit */ + cnt = (bytesize + (sizeof(uintptr_t) - 1)) / sizeof(uintptr_t); + + for (i = 0; i < cnt; i++) + { + *src++ = zero; + } + + /* Ensuring data-changing */ + __asm volatile ("DSB SY"); + } + else + { + /* Do nothing */ + } +} + +#if !(BSP_CFG_RAM_EXECUTION) + +/*******************************************************************************************************************//** + * Copy the application program block from external Flash to internal RAM. + **********************************************************************************************************************/ +void bsp_copy_to_ram (void) +{ + /* Define destination/source address pointer and block size */ + uintptr_t * src; + uintptr_t * dst; + uintptr_t size; + + /* Copy exception vector block */ + src = (uintptr_t *) BSP_PRV_SECTION_VECTOR_ROM_ADDRESS; + dst = (uintptr_t *) BSP_PRV_SECTION_VECTOR_RAM_START; + size = (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_END - (uintptr_t) BSP_PRV_SECTION_VECTOR_RAM_START; + bsp_copy_multibyte(src, dst, size); + + /* Copy user program block */ + src = (uintptr_t *) BSP_PRV_SECTION_USER_PRG_ROM_ADDRESS; + dst = (uintptr_t *) BSP_PRV_SECTION_USER_PRG_RAM_START; + size = (uintptr_t) BSP_PRV_SECTION_USER_PRG_RAM_END - (uintptr_t) BSP_PRV_SECTION_USER_PRG_RAM_START; + bsp_copy_multibyte(src, dst, size); + + /* Copy user data block */ + src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_ROM_ADDRESS; + dst = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_RAM_START; + size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_RAM_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_RAM_START; + bsp_copy_multibyte(src, dst, size); + + /* Copy user data_noncache block */ + src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_NONCACHE_ROM_ADDRESS; + dst = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START; + size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_END - + (uintptr_t) BSP_PRV_SECTION_USER_DATA_NONCACHE_RAM_START; + bsp_copy_multibyte(src, dst, size); +} + +/*******************************************************************************************************************//** + * Clear the application bss block in internal RAM. + **********************************************************************************************************************/ +void bsp_application_bss_init (void) +{ + /* Define source address pointer and block size */ + uintptr_t * src; + uintptr_t size; + + /* Clear application bss block. */ + src = (uintptr_t *) BSP_PRV_SECTION_USER_DATA_BSS_START; + size = (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_END - (uintptr_t) BSP_PRV_SECTION_USER_DATA_BSS_START; + bsp_bss_init_multibyte(src, size); +} + +#endif + +#if BSP_FEATURE_TFU_SUPPORTED +void bsp_tfu_init (void) +{ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET); + R_BSP_MODULE_START(FSP_IP_TFU, 0U); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET); +} + +#endif + +#if !BSP_CFG_PORT_PROTECT +void bsp_release_port_protect (void) +{ + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO); + R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO); +} + +#endif + +/*******************************************************************************************************************//** + * Initialize static constructors. + **********************************************************************************************************************/ +#if BSP_CFG_C_RUNTIME_INIT +void bsp_static_constructor_init (void) +{ + #if defined(__ICCARM__) + #if !(BSP_CFG_RAM_EXECUTION) + + /* In the case of ROM boot, initialization of static constructors is performed by __iar_data_init3(). */ + __iar_data_init3(); + #endif + #elif defined(__GNUC__) + intptr_t count; + intptr_t i; + + count = __preinit_array_end - __preinit_array_start; + for (i = 0; i < count; i++) + { + __preinit_array_start[i](); + } + + count = __init_array_end - __init_array_start; + for (i = 0; i < count; i++) + { + __init_array_start[i](); + } + #endif +} + +#endif + +/* This vector table is for SGI and PPI interrupts. */ +BSP_DONT_REMOVE fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES] = +{ + NULL, /* INTID0 : SOFTWARE_GENERATE_INT0 */ + NULL, /* INTID1 : SOFTWARE_GENERATE_INT1 */ + NULL, /* INTID2 : SOFTWARE_GENERATE_INT2 */ + NULL, /* INTID3 : SOFTWARE_GENERATE_INT3 */ + NULL, /* INTID4 : SOFTWARE_GENERATE_INT4 */ + NULL, /* INTID5 : SOFTWARE_GENERATE_INT5 */ + NULL, /* INTID6 : SOFTWARE_GENERATE_INT6 */ + NULL, /* INTID7 : SOFTWARE_GENERATE_INT7 */ + NULL, /* INTID8 : SOFTWARE_GENERATE_INT8 */ + NULL, /* INTID9 : SOFTWARE_GENERATE_INT9 */ + NULL, /* INTID10 : SOFTWARE_GENERATE_INT10 */ + NULL, /* INTID11 : SOFTWARE_GENERATE_INT11 */ + NULL, /* INTID12 : SOFTWARE_GENERATE_INT12 */ + NULL, /* INTID13 : SOFTWARE_GENERATE_INT13 */ + NULL, /* INTID14 : SOFTWARE_GENERATE_INT14 */ + NULL, /* INTID15 : SOFTWARE_GENERATE_INT15 */ + NULL, /* INTID16 : RESERVED */ + NULL, /* INTID17 : RESERVED */ + NULL, /* INTID18 : RESERVED */ + NULL, /* INTID19 : RESERVED */ + NULL, /* INTID20 : RESERVED */ + NULL, /* INTID21 : RESERVED */ + NULL, /* INTID22 : DEBUG_COMMUNICATIONS_CHANNEL_INT */ + NULL, /* INTID23 : PERFORMANCE_MONITOR_COUNTER_OVERFLOW_INT */ + NULL, /* INTID24 : CROSS_TRIGGER_INTERFACE_INT */ + NULL, /* INTID25 : VIRTUAL_CPU_INTERFACE_MAINTENANCE_INT */ + NULL, /* INTID26 : HYPERVISOR_TIMER_INT */ + NULL, /* INTID27 : VIRTUAL_TIMER_INT */ + NULL, /* INTID28 : RESERVED */ + NULL, /* INTID29 : RESERVED */ + NULL, /* INTID30 : NON-SECURE_PHYSICAL_TIMER_INT */ + NULL, /* INTID31 : RESERVED */ +}; diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_cache.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_cache.c new file mode 100644 index 00000000000..4a42d4ca6c1 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_cache.c @@ -0,0 +1,752 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_PRV_SCTLR_ELX_BIT_I (0x1000U) +#define BSP_PRV_SCTLR_ELX_BIT_C (0x4U) +#define BSP_PRV_SCTLR_ELX_BIT_M (0x1U) + +#define BSP_PRV_CLIDR_CTYPE_OFFSET (3U) +#define BSP_PRV_CLIDR_CTYPE_MASK (7U) +#define BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE (2U) +#define BSP_PRV_CLIDR_LOC_OFFSET (24U) +#define BSP_PRV_CLIDR_LOC_MASK (7U) + +#define BSP_PRV_CCSIDR_LINESIZE_OFFSET (0U) +#define BSP_PRV_CCSIDR_LINESIZE_MASK (7U) +#define BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE (4U) +#define BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET (3U) +#define BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK (0x3FFU) +#define BSP_PRV_CCSIDR_NUMSETS_OFFSET (13U) +#define BSP_PRV_CCSIDR_NUMSETS_MASK (0x7FFFU) +#define BSP_PRV_CCSIDR_SHIFT_MAX (32U) + +#define BSP_PRV_CSSELR_LEVEL_OFFSET (1U) + +#define BSP_PRV_CTR_IMINLINE_OFFSET (0U) +#define BSP_PRV_CTR_IMINLINE_MASK (0xFU) +#define BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS (4U) +#define BSP_PRV_CTR_IMINLINE_ADDRESS_MASK (1U) +#define BSP_PRV_CTR_DMINLINE_OFFSET (16U) +#define BSP_PRV_CTR_DMINLINE_MASK (0xFU) +#define BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS (4U) +#define BSP_PRV_CTR_DMINLINE_ADDRESS_MASK (1U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enable instruction caching. + **********************************************************************************************************************/ +void R_BSP_CacheEnableInst (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr |= BSP_PRV_SCTLR_ELX_BIT_I; + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Enable data caching. + **********************************************************************************************************************/ +void R_BSP_CacheEnableData (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr |= BSP_PRV_SCTLR_ELX_BIT_C; + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Enable memory protect. + **********************************************************************************************************************/ +void R_BSP_CacheEnableMemoryProtect (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr |= BSP_PRV_SCTLR_ELX_BIT_M; + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Disable instruction caching. + **********************************************************************************************************************/ +void R_BSP_CacheDisableInst (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_I); + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Disable data caching. + **********************************************************************************************************************/ +void R_BSP_CacheDisableData (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_C); + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Disable memory protect. + **********************************************************************************************************************/ +void R_BSP_CacheDisableMemoryProtect (void) +{ + uintptr_t sctlr; + + sctlr = __get_SCTLR(); + sctlr &= ~(BSP_PRV_SCTLR_ELX_BIT_M); + + __asm volatile ("DSB SY"); + + __set_SCTLR(sctlr); + + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Clean data cache by set/way. + * Clean means writing the cache data to memory and clear the dirty bits + * if there is a discrepancy between the cache and memory data. + **********************************************************************************************************************/ +void R_BSP_CacheCleanAll (void) +{ + uintptr_t clidr; + uintptr_t clidr_loc; + uintptr_t clidr_ctype; + uintptr_t clidr_ctype_shift; + + uintptr_t csselr; + uintptr_t csselr_level; + + uintptr_t ccsidr; + uintptr_t ccsidr_linesize; + uintptr_t ccsidr_associativity; + uintptr_t ccsidr_associativity_clz; + uintptr_t ccsidr_associativity_value; + uintptr_t ccsidr_associativity_msb; + uintptr_t ccsidr_numsets; + uintptr_t ccsidr_numsets_total; + + uintptr_t dccsw; + + __asm volatile ("DSB SY"); + + __set_ICIALLU(0); + + __asm volatile ("DMB SY"); + + /* Reads the maximum level of cache implemented */ + clidr = __get_CLIDR(); + clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK; + + /* If the cache does not exist, do not process */ + if (0 != clidr_loc) + { + /* Loop until all levels of cache are processed */ + for (csselr = 0; csselr < clidr_loc; csselr++) + { + /* Read the current level cache type */ + clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET; + clidr_ctype = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK; + + /* If no data cache exists in the current level of cache, do not process */ + if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype) + { + /* Set the current level to Cache Size Selection Register */ + csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET; + __set_CSSELR(csselr_level); + + __asm volatile ("DSB SY"); + + /* Read the line size, number of ways, and number of sets for the current level of cache */ + ccsidr = __get_CCSIDR(); + ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) + + BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE; + ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) & + BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK; + ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK; + + /* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */ + ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity); + if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz) + { + ccsidr_associativity_clz--; + } + else + { + /* Do Nothing */ + } + + /* Loop until all sets are processed */ + while (1) + { + /* Working copy of number of ways */ + ccsidr_associativity_value = ccsidr_associativity; + + /* Loop until all ways are processed */ + while (1) + { + ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) | + csselr_level; /* Left shift way */ + ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize; /* Left shift set */ + dccsw = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */ + + /* DCCSW - Data or unified Cache line Clean by Set/Way */ + __set_DCCSW(dccsw); + + if (0 != ccsidr_associativity_value) + { + ccsidr_associativity_value--; + } + else + { + break; + } + } + + if (0 != ccsidr_numsets) + { + ccsidr_numsets--; + } + else + { + break; + } + } + } + else + { + /* Do Nothing */ + } + } + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); + } + else + { + /* Do Nothing */ + } +} + +/*******************************************************************************************************************//** + * Invalidate data cache by set/way. + * Also Invalidate instruction cache. + * + * Invalidate means to delete cache data. + **********************************************************************************************************************/ +void R_BSP_CacheInvalidateAll (void) +{ + uintptr_t clidr; + uintptr_t clidr_loc; + uintptr_t clidr_ctype; + uintptr_t clidr_ctype_shift; + + uintptr_t csselr; + uintptr_t csselr_level; + + uintptr_t ccsidr; + uintptr_t ccsidr_linesize; + uintptr_t ccsidr_associativity; + uintptr_t ccsidr_associativity_clz; + uintptr_t ccsidr_associativity_value; + uintptr_t ccsidr_associativity_msb; + uintptr_t ccsidr_numsets; + uintptr_t ccsidr_numsets_total; + + uintptr_t dcisw; + + __asm volatile ("DSB SY"); + + __set_ICIALLU(0); + + __asm volatile ("DMB SY"); + + /* Reads the maximum level of cache implemented */ + clidr = __get_CLIDR(); + clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK; + + /* If the cache does not exist, do not process */ + if (0 != clidr_loc) + { + /* Loop until all levels of cache are processed */ + for (csselr = 0; csselr < clidr_loc; csselr++) + { + /* Read the current level cache type */ + clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET; + clidr_ctype = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK; + + /* If no data cache exists in the current level of cache, do not process */ + if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype) + { + /* Set the current level to Cache Size Selection Register */ + csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET; + __set_CSSELR(csselr_level); + + __asm volatile ("DSB SY"); + + /* Read the line size, number of ways, and number of sets for the current level of cache */ + ccsidr = __get_CCSIDR(); + ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) + + BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE; + ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) & + BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK; + ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK; + + /* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */ + ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity); + if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz) + { + ccsidr_associativity_clz--; + } + else + { + /* Do Nothing */ + } + + /* Loop until all sets are processed */ + while (1) + { + /* Working copy of number of ways */ + ccsidr_associativity_value = ccsidr_associativity; + + /* Loop until all ways are processed */ + while (1) + { + ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) | + csselr_level; /* Left shift way */ + ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize; /* Left shift set */ + dcisw = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */ + + /* DCISW - Data or unified Cache line Invalidate by Set/Way */ + __set_DCISW(dcisw); + + if (0 != ccsidr_associativity_value) + { + ccsidr_associativity_value--; + } + else + { + break; + } + } + + if (0 != ccsidr_numsets) + { + ccsidr_numsets--; + } + else + { + break; + } + } + } + else + { + /* Do Nothing */ + } + } + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); + } + else + { + /* Do Nothing */ + } +} + +/*******************************************************************************************************************//** + * Clean and Invalidate data cache by set/way. + * Also Invalidate instruction cache. + * + * Clean means writing the cache data to memory and clear the dirty bits + * if there is a discrepancy between the cache and memory data. + * + * Invalidate means to delete cache data. + **********************************************************************************************************************/ +void R_BSP_CacheCleanInvalidateAll (void) +{ + uintptr_t clidr; + uintptr_t clidr_loc; + uintptr_t clidr_ctype; + uintptr_t clidr_ctype_shift; + + uintptr_t csselr; + uintptr_t csselr_level; + + uintptr_t ccsidr; + uintptr_t ccsidr_linesize; + uintptr_t ccsidr_associativity; + uintptr_t ccsidr_associativity_clz; + uintptr_t ccsidr_associativity_value; + uintptr_t ccsidr_associativity_msb; + uintptr_t ccsidr_numsets; + uintptr_t ccsidr_numsets_total; + + uintptr_t dccisw; + + __asm volatile ("DSB SY"); + + __set_ICIALLU(0); + + __asm volatile ("DMB SY"); + + /* Reads the maximum level of cache implemented */ + clidr = __get_CLIDR(); + clidr_loc = (clidr >> BSP_PRV_CLIDR_LOC_OFFSET) & BSP_PRV_CLIDR_LOC_MASK; + + /* If the cache does not exist, do not process */ + if (0 != clidr_loc) + { + /* Loop until all levels of cache are processed */ + for (csselr = 0; csselr < clidr_loc; csselr++) + { + /* Read the current level cache type */ + clidr_ctype_shift = csselr * BSP_PRV_CLIDR_CTYPE_OFFSET; + clidr_ctype = (clidr >> clidr_ctype_shift) & BSP_PRV_CLIDR_CTYPE_MASK; + + /* If no data cache exists in the current level of cache, do not process */ + if (BSP_PRV_CLIDR_CTYPE_EXIST_DATACACHE <= clidr_ctype) + { + /* Set the current level to Cache Size Selection Register */ + csselr_level = csselr << BSP_PRV_CSSELR_LEVEL_OFFSET; + __set_CSSELR(csselr_level); + + __asm volatile ("DSB SY"); + + /* Read the line size, number of ways, and number of sets for the current level of cache */ + ccsidr = __get_CCSIDR(); + ccsidr_linesize = ((ccsidr >> BSP_PRV_CCSIDR_LINESIZE_OFFSET) & BSP_PRV_CCSIDR_LINESIZE_MASK) + + BSP_PRV_CCSIDR_LINESIZE_ACTUAL_VALUE; + ccsidr_associativity = (ccsidr >> BSP_PRV_CCSIDR_ASSOCIATIVITY_OFFSET) & + BSP_PRV_CCSIDR_ASSOCIATIVITY_MASK; + ccsidr_numsets = (ccsidr >> BSP_PRV_CCSIDR_NUMSETS_OFFSET) & BSP_PRV_CCSIDR_NUMSETS_MASK; + + /* Count consecutive number of 0 starting from the most significant bit (CLZ = Count Leading Zeros) */ + ccsidr_associativity_clz = __CLZ((uint32_t) ccsidr_associativity); + if (BSP_PRV_CCSIDR_SHIFT_MAX == ccsidr_associativity_clz) + { + ccsidr_associativity_clz--; + } + else + { + /* Do Nothing */ + } + + /* Loop until all sets are processed */ + while (1) + { + /* Working copy of number of ways */ + ccsidr_associativity_value = ccsidr_associativity; + + /* Loop until all ways are processed */ + while (1) + { + ccsidr_associativity_msb = (ccsidr_associativity_value << ccsidr_associativity_clz) | + csselr_level; /* Left shift way */ + ccsidr_numsets_total = ccsidr_numsets << ccsidr_linesize; /* Left shift set */ + dccisw = ccsidr_associativity_msb | ccsidr_numsets_total; /* Combine set and way */ + + /* DCCISW - Data or unified Cache line Clean and Invalidate by Set/Way */ + __set_DCCISW(dccisw); + + if (0 != ccsidr_associativity_value) + { + ccsidr_associativity_value--; + } + else + { + break; + } + } + + if (0 != ccsidr_numsets) + { + ccsidr_numsets--; + } + else + { + break; + } + } + } + else + { + /* Do Nothing */ + } + } + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); + } + else + { + /* Do Nothing */ + } +} + +/*******************************************************************************************************************//** + * Clean data cache and Invalidate instruction cache by address. + * + * Clean means writing the cache data to memory and clear the dirty bits + * if there is a discrepancy between the cache and memory data. + * + * Invalidate means to delete cache data. + * + * @param[in] base_address Start address of area you want to Clean. + * @param[in] length Size of area you want to Clean. + **********************************************************************************************************************/ +void R_BSP_CacheCleanRange (uintptr_t base_address, uintptr_t length) +{ + uintptr_t end_address; + uintptr_t ctr; + + uintptr_t dminline; + uintptr_t dminline_size; + uintptr_t dccvac; + + uintptr_t iminline; + uintptr_t iminline_size; + uintptr_t icivau; + + end_address = base_address + length; + + /* Calculate data cache line size */ + ctr = __get_CTR(); + dminline = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK; + dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline); + + /* Align base address with cache line */ + dccvac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK); + do + { + /* Data or unified Cache line Clean by VA to PoC */ + __set_DCCVAC(dccvac); + + dccvac += dminline_size; /* Next data line */ + } while (end_address > dccvac); + + __asm volatile ("DSB SY"); + + /* Calculate instruction cache line size */ + iminline = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK; + iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline); + + /* Align base address with cache line */ + icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK); + do + { + /* Instruction Cache line Invalidate by VA to PoU */ + __set_ICIVAU(icivau); + + icivau += iminline_size; /* Next data line */ + } while (end_address == icivau); + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Invalidate instruction and data cache by address. + * + * Invalidate means to delete cache data. + * + * @param[in] base_address Start address of area you want to Invalidate. + * @param[in] length Size of area you want to Invalidate. + **********************************************************************************************************************/ +void R_BSP_CacheInvalidateRange (uintptr_t base_address, uintptr_t length) +{ + uintptr_t end_address; + uintptr_t ctr; + + uintptr_t dminline; + uintptr_t dminline_size; + uintptr_t dcivac; + + uintptr_t iminline; + uintptr_t iminline_size; + uintptr_t icivau; + + end_address = base_address + length; + + /* Calculate data cache line size */ + ctr = __get_CTR(); + dminline = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK; + dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline); + + /* Align base address with cache line */ + dcivac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK); + do + { + /* Data or unified Cache line Invalidate by VA to PoC */ + __set_DCIVAC(dcivac); + + dcivac += dminline_size; /* Next data line */ + } while (end_address > dcivac); + + __asm volatile ("DSB SY"); + + /* Calculate instruction cache line size */ + iminline = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK; + iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline); + + /* Align base address with cache line */ + icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK); + do + { + /* Instruction Cache line Invalidate by VA to PoU */ + __set_ICIVAU(icivau); + + icivau += iminline_size; /* Next data line */ + } while (end_address == icivau); + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Clean and Invalidate data cache and Invalidate instruction cache by address. + * + * Clean means writing the cache data to memory and clear the dirty bits + * if there is a discrepancy between the cache and memory data. + * + * Invalidate means to delete cache data. + * + * @param[in] base_address Start address of area you want to Clean and Invalidate. + * @param[in] length Size of area you want to Clean and Invalidate. + **********************************************************************************************************************/ +void R_BSP_CacheCleanInvalidateRange (uintptr_t base_address, uintptr_t length) +{ + uintptr_t end_address; + uintptr_t ctr; + + uintptr_t dminline; + uintptr_t dminline_size; + uintptr_t dccivac; + + uintptr_t iminline; + uintptr_t iminline_size; + uintptr_t icivau; + + end_address = base_address + length; + + /* Calculate data cache line size */ + ctr = __get_CTR(); + dminline = (ctr >> BSP_PRV_CTR_DMINLINE_OFFSET) & BSP_PRV_CTR_DMINLINE_MASK; + dminline_size = (BSP_PRV_CTR_DMINLINE_NUMBER_OF_WORDS << dminline); + + /* Align base address with cache line */ + dccivac = base_address & ~(dminline_size - BSP_PRV_CTR_DMINLINE_ADDRESS_MASK); + do + { + /* Data or unified Cache line Clean and Invalidate by VA to PoC */ + __set_DCCIVAC(dccivac); + + dccivac += dminline_size; /* Next data line */ + } while (end_address > dccivac); + + __asm volatile ("DSB SY"); + + /* Calculate instruction cache line size */ + iminline = (ctr >> BSP_PRV_CTR_IMINLINE_OFFSET) & BSP_PRV_CTR_IMINLINE_MASK; + iminline_size = (BSP_PRV_CTR_IMINLINE_NUMBER_OF_WORDS << iminline); + + /* Align base address with cache line */ + icivau = base_address & ~(iminline_size - BSP_PRV_CTR_IMINLINE_ADDRESS_MASK); + do + { + /* Instruction Cache line Invalidate by VA to PoU */ + __set_ICIVAU(icivau); + + icivau += iminline_size; /* Next data line */ + } while (end_address == icivau); + + __asm volatile ("DSB SY"); + __asm volatile ("ISB SY"); +} + +/*******************************************************************************************************************//** + * Powers on and off the L3 cache way. + * CA55 only. + **********************************************************************************************************************/ +void R_BSP_CacheL3PowerCtrl (void) +{ + r_bsp_cache_l3_power_ctrl(); +} + +/*******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU) + **********************************************************************************************************************/ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_cache.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_cache.h new file mode 100644 index 00000000000..8f311e8c5dc --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_cache.h @@ -0,0 +1,67 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_CACHE_H +#define BSP_CACHE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(BSP_CFG_CORE_CR52) + #include "cr/bsp_cache_core.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void R_BSP_CacheEnableInst(void); +void R_BSP_CacheEnableData(void); +void R_BSP_CacheEnableMemoryProtect(void); +void R_BSP_CacheDisableInst(void); +void R_BSP_CacheDisableData(void); +void R_BSP_CacheDisableMemoryProtect(void); +void R_BSP_CacheCleanAll(void); +void R_BSP_CacheInvalidateAll(void); +void R_BSP_CacheCleanInvalidateAll(void); +void R_BSP_CacheCleanRange(uintptr_t base_address, uintptr_t length); +void R_BSP_CacheInvalidateRange(uintptr_t base_address, uintptr_t length); +void R_BSP_CacheCleanInvalidateRange(uintptr_t base_address, uintptr_t length); +void R_BSP_CacheL3PowerCtrl(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_clocks.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_clocks.c new file mode 100644 index 00000000000..8d7da17b406 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -0,0 +1,374 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_clocks.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) +#define BSP_PRV_PRCR_CGC_UNLOCK ((BSP_PRV_PRCR_KEY) | 0x1U) +#define BSP_PRV_PRCR_LOCK ((BSP_PRV_PRCR_KEY) | 0x0U) + +/* Key code for writing PCMD register. */ +#define BSP_PRV_PCMD_KEY (0xA5U) + +/* Calculate the value to write to SCKCR. */ +#define BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS (BSP_CFG_FSELXSPI0_DIVSELXSPI0 & 0x47U) +#define BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS ((BSP_CFG_FSELXSPI1_DIVSELXSPI1 & 0x47U) << 8U) +#define BSP_PRV_STARTUP_SCKCR_CKIO_BITS ((BSP_CFG_CKIO & 7U) << 16U) +#define BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS ((BSP_CFG_FSELCANFD & 1U) << 20U) +#define BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS ((BSP_CFG_PHYSEL & 1U) << 21U) +#define BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS ((BSP_CFG_CLMASEL & 1U) << 22U) +#define BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS ((BSP_CFG_SPI0ASYNCCLK & 1U) << 24U) +#define BSP_PRV_STARTUP_SCKCR_SPI1ASYNCSEL_BITS ((BSP_CFG_SPI1ASYNCCLK & 1U) << 25U) +#define BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS ((BSP_CFG_SPI2ASYNCCLK & 1U) << 26U) +#define BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS ((BSP_CFG_SCI0ASYNCCLK & 1U) << 27U) +#define BSP_PRV_STARTUP_SCKCR_SCI1ASYNCSEL_BITS ((BSP_CFG_SCI1ASYNCCLK & 1U) << 28U) +#define BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS ((BSP_CFG_SCI2ASYNCCLK & 1U) << 29U) +#define BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS ((BSP_CFG_SCI3ASYNCCLK & 1U) << 30U) +#define BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS ((BSP_CFG_SCI4ASYNCCLK & 1U) << 31U) + +/* Calculate the value to write to SCKCR2. */ +#define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS (BSP_CFG_FSELCPU0 & 3U) +#define BSP_PRV_STARTUP_SCKCR2_RESERVED_BIT4_BITS (1U << 4U) // The write value should be 1. +#define BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS ((BSP_CFG_DIVSELSUB & 1U) << 5U) +#define BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS ((BSP_CFG_SPI3ASYNCCLK & 1U) << 24U) +#define BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS ((BSP_CFG_SCI5ASYNCCLK & 1U) << 25U) + +#define BSP_PRV_STARTUP_SCKCR (BSP_PRV_STARTUP_SCKCR_FSELXSPI0_DIVSELXSPI0_BITS | \ + BSP_PRV_STARTUP_SCKCR_FSELXSPI1_DIVSELXSPI1_BITS | \ + BSP_PRV_STARTUP_SCKCR_CKIO_BITS | \ + BSP_PRV_STARTUP_SCKCR_FSELCANFD_BITS | \ + BSP_PRV_STARTUP_SCKCR_PHYSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_CLMASEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SPI0ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SPI1ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SPI2ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SCI0ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SCI1ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SCI2ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SCI3ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR_SCI4ASYNCSEL_BITS) + +#define BSP_PRV_STARTUP_SCKCR2 (BSP_PRV_STARTUP_SCKCR2_FSELCPU0_BITS | \ + BSP_PRV_STARTUP_SCKCR2_RESERVED_BIT4_BITS | \ + BSP_PRV_STARTUP_SCKCR2_DIVSELSUB_BITS | \ + BSP_PRV_STARTUP_SCKCR2_SPI3ASYNCSEL_BITS | \ + BSP_PRV_STARTUP_SCKCR2_SCI5ASYNCSEL_BITS) + +#define BSP_PRV_STARTUP_SCKCR2_FSELCPU0_ICLK_MUL2 (BSP_CLOCKS_FSELCPU0_ICLK_MUL2 << \ + R_SYSC_S_SCKCR2_FSELCPU0_Pos) + +/* Calculate the value to write to HIZCTRLEN. */ +#define BSP_PRV_STARTUP_HIZCTRLEN ((BSP_CFG_CLMA1MASK << 2) | (BSP_CFG_CLMA0MASK << 1) | \ + BSP_CFG_CLMA3MASK) + +/* Frequencies of clocks. */ +#define BSP_PRV_CPU_FREQ_200_MHZ (200000000U) // CPU frequency is 200 MHz +#define BSP_PRV_CPU_FREQ_150_MHZ (150000000U) // CPU frequency is 150 MHz + +/* Command sequence for enabling CLMA. */ +#define BSP_PRV_CTL0_ENABLE_TARGET_CMD (0x01) +#define BSP_PRV_CTL0_ENABLE_REVERSED_CMD (0xFE) + +#define BSP_PRV_LOCO_STABILIZATION_COUNT (40000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +#if !BSP_CFG_SOFT_RESET_SUPPORTED +static void bsp_prv_clock_set_hard_reset(void); + +#endif + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Update SystemCoreClock variable based on current clock settings. + **********************************************************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t devselsub = R_SYSC_S->SCKCR2_b.DIVSELSUB; + uint32_t fselcpu = (R_SYSC_S->SCKCR2_b.FSELCPU0 & 1U); + + if (0U == devselsub) + { + SystemCoreClock = BSP_PRV_CPU_FREQ_200_MHZ << fselcpu; + } + else + { + SystemCoreClock = BSP_PRV_CPU_FREQ_150_MHZ << fselcpu; + } +} + +/*******************************************************************************************************************//** + * Applies system core clock source and divider changes. The MCU is expected to be in high speed mode during this + * configuration and the CGC registers are expected to be unlocked in PRCR. + * + * @param[in] sckcr Value to set in SCKCR register + * @param[in] sckcr2 Value to set in SCKCR2 register + **********************************************************************************************************************/ +void bsp_prv_clock_set (uint32_t sckcr, uint32_t sckcr2) +{ + volatile uint32_t dummy; + sckcr = sckcr & BSP_PRV_SCKCR_MASK; + sckcr2 = sckcr2 & BSP_PRV_SCKCR2_MASK; + + /* Set the system source clock */ + R_SYSC_S->SCKCR2 = sckcr2; + + /** In order to secure processing after clock frequency is changed, + * dummy read the same register at least eight times. + * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */ + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + + R_SYSC_NS->SCKCR = sckcr; + + /** In order to secure processing after clock frequency is changed, + * dummy read the same register at least eight times. + * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */ + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + + FSP_PARAMETER_NOT_USED(dummy); + + /* Clock is now at requested frequency. */ + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClockUpdate(); +} + +#if !BSP_CFG_SOFT_RESET_SUPPORTED + +static void bsp_prv_clock_set_hard_reset (void) +{ + volatile uint32_t dummy; + uint32_t sckcr = BSP_PRV_STARTUP_SCKCR & BSP_PRV_SCKCR_MASK; + uint32_t sckcr2 = BSP_PRV_STARTUP_SCKCR2 & BSP_PRV_SCKCR2_MASK; + + /* Set the system source clock */ + R_SYSC_S->SCKCR2 = sckcr2; + + /** In order to secure processing after clock frequency is changed, + * dummy read the same register at least eight times. + * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */ + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + dummy = R_SYSC_S->SCKCR2; + + R_SYSC_NS->SCKCR = sckcr; + + /** In order to secure processing after clock frequency is changed, + * dummy read the same register at least eight times. + * Refer to "Notes on Clock Generation Circuit" in the RZ microprocessor manual. */ + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + dummy = R_SYSC_NS->SCKCR; + + FSP_PARAMETER_NOT_USED(dummy); + + /* Clock is now at requested frequency. */ + + /* Update the CMSIS core clock variable so that it reflects the new ICLK frequency. */ + SystemCoreClockUpdate(); +} + +#endif + +/*******************************************************************************************************************//** + * Initializes system clocks. Makes no assumptions about current register settings. + **********************************************************************************************************************/ +void bsp_clock_init (void) +{ + volatile uint32_t dummy = 0; + + /* Unlock CGC protection registers. */ + R_RWP_NS->PRCRN = (uint16_t) BSP_PRV_PRCR_CGC_UNLOCK; + R_RWP_S->PRCRS = (uint16_t) BSP_PRV_PRCR_CGC_UNLOCK; + + /* The SystemCoreClock needs to be updated before calling R_BSP_SoftwareDelay. */ + SystemCoreClockUpdate(); + + /* Set source clock and dividers. */ +#if BSP_CFG_SOFT_RESET_SUPPORTED + bsp_prv_clock_set(BSP_PRV_STARTUP_SCKCR, BSP_PRV_STARTUP_SCKCR2); +#else + bsp_prv_clock_set_hard_reset(); +#endif + +#if (BSP_CLOCKS_PLL1_INITIAL != BSP_CFG_PLL1) + R_SYSC_S->PLL1EN = BSP_CFG_PLL1; +#endif + +#if (BSP_CLOCKS_LOCO_ENABLE == BSP_CFG_LOCO_ENABLE) + R_SYSC_S->LOCOCR = BSP_CLOCKS_LOCO_ENABLE; + + /* Only start using the LOCO clock after + * the LOCO oscillation stabilization time (tLOCOWT) has elapsed. */ + for (uint16_t i = 0; i < BSP_PRV_LOCO_STABILIZATION_COUNT; i++) + { + __asm volatile ("nop"); + } +#endif + + R_SYSC_S->HIZCTRLEN = BSP_PRV_STARTUP_HIZCTRLEN; + +#if (BSP_CLOCKS_CLMA0_ENABLE == BSP_CFG_CLMA0_ENABLE) + + /* Set the lower and upper limit for comparing frequency domains. */ + R_CLMA0->CMPL = BSP_CFG_CLMA0_CMPL; + R_CLMA0->CMPH = BSP_CFG_CLMA0_CMPH; + + /* Enabling CLMA0 operation. */ + do + { + R_CLMA0->PCMD = BSP_PRV_PCMD_KEY; + + R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; + R_CLMA0->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + + if (1 != R_CLMA0->CTL0) + { + /* Check the value of PROTSR register. */ + dummy = R_CLMA0->PROTSR; + } + } while (1 == R_CLMA0->PROTSR_b.PRERR); +#endif + +#if (BSP_CLOCKS_CLMA1_ENABLE == BSP_CFG_CLMA1_ENABLE) + + /* Set the lower and upper limit for comparing frequency domains. */ + R_CLMA1->CMPL = BSP_CFG_CLMA1_CMPL; + R_CLMA1->CMPH = BSP_CFG_CLMA1_CMPH; + + /* Enabling CLMA1 operation. */ + do + { + R_CLMA1->PCMD = BSP_PRV_PCMD_KEY; + + R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; + R_CLMA1->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + + if (1 != R_CLMA1->CTL0) + { + /* Check the value of PROTSR register. */ + dummy = R_CLMA1->PROTSR; + } + } while (1 == R_CLMA1->PROTSR_b.PRERR); +#endif + +#if (BSP_CLOCKS_CLMA2_ENABLE == BSP_CFG_CLMA2_ENABLE) + + /* Set the lower and upper limit for comparing frequency domains. */ + R_CLMA2->CMPL = BSP_CFG_CLMA2_CMPL; + R_CLMA2->CMPH = BSP_CFG_CLMA2_CMPH; + + /* Enabling CLMA2 operation. */ + do + { + R_CLMA2->PCMD = BSP_PRV_PCMD_KEY; + + R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; + R_CLMA2->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + + if (1 != R_CLMA2->CTL0) + { + /* Check the value of PROTSR register. */ + dummy = R_CLMA2->PROTSR; + } + } while (1 == R_CLMA2->PROTSR_b.PRERR); +#endif + +#if (BSP_CLOCKS_CLMA3_ENABLE == BSP_CFG_CLMA3_ENABLE) + + /* Set the lower and upper limit for comparing frequency domains. */ + R_CLMA3->CMPL = BSP_CFG_CLMA3_CMPL; + R_CLMA3->CMPH = BSP_CFG_CLMA3_CMPH; + + /* Enabling CLMA3 operation. */ + do + { + R_CLMA3->PCMD = BSP_PRV_PCMD_KEY; + + R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_REVERSED_CMD; + R_CLMA3->CTL0 = BSP_PRV_CTL0_ENABLE_TARGET_CMD; + + if (1 != R_CLMA3->CTL0) + { + /* Check the value of PROTSR register. */ + dummy = R_CLMA3->PROTSR; + } + } while (1 == R_CLMA3->PROTSR_b.PRERR); +#endif + + /* Lock CGC and LPM protection registers. */ + R_RWP_NS->PRCRN = (uint16_t) BSP_PRV_PRCR_LOCK; + R_RWP_S->PRCRS = (uint16_t) BSP_PRV_PRCR_LOCK; + + FSP_PARAMETER_NOT_USED(dummy); +} + +/** @} (end addtogroup BSP_MCU_PRV) */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_clocks.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_clocks.h new file mode 100644 index 00000000000..b292987ccd9 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -0,0 +1,221 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_CLOCKS_H +#define BSP_CLOCKS_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_clock_cfg.h" +#include "bsp_api.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Startup clock frequency of each system clock. These macros are only helpful if the system clock and dividers have + * not changed since startup. These macros are not used in FSP modules except for the clock startup code. */ + +/* xSPI unit0 clock options. */ +#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_133_3_MHZ (0x02) // xSPI0 base clock 800MHz and xSPI0 clock 133.3MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_100_0_MHZ (0x03) // xSPI0 base clock 800MHz and xSPI0 clock 100.0 MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_50_0_MHZ (0x04) // xSPI0 base clock 800MHz and xSPI0 clock 50.0 MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_25_0_MHZ (0x05) // xSPI0 base clock 800MHz and xSPI0 clock 25.0 MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ (0x06) // xSPI0 base clock 800MHz and xSPI0 clock 12.5 MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV1_75_0_MHZ (0x43) // xSPI0 base clock 600MHz and xSPI0 clock 75.0 MHz. +#define BSP_CLOCKS_XSPI0_CLOCK_DIV1_37_5_MHZ (0x44) // xSPI0 base clock 600MHz and xSPI0 clock 37.5 MHz. + +/* xSPI unit1 clock options. */ +#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_133_3_MHZ (0x02) // xSPI1 base clock 800MHz and xSPI1 clock 133.3MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_100_0_MHZ (0x03) // xSPI1 base clock 800MHz and xSPI1 clock 100.0 MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_50_0_MHZ (0x04) // xSPI1 base clock 800MHz and xSPI1 clock 50.0 MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_25_0_MHZ (0x05) // xSPI1 base clock 800MHz and xSPI1 clock 25.0 MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ (0x06) // xSPI1 base clock 800MHz and xSPI1 clock 12.5 MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV1_75_0_MHZ (0x43) // xSPI1 base clock 600MHz and xSPI1 clock 75.0 MHz. +#define BSP_CLOCKS_XSPI1_CLOCK_DIV1_37_5_MHZ (0x44) // xSPI1 base clock 600MHz and xSPI1 clock 37.5 MHz. + +/* CKIO clock options. */ +#define BSP_CLOCKS_CKIO_ICLK_DIV2 (0) // CKIO clock 100.0 MHz (when SCKCR2.DIVSELSUB = 0), + // or 75.0 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV3 (1) // CKIO clock 66.7 MHz (when SCKCR2.DIVSELSUB = 0), + // or 50.0 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV4 (2) // CKIO clock 50.0 MHz (when SCKCR2.DIVSELSUB = 0), + // or 37.5 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV5 (3) // CKIO clock 40.0 MHz (when SCKCR2.DIVSELSUB = 0), + // or 30.0 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV6 (4) // CKIO clock 33.3 MHz (when SCKCR2.DIVSELSUB = 0), + // or 25.0 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV7 (5) // CKIO clock 28.6 MHz (when SCKCR2.DIVSELSUB = 0), + // or 21.4 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_CKIO_ICLK_DIV8 (6) // CKIO clock 25.0 MHz (when SCKCR2.DIVSELSUB = 0), + // or 18.75 MHz (when SCKCR2.DIVSELSUB = 1). + +/* CANFD clock options. */ +#define BSP_CLOCKS_CANFD_CLOCK_80_MHZ (0) // CANFD clock 80 MHz. +#define BSP_CLOCKS_CANFD_CLOCK_40_MHZ (1) // CANFD clock 40 MHz. + +/* Ethernet PHY reference clock (ETHn_REFCLK : n = 0 to 2) options. */ +#define BSP_CLOCKS_PHYSEL_PLL1_DIV (0) // PLL1 devider clock. +#define BSP_CLOCKS_PHYSEL_MAINOSC_DIV (1) // Main clock oscillator. + +/* Alternative clock options when main clock abnormal oscillation is detected in CLMA3. */ +#define BSP_CLOCKS_CLMASEL_LOCO (0) // LOCO clock. +#define BSP_CLOCKS_CLMASEL_PLL (1) // PLL clock. + +/* SPI clock options. */ +#define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI0 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI0 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI1 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI1 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI2 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI2 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SPI3 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SPI3 asynchronous serial clock 96.0 MHz. + +/* SCI clock options. */ +#define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI0 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI0 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI1 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI1 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI2 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI2 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI3 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI3 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI4 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI4 asynchronous serial clock 96.0 MHz. +#define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_75_MHZ (0) // SCI5 asynchronous serial clock 75.0 MHz. +#define BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ (1) // SCI5 asynchronous serial clock 96.0 MHz. + +/* CPU0 clock options. */ +#define BSP_CLOCKS_FSELCPU0_ICLK_MUL2 (1) // CPU0 clock 400 MHz (when SCKCR2.DIVSELSUB = 0), + // or 300 MHz (when SCKCR2.DIVSELSUB = 1). +#define BSP_CLOCKS_FSELCPU0_ICLK_MUL1 (0) // CPU0 clock 200 MHz (when SCKCR2.DIVSELSUB = 0), + // or 150 MHz (when SCKCR2.DIVSELSUB = 1). + +/* Peripheral module base clock options. */ +#define BSP_CLOCKS_DIVSELSUB_0 (0) // ICLK:200MHz, PCLKH:200MHz, PCLKM:100MHz, + // PCLKL:50MHz, PCLKADC:25MHz, PCLKGPTL:400MHz. +#define BSP_CLOCKS_DIVSELSUB_1 (1) // ICLK:150MHz, PCLKH:150MHz, PCLKM:75 MHz, + // PCLKL:37.5MHz, PCLKADC:18.75MHz, PCLKGPTL:300MHz. + +/* LOCO enable options. */ +#define BSP_CLOCKS_LOCO_DISABLE (0) // LOCO Stop +#define BSP_CLOCKS_LOCO_ENABLE (1) // LOCO Run + +/* PLL1 enable options. */ +#define BSP_CLOCKS_PLL1_INITIAL (0xFF) // Initial (This value should not be reflected in the register) +#define BSP_CLOCKS_PLL1_STANDBY (0) // PLL1 is standby state. +#define BSP_CLOCKS_PLL1_NORMAL (1) // PLL1 is normal state. + +/* CLMA error mask options. */ +#define BSP_CLOCKS_CLMA0_ERROR_MASK (0) // CLMA0 error is not transferred to POE3 and POEG. +#define BSP_CLOCKS_CLMA0_ERROR_NOT_MASK (1) // CLMA0 error is transferred to POE3 and POEG. +#define BSP_CLOCKS_CLMA1_ERROR_MASK (0) // CLMA1 error is not transferred to POE3 and POEG. +#define BSP_CLOCKS_CLMA1_ERROR_NOT_MASK (1) // CLMA1 error is transferred to POE3 and POEG. +#define BSP_CLOCKS_CLMA3_ERROR_MASK (0) // CLMA3 error is not transferred to POE3 and POEG. +#define BSP_CLOCKS_CLMA3_ERROR_NOT_MASK (1) // CLMA3 error is transferred to POE3 and POEG. + +/* CLMA enable options. */ +#define BSP_CLOCKS_CLMA0_DISABLE (0) // Disable CLMA0 operation. +#define BSP_CLOCKS_CLMA0_ENABLE (1) // Enable CLMA0 operation. +#define BSP_CLOCKS_CLMA1_DISABLE (0) // Disable CLMA1 operation. +#define BSP_CLOCKS_CLMA1_ENABLE (1) // Enable CLMA1 operation. +#define BSP_CLOCKS_CLMA2_DISABLE (0) // Disable CLMA2 operation. +#define BSP_CLOCKS_CLMA2_ENABLE (1) // Enable CLMA2 operation. +#define BSP_CLOCKS_CLMA3_DISABLE (0) // Disable CLMA3 operation. +#define BSP_CLOCKS_CLMA3_ENABLE (1) // Enable CLMA3 operation. + +/* Create a mask of valid bits in SCKCR. */ +#define BSP_PRV_SCKCR_FSELXSPI0_MASK (7U << 0) +#define BSP_PRV_SCKCR_DIVSELXSPI0_MASK (1U << 6) +#define BSP_PRV_SCKCR_FSELXSPI1_MASK (7U << 8) +#define BSP_PRV_SCKCR_DIVSELXSPI1_MASK (1U << 14) +#define BSP_PRV_SCKCR_CKIO_MASK (7U << 16) +#define BSP_PRV_SCKCR_FSELCANFD_MASK (1U << 20) +#define BSP_PRV_SCKCR_PHYSEL_MASK (1U << 21) +#define BSP_PRV_SCKCR_CLMASEL_MASK (1U << 22) +#define BSP_PRV_SCKCR_SPI0ASYNCSEL_MASK (1U << 24) +#define BSP_PRV_SCKCR_SPI1ASYNCSEL_MASK (1U << 25) +#define BSP_PRV_SCKCR_SPI2ASYNCSEL_MASK (1U << 26) +#define BSP_PRV_SCKCR_SCI0ASYNCSEL_MASK (1U << 27) +#define BSP_PRV_SCKCR_SCI1ASYNCSEL_MASK (1U << 28) +#define BSP_PRV_SCKCR_SCI2ASYNCSEL_MASK (1U << 29) +#define BSP_PRV_SCKCR_SCI3ASYNCSEL_MASK (1U << 30) +#define BSP_PRV_SCKCR_SCI4ASYNCSEL_MASK (1U << 31) +#define BSP_PRV_SCKCR_MASK (((((((((((((((BSP_PRV_SCKCR_FSELXSPI0_MASK | \ + BSP_PRV_SCKCR_DIVSELXSPI0_MASK) | \ + BSP_PRV_SCKCR_FSELXSPI1_MASK) | \ + BSP_PRV_SCKCR_DIVSELXSPI1_MASK) | \ + BSP_PRV_SCKCR_CKIO_MASK) | \ + BSP_PRV_SCKCR_FSELCANFD_MASK) | \ + BSP_PRV_SCKCR_PHYSEL_MASK) | \ + BSP_PRV_SCKCR_CLMASEL_MASK) | \ + BSP_PRV_SCKCR_SPI0ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SPI1ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SPI2ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SCI0ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SCI1ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SCI2ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SCI3ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR_SCI4ASYNCSEL_MASK) +#define BSP_PRV_SCKCR_DIVSELXSPI_MASK (BSP_PRV_SCKCR_DIVSELXSPI0_MASK | \ + BSP_PRV_SCKCR_DIVSELXSPI1_MASK) + +/* Create a mask of valid bits in SCKCR2. */ +#define BSP_PRV_SCKCR2_FSELCPU0_MASK (3U << 0) +#define BSP_PRV_SCKCR2_RESERVED_BIT4_MASK (1U << 4) +#define BSP_PRV_SCKCR2_DIVSELSUB_MASK (1U << 5) +#define BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK (1U << 24) +#define BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK (1U << 25) +#define BSP_PRV_SCKCR2_MASK ((((BSP_PRV_SCKCR2_FSELCPU0_MASK | \ + BSP_PRV_SCKCR2_RESERVED_BIT4_MASK) | \ + BSP_PRV_SCKCR2_DIVSELSUB_MASK) | \ + BSP_PRV_SCKCR2_SPI3ASYNCSEL_MASK) | \ + BSP_PRV_SCKCR2_SCI5ASYNCSEL_MASK) + +#define BSP_PRV_FSELCPU0_INIT (0x02U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_clock_init(void); // Used internally by BSP + +/* Used internally by CGC */ + +void bsp_prv_clock_set(uint32_t sckcr, uint32_t sckcr2); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_common.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_common.c new file mode 100644 index 00000000000..4f70b298c67 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_common.c @@ -0,0 +1,221 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ICCARM__) + #define WEAK_ERROR_ATTRIBUTE + #define WEAK_INIT_ATTRIBUTE + #pragma weak fsp_error_log = fsp_error_log_internal + #pragma weak bsp_init = bsp_init_internal +#elif defined(__GNUC__) + + #define WEAK_ERROR_ATTRIBUTE __attribute__((weak, alias("fsp_error_log_internal"))) + + #define WEAK_INIT_ATTRIBUTE __attribute__((weak, alias("bsp_init_internal"))) +#endif + +#define FSP_SECTION_VERSION ".version" + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* System clock frequency information */ +const uint32_t g_bsp_system_clock_select[][2] = +{ + {BSP_PRV_CPU_FREQ_200_MHZ, BSP_PRV_CPU_FREQ_150_MHZ }, // FSP_PRIV_CLOCK_CPU0 + {0, 0 }, // Reserved + {BSP_PRV_ICLK_FREQ_200_MHZ, BSP_PRV_ICLK_FREQ_150_MHZ }, // FSP_PRIV_CLOCK_ICLK + {BSP_PRV_PCLKH_FREQ_200_MHZ, BSP_PRV_PCLKH_FREQ_150_MHZ }, // FSP_PRIV_CLOCK_PCLKH + {BSP_PRV_PCLKM_FREQ_100_MHZ, BSP_PRV_PCLKM_FREQ_75_MHZ }, // FSP_PRIV_CLOCK_PCLKM + {BSP_PRV_PCLKL_FREQ_50_MHZ, BSP_PRV_PCLKL_FREQ_37_5_MHZ }, // FSP_PRIV_CLOCK_PCLKL + {BSP_PRV_PCLKADC_FREQ_25_MHZ, BSP_PRV_PCLKADC_FREQ_18_75_MHZ}, // FSP_PRIV_CLOCK_PCLKADC + {BSP_PRV_PCLKGPTL_FREQ_400_MHZ, BSP_PRV_PCLKGPTL_FREQ_300_MHZ }, // FSP_PRIV_CLOCK_PCLKGPTL + {BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI0 + {BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI1 + {BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI2 + {BSP_PRV_PCLKSPI_FREQ_75_MHZ, BSP_PRV_PCLKSPI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSPI3 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI0 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI1 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI2 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI3 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI4 + {BSP_PRV_PCLKSCI_FREQ_75_MHZ, BSP_PRV_PCLKSCI_FREQ_96_MHZ }, // FSP_PRIV_CLOCK_PCLKSCI5 + {BSP_PRV_PCLKCAN_FREQ_80_MHZ, BSP_PRV_PCLKCAN_FREQ_40_MHZ }, // FSP_PRIV_CLOCK_PCLKCAN +}; + +/* System clock frequency information for CKIO */ +const uint32_t g_bsp_system_clock_select_ckio[][2] = +{ + {BSP_PRV_CKIO_FREQ_100_MHZ, BSP_PRV_CKIO_FREQ_75_MHZ }, // CKIO = 000b + {BSP_PRV_CKIO_FREQ_66_7_MHZ, BSP_PRV_CKIO_FREQ_50_MHZ }, // CKIO = 001b + {BSP_PRV_CKIO_FREQ_50_MHZ, BSP_PRV_CKIO_FREQ_37_5_MHZ }, // CKIO = 010b + {BSP_PRV_CKIO_FREQ_40_MHZ, BSP_PRV_CKIO_FREQ_30_MHZ }, // CKIO = 011b + {BSP_PRV_CKIO_FREQ_33_3_MHZ, BSP_PRV_CKIO_FREQ_25_MHZ }, // CKIO = 100b + {BSP_PRV_CKIO_FREQ_28_6_MHZ, BSP_PRV_CKIO_FREQ_21_4_MHZ }, // CKIO = 101b + {BSP_PRV_CKIO_FREQ_25_MHZ, BSP_PRV_CKIO_FREQ_18_75_MHZ }, // CKIO = 110b + {BSP_PRV_CKIO_FREQ_NOT_SUPPORTED, BSP_PRV_CKIO_FREQ_NOT_SUPPORTED}, // CKIO = 111b +}; + +/* System clock frequency information for XSPI_CLK */ +const uint32_t g_bsp_system_clock_select_xspi_clk[][2] = +{ + {BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 000b + {BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 001b + {BSP_PRV_XSPI_CLK_FREQ_133_3_MHZ, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 010b + {BSP_PRV_XSPI_CLK_FREQ_100_MHZ, BSP_PRV_XSPI_CLK_FREQ_75_MHZ }, // FSELXSPIn = 011b + {BSP_PRV_XSPI_CLK_FREQ_50_MHZ, BSP_PRV_XSPI_CLK_FREQ_37_5_MHZ }, // FSELXSPIn = 100b + {BSP_PRV_XSPI_CLK_FREQ_25_MHZ, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 101b + {BSP_PRV_XSPI_CLK_FREQ_12_5_MHZ, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 110b + {BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED, BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED}, // FSELXSPIn = 111b +}; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/* FSP pack version structure. */ +static BSP_DONT_REMOVE const fsp_pack_version_t g_fsp_version BSP_PLACE_IN_SECTION (FSP_SECTION_VERSION) = +{ + .version_id_b = + { + .minor = FSP_VERSION_MINOR, + .major = FSP_VERSION_MAJOR, + .build = FSP_VERSION_BUILD, + .patch = FSP_VERSION_PATCH + } +}; + +/* Public FSP version name. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_STRING; + +/* Unique FSP version ID. */ +static BSP_DONT_REMOVE const uint8_t g_fsp_version_build_string[] BSP_PLACE_IN_SECTION(FSP_SECTION_VERSION) = + FSP_VERSION_BUILD_STRING; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/** Prototype of initialization function called before main. This prototype sets the weak association of this + * function to an internal example implementation. If this function is defined in the application code, the + * application code version is used. */ + +void bsp_init(void * p_args) WEAK_INIT_ATTRIBUTE; + +void bsp_init_internal(void * p_args); /// Default initialization function + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of function called before errors are returned in FSP code if BSP_CFG_ERROR_LOG is set to 1. This + * prototype sets the weak association of this function to an internal example implementation. */ + +void fsp_error_log(fsp_err_t err, const char * file, int32_t line) WEAK_ERROR_ATTRIBUTE; + +void fsp_error_log_internal(fsp_err_t err, const char * file, int32_t line); /// Default error logger function + +#endif + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Get the FSP version based on compile time macros. + * + * @param[out] p_version Memory address to return version information to. + * + * @retval FSP_SUCCESS Version information stored. + * @retval FSP_ERR_ASSERTION The parameter p_version is NULL. + **********************************************************************************************************************/ +fsp_err_t R_FSP_VersionGet (fsp_pack_version_t * const p_version) +{ +#if BSP_CFG_PARAM_CHECKING_ENABLE + + /** Verify parameters are valid */ + FSP_ASSERT(NULL != p_version); +#endif + + *p_version = g_fsp_version; + + return FSP_SUCCESS; +} + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/*******************************************************************************************************************//** + * Default error logger function, used only if fsp_error_log is not defined in the user application. + * + * @param[in] err The error code encountered. + * @param[in] file The file name in which the error code was encountered. + * @param[in] line The line number at which the error code was encountered. + **********************************************************************************************************************/ +void fsp_error_log_internal (fsp_err_t err, const char * file, int32_t line) +{ + /** Do nothing. Do not generate any 'unused' warnings. */ + FSP_PARAMETER_NOT_USED(err); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); +} + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * Default initialization function, used only if bsp_init is not defined in the user application. + **********************************************************************************************************************/ +void bsp_init_internal (void * p_args) +{ + /* Do nothing. */ + FSP_PARAMETER_NOT_USED(p_args); +} + +#if defined(__ARMCC_VERSION) + +/*******************************************************************************************************************//** + * Default implementation of assert for AC6. + **********************************************************************************************************************/ +__attribute__((weak, noreturn)) +void __aeabi_assert (const char * expr, const char * file, int line) { + FSP_PARAMETER_NOT_USED(expr); + FSP_PARAMETER_NOT_USED(file); + FSP_PARAMETER_NOT_USED(line); + __BKPT(0); + while (1) + { + /* Do nothing. */ + } +} + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_common.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_common.h new file mode 100644 index 00000000000..f6f12905bc6 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_common.h @@ -0,0 +1,435 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_COMMON_H +#define BSP_COMMON_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* C99 includes. */ +#include +#include +#include +#include +#include + +/* Different compiler support. */ +#include "../../inc/fsp_common_api.h" +#include "bsp_compiler_support.h" +#include "bsp_cfg.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Used to signify that an ELC event is not able to be used as an interrupt. */ +#define BSP_IRQ_DISABLED (0xFFU) + +/* Vector Number offset */ +#define BSP_VECTOR_NUM_OFFSET (32) +#define BSP_INTERRUPT_TYPE_OFFSET (16U) + +#define FSP_CONTEXT_SAVE +#define FSP_CONTEXT_RESTORE + +#define BSP_PRV_CPU_FREQ_200_MHZ (200000000U) // CPU frequency is 200 MHz +#define BSP_PRV_CPU_FREQ_150_MHZ (150000000U) // CPU frequency is 150 MHz + +#define BSP_PRV_ICLK_FREQ_200_MHZ (200000000U) // ICLK frequency is 200 MHz +#define BSP_PRV_ICLK_FREQ_150_MHZ (150000000U) // ICLK frequency is 150 MHz + +#define BSP_PRV_PCLKH_FREQ_200_MHZ (200000000U) // PCLKH frequency is 200 MHz +#define BSP_PRV_PCLKH_FREQ_150_MHZ (150000000U) // PCLKH frequency is 150 MHz + +#define BSP_PRV_PCLKM_FREQ_100_MHZ (100000000U) // PCLKM frequency is 100 MHz +#define BSP_PRV_PCLKM_FREQ_75_MHZ (75000000U) // PCLKM frequency is 750 MHz + +#define BSP_PRV_PCLKL_FREQ_50_MHZ (50000000U) // PCLKL frequency is 50 MHz +#define BSP_PRV_PCLKL_FREQ_37_5_MHZ (37500000U) // PCLKL frequency is 37.5 MHz + +#define BSP_PRV_PCLKADC_FREQ_25_MHZ (25000000U) // PCLKADC frequency is 25 MHz +#define BSP_PRV_PCLKADC_FREQ_18_75_MHZ (18750000U) // PCLKADC frequency is 18.75 MHz + +#define BSP_PRV_PCLKGPTL_FREQ_400_MHZ (400000000U) // PCLKGPTL frequency is 400 MHz +#define BSP_PRV_PCLKGPTL_FREQ_300_MHZ (300000000U) // PCLKGPTL frequency is 300 MHz + +#define BSP_PRV_PCLKSCI_FREQ_75_MHZ (75000000U) // PCLKSCI frequency is 75 MHz +#define BSP_PRV_PCLKSCI_FREQ_96_MHZ (96000000U) // PCLKSCI frequency is 96 MHz + +#define BSP_PRV_PCLKSPI_FREQ_75_MHZ (75000000U) // PCLKSPI frequency is 75 MHz +#define BSP_PRV_PCLKSPI_FREQ_96_MHZ (96000000U) // PCLKSPI frequency is 96 MHz + +#define BSP_PRV_PCLKCAN_FREQ_80_MHZ (80000000U) // PCLKCAN frequency is 80 MHz +#define BSP_PRV_PCLKCAN_FREQ_40_MHZ (40000000U) // PCLKCAN frequency is 40 MHz + +#define BSP_PRV_CKIO_FREQ_100_MHZ (100000000U) // CKIO frequency is 100 MHz +#define BSP_PRV_CKIO_FREQ_75_MHZ (75000000U) // CKIO frequency is 75 MHz +#define BSP_PRV_CKIO_FREQ_66_7_MHZ (66666666U) // CKIO frequency is 66.7 MHz +#define BSP_PRV_CKIO_FREQ_50_MHZ (50000000U) // CKIO frequency is 50 MHz +#define BSP_PRV_CKIO_FREQ_40_MHZ (40000000U) // CKIO frequency is 40 MHz +#define BSP_PRV_CKIO_FREQ_37_5_MHZ (37500000U) // CKIO frequency is 37.5 MHz +#define BSP_PRV_CKIO_FREQ_33_3_MHZ (33333333U) // CKIO frequency is 33.3MHz +#define BSP_PRV_CKIO_FREQ_30_MHZ (30000000U) // CKIO frequency is 30 MHz +#define BSP_PRV_CKIO_FREQ_28_6_MHZ (28571428U) // CKIO frequency is 28.6 MHz +#define BSP_PRV_CKIO_FREQ_25_MHZ (25000000U) // CKIO frequency is 25 MHz +#define BSP_PRV_CKIO_FREQ_21_4_MHZ (21428571U) // CKIO frequency is 21.4 MHz +#define BSP_PRV_CKIO_FREQ_18_75_MHZ (18750000U) // CKIO frequency is 18.75 MHz +#define BSP_PRV_CKIO_FREQ_NOT_SUPPORTED (0xFFFFFFFFU) // CKIO frequency is not supported + +#define BSP_PRV_XSPI_CLK_FREQ_133_3_MHZ (133333333U) // XSPI_CLK frequency is 133.3 MHz +#define BSP_PRV_XSPI_CLK_FREQ_100_MHZ (100000000U) // XSPI_CLK frequency is 100.0 MHz +#define BSP_PRV_XSPI_CLK_FREQ_75_MHZ (75000000U) // XSPI_CLK frequency is 75.0 MHz +#define BSP_PRV_XSPI_CLK_FREQ_50_MHZ (50000000U) // XSPI_CLK frequency is 50.0 MHz +#define BSP_PRV_XSPI_CLK_FREQ_37_5_MHZ (37500000U) // XSPI_CLK frequency is 37.5 MHz +#define BSP_PRV_XSPI_CLK_FREQ_25_MHZ (25000000U) // XSPI_CLK frequency is 25.0 MHz +#define BSP_PRV_XSPI_CLK_FREQ_12_5_MHZ (12500000U) // XSPI_CLK frequency is 12.5 MHz +#define BSP_PRV_XSPI_CLK_FREQ_NOT_SUPPORTED (0xFFFFFFFFU) // XSPI_CLK frequency is not supported + +/** Macro to log and return error without an assertion. */ +#ifndef FSP_RETURN + + #define FSP_RETURN(err) FSP_ERROR_LOG((err)); \ + return err; +#endif + +/** This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in + * user code and do required debugging (breakpoints, stack dump, etc) in this function.*/ +#if (1 == BSP_CFG_ERROR_LOG) + + #ifndef FSP_ERROR_LOG + #define FSP_ERROR_LOG(err) \ + fsp_error_log((err), __FILE__, __LINE__); + #endif +#else + + #define FSP_ERROR_LOG(err) +#endif + +/** Default assertion calls ::FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP + * functions. */ +#if (3 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) +#elif (2 == BSP_CFG_ASSERT) + #define FSP_ASSERT(a) {assert(a);} +#else + #define FSP_ASSERT(a) FSP_ERROR_RETURN((a), FSP_ERR_ASSERTION) +#endif // ifndef FSP_ASSERT + +/** All FSP error codes are returned using this macro. Calls ::FSP_ERROR_LOG function if condition "a" is false. Used + * to identify runtime errors in FSP functions. */ + +#define FSP_ERROR_RETURN(a, err) \ + { \ + if ((a)) \ + { \ + (void) 0; /* Do nothing */ \ + } \ + else \ + { \ + FSP_ERROR_LOG(err); \ + return err; \ + } \ + } + +/* Function-like macro used to wait for a condition to be met, most often used to wait for hardware register updates. + * This macro can be redefined to add a timeout if necessary. */ +#ifndef FSP_HARDWARE_REGISTER_WAIT + #define FSP_HARDWARE_REGISTER_WAIT(reg, required_value) while (reg != required_value) { /* Wait. */} +#endif + +/* Function-like macro used to wait for a condition to be met with timeout, + * most often used to wait for hardware register updates. */ +#define BSP_HARDWARE_REGISTER_WAIT_WTIH_TIMEOUT(reg, required_value, timeout) \ + while ((timeout)) \ + { \ + if ((required_value) == (reg)) \ + { \ + break; \ + } \ + (timeout)--; \ + } + +#ifndef BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION + #define BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION (0U) +#endif + +/* This macro defines a variable for saving previous mask value */ +#ifndef FSP_CRITICAL_SECTION_DEFINE + + #define FSP_CRITICAL_SECTION_DEFINE uintptr_t old_mask_level = 0U +#endif + +/* These macros abstract methods to save and restore the interrupt state. */ +#define FSP_CRITICAL_SECTION_GET_CURRENT_STATE __get_ICC_PMR +#define FSP_CRITICAL_SECTION_SET_STATE __set_ICC_PMR +#define FSP_CRITICAL_SECTION_IRQ_MASK_SET ((uint8_t) (BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION << \ + BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT)) + +/** This macro temporarily saves the current interrupt state and disables interrupts. */ +#ifndef FSP_CRITICAL_SECTION_ENTER + #define FSP_CRITICAL_SECTION_ENTER \ + old_mask_level = FSP_CRITICAL_SECTION_GET_CURRENT_STATE(); \ + FSP_CRITICAL_SECTION_SET_STATE(FSP_CRITICAL_SECTION_IRQ_MASK_SET) +#endif + +/** This macro restores the previously saved interrupt state, reenabling interrupts. */ +#ifndef FSP_CRITICAL_SECTION_EXIT + #define FSP_CRITICAL_SECTION_EXIT FSP_CRITICAL_SECTION_SET_STATE(old_mask_level) +#endif + +/* Number of Cortex processor exceptions. */ +#define FSP_PRIV_CORTEX_PROCESSOR_EXCEPTIONS (32U) + +/** Used to signify that the requested IRQ vector is not defined in this system. */ +#define FSP_INVALID_VECTOR ((IRQn_Type) - 33) + +/* This macro Enable or Disable interrupts. */ +#define BSP_INTERRUPT_ENABLE __asm volatile ("cpsie i"); \ + __asm volatile ("isb"); + +#define BSP_INTERRUPT_DISABLE __asm volatile ("cpsid i"); \ + __asm volatile ("isb"); + +/** In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will + * alert the user of the error. The user can override this default behavior by defining their own + * BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro. + */ +#if !defined(BSP_CFG_HANDLE_UNRECOVERABLE_ERROR) + + #define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x) __BKPT((x)) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Different warm start entry locations in the BSP. */ +typedef enum e_bsp_warm_start_event +{ + BSP_WARM_START_RESET = 0, ///< Called almost immediately after reset. No C runtime environment, clocks, or IRQs. + BSP_WARM_START_POST_CLOCK, ///< Called after clock initialization. No C runtime environment or IRQs. + BSP_WARM_START_POST_C ///< Called after clocks and C runtime environment have been set up +} bsp_warm_start_event_t; + +/* Private enum used in R_FSP_SystemClockHzGet. */ +typedef enum e_fsp_priv_clock +{ + FSP_PRIV_CLOCK_CPU0 = 0, + FSP_PRIV_CLOCK_ICLK = 2, + FSP_PRIV_CLOCK_PCLKH = 3, + FSP_PRIV_CLOCK_PCLKM = 4, + FSP_PRIV_CLOCK_PCLKL = 5, + FSP_PRIV_CLOCK_PCLKADC = 6, + FSP_PRIV_CLOCK_PCLKGPTL = 7, + FSP_PRIV_CLOCK_PCLKSPI0 = 8, + FSP_PRIV_CLOCK_PCLKSPI1 = 9, + FSP_PRIV_CLOCK_PCLKSPI2 = 10, + FSP_PRIV_CLOCK_PCLKSPI3 = 11, + FSP_PRIV_CLOCK_PCLKSCI0 = 12, + FSP_PRIV_CLOCK_PCLKSCI1 = 13, + FSP_PRIV_CLOCK_PCLKSCI2 = 14, + FSP_PRIV_CLOCK_PCLKSCI3 = 15, + FSP_PRIV_CLOCK_PCLKSCI4 = 16, + FSP_PRIV_CLOCK_PCLKSCI5 = 17, + FSP_PRIV_CLOCK_PCLKCAN = 18, + FSP_PRIV_CLOCK_CKIO = 19, + FSP_PRIV_CLOCK_XSPI0_CLK = 20, + FSP_PRIV_CLOCK_XSPI1_CLK = 21, +} fsp_priv_clock_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +extern const uint32_t g_bsp_system_clock_select[][2]; +extern const uint32_t g_bsp_system_clock_select_ckio[][2]; +extern const uint32_t g_bsp_system_clock_select_xspi_clk[][2]; + +extern IRQn_Type g_current_interrupt_num[]; +extern uint8_t g_current_interrupt_pointer; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Return active interrupt vector number value + * + * @return Active interrupt vector number value + **********************************************************************************************************************/ +__STATIC_INLINE IRQn_Type R_FSP_CurrentIrqGet (void) +{ + /* Return the current interrupt number. */ + return g_current_interrupt_num[(g_current_interrupt_pointer - 1U)]; +} + +/*******************************************************************************************************************//** + * Gets the frequency of a system clock. + * + * @return Frequency of requested clock in Hertz. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet (fsp_priv_clock_t clock) +{ + uint32_t clock_hz = 0; + uint32_t fselcpu0 = R_SYSC_S->SCKCR2_b.FSELCPU0; + + switch (clock) + { + case FSP_PRIV_CLOCK_CPU0: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.DIVSELSUB] << fselcpu0; + break; + } + + /* These iclk and pclk cases are intentionally combined. */ + case FSP_PRIV_CLOCK_ICLK: + case FSP_PRIV_CLOCK_PCLKH: + case FSP_PRIV_CLOCK_PCLKM: + case FSP_PRIV_CLOCK_PCLKL: + case FSP_PRIV_CLOCK_PCLKADC: + case FSP_PRIV_CLOCK_PCLKGPTL: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.DIVSELSUB]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSPI0: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SPI0ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSPI1: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SPI1ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSPI2: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SPI2ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSPI3: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.SPI3ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI0: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI0ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI1: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI1ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI2: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI2ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI3: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI3ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI4: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.SCI4ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKSCI5: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_S->SCKCR2_b.SCI5ASYNCSEL]; + break; + } + + case FSP_PRIV_CLOCK_PCLKCAN: + { + clock_hz = g_bsp_system_clock_select[clock][R_SYSC_NS->SCKCR_b.FSELCANFD]; + break; + } + + case FSP_PRIV_CLOCK_CKIO: + { + uint32_t ckio = R_SYSC_NS->SCKCR_b.CKIO; + clock_hz = g_bsp_system_clock_select_ckio[ckio][R_SYSC_S->SCKCR2_b.DIVSELSUB]; + break; + } + + case FSP_PRIV_CLOCK_XSPI0_CLK: + { + uint32_t fselxspi0 = R_SYSC_NS->SCKCR_b.FSELXSPI0; + clock_hz = g_bsp_system_clock_select_xspi_clk[fselxspi0][R_SYSC_NS->SCKCR_b.DIVSELXSPI0]; + break; + } + + case FSP_PRIV_CLOCK_XSPI1_CLK: + { + uint32_t fselxspi1 = R_SYSC_NS->SCKCR_b.FSELXSPI1; + clock_hz = g_bsp_system_clock_select_xspi_clk[fselxspi1][R_SYSC_NS->SCKCR_b.DIVSELXSPI1]; + break; + } + + default: + { + break; + } + } + + return clock_hz; +} + +#if ((1 == BSP_CFG_ERROR_LOG) || (1 == BSP_CFG_ASSERT)) + +/** Prototype of default function called before errors are returned in FSP code if BSP_CFG_LOG_ERRORS is set to 1. */ +void fsp_error_log(fsp_err_t err, const char * file, int32_t line); + +#endif + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h new file mode 100644 index 00000000000..d593dee9d60 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_compiler_support.h @@ -0,0 +1,110 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_COMPILER_SUPPORT_H +#define BSP_COMPILER_SUPPORT_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + #include +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) /* AC6 compiler */ + +/* The AC6 linker requires uninitialized code to be placed in a section that starts with ".bss." Without this, load + * memory (ROM) is reserved unnecessarily. */ + #define BSP_UNINIT_SECTION_PREFIX ".bss" + #define BSP_SECTION_HEAP BSP_UNINIT_SECTION_PREFIX ".heap" + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #define BSP_TARGET_ARM #pragma arm +#elif defined(__GNUC__) /* GCC compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_SECTION_HEAP ".heap" + #define BSP_DONT_REMOVE + #define BSP_ATTRIBUTE_STACKLESS __attribute__((naked)) + #define BSP_FORCE_INLINE __attribute__((always_inline)) + #define BSP_TARGET_ARM __attribute__((target("arm"))) +#elif defined(__ICCARM__) /* IAR compiler */ + #define BSP_UNINIT_SECTION_PREFIX + #define BSP_SECTION_HEAP "HEAP" + #define BSP_DONT_REMOVE __root + #define BSP_ATTRIBUTE_STACKLESS __stackless + #define BSP_FORCE_INLINE _Pragma("inline=forced") + #define BSP_TARGET_ARM __arm +#endif + +#define BSP_SECTION_FIQ_STACK BSP_UNINIT_SECTION_PREFIX ".fiq_stack" +#define BSP_SECTION_IRQ_STACK BSP_UNINIT_SECTION_PREFIX ".irq_stack" +#define BSP_SECTION_ABT_STACK BSP_UNINIT_SECTION_PREFIX ".abt_stack" +#define BSP_SECTION_UND_STACK BSP_UNINIT_SECTION_PREFIX ".und_stack" +#define BSP_SECTION_SYS_STACK BSP_UNINIT_SECTION_PREFIX ".sys_stack" +#define BSP_SECTION_SVC_STACK BSP_UNINIT_SECTION_PREFIX ".svc_stack" +#define BSP_SECTION_NOINIT BSP_UNINIT_SECTION_PREFIX ".noinit" +#define BSP_SECTION_FIXED_VECTORS ".fixed_vectors" +#define BSP_SECTION_APPLICATION_VECTORS ".application_vectors" +#define BSP_SECTION_ROM_REGISTERS ".rom_registers" +#define BSP_SECTION_ID_CODE ".id_code" +#define BSP_SECTION_LOADER_PARAM ".loader_param" + +/* Compiler neutral macros. */ +#define BSP_PLACE_IN_SECTION(x) __attribute__((section(x))) __attribute__((__used__)) + +#define BSP_ALIGN_VARIABLE(x) __attribute__((aligned(x))) + +#define BSP_PACKED __attribute__((aligned(1))) + +#define BSP_WEAK_REFERENCE __attribute__((weak)) + +/** Stacks (and heap) must be sized and aligned to an integer multiple of this number. */ +#define BSP_STACK_ALIGNMENT (8) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** @} (end of addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_delay.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_delay.c new file mode 100644 index 00000000000..e24d3f0abc8 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_delay.c @@ -0,0 +1,159 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "bsp_delay.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_DELAY_NS_PER_SECOND (1000000000) +#define BSP_DELAY_NS_PER_US (1000) +#define BSP_DELAY_SIGNIFICANT_DIGITS (10000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Delay for at least the specified duration in units and return. + * @param[in] delay The number of 'units' to delay. + * @param[in] units The 'base' (bsp_delay_units_t) for the units specified. Valid values are: + * BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.@n + * For example:@n + * At 200 MHz one cycle takes 1/200 microsecond or 5 nanoseconds.@n + * At 800 MHz one cycle takes 1/800 microsecond or 1.25 nanoseconds.@n + * Therefore one run through bsp_prv_software_delay_loop() takes: + * ~ (1.25 * BSP_DELAY_LOOP_CYCLES) or 5 ns. + * A delay of 2 us therefore requires 2000ns/5ns or 400 loops. + * + * The 'theoretical' maximum delay that may be obtained is determined by a full 32 bit loop count and the system clock rate. + * @200MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 200000000) = 85 seconds. + * @800MHz: ((0xFFFFFFFF loops * 4 cycles /loop) / 800000000) = 21 seconds. + * + * Note that requests for very large delays will be affected by rounding in the calculations and the actual delay + * achieved may be slightly longer. @200 MHz, for example, a request for 85 seconds will be closer to 86 seconds. + * + * Note also that if the calculations result in a loop_cnt of zero, the bsp_prv_software_delay_loop() function is not called + * at all. In this case the requested delay is too small (nanoseconds) to be carried out by the loop itself, and the + * overhead associated with executing the code to just get to this point has certainly satisfied the requested delay. + * + * + * @note R_BSP_SoftwareDelay() obtains the system clock value by reading the SystemCoreClock variable. + * Therefore, R_BSP_SoftwareDelay() cannot be used until after the SystemCoreClock has been updated. + * The SystemCoreClock is updated by executing SystemCoreClockUpdate() in startup; + * users cannot call R_BSP_SoftwareDelay() inside R_BSP_WarmStart(BSP_WARM_START_RESET) and + * R_BSP_WarmStart(BSP_WARM_START_POST_CLOCK) since they are invoked before SystemCoreClockUpdate() in startup. + * + * @note This function will delay for **at least** the specified duration. Due to overhead in calculating the correct number + * of loops to delay, very small delay values (generally 1-5 microseconds) may be significantly longer than specified. + * Approximate overhead for this function is as follows: + * - CR52: 87-94 cycles + * + * @note If more accurate microsecond timing must be performed in software it is recommended to use + * bsp_prv_software_delay_loop() directly. In this case, use BSP_DELAY_LOOP_CYCLES or BSP_DELAY_LOOPS_CALCULATE() + * to convert a calculated delay cycle count to a number of software delay loops. + * + * @note Delays may be longer than expected when compiler optimization is turned off. + **********************************************************************************************************************/ + +void R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units) +{ + uint32_t cpu_hz; + uint32_t cycles_requested; + uint32_t ns_per_cycle; + uint32_t loops_required = 0; + uint32_t total_us = (delay * units); /** Convert the requested time to microseconds. */ + uint64_t ns_64bits; + + cpu_hz = SystemCoreClock; /** Get the system clock frequency in Hz. */ + + /* BSP_DELAY_SIGNIFICANT_DIGITS to keep the decimal point. */ + ns_per_cycle = BSP_DELAY_NS_PER_SECOND / (cpu_hz / BSP_DELAY_SIGNIFICANT_DIGITS); /** Get the # of nanoseconds/cycle. */ + + /* We want to get the time in total nanoseconds but need to be conscious of overflowing 32 bits. We also do not want to do 64 bit */ + /* division as that pulls in a division library. */ + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + ns_64bits = ns_64bits * (uint64_t) BSP_DELAY_SIGNIFICANT_DIGITS; + + /* No, we will not overflow. + * Multiply the calculation result by BSP_DELAY_SIGNIFICANT_DIGITS to disable the retention of the decimal point.*/ + cycles_requested = (uint32_t) (ns_64bits / (uint64_t) ns_per_cycle); + loops_required = cycles_requested / BSP_DELAY_LOOP_CYCLES; + } + else + { + /* We did overflow. Try dividing down first. + * Multiply the calculation result by BSP_DELAY_SIGNIFICANT_DIGITS to disable the retention of the decimal point.*/ + total_us = (total_us / (ns_per_cycle * BSP_DELAY_LOOP_CYCLES)) * BSP_DELAY_SIGNIFICANT_DIGITS; + ns_64bits = (uint64_t) total_us * (uint64_t) BSP_DELAY_NS_PER_US; // Convert to ns. + + /* Have we overflowed 32 bits? */ + if (ns_64bits <= UINT32_MAX) + { + /* No, we will not overflow. */ + loops_required = (uint32_t) ns_64bits; + } + else + { + /* We still overflowed, use the max count for cycles */ + loops_required = UINT32_MAX; + } + } + + /** Only delay if the supplied parameters constitute a delay. */ + if (loops_required > (uint32_t) 0) + { + bsp_prv_software_delay_loop(loops_required); + } +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles + * occur when the loop exits. The 'naked' attribute indicates that the specified function does not need + * prologue/epilogue sequences generated by the compiler. + * @param[in] loop_cnt The number of loops to iterate. + **********************************************************************************************************************/ +void bsp_prv_software_delay_loop (uint32_t loop_cnt) +{ + r_bsp_software_delay_loop(loop_cnt); +} diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_delay.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_delay.h new file mode 100644 index 00000000000..82e69ab1188 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_delay.h @@ -0,0 +1,72 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_DELAY_H +#define BSP_DELAY_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(BSP_CFG_CORE_CR52) + #include "cr/bsp_delay_core.h" +#endif + +#include "bsp_compiler_support.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds */ +typedef enum +{ + BSP_DELAY_UNITS_SECONDS = 1000000, ///< Requested delay amount is in seconds + BSP_DELAY_UNITS_MILLISECONDS = 1000, ///< Requested delay amount is in milliseconds + BSP_DELAY_UNITS_MICROSECONDS = 1 ///< Requested delay amount is in microseconds +} bsp_delay_units_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void bsp_prv_software_delay_loop(uint32_t loop_cnt); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h new file mode 100644 index 00000000000..37b0468ac00 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_exceptions.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_EXCEPTIONS_H +#define BSP_EXCEPTIONS_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_io.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_io.c new file mode 100644 index 00000000000..4cf8a6285a6 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_io.c @@ -0,0 +1,41 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +volatile uint32_t g_protect_port_counter; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_io.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_io.h new file mode 100644 index 00000000000..0da51954ec8 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_io.h @@ -0,0 +1,544 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @defgroup BSP_IO BSP I/O access + * @ingroup RENESAS_COMMON + * @brief This module provides basic read/write/toggle access to port pins and read/write access to port. + * + * @{ + **********************************************************************************************************************/ + +#ifndef BSP_IO_H +#define BSP_IO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Private definition to set enumeration values. */ +#define BSP_IO_PRV_8BIT_MASK (0xFF) +#define BSP_IO_PM_OUTPUT (3U) + +/* Key code for writing PRCR register. */ +#define BSP_IO_PRV_PRCR_KEY (0xA500U) +#define BSP_IO_REG_PROTECT_GPIO (0x0004U) + +/* Difference between safety and non safety I/O port region addresses. */ +#define BSP_IO_REGION_ADDRESS_DIFF (R_PORT_SR_BASE - R_PORT_NSR_BASE) + +/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */ +#define BSP_IO_PRV_PORT_OFFSET (8U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** Levels that can be set and read for individual pins */ +typedef enum e_bsp_io_level +{ + BSP_IO_LEVEL_LOW = 0, ///< Low + BSP_IO_LEVEL_HIGH ///< High +} bsp_io_level_t; + +/** Direction of individual pins */ +typedef enum e_bsp_io_dir +{ + BSP_IO_DIRECTION_INPUT = 0, ///< Input + BSP_IO_DIRECTION_OUTPUT ///< Output +} bsp_io_direction_t; + +/** Superset list of all possible IO ports. */ +typedef enum e_bsp_io_port +{ + BSP_IO_PORT_00 = 0x0000, ///< IO port 0 + BSP_IO_PORT_01 = 0x0100, ///< IO port 1 + BSP_IO_PORT_02 = 0x0200, ///< IO port 2 + BSP_IO_PORT_03 = 0x0300, ///< IO port 3 + BSP_IO_PORT_04 = 0x0400, ///< IO port 4 + BSP_IO_PORT_05 = 0x0500, ///< IO port 5 + BSP_IO_PORT_06 = 0x0600, ///< IO port 6 + BSP_IO_PORT_07 = 0x0700, ///< IO port 7 + BSP_IO_PORT_08 = 0x0800, ///< IO port 8 + BSP_IO_PORT_09 = 0x0900, ///< IO port 9 + BSP_IO_PORT_10 = 0x0A00, ///< IO port 10 + BSP_IO_PORT_11 = 0x0B00, ///< IO port 11 + BSP_IO_PORT_12 = 0x0C00, ///< IO port 12 + BSP_IO_PORT_13 = 0x0D00, ///< IO port 13 + BSP_IO_PORT_14 = 0x0E00, ///< IO port 14 + BSP_IO_PORT_15 = 0x0F00, ///< IO port 15 + BSP_IO_PORT_16 = 0x1000, ///< IO port 16 + BSP_IO_PORT_17 = 0x1100, ///< IO port 17 + BSP_IO_PORT_18 = 0x1200, ///< IO port 18 + BSP_IO_PORT_19 = 0x1300, ///< IO port 19 + BSP_IO_PORT_20 = 0x1400, ///< IO port 20 + BSP_IO_PORT_21 = 0x1500, ///< IO port 21 + BSP_IO_PORT_22 = 0x1600, ///< IO port 22 + BSP_IO_PORT_23 = 0x1700, ///< IO port 23 + BSP_IO_PORT_24 = 0x1800, ///< IO port 24 +} bsp_io_port_t; + +/** Superset list of all possible IO port pins. */ +typedef enum e_bsp_io_port_pin +{ + BSP_IO_PORT_00_PIN_0 = 0x0000, ///< IO port 0 pin 0 + BSP_IO_PORT_00_PIN_1 = 0x0001, ///< IO port 0 pin 1 + BSP_IO_PORT_00_PIN_2 = 0x0002, ///< IO port 0 pin 2 + BSP_IO_PORT_00_PIN_3 = 0x0003, ///< IO port 0 pin 3 + BSP_IO_PORT_00_PIN_4 = 0x0004, ///< IO port 0 pin 4 + BSP_IO_PORT_00_PIN_5 = 0x0005, ///< IO port 0 pin 5 + BSP_IO_PORT_00_PIN_6 = 0x0006, ///< IO port 0 pin 6 + BSP_IO_PORT_00_PIN_7 = 0x0007, ///< IO port 0 pin 7 + + BSP_IO_PORT_01_PIN_0 = 0x0100, ///< IO port 1 pin 0 + BSP_IO_PORT_01_PIN_1 = 0x0101, ///< IO port 1 pin 1 + BSP_IO_PORT_01_PIN_2 = 0x0102, ///< IO port 1 pin 2 + BSP_IO_PORT_01_PIN_3 = 0x0103, ///< IO port 1 pin 3 + BSP_IO_PORT_01_PIN_4 = 0x0104, ///< IO port 1 pin 4 + BSP_IO_PORT_01_PIN_5 = 0x0105, ///< IO port 1 pin 5 + BSP_IO_PORT_01_PIN_6 = 0x0106, ///< IO port 1 pin 6 + BSP_IO_PORT_01_PIN_7 = 0x0107, ///< IO port 1 pin 7 + + BSP_IO_PORT_02_PIN_0 = 0x0200, ///< IO port 2 pin 0 + BSP_IO_PORT_02_PIN_1 = 0x0201, ///< IO port 2 pin 1 + BSP_IO_PORT_02_PIN_2 = 0x0202, ///< IO port 2 pin 2 + BSP_IO_PORT_02_PIN_3 = 0x0203, ///< IO port 2 pin 3 + BSP_IO_PORT_02_PIN_4 = 0x0204, ///< IO port 2 pin 4 + BSP_IO_PORT_02_PIN_5 = 0x0205, ///< IO port 2 pin 5 + BSP_IO_PORT_02_PIN_6 = 0x0206, ///< IO port 2 pin 6 + BSP_IO_PORT_02_PIN_7 = 0x0207, ///< IO port 2 pin 7 + + BSP_IO_PORT_03_PIN_0 = 0x0300, ///< IO port 3 pin 0 + BSP_IO_PORT_03_PIN_1 = 0x0301, ///< IO port 3 pin 1 + BSP_IO_PORT_03_PIN_2 = 0x0302, ///< IO port 3 pin 2 + BSP_IO_PORT_03_PIN_3 = 0x0303, ///< IO port 3 pin 3 + BSP_IO_PORT_03_PIN_4 = 0x0304, ///< IO port 3 pin 4 + BSP_IO_PORT_03_PIN_5 = 0x0305, ///< IO port 3 pin 5 + BSP_IO_PORT_03_PIN_6 = 0x0306, ///< IO port 3 pin 6 + BSP_IO_PORT_03_PIN_7 = 0x0307, ///< IO port 3 pin 7 + + BSP_IO_PORT_04_PIN_0 = 0x0400, ///< IO port 4 pin 0 + BSP_IO_PORT_04_PIN_1 = 0x0401, ///< IO port 4 pin 1 + BSP_IO_PORT_04_PIN_2 = 0x0402, ///< IO port 4 pin 2 + BSP_IO_PORT_04_PIN_3 = 0x0403, ///< IO port 4 pin 3 + BSP_IO_PORT_04_PIN_4 = 0x0404, ///< IO port 4 pin 4 + BSP_IO_PORT_04_PIN_5 = 0x0405, ///< IO port 4 pin 5 + BSP_IO_PORT_04_PIN_6 = 0x0406, ///< IO port 4 pin 6 + BSP_IO_PORT_04_PIN_7 = 0x0407, ///< IO port 4 pin 7 + + BSP_IO_PORT_05_PIN_0 = 0x0500, ///< IO port 5 pin 0 + BSP_IO_PORT_05_PIN_1 = 0x0501, ///< IO port 5 pin 1 + BSP_IO_PORT_05_PIN_2 = 0x0502, ///< IO port 5 pin 2 + BSP_IO_PORT_05_PIN_3 = 0x0503, ///< IO port 5 pin 3 + BSP_IO_PORT_05_PIN_4 = 0x0504, ///< IO port 5 pin 4 + BSP_IO_PORT_05_PIN_5 = 0x0505, ///< IO port 5 pin 5 + BSP_IO_PORT_05_PIN_6 = 0x0506, ///< IO port 5 pin 6 + BSP_IO_PORT_05_PIN_7 = 0x0507, ///< IO port 5 pin 7 + + BSP_IO_PORT_06_PIN_0 = 0x0600, ///< IO port 6 pin 0 + BSP_IO_PORT_06_PIN_1 = 0x0601, ///< IO port 6 pin 1 + BSP_IO_PORT_06_PIN_2 = 0x0602, ///< IO port 6 pin 2 + BSP_IO_PORT_06_PIN_3 = 0x0603, ///< IO port 6 pin 3 + BSP_IO_PORT_06_PIN_4 = 0x0604, ///< IO port 6 pin 4 + BSP_IO_PORT_06_PIN_5 = 0x0605, ///< IO port 6 pin 5 + BSP_IO_PORT_06_PIN_6 = 0x0606, ///< IO port 6 pin 6 + BSP_IO_PORT_06_PIN_7 = 0x0607, ///< IO port 6 pin 7 + + BSP_IO_PORT_07_PIN_0 = 0x0700, ///< IO port 7 pin 0 + BSP_IO_PORT_07_PIN_1 = 0x0701, ///< IO port 7 pin 1 + BSP_IO_PORT_07_PIN_2 = 0x0702, ///< IO port 7 pin 2 + BSP_IO_PORT_07_PIN_3 = 0x0703, ///< IO port 7 pin 3 + BSP_IO_PORT_07_PIN_4 = 0x0704, ///< IO port 7 pin 4 + BSP_IO_PORT_07_PIN_5 = 0x0705, ///< IO port 7 pin 5 + BSP_IO_PORT_07_PIN_6 = 0x0706, ///< IO port 7 pin 6 + BSP_IO_PORT_07_PIN_7 = 0x0707, ///< IO port 7 pin 7 + + BSP_IO_PORT_08_PIN_0 = 0x0800, ///< IO port 8 pin 0 + BSP_IO_PORT_08_PIN_1 = 0x0801, ///< IO port 8 pin 1 + BSP_IO_PORT_08_PIN_2 = 0x0802, ///< IO port 8 pin 2 + BSP_IO_PORT_08_PIN_3 = 0x0803, ///< IO port 8 pin 3 + BSP_IO_PORT_08_PIN_4 = 0x0804, ///< IO port 8 pin 4 + BSP_IO_PORT_08_PIN_5 = 0x0805, ///< IO port 8 pin 5 + BSP_IO_PORT_08_PIN_6 = 0x0806, ///< IO port 8 pin 6 + BSP_IO_PORT_08_PIN_7 = 0x0807, ///< IO port 8 pin 7 + + BSP_IO_PORT_09_PIN_0 = 0x0900, ///< IO port 9 pin 0 + BSP_IO_PORT_09_PIN_1 = 0x0901, ///< IO port 9 pin 1 + BSP_IO_PORT_09_PIN_2 = 0x0902, ///< IO port 9 pin 2 + BSP_IO_PORT_09_PIN_3 = 0x0903, ///< IO port 9 pin 3 + BSP_IO_PORT_09_PIN_4 = 0x0904, ///< IO port 9 pin 4 + BSP_IO_PORT_09_PIN_5 = 0x0905, ///< IO port 9 pin 5 + BSP_IO_PORT_09_PIN_6 = 0x0906, ///< IO port 9 pin 6 + BSP_IO_PORT_09_PIN_7 = 0x0907, ///< IO port 9 pin 7 + + BSP_IO_PORT_10_PIN_0 = 0x0A00, ///< IO port 10 pin 0 + BSP_IO_PORT_10_PIN_1 = 0x0A01, ///< IO port 10 pin 1 + BSP_IO_PORT_10_PIN_2 = 0x0A02, ///< IO port 10 pin 2 + BSP_IO_PORT_10_PIN_3 = 0x0A03, ///< IO port 10 pin 3 + BSP_IO_PORT_10_PIN_4 = 0x0A04, ///< IO port 10 pin 4 + BSP_IO_PORT_10_PIN_5 = 0x0A05, ///< IO port 10 pin 5 + BSP_IO_PORT_10_PIN_6 = 0x0A06, ///< IO port 10 pin 6 + BSP_IO_PORT_10_PIN_7 = 0x0A07, ///< IO port 10 pin 7 + + BSP_IO_PORT_11_PIN_0 = 0x0B00, ///< IO port 11 pin 0 + BSP_IO_PORT_11_PIN_1 = 0x0B01, ///< IO port 11 pin 1 + BSP_IO_PORT_11_PIN_2 = 0x0B02, ///< IO port 11 pin 2 + BSP_IO_PORT_11_PIN_3 = 0x0B03, ///< IO port 11 pin 3 + BSP_IO_PORT_11_PIN_4 = 0x0B04, ///< IO port 11 pin 4 + BSP_IO_PORT_11_PIN_5 = 0x0B05, ///< IO port 11 pin 5 + BSP_IO_PORT_11_PIN_6 = 0x0B06, ///< IO port 11 pin 6 + BSP_IO_PORT_11_PIN_7 = 0x0B07, ///< IO port 11 pin 7 + + BSP_IO_PORT_12_PIN_0 = 0x0C00, ///< IO port 12 pin 0 + BSP_IO_PORT_12_PIN_1 = 0x0C01, ///< IO port 12 pin 1 + BSP_IO_PORT_12_PIN_2 = 0x0C02, ///< IO port 12 pin 2 + BSP_IO_PORT_12_PIN_3 = 0x0C03, ///< IO port 12 pin 3 + BSP_IO_PORT_12_PIN_4 = 0x0C04, ///< IO port 12 pin 4 + BSP_IO_PORT_12_PIN_5 = 0x0C05, ///< IO port 12 pin 5 + BSP_IO_PORT_12_PIN_6 = 0x0C06, ///< IO port 12 pin 6 + BSP_IO_PORT_12_PIN_7 = 0x0C07, ///< IO port 12 pin 7 + + BSP_IO_PORT_13_PIN_0 = 0x0D00, ///< IO port 13 pin 0 + BSP_IO_PORT_13_PIN_1 = 0x0D01, ///< IO port 13 pin 1 + BSP_IO_PORT_13_PIN_2 = 0x0D02, ///< IO port 13 pin 2 + BSP_IO_PORT_13_PIN_3 = 0x0D03, ///< IO port 13 pin 3 + BSP_IO_PORT_13_PIN_4 = 0x0D04, ///< IO port 13 pin 4 + BSP_IO_PORT_13_PIN_5 = 0x0D05, ///< IO port 13 pin 5 + BSP_IO_PORT_13_PIN_6 = 0x0D06, ///< IO port 13 pin 6 + BSP_IO_PORT_13_PIN_7 = 0x0D07, ///< IO port 13 pin 7 + + BSP_IO_PORT_14_PIN_0 = 0x0E00, ///< IO port 14 pin 0 + BSP_IO_PORT_14_PIN_1 = 0x0E01, ///< IO port 14 pin 1 + BSP_IO_PORT_14_PIN_2 = 0x0E02, ///< IO port 14 pin 2 + BSP_IO_PORT_14_PIN_3 = 0x0E03, ///< IO port 14 pin 3 + BSP_IO_PORT_14_PIN_4 = 0x0E04, ///< IO port 14 pin 4 + BSP_IO_PORT_14_PIN_5 = 0x0E05, ///< IO port 14 pin 5 + BSP_IO_PORT_14_PIN_6 = 0x0E06, ///< IO port 14 pin 6 + BSP_IO_PORT_14_PIN_7 = 0x0E07, ///< IO port 14 pin 7 + + BSP_IO_PORT_15_PIN_0 = 0x0F00, ///< IO port 15 pin 0 + BSP_IO_PORT_15_PIN_1 = 0x0F01, ///< IO port 15 pin 1 + BSP_IO_PORT_15_PIN_2 = 0x0F02, ///< IO port 15 pin 2 + BSP_IO_PORT_15_PIN_3 = 0x0F03, ///< IO port 15 pin 3 + BSP_IO_PORT_15_PIN_4 = 0x0F04, ///< IO port 15 pin 4 + BSP_IO_PORT_15_PIN_5 = 0x0F05, ///< IO port 15 pin 5 + BSP_IO_PORT_15_PIN_6 = 0x0F06, ///< IO port 15 pin 6 + BSP_IO_PORT_15_PIN_7 = 0x0F07, ///< IO port 15 pin 7 + + BSP_IO_PORT_16_PIN_0 = 0x1000, ///< IO port 16 pin 0 + BSP_IO_PORT_16_PIN_1 = 0x1001, ///< IO port 16 pin 1 + BSP_IO_PORT_16_PIN_2 = 0x1002, ///< IO port 16 pin 2 + BSP_IO_PORT_16_PIN_3 = 0x1003, ///< IO port 16 pin 3 + BSP_IO_PORT_16_PIN_4 = 0x1004, ///< IO port 16 pin 4 + BSP_IO_PORT_16_PIN_5 = 0x1005, ///< IO port 16 pin 5 + BSP_IO_PORT_16_PIN_6 = 0x1006, ///< IO port 16 pin 6 + BSP_IO_PORT_16_PIN_7 = 0x1007, ///< IO port 16 pin 7 + + BSP_IO_PORT_17_PIN_0 = 0x1100, ///< IO port 17 pin 0 + BSP_IO_PORT_17_PIN_1 = 0x1101, ///< IO port 17 pin 1 + BSP_IO_PORT_17_PIN_2 = 0x1102, ///< IO port 17 pin 2 + BSP_IO_PORT_17_PIN_3 = 0x1103, ///< IO port 17 pin 3 + BSP_IO_PORT_17_PIN_4 = 0x1104, ///< IO port 17 pin 4 + BSP_IO_PORT_17_PIN_5 = 0x1105, ///< IO port 17 pin 5 + BSP_IO_PORT_17_PIN_6 = 0x1106, ///< IO port 17 pin 6 + BSP_IO_PORT_17_PIN_7 = 0x1107, ///< IO port 17 pin 7 + + BSP_IO_PORT_18_PIN_0 = 0x1200, ///< IO port 18 pin 0 + BSP_IO_PORT_18_PIN_1 = 0x1201, ///< IO port 18 pin 1 + BSP_IO_PORT_18_PIN_2 = 0x1202, ///< IO port 18 pin 2 + BSP_IO_PORT_18_PIN_3 = 0x1203, ///< IO port 18 pin 3 + BSP_IO_PORT_18_PIN_4 = 0x1204, ///< IO port 18 pin 4 + BSP_IO_PORT_18_PIN_5 = 0x1205, ///< IO port 18 pin 5 + BSP_IO_PORT_18_PIN_6 = 0x1206, ///< IO port 18 pin 6 + BSP_IO_PORT_18_PIN_7 = 0x1207, ///< IO port 18 pin 7 + + BSP_IO_PORT_19_PIN_0 = 0x1300, ///< IO port 19 pin 0 + BSP_IO_PORT_19_PIN_1 = 0x1301, ///< IO port 19 pin 1 + BSP_IO_PORT_19_PIN_2 = 0x1302, ///< IO port 19 pin 2 + BSP_IO_PORT_19_PIN_3 = 0x1303, ///< IO port 19 pin 3 + BSP_IO_PORT_19_PIN_4 = 0x1304, ///< IO port 19 pin 4 + BSP_IO_PORT_19_PIN_5 = 0x1305, ///< IO port 19 pin 5 + BSP_IO_PORT_19_PIN_6 = 0x1306, ///< IO port 19 pin 6 + BSP_IO_PORT_19_PIN_7 = 0x1307, ///< IO port 19 pin 7 + + BSP_IO_PORT_20_PIN_0 = 0x1400, ///< IO port 20 pin 0 + BSP_IO_PORT_20_PIN_1 = 0x1401, ///< IO port 20 pin 1 + BSP_IO_PORT_20_PIN_2 = 0x1402, ///< IO port 20 pin 2 + BSP_IO_PORT_20_PIN_3 = 0x1403, ///< IO port 20 pin 3 + BSP_IO_PORT_20_PIN_4 = 0x1404, ///< IO port 20 pin 4 + BSP_IO_PORT_20_PIN_5 = 0x1405, ///< IO port 20 pin 5 + BSP_IO_PORT_20_PIN_6 = 0x1406, ///< IO port 20 pin 6 + BSP_IO_PORT_20_PIN_7 = 0x1407, ///< IO port 20 pin 7 + + BSP_IO_PORT_21_PIN_0 = 0x1500, ///< IO port 21 pin 0 + BSP_IO_PORT_21_PIN_1 = 0x1501, ///< IO port 21 pin 1 + BSP_IO_PORT_21_PIN_2 = 0x1502, ///< IO port 21 pin 2 + BSP_IO_PORT_21_PIN_3 = 0x1503, ///< IO port 21 pin 3 + BSP_IO_PORT_21_PIN_4 = 0x1504, ///< IO port 21 pin 4 + BSP_IO_PORT_21_PIN_5 = 0x1505, ///< IO port 21 pin 5 + BSP_IO_PORT_21_PIN_6 = 0x1506, ///< IO port 21 pin 6 + BSP_IO_PORT_21_PIN_7 = 0x1507, ///< IO port 21 pin 7 + + BSP_IO_PORT_22_PIN_0 = 0x1600, ///< IO port 22 pin 0 + BSP_IO_PORT_22_PIN_1 = 0x1601, ///< IO port 22 pin 1 + BSP_IO_PORT_22_PIN_2 = 0x1602, ///< IO port 22 pin 2 + BSP_IO_PORT_22_PIN_3 = 0x1603, ///< IO port 22 pin 3 + BSP_IO_PORT_22_PIN_4 = 0x1604, ///< IO port 22 pin 4 + BSP_IO_PORT_22_PIN_5 = 0x1605, ///< IO port 22 pin 5 + BSP_IO_PORT_22_PIN_6 = 0x1606, ///< IO port 22 pin 6 + BSP_IO_PORT_22_PIN_7 = 0x1607, ///< IO port 22 pin 7 + + BSP_IO_PORT_23_PIN_0 = 0x1700, ///< IO port 23 pin 0 + BSP_IO_PORT_23_PIN_1 = 0x1701, ///< IO port 23 pin 1 + BSP_IO_PORT_23_PIN_2 = 0x1702, ///< IO port 23 pin 2 + BSP_IO_PORT_23_PIN_3 = 0x1703, ///< IO port 23 pin 3 + BSP_IO_PORT_23_PIN_4 = 0x1704, ///< IO port 23 pin 4 + BSP_IO_PORT_23_PIN_5 = 0x1705, ///< IO port 23 pin 5 + BSP_IO_PORT_23_PIN_6 = 0x1706, ///< IO port 23 pin 6 + BSP_IO_PORT_23_PIN_7 = 0x1707, ///< IO port 23 pin 7 + + BSP_IO_PORT_24_PIN_0 = 0x1800, ///< IO port 24 pin 0 + BSP_IO_PORT_24_PIN_1 = 0x1801, ///< IO port 24 pin 1 + BSP_IO_PORT_24_PIN_2 = 0x1802, ///< IO port 24 pin 2 + BSP_IO_PORT_24_PIN_3 = 0x1803, ///< IO port 24 pin 3 + BSP_IO_PORT_24_PIN_4 = 0x1804, ///< IO port 24 pin 4 + BSP_IO_PORT_24_PIN_5 = 0x1805, ///< IO port 24 pin 5 + BSP_IO_PORT_24_PIN_6 = 0x1806, ///< IO port 24 pin 6 + BSP_IO_PORT_24_PIN_7 = 0x1807, ///< IO port 24 pin 7 +} bsp_io_port_pin_t; + +/** Offset for pin safety region access */ +typedef enum e_bsp_io_region +{ + BSP_IO_REGION_NOT_SAFE = 0, ///< Non safety region + BSP_IO_REGION_SAFE = BSP_IO_REGION_ADDRESS_DIFF, ///< Safety region +} bsp_io_region_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern volatile uint32_t g_protect_port_counter; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Set the output level of the pin in the specified region. + * + * @param[in] region The target IO region + * @param[in] pin The pin + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinSet (bsp_io_region_t region, bsp_io_port_pin_t pin) +{ + /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on + * the right side. */ + ((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[pin >> + BSP_IO_PRV_PORT_OFFSET] |= + (uint8_t) (1UL << (pin & BSP_IO_PRV_8BIT_MASK)); +} + +/*******************************************************************************************************************//** + * Clear the output level of the pin in the specified region. + * + * @param[in] region The target IO region + * @param[in] pin The pin + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinClear (bsp_io_region_t region, bsp_io_port_pin_t pin) +{ + /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on + * the right side. */ + ((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[pin >> BSP_IO_PRV_PORT_OFFSET] &= + (uint8_t) (~(1UL << (pin & BSP_IO_PRV_8BIT_MASK))); +} + +/*******************************************************************************************************************//** + * Toggle the output level of the pin in the specified region. + * + * @param[in] region The target IO region + * @param[in] pin The pin + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinToggle (bsp_io_region_t region, bsp_io_port_pin_t pin) +{ + /* Casting to a uint8_t type is valid because only the lower 8 bits of pin(uint16_t) are extracted by masking on + * the right side. */ + ((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[pin >> + BSP_IO_PRV_PORT_OFFSET] ^= + (uint8_t) (1UL << (pin & BSP_IO_PRV_8BIT_MASK)); +} + +/*******************************************************************************************************************//** + * Read the input level of the pin in the specified region. + * + * @param[in] region The target IO region + * @param[in] pin The pin + * + * @retval Current input level + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_FastPinRead (bsp_io_region_t region, bsp_io_port_pin_t pin) +{ + return (uint32_t) ((((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->PIN[pin >> BSP_IO_PRV_PORT_OFFSET]) >> + (pin & BSP_IO_PRV_8BIT_MASK)) & 0x00000001UL; +} + +/*******************************************************************************************************************//** + * Set the output value of the port in the specified region. All pins in the port must be set to the same IO region to + * use this function. + * + * @param[in] region The target IO region + * @param[in] port The port + * @param[in] set_value The setting value + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PortWrite (bsp_io_region_t region, bsp_io_port_t port, uint8_t set_value) +{ + ((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->P[port >> BSP_IO_PRV_PORT_OFFSET] = set_value; +} + +/*******************************************************************************************************************//** + * Read the input value of the port in the specified region. All pins in the port must be set to the same IO region to + * use this function. + * + * @param[in] region The target IO region + * @param[in] port The port + * + * @retval Current input value + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_PortRead (bsp_io_region_t region, bsp_io_port_t port) +{ + return (uint32_t) (((R_PORT_COMMON_Type *) (R_PORT_NSR_BASE + region))->PIN[port >> BSP_IO_PRV_PORT_OFFSET]); +} + +/*******************************************************************************************************************//** + * Enable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur + * via multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessEnable (void) +{ +#if BSP_CFG_PORT_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** If this is first entry then allow writing of PFS. */ + if (0 == g_protect_port_counter) + { + /** Disable protection using PRCR register. */ + + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO); + R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) | BSP_IO_REG_PROTECT_GPIO); + } + + /** Increment the protect counter */ + g_protect_port_counter++; + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/*******************************************************************************************************************//** + * Disable access to the PFS registers. Uses a reference counter to protect against interrupts that could occur via + * multiple threads or an ISR re-entering this code. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_PinAccessDisable (void) +{ +#if BSP_CFG_PORT_PROTECT + + /** Get the current state of interrupts */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /** Is it safe to disable PFS register? */ + if (0 != g_protect_port_counter) + { + /* Decrement the protect counter */ + g_protect_port_counter--; + } + + /** Is it safe to disable writing of PFS? */ + if (0 == g_protect_port_counter) + { + /** Enable protection using PRCR register. */ + + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_IO_PRV_PRCR_KEY) & (uint16_t) (~BSP_IO_REG_PROTECT_GPIO)); + R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_IO_PRV_PRCR_KEY) & (uint16_t) (~BSP_IO_REG_PROTECT_GPIO)); + } + + /** Restore the interrupt state */ + FSP_CRITICAL_SECTION_EXIT; +#endif +} + +/*******************************************************************************************************************//** + * Read IO region of the pin. + * + * @param[in] pin The pin + * + * @retval BSP_IO_REGION_SAFE IO region of the pin is safety + * @retval BSP_IO_REGION_NOT_SAFE IO region of the pin is non-safety + * + * This function can be given as an argument to pin/port access functions described below. When used in a function + * starting with R_BSP_Port, any one pin in the port should be given as an argument to this function. + * R_BSP_PinSet(), R_BSP_PinClear(), R_BSP_PinToggle(), R_BSP_FastPinRead(), R_BSP_PortWrite(), R_BSP_PortRead() + * + * @note This function can be used to get the region of a specified pin, but the overhead should be considered if this + * function is executed each time the pin is accessed. When accessing the same pin repeatedly, it is recommended + * that the value obtained by this function be held in a variable beforehand, and the value of the variable be + * used as the region argument of the pin access function. + **********************************************************************************************************************/ +__STATIC_INLINE bsp_io_region_t R_BSP_IoRegionGet (bsp_io_port_pin_t pin) +{ + /* Casting to a uint32_t type is valid because the range of values represented by uint32_t is not over in the + * calculation process of the right-hand side. */ + uint32_t aselp = + ((uint32_t) ((R_PTADR->RSELP[pin >> BSP_IO_PRV_PORT_OFFSET]) >> (pin & BSP_IO_PRV_8BIT_MASK)) & 0x00000001UL); + + if (0U == aselp) + { + return BSP_IO_REGION_SAFE; + } + else + { + return BSP_IO_REGION_NOT_SAFE; + } +} + +/** @} (end addtogroup BSP_IO) */ + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_irq.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_irq.c new file mode 100644 index 00000000000..3fe92cc3e2d --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_irq.c @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initialize interrupt controller. + * + * @retval None + **********************************************************************************************************************/ +void bsp_irq_cfg (void) +{ + bsp_irq_core_cfg(); +} diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_irq.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_irq.h new file mode 100644 index 00000000000..f8fa8e2d021 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_irq.h @@ -0,0 +1,236 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_IRQ_H +#define BSP_IRQ_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(BSP_CFG_CORE_CR52) + #include "cr/bsp_irq_core.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Sets the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @param[in] p_context ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void R_FSP_IsrContextSet (IRQn_Type const irq, void * p_context) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + r_fsp_irq_context_set(irq, p_context); +} + +/*******************************************************************************************************************//** + * Clear the GIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqClearPending (IRQn_Type irq) +{ + r_bsp_irq_clear_pending(irq); +} + +/*******************************************************************************************************************//** + * Get the GIC pending interrupt. + * + * @param[in] irq Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @return Value indicating the status of the level interrupt. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_IrqPendingGet (IRQn_Type irq) +{ + return r_bsp_irq_pending_get(irq); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ number to configure. + * @param[in] priority GIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + r_bsp_irq_cfg(irq, priority); + + /* Store the context. The context is recovered in the ISR. */ + R_FSP_IsrContextSet(irq, p_context); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the GIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the + * Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnableNoClear (IRQn_Type const irq) +{ + r_bsp_irq_enable_no_clear(irq); +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the GIC (With clearing the pending bit). + * + * @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the + * Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqEnable (IRQn_Type const irq) +{ + /* Clear pending interrupts in the GIC. */ + R_BSP_IrqClearPending(irq); + + /* Enable the interrupt in the GIC. */ + R_BSP_IrqEnableNoClear(irq); +} + +/*******************************************************************************************************************//** + * Disables interrupts in the GIC. + * + * @param[in] irq The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqDisable (IRQn_Type const irq) +{ + r_bsp_irq_disable(irq); +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context, clears pending interrupts, then enables the interrupt. + * + * @param[in] irq Interrupt number. + * @param[in] priority GIC priority of the interrupt + * @param[in] p_context The interrupt context is a pointer to data required in the ISR. + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void * p_context) +{ + R_BSP_IrqCfg(irq, priority, p_context); + R_BSP_IrqEnable(irq); +} + +/*******************************************************************************************************************//** + * @brief Finds the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @return ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void * R_FSP_IsrContextGet (IRQn_Type const irq) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + return gp_renesas_isr_context[irq + BSP_VECTOR_NUM_OFFSET]; +} + +/*******************************************************************************************************************//** + * Sets the interrupt detect type. + * + * @param[in] irq The IRQ number to configure. + * @param[in] detect_type GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd). + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqDetectTypeSet (IRQn_Type const irq, uint32_t detect_type) +{ + r_bsp_irq_detect_type_set(irq, detect_type); +} + +/*******************************************************************************************************************//** + * Sets the interrupt Group. + * + * @param[in] irq The IRQ number to configure. + * @param[in] interrupt_group GIC interrupt group number ( 0 : FIQ, 1 : IRQ ). + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqGroupSet (IRQn_Type const irq, uint32_t interrupt_group) +{ + r_bsp_irq_group_set(irq, interrupt_group); +} + +/*******************************************************************************************************************//** + * Sets the interrupt mask level. + * + * @param[in] mask_level The interrupt mask level + **********************************************************************************************************************/ +__STATIC_INLINE void R_BSP_IrqMaskLevelSet (uint32_t mask_level) +{ + FSP_CRITICAL_SECTION_SET_STATE(mask_level << BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT); +} + +/*******************************************************************************************************************//** + * Gets the interrupt mask level. + * + * @return Value indicating the interrupt mask level. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t R_BSP_IrqMaskLevelGet (void) +{ + return (uint32_t) ((FSP_CRITICAL_SECTION_GET_CURRENT_STATE() >> BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT) & + 0x0000001FUL); +} + +/** @} (end addtogroup BSP_MCU) */ + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_cfg(void); // Used internally by BSP + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h new file mode 100644 index 00000000000..12eab87147f --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_mcu_api.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_MCU_API_H +#define BSP_MCU_API_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_bsp_event_info +{ + IRQn_Type irq; + elc_event_t event; +} bsp_event_info_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void R_BSP_RegisterProtectEnable(bsp_reg_protect_t regs_to_protect); +void R_BSP_RegisterProtectDisable(bsp_reg_protect_t regs_to_unprotect); +void R_BSP_SoftwareDelay(uint32_t delay, bsp_delay_units_t units); +void R_BSP_SystemReset(void); +void R_BSP_CPUReset(bsp_reset_t cpu); +void R_BSP_CPUResetRelease(bsp_reset_t cpu); +void R_BSP_ModuleResetEnable(bsp_module_reset_t module_to_enable); +void R_BSP_ModuleResetDisable(bsp_module_reset_t module_to_disable); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h new file mode 100644 index 00000000000..fa92dd9cdb6 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -0,0 +1,228 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_MODULE_H +#define BSP_MODULE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Cancels the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_START(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) &= ~BSP_MSTP_BIT_ ## ip(channel); \ + BSP_MSTP_REG_ ## ip(channel); \ + BSP_MSTP_DMY_ ## ip(channel); \ + BSP_MSTP_DMY_ ## ip(channel); \ + BSP_MSTP_DMY_ ## ip(channel); \ + BSP_MSTP_DMY_ ## ip(channel); \ + BSP_MSTP_DMY_ ## ip(channel); \ + FSP_CRITICAL_SECTION_EXIT;} + +/*******************************************************************************************************************//** + * Enables the module stop state. + * + * @param ip fsp_ip_t enum value for the module to be stopped + * @param channel The channel. Use channel 0 for modules without channels. + **********************************************************************************************************************/ +#define R_BSP_MODULE_STOP(ip, channel) {FSP_CRITICAL_SECTION_DEFINE; \ + FSP_CRITICAL_SECTION_ENTER; \ + BSP_MSTP_REG_ ## ip(channel) |= BSP_MSTP_BIT_ ## ip(channel); \ + BSP_MSTP_REG_ ## ip(channel); \ + FSP_CRITICAL_SECTION_EXIT;} + +/** @} (end addtogroup BSP_MCU) */ + +#define BSP_MSTP_REG_FSP_IP_BSC(channel) R_SYSC_NS->MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_BSC(channel) (1U); +#define BSP_MSTP_DMY_FSP_IP_BSC(channel) R_BSC->SDCR; + +#define BSP_MSTP_REG_FSP_IP_XSPI(channel) R_SYSC_NS->MSTPCRA +#define BSP_MSTP_BIT_FSP_IP_XSPI(channel) (1U << (4U + channel)); +#define BSP_MSTP_DMY_FSP_IP_XSPI(channel) (0 >= channel) ? R_XSPI0->WRAPCFG : R_XSPI1->WRAPCFG + +#define BSP_MSTP_REG_FSP_IP_SCI(channel) *((4U >= channel) ? &R_SYSC_NS->MSTPCRA : &R_SYSC_S->MSTPCRG) +#define BSP_MSTP_BIT_FSP_IP_SCI(channel) ((4U >= channel) ? (1U << (8U + channel)) : (1U)); +#define BSP_MSTP_DMY_FSP_IP_SCI(channel) (0 >= channel) ? R_SCI0->RDR : ((1 >= channel) ? R_SCI1->RDR : \ + ((2 >= \ + channel) ? R_SCI2->RDR : ((3 >= \ + channel) \ + ? R_SCI3 \ + ->RDR : \ + ((4 \ + >= \ + channel) \ + ? R_SCI4 \ + ->RDR : \ + R_SCI5-> \ + RDR)))) + +#define BSP_MSTP_REG_FSP_IP_IIC(channel) *((1U >= channel) ? &R_SYSC_NS->MSTPCRB : &R_SYSC_S->MSTPCRG) +#define BSP_MSTP_BIT_FSP_IP_IIC(channel) ((1U >= channel) ? (1U << (0U + channel)) : (1U << (1U))); +#define BSP_MSTP_DMY_FSP_IP_IIC(channel) (0 >= channel) ? R_IIC0->ICCR1 : ((1 >= channel) ? R_IIC1->ICCR1 \ + : R_IIC2->ICCR1) + +#define BSP_MSTP_REG_FSP_IP_SPI(channel) *((2U >= channel) ? &R_SYSC_NS->MSTPCRB : &R_SYSC_S->MSTPCRG) +#define BSP_MSTP_BIT_FSP_IP_SPI(channel) ((2U >= channel) ? (1U << (4U + channel)) : (1U << (2U))); +#define BSP_MSTP_DMY_FSP_IP_SPI(channel) (0 >= channel) ? R_SPI0->SPCKD : ((1 >= channel) ? R_SPI1->SPCKD : \ + ((2 >= \ + channel) ? R_SPI2->SPCKD : R_SPI3 \ + ->SPCKD)) + +#define BSP_MSTP_REG_FSP_IP_MTU3(channel) R_SYSC_NS->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_MTU3(channel) (1U); +#define BSP_MSTP_DMY_FSP_IP_MTU3(channel) R_MTU0->TCR; + +#define BSP_MSTP_REG_FSP_IP_GPT(channel) *((13U >= channel) ? &R_SYSC_NS->MSTPCRC : &R_SYSC_S->MSTPCRG) +#define BSP_MSTP_BIT_FSP_IP_GPT(channel) ((6U >= channel) ? (1U << (1U)) : ((13U >= channel) ? \ + (1U << (2U)) : (1U << (3U)))); +#define BSP_MSTP_DMY_FSP_IP_GPT(channel) (6 >= \ + channel) ? R_GPT0->GTSTR : ((13 >= \ + channel) ? R_GPT7->GTSTR : R_GPT14-> \ + GTSTR); +#define BSP_MSTP_REG_FSP_IP_TFU(channel) R_SYSC_NS->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_TFU(channel) (1U << (5U)); +#define BSP_MSTP_DMY_FSP_IP_TFU(channel) R_TFU->TRGSTS; + +#define BSP_MSTP_REG_FSP_IP_ADC12(channel) R_SYSC_NS->MSTPCRC +#define BSP_MSTP_BIT_FSP_IP_ADC12(channel) (1U << (6U + channel)); +#define BSP_MSTP_DMY_FSP_IP_ADC12(channel) (0 >= channel) ? R_ADC120->ADCSR : R_ADC121->ADCSR; + +#define BSP_MSTP_REG_FSP_IP_DSMIF(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_DSMIF(channel) (1U << (0U + channel)); +#define BSP_MSTP_DMY_FSP_IP_DSMIF(channel) (0 >= channel) ? R_DSMIF0->DSSEICR : R_DSMIF1->DSSEICR + +#define BSP_MSTP_REG_FSP_IP_CMT(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_CMT(channel) (1U << (2U + channel)); +#define BSP_MSTP_DMY_FSP_IP_CMT(channel) (0 >= \ + channel) ? R_CMT->UNT[0].CMSTR0 : ((1 >= \ + channel) ? R_CMT->UNT[1].CMSTR0 \ + : R_CMT->UNT[2].CMSTR0) + +#define BSP_MSTP_REG_FSP_IP_CMTW(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_CMTW(channel) (1U << (5U + channel)); +#define BSP_MSTP_DMY_FSP_IP_CMTW(channel) (0 >= channel) ? R_CMTW0->CMWSTR : R_CMTW1->CMWSTR + +#define BSP_MSTP_REG_FSP_IP_TSU(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_TSU(channel) (1U << (7U)); +#define BSP_MSTP_DMY_FSP_IP_TSU(channel) R_TSU->TSUSM; + +#define BSP_MSTP_REG_FSP_IP_DOC(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_DOC(channel) (1U << (8U)); +#define BSP_MSTP_DMY_FSP_IP_DOC(channel) R_DOC->DOCR + +#define BSP_MSTP_REG_FSP_IP_CRC(channel) *((0U == channel) ? &R_SYSC_NS->MSTPCRD : &R_SYSC_S->MSTPCRG) +#define BSP_MSTP_BIT_FSP_IP_CRC(channel) ((0U == channel) ? (1U << (9U)) : (1U << (4U))); +#define BSP_MSTP_DMY_FSP_IP_CRC(channel) (0 >= channel) ? R_CRC0->CRCDIR : R_CRC1->CRCDIR; + +#define BSP_MSTP_REG_FSP_IP_CANFD(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_CANFD(channel) (1U << (10U)); +#define BSP_MSTP_DMY_FSP_IP_CANFD(channel) R_CANFD->CFDGIPV; + +#define BSP_MSTP_REG_FSP_IP_CKIO(channel) R_SYSC_NS->MSTPCRD +#define BSP_MSTP_BIT_FSP_IP_CKIO(channel) (1U << (11U)); +#define BSP_MSTP_DMY_FSP_IP_CKIO(channel) ; + +#define BSP_MSTP_REG_FSP_IP_GMAC(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_GMAC(channel) (1U); +#define BSP_MSTP_DMY_FSP_IP_GMAC(channel) R_GMAC->MAC_Configuration + +#define BSP_MSTP_REG_FSP_IP_ETHSW(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_ETHSW(channel) (1U << (1U)); +#define BSP_MSTP_DMY_FSP_IP_ETHSW(channel) R_ETHSW->REVISION + +#define BSP_MSTP_REG_FSP_IP_ESC(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_ESC(channel) (1U << (2U)); +#define BSP_MSTP_DMY_FSP_IP_ESC(channel) R_ESC->TYPE; + +#define BSP_MSTP_REG_FSP_IP_ETHSS(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_ETHSS(channel) (1U << (3U)); +#define BSP_MSTP_DMY_FSP_IP_ETHSS(channel) R_ETHSS->PRCMD + +#define BSP_MSTP_REG_FSP_IP_ENCIF(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_ENCIF(channel) (1U << (4U)); +#define BSP_MSTP_DMY_FSP_IP_ENCIF(channel) ; + +#define BSP_MSTP_REG_FSP_IP_USBHS(channel) R_SYSC_NS->MSTPCRE +#define BSP_MSTP_BIT_FSP_IP_USBHS(channel) (1U << (8U)); +#define BSP_MSTP_DMY_FSP_IP_USBHS(channel) R_USBHC->HCREVISION; + +#define BSP_MSTP_REG_FSP_IP_TRACECLOCK(channel) R_SYSC_S->MSTPCRF +#define BSP_MSTP_BIT_FSP_IP_TRACECLOCK(channel) (1U << (0U)); +#define BSP_MSTP_DMY_FSP_IP_TRACECLOCK(channel) ; + +#define BSP_MSTP_REG_FSP_IP_RTC(channel) R_SYSC_S->MSTPCRG +#define BSP_MSTP_BIT_FSP_IP_RTC(channel) (1U << (5U)); +#define BSP_MSTP_DMY_FSP_IP_RTC(channel) R_RTC->RTCA0CTL0; + +#define BSP_MSTP_REG_FSP_IP_CLMA(channel) R_SYSC_S->MSTPCRG +#define BSP_MSTP_BIT_FSP_IP_CLMA(channel) ((2U >= channel) ? \ + (1U << (9U + channel)) : (1U << (8U))); +#define BSP_MSTP_DMY_FSP_IP_CLMA(channel) (0 >= \ + channel) ? R_CLMA0->CTL0 : ((1 >= \ + channel) ? R_CLMA1->CTL0 : ((2 >= \ + channel) ? \ + R_CLMA2-> \ + CTL0 : \ + R_CLMA3-> \ + CTL0)); + +#define BSP_MSTP_REG_FSP_IP_SHOSTIF(channel) R_SYSC_S->MSTPCRI +#define BSP_MSTP_BIT_FSP_IP_SHOSTIF(channel) (1U << (1U)); +#define BSP_MSTP_DMY_FSP_IP_SHOSTIF(channel) ; + +#define BSP_MSTP_REG_FSP_IP_PHOSTIF(channel) R_SYSC_S->MSTPCRI +#define BSP_MSTP_BIT_FSP_IP_PHOSTIF(channel) (1U << (0U)); +#define BSP_MSTP_DMY_FSP_IP_PHOSTIF(channel) ; + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c new file mode 100644 index 00000000000..8db202648dc --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.c @@ -0,0 +1,116 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing PRCR register. */ +#define BSP_PRV_PRCR_KEY (0xA500U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/** Used for holding reference counters for protection bits. */ +volatile uint16_t g_protect_counters[] = +{ + 0U, 0U, 0U, 0U +}; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/** Masks for setting or clearing the PRCR register. Use -1 for size because PWPR in MPC is used differently. */ +static const uint16_t g_prcr_masks[] = +{ + 0x0001U, /* PRC0. */ + 0x0002U, /* PRC1. */ + 0x0004U, /* PRC2. */ + 0x0008U, /* PRC3. */ +}; + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Enable register protection. Registers that are protected cannot be written to. Register protection is + * enabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR). + * + * @param[in] regs_to_protect Registers which have write protection enabled. + **********************************************************************************************************************/ +void R_BSP_RegisterProtectEnable (bsp_reg_protect_t regs_to_protect) +{ + /* Is it safe to disable write access? */ + if (0U != g_protect_counters[regs_to_protect]) + { + /* Decrement the protect counter */ + g_protect_counters[regs_to_protect]--; + } + + /* Is it safe to disable write access? */ + if (0U == g_protect_counters[regs_to_protect]) + { + /** Enable protection using PRCR register. */ + + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); + R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_PRV_PRCR_KEY) & (uint16_t) (~g_prcr_masks[regs_to_protect])); + } +} + +/*******************************************************************************************************************//** + * Disable register protection. Registers that are protected cannot be written to. Register protection is + * disabled by using the Protect Register (PRCR) and the MPC's Write-Protect Register (PWPR). + * + * @param[in] regs_to_unprotect Registers which have write protection disabled. + **********************************************************************************************************************/ +void R_BSP_RegisterProtectDisable (bsp_reg_protect_t regs_to_unprotect) +{ + /* If this is first entry then disable protection. */ + if (0U == g_protect_counters[regs_to_unprotect]) + { + /** Disable protection using PRCR register. */ + + /** When writing to the PRCR register the upper 8-bits must be the correct key. Set lower bits to 0 to + * disable writes. */ + R_RWP_NS->PRCRN = ((R_RWP_NS->PRCRN | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); + R_RWP_S->PRCRS = ((R_RWP_S->PRCRS | BSP_PRV_PRCR_KEY) | g_prcr_masks[regs_to_unprotect]); + } + + /** Increment the protect counter */ + g_protect_counters[regs_to_unprotect]++; +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h new file mode 100644 index 00000000000..63917ea4690 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_register_protection.h @@ -0,0 +1,76 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_REGISTER_PROTECTION_H +#define BSP_REGISTER_PROTECTION_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** The different types of registers that can be protected. */ +typedef enum e_bsp_reg_protect +{ + /** Enables writing to the registers related to the clock generation circuit. */ + BSP_REG_PROTECT_CGC = 0, + + /** Enables writing to the registers related to low power consumption and reset. */ + BSP_REG_PROTECT_LPC_RESET, + + /** Enables writing to the registers related to GPIO. */ + BSP_REG_PROTECT_GPIO, + + /** Enables writing to the registers related to Non-Safety reg. */ + BSP_REG_PROTECT_SYSTEM, +} bsp_reg_protect_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_register_protect_open(void); // Used internally by BSP + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_reset.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_reset.c new file mode 100644 index 00000000000..a8b44d2419d --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_reset.c @@ -0,0 +1,139 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_RESET_MRCTL_BIT_SHIFT_MASK (0x0000001FU) +#define BSP_RESET_MRCTL_SELECT_MASK (0x001F0000U) +#define BSP_RESET_MRCTL_REGION_SELECT_MASK (0x00400000U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Occur the system software reset. + **********************************************************************************************************************/ +void R_BSP_SystemReset (void) +{ + /* System software reset. */ + R_SYSC_S->SWRSYS = BSP_PRV_RESET_KEY; +} + +/*******************************************************************************************************************//** + * Occur the CPU software reset. + * + * @param[in] cpu to be reset state. + **********************************************************************************************************************/ +void R_BSP_CPUReset (bsp_reset_t cpu) +{ + /* CPU0 software reset. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET); + R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_KEY; + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET); + __WFI(); + FSP_PARAMETER_NOT_USED(cpu); +} + +/*******************************************************************************************************************//** + * Release the CPU reset state. + * + * @param[in] cpu to be release reset state. + **********************************************************************************************************************/ +void R_BSP_CPUResetRelease (bsp_reset_t cpu) +{ + /* Release CPU0 reset state. */ + R_SYSC_S->SWRCPU0 = BSP_PRV_RESET_RELEASE_KEY; + FSP_PARAMETER_NOT_USED(cpu); +} + +/*******************************************************************************************************************//** + * Enable module reset state. + * + * @param[in] module_to_enable Modules to enable module reset state. + **********************************************************************************************************************/ +void R_BSP_ModuleResetEnable (bsp_module_reset_t module_to_enable) +{ + volatile uint32_t mrctl; + uint32_t * p_reg; + + /** When MRCTLn register exists in the safety region, + * it is necessary to add an offset of safety region. */ + p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA + + (((module_to_enable & BSP_RESET_MRCTL_SELECT_MASK) >> 16U) + + (module_to_enable & BSP_RESET_MRCTL_REGION_SELECT_MASK)); + mrctl = 1U << (module_to_enable & BSP_RESET_MRCTL_BIT_SHIFT_MASK); + + /** Enable module reset state using MRCTLE register. */ + *p_reg |= mrctl; + + /** To ensure processing after module reset. */ + mrctl = *(volatile uint32_t *) (p_reg); +} + +/*******************************************************************************************************************//** + * Disable module reset state. + * + * @param[in] module_to_disable Modules to disable module reset state. + **********************************************************************************************************************/ +void R_BSP_ModuleResetDisable (bsp_module_reset_t module_to_disable) +{ + volatile uint32_t mrctl; + uint32_t * p_reg; + + /** When MRCTLn register exists in the safety region, + * it is necessary to add an offset of safety region. */ + p_reg = (uint32_t *) &R_SYSC_NS->MRCTLA + + (((module_to_disable & BSP_RESET_MRCTL_SELECT_MASK) >> 16U) + + (module_to_disable & BSP_RESET_MRCTL_REGION_SELECT_MASK)); + mrctl = 1U << (module_to_disable & BSP_RESET_MRCTL_BIT_SHIFT_MASK); + + /** Disable module stop state using MRCTLn register. */ + *p_reg &= ~mrctl; + + /** In order to secure processing after release from module reset, + * dummy read the same register at least three times. + * Refer to "Notes on Module Reset Control Register Operation" of the RZ microprocessor manual. */ + mrctl = *(volatile uint32_t *) (p_reg); + mrctl = *(volatile uint32_t *) (p_reg); + mrctl = *(volatile uint32_t *) (p_reg); +} + +/** @} (end addtogroup BSP_MCU) */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_reset.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_reset.h new file mode 100644 index 00000000000..10cd9c44db4 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_reset.h @@ -0,0 +1,150 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_RESET_H +#define BSP_RESET_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Key code for writing reset register. */ +#define BSP_PRV_RESET_KEY (0x4321A501U) +#define BSP_PRV_RESET_RELEASE_KEY (0x00000000U) + +/* MRCTL register selection. Bits 16-20 assign values in order for the module control registers (A=0, E=4). + * Bit 24 indicates whether MRCTLn register is in the safety region. */ +#define BSP_RESET_MRCTLA_SELECT (0x00000000U) +#define BSP_RESET_MRCTLE_SELECT (0x00040000U) +#define BSP_RESET_MRCTLI_SELECT (0x00480000U) + +/* MRCTL register bit number. */ +#define BSP_RESET_MRCTL_BIT0_SHIFT (0x00000000U) +#define BSP_RESET_MRCTL_BIT1_SHIFT (0x00000001U) +#define BSP_RESET_MRCTL_BIT2_SHIFT (0x00000002U) +#define BSP_RESET_MRCTL_BIT3_SHIFT (0x00000003U) +#define BSP_RESET_MRCTL_BIT4_SHIFT (0x00000004U) +#define BSP_RESET_MRCTL_BIT5_SHIFT (0x00000005U) +#define BSP_RESET_MRCTL_BIT6_SHIFT (0x00000006U) +#define BSP_RESET_MRCTL_BIT7_SHIFT (0x00000007U) +#define BSP_RESET_MRCTL_BIT8_SHIFT (0x00000008U) +#define BSP_RESET_MRCTL_BIT9_SHIFT (0x00000009U) +#define BSP_RESET_MRCTL_BIT10_SHIFT (0x0000000AU) +#define BSP_RESET_MRCTL_BIT11_SHIFT (0x0000000BU) +#define BSP_RESET_MRCTL_BIT12_SHIFT (0x0000000CU) +#define BSP_RESET_MRCTL_BIT13_SHIFT (0x0000000DU) +#define BSP_RESET_MRCTL_BIT14_SHIFT (0x0000000EU) +#define BSP_RESET_MRCTL_BIT15_SHIFT (0x0000000FU) +#define BSP_RESET_MRCTL_BIT16_SHIFT (0x00000010U) +#define BSP_RESET_MRCTL_BIT17_SHIFT (0x00000011U) +#define BSP_RESET_MRCTL_BIT18_SHIFT (0x00000012U) +#define BSP_RESET_MRCTL_BIT19_SHIFT (0x00000013U) +#define BSP_RESET_MRCTL_BIT20_SHIFT (0x00000014U) +#define BSP_RESET_MRCTL_BIT21_SHIFT (0x00000015U) +#define BSP_RESET_MRCTL_BIT22_SHIFT (0x00000016U) +#define BSP_RESET_MRCTL_BIT23_SHIFT (0x00000017U) +#define BSP_RESET_MRCTL_BIT24_SHIFT (0x00000018U) +#define BSP_RESET_MRCTL_BIT25_SHIFT (0x00000019U) +#define BSP_RESET_MRCTL_BIT26_SHIFT (0x0000001AU) +#define BSP_RESET_MRCTL_BIT27_SHIFT (0x0000001BU) +#define BSP_RESET_MRCTL_BIT28_SHIFT (0x0000001CU) +#define BSP_RESET_MRCTL_BIT29_SHIFT (0x0000001DU) +#define BSP_RESET_MRCTL_BIT30_SHIFT (0x0000001EU) +#define BSP_RESET_MRCTL_BIT31_SHIFT (0x0000001FU) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/** CPU to be reset target.*/ +typedef enum e_bsp_reset +{ + BSP_RESET_CR52_0 = 0, ///< Software reset for CR52_0 +} bsp_reset_t; + +/** The different types of registers that can control the reset of peripheral modules related to Ethernet. */ +typedef enum e_bsp_module_reset +{ + /** Enables writing to the registers related to xSPI Unit 0 reset control. */ + BSP_MODULE_RESET_XSPI0 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT), + + /** Enables writing to the registers related to xSPI Unit 1 reset control. */ + BSP_MODULE_RESET_XSPI1 = (BSP_RESET_MRCTLA_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT), + + /** Enables writing to the registers related to GMAC (PCLKH clock domain) reset control. */ + BSP_MODULE_RESET_GMAC0_PCLKH = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT), + + /** Enables writing to the registers related to GMAC (PCLKM clock domain) reset control. */ + BSP_MODULE_RESET_GMAC0_PCLKM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT), + + /** Enables writing to the registers related to ETHSW reset control. */ + BSP_MODULE_RESET_ETHSW = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT), + + /** Enables writing to the registers related to ESC (Bus clock domain) reset control. */ + BSP_MODULE_RESET_ESC_BUS = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT), + + /** Enables writing to the registers related to ESC (IP clock domain) reset control. */ + BSP_MODULE_RESET_ESC_IP = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT4_SHIFT), + + /** Enables writing to the registers related to Ethernet subsystem register reset control. */ + BSP_MODULE_RESET_ESC_ETH_SUBSYSTEM = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT5_SHIFT), + + /** Enables writing to the registers related to MII converter reset control. */ + BSP_MODULE_RESET_MII = (BSP_RESET_MRCTLE_SELECT | BSP_RESET_MRCTL_BIT6_SHIFT), + + /** Enables writing to the registers related to PHOSTIF reset control. */ + BSP_MODULE_RESET_PHOSTIF = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT0_SHIFT), + + /** Enables writing to the registers related to SHOSTIF (Master bus clock domain) reset control. */ + BSP_MODULE_RESET_SHOSTIF_MASTER_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT1_SHIFT), + + /** Enables writing to the registers related to SHOSTIF (Slave bus clock domain) reset control. */ + BSP_MODULE_RESET_SHOSTIF_SLAVE_BUS_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT2_SHIFT), + + /** Enables writing to the registers related to SHOSTIF (IP clock domain) reset control. */ + BSP_MODULE_RESET_SHOSTIF_IP_CLOCK = (BSP_RESET_MRCTLI_SELECT | BSP_RESET_MRCTL_BIT3_SHIFT), +} bsp_module_reset_t; + +/** @} (end addtogroup BSP_MCU) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c new file mode 100644 index 00000000000..35759244d0e --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_sbrk.c @@ -0,0 +1,108 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#include +#include +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ +caddr_t _sbrk(int incr); + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * FSP implementation of the standard library _sbrk() function. + * @param[in] inc The number of bytes being asked for by malloc(). + * + * @note This function overrides the _sbrk version that exists in the newlib library that is linked with. + * That version improperly relies on the SP as part of it's allocation strategy. This is bad in general and + * worse in an RTOS environment. This version insures that we allocate the byte pool requested by malloc() + * only from our allocated HEAP area. Also note that newlib is pre-built and forces the pagesize used by + * malloc() to be 4096. That requires that we have a HEAP of at least 4096 if we are to support malloc(). + * @retval Address of allocated area if successful, -1 otherwise. + **********************************************************************************************************************/ +caddr_t _sbrk (int incr) +{ + extern char _Heap_Begin __asm("__HeapBase"); ///< Defined by the linker. + + extern char _Heap_Limit __asm("__HeapLimit"); ///< Defined by the linker. + + uint32_t bytes = (uint32_t) incr; + static char * current_heap_end = 0; + char * current_block_address; + + if (current_heap_end == 0) + { + current_heap_end = &_Heap_Begin; + } + + current_block_address = current_heap_end; + + /* The returned address must be aligned to a word boundary to prevent hard faults on cores that do not support + * unaligned access. We assume the heap starts on a word boundary and make sure all allocations are a multiple + * of 4. */ + bytes = (bytes + 3U) & (~3U); + if (current_heap_end + bytes > &_Heap_Limit) + { + /** Heap has overflowed */ + errno = ENOMEM; + + return (caddr_t) -1; + } + + current_heap_end += bytes; + + return (caddr_t) current_block_address; +} + +#endif + +/******************************************************************************************************************//** + * @} (end addtogroup BSP_MCU) + *********************************************************************************************************************/ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_tfu.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_tfu.h new file mode 100644 index 00000000000..42304d7d02f --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/bsp_tfu.h @@ -0,0 +1,228 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef RENESAS_TFU +#define RENESAS_TFU + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* Mathematical Functions includes. */ +#ifdef __cplusplus + #include +#else + #include +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define R_TFU_HYPOT_SCALING_FACTOR 0.607252935F + +#ifdef __GNUC__ /* and (arm)clang */ + #if (__STDC_VERSION__ < 199901L) && defined(__STRICT_ANSI__) && !defined(__cplusplus) + +/* No form of inline is available, it happens only when -std=c89, gnu89 and + * above are OK */ + #warning \ + "-std=c89 doesn't support type checking on TFU. Please use -std=gnu89 or higher for example -std=c99" + #else + #ifdef __GNUC_GNU_INLINE__ + +/* gnu89 semantics of inline and extern inline are essentially the exact + * opposite of those in C99 */ + #define BSP_TFU_INLINE extern inline __attribute__((always_inline)) + #else /* __GNUC_STDC_INLINE__ */ + #define BSP_TFU_INLINE static inline __attribute__((always_inline)) + #endif + #endif +#elif __ICCARM__ + #define BSP_TFU_INLINE +#else + #error "Compiler not supported!" +#endif + +#if BSP_CFG_USE_TFU_MATHLIB + #define sinf(x) __sinf(x) + #define cosf(x) __cosf(x) + #define atan2f(y, x) __atan2f(y, x) + #define hypotf(x, y) __hypotf(x, y) + #define atan2hypotf(y, x, a, h) __atan2hypotf(y, x, a, h) + #define sincosf(a, s, c) __sincosf(a, s, c) +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Calculates sine of the given angle. + * @param[in] angle The value of an angle in radian. + * + * @retval Sine value of an angle. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __sinf (float angle) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read sin from R_TFU->SCDT1 */ + return R_TFU->SCDT1; +} + +/*******************************************************************************************************************//** + * Calculates cosine of the given angle. + * @param[in] angle The value of an angle in radian. + * + * @retval Cosine value of an angle. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __cosf (float angle) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read cos from R_TFU->SCDT1 */ + return R_TFU->SCDT0; +} + +/*******************************************************************************************************************//** + * Calculates sine and cosine of the given angle. + * @param[in] angle The value of an angle in radian. + * @param[out] sin Sine value of an angle. + * @param[out] cos Cosine value of an angle. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE void __sincosf (float angle, float * sin, float * cos) +{ + /* Set the angle to R_TFU->SCDT1 */ + R_TFU->SCDT1 = angle; + + /* Read sin from R_TFU->SCDT1 */ + *sin = R_TFU->SCDT1; + + /* Read sin from R_TFU->SCDT1 */ + *cos = R_TFU->SCDT0; +} + +/*******************************************************************************************************************//** + * Calculates the arc tangent based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-Axis cordinate value. + * @param[in] x_cord X-Axis cordinate value. + * + * @retval Arc tangent for given values. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __atan2f (float y_cord, float x_cord) +{ + /* Set X-cordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-cordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read arctan(y/x) from R_TFU->ATDT1 */ + return R_TFU->ATDT1; +} + +/*******************************************************************************************************************//** + * Calculates the hypotenuse based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-cordinate value. + * @param[in] x_cord X-cordinate value. + * + * @retval Hypotenuse for given values. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE float __hypotf (float x_cord, float y_cord) +{ + /* Set X-coordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-coordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ + return R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; +} + +/*******************************************************************************************************************//** + * Calculates the arc tangent and hypotenuse based on given X-cordinate and Y-cordinate values. + * @param[in] y_cord Y-cordinate value. + * @param[in] x_cord X-cordinate value. + * @param[out] atan2 Arc tangent for given values. + * @param[out] hypot Hypotenuse for given values. + **********************************************************************************************************************/ +#if __ICCARM__ + #pragma inline = forced +#endif +BSP_TFU_INLINE void __atan2hypotf (float y_cord, float x_cord, float * atan2, float * hypot) +{ + /* Set X-coordinate to R_TFU->ATDT0 */ + R_TFU->ATDT0 = x_cord; + + /* set Y-coordinate to R_TFU->ATDT1 */ + R_TFU->ATDT1 = y_cord; + + /* Read arctan(y/x) from R_TFU->ATDT1 */ + *atan2 = R_TFU->ATDT1; + + /* Read sqrt (x_cord2 + y_cord2) from R_TFU->ATDT0 */ + *hypot = R_TFU->ATDT0 * R_TFU_HYPOT_SCALING_FACTOR; +} + +/** @} (end addtogroup BSP_MCU) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif /* RENESAS_TFU */ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c new file mode 100644 index 00000000000..f85e3dbdae9 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.c @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Powers on and off the L3 cache way. + **********************************************************************************************************************/ +void r_bsp_cache_l3_power_ctrl (void) +{ + /* Does nothing because CR52 does not have the CLUSTERPWRCTLR register. */ +} diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h new file mode 100644 index 00000000000..a0ca23c5e6b --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_cache_core.h @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_CACHE_CORE_H +#define BSP_CACHE_CORE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +void r_bsp_cache_l3_power_ctrl(void); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c new file mode 100644 index 00000000000..9eea2c8a1da --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.c @@ -0,0 +1,63 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This assembly language routine takes roughly 4 cycles per loop. 2 additional cycles + * occur when the loop exits. The 'naked' attribute indicates that the specified function does not need + * prologue/epilogue sequences generated by the compiler. + * @param[in] loop_cnt The number of loops to iterate. + **********************************************************************************************************************/ +BSP_ATTRIBUTE_STACKLESS void r_bsp_software_delay_loop (__attribute__((unused)) uint32_t loop_cnt) +{ + __asm volatile ("sw_delay_loop: \n" + +#if defined(__ICCARM__) || defined(__ARMCC_VERSION) + " subs r0, #1 \n" ///< 1 cycle +#elif defined(__GNUC__) + " sub r0, r0, #1 \n" ///< 1 cycle +#endif + + " cmp r0, #0 \n" ///< 1 cycle + + " bne sw_delay_loop \n" ///< 2 cycles + + " bx lr \n"); ///< 2 cycles +} diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h new file mode 100644 index 00000000000..1e31cd2b4e1 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_delay_core.h @@ -0,0 +1,63 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_DELAY_CORE_H +#define BSP_DELAY_CORE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* The number of cycles required per software delay loop. */ +#ifndef BSP_DELAY_LOOP_CYCLES + #define BSP_DELAY_LOOP_CYCLES (4) +#endif + +/* Calculates the number of delay loops to pass to r_bsp_software_delay_loop to achieve at least the requested cycle + * count delay. This is 1 loop longer than optimal if cycles is a multiple of BSP_DELAY_LOOP_CYCLES, but it ensures + * the requested number of loops is at least 1 since r_bsp_software_delay_loop cannot be called with a loop count + * of 0. */ +#define BSP_DELAY_LOOPS_CALCULATE(cycles) (((cycles) / BSP_DELAY_LOOP_CYCLES) + 1U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +BSP_ATTRIBUTE_STACKLESS void r_bsp_software_delay_loop(uint32_t loop_cnt); + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c new file mode 100644 index 00000000000..d31ab2fb5b1 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.c @@ -0,0 +1,146 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/** ELC event definitions. */ + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_IRQ_UINT32_MAX (0xFFFFFFFFU) + +#define BSP_PRV_CLEAR_REG_MAX (13U) +#define BSP_PRV_ALL_BIT_CLEAR (0xFFFFFFFFU) + +#define BSP_PRV_ID_MASK (0x000003FFU) +#define BSP_PRV_INTERRUPTABLE_NUM (32U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ +#if VECTOR_DATA_IRQ_COUNT > 0 +extern fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES]; +#endif +extern fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES]; + +extern const uint32_t BSP_GICD_ICFGR_INIT[BSP_NON_SELECTABLE_ICFGR_MAX]; + +/* This table is used to store the context in the ISR. */ +void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES]; + +/* GIC current interrupt ID and variable. */ +IRQn_Type g_current_interrupt_num[BSP_PRV_INTERRUPTABLE_NUM]; +uint8_t g_current_interrupt_pointer = 0; + +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_WEAK_REFERENCE = +{ + (bsp_interrupt_event_t) 0 +}; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Using the vector table information section that has been built by the linker and placed into ROM in the + * .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts + * in the NVIC. + * + **********************************************************************************************************************/ +void bsp_irq_core_cfg (void) +{ + uint32_t gicd_reg_num; + GICD_Type * GICD; + GICR_CONTROL_TARGET_Type * GICR_TARGET0_IFREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_IFREG = BSP_PRV_GICR_TARGET0_IFREG_ADDRESS; + + /* Enable Group1 interrupts from the GIC Distributor to the GIC CPU interface. */ + GICD->GICD_CTLR |= 0x00000002UL; + + /* Release Processor Sleep state of the target. */ + GICR_TARGET0_IFREG->GICR_WAKER = 0x00000000UL; + + /* Initialize GICD_ICFGR register for the edge-triggered interrupt. */ + for (gicd_reg_num = 0; gicd_reg_num < BSP_NON_SELECTABLE_ICFGR_MAX; gicd_reg_num++) + { + GICD->GICD_ICFGR[gicd_reg_num] = BSP_GICD_ICFGR_INIT[gicd_reg_num]; + } + + /* Clear the Pending and Active bit for the all interrupts. */ + for (gicd_reg_num = 0; gicd_reg_num < BSP_PRV_CLEAR_REG_MAX; gicd_reg_num++) + { + GICD->GICD_ICPENDR[gicd_reg_num] = BSP_PRV_ALL_BIT_CLEAR; + GICD->GICD_ICACTIVER[gicd_reg_num] = BSP_PRV_ALL_BIT_CLEAR; + } + + __asm volatile ("cpsie i \n" /* Enable IRQ Interrupts */ + "cpsie f \n" /* Enable FIQ Interrupts */ + "cpsie a \n" /* Enable SError Interrupts */ + "isb"); /* Ensuring Context-changing */ +} + +/*******************************************************************************************************************//** + * This function is called first when an interrupt is generated and branches to each interrupt isr function. + * + * @param[in] id GIC INTID used to identify the interrupt. + **********************************************************************************************************************/ +void bsp_common_interrupt_handler (uint32_t id) +{ + uint16_t gic_intid; + IRQn_Type irq; + + /* Get interrupt ID (GIC INTID). */ + gic_intid = (uint16_t) (id & BSP_PRV_ID_MASK); + + irq = (IRQn_Type) (gic_intid - BSP_CORTEX_VECTOR_TABLE_ENTRIES); + + /* Remain the interrupt number */ + g_current_interrupt_num[g_current_interrupt_pointer++] = irq; + __asm volatile ("dmb"); + + BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE + +#if VECTOR_DATA_IRQ_COUNT > 0 + if (BSP_CORTEX_VECTOR_TABLE_ENTRIES <= gic_intid) + { + /* Branch to an interrupt handler. */ + g_vector_table[irq](); + } + else +#endif + { + /* Branch to an interrupt handler. */ + g_sgi_ppi_vector_table[gic_intid](); + } + + g_current_interrupt_pointer--; + + BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE +} diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h new file mode 100644 index 00000000000..60588e23256 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/all/cr/bsp_irq_core.h @@ -0,0 +1,347 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_IRQ_CORE_H +#define BSP_IRQ_CORE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_ICU_VECTOR_MAX_ENTRIES (BSP_VECTOR_TABLE_MAX_ENTRIES) + +#define BSP_PRV_GICD_ADDRESS (GICD0) +#define BSP_PRV_GICR_TARGET0_INTREG_ADDRESS (GICR0_TARGET0_INTREG) +#define BSP_PRV_GICR_TARGET0_IFREG_ADDRESS (GICR0_TARGET0_IFREG) + +#define BSP_EVENT_SGI_PPI_ARRAY_NUM (2U) +#define BSP_NON_SELECTABLE_ICFGR_MAX (BSP_VECTOR_TABLE_MAX_ENTRIES / BSP_INTERRUPT_TYPE_OFFSET) + +#define BSP_PRV_IRQ_CONFIG_MASK (0x000000FFU) +#define BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK (1UL << 1UL) + +#define BSP_PRV_GIC_REG_STRIDE04 (4U) +#define BSP_PRV_GIC_REG_STRIDE16 (16U) +#define BSP_PRV_GIC_REG_STRIDE32 (32U) + +#define BSP_PRV_GIC_REG_BITS1 (1U) +#define BSP_PRV_GIC_REG_BITS2 (2U) +#define BSP_PRV_GIC_REG_BITS8 (8U) + +#define BSP_PRV_GIC_REG_MASK_1BIT (1U) + +#define BSP_PRV_GIC_LOWEST_PPI_INTERRUPT_NUM (-17) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ +extern void * gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES]; + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Inline Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @brief Sets the ISR context associated with the requested IRQ. + * + * @param[in] irq IRQ number (parameter checking must ensure the IRQ number is valid before calling this + * function. + * @param[in] p_context ISR context for IRQ. + **********************************************************************************************************************/ +__STATIC_INLINE void r_fsp_irq_context_set (IRQn_Type const irq, void * p_context) +{ + /* This provides access to the ISR context array defined in bsp_irq.c. This is an inline function instead of + * being part of bsp_irq.c for performance considerations because it is used in interrupt service routines. */ + gp_renesas_isr_context[irq + BSP_VECTOR_NUM_OFFSET] = p_context; +} + +/*******************************************************************************************************************//** + * Clear the GIC pending interrupt. + * + * @param[in] irq Interrupt for which to clear the Pending bit. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_clear_pending (IRQn_Type irq) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + GICD->GICD_ICPENDR[_irq / BSP_PRV_GIC_REG_STRIDE32] = + (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + GICR_TARGET0_INTREG->GICR_ICPENDR0 = (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); + } +} + +/*******************************************************************************************************************//** + * Get the GIC pending interrupt. + * + * @param[in] irq Interrupt that gets a pending bit.. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + * + * @return Value indicating the status of the level interrupt. + **********************************************************************************************************************/ +__STATIC_INLINE uint32_t r_bsp_irq_pending_get (IRQn_Type irq) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + uint32_t value = 0; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + uint32_t shift = (_irq % BSP_PRV_GIC_REG_STRIDE32); + value = (GICD->GICD_ISPENDR[_irq / BSP_PRV_GIC_REG_STRIDE32] >> shift) & (uint32_t) (BSP_PRV_GIC_REG_MASK_1BIT); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + uint32_t shift = _irq; + value = (GICR_TARGET0_INTREG->GICR_ISPENDR0 >> shift) & (uint32_t) (BSP_PRV_GIC_REG_MASK_1BIT); + } + + return value; +} + +/*******************************************************************************************************************//** + * Sets the interrupt priority and context. + * + * @param[in] irq The IRQ number to configure. + * @param[in] priority GIC priority of the interrupt + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_cfg (IRQn_Type const irq, uint32_t priority) +{ +#if (52U == __CORTEX_R) + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + + /* Set the interrupt group to 1 (IRQ) */ + GICD->GICD_IGROUPR[_irq / BSP_PRV_GIC_REG_STRIDE32] |= + (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); + + /* Set the interrupt priority */ + GICD->GICD_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] &= + (uint32_t) (~(BSP_PRV_IRQ_CONFIG_MASK << (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04)))); + GICD->GICD_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] |= + (priority << + (BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT + (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04)))); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + + /* Set the interrupt group to 1 (IRQ) */ + GICR_TARGET0_INTREG->GICR_IGROUPR0 |= (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); + + /* Set the interrupt priority */ + GICR_TARGET0_INTREG->GICR_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] &= + (uint32_t) (~(BSP_PRV_IRQ_CONFIG_MASK << (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04)))); + GICR_TARGET0_INTREG->GICR_IPRIORITYR[_irq / BSP_PRV_GIC_REG_STRIDE04] |= + (priority << + (BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT + (BSP_PRV_GIC_REG_BITS8 * (_irq % BSP_PRV_GIC_REG_STRIDE04)))); + } +#endif +} + +/*******************************************************************************************************************//** + * Enable the IRQ in the GIC (Without clearing the pending bit). + * + * @param[in] irq The IRQ number to enable. Note that the enums listed for IRQn_Type are only those for the + * Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_enable_no_clear (IRQn_Type const irq) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + GICD->GICD_ISENABLER[_irq / BSP_PRV_GIC_REG_STRIDE32] |= + (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + GICR_TARGET0_INTREG->GICR_ISENABLER0 |= (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); + } +} + +/*******************************************************************************************************************//** + * Disables interrupts in the GIC. + * + * @param[in] irq The IRQ number to disable in the GIC. Note that the enums listed for IRQn_Type are + * only those for the Cortex Processor Exceptions Numbers. + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_disable (IRQn_Type const irq) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + GICD->GICD_ICENABLER[_irq / BSP_PRV_GIC_REG_STRIDE32] = + (uint32_t) (BSP_PRV_GIC_REG_BITS1 << (_irq % BSP_PRV_GIC_REG_STRIDE32)); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + GICR_TARGET0_INTREG->GICR_ICENABLER0 = (uint32_t) (BSP_PRV_GIC_REG_BITS1 << _irq); + } + + __DSB(); + __ISB(); +} + +/*******************************************************************************************************************//** + * Sets the interrupt detect type. + * + * @param[in] irq The IRQ number to configure. + * @param[in] detect_type GIC detect type of the interrupt (0 : active-HIGH level, 1 : rising edge-triggerd). + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_detect_type_set (IRQn_Type const irq, uint32_t detect_type) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + if (0 != detect_type) + { + GICD->GICD_ICFGR[_irq / BSP_PRV_GIC_REG_STRIDE16] |= + (uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK << + (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16))); + } + else + { + GICD->GICD_ICFGR[_irq / BSP_PRV_GIC_REG_STRIDE16] &= + ~((uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK << + (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16)))); + } + } + else if (irq >= BSP_PRV_GIC_LOWEST_PPI_INTERRUPT_NUM) + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + if (0 != detect_type) + { + GICR_TARGET0_INTREG->GICR_ICFGR1 |= + (uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK << + (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16))); + } + else + { + GICR_TARGET0_INTREG->GICR_ICFGR1 &= + ~((uint32_t) (BSP_PRV_GICD_ICFGR_INT_CONFIG_MASK << + (BSP_PRV_GIC_REG_BITS2 * (_irq % BSP_PRV_GIC_REG_STRIDE16)))); + } + } + else + { + /* The register that sets the SGI interrupt type (GICR_ICFGR0) is read-only, so do not set it. */ + } +} + +/*******************************************************************************************************************//** + * Sets the interrupt Group. + * + * @param[in] irq The IRQ number to configure. + * @param[in] interrupt_group GIC interrupt group number ( 0 : FIQ, 1 : IRQ ). + **********************************************************************************************************************/ +__STATIC_INLINE void r_bsp_irq_group_set (IRQn_Type const irq, uint32_t interrupt_group) +{ + GICD_Type * GICD; + GICR_SGI_PPI_Type * GICR_TARGET0_INTREG; + + GICD = BSP_PRV_GICD_ADDRESS; + GICR_TARGET0_INTREG = BSP_PRV_GICR_TARGET0_INTREG_ADDRESS; + + if (irq >= 0) + { + uint32_t _irq = (uint32_t) irq; + GICD->GICD_IGROUPR[_irq / BSP_PRV_GIC_REG_STRIDE32] |= (interrupt_group << (_irq % BSP_PRV_GIC_REG_STRIDE32)); + } + else + { + uint32_t _irq = (uint32_t) (irq + BSP_VECTOR_NUM_OFFSET); + GICR_TARGET0_INTREG->GICR_IGROUPR0 |= interrupt_group << _irq; + } +} + +/*******************************************************************************************************************//** + * @internal + * @addtogroup BSP_MCU_PRV Internal BSP Documentation + * @ingroup RENESAS_INTERNAL + * @{ + **********************************************************************************************************************/ + +/* Public functions defined in bsp.h */ +void bsp_irq_core_cfg(void); // Used internally by BSP +void bsp_common_interrupt_handler(uint32_t id); + +/** @} (end addtogroup BSP_MCU_PRV) */ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h new file mode 100644 index 00000000000..8362b2fb7cc --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_elc.h @@ -0,0 +1,523 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_ELC_H +#define BSP_ELC_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RZN2L + * @{ + **********************************************************************************************************************/ + +/** Sources of event signals to be linked to other peripherals or the CPU + * @note This list may change based on based on the device. + * */ +typedef enum e_elc_event_rzn2l +{ + ELC_EVENT_INTCPU0 = (0), // Software interrupt 0 + ELC_EVENT_INTCPU1 = (1), // Software interrupt 1 + ELC_EVENT_INTCPU2 = (2), // Software interrupt 2 + ELC_EVENT_INTCPU3 = (3), // Software interrupt 3 + ELC_EVENT_INTCPU4 = (4), // Software interrupt 4 + ELC_EVENT_INTCPU5 = (5), // Software interrupt 5 + ELC_EVENT_IRQ0 = (6), // External pin interrupt 0 + ELC_EVENT_IRQ1 = (7), // External pin interrupt 1 + ELC_EVENT_IRQ2 = (8), // External pin interrupt 2 + ELC_EVENT_IRQ3 = (9), // External pin interrupt 3 + ELC_EVENT_IRQ4 = (10), // External pin interrupt 4 + ELC_EVENT_IRQ5 = (11), // External pin interrupt 5 + ELC_EVENT_IRQ6 = (12), // External pin interrupt 6 + ELC_EVENT_IRQ7 = (13), // External pin interrupt 7 + ELC_EVENT_IRQ8 = (14), // External pin interrupt 8 + ELC_EVENT_IRQ9 = (15), // External pin interrupt 9 + ELC_EVENT_IRQ10 = (16), // External pin interrupt 10 + ELC_EVENT_IRQ11 = (17), // External pin interrupt 11 + ELC_EVENT_IRQ12 = (18), // External pin interrupt 12 + ELC_EVENT_IRQ13 = (19), // External pin interrupt 13 + ELC_EVENT_BSC_CMI = (20), // Refresh compare match interrupt + ELC_EVENT_DMAC0_INT0 = (21), // DMAC0 transfer completion 0 + ELC_EVENT_DMAC0_INT1 = (22), // DMAC0 transfer completion 1 + ELC_EVENT_DMAC0_INT2 = (23), // DMAC0 transfer completion 2 + ELC_EVENT_DMAC0_INT3 = (24), // DMAC0 transfer completion 3 + ELC_EVENT_DMAC0_INT4 = (25), // DMAC0 transfer completion 4 + ELC_EVENT_DMAC0_INT5 = (26), // DMAC0 transfer completion 5 + ELC_EVENT_DMAC0_INT6 = (27), // DMAC0 transfer completion 6 + ELC_EVENT_DMAC0_INT7 = (28), // DMAC0 transfer completion 7 + ELC_EVENT_DMAC1_INT0 = (37), // DMAC1 transfer completion 0 + ELC_EVENT_DMAC1_INT1 = (38), // DMAC1 transfer completion 1 + ELC_EVENT_DMAC1_INT2 = (39), // DMAC1 transfer completion 2 + ELC_EVENT_DMAC1_INT3 = (40), // DMAC1 transfer completion 3 + ELC_EVENT_DMAC1_INT4 = (41), // DMAC1 transfer completion 4 + ELC_EVENT_DMAC1_INT5 = (42), // DMAC1 transfer completion 5 + ELC_EVENT_DMAC1_INT6 = (43), // DMAC1 transfer completion 6 + ELC_EVENT_DMAC1_INT7 = (44), // DMAC1 transfer completion 7 + ELC_EVENT_CMT0_CMI = (53), // CMT0 Compare match + ELC_EVENT_CMT1_CMI = (54), // CMT1 Compare match + ELC_EVENT_CMT2_CMI = (55), // CMT2 Compare match + ELC_EVENT_CMT3_CMI = (56), // CMT3 Compare match + ELC_EVENT_CMT4_CMI = (57), // CMT4 Compare match + ELC_EVENT_CMT5_CMI = (58), // CMT5 Compare match + ELC_EVENT_CMTW0_CMWI = (59), // CMTW0 Compare match + ELC_EVENT_CMTW0_IC0I = (60), // CMTW0 Input capture of register 0 + ELC_EVENT_CMTW0_IC1I = (61), // CMTW0 Input capture of register 1 + ELC_EVENT_CMTW0_OC0I = (62), // CMTW0 Output compare of register 0 + ELC_EVENT_CMTW0_OC1I = (63), // CMTW0 Output compare of register 1 + ELC_EVENT_CMTW1_CMWI = (64), // CMTW1 Compare match + ELC_EVENT_CMTW1_IC0I = (65), // CMTW1 Input capture of register 0 + ELC_EVENT_CMTW1_IC1I = (66), // CMTW1 Input capture of register 1 + ELC_EVENT_CMTW1_OC0I = (67), // CMTW1 Output compare of register 0 + ELC_EVENT_CMTW1_OC1I = (68), // CMTW1 Output compare of register 1 + ELC_EVENT_TGIA0 = (69), // MTU0.TGRA input capture/compare match + ELC_EVENT_TGIB0 = (70), // MTU0.TGRB input capture/compare match + ELC_EVENT_TGIC0 = (71), // MTU0.TGRC input capture/compare match + ELC_EVENT_TGID0 = (72), // MTU0.TGRD input capture/compare match + ELC_EVENT_TCIV0 = (73), // MTU0.TCNT overflow + ELC_EVENT_TGIE0 = (74), // MTU0.TGRE compare match + ELC_EVENT_TGIF0 = (75), // MTU0.TGRF compare match + ELC_EVENT_TGIA1 = (76), // MTU1.TGRA input capture/compare match + ELC_EVENT_TGIB1 = (77), // MTU1.TGRB input capture/compare match + ELC_EVENT_TCIV1 = (78), // MTU1.TCNT overflow + ELC_EVENT_TCIU1 = (79), // MTU1.TCNT underflow + ELC_EVENT_TGIA2 = (80), // MTU2.TGRA input capture/compare match + ELC_EVENT_TGIB2 = (81), // MTU2.TGRB input capture/compare match + ELC_EVENT_TCIV2 = (82), // MTU2.TCNT overflow + ELC_EVENT_TCIU2 = (83), // MTU2.TCNT underflow + ELC_EVENT_TGIA3 = (84), // MTU3.TGRA input capture/compare match + ELC_EVENT_TGIB3 = (85), // MTU3.TGRB input capture/compare match + ELC_EVENT_TGIC3 = (86), // MTU3.TGRC input capture/compare match + ELC_EVENT_TGID3 = (87), // MTU3.TGRD input capture/compare match + ELC_EVENT_TCIV3 = (88), // MTU3.TCNT overflow + ELC_EVENT_TGIA4 = (89), // MTU4.TGRA input capture/compare match + ELC_EVENT_TGIB4 = (90), // MTU4.TGRB input capture/compare match + ELC_EVENT_TGIC4 = (91), // MTU4.TGRC input capture/compare match + ELC_EVENT_TGID4 = (92), // MTU4.TGRD input capture/compare match + ELC_EVENT_TCIV4 = (93), // MTU4.TCNT overflow/underflow + ELC_EVENT_TGIU5 = (94), // MTU5.TGRU input capture/compare match + ELC_EVENT_TGIV5 = (95), // MTU5.TGRV input capture/compare match + ELC_EVENT_TGIW5 = (96), // MTU5.TGRW input capture/compare match + ELC_EVENT_TGIA6 = (97), // MTU6.TGRA input capture/compare match + ELC_EVENT_TGIB6 = (98), // MTU6.TGRB input capture/compare match + ELC_EVENT_TGIC6 = (99), // MTU6.TGRC input capture/compare match + ELC_EVENT_TGID6 = (100), // MTU6.TGRD input capture/compare match + ELC_EVENT_TCIV6 = (101), // MTU6.TCNT overflow + ELC_EVENT_TGIA7 = (102), // MTU7.TGRA input capture/compare match + ELC_EVENT_TGIB7 = (103), // MTU7.TGRB input capture/compare match + ELC_EVENT_TGIC7 = (104), // MTU7.TGRC input capture/compare match + ELC_EVENT_TGID7 = (105), // MTU7.TGRD input capture/compare match + ELC_EVENT_TCIV7 = (106), // MTU7.TCNT overflow/underflow + ELC_EVENT_TGIA8 = (107), // MTU8.TGRA input capture/compare match + ELC_EVENT_TGIB8 = (108), // MTU8.TGRB input capture/compare match + ELC_EVENT_TGIC8 = (109), // MTU8.TGRC input capture/compare match + ELC_EVENT_TGID8 = (110), // MTU8.TGRD input capture/compare match + ELC_EVENT_TCIV8 = (111), // MTU8.TCNT overflow + ELC_EVENT_OEI1 = (112), // Output enable interrupt 1 + ELC_EVENT_OEI2 = (113), // Output enable interrupt 2 + ELC_EVENT_OEI3 = (114), // Output enable interrupt 3 + ELC_EVENT_OEI4 = (115), // Output enable interrupt 4 + ELC_EVENT_GPT0_CCMPA = (116), // GPT0 GTCCRA input capture/compare match + ELC_EVENT_GPT0_CCMPB = (117), // GPT0 GTCCRB input capture/compare match + ELC_EVENT_GPT0_CMPC = (118), // GPT0 GTCCRC compare match + ELC_EVENT_GPT0_CMPD = (119), // GPT0 GTCCRD compare match + ELC_EVENT_GPT0_CMPE = (120), // GPT0 GTCCRE compare match + ELC_EVENT_GPT0_CMPF = (121), // GPT0 GTCCRF compare match + ELC_EVENT_GPT0_OVF = (122), // GPT0 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT0_UDF = (123), // GPT0 GTCNT underflow + ELC_EVENT_GPT0_DTE = (124), // GPT0 Dead time error + ELC_EVENT_GPT1_CCMPA = (125), // GPT1 GTCCRA input capture/compare match + ELC_EVENT_GPT1_CCMPB = (126), // GPT1 GTCCRB input capture/compare match + ELC_EVENT_GPT1_CMPC = (127), // GPT1 GTCCRC compare match + ELC_EVENT_GPT1_CMPD = (128), // GPT1 GTCCRD compare match + ELC_EVENT_GPT1_CMPE = (129), // GPT1 GTCCRE compare match + ELC_EVENT_GPT1_CMPF = (130), // GPT1 GTCCRF compare match + ELC_EVENT_GPT1_OVF = (131), // GPT1 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT1_UDF = (132), // GPT1 GTCNT underflow + ELC_EVENT_GPT1_DTE = (133), // GPT1 Dead time error + ELC_EVENT_GPT2_CCMPA = (134), // GPT2 GTCCRA input capture/compare match + ELC_EVENT_GPT2_CCMPB = (135), // GPT2 GTCCRB input capture/compare match + ELC_EVENT_GPT2_CMPC = (136), // GPT2 GTCCRC compare match + ELC_EVENT_GPT2_CMPD = (137), // GPT2 GTCCRD compare match + ELC_EVENT_GPT2_CMPE = (138), // GPT2 GTCCRE compare match + ELC_EVENT_GPT2_CMPF = (139), // GPT2 GTCCRF compare match + ELC_EVENT_GPT2_OVF = (140), // GPT2 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT2_UDF = (141), // GPT2 GTCNT underflow + ELC_EVENT_GPT2_DTE = (142), // GPT2 Dead time error + ELC_EVENT_GPT3_CCMPA = (143), // GPT3 GTCCRA input capture/compare match + ELC_EVENT_GPT3_CCMPB = (144), // GPT3 GTCCRB input capture/compare match + ELC_EVENT_GPT3_CMPC = (145), // GPT3 GTCCRC compare match + ELC_EVENT_GPT3_CMPD = (146), // GPT3 GTCCRD compare match + ELC_EVENT_GPT3_CMPE = (147), // GPT3 GTCCRE compare match + ELC_EVENT_GPT3_CMPF = (148), // GPT3 GTCCRF compare match + ELC_EVENT_GPT3_OVF = (149), // GPT3 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT3_UDF = (150), // GPT3 GTCNT underflow + ELC_EVENT_GPT3_DTE = (151), // GPT3 Dead time error + ELC_EVENT_GPT4_CCMPA = (152), // GPT4 GTCCRA input capture/compare match + ELC_EVENT_GPT4_CCMPB = (153), // GPT4 GTCCRB input capture/compare match + ELC_EVENT_GPT4_CMPC = (154), // GPT4 GTCCRC compare match + ELC_EVENT_GPT4_CMPD = (155), // GPT4 GTCCRD compare match + ELC_EVENT_GPT4_CMPE = (156), // GPT4 GTCCRE compare match + ELC_EVENT_GPT4_CMPF = (157), // GPT4 GTCCRF compare match + ELC_EVENT_GPT4_OVF = (158), // GPT4 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT4_UDF = (159), // GPT4 GTCNT underflow + ELC_EVENT_GPT4_DTE = (160), // GPT4 Dead time error + ELC_EVENT_GPT5_CCMPA = (161), // GPT5 GTCCRA input capture/compare match + ELC_EVENT_GPT5_CCMPB = (162), // GPT5 GTCCRB input capture/compare match + ELC_EVENT_GPT5_CMPC = (163), // GPT5 GTCCRC compare match + ELC_EVENT_GPT5_CMPD = (164), // GPT5 GTCCRD compare match + ELC_EVENT_GPT5_CMPE = (165), // GPT5 GTCCRE compare match + ELC_EVENT_GPT5_CMPF = (166), // GPT5 GTCCRF compare match + ELC_EVENT_GPT5_OVF = (167), // GPT5 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT5_UDF = (168), // GPT5 GTCNT underflow + ELC_EVENT_GPT5_DTE = (169), // GPT5 Dead time error + ELC_EVENT_GPT6_CCMPA = (170), // GPT6 GTCCRA input capture/compare match + ELC_EVENT_GPT6_CCMPB = (171), // GPT6 GTCCRB input capture/compare match + ELC_EVENT_GPT6_CMPC = (172), // GPT6 GTCCRC compare match + ELC_EVENT_GPT6_CMPD = (173), // GPT6 GTCCRD compare match + ELC_EVENT_GPT6_CMPE = (174), // GPT6 GTCCRE compare match + ELC_EVENT_GPT6_CMPF = (175), // GPT6 GTCCRF compare match + ELC_EVENT_GPT6_OVF = (176), // GPT6 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT6_UDF = (177), // GPT6 GTCNT underflow + ELC_EVENT_GPT6_DTE = (178), // GPT6 Dead time error + ELC_EVENT_GPT7_CCMPA = (179), // GPT7 GTCCRA input capture/compare match + ELC_EVENT_GPT7_CCMPB = (180), // GPT7 GTCCRB input capture/compare match + ELC_EVENT_GPT7_CMPC = (181), // GPT7 GTCCRC compare match + ELC_EVENT_GPT7_CMPD = (182), // GPT7 GTCCRD compare match + ELC_EVENT_GPT7_CMPE = (183), // GPT7 GTCCRE compare match + ELC_EVENT_GPT7_CMPF = (184), // GPT7 GTCCRF compare match + ELC_EVENT_GPT7_OVF = (185), // GPT7 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT7_UDF = (186), // GPT7 GTCNT underflow + ELC_EVENT_GPT7_DTE = (187), // GPT7 Dead time error + ELC_EVENT_GPT8_CCMPA = (188), // GPT8 GTCCRA input capture/compare match + ELC_EVENT_GPT8_CCMPB = (189), // GPT8 GTCCRB input capture/compare match + ELC_EVENT_GPT8_CMPC = (190), // GPT8 GTCCRC compare match + ELC_EVENT_GPT8_CMPD = (191), // GPT8 GTCCRD compare match + ELC_EVENT_GPT8_CMPE = (192), // GPT8 GTCCRE compare match + ELC_EVENT_GPT8_CMPF = (193), // GPT8 GTCCRF compare match + ELC_EVENT_GPT8_OVF = (194), // GPT8 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT8_UDF = (195), // GPT8 GTCNT underflow + ELC_EVENT_GPT8_DTE = (196), // GPT8 Dead time error + ELC_EVENT_GPT9_CCMPA = (197), // GPT9 GTCCRA input capture/compare match + ELC_EVENT_GPT9_CCMPB = (198), // GPT9 GTCCRB input capture/compare match + ELC_EVENT_GPT9_CMPC = (199), // GPT9 GTCCRC compare match + ELC_EVENT_GPT9_CMPD = (200), // GPT9 GTCCRD compare match + ELC_EVENT_GPT9_CMPE = (201), // GPT9 GTCCRE compare match + ELC_EVENT_GPT9_CMPF = (202), // GPT9 GTCCRF compare match + ELC_EVENT_GPT9_OVF = (203), // GPT9 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT9_UDF = (204), // GPT9 GTCNT underflow + ELC_EVENT_GPT9_DTE = (205), // GPT9 Dead time error + ELC_EVENT_GPT10_CCMPA = (206), // GPT10 GTCCRA input capture/compare match + ELC_EVENT_GPT10_CCMPB = (207), // GPT10 GTCCRB input capture/compare match + ELC_EVENT_GPT10_CMPC = (208), // GPT10 GTCCRC compare match + ELC_EVENT_GPT10_CMPD = (209), // GPT10 GTCCRD compare match + ELC_EVENT_GPT10_CMPE = (210), // GPT10 GTCCRE compare match + ELC_EVENT_GPT10_CMPF = (211), // GPT10 GTCCRF compare match + ELC_EVENT_GPT10_OVF = (212), // GPT10 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT10_UDF = (213), // GPT10 GTCNT underflow + ELC_EVENT_GPT10_DTE = (214), // GPT10 Dead time error + ELC_EVENT_GPT11_CCMPA = (215), // GPT11 GTCCRA input capture/compare match + ELC_EVENT_GPT11_CCMPB = (216), // GPT11 GTCCRB input capture/compare match + ELC_EVENT_GPT11_CMPC = (217), // GPT11 GTCCRC compare match + ELC_EVENT_GPT11_CMPD = (218), // GPT11 GTCCRD compare match + ELC_EVENT_GPT11_CMPE = (219), // GPT11 GTCCRE compare match + ELC_EVENT_GPT11_CMPF = (220), // GPT11 GTCCRF compare match + ELC_EVENT_GPT11_OVF = (221), // GPT11 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT11_UDF = (222), // GPT11 GTCNT underflow + ELC_EVENT_GPT11_DTE = (223), // GPT11 Dead time error + ELC_EVENT_GPT12_CCMPA = (224), // GPT12 GTCCRA input capture/compare match + ELC_EVENT_GPT12_CCMPB = (225), // GPT12 GTCCRB input capture/compare match + ELC_EVENT_GPT12_CMPC = (226), // GPT12 GTCCRC compare match + ELC_EVENT_GPT12_CMPD = (227), // GPT12 GTCCRD compare match + ELC_EVENT_GPT12_CMPE = (228), // GPT12 GTCCRE compare match + ELC_EVENT_GPT12_CMPF = (229), // GPT12 GTCCRF compare match + ELC_EVENT_GPT12_OVF = (230), // GPT12 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT12_UDF = (231), // GPT12 GTCNT underflow + ELC_EVENT_GPT12_DTE = (232), // GPT12 Dead time error + ELC_EVENT_GPT13_CCMPA = (233), // GPT13 GTCCRA input capture/compare match + ELC_EVENT_GPT13_CCMPB = (234), // GPT13 GTCCRB input capture/compare match + ELC_EVENT_GPT13_CMPC = (235), // GPT13 GTCCRC compare match + ELC_EVENT_GPT13_CMPD = (236), // GPT13 GTCCRD compare match + ELC_EVENT_GPT13_CMPE = (237), // GPT13 GTCCRE compare match + ELC_EVENT_GPT13_CMPF = (238), // GPT13 GTCCRF compare match + ELC_EVENT_GPT13_OVF = (239), // GPT13 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT13_UDF = (240), // GPT13 GTCNT underflow + ELC_EVENT_GPT13_DTE = (241), // GPT13 Dead time error + ELC_EVENT_POEG0_GROUP0 = (242), // POEG group A interrupt for channels in LLPP + ELC_EVENT_POEG0_GROUP1 = (243), // POEG group B interrupt for channels in LLPP + ELC_EVENT_POEG0_GROUP2 = (244), // POEG group C interrupt for channels in LLPP + ELC_EVENT_POEG0_GROUP3 = (245), // POEG group D interrupt for channels in LLPP + ELC_EVENT_POEG1_GROUP0 = (246), // POEG group A interrupt for channels in NONSAFETY + ELC_EVENT_POEG1_GROUP1 = (247), // POEG group B interrupt for channels in NONSAFETY + ELC_EVENT_POEG1_GROUP2 = (248), // POEG group C interrupt for channels in NONSAFETY + ELC_EVENT_POEG1_GROUP3 = (249), // POEG group D interrupt for channels in NONSAFETY + ELC_EVENT_GMAC_LPI = (250), // GMAC1 energy efficient + ELC_EVENT_GMAC_PMT = (251), // GMAC1 power management + ELC_EVENT_GMAC_SBD = (252), // GMAC1 general interrupt + ELC_EVENT_ETHSW_INTR = (253), // Ethernet Switch interrupt + ELC_EVENT_ETHSW_DLR = (254), // Ethernet Switch DLR interrupt + ELC_EVENT_ETHSW_PRP = (255), // Ethernet Switch PRP interrupt + ELC_EVENT_ETHSW_IHUB = (256), // Ethernet Switch Integrated Hub interrupt + ELC_EVENT_ETHSW_PTRN0 = (257), // Ethernet Switch RX Pattern Matcher interrupt 0 + ELC_EVENT_ETHSW_PTRN1 = (258), // Ethernet Switch RX Pattern Matcher interrupt 1 + ELC_EVENT_ETHSW_PTRN2 = (259), // Ethernet Switch RX Pattern Matcher interrupt 2 + ELC_EVENT_ETHSW_PTRN3 = (260), // Ethernet Switch RX Pattern Matcher interrupt 3 + ELC_EVENT_ETHSW_PTRN4 = (261), // Ethernet Switch RX Pattern Matcher interrupt 4 + ELC_EVENT_ETHSW_PTRN5 = (262), // Ethernet Switch RX Pattern Matcher interrupt 5 + ELC_EVENT_ETHSW_PTRN6 = (263), // Ethernet Switch RX Pattern Matcher interrupt 6 + ELC_EVENT_ETHSW_PTRN7 = (264), // Ethernet Switch RX Pattern Matcher interrupt 7 + ELC_EVENT_ETHSW_PTRN8 = (265), // Ethernet Switch RX Pattern Matcher interrupt 8 + ELC_EVENT_ETHSW_PTRN9 = (266), // Ethernet Switch RX Pattern Matcher interrupt 9 + ELC_EVENT_ETHSW_PTRN10 = (267), // Ethernet Switch RX Pattern Matcher interrupt 10 + ELC_EVENT_ETHSW_PTRN11 = (268), // Ethernet Switch RX Pattern Matcher interrupt 11 + ELC_EVENT_ETHSW_PTPOUT0 = (269), // Ethernet switch timer pulse output 0 + ELC_EVENT_ETHSW_PTPOUT1 = (270), // Ethernet switch timer pulse output 1 + ELC_EVENT_ETHSW_PTPOUT2 = (271), // Ethernet switch timer pulse output 2 + ELC_EVENT_ETHSW_PTPOUT3 = (272), // Ethernet switch timer pulse output 3 + ELC_EVENT_ETHSW_TDMAOUT0 = (273), // Ethernet Switch TDMA timer output 0 + ELC_EVENT_ETHSW_TDMAOUT1 = (274), // Ethernet Switch TDMA timer output 1 + ELC_EVENT_ETHSW_TDMAOUT2 = (275), // Ethernet Switch TDMA timer output 2 + ELC_EVENT_ETHSW_TDMAOUT3 = (276), // Ethernet Switch TDMA timer output 3 + ELC_EVENT_ESC_SYNC0 = (277), // EtherCAT Sync0 interrupt + ELC_EVENT_ESC_SYNC1 = (278), // EtherCAT Sync1 interrupt + ELC_EVENT_ESC_CAT = (279), // EtherCAT interrupt + ELC_EVENT_ESC_SOF = (280), // EtherCAT SOF interrupt + ELC_EVENT_ESC_EOF = (281), // EtherCAT EOF interrupt + ELC_EVENT_ESC_WDT = (282), // EtherCAT WDT interrupt + ELC_EVENT_ESC_RST = (283), // EtherCAT RESET interrupt + ELC_EVENT_USB_HI = (284), // USB (Host) interrupt + ELC_EVENT_USB_FI = (285), // USB (Function) interrupt + ELC_EVENT_USB_FDMA0 = (286), // USB (Function) DMA 0 transmit completion + ELC_EVENT_USB_FDMA1 = (287), // USB (Function) DMA 1 transmit completion + ELC_EVENT_SCI0_ERI = (288), // SCI0 Receive error + ELC_EVENT_SCI0_RXI = (289), // SCI0 Receive data full + ELC_EVENT_SCI0_TXI = (290), // SCI0 Transmit data empty + ELC_EVENT_SCI0_TEI = (291), // SCI0 Transmit end + ELC_EVENT_SCI1_ERI = (292), // SCI1 Receive error + ELC_EVENT_SCI1_RXI = (293), // SCI1 Receive data full + ELC_EVENT_SCI1_TXI = (294), // SCI1 Transmit data empty + ELC_EVENT_SCI1_TEI = (295), // SCI1 Transmit end + ELC_EVENT_SCI2_ERI = (296), // SCI2 Receive error + ELC_EVENT_SCI2_RXI = (297), // SCI2 Receive data full + ELC_EVENT_SCI2_TXI = (298), // SCI2 Transmit data empty + ELC_EVENT_SCI2_TEI = (299), // SCI2 Transmit end + ELC_EVENT_SCI3_ERI = (300), // SCI3 Receive error + ELC_EVENT_SCI3_RXI = (301), // SCI3 Receive data full + ELC_EVENT_SCI3_TXI = (302), // SCI3 Transmit data empty + ELC_EVENT_SCI3_TEI = (303), // SCI3 Transmit end + ELC_EVENT_SCI4_ERI = (304), // SCI4 Receive error + ELC_EVENT_SCI4_RXI = (305), // SCI4 Receive data full + ELC_EVENT_SCI4_TXI = (306), // SCI4 Transmit data empty + ELC_EVENT_SCI4_TEI = (307), // SCI4 Transmit end + ELC_EVENT_IIC0_EEI = (308), // IIC0 Transfer error or event generation + ELC_EVENT_IIC0_RXI = (309), // IIC0 Receive data full + ELC_EVENT_IIC0_TXI = (310), // IIC0 Transmit data empty + ELC_EVENT_IIC0_TEI = (311), // IIC0 Transmit end + ELC_EVENT_IIC1_EEI = (312), // IIC1 Transfer error or event generation + ELC_EVENT_IIC1_RXI = (313), // IIC1 Receive data full + ELC_EVENT_IIC1_TXI = (314), // IIC1 Transmit data empty + ELC_EVENT_IIC1_TEI = (315), // IIC1 Transmit end + ELC_EVENT_CAN_RXF = (316), // CANFD RX FIFO interrupt + ELC_EVENT_CAN_GLERR = (317), // CANFD Global error interrupt + ELC_EVENT_CAN0_TX = (318), // CAFND0 Channel TX interrupt + ELC_EVENT_CAN0_CHERR = (319), // CAFND0 Channel CAN error interrupt + ELC_EVENT_CAN0_COMFRX = (320), // CAFND0 Common RX FIFO or TXQ interrupt + ELC_EVENT_CAN1_TX = (321), // CAFND1 Channel TX interrupt + ELC_EVENT_CAN1_CHERR = (322), // CAFND1 Channel CAN error interrupt + ELC_EVENT_CAN1_COMFRX = (323), // CAFND1 Common RX FIFO or TXQ interrupt + ELC_EVENT_SPI0_SPRI = (324), // SPI0 Reception buffer full + ELC_EVENT_SPI0_SPTI = (325), // SPI0 Transmit buffer empty + ELC_EVENT_SPI0_SPII = (326), // SPI0 SPI idle + ELC_EVENT_SPI0_SPEI = (327), // SPI0 errors + ELC_EVENT_SPI0_SPCEND = (328), // SPI0 Communication complete + ELC_EVENT_SPI1_SPRI = (329), // SPI1 Reception buffer full + ELC_EVENT_SPI1_SPTI = (330), // SPI1 Transmit buffer empty + ELC_EVENT_SPI1_SPII = (331), // SPI1 SPI idle + ELC_EVENT_SPI1_SPEI = (332), // SPI1 errors + ELC_EVENT_SPI1_SPCEND = (333), // SPI1 Communication complete + ELC_EVENT_SPI2_SPRI = (334), // SPI2 Reception buffer full + ELC_EVENT_SPI2_SPTI = (335), // SPI2 Transmit buffer empty + ELC_EVENT_SPI2_SPII = (336), // SPI2 SPI idle + ELC_EVENT_SPI2_SPEI = (337), // SPI2 errors + ELC_EVENT_SPI2_SPCEND = (338), // SPI2 Communication complete + ELC_EVENT_XSPI0_INT = (339), // xSPI0 Interrupt + ELC_EVENT_XSPI0_INTERR = (340), // xSPI0 Error interrupt + ELC_EVENT_XSPI1_INT = (341), // xSPI1 Interrupt + ELC_EVENT_XSPI1_INTERR = (342), // xSPI1 Error interrupt + ELC_EVENT_DSMIF0_CDRUI = (343), // DSMIF0 current data register update (ORed ch0 to ch2) + ELC_EVENT_DSMIF1_CDRUI = (344), // DSMIF1 current data register update (ORed ch3 to ch5) + ELC_EVENT_ADC0_ADI = (345), // ADC0 A/D scan end interrupt + ELC_EVENT_ADC0_GBADI = (346), // ADC0 A/D scan end interrupt for Group B + ELC_EVENT_ADC0_GCADI = (347), // ADC0 A/D scan end interrupt for Group C + ELC_EVENT_ADC0_CMPAI = (348), // ADC0 Window A compare match + ELC_EVENT_ADC0_CMPBI = (349), // ADC0 Window B compare match + ELC_EVENT_ADC1_ADI = (350), // ADC1 A/D scan end interrupt + ELC_EVENT_ADC1_GBADI = (351), // ADC1 A/D scan end interrupt for Group B + ELC_EVENT_ADC1_GCADI = (352), // ADC1 A/D scan end interrupt for Group C + ELC_EVENT_ADC1_CMPAI = (353), // ADC1 Window A compare match + ELC_EVENT_ADC1_CMPBI = (354), // ADC1 Window B compare match + ELC_EVENT_MBX_INT0 = (372), // Mailbox (Host CPU to Cortex-R52) interrupt 0 + ELC_EVENT_MBX_INT1 = (373), // Mailbox (Host CPU to Cortex-R52) interrupt 1 + ELC_EVENT_MBX_INT2 = (374), // Mailbox (Host CPU to Cortex-R52) interrupt 2 + ELC_EVENT_MBX_INT3 = (375), // Mailbox (Host CPU to Cortex-R52) interrupt 3 + ELC_EVENT_CPU0_ERR0 = (384), // Cortex-R52 CPU0 error event 0 + ELC_EVENT_CPU0_ERR1 = (385), // Cortex-R52 CPU0 error event 1 + ELC_EVENT_PERI_ERR0 = (388), // Peripherals error event 0 + ELC_EVENT_PERI_ERR1 = (389), // Peripherals error event 1 + ELC_EVENT_SHOST_INT = (390), // SHOSTIF interrupt + ELC_EVENT_PHOST_INT = (391), // PHOSTIF interrupt + ELC_EVENT_INTCPU6 = (392), // Software interrupt 6 + ELC_EVENT_INTCPU7 = (393), // Software interrupt 7 + ELC_EVENT_IRQ14 = (394), // External pin interrupt 14 + ELC_EVENT_IRQ15 = (395), // External pin interrupt 15 + ELC_EVENT_GPT14_CCMPA = (396), // GPT14 GTCCRA input capture/compare match + ELC_EVENT_GPT14_CCMPB = (397), // GPT14 GTCCRB input capture/compare match + ELC_EVENT_GPT14_CMPC = (398), // GPT14 GTCCRC compare match + ELC_EVENT_GPT14_CMPD = (399), // GPT14 GTCCRD compare match + ELC_EVENT_GPT14_CMPE = (400), // GPT14 GTCCRE compare match + ELC_EVENT_GPT14_CMPF = (401), // GPT14 GTCCRF compare match + ELC_EVENT_GPT14_OVF = (402), // GPT14 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT14_UDF = (403), // GPT14 GTCNT underflow + ELC_EVENT_GPT15_CCMPA = (404), // GPT15 GTCCRA input capture/compare match + ELC_EVENT_GPT15_CCMPB = (405), // GPT15 GTCCRB input capture/compare match + ELC_EVENT_GPT15_CMPC = (406), // GPT15 GTCCRC compare match + ELC_EVENT_GPT15_CMPD = (407), // GPT15 GTCCRD compare match + ELC_EVENT_GPT15_CMPE = (408), // GPT15 GTCCRE compare match + ELC_EVENT_GPT15_CMPF = (409), // GPT15 GTCCRF compare match + ELC_EVENT_GPT15_OVF = (410), // GPT15 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT15_UDF = (411), // GPT15 GTCNT underflow + ELC_EVENT_GPT16_CCMPA = (412), // GPT16 GTCCRA input capture/compare match + ELC_EVENT_GPT16_CCMPB = (413), // GPT16 GTCCRB input capture/compare match + ELC_EVENT_GPT16_CMPC = (414), // GPT16 GTCCRC compare match + ELC_EVENT_GPT16_CMPD = (415), // GPT16 GTCCRD compare match + ELC_EVENT_GPT16_CMPE = (416), // GPT16 GTCCRE compare match + ELC_EVENT_GPT16_CMPF = (417), // GPT16 GTCCRF compare match + ELC_EVENT_GPT16_OVF = (418), // GPT16 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT16_UDF = (419), // GPT16 GTCNT underflow + ELC_EVENT_GPT17_CCMPA = (420), // GPT17 GTCCRA input capture/compare match + ELC_EVENT_GPT17_CCMPB = (421), // GPT17 GTCCRB input capture/compare match + ELC_EVENT_GPT17_CMPC = (422), // GPT17 GTCCRC compare match + ELC_EVENT_GPT17_CMPD = (423), // GPT17 GTCCRD compare match + ELC_EVENT_GPT17_CMPE = (424), // GPT17 GTCCRE compare match + ELC_EVENT_GPT17_CMPF = (425), // GPT17 GTCCRF compare match + ELC_EVENT_GPT17_OVF = (426), // GPT17 GTCNT overflow (GTPR compare match) + ELC_EVENT_GPT17_UDF = (427), // GPT17 GTCNT underflow + ELC_EVENT_POEG2_GROUP0 = (428), // POEG group A interrupt for channels in SAFETY + ELC_EVENT_POEG2_GROUP1 = (429), // POEG group B interrupt for channels in SAFETY + ELC_EVENT_POEG2_GROUP2 = (430), // POEG group C interrupt for channels in SAFETY + ELC_EVENT_POEG2_GROUP3 = (431), // POEG group D interrupt for channels in SAFETY + ELC_EVENT_RTC_ALM = (432), // Alarm interrupt + ELC_EVENT_RTC_1S = (433), // 1 second interrupt + ELC_EVENT_RTC_PRD = (434), // Fixed interval interrupt + ELC_EVENT_SCI5_ERI = (435), // SCI5 Receive error + ELC_EVENT_SCI5_RXI = (436), // SCI5 Receive data full + ELC_EVENT_SCI5_TXI = (437), // SCI5 Transmit data empty + ELC_EVENT_SCI5_TEI = (438), // SCI5 Transmit end + ELC_EVENT_IIC2_EEI = (439), // IIC2 Transfer error or event generation + ELC_EVENT_IIC2_RXI = (440), // IIC2 Receive data full + ELC_EVENT_IIC2_TXI = (441), // IIC2 Transmit data empty + ELC_EVENT_IIC2_TEI = (442), // IIC2 Transmit end + ELC_EVENT_SPI3_SPRI = (443), // SPI3 Reception buffer full + ELC_EVENT_SPI3_SPTI = (444), // SPI3 Transmit buffer empty + ELC_EVENT_SPI3_SPII = (445), // SPI3 SPI idle + ELC_EVENT_SPI3_SPEI = (446), // SPI3 errors + ELC_EVENT_SPI3_SPCEND = (447), // SPI3 Communication complete + ELC_EVENT_DREQ = (448), // External DMA request + ELC_EVENT_CAN_RF_DMAREQ0 = (449), // CAFND RX FIFO 0 DMA request + ELC_EVENT_CAN_RF_DMAREQ1 = (450), // CAFND RX FIFO 1 DMA request + ELC_EVENT_CAN_RF_DMAREQ2 = (451), // CAFND RX FIFO 2 DMA request + ELC_EVENT_CAN_RF_DMAREQ3 = (452), // CAFND RX FIFO 3 DMA request + ELC_EVENT_CAN_RF_DMAREQ4 = (453), // CAFND RX FIFO 4 DMA request + ELC_EVENT_CAN_RF_DMAREQ5 = (454), // CAFND RX FIFO 5 DMA request + ELC_EVENT_CAN_RF_DMAREQ6 = (455), // CAFND RX FIFO 6 DMA request + ELC_EVENT_CAN_RF_DMAREQ7 = (456), // CAFND RX FIFO 7 DMA request + ELC_EVENT_CAN0_CF_DMAREQ = (457), // CAFND0 First common FIFO DMA request + ELC_EVENT_CAN1_CF_DMAREQ = (458), // CAFND1 First common FIFO DMA request + ELC_EVENT_ADC0_WCMPM = (459), // ADC0 compare match + ELC_EVENT_ADC0_WCMPUM = (460), // ADC0 compare mismatch + ELC_EVENT_ADC1_WCMPM = (461), // ADC1 compare match + ELC_EVENT_ADC1_WCMPUM = (462), // ADC1 compare mismatch + ELC_EVENT_TCIV4_OF = (463), // MTU4.TCNT overflow + ELC_EVENT_TCIV4_UF = (464), // MTU4.TCNT underflow + ELC_EVENT_TCIV7_OF = (465), // MTU7.TCNT overflow + ELC_EVENT_TCIV7_UF = (466), // MTU7.TCNT underflow + ELC_EVENT_IOPORT_GROUP1 = (467), // Input edge detection of input port group 1 + ELC_EVENT_IOPORT_GROUP2 = (468), // Input edge detection of input port group 2 + ELC_EVENT_IOPORT_SINGLE0 = (469), // Input edge detection of single input port 0 + ELC_EVENT_IOPORT_SINGLE1 = (470), // Input edge detection of single input port 1 + ELC_EVENT_IOPORT_SINGLE2 = (471), // Input edge detection of single input port 2 + ELC_EVENT_IOPORT_SINGLE3 = (472), // Input edge detection of single input port 3 + ELC_EVENT_GPT0_ADTRGA = (473), // GPT0 GTADTRA compare match + ELC_EVENT_GPT0_ADTRGB = (474), // GPT0 GTADTRB compare match + ELC_EVENT_GPT1_ADTRGA = (475), // GPT1 GTADTRA compare match + ELC_EVENT_GPT1_ADTRGB = (476), // GPT1 GTADTRB compare match + ELC_EVENT_GPT2_ADTRGA = (477), // GPT2 GTADTRA compare match + ELC_EVENT_GPT2_ADTRGB = (478), // GPT2 GTADTRB compare match + ELC_EVENT_GPT3_ADTRGA = (479), // GPT3 GTADTRA compare match + ELC_EVENT_GPT3_ADTRGB = (480), // GPT3 GTADTRB compare match + ELC_EVENT_GPT4_ADTRGA = (481), // GPT4 GTADTRA compare match + ELC_EVENT_GPT4_ADTRGB = (482), // GPT4 GTADTRB compare match + ELC_EVENT_GPT5_ADTRGA = (483), // GPT5 GTADTRA compare match + ELC_EVENT_GPT5_ADTRGB = (484), // GPT5 GTADTRB compare match + ELC_EVENT_GPT6_ADTRGA = (485), // GPT6 GTADTRA compare match + ELC_EVENT_GPT6_ADTRGB = (486), // GPT6 GTADTRB compare match + ELC_EVENT_GPT7_ADTRGA = (487), // GPT7 GTADTRA compare match + ELC_EVENT_GPT7_ADTRGB = (488), // GPT7 GTADTRB compare match + ELC_EVENT_GPT8_ADTRGA = (489), // GPT8 GTADTRA compare match + ELC_EVENT_GPT8_ADTRGB = (490), // GPT8 GTADTRB compare match + ELC_EVENT_GPT9_ADTRGA = (491), // GPT9 GTADTRA compare match + ELC_EVENT_GPT9_ADTRGB = (492), // GPT9 GTADTRB compare match + ELC_EVENT_GPT10_ADTRGA = (493), // GPT10 GTADTRA compare match + ELC_EVENT_GPT10_ADTRGB = (494), // GPT10 GTADTRB compare match + ELC_EVENT_GPT11_ADTRGA = (495), // GPT11 GTADTRA compare match + ELC_EVENT_GPT11_ADTRGB = (496), // GPT11 GTADTRB compare match + ELC_EVENT_GPT12_ADTRGA = (497), // GPT12 GTADTRA compare match + ELC_EVENT_GPT12_ADTRGB = (498), // GPT12 GTADTRB compare match + ELC_EVENT_GPT13_ADTRGA = (499), // GPT13 GTADTRA compare match + ELC_EVENT_GPT13_ADTRGB = (500), // GPT13 GTADTRB compare match + ELC_EVENT_NONE +} elc_event_t; + +/** @} (end addtogroup BSP_MCU_RZN2L) */ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h new file mode 100644 index 00000000000..f4a7fa9a188 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_feature.h @@ -0,0 +1,242 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef BSP_FEATURE_H +#define BSP_FEATURE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#define BSP_FEATURE_ADC_ADDITION_SUPPORTED (1U) +#define BSP_FEATURE_ADC_CALIBRATION_REG_AVAILABLE (0U) +#define BSP_FEATURE_ADC_CLOCK_SOURCE (FSP_PRIV_CLOCK_PCLKADC) +#define BSP_FEATURE_ADC_GROUP_B_SENSORS_ALLOWED (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADPRC (1U) +#define BSP_FEATURE_ADC_HAS_ADCER_ADRFMT (1U) +#define BSP_FEATURE_ADC_HAS_PGA (1U) +#define BSP_FEATURE_ADC_HAS_SAMPLE_HOLD_REG (1U) +#define BSP_FEATURE_ADC_HAS_VREFAMPCNT (0U) +#define BSP_FEATURE_ADC_MAX_RESOLUTION_BITS (12U) +#define BSP_FEATURE_ADC_REGISTER_MASK_TYPE (1U) +#define BSP_FEATURE_ADC_SENSOR_MIN_SAMPLING_TIME (4150U) +#define BSP_FEATURE_ADC_SENSORS_EXCLUSIVE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION_AVAILABLE (0U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_CALIBRATION32_MASK (0x00000FFFU) +#define BSP_FEATURE_ADC_TSN_CONTROL_AVAILABLE (1U) +#define BSP_FEATURE_ADC_TSN_SLOPE (4000U) +#define BSP_FEATURE_ADC_UNIT_0_CHANNELS (0x000F) // 0 to 3 in unit 0 +#define BSP_FEATURE_ADC_UNIT_1_CHANNELS (0x00FF) // 0 to 7 in unit 1 +#define BSP_FEATURE_ADC_VALID_UNIT_MASK (3U) + +#define BSP_FEATURE_BSP_IRQ_PRIORITY_MASK (0xF8U) +#define BSP_FEATURE_BSP_IRQ_PRIORITY_POS_BIT (3U) +#define BSP_FEATURE_BSP_MASTER_MPU0_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU1_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU2_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU3_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU4_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU6_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU7_SUPPORTED (1U) +#define BSP_FEATURE_BSP_MASTER_MPU8_SUPPORTED (1U) + +#define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) +#define BSP_FEATURE_CAN_CLOCK (0U) +#define BSP_FEATURE_CAN_MCLOCK_ONLY (0U) +#define BSP_FEATURE_CAN_NUM_CHANNELS (2U) + +#define BSP_FEATURE_CANFD_NUM_CHANNELS (2U) + +#define BSP_FEATURE_CGC_HAS_BCLK (1U) +#define BSP_FEATURE_CGC_HAS_FCLK (1U) +#define BSP_FEATURE_CGC_HAS_FLDWAITR (0U) +#define BSP_FEATURE_CGC_HAS_FLWT (1U) +#define BSP_FEATURE_CGC_HAS_HOCOWTCR (1U) +#define BSP_FEATURE_CGC_HAS_MEMWAIT (0U) +#define BSP_FEATURE_CGC_HAS_PCLKA (1U) +#define BSP_FEATURE_CGC_HAS_PCLKB (1U) +#define BSP_FEATURE_CGC_HAS_PCLKC (1U) +#define BSP_FEATURE_CGC_HAS_PCLKD (1U) +#define BSP_FEATURE_CGC_HAS_PLL (1U) +#define BSP_FEATURE_CGC_HAS_PLL2 (0U) +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) +#define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) +#define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) +#define BSP_FEATURE_CGC_LOCO_CONTROL_ADDRESS (0x81280070U) +#define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) +#define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz +#define BSP_FEATURE_CGC_LOW_VOLTAGE_MAX_FREQ_HZ (0U) // This MCU does not have Low Voltage Mode +#define BSP_FEATURE_CGC_MIDDLE_SPEED_MAX_FREQ_HZ (0U) // This MCU does not have Middle Speed Mode +#define BSP_FEATURE_CGC_MOCO_STABILIZATION_MAX_US (15U) +#define BSP_FEATURE_CGC_MODRV_MASK (0x30U) +#define BSP_FEATURE_CGC_MODRV_SHIFT (0x4U) +#define BSP_FEATURE_CGC_PLL1_CONTROL_ADDRESS (0x81280050U) +#define BSP_FEATURE_CGC_PLLCCR_MAX_HZ (240000000U) +#define BSP_FEATURE_CGC_PLLCCR_TYPE (1U) +#define BSP_FEATURE_CGC_PLLCCR_WAIT_US (0U) // No wait between setting PLLCCR and clearing PLLSTP +#define BSP_FEATURE_CGC_SCKDIVCR_BCLK_MATCHES_PCLKB (0U) +#define BSP_FEATURE_CGC_SODRV_MASK (0x02U) +#define BSP_FEATURE_CGC_SODRV_SHIFT (0x1U) +#define BSP_FEATURE_CGC_STARTUP_OPCCR_MODE (0U) + +#define BSP_FEATURE_CMT_VALID_CHANNEL_MASK (0x3FU) + +#define BSP_FEATURE_CMTW_VALID_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_CRC_VALID_CHANNEL_MASK (0x3U) + +#define BSP_FEATURE_DMAC_MAX_CHANNEL (8U) +#define BSP_FEATURE_DMAC_MAX_UNIT (2U) +#define BSP_FEATURE_DMAC_UNIT0_ERROR_NUM (5U) + +#define BSP_FEATURE_DSMIF_CHANNEL_STATUS (1U) +#define BSP_FEATURE_DSMIF_DATA_FORMAT_SEL (0U) +#define BSP_FEATURE_DSMIF_ERROR_STATUS_CLR (5U) +#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_CONTROL (1U) +#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_ISR (1U) +#define BSP_FEATURE_DSMIF_OVERCURRENT_DETECT_NOTIFY (0U) +#define BSP_FEATURE_DSMIF_OVERCURRENT_ERROR_STATUS (1U) +#define BSP_FEATURE_DSMIF_OVERCURRENT_NOTIFY_STATUS (0U) + +#define BSP_FEATURE_ELC_ELC_SSEL_NUM (19) +#define BSP_FEATURE_ELC_EVENT_MASK_NUM (4U) +#define BSP_FEATURE_ELC_PERIPHERAL_0_MASK (0xFFFFFFFFU) // ELC event source no.0 to 31 available on this MCU +#define BSP_FEATURE_ELC_PERIPHERAL_1_MASK (0x007FF9FFU) // ELC event source no.32 to 63 available on this MCU. +#define BSP_FEATURE_ELC_PERIPHERAL_2_MASK (0x00000000U) // ELC event source no.64 to 95 available on this MCU. +#define BSP_FEATURE_ELC_PERIPHERAL_3_MASK (0x00000000U) // ELC event source no.96 to 127 available on this MCU. +#define BSP_FEATURE_ELC_PERIPHERAL_TYPE (1U) + +#define BSP_FEATURE_ESC_MAX_PORTS (3U) +#define BSP_FEATURE_ETHER_FIFO_DEPTH (0x0000070FU) +#define BSP_FEATURE_ETHER_PHY_MAX_CHANNELS (3U) +#define BSP_FEATURE_ETHSS_MAX_PORTS (3U) +#define BSP_FEATURE_ETHSS_SWITCH_MODE_BIT_MASK (3U) + +#define BSP_FEATURE_ETHSW_MAX_CHANNELS (1U) +#define BSP_FEATURE_ETHSW_SUPPORTED (1U) +#define BSP_FEATURE_GMAC_MAX_CHANNELS (1U) +#define BSP_FEATURE_GMAC_MAX_PORTS (3U) + +#define BSP_FEATURE_GPT_32BIT_CHANNEL_MASK (0x3FFFF) +#define BSP_FEATURE_GPT_LLPP_BASE_CHANNEL (0) // LLPP channel: ch0-6 +#define BSP_FEATURE_GPT_LLPP_CHANNEL_MASK (0x0007F) +#define BSP_FEATURE_GPT_NONSAFETY_BASE_CHANNEL (7) // Non-safety channel: ch7-13 +#define BSP_FEATURE_GPT_NONSAFETY_CHANNEL_MASK (0x0007F) +#define BSP_FEATURE_GPT_SAFETY_BASE_CHANNEL (14) // safety channel: ch14-17 +#define BSP_FEATURE_GPT_SAFETY_CHANNEL_MASK (0x0000F) +#define BSP_FEATURE_GPT_VALID_CHANNEL_MASK (0x3FFFF) + +#define BSP_FEATURE_GPTE_CHANNEL_MASK (0xF0) +#define BSP_FEATURE_GPTEH_CHANNEL_MASK (0xF) + +#define BSP_FEATURE_ICU_ERROR_PERI_ERR_REG_NUM (2U) +#define BSP_FEATURE_ICU_ERROR_PERI_ERR0_REG_MASK (0xFFFFFEFFU) +#define BSP_FEATURE_ICU_ERROR_PERI_ERR1_REG_MASK (0x19FFA3FFU) +#define BSP_FEATURE_ICU_ERROR_PERIPHERAL_TYPE (1U) +#define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) +#define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) +#define BSP_FEATURE_ICU_WUPEN_MASK (0xFF4FFFFFU) + +#define BSP_FEATURE_IIC_FAST_MODE_PLUS (0U) +#define BSP_FEATURE_IIC_SAFETY_CHANNEL (2U) +#define BSP_FEATURE_IIC_SAFETY_CHANNEL_BASE_ADDRESS (R_IIC2_BASE) +#define BSP_FEATURE_IIC_VALID_CHANNEL_MASK (0x07) + +#define BSP_FEATURE_IOPORT_ELC_PORTS (4U) +#define BSP_FEATURE_IOPORT_HAS_ETHERNET (1U) + +#define BSP_FEATURE_LPM_CHANGE_MSTP_ARRAY {{0, 15}, {0, 13}, {1, 31}, {1, 6}, {1, 5}, {1, 4}, {2, 5}} +#define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) +#define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00137FFFU) +#define BSP_FEATURE_LPM_DPSIER_MASK (0x071F7FFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) +#define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) +#define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) +#define BSP_FEATURE_LPM_HAS_STCONR (1U) +#define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0U) +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) + +#define BSP_FEATURE_MTU3_MAX_CHANNELS (9U) +#define BSP_FEATURE_MTU3_UVW_MAX_CHANNELS (3U) +#define BSP_FEATURE_MTU3_VALID_CHANNEL_MASK (0x01FF) + +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) + +#define BSP_FEATURE_POE3_ERROR_SIGNAL_TYPE (1U) +#define BSP_FEATURE_POE3_PIN_SELECT_TYPE (1U) + +#define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) +#define BSP_FEATURE_POEG_ERROR_SIGNAL_TYPE (1U) +#define BSP_FEATURE_POEG_GROUP_OFSSET_ADDRESS (0x400) +#define BSP_FEATURE_POEG_LLPP_UNIT (0U) +#define BSP_FEATURE_POEG_MAX_UNIT (2U) +#define BSP_FEATURE_POEG_NONSAFETY_UNIT (1U) +#define BSP_FEATURE_POEG_SAFETY_UNIT (2U) + +#define BSP_FEATURE_SCI_ADDRESS_MATCH_CHANNELS (BSP_FEATURE_SCI_CHANNELS) +#define BSP_FEATURE_SCI_CHANNELS (0x3FU) +#define BSP_FEATURE_SCI_SAFETY_CHANNEL (5U) +#define BSP_FEATURE_SCI_SAFETY_CHANNEL_BASE_ADDRESS (R_SCI5_BASE) +#define BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS (0x03FU) +#define BSP_FEATURE_SCI_UART_FIFO_CHANNELS (0x3FFU) +#define BSP_FEATURE_SCI_UART_FIFO_DEPTH (16U) + +#define BSP_FEATURE_SEM_SUPPORTED (0U) + +#define BSP_FEATURE_SPI_HAS_BYTE_SWAP (1U) +#define BSP_FEATURE_SPI_HAS_SPCR3 (0U) +#define BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP (1U) +#define BSP_FEATURE_SPI_MAX_CHANNEL (4U) +#define BSP_FEATURE_SPI_SAFETY_CHANNEL (3U) +#define BSP_FEATURE_SPI_SAFETY_CHANNEL_BASE_ADDRESS (R_SPI3_BASE) + +#define BSP_FEATURE_TFU_SUPPORTED (1U) + +#define BSP_FEATURE_XSPI_CHANNELS (0x03U) +#define BSP_FEATURE_XSPI_NUM_CHIP_SELECT (2U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c new file mode 100644 index 00000000000..b524d268706 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_irq_sense.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RZN2L + * @{ + **********************************************************************************************************************/ + +/** Array of GICD_ICFGR initialization value. */ +const uint32_t BSP_GICD_ICFGR_INIT[BSP_NON_SELECTABLE_ICFGR_MAX] = +{ + 0xAAAAAAAAUL, /* Event No. 0 to 15 */ + 0x000000AAUL, /* Event No. 16 to 31 */ + 0x00000000UL, /* Event No. 32 to 47 */ + 0xAAAAA800UL, /* Event No. 48 to 63 */ + 0xAAAAAAAAUL, /* Event No. 64 to 79 */ + 0xAAAAAAAAUL, /* Event No. 80 to 95 */ + 0xAAAAAAAAUL, /* Event No. 96 to 111 */ + 0xAAAAAA00UL, /* Event No. 112 to 127 */ + 0xAAAAAAAAUL, /* Event No. 128 to 143 */ + 0xAAAAAAAAUL, /* Event No. 144 to 159 */ + 0xAAAAAAAAUL, /* Event No. 160 to 175 */ + 0xAAAAAAAAUL, /* Event No. 176 to 191 */ + 0xAAAAAAAAUL, /* Event No. 192 to 207 */ + 0xAAAAAAAAUL, /* Event No. 208 to 223 */ + 0xAAAAAAAAUL, /* Event No. 224 to 239 */ + 0x0000000AUL, /* Event No. 240 to 255 */ + 0xA8000000UL, /* Event No. 256 to 271 */ + 0xA82A2AAAUL, /* Event No. 272 to 287 */ + 0x28282828UL, /* Event No. 288 to 303 */ + 0x00282828UL, /* Event No. 304 to 319 */ + 0xA82A0A00UL, /* Event No. 320 to 335 */ + 0xA0AA8020UL, /* Event No. 336 to 351 */ + 0x00000002UL, /* Event No. 352 to 367 */ + 0x00000000UL, /* Event No. 368 to 383 */ + 0xAAAA0A0AUL, /* Event No. 384 to 399 */ + 0xAAAAAAAAUL, /* Event No. 400 to 415 */ + 0x00AAAAAAUL, /* Event No. 416 to 431 */ + 0x828A0A2AUL, /* Event No. 432 to 447 */ +}; + +const uint32_t BSP_GICR_SGI_PPI_ICFGR_INIT[BSP_EVENT_SGI_PPI_ARRAY_NUM] = +{ + 0xAAAAAAAAUL, /* event SGI */ + 0x00020000UL, /* event PPI */ +}; + +/** @} (end addtogroup BSP_MCU_RZN2L) */ + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c new file mode 100644 index 00000000000..3933a103ba5 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_loader_param.c @@ -0,0 +1,69 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ +#include "bsp_api.h" + +#if !(BSP_CFG_RAM_EXECUTION) + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + #define BSP_LOADER_PARAM_MAX (19) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global variables (to be accessed by other files) + **********************************************************************************************************************/ + +/* Parameter Information for the Loader. */ +BSP_DONT_REMOVE const uint32_t g_bsp_loader_param[BSP_LOADER_PARAM_MAX] BSP_PLACE_IN_SECTION(BSP_SECTION_LOADER_PARAM) = +{ + BSP_CFG_CACHE_FLG, + BSP_CFG_CS0BCR_V_WRAPCFG_V, + BSP_CFG_CS0WCR_V_COMCFG_V, + BSP_CFG_DUMMY0_BMCFG_V, + BSP_CFG_BSC_FLG_xSPI_FLG, + BSP_CFG_LDR_ADDR_NML, + BSP_CFG_LDR_SIZE_NML, + BSP_CFG_DEST_ADDR_NML, + BSP_CFG_DUMMY1, + BSP_CFG_DUMMY2, + BSP_CFG_DUMMY3_CSSCTL_V, + BSP_CFG_DUMMY4_LIOCFGCS0_V, + BSP_CFG_DUMMY5, + BSP_CFG_DUMMY6, + BSP_CFG_DUMMY7, + BSP_CFG_DUMMY8, + BSP_CFG_DUMMY9, + BSP_CFG_DUMMY10_ACCESS_SPEED, + BSP_CFG_CHECK_SUM +}; + +/*********************************************************************************************************************** + * Private global variables and functions + **********************************************************************************************************************/ + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h new file mode 100644 index 00000000000..e0b338a753e --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @ingroup BSP_MCU + * @defgroup BSP_MCU_RZN2L RZN2L + * @includedoc config_bsp_rzn2l_fsp.html + * @{ + **********************************************************************************************************************/ + +/** @} (end defgroup BSP_MCU_RZN2L) */ + +#ifndef BSP_MCU_INFO_H +#define BSP_MCU_INFO_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP MCU Specific Includes. */ +#include "bsp_elc.h" +#include "bsp_feature.h" + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef elc_event_t bsp_interrupt_event_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h new file mode 100644 index 00000000000..ea77b6eb9aa --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/bsp/mcu/rzn2l/bsp_override.h @@ -0,0 +1,1455 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup BSP_MCU_RZN2L + * @{ + **********************************************************************************************************************/ + +/** @} (end addtogroup BSP_MCU_RZN2L) */ + +#ifndef BSP_OVERRIDE_H +#define BSP_OVERRIDE_H + +/*********************************************************************************************************************** + * Includes , "Project Includes" + **********************************************************************************************************************/ + +/* BSP Common Includes. */ +#include "../../src/bsp/mcu/all/bsp_common.h" + +/* BSP MPU Specific Includes. */ +#include "../../src/bsp/mcu/all/bsp_register_protection.h" +#include "../../src/bsp/mcu/all/bsp_irq.h" +#include "../../src/bsp/mcu/all/bsp_io.h" +#include "../../src/bsp/mcu/all/bsp_clocks.h" +#include "../../src/bsp/mcu/all/bsp_module_stop.h" +#include "../../src/bsp/mcu/all/bsp_reset.h" +#include "../../src/bsp/mcu/all/bsp_cache.h" + +/* Factory MPU information. */ +#include "../../inc/fsp_features.h" + +/* BSP Common Includes (Other than bsp_common.h) */ +#include "../../src/bsp/mcu/all/bsp_delay.h" +#include "../../src/bsp/mcu/all/bsp_mcu_api.h" + +/* BSP TFU Includes. */ +#if BSP_FEATURE_TFU_SUPPORTED + #include "../../src/bsp/mcu/all/bsp_tfu.h" +#endif + +/** Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Define overrides required for this MPU. */ +#define BSP_OVERRIDE_ADC_MODE_T +#define BSP_OVERRIDE_ADC_CHANNEL_T +#define BSP_OVERRIDE_CGC_CLOCK_T +#define BSP_OVERRIDE_CGC_PLL_CFG_T +#define BSP_OVERRIDE_CGC_DIVIDER_CFG_T +#define BSP_OVERRIDE_CGC_CLOCK_CHANGE_T +#define BSP_OVERRIDE_CGC_CLOCKS_CFG_T +#define BSP_OVERRIDE_ELC_PERIPHERAL_T +#define BSP_OVERRIDE_ERROR_EVENT_T +#define BSP_OVERRIDE_ETHER_EVENT_T +#define BSP_OVERRIDE_ETHER_CALLBACK_ARGS_T +#define BSP_OVERRIDE_ETHER_PHY_LSI_TYPE_T +#define BSP_OVERRIDE_ETHER_SWITCH_CALLBACK_ARGS_T +#define BSP_OVERRIDE_POE3_STATE_T +#define BSP_OVERRIDE_POEG_STATE_T +#define BSP_OVERRIDE_POEG_TRIGGER_T +#define BSP_OVERRIDE_TRANSFER_MODE_T +#define BSP_OVERRIDE_TRANSFER_SIZE_T +#define BSP_OVERRIDE_TRANSFER_ADDR_MODE_T +#define BSP_OVERRIDE_TRANSFER_CALLBACK_ARGS_T +#define BSP_OVERRIDE_TRANSFER_INFO_T + +/* Override definitions. */ + +#define ELC_PERIPHERAL_NUM (55U) + +/* Private definition to set enumeration values. */ +#define IOPORT_P_OFFSET (0U) +#define IOPORT_PM_OFFSET (1U) +#define IOPORT_PMC_OFFSET (3U) +#define IOPORT_PFC_OFFSET (4U) +#define IOPORT_DRCTL_OFFSET (8U) +#define IOPORT_RSELP_OFFSET (14U) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/*============================================== + * ADC API Overrides + *==============================================*/ + +/** ADC operation mode definitions */ +typedef enum e_adc_mode +{ + ADC_MODE_SINGLE_SCAN = 0, ///< Single scan - one or more channels + ADC_MODE_GROUP_SCAN = 1, ///< Two trigger sources to trigger scan for two groups which contain one or more channels + ADC_MODE_CONTINUOUS_SCAN = 2, ///< Continuous scan - one or more channels + ADC_MODE_SYNCHRONIZE_SCAN = 3, ///< Channel synchronization control mode + ADC_MODE_INDIVIDUAL_SCAN = 4, ///< Channel individual control mode +} adc_mode_t; + +/** ADC channels */ +typedef enum e_adc_channel +{ + ADC_CHANNEL_0 = 0, ///< ADC channel 0 + ADC_CHANNEL_1 = 1, ///< ADC channel 1 + ADC_CHANNEL_2 = 2, ///< ADC channel 2 + ADC_CHANNEL_3 = 3, ///< ADC channel 3 + ADC_CHANNEL_4 = 4, ///< ADC channel 4 + ADC_CHANNEL_5 = 5, ///< ADC channel 5 + ADC_CHANNEL_6 = 6, ///< ADC channel 6 + ADC_CHANNEL_7 = 7, ///< ADC channel 7 + ADC_CHANNEL_8 = 8, ///< ADC channel 8 + ADC_CHANNEL_9 = 9, ///< ADC channel 9 + ADC_CHANNEL_10 = 10, ///< ADC channel 10 + ADC_CHANNEL_11 = 11, ///< ADC channel 11 + ADC_CHANNEL_12 = 12, ///< ADC channel 12 + ADC_CHANNEL_13 = 13, ///< ADC channel 13 + ADC_CHANNEL_14 = 14, ///< ADC channel 14 + ADC_CHANNEL_15 = 15, ///< ADC channel 15 + ADC_CHANNEL_16 = 16, ///< ADC channel 16 + ADC_CHANNEL_17 = 17, ///< ADC channel 17 + ADC_CHANNEL_18 = 18, ///< ADC channel 18 + ADC_CHANNEL_19 = 19, ///< ADC channel 19 + ADC_CHANNEL_20 = 20, ///< ADC channel 20 + ADC_CHANNEL_21 = 21, ///< ADC channel 21 + ADC_CHANNEL_22 = 22, ///< ADC channel 22 + ADC_CHANNEL_23 = 23, ///< ADC channel 23 + ADC_CHANNEL_24 = 24, ///< ADC channel 24 + ADC_CHANNEL_25 = 25, ///< ADC channel 25 + ADC_CHANNEL_26 = 26, ///< ADC channel 26 + ADC_CHANNEL_27 = 27, ///< ADC channel 27 + ADC_CHANNEL_DUPLEX_A = 50, ///< Data duplexing register A + ADC_CHANNEL_DUPLEX_B = 51, ///< Data duplexing register B + ADC_CHANNEL_DUPLEX = -4, ///< Data duplexing register + ADC_CHANNEL_TEMPERATURE = -3, ///< Temperature sensor output + ADC_CHANNEL_VOLT = -2, ///< Internal reference voltage + ADC_CHANNEL_0_DSMIF_CAPTURE_A = 0x100, ///< ADC channel 0 Capture Current Data Register A + ADC_CHANNEL_0_DSMIF_CAPTURE_B = 0x200, ///< ADC channel 0 Capture Current Data Register B + ADC_CHANNEL_1_DSMIF_CAPTURE_A = 0x101, ///< ADC channel 1 Capture Current Data Register A + ADC_CHANNEL_1_DSMIF_CAPTURE_B = 0x201, ///< ADC channel 1 Capture Current Data Register B + ADC_CHANNEL_2_DSMIF_CAPTURE_A = 0x102, ///< ADC channel 2 Capture Current Data Register A + ADC_CHANNEL_2_DSMIF_CAPTURE_B = 0x202, ///< ADC channel 2 Capture Current Data Register B +} adc_channel_t; + +/*============================================== + * CGC API Overrides + *==============================================*/ + +/** Divider values of clock provided to xSPI */ +typedef enum e_cgc_fsel_xspi_clock_div +{ + CGC_FSEL_XSPI_CLOCK_DIV_6 = 0x02, ///< XSPI_CLKn 133.3MHz (XSPI base clock divided by 3) + CGC_FSEL_XSPI_CLOCK_DIV_8 = 0x03, ///< XSPI_CLKn 100.0MHz / 75.0MHz (XSPI base clock divided by 3 / divided by 4) + CGC_FSEL_XSPI_CLOCK_DIV_16 = 0x04, ///< XSPI_CLKn 50.0MHz / 37.5MHz (XSPI base clock divided by 3 / divided by 4) + CGC_FSEL_XSPI_CLOCK_DIV_32 = 0x05, ///< XSPI_CLKn 25.0MHz (XSPI base clock divided by 3) + CGC_FSEL_XSPI_CLOCK_DIV_64 = 0x06, ///< XSPI_CLKn 12.5MHz (XSPI base clock divided by 3) +} cgc_fsel_xspi_clock_div_t; + +/** Divider values of base clock generated for xSPI */ +typedef enum e_cgc_divsel_xspi_clock_div +{ + CGC_DIVSEL_XSPI_CLOCK_DIV_3 = 0x00, ///< XSPI base clock divided by 3 + CGC_DIVSEL_XSPI_CLOCK_DIV_4 = 0x01, ///< XSPI base clock divided by 4 +} cgc_divsel_xspi_clock_div_t; + +/** Clock output divider values */ +typedef enum e_cgc_clock_out_clock_div +{ + CGC_CLOCK_OUT_CLOCK_DIV_2 = 0, ///< CKIO 100.0MHz / 75.0MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_3 = 1, ///< CKIO 66.7MHz / 50.0MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_4 = 2, ///< CKIO 50.0MHz / 37.5MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_5 = 3, ///< CKIO 40.0MHz / 30.0MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_6 = 4, ///< CKIO 33.3MHz / 25.0MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_7 = 5, ///< CKIO 28.6MHz / 21.4MHz (Base clock divided by 3 / divided by 4) + CGC_CLOCK_OUT_CLOCK_DIV_8 = 6, ///< CKIO 25.0MHz / 18.75MHz (Base clock divided by 3 / divided by 4) +} cgc_clock_out_clock_div_t; + +/** CANFD clock divider values */ +typedef enum e_cgc_canfd_clock_div +{ + CGC_CANFD_CLOCK_DIV_10 = 0, ///< CANFD clock 80.0MHz + CGC_CANFD_CLOCK_DIV_20 = 1, ///< CANFD clock 40.0MHz +} cgc_canfd_clock_div_t; + +/** PHY clock source identifiers */ +typedef enum e_cgc_phy_clock +{ + CGC_PHY_CLOCK_PLL1 = 0, ///< PLL1 divider clock + CGC_PHY_CLOCK_MAIN_OSC = 1, ///< Main clock oscillator +} cgc_phy_clock_t; + +/** SPI asynchronous serial clock frequency */ +typedef enum e_cgc_spi_async_clock +{ + CGC_SPI_ASYNC_CLOCK_75MHZ = 0, ///< SPI asynchronous serial clock 75MHz + CGC_SPI_ASYNC_CLOCK_96MHZ = 1, ///< SPI asynchronous serial clock 96MHz +} cgc_spi_async_clock_t; + +/** SCI asynchronous serial clock frequency */ +typedef enum e_cgc_sci_async_clock +{ + CGC_SCI_ASYNC_CLOCK_75MHZ = 0, ///< SCI asynchronous serial clock 75MHz + CGC_SCI_ASYNC_CLOCK_96MHZ = 1, ///< SCI asynchronous serial clock 96MHz +} cgc_sci_async_clock_t; + +/** CPU clock divider values */ +typedef enum e_cgc_cpu_clock_div +{ + CGC_CPU_CLOCK_DIV_2 = 0, ///< CPU 200.0MHz / 150.0MHz (Base clock divided by 3 / divided by 4) + CGC_CPU_CLOCK_DIV_1 = 1, ///< CPU 400.0MHz / 300.0MHz (Base clock divided by 3 / divided by 4) +} cgc_cpu_clock_div_t; + +/** Base clock divider values */ +typedef enum e_cgc_baseclock_div +{ + CGC_BASECLOCK_DIV_3 = 0, ///< Base clock divided by 3 (ICLK=200.0MHz etc.) + CGC_BASECLOCK_DIV_4 = 1, ///< Base clock divided by 4 (ICLK=150.0MHz etc.) +} cgc_baseclock_div_t; + +/** System clock source identifiers */ +typedef enum e_cgc_clock +{ + CGC_CLOCK_LOCO = 0, ///< The low speed on chip oscillator + CGC_CLOCK_PLL0 = 1, ///< The PLL0 oscillator + CGC_CLOCK_PLL1 = 2, ///< The PLL1 oscillator +} cgc_clock_t; + +/** Clock configuration structure - Dummy definition because it is not used in this MPU. + * Set NULL as an input parameter to the @ref cgc_api_t::clockStart function for the PLL clock. */ +typedef struct st_cgc_pll_cfg +{ + uint32_t dummy; /* Dummy. */ +} cgc_pll_cfg_t; + +/** Clock configuration structure */ +typedef struct st_cgc_divider_cfg +{ + union + { + uint32_t sckcr_w; ///< System Clock Control Register + + struct + { + cgc_fsel_xspi_clock_div_t fselxspi0 : 3; ///< Divider value for XSPI_CLK0 + uint32_t : 3; + cgc_divsel_xspi_clock_div_t divselxspi0 : 1; ///< Divider base value for XSPI_CLK0 + uint32_t : 1; + cgc_fsel_xspi_clock_div_t fselxspi1 : 3; ///< Divider value for XSPI_CLK1 + uint32_t : 3; + cgc_divsel_xspi_clock_div_t divselxspi1 : 1; ///< Divider base value for XSPI_CLK1 + uint32_t : 1; + cgc_clock_out_clock_div_t ckio_div : 3; ///< Divider value for CKIO + uint32_t : 1; + cgc_canfd_clock_div_t fselcanfd_div : 1; ///< Divider value for CANFD clock + cgc_phy_clock_t phy_sel : 1; ///< Ethernet PHY reference clock output + uint32_t : 2; + cgc_spi_async_clock_t spi0_async_sel : 1; ///< SPI0 asynchronous serial clock + cgc_spi_async_clock_t spi1_async_sel : 1; ///< SPI1 asynchronous serial clock + cgc_spi_async_clock_t spi2_async_sel : 1; ///< SPI2 asynchronous serial clock + cgc_sci_async_clock_t sci0_async_sel : 1; ///< SCI0 asynchronous serial clock + cgc_sci_async_clock_t sci1_async_sel : 1; ///< SCI1 asynchronous serial clock + cgc_sci_async_clock_t sci2_async_sel : 1; ///< SCI2 asynchronous serial clock + cgc_sci_async_clock_t sci3_async_sel : 1; ///< SCI3 asynchronous serial clock + cgc_sci_async_clock_t sci4_async_sel : 1; ///< SCI4 asynchronous serial clock + } sckcr_b; + }; + + union + { + uint32_t sckcr2_w; ///< System Clock Control Register 2 + + struct + { + cgc_cpu_clock_div_t fsel0cr52 : 1; ///< Divider value for Cortex-R52 CPU0 + uint32_t : 4; + cgc_baseclock_div_t div_sub_sel : 1; ///< Divider value for base clock + uint32_t : 18; + cgc_spi_async_clock_t spi3_async_sel : 1; ///< SPI3 asynchronous serial clock + cgc_sci_async_clock_t sci5_async_sel : 1; ///< SCI5 asynchronous serial clock + uint32_t : 6; + } sckcr2_b; + }; +} cgc_divider_cfg_t; + +/** Clock options */ +typedef enum e_cgc_clock_change +{ + CGC_CLOCK_CHANGE_START = 0, ///< Start the clock + CGC_CLOCK_CHANGE_STOP = 1, ///< Stop the clock + CGC_CLOCK_CHANGE_NONE = 2, ///< No change to the clock +} cgc_clock_change_t; + +/** Clock configuration */ +typedef struct st_cgc_clocks_cfg +{ + cgc_divider_cfg_t divider_cfg; ///< Clock dividers structure + cgc_clock_change_t loco_state; ///< State of LOCO + cgc_clock_change_t pll1_state; ///< State of PLL1 +} cgc_clocks_cfg_t; + +/*============================================== + * ELC API Overrides + *==============================================*/ + +/** Possible peripherals to be linked to event signals (not all available on all MPUs) */ +typedef enum e_elc_peripheral +{ + ELC_PERIPHERAL_MTU0 = (0), + ELC_PERIPHERAL_MTU3 = (1), + ELC_PERIPHERAL_MTU4 = (2), + ELC_PERIPHERAL_LLPPGPT_A = (3), + ELC_PERIPHERAL_LLPPGPT_B = (4), + ELC_PERIPHERAL_LLPPGPT_C = (5), + ELC_PERIPHERAL_LLPPGPT_D = (6), + ELC_PERIPHERAL_LLPPGPT_E = (7), + ELC_PERIPHERAL_LLPPGPT_F = (8), + ELC_PERIPHERAL_LLPPGPT_G = (9), + ELC_PERIPHERAL_LLPPGPT_H = (10), + ELC_PERIPHERAL_NONSAFTYGPT_A = (11), + ELC_PERIPHERAL_NONSAFTYGPT_B = (12), + ELC_PERIPHERAL_NONSAFTYGPT_C = (13), + ELC_PERIPHERAL_NONSAFTYGPT_D = (14), + ELC_PERIPHERAL_NONSAFTYGPT_E = (15), + ELC_PERIPHERAL_NONSAFTYGPT_F = (16), + ELC_PERIPHERAL_NONSAFTYGPT_G = (17), + ELC_PERIPHERAL_NONSAFTYGPT_H = (18), + ELC_PERIPHERAL_ADC0_A = (19), + ELC_PERIPHERAL_ADC0_B = (20), + ELC_PERIPHERAL_ADC1_A = (21), + ELC_PERIPHERAL_ADC1_B = (22), + ELC_PERIPHERAL_DSMIF0_CAP0 = (23), + ELC_PERIPHERAL_DSMIF0_CAP1 = (24), + ELC_PERIPHERAL_DSMIF0_CAP2 = (25), + ELC_PERIPHERAL_DSMIF0_CAP3 = (26), + ELC_PERIPHERAL_DSMIF0_CAP4 = (27), + ELC_PERIPHERAL_DSMIF0_CAP5 = (28), + ELC_PERIPHERAL_DSMIF0_CDCNT0 = (29), + ELC_PERIPHERAL_DSMIF0_CDCNT1 = (30), + ELC_PERIPHERAL_DSMIF0_CDCNT2 = (31), + ELC_PERIPHERAL_DSMIF1_CAP0 = (32), + ELC_PERIPHERAL_DSMIF1_CAP1 = (33), + ELC_PERIPHERAL_DSMIF1_CAP2 = (34), + ELC_PERIPHERAL_DSMIF1_CAP3 = (35), + ELC_PERIPHERAL_DSMIF1_CAP4 = (36), + ELC_PERIPHERAL_DSMIF1_CAP5 = (37), + ELC_PERIPHERAL_DSMIF1_CDCNT0 = (38), + ELC_PERIPHERAL_DSMIF1_CDCNT1 = (39), + ELC_PERIPHERAL_DSMIF1_CDCNT2 = (40), + ELC_PERIPHERAL_ESC0 = (43), + ELC_PERIPHERAL_ESC1 = (44), + ELC_PERIPHERAL_GMA0 = (45), + ELC_PERIPHERAL_GMA1 = (46), + ELC_PERIPHERAL_OUTPORTGR1 = (47), + ELC_PERIPHERAL_OUTPORTGR2 = (48), + ELC_PERIPHERAL_INPORTGR1 = (49), + ELC_PERIPHERAL_INPORTGR2 = (50), + ELC_PERIPHERAL_SINGLEPORT0 = (51), + ELC_PERIPHERAL_SINGLEPORT1 = (52), + ELC_PERIPHERAL_SINGLEPORT2 = (53), + ELC_PERIPHERAL_SINGLEPORT3 = (54), +} elc_peripheral_t; + +/*============================================== + * ERROR API Overrides + *==============================================*/ + +/** Error event source. */ +typedef enum e_error_event +{ + ERROR_EVENT_CPU0, ///< Error event from CPU0 + ERROR_EVENT_PERIPHERAL_0, ///< Error event from Peripheral 0 + ERROR_EVENT_PERIPHERAL_1, ///< Error event from Peripheral 1 +} error_event_t; + +/*============================================== + * ETHER API Overrides + *==============================================*/ + +/** Event code of callback function */ +typedef enum e_ether_event +{ + ETHER_EVENT_WAKEON_LAN, ///< Magic packet detection event + ETHER_EVENT_LINK_ON, ///< Link up detection event + ETHER_EVENT_LINK_OFF, ///< Link down detection event + ETHER_EVENT_SBD_INTERRUPT, ///< SBD Interrupt event + ETHER_EVENT_PMT_INTERRUPT ///< PMT Interrupt event +} ether_event_t; + +/** Ether Callback function parameter data */ +typedef struct st_ether_callback_args +{ + uint32_t channel; ///< Device channel number + ether_event_t event; ///< Event code + + uint32_t status_ether; ///< Interrupt status of SDB or PMT + uint32_t status_link; ///< Link status + + void const * p_context; ///< Placeholder for user data. +} ether_callback_args_t; + +/*============================================== + * ETHER PHY API Overrides + *==============================================*/ + +/** Phy LSI */ +typedef enum e_ether_phy_lsi_type +{ + ETHER_PHY_LSI_TYPE_DEFAULT = 0, ///< Select default configuration. This type dose not change Phy LSI default setting by strapping option. + ETHER_PHY_LSI_TYPE_VSC8541 = 1, ///< Select configuration forVSC8541 + ETHER_PHY_LSI_TYPE_KSZ9131 = 2, ///< Select configuration forKSZ9131 + ETHER_PHY_LSI_TYPE_KSZ9031 = 3, ///< Select configuration forKSZ9031 + ETHER_PHY_LSI_TYPE_KSZ8081 = 4, ///< Select configuration forKSZ8081 + ETHER_PHY_LSI_TYPE_KSZ8041 = 5, ///< Select configuration forKSZ8041 + ETHER_PHY_LSI_TYPE_CUSTOM = 0xFFU, ///< Select configuration for User custom. +} ether_phy_lsi_type_t; + +/*============================================== + * ETHER SWITCH API Overrides + *==============================================*/ + +/** Ether Switch Event code of callback function */ +typedef enum e_ether_switch_event +{ + ETHER_SWITCH_EVENT_LINK_CHANGE ///< Change Link status +} ether_switch_event_t; + +/** Ether Switch Callback function parameter data */ +typedef struct st_ether_switch_callback_args +{ + uint32_t channel; ///< Device channel number + ether_switch_event_t event; ///< Event code + + uint32_t status_link; ///< Link status bit0:port0. bit1:port1. bit2:port2, bit3:port3 + + void const * p_context; ///< Placeholder for user data. +} ether_switch_callback_args_t; + +/*============================================== + * IOPORT API Overrides + *==============================================*/ + +/** Superset of all peripheral functions. */ +typedef enum e_ioport_pin_pfc +{ + IOPORT_PIN_P000_PFC_00_ETH2_RXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_0 / ETHER_ETHn / ETH2_RXD3 + IOPORT_PIN_P000_PFC_02_D15 = (0x02U << IOPORT_PFC_OFFSET), ///< P00_0 / BSC / D15 + IOPORT_PIN_P000_PFC_03_SCK2 = (0x03U << IOPORT_PFC_OFFSET), ///< P00_0 / SCIn / SCK2 + IOPORT_PIN_P000_PFC_04_DE2 = (0x04U << IOPORT_PFC_OFFSET), ///< P00_0 / SCIn / DE2 + IOPORT_PIN_P000_PFC_05_HD15 = (0x05U << IOPORT_PFC_OFFSET), ///< P00_0 / PHOSTIF / HD15 + IOPORT_PIN_P001_PFC_00_IRQ0 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_1 / IRQ / IRQ0 + IOPORT_PIN_P001_PFC_01_ETH2_RXDV = (0x01U << IOPORT_PFC_OFFSET), ///< P00_1 / ETHER_ETHn / ETH2_RXDV + IOPORT_PIN_P001_PFC_03_A13 = (0x03U << IOPORT_PFC_OFFSET), ///< P00_1 / BSC / A13 + IOPORT_PIN_P001_PFC_04_MTIC5U = (0x04U << IOPORT_PFC_OFFSET), ///< P00_1 / MTU3n / MTIC5U + IOPORT_PIN_P001_PFC_05_RXD2_SCL2_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P00_1 / SCIn / RXD2_SCL2_MISO2 + IOPORT_PIN_P002_PFC_00_ETH2_TXEN = (0x00U << IOPORT_PFC_OFFSET), ///< P00_2 / ETHER_ETHn / ETH2_TXEN + IOPORT_PIN_P002_PFC_02_RD = (0x02U << IOPORT_PFC_OFFSET), ///< P00_2 / BSC / RD + IOPORT_PIN_P002_PFC_03_MTIC5V = (0x03U << IOPORT_PFC_OFFSET), ///< P00_2 / MTU3n / MTIC5V + IOPORT_PIN_P002_PFC_04_TXD2_SDA2_MOSI2 = (0x04U << IOPORT_PFC_OFFSET), ///< P00_2 / SCIn / TXD2_SDA2_MOSI2 + IOPORT_PIN_P002_PFC_05_USB_OVRCUR = (0x05U << IOPORT_PFC_OFFSET), ///< P00_2 / USB_HS / USB_OVRCUR + IOPORT_PIN_P003_PFC_00_IRQ1 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_3 / IRQ / IRQ1 + IOPORT_PIN_P003_PFC_01_ETH2_REFCLK = (0x01U << IOPORT_PFC_OFFSET), ///< P00_3 / ETHER_ETHn / ETH2_REFCLK + IOPORT_PIN_P003_PFC_02_RMII2_REFCLK = (0x02U << IOPORT_PFC_OFFSET), ///< P00_3 / ETHER_ETHn / RMII2_REFCLK + IOPORT_PIN_P003_PFC_04_RD_WR = (0x04U << IOPORT_PFC_OFFSET), ///< P00_3 / BSC / RD_WR + IOPORT_PIN_P003_PFC_05_MTIC5W = (0x05U << IOPORT_PFC_OFFSET), ///< P00_3 / MTU3n / MTIC5W + IOPORT_PIN_P003_PFC_06_SS2_CTS2_RTS2 = (0x06U << IOPORT_PFC_OFFSET), ///< P00_3 / SCIn / SS2_CTS2_RTS2 + IOPORT_PIN_P004_PFC_00_IRQ13 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_4 / IRQ / IRQ13 + IOPORT_PIN_P004_PFC_01_ETH2_RXER = (0x01U << IOPORT_PFC_OFFSET), ///< P00_4 / ETHER_ETHn / ETH2_RXER + IOPORT_PIN_P004_PFC_03_WAIT = (0x03U << IOPORT_PFC_OFFSET), ///< P00_4 / BSC / WAIT + IOPORT_PIN_P004_PFC_04_MTIOC3A = (0x04U << IOPORT_PFC_OFFSET), ///< P00_4 / MTU3n / MTIOC3A + IOPORT_PIN_P004_PFC_05_GTIOC0A = (0x05U << IOPORT_PFC_OFFSET), ///< P00_4 / GPTn / GTIOC0A + IOPORT_PIN_P004_PFC_06_MCLK0 = (0x06U << IOPORT_PFC_OFFSET), ///< P00_4 / DSMIFn / MCLK0 + IOPORT_PIN_P004_PFC_07_HWAIT = (0x07U << IOPORT_PFC_OFFSET), ///< P00_4 / PHOSTIF / HWAIT + IOPORT_PIN_P005_PFC_00_ETHSW_PHYLINK2 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ETHSW / ETHSW_PHYLINK2 + IOPORT_PIN_P005_PFC_02_CS0 = (0x02U << IOPORT_PFC_OFFSET), ///< P00_5 / BSC / CS0 + IOPORT_PIN_P005_PFC_03_ESC_PHYLINK2 = (0x03U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ESC / ESC_PHYLINK2 + IOPORT_PIN_P005_PFC_04_MTIOC3C = (0x04U << IOPORT_PFC_OFFSET), ///< P00_5 / MTU3n / MTIOC3C + IOPORT_PIN_P005_PFC_05_GTIOC0B = (0x05U << IOPORT_PFC_OFFSET), ///< P00_5 / GPTn / GTIOC0B + IOPORT_PIN_P005_PFC_06_MDAT0 = (0x06U << IOPORT_PFC_OFFSET), ///< P00_5 / DSMIFn / MDAT0 + IOPORT_PIN_P005_PFC_07_ETHSW_PHYLINK0 = (0x07U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ETHSW / ETHSW_PHYLINK0 + IOPORT_PIN_P005_PFC_08_ESC_PHYLINK0 = (0x08U << IOPORT_PFC_OFFSET), ///< P00_5 / ETHER_ESC / ESC_PHYLINK0 + IOPORT_PIN_P006_PFC_00_ETH2_TXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P00_6 / ETHER_ETHn / ETH2_TXCLK + IOPORT_PIN_P006_PFC_01_CS5 = (0x01U << IOPORT_PFC_OFFSET), ///< P00_6 / BSC / CS5 + IOPORT_PIN_P006_PFC_02_MTIOC3B = (0x02U << IOPORT_PFC_OFFSET), ///< P00_6 / MTU3n / MTIOC3B + IOPORT_PIN_P006_PFC_03_GTIOC1A = (0x03U << IOPORT_PFC_OFFSET), ///< P00_6 / GPTn / GTIOC1A + IOPORT_PIN_P007_PFC_00_IRQ13 = (0x00U << IOPORT_PFC_OFFSET), ///< P00_7 / IRQ / IRQ13 + IOPORT_PIN_P007_PFC_01_RAS = (0x01U << IOPORT_PFC_OFFSET), ///< P00_7 / BSC / RAS + IOPORT_PIN_P007_PFC_02_MTIOC4A = (0x02U << IOPORT_PFC_OFFSET), ///< P00_7 / MTU3n / MTIOC4A + IOPORT_PIN_P007_PFC_03_GTIOC2A = (0x03U << IOPORT_PFC_OFFSET), ///< P00_7 / GPTn / GTIOC2A + IOPORT_PIN_P010_PFC_00_GMAC_MDIO = (0x00U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_GMAC / GMAC_MDIO + IOPORT_PIN_P010_PFC_01_ETHSW_MDIO = (0x01U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_ETHSW / ETHSW_MDIO + IOPORT_PIN_P010_PFC_02_CAS = (0x02U << IOPORT_PFC_OFFSET), ///< P01_0 / BSC / CAS + IOPORT_PIN_P010_PFC_03_ESC_MDIO = (0x03U << IOPORT_PFC_OFFSET), ///< P01_0 / ETHER_ESC / ESC_MDIO + IOPORT_PIN_P010_PFC_04_MTIOC4C = (0x04U << IOPORT_PFC_OFFSET), ///< P01_0 / MTU3n / MTIOC4C + IOPORT_PIN_P010_PFC_05_GTIOC3A = (0x05U << IOPORT_PFC_OFFSET), ///< P01_0 / GPTn / GTIOC3A + IOPORT_PIN_P010_PFC_06_CTS2 = (0x06U << IOPORT_PFC_OFFSET), ///< P01_0 / SCIn / CTS2 + IOPORT_PIN_P010_PFC_07_MCLK1 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_0 / DSMIFn / MCLK1 + IOPORT_PIN_P011_PFC_00_GMAC_MDC = (0x00U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_GMAC / GMAC_MDC + IOPORT_PIN_P011_PFC_01_ETHSW_MDC = (0x01U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_ETHSW / ETHSW_MDC + IOPORT_PIN_P011_PFC_02_CKE = (0x02U << IOPORT_PFC_OFFSET), ///< P01_1 / BSC / CKE + IOPORT_PIN_P011_PFC_03_ESC_MDC = (0x03U << IOPORT_PFC_OFFSET), ///< P01_1 / ETHER_ESC / ESC_MDC + IOPORT_PIN_P011_PFC_04_MTIOC3D = (0x04U << IOPORT_PFC_OFFSET), ///< P01_1 / MTU3n / MTIOC3D + IOPORT_PIN_P011_PFC_05_GTIOC1B = (0x05U << IOPORT_PFC_OFFSET), ///< P01_1 / GPTn / GTIOC1B + IOPORT_PIN_P011_PFC_06_DE2 = (0x06U << IOPORT_PFC_OFFSET), ///< P01_1 / SCIn / DE2 + IOPORT_PIN_P011_PFC_07_MDAT1 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_1 / DSMIFn / MDAT1 + IOPORT_PIN_P012_PFC_00_IRQ2 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_2 / IRQ / IRQ2 + IOPORT_PIN_P012_PFC_01_ETH2_TXD3 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_2 / ETHER_ETHn / ETH2_TXD3 + IOPORT_PIN_P012_PFC_02_CS2 = (0x02U << IOPORT_PFC_OFFSET), ///< P01_2 / BSC / CS2 + IOPORT_PIN_P012_PFC_03_MTIOC4B = (0x03U << IOPORT_PFC_OFFSET), ///< P01_2 / MTU3n / MTIOC4B + IOPORT_PIN_P012_PFC_04_GTIOC2B = (0x04U << IOPORT_PFC_OFFSET), ///< P01_2 / GPTn / GTIOC2B + IOPORT_PIN_P013_PFC_00_ETH2_TXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_3 / ETHER_ETHn / ETH2_TXD2 + IOPORT_PIN_P013_PFC_01_AH = (0x01U << IOPORT_PFC_OFFSET), ///< P01_3 / BSC / AH + IOPORT_PIN_P013_PFC_02_MTIOC4D = (0x02U << IOPORT_PFC_OFFSET), ///< P01_3 / MTU3n / MTIOC4D + IOPORT_PIN_P013_PFC_03_GTIOC3B = (0x03U << IOPORT_PFC_OFFSET), ///< P01_3 / GPTn / GTIOC3B + IOPORT_PIN_P014_PFC_00_IRQ3 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_4 / IRQ / IRQ3 + IOPORT_PIN_P014_PFC_01_ETH2_TXD1 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_4 / ETHER_ETHn / ETH2_TXD1 + IOPORT_PIN_P014_PFC_02_WE1_DQMLU = (0x02U << IOPORT_PFC_OFFSET), ///< P01_4 / BSC / WE1_DQMLU + IOPORT_PIN_P014_PFC_03_POE0 = (0x03U << IOPORT_PFC_OFFSET), ///< P01_4 / MTU_POE3 / POE0 + IOPORT_PIN_P015_PFC_00_ETH2_TXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_5 / ETHER_ETHn / ETH2_TXD0 + IOPORT_PIN_P015_PFC_01_WE0_DQMLL = (0x01U << IOPORT_PFC_OFFSET), ///< P01_5 / BSC / WE0_DQMLL + IOPORT_PIN_P016_PFC_00_GMAC_PTPTRG1 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_GMAC / GMAC_PTPTRG1 + IOPORT_PIN_P016_PFC_01_TRACEDATA0 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_6 / TRACE / TRACEDATA0 + IOPORT_PIN_P016_PFC_02_A20 = (0x02U << IOPORT_PFC_OFFSET), ///< P01_6 / BSC / A20 + IOPORT_PIN_P016_PFC_03_ESC_LATCH1 = (0x03U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_ESC / ESC_LATCH1 + IOPORT_PIN_P016_PFC_04_ESC_LATCH0 = (0x04U << IOPORT_PFC_OFFSET), ///< P01_6 / ETHER_ESC / ESC_LATCH0 + IOPORT_PIN_P016_PFC_05_MTIOC1A = (0x05U << IOPORT_PFC_OFFSET), ///< P01_6 / MTU3n / MTIOC1A + IOPORT_PIN_P016_PFC_06_GTIOC9A = (0x06U << IOPORT_PFC_OFFSET), ///< P01_6 / GPTn / GTIOC9A + IOPORT_PIN_P016_PFC_07_CTS1 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_6 / SCIn / CTS1 + IOPORT_PIN_P016_PFC_08_CANTXDP1 = (0x08U << IOPORT_PFC_OFFSET), ///< P01_6 / CANFDn / CANTXDP1 + IOPORT_PIN_P016_PFC_0A_HA20 = (0x0AU << IOPORT_PFC_OFFSET), ///< P01_6 / PHOSTIF / HA20 + IOPORT_PIN_P017_PFC_00_ETHSW_LPI1 = (0x00U << IOPORT_PFC_OFFSET), ///< P01_7 / ETHER_ETHSW / ETHSW_LPI1 + IOPORT_PIN_P017_PFC_01_TRACEDATA1 = (0x01U << IOPORT_PFC_OFFSET), ///< P01_7 / TRACE / TRACEDATA1 + IOPORT_PIN_P017_PFC_02_A19 = (0x02U << IOPORT_PFC_OFFSET), ///< P01_7 / BSC / A19 + IOPORT_PIN_P017_PFC_03_MTIOC1B = (0x03U << IOPORT_PFC_OFFSET), ///< P01_7 / MTU3n / MTIOC1B + IOPORT_PIN_P017_PFC_04_GTIOC9B = (0x04U << IOPORT_PFC_OFFSET), ///< P01_7 / GPTn / GTIOC9B + IOPORT_PIN_P017_PFC_05_ADTRG0 = (0x05U << IOPORT_PFC_OFFSET), ///< P01_7 / ADCn / ADTRG0 + IOPORT_PIN_P017_PFC_06_SCK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P01_7 / SCIn / SCK1 + IOPORT_PIN_P017_PFC_07_SPI_RSPCK3 = (0x07U << IOPORT_PFC_OFFSET), ///< P01_7 / SPIn / SPI_RSPCK3 + IOPORT_PIN_P017_PFC_08_CANRX0 = (0x08U << IOPORT_PFC_OFFSET), ///< P01_7 / CANFDn / CANRX0 + IOPORT_PIN_P017_PFC_0A_HA19 = (0x0AU << IOPORT_PFC_OFFSET), ///< P01_7 / PHOSTIF / HA19 + IOPORT_PIN_P020_PFC_00_IRQ4 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_0 / IRQ / IRQ4 + IOPORT_PIN_P020_PFC_01_ETHSW_LPI2 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_0 / ETHER_ETHSW / ETHSW_LPI2 + IOPORT_PIN_P020_PFC_02_TRACEDATA2 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_0 / TRACE / TRACEDATA2 + IOPORT_PIN_P020_PFC_03_A18 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_0 / BSC / A18 + IOPORT_PIN_P020_PFC_04_GTADSML0 = (0x04U << IOPORT_PFC_OFFSET), ///< P02_0 / GPT / GTADSML0 + IOPORT_PIN_P020_PFC_05_RXD1_SCL1_MISO1 = (0x05U << IOPORT_PFC_OFFSET), ///< P02_0 / SCIn / RXD1_SCL1_MISO1 + IOPORT_PIN_P020_PFC_06_SPI_MISO3 = (0x06U << IOPORT_PFC_OFFSET), ///< P02_0 / SPIn / SPI_MISO3 + IOPORT_PIN_P020_PFC_07_CANTX1 = (0x07U << IOPORT_PFC_OFFSET), ///< P02_0 / CANFDn / CANTX1 + IOPORT_PIN_P020_PFC_08_USB_OTGID = (0x08U << IOPORT_PFC_OFFSET), ///< P02_0 / USB_HS / USB_OTGID + IOPORT_PIN_P020_PFC_0A_HA18 = (0x0AU << IOPORT_PFC_OFFSET), ///< P02_0 / PHOSTIF / HA18 + IOPORT_PIN_P021_PFC_00_ETHSW_PTPOUT1 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ETHSW / ETHSW_PTPOUT1 + IOPORT_PIN_P021_PFC_01_A17 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_1 / BSC / A17 + IOPORT_PIN_P021_PFC_02_ESC_SYNC1 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P021_PFC_03_ESC_SYNC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_1 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P021_PFC_04_DE1 = (0x04U << IOPORT_PFC_OFFSET), ///< P02_1 / SCIn / DE1 + IOPORT_PIN_P021_PFC_05_HA17 = (0x05U << IOPORT_PFC_OFFSET), ///< P02_1 / PHOSTIF / HA17 + IOPORT_PIN_P022_PFC_00_IRQ14 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_2 / IRQ / IRQ14 + IOPORT_PIN_P022_PFC_01_ETHSW_TDMAOUT0 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_2 / ETHER_ETHSW / ETHSW_TDMAOUT0 + IOPORT_PIN_P022_PFC_02_A16 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_2 / BSC / A16 + IOPORT_PIN_P022_PFC_03_MTIOC2A = (0x03U << IOPORT_PFC_OFFSET), ///< P02_2 / MTU3n / MTIOC2A + IOPORT_PIN_P022_PFC_04_GTIOC10A = (0x04U << IOPORT_PFC_OFFSET), ///< P02_2 / GPTn / GTIOC10A + IOPORT_PIN_P022_PFC_05_POE10 = (0x05U << IOPORT_PFC_OFFSET), ///< P02_2 / MTU_POE3 / POE10 + IOPORT_PIN_P022_PFC_06_TXD1_SDA1_MOSI1 = (0x06U << IOPORT_PFC_OFFSET), ///< P02_2 / SCIn / TXD1_SDA1_MOSI1 + IOPORT_PIN_P022_PFC_07_SPI_MOSI3 = (0x07U << IOPORT_PFC_OFFSET), ///< P02_2 / SPIn / SPI_MOSI3 + IOPORT_PIN_P022_PFC_08_CANTX0 = (0x08U << IOPORT_PFC_OFFSET), ///< P02_2 / CANFDn / CANTX0 + IOPORT_PIN_P022_PFC_0A_RTCAT1HZ = (0x0AU << IOPORT_PFC_OFFSET), ///< P02_2 / RTC / RTCAT1HZ + IOPORT_PIN_P022_PFC_0B_HA16 = (0x0BU << IOPORT_PFC_OFFSET), ///< P02_2 / PHOSTIF / HA16 + IOPORT_PIN_P023_PFC_00_IRQ15 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_3 / IRQ / IRQ15 + IOPORT_PIN_P023_PFC_01_ETHSW_TDMAOUT1 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_3 / ETHER_ETHSW / ETHSW_TDMAOUT1 + IOPORT_PIN_P023_PFC_02_A15 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_3 / BSC / A15 + IOPORT_PIN_P023_PFC_03_AH = (0x03U << IOPORT_PFC_OFFSET), ///< P02_3 / BSC / AH + IOPORT_PIN_P023_PFC_04_MTIOC2B = (0x04U << IOPORT_PFC_OFFSET), ///< P02_3 / MTU3n / MTIOC2B + IOPORT_PIN_P023_PFC_05_GTIOC10B = (0x05U << IOPORT_PFC_OFFSET), ///< P02_3 / GPTn / GTIOC10B + IOPORT_PIN_P023_PFC_06_POE11 = (0x06U << IOPORT_PFC_OFFSET), ///< P02_3 / MTU_POE3 / POE11 + IOPORT_PIN_P023_PFC_07_SS1_CTS1_RTS1 = (0x07U << IOPORT_PFC_OFFSET), ///< P02_3 / SCIn / SS1_CTS1_RTS1 + IOPORT_PIN_P023_PFC_08_SPI_SSL30 = (0x08U << IOPORT_PFC_OFFSET), ///< P02_3 / SPIn / SPI_SSL30 + IOPORT_PIN_P023_PFC_09_CANRX1 = (0x09U << IOPORT_PFC_OFFSET), ///< P02_3 / CANFDn / CANRX1 + IOPORT_PIN_P023_PFC_0B_HA15 = (0x0BU << IOPORT_PFC_OFFSET), ///< P02_3 / PHOSTIF / HA15 + IOPORT_PIN_P024_PFC_00_TDO = (0x00U << IOPORT_PFC_OFFSET), ///< P02_4 / JTAG/SWD / TDO + IOPORT_PIN_P024_PFC_01_WE0_DQMLL = (0x01U << IOPORT_PFC_OFFSET), ///< P02_4 / BSC / WE0_DQMLL + IOPORT_PIN_P024_PFC_02_DE1 = (0x02U << IOPORT_PFC_OFFSET), ///< P02_4 / SCIn / DE1 + IOPORT_PIN_P024_PFC_03_SPI_SSL33 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_4 / SPIn / SPI_SSL33 + IOPORT_PIN_P025_PFC_00_ETHSW_TDMAOUT3 = (0x00U << IOPORT_PFC_OFFSET), ///< P02_5 / ETHER_ETHSW / ETHSW_TDMAOUT3 + IOPORT_PIN_P025_PFC_01_TDI = (0x01U << IOPORT_PFC_OFFSET), ///< P02_5 / JTAG/SWD / TDI + IOPORT_PIN_P025_PFC_02_WE1_DQMLU = (0x02U << IOPORT_PFC_OFFSET), ///< P02_5 / BSC / WE1_DQMLU + IOPORT_PIN_P025_PFC_03_SCK5 = (0x03U << IOPORT_PFC_OFFSET), ///< P02_5 / SCIn / SCK5 + IOPORT_PIN_P025_PFC_04_SPI_SSL31 = (0x04U << IOPORT_PFC_OFFSET), ///< P02_5 / SPIn / SPI_SSL31 + IOPORT_PIN_P026_PFC_00_TMS_SWDIO = (0x00U << IOPORT_PFC_OFFSET), ///< P02_6 / JTAG/SWD / TMS_SWDIO + IOPORT_PIN_P026_PFC_01_RXD5_SCL5_MISO5 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_6 / SCIn / RXD5_SCL5_MISO5 + IOPORT_PIN_P027_PFC_00_TCK_SWCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P02_7 / JTAG/SWD / TCK_SWCLK + IOPORT_PIN_P027_PFC_01_TXD5_SDA5_MOSI5 = (0x01U << IOPORT_PFC_OFFSET), ///< P02_7 / SCIn / TXD5_SDA5_MOSI5 + IOPORT_PIN_P030_PFC_00_IRQ14 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_0 / IRQ / IRQ14 + IOPORT_PIN_P030_PFC_01_TRACEDATA3 = (0x01U << IOPORT_PFC_OFFSET), ///< P03_0 / TRACE / TRACEDATA3 + IOPORT_PIN_P030_PFC_02_A14 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_0 / BSC / A14 + IOPORT_PIN_P030_PFC_03_CS5 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_0 / BSC / CS5 + IOPORT_PIN_P030_PFC_04_GTADSML1 = (0x04U << IOPORT_PFC_OFFSET), ///< P03_0 / GPT / GTADSML1 + IOPORT_PIN_P030_PFC_05_SCK2 = (0x05U << IOPORT_PFC_OFFSET), ///< P03_0 / SCIn / SCK2 + IOPORT_PIN_P030_PFC_06_SPI_SSL32 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_0 / SPIn / SPI_SSL32 + IOPORT_PIN_P030_PFC_07_CANTXDP1 = (0x07U << IOPORT_PFC_OFFSET), ///< P03_0 / CANFDn / CANTXDP1 + IOPORT_PIN_P030_PFC_09_HA14 = (0x09U << IOPORT_PFC_OFFSET), ///< P03_0 / PHOSTIF / HA14 + IOPORT_PIN_P035_PFC_00_IRQ5 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_5 / IRQ / IRQ5 + IOPORT_PIN_P035_PFC_01_ETH2_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P03_5 / ETHER_ETHn / ETH2_CRS + IOPORT_PIN_P035_PFC_02_A12 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_5 / BSC / A12 + IOPORT_PIN_P035_PFC_03_MTIOC3A = (0x03U << IOPORT_PFC_OFFSET), ///< P03_5 / MTU3n / MTIOC3A + IOPORT_PIN_P035_PFC_04_GTIOC4A = (0x04U << IOPORT_PFC_OFFSET), ///< P03_5 / GPTn / GTIOC4A + IOPORT_PIN_P035_PFC_05_RXD2_SCL2_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P03_5 / SCIn / RXD2_SCL2_MISO2 + IOPORT_PIN_P035_PFC_06_MCLK2 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_5 / DSMIFn / MCLK2 + IOPORT_PIN_P035_PFC_07_HA12 = (0x07U << IOPORT_PFC_OFFSET), ///< P03_5 / PHOSTIF / HA12 + IOPORT_PIN_P036_PFC_00_IRQ8 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_6 / IRQ / IRQ8 + IOPORT_PIN_P036_PFC_01_ETH2_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P03_6 / ETHER_ETHn / ETH2_COL + IOPORT_PIN_P036_PFC_02_TRACEDATA4 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_6 / TRACE / TRACEDATA4 + IOPORT_PIN_P036_PFC_03_A11 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_6 / BSC / A11 + IOPORT_PIN_P036_PFC_04_MTIOC3B = (0x04U << IOPORT_PFC_OFFSET), ///< P03_6 / MTU3n / MTIOC3B + IOPORT_PIN_P036_PFC_05_GTIOC4B = (0x05U << IOPORT_PFC_OFFSET), ///< P03_6 / GPTn / GTIOC4B + IOPORT_PIN_P036_PFC_06_TXD2_SDA2_MOSI2 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_6 / SCIn / TXD2_SDA2_MOSI2 + IOPORT_PIN_P036_PFC_07_SPI_SSL13 = (0x07U << IOPORT_PFC_OFFSET), ///< P03_6 / SPIn / SPI_SSL13 + IOPORT_PIN_P036_PFC_08_MDAT2 = (0x08U << IOPORT_PFC_OFFSET), ///< P03_6 / DSMIFn / MDAT2 + IOPORT_PIN_P036_PFC_09_HA11 = (0x09U << IOPORT_PFC_OFFSET), ///< P03_6 / PHOSTIF / HA11 + IOPORT_PIN_P037_PFC_00_IRQ9 = (0x00U << IOPORT_PFC_OFFSET), ///< P03_7 / IRQ / IRQ9 + IOPORT_PIN_P037_PFC_01_ETH2_TXER = (0x01U << IOPORT_PFC_OFFSET), ///< P03_7 / ETHER_ETHn / ETH2_TXER + IOPORT_PIN_P037_PFC_02_TRACEDATA5 = (0x02U << IOPORT_PFC_OFFSET), ///< P03_7 / TRACE / TRACEDATA5 + IOPORT_PIN_P037_PFC_03_A10 = (0x03U << IOPORT_PFC_OFFSET), ///< P03_7 / BSC / A10 + IOPORT_PIN_P037_PFC_04_MTIOC3C = (0x04U << IOPORT_PFC_OFFSET), ///< P03_7 / MTU3n / MTIOC3C + IOPORT_PIN_P037_PFC_05_GTIOC5A = (0x05U << IOPORT_PFC_OFFSET), ///< P03_7 / GPTn / GTIOC5A + IOPORT_PIN_P037_PFC_06_SCK3 = (0x06U << IOPORT_PFC_OFFSET), ///< P03_7 / SCIn / SCK3 + IOPORT_PIN_P037_PFC_07_HA10 = (0x07U << IOPORT_PFC_OFFSET), ///< P03_7 / PHOSTIF / HA10 + IOPORT_PIN_P040_PFC_00_TRACEDATA6 = (0x00U << IOPORT_PFC_OFFSET), ///< P04_0 / TRACE / TRACEDATA6 + IOPORT_PIN_P040_PFC_01_A9 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_0 / BSC / A9 + IOPORT_PIN_P040_PFC_02_MTIOC3D = (0x02U << IOPORT_PFC_OFFSET), ///< P04_0 / MTU3n / MTIOC3D + IOPORT_PIN_P040_PFC_03_GTIOC5B = (0x03U << IOPORT_PFC_OFFSET), ///< P04_0 / GPTn / GTIOC5B + IOPORT_PIN_P040_PFC_04_RXD3_SCL3_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_0 / SCIn / RXD3_SCL3_MISO3 + IOPORT_PIN_P040_PFC_05_HA9 = (0x05U << IOPORT_PFC_OFFSET), ///< P04_0 / PHOSTIF / HA9 + IOPORT_PIN_P041_PFC_00_CKIO = (0x00U << IOPORT_PFC_OFFSET), ///< P04_1 / BSC / CKIO + IOPORT_PIN_P041_PFC_01_TXD3_SDA3_MOSI3 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_1 / SCIn / TXD3_SDA3_MOSI3 + IOPORT_PIN_P041_PFC_02_SPI_MOSI0 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_1 / SPIn / SPI_MOSI0 + IOPORT_PIN_P041_PFC_03_IIC_SDA2 = (0x03U << IOPORT_PFC_OFFSET), ///< P04_1 / IICn / IIC_SDA2 + IOPORT_PIN_P041_PFC_04_HCKIO = (0x04U << IOPORT_PFC_OFFSET), ///< P04_1 / PHOSTIF / HCKIO + IOPORT_PIN_P044_PFC_00_IRQ10 = (0x00U << IOPORT_PFC_OFFSET), ///< P04_4 / IRQ / IRQ10 + IOPORT_PIN_P044_PFC_01_TRACEDATA7 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_4 / TRACE / TRACEDATA7 + IOPORT_PIN_P044_PFC_02_A8 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_4 / BSC / A8 + IOPORT_PIN_P044_PFC_03_GTADSMP0 = (0x03U << IOPORT_PFC_OFFSET), ///< P04_4 / GPT / GTADSMP0 + IOPORT_PIN_P044_PFC_04_POE10 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_4 / MTU_POE3 / POE10 + IOPORT_PIN_P044_PFC_05_CTS3 = (0x05U << IOPORT_PFC_OFFSET), ///< P04_4 / SCIn / CTS3 + IOPORT_PIN_P044_PFC_06_SPI_RSPCK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P04_4 / SPIn / SPI_RSPCK1 + IOPORT_PIN_P044_PFC_08_HA8 = (0x08U << IOPORT_PFC_OFFSET), ///< P04_4 / PHOSTIF / HA8 + IOPORT_PIN_P045_PFC_00_A7 = (0x00U << IOPORT_PFC_OFFSET), ///< P04_5 / BSC / A7 + IOPORT_PIN_P045_PFC_01_DE3 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_5 / SCIn / DE3 + IOPORT_PIN_P045_PFC_02_ETHSW_PTPOUT0 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_5 / ETHER_ETHSW / ETHSW_PTPOUT0 + IOPORT_PIN_P045_PFC_03_ESC_SYNC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P04_5 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P045_PFC_04_ESC_SYNC1 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_5 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P045_PFC_05_HA7 = (0x05U << IOPORT_PFC_OFFSET), ///< P04_5 / PHOSTIF / HA7 + IOPORT_PIN_P046_PFC_00_ETH1_TXER = (0x00U << IOPORT_PFC_OFFSET), ///< P04_6 / ETHER_ETHn / ETH1_TXER + IOPORT_PIN_P046_PFC_01_A6 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_6 / BSC / A6 + IOPORT_PIN_P046_PFC_02_DACK = (0x02U << IOPORT_PFC_OFFSET), ///< P04_6 / DMAC / DACK + IOPORT_PIN_P046_PFC_03_RTCAT1HZ = (0x03U << IOPORT_PFC_OFFSET), ///< P04_6 / RTC / RTCAT1HZ + IOPORT_PIN_P046_PFC_04_HA6 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_6 / PHOSTIF / HA6 + IOPORT_PIN_P047_PFC_00_ETH0_TXER = (0x00U << IOPORT_PFC_OFFSET), ///< P04_7 / ETHER_ETHn / ETH0_TXER + IOPORT_PIN_P047_PFC_01_A5 = (0x01U << IOPORT_PFC_OFFSET), ///< P04_7 / BSC / A5 + IOPORT_PIN_P047_PFC_02_SPI_SSL21 = (0x02U << IOPORT_PFC_OFFSET), ///< P04_7 / SPIn / SPI_SSL21 + IOPORT_PIN_P047_PFC_03_ETH2_TXER = (0x03U << IOPORT_PFC_OFFSET), ///< P04_7 / ETHER_ETHn / ETH2_TXER + IOPORT_PIN_P047_PFC_04_HA5 = (0x04U << IOPORT_PFC_OFFSET), ///< P04_7 / PHOSTIF / HA5 + IOPORT_PIN_P050_PFC_00_IRQ12 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_0 / IRQ / IRQ12 + IOPORT_PIN_P050_PFC_01_ETH1_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P05_0 / ETHER_ETHn / ETH1_CRS + IOPORT_PIN_P050_PFC_02_A4 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_0 / BSC / A4 + IOPORT_PIN_P050_PFC_03_MTIOC4A = (0x03U << IOPORT_PFC_OFFSET), ///< P05_0 / MTU3n / MTIOC4A + IOPORT_PIN_P050_PFC_04_GTIOC6A = (0x04U << IOPORT_PFC_OFFSET), ///< P05_0 / GPTn / GTIOC6A + IOPORT_PIN_P050_PFC_05_CMTW0_TOC0 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_0 / CMTWn / CMTW0_TOC0 + IOPORT_PIN_P050_PFC_06_SS5_CTS5_RTS5 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_0 / SCIn / SS5_CTS5_RTS5 + IOPORT_PIN_P050_PFC_07_CANTXDP0 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_0 / CANFDn / CANTXDP0 + IOPORT_PIN_P050_PFC_08_USB_VBUSEN = (0x08U << IOPORT_PFC_OFFSET), ///< P05_0 / USB_HS / USB_VBUSEN + IOPORT_PIN_P050_PFC_09_MCLK3 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_0 / DSMIFn / MCLK3 + IOPORT_PIN_P050_PFC_0B_HA4 = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_0 / PHOSTIF / HA4 + IOPORT_PIN_P051_PFC_00_IRQ13 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_1 / IRQ / IRQ13 + IOPORT_PIN_P051_PFC_01_ETH1_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P05_1 / ETHER_ETHn / ETH1_COL + IOPORT_PIN_P051_PFC_02_A3 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_1 / BSC / A3 + IOPORT_PIN_P051_PFC_03_MTIOC4B = (0x03U << IOPORT_PFC_OFFSET), ///< P05_1 / MTU3n / MTIOC4B + IOPORT_PIN_P051_PFC_04_GTIOC6B = (0x04U << IOPORT_PFC_OFFSET), ///< P05_1 / GPTn / GTIOC6B + IOPORT_PIN_P051_PFC_05_CMTW0_TIC1 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_1 / CMTWn / CMTW0_TIC1 + IOPORT_PIN_P051_PFC_06_CTS5 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_1 / SCIn / CTS5 + IOPORT_PIN_P051_PFC_07_CANRXDP0 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_1 / CANFDn / CANRXDP0 + IOPORT_PIN_P051_PFC_08_USB_EXICEN = (0x08U << IOPORT_PFC_OFFSET), ///< P05_1 / USB_HS / USB_EXICEN + IOPORT_PIN_P051_PFC_09_MDAT3 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_1 / DSMIFn / MDAT3 + IOPORT_PIN_P051_PFC_0B_HA3 = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_1 / PHOSTIF / HA3 + IOPORT_PIN_P052_PFC_00_IRQ14 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_2 / IRQ / IRQ14 + IOPORT_PIN_P052_PFC_01_ETH0_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P05_2 / ETHER_ETHn / ETH0_CRS + IOPORT_PIN_P052_PFC_02_A2 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_2 / BSC / A2 + IOPORT_PIN_P052_PFC_03_MTIOC4C = (0x03U << IOPORT_PFC_OFFSET), ///< P05_2 / MTU3n / MTIOC4C + IOPORT_PIN_P052_PFC_04_GTETRGSA = (0x04U << IOPORT_PFC_OFFSET), ///< P05_2 / GPT_POEG / GTETRGSA + IOPORT_PIN_P052_PFC_05_GTIOC7A = (0x05U << IOPORT_PFC_OFFSET), ///< P05_2 / GPTn / GTIOC7A + IOPORT_PIN_P052_PFC_06_CMTW0_TOC0 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_2 / CMTWn / CMTW0_TOC0 + IOPORT_PIN_P052_PFC_07_DE5 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_2 / SCIn / DE5 + IOPORT_PIN_P052_PFC_08_IIC_SCL1 = (0x08U << IOPORT_PFC_OFFSET), ///< P05_2 / IICn / IIC_SCL1 + IOPORT_PIN_P052_PFC_09_CANRX0 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_2 / CANFDn / CANRX0 + IOPORT_PIN_P052_PFC_0A_DREQ = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_2 / DMAC / DREQ + IOPORT_PIN_P052_PFC_0B_USB_VBUSEN = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_2 / USB_HS / USB_VBUSEN + IOPORT_PIN_P052_PFC_0D_HA2 = (0x0DU << IOPORT_PFC_OFFSET), ///< P05_2 / PHOSTIF / HA2 + IOPORT_PIN_P053_PFC_00_IRQ15 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_3 / IRQ / IRQ15 + IOPORT_PIN_P053_PFC_01_ETH0_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P05_3 / ETHER_ETHn / ETH0_COL + IOPORT_PIN_P053_PFC_02_A1 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_3 / BSC / A1 + IOPORT_PIN_P053_PFC_03_MTIOC4D = (0x03U << IOPORT_PFC_OFFSET), ///< P05_3 / MTU3n / MTIOC4D + IOPORT_PIN_P053_PFC_04_GTETRGSB = (0x04U << IOPORT_PFC_OFFSET), ///< P05_3 / GPT_POEG / GTETRGSB + IOPORT_PIN_P053_PFC_05_GTIOC7B = (0x05U << IOPORT_PFC_OFFSET), ///< P05_3 / GPTn / GTIOC7B + IOPORT_PIN_P053_PFC_06_POE11 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_3 / MTU_POE3 / POE11 + IOPORT_PIN_P053_PFC_07_CMTW0_TIC0 = (0x07U << IOPORT_PFC_OFFSET), ///< P05_3 / CMTWn / CMTW0_TIC0 + IOPORT_PIN_P053_PFC_08_SCK4 = (0x08U << IOPORT_PFC_OFFSET), ///< P05_3 / SCIn / SCK4 + IOPORT_PIN_P053_PFC_09_IIC_SDA1 = (0x09U << IOPORT_PFC_OFFSET), ///< P05_3 / IICn / IIC_SDA1 + IOPORT_PIN_P053_PFC_0A_CANTX0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_3 / CANFDn / CANTX0 + IOPORT_PIN_P053_PFC_0B_USB_EXICEN = (0x0BU << IOPORT_PFC_OFFSET), ///< P05_3 / USB_HS / USB_EXICEN + IOPORT_PIN_P053_PFC_0D_HA1 = (0x0DU << IOPORT_PFC_OFFSET), ///< P05_3 / PHOSTIF / HA1 + IOPORT_PIN_P054_PFC_00_IRQ12 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_4 / IRQ / IRQ12 + IOPORT_PIN_P054_PFC_01_ETHSW_LPI0 = (0x01U << IOPORT_PFC_OFFSET), ///< P05_4 / ETHER_ETHSW / ETHSW_LPI0 + IOPORT_PIN_P054_PFC_02_A0 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_4 / BSC / A0 + IOPORT_PIN_P054_PFC_03_GTIOC14A = (0x03U << IOPORT_PFC_OFFSET), ///< P05_4 / GPTn / GTIOC14A + IOPORT_PIN_P054_PFC_04_RXD4_SCL4_MISO4 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_4 / SCIn / RXD4_SCL4_MISO4 + IOPORT_PIN_P054_PFC_05_SPI_SSL00 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_4 / SPIn / SPI_SSL00 + IOPORT_PIN_P054_PFC_06_CANTXDP0 = (0x06U << IOPORT_PFC_OFFSET), ///< P05_4 / CANFDn / CANTXDP0 + IOPORT_PIN_P054_PFC_07_DACK = (0x07U << IOPORT_PFC_OFFSET), ///< P05_4 / DMAC / DACK + IOPORT_PIN_P054_PFC_08_USB_OVRCUR = (0x08U << IOPORT_PFC_OFFSET), ///< P05_4 / USB_HS / USB_OVRCUR + IOPORT_PIN_P054_PFC_0A_HA0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P05_4 / PHOSTIF / HA0 + IOPORT_PIN_P055_PFC_00_ETHSW_PHYLINK1 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_5 / ETHER_ETHSW / ETHSW_PHYLINK1 + IOPORT_PIN_P055_PFC_02_ESC_PHYLINK1 = (0x02U << IOPORT_PFC_OFFSET), ///< P05_5 / ETHER_ESC / ESC_PHYLINK1 + IOPORT_PIN_P055_PFC_03_GTIOC14B = (0x03U << IOPORT_PFC_OFFSET), ///< P05_5 / GPTn / GTIOC14B + IOPORT_PIN_P055_PFC_04_CMTW0_TOC1 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_5 / CMTWn / CMTW0_TOC1 + IOPORT_PIN_P055_PFC_05_SPI_RSPCK2 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_5 / SPIn / SPI_RSPCK2 + IOPORT_PIN_P056_PFC_00_IRQ12 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_6 / IRQ / IRQ12 + IOPORT_PIN_P056_PFC_01_ETH1_RXER = (0x01U << IOPORT_PFC_OFFSET), ///< P05_6 / ETHER_ETHn / ETH1_RXER + IOPORT_PIN_P056_PFC_03_GTIOC15A = (0x03U << IOPORT_PFC_OFFSET), ///< P05_6 / GPTn / GTIOC15A + IOPORT_PIN_P056_PFC_04_CMTW1_TIC0 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_6 / CMTWn / CMTW1_TIC0 + IOPORT_PIN_P056_PFC_05_SPI_SSL22 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_6 / SPIn / SPI_SSL22 + IOPORT_PIN_P057_PFC_00_ETH1_TXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P05_7 / ETHER_ETHn / ETH1_TXD2 + IOPORT_PIN_P057_PFC_02_GTIOC15B = (0x02U << IOPORT_PFC_OFFSET), ///< P05_7 / GPTn / GTIOC15B + IOPORT_PIN_P057_PFC_03_CMTW1_TOC1 = (0x03U << IOPORT_PFC_OFFSET), ///< P05_7 / CMTWn / CMTW1_TOC1 + IOPORT_PIN_P057_PFC_04_TXD4_SDA4_MOSI4 = (0x04U << IOPORT_PFC_OFFSET), ///< P05_7 / SCIn / TXD4_SDA4_MOSI4 + IOPORT_PIN_P057_PFC_05_SPI_SSL23 = (0x05U << IOPORT_PFC_OFFSET), ///< P05_7 / SPIn / SPI_SSL23 + IOPORT_PIN_P060_PFC_00_ETH1_TXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_0 / ETHER_ETHn / ETH1_TXD3 + IOPORT_PIN_P060_PFC_02_GTIOC16A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_0 / GPTn / GTIOC16A + IOPORT_PIN_P060_PFC_03_CMTW1_TOC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_0 / CMTWn / CMTW1_TOC0 + IOPORT_PIN_P060_PFC_04_SS4_CTS4_RTS4 = (0x04U << IOPORT_PFC_OFFSET), ///< P06_0 / SCIn / SS4_CTS4_RTS4 + IOPORT_PIN_P060_PFC_05_SPI_SSL23 = (0x05U << IOPORT_PFC_OFFSET), ///< P06_0 / SPIn / SPI_SSL23 + IOPORT_PIN_P060_PFC_06_CANRX1 = (0x06U << IOPORT_PFC_OFFSET), ///< P06_0 / CANFDn / CANRX1 + IOPORT_PIN_P061_PFC_00_ETH1_REFCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P06_1 / ETHER_ETHn / ETH1_REFCLK + IOPORT_PIN_P061_PFC_01_RMII1_REFCLK = (0x01U << IOPORT_PFC_OFFSET), ///< P06_1 / ETHER_ETHn / RMII1_REFCLK + IOPORT_PIN_P061_PFC_03_GTIOC16B = (0x03U << IOPORT_PFC_OFFSET), ///< P06_1 / GPTn / GTIOC16B + IOPORT_PIN_P061_PFC_04_CTS4 = (0x04U << IOPORT_PFC_OFFSET), ///< P06_1 / SCIn / CTS4 + IOPORT_PIN_P061_PFC_05_SPI_SSL22 = (0x05U << IOPORT_PFC_OFFSET), ///< P06_1 / SPIn / SPI_SSL22 + IOPORT_PIN_P061_PFC_06_CANTX1 = (0x06U << IOPORT_PFC_OFFSET), ///< P06_1 / CANFDn / CANTX1 + IOPORT_PIN_P062_PFC_00_ETH1_TXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_2 / ETHER_ETHn / ETH1_TXD1 + IOPORT_PIN_P062_PFC_02_GTIOC17A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_2 / GPTn / GTIOC17A + IOPORT_PIN_P062_PFC_03_CANRXDP1 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_2 / CANFDn / CANRXDP1 + IOPORT_PIN_P063_PFC_00_ETH1_TXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_3 / ETHER_ETHn / ETH1_TXD0 + IOPORT_PIN_P063_PFC_02_GTIOC17B = (0x02U << IOPORT_PFC_OFFSET), ///< P06_3 / GPTn / GTIOC17B + IOPORT_PIN_P063_PFC_03_CMTW1_TIC1 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_3 / CMTWn / CMTW1_TIC1 + IOPORT_PIN_P063_PFC_04_DE4 = (0x04U << IOPORT_PFC_OFFSET), ///< P06_3 / SCIn / DE4 + IOPORT_PIN_P063_PFC_05_SPI_MISO1 = (0x05U << IOPORT_PFC_OFFSET), ///< P06_3 / SPIn / SPI_MISO1 + IOPORT_PIN_P063_PFC_06_CANTXDP1 = (0x06U << IOPORT_PFC_OFFSET), ///< P06_3 / CANFDn / CANTXDP1 + IOPORT_PIN_P064_PFC_00_ETH1_TXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P06_4 / ETHER_ETHn / ETH1_TXCLK + IOPORT_PIN_P064_PFC_02_GTIOC11A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_4 / GPTn / GTIOC11A + IOPORT_PIN_P064_PFC_03_SPI_MOSI1 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_4 / SPIn / SPI_MOSI1 + IOPORT_PIN_P065_PFC_00_ETH1_TXEN = (0x00U << IOPORT_PFC_OFFSET), ///< P06_5 / ETHER_ETHn / ETH1_TXEN + IOPORT_PIN_P065_PFC_02_GTIOC11B = (0x02U << IOPORT_PFC_OFFSET), ///< P06_5 / GPTn / GTIOC11B + IOPORT_PIN_P066_PFC_00_ETH1_RXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_6 / ETHER_ETHn / ETH1_RXD0 + IOPORT_PIN_P066_PFC_02_GTIOC12A = (0x02U << IOPORT_PFC_OFFSET), ///< P06_6 / GPTn / GTIOC12A + IOPORT_PIN_P066_PFC_03_SPI_SSL10 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_6 / SPIn / SPI_SSL10 + IOPORT_PIN_P067_PFC_00_ETH1_RXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P06_7 / ETHER_ETHn / ETH1_RXD1 + IOPORT_PIN_P067_PFC_02_GTIOC12B = (0x02U << IOPORT_PFC_OFFSET), ///< P06_7 / GPTn / GTIOC12B + IOPORT_PIN_P067_PFC_03_SPI_SSL11 = (0x03U << IOPORT_PFC_OFFSET), ///< P06_7 / SPIn / SPI_SSL11 + IOPORT_PIN_P070_PFC_00_ETH1_RXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_0 / ETHER_ETHn / ETH1_RXD2 + IOPORT_PIN_P070_PFC_02_GTIOC13A = (0x02U << IOPORT_PFC_OFFSET), ///< P07_0 / GPTn / GTIOC13A + IOPORT_PIN_P071_PFC_00_ETH1_RXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_1 / ETHER_ETHn / ETH1_RXD3 + IOPORT_PIN_P071_PFC_02_GTIOC13B = (0x02U << IOPORT_PFC_OFFSET), ///< P07_1 / GPTn / GTIOC13B + IOPORT_PIN_P072_PFC_00_ETH1_RXDV = (0x00U << IOPORT_PFC_OFFSET), ///< P07_2 / ETHER_ETHn / ETH1_RXDV + IOPORT_PIN_P073_PFC_00_ETH1_RXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P07_3 / ETHER_ETHn / ETH1_RXCLK + IOPORT_PIN_P074_PFC_00_IRQ1 = (0x00U << IOPORT_PFC_OFFSET), ///< P07_4 / IRQ / IRQ1 + IOPORT_PIN_P074_PFC_01_ADTRG0 = (0x01U << IOPORT_PFC_OFFSET), ///< P07_4 / ADCn / ADTRG0 + IOPORT_PIN_P074_PFC_02_USB_VBUSIN = (0x02U << IOPORT_PFC_OFFSET), ///< P07_4 / USB_HS / USB_VBUSIN + IOPORT_PIN_P084_PFC_00_ETH0_RXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P08_4 / ETHER_ETHn / ETH0_RXD3 + IOPORT_PIN_P084_PFC_02_MTIOC6A = (0x02U << IOPORT_PFC_OFFSET), ///< P08_4 / MTU3n / MTIOC6A + IOPORT_PIN_P085_PFC_00_ETH0_RXDV = (0x00U << IOPORT_PFC_OFFSET), ///< P08_5 / ETHER_ETHn / ETH0_RXDV + IOPORT_PIN_P085_PFC_01_MTIOC6B = (0x01U << IOPORT_PFC_OFFSET), ///< P08_5 / MTU3n / MTIOC6B + IOPORT_PIN_P086_PFC_00_ETH0_RXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P08_6 / ETHER_ETHn / ETH0_RXCLK + IOPORT_PIN_P086_PFC_01_MTIOC6C = (0x01U << IOPORT_PFC_OFFSET), ///< P08_6 / MTU3n / MTIOC6C + IOPORT_PIN_P087_PFC_00_GMAC_MDC = (0x00U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_GMAC / GMAC_MDC + IOPORT_PIN_P087_PFC_01_ETHSW_MDC = (0x01U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_ETHSW / ETHSW_MDC + IOPORT_PIN_P087_PFC_03_ESC_MDC = (0x03U << IOPORT_PFC_OFFSET), ///< P08_7 / ETHER_ESC / ESC_MDC + IOPORT_PIN_P087_PFC_04_MTIOC6D = (0x04U << IOPORT_PFC_OFFSET), ///< P08_7 / MTU3n / MTIOC6D + IOPORT_PIN_P090_PFC_00_GMAC_MDIO = (0x00U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_GMAC / GMAC_MDIO + IOPORT_PIN_P090_PFC_01_ETHSW_MDIO = (0x01U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_ETHSW / ETHSW_MDIO + IOPORT_PIN_P090_PFC_03_ESC_MDIO = (0x03U << IOPORT_PFC_OFFSET), ///< P09_0 / ETHER_ESC / ESC_MDIO + IOPORT_PIN_P090_PFC_04_MTIOC7A = (0x04U << IOPORT_PFC_OFFSET), ///< P09_0 / MTU3n / MTIOC7A + IOPORT_PIN_P091_PFC_00_ETH0_REFCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P09_1 / ETHER_ETHn / ETH0_REFCLK + IOPORT_PIN_P091_PFC_01_RMII0_REFCLK = (0x01U << IOPORT_PFC_OFFSET), ///< P09_1 / ETHER_ETHn / RMII0_REFCLK + IOPORT_PIN_P091_PFC_02_MTIOC7B = (0x02U << IOPORT_PFC_OFFSET), ///< P09_1 / MTU3n / MTIOC7B + IOPORT_PIN_P092_PFC_00_IRQ0 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_2 / IRQ / IRQ0 + IOPORT_PIN_P092_PFC_01_ETH0_RXER = (0x01U << IOPORT_PFC_OFFSET), ///< P09_2 / ETHER_ETHn / ETH0_RXER + IOPORT_PIN_P092_PFC_03_MTIOC7C = (0x03U << IOPORT_PFC_OFFSET), ///< P09_2 / MTU3n / MTIOC7C + IOPORT_PIN_P093_PFC_00_ETH0_TXD3 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_3 / ETHER_ETHn / ETH0_TXD3 + IOPORT_PIN_P093_PFC_01_MTIOC7D = (0x01U << IOPORT_PFC_OFFSET), ///< P09_3 / MTU3n / MTIOC7D + IOPORT_PIN_P094_PFC_00_ETH0_TXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_4 / ETHER_ETHn / ETH0_TXD2 + IOPORT_PIN_P095_PFC_00_ETH0_TXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_5 / ETHER_ETHn / ETH0_TXD1 + IOPORT_PIN_P096_PFC_00_ETH0_TXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P09_6 / ETHER_ETHn / ETH0_TXD0 + IOPORT_PIN_P097_PFC_00_ETH0_TXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P09_7 / ETHER_ETHn / ETH0_TXCLK + IOPORT_PIN_P100_PFC_00_ETH0_TXEN = (0x00U << IOPORT_PFC_OFFSET), ///< P10_0 / ETHER_ETHn / ETH0_TXEN + IOPORT_PIN_P101_PFC_00_ETH0_RXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_1 / ETHER_ETHn / ETH0_RXD0 + IOPORT_PIN_P102_PFC_00_ETH0_RXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_2 / ETHER_ETHn / ETH0_RXD1 + IOPORT_PIN_P103_PFC_00_ETH0_RXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_3 / ETHER_ETHn / ETH0_RXD2 + IOPORT_PIN_P103_PFC_01_RTCAT1HZ = (0x01U << IOPORT_PFC_OFFSET), ///< P10_3 / RTC / RTCAT1HZ + IOPORT_PIN_P104_PFC_00_IRQ11 = (0x00U << IOPORT_PFC_OFFSET), ///< P10_4 / IRQ / IRQ11 + IOPORT_PIN_P104_PFC_01_ETHSW_PHYLINK0 = (0x01U << IOPORT_PFC_OFFSET), ///< P10_4 / ETHER_ETHSW / ETHSW_PHYLINK0 + IOPORT_PIN_P104_PFC_03_ESC_PHYLINK0 = (0x03U << IOPORT_PFC_OFFSET), ///< P10_4 / ETHER_ESC / ESC_PHYLINK0 + IOPORT_PIN_P124_PFC_01_ETH1_CRS = (0x01U << IOPORT_PFC_OFFSET), ///< P12_4 / ETHER_ETHn / ETH1_CRS + IOPORT_PIN_P124_PFC_02_TRACEDATA0 = (0x02U << IOPORT_PFC_OFFSET), ///< P12_4 / TRACE / TRACEDATA0 + IOPORT_PIN_P124_PFC_03_D15 = (0x03U << IOPORT_PFC_OFFSET), ///< P12_4 / BSC / D15 + IOPORT_PIN_P124_PFC_04_MTIOC8B = (0x04U << IOPORT_PFC_OFFSET), ///< P12_4 / MTU3n / MTIOC8B + IOPORT_PIN_P124_PFC_05_GTIOC8B = (0x05U << IOPORT_PFC_OFFSET), ///< P12_4 / GPTn / GTIOC8B + IOPORT_PIN_P124_PFC_06_SPI_SSL01 = (0x06U << IOPORT_PFC_OFFSET), ///< P12_4 / SPIn / SPI_SSL01 + IOPORT_PIN_P124_PFC_08_MBX_HINT = (0x08U << IOPORT_PFC_OFFSET), ///< P12_4 / MBXSEM / MBX_HINT + IOPORT_PIN_P132_PFC_00_IRQ5 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_2 / IRQ / IRQ5 + IOPORT_PIN_P132_PFC_02_ETHSW_PTPOUT2 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_2 / ETHER_ETHSW / ETHSW_PTPOUT2 + IOPORT_PIN_P132_PFC_03_TRACEDATA6 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_2 / TRACE / TRACEDATA6 + IOPORT_PIN_P132_PFC_04_D9 = (0x04U << IOPORT_PFC_OFFSET), ///< P13_2 / BSC / D9 + IOPORT_PIN_P132_PFC_05_ESC_I2CCLK = (0x05U << IOPORT_PFC_OFFSET), ///< P13_2 / ETHER_ESC / ESC_I2CCLK + IOPORT_PIN_P132_PFC_06_MTIOC0A = (0x06U << IOPORT_PFC_OFFSET), ///< P13_2 / MTU3n / MTIOC0A + IOPORT_PIN_P132_PFC_07_GTIOC10A = (0x07U << IOPORT_PFC_OFFSET), ///< P13_2 / GPTn / GTIOC10A + IOPORT_PIN_P132_PFC_08_POE8 = (0x08U << IOPORT_PFC_OFFSET), ///< P13_2 / MTU_POE3 / POE8 + IOPORT_PIN_P132_PFC_09_SS1_CTS1_RTS1 = (0x09U << IOPORT_PFC_OFFSET), ///< P13_2 / SCIn / SS1_CTS1_RTS1 + IOPORT_PIN_P132_PFC_0A_SPI_MISO0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P13_2 / SPIn / SPI_MISO0 + IOPORT_PIN_P132_PFC_0B_IIC_SCL0 = (0x0BU << IOPORT_PFC_OFFSET), ///< P13_2 / IICn / IIC_SCL0 + IOPORT_PIN_P132_PFC_0C_MCLK4 = (0x0CU << IOPORT_PFC_OFFSET), ///< P13_2 / DSMIFn / MCLK4 + IOPORT_PIN_P132_PFC_0E_A13 = (0x0EU << IOPORT_PFC_OFFSET), ///< P13_2 / BSC / A13 + IOPORT_PIN_P133_PFC_01_ETHSW_PTPOUT3 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_3 / ETHER_ETHSW / ETHSW_PTPOUT3 + IOPORT_PIN_P133_PFC_02_TRACEDATA7 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_3 / TRACE / TRACEDATA7 + IOPORT_PIN_P133_PFC_03_D8 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_3 / BSC / D8 + IOPORT_PIN_P133_PFC_04_ESC_I2CDATA = (0x04U << IOPORT_PFC_OFFSET), ///< P13_3 / ETHER_ESC / ESC_I2CDATA + IOPORT_PIN_P133_PFC_05_MTIOC0C = (0x05U << IOPORT_PFC_OFFSET), ///< P13_3 / MTU3n / MTIOC0C + IOPORT_PIN_P133_PFC_06_MTIOC0B = (0x06U << IOPORT_PFC_OFFSET), ///< P13_3 / MTU3n / MTIOC0B + IOPORT_PIN_P133_PFC_07_GTIOC10B = (0x07U << IOPORT_PFC_OFFSET), ///< P13_3 / GPTn / GTIOC10B + IOPORT_PIN_P133_PFC_08_CMTW1_TOC0 = (0x08U << IOPORT_PFC_OFFSET), ///< P13_3 / CMTWn / CMTW1_TOC0 + IOPORT_PIN_P133_PFC_09_CTS1 = (0x09U << IOPORT_PFC_OFFSET), ///< P13_3 / SCIn / CTS1 + IOPORT_PIN_P133_PFC_0A_SPI_RSPCK0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P13_3 / SPIn / SPI_RSPCK0 + IOPORT_PIN_P133_PFC_0B_IIC_SDA0 = (0x0BU << IOPORT_PFC_OFFSET), ///< P13_3 / IICn / IIC_SDA0 + IOPORT_PIN_P133_PFC_0C_MDAT4 = (0x0CU << IOPORT_PFC_OFFSET), ///< P13_3 / DSMIFn / MDAT4 + IOPORT_PIN_P133_PFC_0E_RD = (0x0EU << IOPORT_PFC_OFFSET), ///< P13_3 / BSC / RD + IOPORT_PIN_P134_PFC_01_ESC_RESETOUT = (0x01U << IOPORT_PFC_OFFSET), ///< P13_4 / ETHER_ESC / ESC_RESETOUT + IOPORT_PIN_P134_PFC_02_MTIOC0D = (0x02U << IOPORT_PFC_OFFSET), ///< P13_4 / MTU3n / MTIOC0D + IOPORT_PIN_P134_PFC_03_GTIOC8B = (0x03U << IOPORT_PFC_OFFSET), ///< P13_4 / GPTn / GTIOC8B + IOPORT_PIN_P134_PFC_05_A0 = (0x05U << IOPORT_PFC_OFFSET), ///< P13_4 / BSC / A0 + IOPORT_PIN_P135_PFC_00_XSPI0_WP1 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_5 / XSPIn / XSPI0_WP1 + IOPORT_PIN_P135_PFC_01_GMAC_PTPTRG0 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_GMAC / GMAC_PTPTRG0 + IOPORT_PIN_P135_PFC_02_ESC_LATCH0 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_ESC / ESC_LATCH0 + IOPORT_PIN_P135_PFC_03_ESC_LATCH1 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_5 / ETHER_ESC / ESC_LATCH1 + IOPORT_PIN_P135_PFC_04_MTCLKA = (0x04U << IOPORT_PFC_OFFSET), ///< P13_5 / MTU3 / MTCLKA + IOPORT_PIN_P135_PFC_05_SPI_RSPCK1 = (0x05U << IOPORT_PFC_OFFSET), ///< P13_5 / SPIn / SPI_RSPCK1 + IOPORT_PIN_P135_PFC_06_IIC_SCL2 = (0x06U << IOPORT_PFC_OFFSET), ///< P13_5 / IICn / IIC_SCL2 + IOPORT_PIN_P136_PFC_00_XSPI0_WP0 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_6 / XSPIn / XSPI0_WP0 + IOPORT_PIN_P136_PFC_01_ETHSW_PTPOUT0 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ETHSW / ETHSW_PTPOUT0 + IOPORT_PIN_P136_PFC_02_ESC_SYNC0 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P136_PFC_03_ESC_SYNC1 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_6 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P136_PFC_04_MTCLKB = (0x04U << IOPORT_PFC_OFFSET), ///< P13_6 / MTU3 / MTCLKB + IOPORT_PIN_P137_PFC_00_XSPI0_ECS1 = (0x00U << IOPORT_PFC_OFFSET), ///< P13_7 / XSPIn / XSPI0_ECS1 + IOPORT_PIN_P137_PFC_01_GMAC_PTPTRG1 = (0x01U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_GMAC / GMAC_PTPTRG1 + IOPORT_PIN_P137_PFC_02_ESC_LATCH1 = (0x02U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_ESC / ESC_LATCH1 + IOPORT_PIN_P137_PFC_03_ESC_LATCH0 = (0x03U << IOPORT_PFC_OFFSET), ///< P13_7 / ETHER_ESC / ESC_LATCH0 + IOPORT_PIN_P137_PFC_04_MTCLKC = (0x04U << IOPORT_PFC_OFFSET), ///< P13_7 / MTU3 / MTCLKC + IOPORT_PIN_P137_PFC_05_MBX_HINT = (0x05U << IOPORT_PFC_OFFSET), ///< P13_7 / MBXSEM / MBX_HINT + IOPORT_PIN_P140_PFC_00_XSPI0_INT0 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_0 / XSPIn / XSPI0_INT0 + IOPORT_PIN_P140_PFC_01_ETHSW_PTPOUT1 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ETHSW / ETHSW_PTPOUT1 + IOPORT_PIN_P140_PFC_02_ESC_SYNC1 = (0x02U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P140_PFC_03_ESC_SYNC0 = (0x03U << IOPORT_PFC_OFFSET), ///< P14_0 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P140_PFC_04_MTCLKD = (0x04U << IOPORT_PFC_OFFSET), ///< P14_0 / MTU3 / MTCLKD + IOPORT_PIN_P141_PFC_00_XSPI0_INT1 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_1 / XSPIn / XSPI0_INT1 + IOPORT_PIN_P141_PFC_01_ETH1_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_ETHn / ETH1_COL + IOPORT_PIN_P141_PFC_03_MTIOC8A = (0x03U << IOPORT_PFC_OFFSET), ///< P14_1 / MTU3n / MTIOC8A + IOPORT_PIN_P141_PFC_04_GTIOC8A = (0x04U << IOPORT_PFC_OFFSET), ///< P14_1 / GPTn / GTIOC8A + IOPORT_PIN_P141_PFC_06_GMAC_PTPTRG1 = (0x06U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_GMAC / GMAC_PTPTRG1 + IOPORT_PIN_P141_PFC_07_ESC_LATCH0 = (0x07U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_ESC / ESC_LATCH0 + IOPORT_PIN_P141_PFC_08_ESC_LATCH1 = (0x08U << IOPORT_PFC_OFFSET), ///< P14_1 / ETHER_ESC / ESC_LATCH1 + IOPORT_PIN_P141_PFC_09_HSPI_IO0 = (0x09U << IOPORT_PFC_OFFSET), ///< P14_1 / SHOSTIF / HSPI_IO0 + IOPORT_PIN_P142_PFC_00_IRQ6 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_2 / IRQ / IRQ6 + IOPORT_PIN_P142_PFC_01_XSPI0_ECS0 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_2 / XSPIn / XSPI0_ECS0 + IOPORT_PIN_P142_PFC_02_ETH0_CRS = (0x02U << IOPORT_PFC_OFFSET), ///< P14_2 / ETHER_ETHn / ETH0_CRS + IOPORT_PIN_P142_PFC_04_MTIOC8B = (0x04U << IOPORT_PFC_OFFSET), ///< P14_2 / MTU3n / MTIOC8B + IOPORT_PIN_P142_PFC_05_GTIOC8B = (0x05U << IOPORT_PFC_OFFSET), ///< P14_2 / GPTn / GTIOC8B + IOPORT_PIN_P142_PFC_07_ETH2_CRS = (0x07U << IOPORT_PFC_OFFSET), ///< P14_2 / ETHER_ETHn / ETH2_CRS + IOPORT_PIN_P142_PFC_08_HSPI_CK = (0x08U << IOPORT_PFC_OFFSET), ///< P14_2 / SHOSTIF / HSPI_CK + IOPORT_PIN_P143_PFC_00_XSPI0_RSTO1 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_3 / XSPIn / XSPI0_RSTO1 + IOPORT_PIN_P143_PFC_01_ETH0_COL = (0x01U << IOPORT_PFC_OFFSET), ///< P14_3 / ETHER_ETHn / ETH0_COL + IOPORT_PIN_P143_PFC_04_MTIOC0A = (0x04U << IOPORT_PFC_OFFSET), ///< P14_3 / MTU3n / MTIOC0A + IOPORT_PIN_P143_PFC_06_ETH2_COL = (0x06U << IOPORT_PFC_OFFSET), ///< P14_3 / ETHER_ETHn / ETH2_COL + IOPORT_PIN_P143_PFC_07_HSPI_IO1 = (0x07U << IOPORT_PFC_OFFSET), ///< P14_3 / SHOSTIF / HSPI_IO1 + IOPORT_PIN_P144_PFC_00_XSPI0_DS = (0x00U << IOPORT_PFC_OFFSET), ///< P14_4 / XSPIn / XSPI0_DS + IOPORT_PIN_P144_PFC_01_BS = (0x01U << IOPORT_PFC_OFFSET), ///< P14_4 / BSC / BS + IOPORT_PIN_P144_PFC_02_ESC_IRQ = (0x02U << IOPORT_PFC_OFFSET), ///< P14_4 / ETHER_ESC / ESC_IRQ + IOPORT_PIN_P144_PFC_03_MTIOC0B = (0x03U << IOPORT_PFC_OFFSET), ///< P14_4 / MTU3n / MTIOC0B + IOPORT_PIN_P144_PFC_04_HBS = (0x04U << IOPORT_PFC_OFFSET), ///< P14_4 / PHOSTIF / HBS + IOPORT_PIN_P145_PFC_00_XSPI0_CKN = (0x00U << IOPORT_PFC_OFFSET), ///< P14_5 / XSPIn / XSPI0_CKN + IOPORT_PIN_P145_PFC_01_CS3 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_5 / BSC / CS3 + IOPORT_PIN_P145_PFC_02_POE8 = (0x02U << IOPORT_PFC_OFFSET), ///< P14_5 / MTU_POE3 / POE8 + IOPORT_PIN_P145_PFC_03_HSPI_INT = (0x03U << IOPORT_PFC_OFFSET), ///< P14_5 / SHOSTIF / HSPI_INT + IOPORT_PIN_P146_PFC_00_XSPI0_CKP = (0x00U << IOPORT_PFC_OFFSET), ///< P14_6 / XSPIn / XSPI0_CKP + IOPORT_PIN_P146_PFC_01_A21 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_6 / BSC / A21 + IOPORT_PIN_P147_PFC_00_XSPI0_IO0 = (0x00U << IOPORT_PFC_OFFSET), ///< P14_7 / XSPIn / XSPI0_IO0 + IOPORT_PIN_P147_PFC_01_A22 = (0x01U << IOPORT_PFC_OFFSET), ///< P14_7 / BSC / A22 + IOPORT_PIN_P147_PFC_02_SCK5 = (0x02U << IOPORT_PFC_OFFSET), ///< P14_7 / SCIn / SCK5 + IOPORT_PIN_P147_PFC_03_SPI_MISO1 = (0x03U << IOPORT_PFC_OFFSET), ///< P14_7 / SPIn / SPI_MISO1 + IOPORT_PIN_P147_PFC_04_BS = (0x04U << IOPORT_PFC_OFFSET), ///< P14_7 / BSC / BS + IOPORT_PIN_P150_PFC_00_XSPI0_IO1 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_0 / XSPIn / XSPI0_IO1 + IOPORT_PIN_P150_PFC_01_A23 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_0 / BSC / A23 + IOPORT_PIN_P150_PFC_02_RXD5_SCL5_MISO5 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_0 / SCIn / RXD5_SCL5_MISO5 + IOPORT_PIN_P150_PFC_03_SPI_MOSI1 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_0 / SPIn / SPI_MOSI1 + IOPORT_PIN_P150_PFC_04_CKE = (0x04U << IOPORT_PFC_OFFSET), ///< P15_0 / BSC / CKE + IOPORT_PIN_P151_PFC_00_XSPI0_IO2 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_1 / XSPIn / XSPI0_IO2 + IOPORT_PIN_P151_PFC_01_A24 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_1 / BSC / A24 + IOPORT_PIN_P151_PFC_02_MTIOC0C = (0x02U << IOPORT_PFC_OFFSET), ///< P15_1 / MTU3n / MTIOC0C + IOPORT_PIN_P151_PFC_03_TXD5_SDA5_MOSI5 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_1 / SCIn / TXD5_SDA5_MOSI5 + IOPORT_PIN_P151_PFC_04_SPI_SSL10 = (0x04U << IOPORT_PFC_OFFSET), ///< P15_1 / SPIn / SPI_SSL10 + IOPORT_PIN_P151_PFC_05_CAS = (0x05U << IOPORT_PFC_OFFSET), ///< P15_1 / BSC / CAS + IOPORT_PIN_P152_PFC_00_XSPI0_IO3 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_2 / XSPIn / XSPI0_IO3 + IOPORT_PIN_P152_PFC_01_A25 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_2 / BSC / A25 + IOPORT_PIN_P152_PFC_02_MTIOC0D = (0x02U << IOPORT_PFC_OFFSET), ///< P15_2 / MTU3n / MTIOC0D + IOPORT_PIN_P152_PFC_03_SS5_CTS5_RTS5 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_2 / SCIn / SS5_CTS5_RTS5 + IOPORT_PIN_P152_PFC_04_SPI_SSL11 = (0x04U << IOPORT_PFC_OFFSET), ///< P15_2 / SPIn / SPI_SSL11 + IOPORT_PIN_P152_PFC_05_RAS = (0x05U << IOPORT_PFC_OFFSET), ///< P15_2 / BSC / RAS + IOPORT_PIN_P153_PFC_00_XSPI0_IO4 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_3 / XSPIn / XSPI0_IO4 + IOPORT_PIN_P153_PFC_01_MTIOC8C = (0x01U << IOPORT_PFC_OFFSET), ///< P15_3 / MTU3n / MTIOC8C + IOPORT_PIN_P153_PFC_02_MCLK1 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_3 / DSMIFn / MCLK1 + IOPORT_PIN_P153_PFC_03_D11 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_3 / BSC / D11 + IOPORT_PIN_P154_PFC_00_XSPI0_IO5 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_4 / XSPIn / XSPI0_IO5 + IOPORT_PIN_P154_PFC_01_MTIOC8D = (0x01U << IOPORT_PFC_OFFSET), ///< P15_4 / MTU3n / MTIOC8D + IOPORT_PIN_P154_PFC_02_MDAT1 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_4 / DSMIFn / MDAT1 + IOPORT_PIN_P154_PFC_03_D12 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_4 / BSC / D12 + IOPORT_PIN_P155_PFC_00_XSPI0_IO6 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_5 / XSPIn / XSPI0_IO6 + IOPORT_PIN_P155_PFC_01_MCLK2 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_5 / DSMIFn / MCLK2 + IOPORT_PIN_P155_PFC_02_D13 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_5 / BSC / D13 + IOPORT_PIN_P156_PFC_00_XSPI0_IO7 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_6 / XSPIn / XSPI0_IO7 + IOPORT_PIN_P156_PFC_01_SPI_SSL12 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_6 / SPIn / SPI_SSL12 + IOPORT_PIN_P156_PFC_02_MDAT2 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_6 / DSMIFn / MDAT2 + IOPORT_PIN_P156_PFC_03_D14 = (0x03U << IOPORT_PFC_OFFSET), ///< P15_6 / BSC / D14 + IOPORT_PIN_P157_PFC_00_XSPI0_CS0 = (0x00U << IOPORT_PFC_OFFSET), ///< P15_7 / XSPIn / XSPI0_CS0 + IOPORT_PIN_P157_PFC_01_CTS5 = (0x01U << IOPORT_PFC_OFFSET), ///< P15_7 / SCIn / CTS5 + IOPORT_PIN_P157_PFC_02_SPI_SSL13 = (0x02U << IOPORT_PFC_OFFSET), ///< P15_7 / SPIn / SPI_SSL13 + IOPORT_PIN_P157_PFC_03_TEND = (0x03U << IOPORT_PFC_OFFSET), ///< P15_7 / DMAC / TEND + IOPORT_PIN_P160_PFC_00_XSPI0_CS1 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_0 / XSPIn / XSPI0_CS1 + IOPORT_PIN_P160_PFC_01_ETH0_TXER = (0x01U << IOPORT_PFC_OFFSET), ///< P16_0 / ETHER_ETHn / ETH0_TXER + IOPORT_PIN_P160_PFC_02_TXD0_SDA0_MOSI0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_0 / SCIn / TXD0_SDA0_MOSI0 + IOPORT_PIN_P160_PFC_03_SPI_MOSI3 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_0 / SPIn / SPI_MOSI3 + IOPORT_PIN_P160_PFC_04_MCLK3 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_0 / DSMIFn / MCLK3 + IOPORT_PIN_P160_PFC_06_ETH2_REFCLK = (0x06U << IOPORT_PFC_OFFSET), ///< P16_0 / ETHER_ETHn / ETH2_REFCLK + IOPORT_PIN_P160_PFC_07_HSPI_CS = (0x07U << IOPORT_PFC_OFFSET), ///< P16_0 / SHOSTIF / HSPI_CS + IOPORT_PIN_P161_PFC_00_XSPI0_RESET0 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_1 / XSPIn / XSPI0_RESET0 + IOPORT_PIN_P161_PFC_01_CMTW0_TOC1 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_1 / CMTWn / CMTW0_TOC1 + IOPORT_PIN_P161_PFC_02_ADTRG0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_1 / ADCn / ADTRG0 + IOPORT_PIN_P161_PFC_03_RXD0_SCL0_MISO0 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_1 / SCIn / RXD0_SCL0_MISO0 + IOPORT_PIN_P161_PFC_04_SPI_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_1 / SPIn / SPI_MISO3 + IOPORT_PIN_P161_PFC_05_MDAT3 = (0x05U << IOPORT_PFC_OFFSET), ///< P16_1 / DSMIFn / MDAT3 + IOPORT_PIN_P161_PFC_07_CS2 = (0x07U << IOPORT_PFC_OFFSET), ///< P16_1 / BSC / CS2 + IOPORT_PIN_P161_PFC_08_HCS1 = (0x08U << IOPORT_PFC_OFFSET), ///< P16_1 / PHOSTIF / HCS1 + IOPORT_PIN_P162_PFC_00_NMI = (0x00U << IOPORT_PFC_OFFSET), ///< P16_2 / IRQ / NMI + IOPORT_PIN_P162_PFC_01_XSPI0_RESET1 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_2 / XSPIn / XSPI0_RESET1 + IOPORT_PIN_P162_PFC_02_CTS0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_2 / SCIn / CTS0 + IOPORT_PIN_P162_PFC_03_SPI_RSPCK3 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_2 / SPIn / SPI_RSPCK3 + IOPORT_PIN_P162_PFC_04_USB_EXICEN = (0x04U << IOPORT_PFC_OFFSET), ///< P16_2 / USB_HS / USB_EXICEN + IOPORT_PIN_P162_PFC_06_HSPI_IO2 = (0x06U << IOPORT_PFC_OFFSET), ///< P16_2 / SHOSTIF / HSPI_IO2 + IOPORT_PIN_P162_PFC_07_HERROUT = (0x07U << IOPORT_PFC_OFFSET), ///< P16_2 / PHOSTIF / HERROUT + IOPORT_PIN_P163_PFC_00_IRQ7 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_3 / IRQ / IRQ7 + IOPORT_PIN_P163_PFC_01_XSPI0_RSTO0 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_3 / XSPIn / XSPI0_RSTO0 + IOPORT_PIN_P163_PFC_02_ETH1_TXER = (0x02U << IOPORT_PFC_OFFSET), ///< P16_3 / ETHER_ETHn / ETH1_TXER + IOPORT_PIN_P163_PFC_03_GTADSMP1 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_3 / GPT / GTADSMP1 + IOPORT_PIN_P163_PFC_04_SCK0 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_3 / SCIn / SCK0 + IOPORT_PIN_P163_PFC_05_SPI_SSL30 = (0x05U << IOPORT_PFC_OFFSET), ///< P16_3 / SPIn / SPI_SSL30 + IOPORT_PIN_P163_PFC_07_ETH1_CRS = (0x07U << IOPORT_PFC_OFFSET), ///< P16_3 / ETHER_ETHn / ETH1_CRS + IOPORT_PIN_P163_PFC_08_CS3 = (0x08U << IOPORT_PFC_OFFSET), ///< P16_3 / BSC / CS3 + IOPORT_PIN_P163_PFC_09_HSPI_IO3 = (0x09U << IOPORT_PFC_OFFSET), ///< P16_3 / SHOSTIF / HSPI_IO3 + IOPORT_PIN_P165_PFC_00_MTIC5U = (0x00U << IOPORT_PFC_OFFSET), ///< P16_5 / MTU3n / MTIC5U + IOPORT_PIN_P165_PFC_01_TXD0_SDA0_MOSI0 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_5 / SCIn / TXD0_SDA0_MOSI0 + IOPORT_PIN_P165_PFC_02_A15 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_5 / BSC / A15 + IOPORT_PIN_P165_PFC_03_HSPI_IO4 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_5 / SHOSTIF / HSPI_IO4 + IOPORT_PIN_P166_PFC_00_IRQ8 = (0x00U << IOPORT_PFC_OFFSET), ///< P16_6 / IRQ / IRQ8 + IOPORT_PIN_P166_PFC_01_MTIC5V = (0x01U << IOPORT_PFC_OFFSET), ///< P16_6 / MTU3n / MTIC5V + IOPORT_PIN_P166_PFC_02_RXD0_SCL0_MISO0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_6 / SCIn / RXD0_SCL0_MISO0 + IOPORT_PIN_P166_PFC_03_CS0 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_6 / BSC / CS0 + IOPORT_PIN_P166_PFC_04_HSPI_IO5 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_6 / SHOSTIF / HSPI_IO5 + IOPORT_PIN_P166_PFC_05_HCS0 = (0x05U << IOPORT_PFC_OFFSET), ///< P16_6 / PHOSTIF / HCS0 + IOPORT_PIN_P167_PFC_00_MTIC5W = (0x00U << IOPORT_PFC_OFFSET), ///< P16_7 / MTU3n / MTIC5W + IOPORT_PIN_P167_PFC_01_SCK0 = (0x01U << IOPORT_PFC_OFFSET), ///< P16_7 / SCIn / SCK0 + IOPORT_PIN_P167_PFC_02_XSPI1_IO0 = (0x02U << IOPORT_PFC_OFFSET), ///< P16_7 / XSPIn / XSPI1_IO0 + IOPORT_PIN_P167_PFC_03_A13 = (0x03U << IOPORT_PFC_OFFSET), ///< P16_7 / BSC / A13 + IOPORT_PIN_P167_PFC_04_HA13 = (0x04U << IOPORT_PFC_OFFSET), ///< P16_7 / PHOSTIF / HA13 + IOPORT_PIN_P170_PFC_00_ESC_IRQ = (0x00U << IOPORT_PFC_OFFSET), ///< P17_0 / ETHER_ESC / ESC_IRQ + IOPORT_PIN_P170_PFC_01_SS0_CTS0_RTS0 = (0x01U << IOPORT_PFC_OFFSET), ///< P17_0 / SCIn / SS0_CTS0_RTS0 + IOPORT_PIN_P170_PFC_02_XSPI1_IO1 = (0x02U << IOPORT_PFC_OFFSET), ///< P17_0 / XSPIn / XSPI1_IO1 + IOPORT_PIN_P173_PFC_00_TRACECTL = (0x00U << IOPORT_PFC_OFFSET), ///< P17_3 / TRACE / TRACECTL + IOPORT_PIN_P173_PFC_01_GTETRGA = (0x01U << IOPORT_PFC_OFFSET), ///< P17_3 / GPT_POEG / GTETRGA + IOPORT_PIN_P173_PFC_02_POE0 = (0x02U << IOPORT_PFC_OFFSET), ///< P17_3 / MTU_POE3 / POE0 + IOPORT_PIN_P173_PFC_03_ADTRG1 = (0x03U << IOPORT_PFC_OFFSET), ///< P17_3 / ADCn / ADTRG1 + IOPORT_PIN_P173_PFC_04_SPI_SSL31 = (0x04U << IOPORT_PFC_OFFSET), ///< P17_3 / SPIn / SPI_SSL31 + IOPORT_PIN_P173_PFC_05_DREQ = (0x05U << IOPORT_PFC_OFFSET), ///< P17_3 / DMAC / DREQ + IOPORT_PIN_P173_PFC_07_XSPI1_IO2 = (0x07U << IOPORT_PFC_OFFSET), ///< P17_3 / XSPIn / XSPI1_IO2 + IOPORT_PIN_P174_PFC_00_TRACECLK = (0x00U << IOPORT_PFC_OFFSET), ///< P17_4 / TRACE / TRACECLK + IOPORT_PIN_P174_PFC_01_MTIOC3C = (0x01U << IOPORT_PFC_OFFSET), ///< P17_4 / MTU3n / MTIOC3C + IOPORT_PIN_P174_PFC_02_GTETRGB = (0x02U << IOPORT_PFC_OFFSET), ///< P17_4 / GPT_POEG / GTETRGB + IOPORT_PIN_P174_PFC_03_GTIOC0A = (0x03U << IOPORT_PFC_OFFSET), ///< P17_4 / GPTn / GTIOC0A + IOPORT_PIN_P174_PFC_04_CTS3 = (0x04U << IOPORT_PFC_OFFSET), ///< P17_4 / SCIn / CTS3 + IOPORT_PIN_P174_PFC_05_SPI_SSL32 = (0x05U << IOPORT_PFC_OFFSET), ///< P17_4 / SPIn / SPI_SSL32 + IOPORT_PIN_P174_PFC_07_XSPI1_IO3 = (0x07U << IOPORT_PFC_OFFSET), ///< P17_4 / XSPIn / XSPI1_IO3 + IOPORT_PIN_P174_PFC_08_DACK = (0x08U << IOPORT_PFC_OFFSET), ///< P17_4 / DMAC / DACK + IOPORT_PIN_P175_PFC_01_MTIOC3A = (0x01U << IOPORT_PFC_OFFSET), ///< P17_5 / MTU3n / MTIOC3A + IOPORT_PIN_P175_PFC_02_GTETRGC = (0x02U << IOPORT_PFC_OFFSET), ///< P17_5 / GPT_POEG / GTETRGC + IOPORT_PIN_P175_PFC_03_GTIOC0B = (0x03U << IOPORT_PFC_OFFSET), ///< P17_5 / GPTn / GTIOC0B + IOPORT_PIN_P175_PFC_04_TEND = (0x04U << IOPORT_PFC_OFFSET), ///< P17_5 / DMAC / TEND + IOPORT_PIN_P175_PFC_05_USB_OVRCUR = (0x05U << IOPORT_PFC_OFFSET), ///< P17_5 / USB_HS / USB_OVRCUR + IOPORT_PIN_P176_PFC_00_MTIOC3B = (0x00U << IOPORT_PFC_OFFSET), ///< P17_6 / MTU3n / MTIOC3B + IOPORT_PIN_P176_PFC_01_GTIOC1A = (0x01U << IOPORT_PFC_OFFSET), ///< P17_6 / GPTn / GTIOC1A + IOPORT_PIN_P176_PFC_02_SCK3 = (0x02U << IOPORT_PFC_OFFSET), ///< P17_6 / SCIn / SCK3 + IOPORT_PIN_P176_PFC_04_XSPI1_DS = (0x04U << IOPORT_PFC_OFFSET), ///< P17_6 / XSPIn / XSPI1_DS + IOPORT_PIN_P176_PFC_05_RD_WR = (0x05U << IOPORT_PFC_OFFSET), ///< P17_6 / BSC / RD_WR + IOPORT_PIN_P176_PFC_06_HWRSTB = (0x06U << IOPORT_PFC_OFFSET), ///< P17_6 / PHOSTIF / HWRSTB + IOPORT_PIN_P177_PFC_00_MTIOC4A = (0x00U << IOPORT_PFC_OFFSET), ///< P17_7 / MTU3n / MTIOC4A + IOPORT_PIN_P177_PFC_01_MTIOC4C = (0x01U << IOPORT_PFC_OFFSET), ///< P17_7 / MTU3n / MTIOC4C + IOPORT_PIN_P177_PFC_02_GTIOC2A = (0x02U << IOPORT_PFC_OFFSET), ///< P17_7 / GPTn / GTIOC2A + IOPORT_PIN_P177_PFC_03_GTIOC3A = (0x03U << IOPORT_PFC_OFFSET), ///< P17_7 / GPTn / GTIOC3A + IOPORT_PIN_P177_PFC_04_RXD3_SCL3_MISO3 = (0x04U << IOPORT_PFC_OFFSET), ///< P17_7 / SCIn / RXD3_SCL3_MISO3 + IOPORT_PIN_P177_PFC_05_DACK = (0x05U << IOPORT_PFC_OFFSET), ///< P17_7 / DMAC / DACK + IOPORT_PIN_P177_PFC_07_XSPI1_CKP = (0x07U << IOPORT_PFC_OFFSET), ///< P17_7 / XSPIn / XSPI1_CKP + IOPORT_PIN_P177_PFC_08_RD = (0x08U << IOPORT_PFC_OFFSET), ///< P17_7 / BSC / RD + IOPORT_PIN_P177_PFC_09_HRD = (0x09U << IOPORT_PFC_OFFSET), ///< P17_7 / PHOSTIF / HRD + IOPORT_PIN_P180_PFC_00_MTIOC4C = (0x00U << IOPORT_PFC_OFFSET), ///< P18_0 / MTU3n / MTIOC4C + IOPORT_PIN_P180_PFC_01_MTIOC4A = (0x01U << IOPORT_PFC_OFFSET), ///< P18_0 / MTU3n / MTIOC4A + IOPORT_PIN_P180_PFC_02_GTIOC3A = (0x02U << IOPORT_PFC_OFFSET), ///< P18_0 / GPTn / GTIOC3A + IOPORT_PIN_P180_PFC_03_GTIOC2A = (0x03U << IOPORT_PFC_OFFSET), ///< P18_0 / GPTn / GTIOC2A + IOPORT_PIN_P180_PFC_04_TXD3_SDA3_MOSI3 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_0 / SCIn / TXD3_SDA3_MOSI3 + IOPORT_PIN_P180_PFC_05_WE0_DQMLL = (0x05U << IOPORT_PFC_OFFSET), ///< P18_0 / BSC / WE0_DQMLL + IOPORT_PIN_P180_PFC_06_HSPI_IO6 = (0x06U << IOPORT_PFC_OFFSET), ///< P18_0 / SHOSTIF / HSPI_IO6 + IOPORT_PIN_P180_PFC_07_HWR0 = (0x07U << IOPORT_PFC_OFFSET), ///< P18_0 / PHOSTIF / HWR0 + IOPORT_PIN_P181_PFC_00_IRQ10 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_1 / IRQ / IRQ10 + IOPORT_PIN_P181_PFC_01_MTIOC3D = (0x01U << IOPORT_PFC_OFFSET), ///< P18_1 / MTU3n / MTIOC3D + IOPORT_PIN_P181_PFC_02_GTIOC1B = (0x02U << IOPORT_PFC_OFFSET), ///< P18_1 / GPTn / GTIOC1B + IOPORT_PIN_P181_PFC_03_ADTRG1 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_1 / ADCn / ADTRG1 + IOPORT_PIN_P181_PFC_04_SS3_CTS3_RTS3 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_1 / SCIn / SS3_CTS3_RTS3 + IOPORT_PIN_P181_PFC_06_WE1_DQMLU = (0x06U << IOPORT_PFC_OFFSET), ///< P18_1 / BSC / WE1_DQMLU + IOPORT_PIN_P181_PFC_07_HSPI_IO7 = (0x07U << IOPORT_PFC_OFFSET), ///< P18_1 / SHOSTIF / HSPI_IO7 + IOPORT_PIN_P181_PFC_08_HWR1 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_1 / PHOSTIF / HWR1 + IOPORT_PIN_P182_PFC_00_MTIOC4B = (0x00U << IOPORT_PFC_OFFSET), ///< P18_2 / MTU3n / MTIOC4B + IOPORT_PIN_P182_PFC_01_MTIOC4D = (0x01U << IOPORT_PFC_OFFSET), ///< P18_2 / MTU3n / MTIOC4D + IOPORT_PIN_P182_PFC_02_GTIOC2B = (0x02U << IOPORT_PFC_OFFSET), ///< P18_2 / GPTn / GTIOC2B + IOPORT_PIN_P182_PFC_03_GTIOC3B = (0x03U << IOPORT_PFC_OFFSET), ///< P18_2 / GPTn / GTIOC3B + IOPORT_PIN_P182_PFC_05_XSPI1_CS0 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_2 / XSPIn / XSPI1_CS0 + IOPORT_PIN_P182_PFC_06_ETH1_COL = (0x06U << IOPORT_PFC_OFFSET), ///< P18_2 / ETHER_ETHn / ETH1_COL + IOPORT_PIN_P182_PFC_07_BS = (0x07U << IOPORT_PFC_OFFSET), ///< P18_2 / BSC / BS + IOPORT_PIN_P182_PFC_08_SCK0 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_2 / SCIn / SCK0 + IOPORT_PIN_P182_PFC_09_IIC_SDA2 = (0x09U << IOPORT_PFC_OFFSET), ///< P18_2 / IICn / IIC_SDA2 + IOPORT_PIN_P183_PFC_00_IRQ0 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_3 / IRQ / IRQ0 + IOPORT_PIN_P183_PFC_01_MTIOC4D = (0x01U << IOPORT_PFC_OFFSET), ///< P18_3 / MTU3n / MTIOC4D + IOPORT_PIN_P183_PFC_02_MTIOC4B = (0x02U << IOPORT_PFC_OFFSET), ///< P18_3 / MTU3n / MTIOC4B + IOPORT_PIN_P183_PFC_03_GTIOC3B = (0x03U << IOPORT_PFC_OFFSET), ///< P18_3 / GPTn / GTIOC3B + IOPORT_PIN_P183_PFC_04_GTIOC2B = (0x04U << IOPORT_PFC_OFFSET), ///< P18_3 / GPTn / GTIOC2B + IOPORT_PIN_P183_PFC_05_CMTW1_TIC1 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_3 / CMTWn / CMTW1_TIC1 + IOPORT_PIN_P183_PFC_06_CANRXDP1 = (0x06U << IOPORT_PFC_OFFSET), ///< P18_3 / CANFDn / CANRXDP1 + IOPORT_PIN_P183_PFC_08_XSPI1_IO4 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_3 / XSPIn / XSPI1_IO4 + IOPORT_PIN_P183_PFC_09_ETH2_CRS = (0x09U << IOPORT_PFC_OFFSET), ///< P18_3 / ETHER_ETHn / ETH2_CRS + IOPORT_PIN_P183_PFC_0A_CKE = (0x0AU << IOPORT_PFC_OFFSET), ///< P18_3 / BSC / CKE + IOPORT_PIN_P184_PFC_00_IRQ1 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_4 / IRQ / IRQ1 + IOPORT_PIN_P184_PFC_01_MTIC5U = (0x01U << IOPORT_PFC_OFFSET), ///< P18_4 / MTU3n / MTIC5U + IOPORT_PIN_P184_PFC_02_TXD4_SDA4_MOSI4 = (0x02U << IOPORT_PFC_OFFSET), ///< P18_4 / SCIn / TXD4_SDA4_MOSI4 + IOPORT_PIN_P184_PFC_03_SPI_RSPCK2 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_4 / SPIn / SPI_RSPCK2 + IOPORT_PIN_P184_PFC_05_XSPI1_IO5 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_4 / XSPIn / XSPI1_IO5 + IOPORT_PIN_P184_PFC_06_ETH1_CRS = (0x06U << IOPORT_PFC_OFFSET), ///< P18_4 / ETHER_ETHn / ETH1_CRS + IOPORT_PIN_P184_PFC_07_CAS = (0x07U << IOPORT_PFC_OFFSET), ///< P18_4 / BSC / CAS + IOPORT_PIN_P184_PFC_08_CANTX0 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_4 / CANFDn / CANTX0 + IOPORT_PIN_P185_PFC_00_TRACECTL = (0x00U << IOPORT_PFC_OFFSET), ///< P18_5 / TRACE / TRACECTL + IOPORT_PIN_P185_PFC_01_MTIC5V = (0x01U << IOPORT_PFC_OFFSET), ///< P18_5 / MTU3n / MTIC5V + IOPORT_PIN_P185_PFC_02_RXD4_SCL4_MISO4 = (0x02U << IOPORT_PFC_OFFSET), ///< P18_5 / SCIn / RXD4_SCL4_MISO4 + IOPORT_PIN_P185_PFC_03_SPI_MOSI2 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_5 / SPIn / SPI_MOSI2 + IOPORT_PIN_P185_PFC_05_XSPI1_IO6 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_5 / XSPIn / XSPI1_IO6 + IOPORT_PIN_P185_PFC_06_ETH2_COL = (0x06U << IOPORT_PFC_OFFSET), ///< P18_5 / ETHER_ETHn / ETH2_COL + IOPORT_PIN_P185_PFC_07_RAS = (0x07U << IOPORT_PFC_OFFSET), ///< P18_5 / BSC / RAS + IOPORT_PIN_P185_PFC_08_CANRX0 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_5 / CANFDn / CANRX0 + IOPORT_PIN_P186_PFC_00_IRQ11 = (0x00U << IOPORT_PFC_OFFSET), ///< P18_6 / IRQ / IRQ11 + IOPORT_PIN_P186_PFC_01_TRACECLK = (0x01U << IOPORT_PFC_OFFSET), ///< P18_6 / TRACE / TRACECLK + IOPORT_PIN_P186_PFC_02_MTIC5W = (0x02U << IOPORT_PFC_OFFSET), ///< P18_6 / MTU3n / MTIC5W + IOPORT_PIN_P186_PFC_03_ADTRG0 = (0x03U << IOPORT_PFC_OFFSET), ///< P18_6 / ADCn / ADTRG0 + IOPORT_PIN_P186_PFC_04_SCK4 = (0x04U << IOPORT_PFC_OFFSET), ///< P18_6 / SCIn / SCK4 + IOPORT_PIN_P186_PFC_05_SPI_MISO2 = (0x05U << IOPORT_PFC_OFFSET), ///< P18_6 / SPIn / SPI_MISO2 + IOPORT_PIN_P186_PFC_06_IIC_SCL2 = (0x06U << IOPORT_PFC_OFFSET), ///< P18_6 / IICn / IIC_SCL2 + IOPORT_PIN_P186_PFC_08_XSPI1_IO7 = (0x08U << IOPORT_PFC_OFFSET), ///< P18_6 / XSPIn / XSPI1_IO7 + IOPORT_PIN_P186_PFC_09_ETH1_COL = (0x09U << IOPORT_PFC_OFFSET), ///< P18_6 / ETHER_ETHn / ETH1_COL + IOPORT_PIN_P186_PFC_0A_DE4 = (0x0AU << IOPORT_PFC_OFFSET), ///< P18_6 / SCIn / DE4 + IOPORT_PIN_P190_PFC_00_USB_VBUSEN = (0x00U << IOPORT_PFC_OFFSET), ///< P19_0 / USB_HS / USB_VBUSEN + IOPORT_PIN_P201_PFC_00_ETHSW_TDMAOUT0 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ETHSW / ETHSW_TDMAOUT0 + IOPORT_PIN_P201_PFC_01_ESC_LINKACT0 = (0x01U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ESC / ESC_LINKACT0 + IOPORT_PIN_P201_PFC_02_ETHSW_PTPOUT3 = (0x02U << IOPORT_PFC_OFFSET), ///< P20_1 / ETHER_ETHSW / ETHSW_PTPOUT3 + IOPORT_PIN_P202_PFC_00_ETHSW_TDMAOUT1 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ETHSW / ETHSW_TDMAOUT1 + IOPORT_PIN_P202_PFC_01_ESC_LEDRUN = (0x01U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ESC / ESC_LEDRUN + IOPORT_PIN_P202_PFC_02_ESC_LEDSTER = (0x02U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ESC / ESC_LEDSTER + IOPORT_PIN_P202_PFC_03_DE3 = (0x03U << IOPORT_PFC_OFFSET), ///< P20_2 / SCIn / DE3 + IOPORT_PIN_P202_PFC_04_ETHSW_PTPOUT2 = (0x04U << IOPORT_PFC_OFFSET), ///< P20_2 / ETHER_ETHSW / ETHSW_PTPOUT2 + IOPORT_PIN_P203_PFC_00_ETHSW_TDMAOUT2 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ETHSW / ETHSW_TDMAOUT2 + IOPORT_PIN_P203_PFC_01_ESC_LEDERR = (0x01U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ESC / ESC_LEDERR + IOPORT_PIN_P203_PFC_02_ETHSW_PTPOUT1 = (0x02U << IOPORT_PFC_OFFSET), ///< P20_3 / ETHER_ETHSW / ETHSW_PTPOUT1 + IOPORT_PIN_P204_PFC_00_ETHSW_TDMAOUT3 = (0x00U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ETHSW / ETHSW_TDMAOUT3 + IOPORT_PIN_P204_PFC_01_ESC_LINKACT1 = (0x01U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ESC / ESC_LINKACT1 + IOPORT_PIN_P204_PFC_02_ETHSW_PTPOUT0 = (0x02U << IOPORT_PFC_OFFSET), ///< P20_4 / ETHER_ETHSW / ETHSW_PTPOUT0 + IOPORT_PIN_P211_PFC_00_TRACEDATA0 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_1 / TRACE / TRACEDATA0 + IOPORT_PIN_P211_PFC_01_D0 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_1 / BSC / D0 + IOPORT_PIN_P211_PFC_02_MTIOC6A = (0x02U << IOPORT_PFC_OFFSET), ///< P21_1 / MTU3n / MTIOC6A + IOPORT_PIN_P211_PFC_03_GTIOC14A = (0x03U << IOPORT_PFC_OFFSET), ///< P21_1 / GPTn / GTIOC14A + IOPORT_PIN_P211_PFC_04_CMTW0_TIC0 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_1 / CMTWn / CMTW0_TIC0 + IOPORT_PIN_P211_PFC_05_SCK5 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_1 / SCIn / SCK5 + IOPORT_PIN_P211_PFC_06_SPI_SSL20 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_1 / SPIn / SPI_SSL20 + IOPORT_PIN_P211_PFC_07_IIC_SCL1 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_1 / IICn / IIC_SCL1 + IOPORT_PIN_P211_PFC_08_MCLK0 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_1 / DSMIFn / MCLK0 + IOPORT_PIN_P211_PFC_0A_ESC_SYNC0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P21_1 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P211_PFC_0B_ESC_SYNC1 = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_1 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P211_PFC_0C_HSPI_INT = (0x0CU << IOPORT_PFC_OFFSET), ///< P21_1 / SHOSTIF / HSPI_INT + IOPORT_PIN_P211_PFC_0D_HD0 = (0x0DU << IOPORT_PFC_OFFSET), ///< P21_1 / PHOSTIF / HD0 + IOPORT_PIN_P212_PFC_00_TRACEDATA1 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_2 / TRACE / TRACEDATA1 + IOPORT_PIN_P212_PFC_01_D1 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_2 / BSC / D1 + IOPORT_PIN_P212_PFC_02_MTIOC6B = (0x02U << IOPORT_PFC_OFFSET), ///< P21_2 / MTU3n / MTIOC6B + IOPORT_PIN_P212_PFC_03_GTIOC14B = (0x03U << IOPORT_PFC_OFFSET), ///< P21_2 / GPTn / GTIOC14B + IOPORT_PIN_P212_PFC_04_CMTW0_TIC1 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_2 / CMTWn / CMTW0_TIC1 + IOPORT_PIN_P212_PFC_05_RXD5_SCL5_MISO5 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_2 / SCIn / RXD5_SCL5_MISO5 + IOPORT_PIN_P212_PFC_06_SPI_MISO2 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_2 / SPIn / SPI_MISO2 + IOPORT_PIN_P212_PFC_07_IIC_SDA1 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_2 / IICn / IIC_SDA1 + IOPORT_PIN_P212_PFC_08_MDAT0 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_2 / DSMIFn / MDAT0 + IOPORT_PIN_P212_PFC_0A_ESC_SYNC0 = (0x0AU << IOPORT_PFC_OFFSET), ///< P21_2 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P212_PFC_0B_ESC_SYNC1 = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_2 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P212_PFC_0C_HD1 = (0x0CU << IOPORT_PFC_OFFSET), ///< P21_2 / PHOSTIF / HD1 + IOPORT_PIN_P213_PFC_00_TRACEDATA2 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_3 / TRACE / TRACEDATA2 + IOPORT_PIN_P213_PFC_01_D2 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_3 / BSC / D2 + IOPORT_PIN_P213_PFC_02_MTIOC6C = (0x02U << IOPORT_PFC_OFFSET), ///< P21_3 / MTU3n / MTIOC6C + IOPORT_PIN_P213_PFC_03_GTIOC15A = (0x03U << IOPORT_PFC_OFFSET), ///< P21_3 / GPTn / GTIOC15A + IOPORT_PIN_P213_PFC_04_TXD5_SDA5_MOSI5 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_3 / SCIn / TXD5_SDA5_MOSI5 + IOPORT_PIN_P213_PFC_05_SPI_SSL33 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_3 / SPIn / SPI_SSL33 + IOPORT_PIN_P213_PFC_06_MCLK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_3 / DSMIFn / MCLK1 + IOPORT_PIN_P213_PFC_08_NMI = (0x08U << IOPORT_PFC_OFFSET), ///< P21_3 / IRQ / NMI + IOPORT_PIN_P213_PFC_09_HD2 = (0x09U << IOPORT_PFC_OFFSET), ///< P21_3 / PHOSTIF / HD2 + IOPORT_PIN_P214_PFC_00_TRACEDATA3 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_4 / TRACE / TRACEDATA3 + IOPORT_PIN_P214_PFC_01_D3 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_4 / BSC / D3 + IOPORT_PIN_P214_PFC_02_MTIOC6D = (0x02U << IOPORT_PFC_OFFSET), ///< P21_4 / MTU3n / MTIOC6D + IOPORT_PIN_P214_PFC_03_GTIOC15B = (0x03U << IOPORT_PFC_OFFSET), ///< P21_4 / GPTn / GTIOC15B + IOPORT_PIN_P214_PFC_04_SS5_CTS5_RTS5 = (0x04U << IOPORT_PFC_OFFSET), ///< P21_4 / SCIn / SS5_CTS5_RTS5 + IOPORT_PIN_P214_PFC_05_SPI_SSL02 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_4 / SPIn / SPI_SSL02 + IOPORT_PIN_P214_PFC_06_MDAT1 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_4 / DSMIFn / MDAT1 + IOPORT_PIN_P214_PFC_08_ETHSW_PTPOUT1 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_4 / ETHER_ETHSW / ETHSW_PTPOUT1 + IOPORT_PIN_P214_PFC_09_ESC_SYNC0 = (0x09U << IOPORT_PFC_OFFSET), ///< P21_4 / ETHER_ESC / ESC_SYNC0 + IOPORT_PIN_P214_PFC_0A_ESC_SYNC1 = (0x0AU << IOPORT_PFC_OFFSET), ///< P21_4 / ETHER_ESC / ESC_SYNC1 + IOPORT_PIN_P214_PFC_0B_HD3 = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_4 / PHOSTIF / HD3 + IOPORT_PIN_P214_PFC_0C_MBX_HINT = (0x0CU << IOPORT_PFC_OFFSET), ///< P21_4 / MBXSEM / MBX_HINT + IOPORT_PIN_P215_PFC_00_IRQ6 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_5 / IRQ / IRQ6 + IOPORT_PIN_P215_PFC_01_TRACEDATA4 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_5 / TRACE / TRACEDATA4 + IOPORT_PIN_P215_PFC_02_D4 = (0x02U << IOPORT_PFC_OFFSET), ///< P21_5 / BSC / D4 + IOPORT_PIN_P215_PFC_03_MTIOC7A = (0x03U << IOPORT_PFC_OFFSET), ///< P21_5 / MTU3n / MTIOC7A + IOPORT_PIN_P215_PFC_04_GTIOC16A = (0x04U << IOPORT_PFC_OFFSET), ///< P21_5 / GPTn / GTIOC16A + IOPORT_PIN_P215_PFC_05_CMTW1_TOC1 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_5 / CMTWn / CMTW1_TOC1 + IOPORT_PIN_P215_PFC_06_ADTRG1 = (0x06U << IOPORT_PFC_OFFSET), ///< P21_5 / ADCn / ADTRG1 + IOPORT_PIN_P215_PFC_07_CTS5 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_5 / SCIn / CTS5 + IOPORT_PIN_P215_PFC_08_SPI_MISO0 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_5 / SPIn / SPI_MISO0 + IOPORT_PIN_P215_PFC_09_MCLK2 = (0x09U << IOPORT_PFC_OFFSET), ///< P21_5 / DSMIFn / MCLK2 + IOPORT_PIN_P215_PFC_0B_HD4 = (0x0BU << IOPORT_PFC_OFFSET), ///< P21_5 / PHOSTIF / HD4 + IOPORT_PIN_P216_PFC_00_IRQ9 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_6 / IRQ / IRQ9 + IOPORT_PIN_P216_PFC_01_TRACEDATA5 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_6 / TRACE / TRACEDATA5 + IOPORT_PIN_P216_PFC_02_D5 = (0x02U << IOPORT_PFC_OFFSET), ///< P21_6 / BSC / D5 + IOPORT_PIN_P216_PFC_03_MTIOC7B = (0x03U << IOPORT_PFC_OFFSET), ///< P21_6 / MTU3n / MTIOC7B + IOPORT_PIN_P216_PFC_04_GTIOC16B = (0x04U << IOPORT_PFC_OFFSET), ///< P21_6 / GPTn / GTIOC16B + IOPORT_PIN_P216_PFC_05_CTS0 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_6 / SCIn / CTS0 + IOPORT_PIN_P216_PFC_06_TEND = (0x06U << IOPORT_PFC_OFFSET), ///< P21_6 / DMAC / TEND + IOPORT_PIN_P216_PFC_07_MDAT2 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_6 / DSMIFn / MDAT2 + IOPORT_PIN_P216_PFC_08_HD5 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_6 / PHOSTIF / HD5 + IOPORT_PIN_P217_PFC_00_IRQ10 = (0x00U << IOPORT_PFC_OFFSET), ///< P21_7 / IRQ / IRQ10 + IOPORT_PIN_P217_PFC_01_TRACEDATA6 = (0x01U << IOPORT_PFC_OFFSET), ///< P21_7 / TRACE / TRACEDATA6 + IOPORT_PIN_P217_PFC_02_D6 = (0x02U << IOPORT_PFC_OFFSET), ///< P21_7 / BSC / D6 + IOPORT_PIN_P217_PFC_03_MTIOC7C = (0x03U << IOPORT_PFC_OFFSET), ///< P21_7 / MTU3n / MTIOC7C + IOPORT_PIN_P217_PFC_04_GTIOC17A = (0x04U << IOPORT_PFC_OFFSET), ///< P21_7 / GPTn / GTIOC17A + IOPORT_PIN_P217_PFC_05_DE0 = (0x05U << IOPORT_PFC_OFFSET), ///< P21_7 / SCIn / DE0 + IOPORT_PIN_P217_PFC_06_DREQ = (0x06U << IOPORT_PFC_OFFSET), ///< P21_7 / DMAC / DREQ + IOPORT_PIN_P217_PFC_07_MCLK3 = (0x07U << IOPORT_PFC_OFFSET), ///< P21_7 / DSMIFn / MCLK3 + IOPORT_PIN_P217_PFC_08_HD6 = (0x08U << IOPORT_PFC_OFFSET), ///< P21_7 / PHOSTIF / HD6 + IOPORT_PIN_P220_PFC_00_IRQ15 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_0 / IRQ / IRQ15 + IOPORT_PIN_P220_PFC_01_TRACEDATA7 = (0x01U << IOPORT_PFC_OFFSET), ///< P22_0 / TRACE / TRACEDATA7 + IOPORT_PIN_P220_PFC_02_D7 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_0 / BSC / D7 + IOPORT_PIN_P220_PFC_03_MTIOC7D = (0x03U << IOPORT_PFC_OFFSET), ///< P22_0 / MTU3n / MTIOC7D + IOPORT_PIN_P220_PFC_04_GTIOC17B = (0x04U << IOPORT_PFC_OFFSET), ///< P22_0 / GPTn / GTIOC17B + IOPORT_PIN_P220_PFC_05_DE5 = (0x05U << IOPORT_PFC_OFFSET), ///< P22_0 / SCIn / DE5 + IOPORT_PIN_P220_PFC_06_MDAT3 = (0x06U << IOPORT_PFC_OFFSET), ///< P22_0 / DSMIFn / MDAT3 + IOPORT_PIN_P220_PFC_07_HD7 = (0x07U << IOPORT_PFC_OFFSET), ///< P22_0 / PHOSTIF / HD7 + IOPORT_PIN_P221_PFC_00_TRACECTL = (0x00U << IOPORT_PFC_OFFSET), ///< P22_1 / TRACE / TRACECTL + IOPORT_PIN_P221_PFC_01_D8 = (0x01U << IOPORT_PFC_OFFSET), ///< P22_1 / BSC / D8 + IOPORT_PIN_P221_PFC_02_ESC_LINKACT2 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_1 / ETHER_ESC / ESC_LINKACT2 + IOPORT_PIN_P221_PFC_03_POE4 = (0x03U << IOPORT_PFC_OFFSET), ///< P22_1 / MTU_POE3 / POE4 + IOPORT_PIN_P221_PFC_04_SS4_CTS4_RTS4 = (0x04U << IOPORT_PFC_OFFSET), ///< P22_1 / SCIn / SS4_CTS4_RTS4 + IOPORT_PIN_P221_PFC_05_HD8 = (0x05U << IOPORT_PFC_OFFSET), ///< P22_1 / PHOSTIF / HD8 + IOPORT_PIN_P221_PFC_06_GTETRGB = (0x06U << IOPORT_PFC_OFFSET), ///< P22_1 / GPT_POEG / GTETRGB + IOPORT_PIN_P222_PFC_00_IRQ4 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_2 / IRQ / IRQ4 + IOPORT_PIN_P222_PFC_01_TRACECLK = (0x01U << IOPORT_PFC_OFFSET), ///< P22_2 / TRACE / TRACECLK + IOPORT_PIN_P222_PFC_02_D9 = (0x02U << IOPORT_PFC_OFFSET), ///< P22_2 / BSC / D9 + IOPORT_PIN_P222_PFC_03_MTIOC8C = (0x03U << IOPORT_PFC_OFFSET), ///< P22_2 / MTU3n / MTIOC8C + IOPORT_PIN_P222_PFC_04_GTETRGSA = (0x04U << IOPORT_PFC_OFFSET), ///< P22_2 / GPT_POEG / GTETRGSA + IOPORT_PIN_P222_PFC_05_SPI_SSL12 = (0x05U << IOPORT_PFC_OFFSET), ///< P22_2 / SPIn / SPI_SSL12 + IOPORT_PIN_P222_PFC_07_HD9 = (0x07U << IOPORT_PFC_OFFSET), ///< P22_2 / PHOSTIF / HD9 + IOPORT_PIN_P222_PFC_08_MCLK1 = (0x08U << IOPORT_PFC_OFFSET), ///< P22_2 / DSMIFn / MCLK1 + IOPORT_PIN_P223_PFC_00_D10 = (0x00U << IOPORT_PFC_OFFSET), ///< P22_3 / BSC / D10 + IOPORT_PIN_P223_PFC_01_MTIOC8D = (0x01U << IOPORT_PFC_OFFSET), ///< P22_3 / MTU3n / MTIOC8D + IOPORT_PIN_P223_PFC_02_GTETRGSB = (0x02U << IOPORT_PFC_OFFSET), ///< P22_3 / GPT_POEG / GTETRGSB + IOPORT_PIN_P223_PFC_04_RXD5_SCL5_MISO5 = (0x04U << IOPORT_PFC_OFFSET), ///< P22_3 / SCIn / RXD5_SCL5_MISO5 + IOPORT_PIN_P223_PFC_05_HD10 = (0x05U << IOPORT_PFC_OFFSET), ///< P22_3 / PHOSTIF / HD10 + IOPORT_PIN_P237_PFC_00_ETH2_RXD0 = (0x00U << IOPORT_PFC_OFFSET), ///< P23_7 / ETHER_ETHn / ETH2_RXD0 + IOPORT_PIN_P237_PFC_02_D11 = (0x02U << IOPORT_PFC_OFFSET), ///< P23_7 / BSC / D11 + IOPORT_PIN_P237_PFC_03_BS = (0x03U << IOPORT_PFC_OFFSET), ///< P23_7 / BSC / BS + IOPORT_PIN_P237_PFC_04_MTIOC0A = (0x04U << IOPORT_PFC_OFFSET), ///< P23_7 / MTU3n / MTIOC0A + IOPORT_PIN_P237_PFC_05_GTETRGA = (0x05U << IOPORT_PFC_OFFSET), ///< P23_7 / GPT_POEG / GTETRGA + IOPORT_PIN_P237_PFC_06_SCK1 = (0x06U << IOPORT_PFC_OFFSET), ///< P23_7 / SCIn / SCK1 + IOPORT_PIN_P237_PFC_07_MCLK4 = (0x07U << IOPORT_PFC_OFFSET), ///< P23_7 / DSMIFn / MCLK4 + IOPORT_PIN_P237_PFC_09_HD11 = (0x09U << IOPORT_PFC_OFFSET), ///< P23_7 / PHOSTIF / HD11 + IOPORT_PIN_P240_PFC_00_ETH2_RXD1 = (0x00U << IOPORT_PFC_OFFSET), ///< P24_0 / ETHER_ETHn / ETH2_RXD1 + IOPORT_PIN_P240_PFC_02_D12 = (0x02U << IOPORT_PFC_OFFSET), ///< P24_0 / BSC / D12 + IOPORT_PIN_P240_PFC_03_CKE = (0x03U << IOPORT_PFC_OFFSET), ///< P24_0 / BSC / CKE + IOPORT_PIN_P240_PFC_04_MTIOC0B = (0x04U << IOPORT_PFC_OFFSET), ///< P24_0 / MTU3n / MTIOC0B + IOPORT_PIN_P240_PFC_05_GTETRGB = (0x05U << IOPORT_PFC_OFFSET), ///< P24_0 / GPT_POEG / GTETRGB + IOPORT_PIN_P240_PFC_06_RXD1_SCL1_MISO1 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_0 / SCIn / RXD1_SCL1_MISO1 + IOPORT_PIN_P240_PFC_07_DREQ = (0x07U << IOPORT_PFC_OFFSET), ///< P24_0 / DMAC / DREQ + IOPORT_PIN_P240_PFC_08_MDAT4 = (0x08U << IOPORT_PFC_OFFSET), ///< P24_0 / DSMIFn / MDAT4 + IOPORT_PIN_P240_PFC_0A_HD12 = (0x0AU << IOPORT_PFC_OFFSET), ///< P24_0 / PHOSTIF / HD12 + IOPORT_PIN_P241_PFC_00_ETH2_RXCLK = (0x00U << IOPORT_PFC_OFFSET), ///< P24_1 / ETHER_ETHn / ETH2_RXCLK + IOPORT_PIN_P241_PFC_02_D13 = (0x02U << IOPORT_PFC_OFFSET), ///< P24_1 / BSC / D13 + IOPORT_PIN_P241_PFC_03_CAS = (0x03U << IOPORT_PFC_OFFSET), ///< P24_1 / BSC / CAS + IOPORT_PIN_P241_PFC_04_MTIOC0C = (0x04U << IOPORT_PFC_OFFSET), ///< P24_1 / MTU3n / MTIOC0C + IOPORT_PIN_P241_PFC_05_GTETRGC = (0x05U << IOPORT_PFC_OFFSET), ///< P24_1 / GPT_POEG / GTETRGC + IOPORT_PIN_P241_PFC_06_POE8 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_1 / MTU_POE3 / POE8 + IOPORT_PIN_P241_PFC_07_MCLK5 = (0x07U << IOPORT_PFC_OFFSET), ///< P24_1 / DSMIFn / MCLK5 + IOPORT_PIN_P241_PFC_09_HD13 = (0x09U << IOPORT_PFC_OFFSET), ///< P24_1 / PHOSTIF / HD13 + IOPORT_PIN_P242_PFC_00_ETH2_RXD2 = (0x00U << IOPORT_PFC_OFFSET), ///< P24_2 / ETHER_ETHn / ETH2_RXD2 + IOPORT_PIN_P242_PFC_02_D14 = (0x02U << IOPORT_PFC_OFFSET), ///< P24_2 / BSC / D14 + IOPORT_PIN_P242_PFC_03_RAS = (0x03U << IOPORT_PFC_OFFSET), ///< P24_2 / BSC / RAS + IOPORT_PIN_P242_PFC_04_MTIOC0D = (0x04U << IOPORT_PFC_OFFSET), ///< P24_2 / MTU3n / MTIOC0D + IOPORT_PIN_P242_PFC_05_GTETRGD = (0x05U << IOPORT_PFC_OFFSET), ///< P24_2 / GPT_POEG / GTETRGD + IOPORT_PIN_P242_PFC_06_TXD1_SDA1_MOSI1 = (0x06U << IOPORT_PFC_OFFSET), ///< P24_2 / SCIn / TXD1_SDA1_MOSI1 + IOPORT_PIN_P242_PFC_07_MDAT5 = (0x07U << IOPORT_PFC_OFFSET), ///< P24_2 / DSMIFn / MDAT5 + IOPORT_PIN_P242_PFC_09_HD14 = (0x09U << IOPORT_PFC_OFFSET), ///< P24_2 / PHOSTIF / HD14 + + /** Marks end of enum - used by parameter checking */ + IOPORT_PERIPHERAL_END +} ioport_pin_pfc_t; + +/** Options to configure pin functions */ +typedef enum e_ioport_cfg_options +{ + IOPORT_CFG_PORT_DIRECTION_HIZ = 0x00000000 << IOPORT_PM_OFFSET, ///< Sets the pin direction to Hi-Z + IOPORT_CFG_PORT_DIRECTION_INPUT = 0x00000001 << IOPORT_PM_OFFSET, ///< Sets the pin direction to input (default) + IOPORT_CFG_PORT_DIRECTION_OUTPUT = 0x00000002 << IOPORT_PM_OFFSET, ///< Sets the pin direction to output + IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT = 0x00000003 << IOPORT_PM_OFFSET, ///< Sets the pin direction to output (data is input to input buffer) + IOPORT_CFG_PORT_OUTPUT_LOW = 0x00000000 << IOPORT_P_OFFSET, ///< Sets the pin level to low + IOPORT_CFG_PORT_OUTPUT_HIGH = 0x00000001 << IOPORT_P_OFFSET, ///< Sets the pin level to high + IOPORT_CFG_PORT_GPIO = 0x00000000 << IOPORT_PMC_OFFSET, ///< Enables pin to operate as an GPIO pin + IOPORT_CFG_PORT_PERI = 0x00000001 << IOPORT_PMC_OFFSET, ///< Enables pin to operate as a peripheral pin + IOPORT_CFG_DRIVE_LOW = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to low + IOPORT_CFG_DRIVE_MID = 0x00000001 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to medium + IOPORT_CFG_DRIVE_HIGH = 0x00000002 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to high + IOPORT_CFG_DRIVE_UHIGH = 0x00000003 << IOPORT_DRCTL_OFFSET, ///< Sets pin drive output to ultra high + IOPORT_CFG_PULLUP_DOWN_DISABLE = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Disables the pin's pull-up / pull-down + IOPORT_CFG_PULLUP_ENABLE = 0x00000004 << IOPORT_DRCTL_OFFSET, ///< Enables the pin's internal pull-up + IOPORT_CFG_PULLDOWN_ENABLE = 0x00000008 << IOPORT_DRCTL_OFFSET, ///< Enables the pin's pull-down + IOPORT_CFG_SCHMITT_TRIGGER_DISABLE = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Disables schmitt trigger input + IOPORT_CFG_SCHMITT_TRIGGER_ENABLE = 0x00000010 << IOPORT_DRCTL_OFFSET, ///< Enables schmitt trigger input + IOPORT_CFG_SLEW_RATE_SLOW = 0x00000000 << IOPORT_DRCTL_OFFSET, ///< Sets the slew rate to slow + IOPORT_CFG_SLEW_RATE_FAST = 0x00000020 << IOPORT_DRCTL_OFFSET, ///< Sets the slew rate to fast + IOPORT_CFG_REGION_SAFETY = 0x00000000 << IOPORT_RSELP_OFFSET, ///< Selects safety region + IOPORT_CFG_REGION_NSAFETY = 0x00000001 << IOPORT_RSELP_OFFSET, ///< Selects non safety region + IOPORT_CFG_PIM_TTL = 0x00000020, ///< This macro has been unsupported + IOPORT_CFG_NMOS_ENABLE = 0x00000040, ///< This macro has been unsupported + IOPORT_CFG_PMOS_ENABLE = 0x00000080, ///< This macro has been unsupported + IOPORT_CFG_DRIVE_HS_HIGH = 0x00000800, ///< This macro has been unsupported + IOPORT_CFG_DRIVE_MID_IIC = 0x00000C00, ///< This macro has been unsupported + IOPORT_CFG_EVENT_RISING_EDGE = 0x00001000, ///< This macro has been unsupported + IOPORT_CFG_EVENT_FALLING_EDGE = 0x00002000, ///< This macro has been unsupported + IOPORT_CFG_EVENT_BOTH_EDGES = 0x00003000, ///< This macro has been unsupported + IOPORT_CFG_IRQ_ENABLE = 0x00004000, ///< This macro has been unsupported + IOPORT_CFG_ANALOG_ENABLE = 0x00008000, ///< This macro has been unsupported + IOPORT_CFG_PERIPHERAL_PIN = 0x00010000 ///< This macro has been unsupported +} ioport_cfg_options_t; + +/*============================================== + * POE3 API Overrides + *==============================================*/ + +/** POE3 states. */ +typedef enum e_poe3_state +{ + POE3_STATE_NO_DISABLE_REQUEST = 0, ///< Timer output is not disabled by POE3 + POE3_STATE_POE0_HIGH_IMPEDANCE_REQUEST = 1U, ///< Timer output disabled due to POE0# pin + POE3_STATE_POE4_HIGH_IMPEDANCE_REQUEST = 1U << 1, ///< Timer output disabled due to POE4# pin + POE3_STATE_POE8_HIGH_IMPEDANCE_REQUEST = 1U << 2, ///< Timer output disabled due to POE8# pin + POE3_STATE_POE10_HIGH_IMPEDANCE_REQUEST = 1U << 3, ///< Timer output disabled due to POE10# pin + POE3_STATE_POE11_HIGH_IMPEDANCE_REQUEST = 1U << 4, ///< Timer output disabled due to POE11# pin + + POE3_STATE_SOFTWARE_STOP_DISABLE_REQUEST = 1U << 5, ///< Timer output disabled due to poe3_api_t::outputDisable() + POE3_STATE_OSCILLATION_STOP_DISABLE_REQUEST = 1U << 6, ///< Timer output disabled due to main oscillator stop + + POE3_STATE_DSMIF0_ERROR_REQUEST = 1U << 7, ///< Timer output disabled due to DSMIF0 error + POE3_STATE_DSMIF1_ERROR_REQUEST = 1U << 8, ///< Timer output disabled due to DSMIF1 error + + POE3_STATE_OUTPUT_SHORT_CIRCUIT_1_ERROR_REQUEST = 1U << 9, ///< Timer output disabled due to output short circuit 1 + POE3_STATE_OUTPUT_SHORT_CIRCUIT_2_ERROR_REQUEST = 1U << 10, ///< Timer output disabled due to output short circuit 2 +} poe3_state_t; + +/*============================================== + * POEG API Overrides + *==============================================*/ + +/** POEG states. */ +typedef enum e_poeg_state +{ + POEG_STATE_NO_DISABLE_REQUEST = 0, ///< GPT output is not disabled by POEG + POEG_STATE_PIN_DISABLE_REQUEST = 1U << 0, ///< GPT output disabled due to GTETRG pin level + POEG_STATE_GPT_OR_COMPARATOR_DISABLE_REQUEST = 1U << 1, ///< GPT output disabled due to high speed analog comparator or GPT + POEG_STATE_OSCILLATION_STOP_DISABLE_REQUEST = 1U << 2, ///< GPT output disabled due to main oscillator stop + POEG_STATE_SOFTWARE_STOP_DISABLE_REQUEST = 1U << 3, ///< GPT output disabled due to poeg_api_t::outputDisable() + + /** GPT output disable request active from the GTETRG pin. If a filter is used, this flag represents the state of + * the filtered input. */ + POEG_STATE_PIN_DISABLE_REQUEST_ACTIVE = 1U << 16, + POEG_STATE_DSMIF0_DISABLE_REQUEST = 1U << 24, ///< GPT output disabled due to DSMIF0 error 0 + POEG_STATE_DSMIF1_DISABLE_REQUEST = 1U << 25, ///< GPT output disabled due to DSMIF1 error 0 +} poeg_state_t; + +/** Triggers that will disable GPT output pins. */ +typedef enum e_poeg_trigger +{ + /** Software disable is always supported with POEG. Select this option if no other triggers are used. */ + POEG_TRIGGER_SOFTWARE = 0U, + POEG_TRIGGER_PIN = 1U << 0, ///< Disable GPT output based on GTETRG input level + POEG_TRIGGER_GPT_OUTPUT_LEVEL = 1U << 1, ///< Disable GPT output based on GPT output pin levels + POEG_TRIGGER_OSCILLATION_STOP = 1U << 2, ///< Disable GPT output based on main oscillator stop + POEG_TRIGGER_ACMPHS0 = 1U << 4, ///< Disable GPT output based on ACMPHS0 comparator result + POEG_TRIGGER_ACMPHS1 = 1U << 5, ///< Disable GPT output based on ACMPHS1 comparator result + POEG_TRIGGER_ACMPHS2 = 1U << 6, ///< Disable GPT output based on ACMPHS2 comparator result + POEG_TRIGGER_ACMPHS3 = 1U << 7, ///< Disable GPT output based on ACMPHS3 comparator result + POEG_TRIGGER_ACMPHS4 = 1U << 8, ///< Disable GPT output based on ACMPHS4 comparator result + POEG_TRIGGER_ACMPHS5 = 1U << 9, ///< Disable GPT output based on ACMPHS5 comparator result + + /** The GPT output pins can be disabled when DSMIF error occurs (LLPP only). */ + POEG_TRIGGER_DERR0E = 1U << 22, ///< Permit output disabled by DSMIF0 error detection + POEG_TRIGGER_DERR1E = 1U << 23, ///< Permit output disabled by DSMIF1 error detection +} poeg_trigger_t; + +/*============================================== + * Transfer API Overrides + *==============================================*/ + +/** Events that can trigger a callback function. */ +typedef enum e_transfer_event +{ + TRANSFER_EVENT_TRANSFER_END = 0, ///< Transfer has completed. + TRANSFER_EVENT_TRANSFER_ERROR = 1, ///< Transfer error has occurred. +} transfer_event_t; + +/** Transfer mode describes what will happen when a transfer request occurs. */ +typedef enum e_transfer_mode +{ + /** Normal mode. */ + TRANSFER_MODE_NORMAL = 0, + + /** Block mode. */ + TRANSFER_MODE_BLOCK = 1 +} transfer_mode_t; + +/** Transfer size specifies the size of each individual transfer. */ +typedef enum e_transfer_size +{ + TRANSFER_SIZE_1_BYTE = 0, ///< Each transfer transfers a 8-bit value + TRANSFER_SIZE_2_BYTE = 1, ///< Each transfer transfers a 16-bit value + TRANSFER_SIZE_4_BYTE = 2, ///< Each transfer transfers a 32-bit value + TRANSFER_SIZE_8_BYTE = 3, ///< Each transfer transfers a 64-bit value + TRANSFER_SIZE_16_BYTE = 4, ///< Each transfer transfers a 128-bit value + TRANSFER_SIZE_32_BYTE = 5, ///< Each transfer transfers a 256-bit value + TRANSFER_SIZE_64_BYTE = 6 ///< Each transfer transfers a 512-bit value +} transfer_size_t; + +/** Address mode specifies whether to modify (increment or decrement) pointer after each transfer. */ +typedef enum e_transfer_addr_mode +{ + /** Address pointer is incremented by associated @ref transfer_size_t after each transfer. */ + TRANSFER_ADDR_MODE_INCREMENTED = 0, + + /** Address pointer remains fixed after each transfer. */ + TRANSFER_ADDR_MODE_FIXED = 1 +} transfer_addr_mode_t; + +/** Callback function parameter data. */ +typedef struct st_transfer_callback_args_t +{ + transfer_event_t event; ///< Event code + void const * p_context; ///< Placeholder for user data. Set in transfer_api_t::open function in ::transfer_cfg_t. +} transfer_callback_args_t; + +/** This structure specifies the properties of the transfer. */ +typedef struct st_transfer_info +{ + /** Select what happens to destination pointer after each transfer. */ + transfer_addr_mode_t dest_addr_mode; + + /** Select what happens to source pointer after each transfer. */ + transfer_addr_mode_t src_addr_mode; + + /** Select mode from @ref transfer_mode_t. */ + transfer_mode_t mode; + + /** Source pointer. */ + void const * volatile p_src; + + /** Destination pointer. */ + void * volatile p_dest; + + /** Length of each transfer. */ + volatile uint32_t length; + + /** Select number of source bytes to transfer at once. */ + transfer_size_t src_size; + + /** Select number of destination bytes to transfer at once. */ + transfer_size_t dest_size; + + /** Next1 Register set settings */ + void const * p_next1_src; + void * p_next1_dest; + uint32_t next1_length; +} transfer_info_t; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Exported global functions (to be accessed by other files) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/r_ioport/r_ioport.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/r_ioport/r_ioport.c new file mode 100644 index 00000000000..a192ee17d4d --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/r_ioport/r_ioport.c @@ -0,0 +1,957 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "r_ioport_api.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* "PORT" in ASCII, used to determine if the module is open */ +#define IOPORT_OPEN (0x504F5254U) +#define IOPORT_CLOSED (0x00000000U) + +/* Shift to get port in bsp_io_port_t and bsp_io_port_pin_t enums. */ +#define IOPORT_PRV_PORT_OFFSET (8U) + +#define IOPORT_PRV_PORT_BITS (0xFF00U) +#define IOPORT_PRV_PIN_BITS (0x00FFU) + +#define IOPORT_PRV_8BIT_MASK (0x00FFU) + +/* Added definitions */ +#define IOPORT_PIN_NUM_MUX (8U) +#define IOPORT_REGION_SEL_SAFE (0U) +#define IOPORT_REGION_SEL_NSAFE (1U) +#define IOPORT_RSEL_MASK (0x01U) +#define IOPORT_PM_BIT_MASK (0x0003U) +#define IOPORT_PFC_BIT_MASK (0x0000000FU) +#define IOPORT_DRTCL_BIT_MASK (0x000000FFU) +#define IOPORT_ELC_PEL_MASK (0x80) +#define IOOPRT_ELC_PGC_MASK (0x88) +#define IOPORT_ELC_PEL_PSM_HIGH (0x20) + +/* Switch IOPORT register region either safety or non safety */ +#define IOPORT_PRV_PORT_ADDRESS(region_sel) (region_sel == 1 ? (R_PORT_NSR) : (R_PORT_SR)) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_ioport_cfg_data +{ + uint32_t p_reg : 1; + uint32_t pm_reg : 2; + uint32_t pmc_reg : 1; + uint32_t pfc_reg : 4; + uint32_t drct_reg : 6; + uint32_t rsel_reg : 1; + uint32_t reserved : 17; +} ioport_cfg_data_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +static void r_ioport_pins_config(const ioport_cfg_t * p_cfg); +static void r_ioport_pin_set(bsp_io_port_pin_t pin, ioport_cfg_data_t * p_cfg_data); +static void r_ioport_event_config(const ioport_extend_cfg_t * p_extend_cfg_data); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global Variables + **********************************************************************************************************************/ + +/* IOPort Implementation of IOPort Driver */ +const ioport_api_t g_ioport_on_ioport = +{ + .open = R_IOPORT_Open, + .close = R_IOPORT_Close, + .pinsCfg = R_IOPORT_PinsCfg, + .pinCfg = R_IOPORT_PinCfg, + .pinEventInputRead = R_IOPORT_PinEventInputRead, + .pinEventOutputWrite = R_IOPORT_PinEventOutputWrite, + .pinRead = R_IOPORT_PinRead, + .pinWrite = R_IOPORT_PinWrite, + .portDirectionSet = R_IOPORT_PortDirectionSet, + .portEventInputRead = R_IOPORT_PortEventInputRead, + .portEventOutputWrite = R_IOPORT_PortEventOutputWrite, + .portRead = R_IOPORT_PortRead, + .portWrite = R_IOPORT_PortWrite, +}; + +/*******************************************************************************************************************//** + * @addtogroup IOPORT + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Initializes internal driver data, then calls pin configuration function to configure pins. + * + * @retval FSP_SUCCESS Pin configuration data written to the multiple registers + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_ALREADY_OPEN Module is already open. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Open (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); + FSP_ERROR_RETURN(IOPORT_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Set driver status to open */ + p_instance_ctrl->open = IOPORT_OPEN; + + p_instance_ctrl->p_cfg = p_cfg; + + r_ioport_pins_config(p_cfg); + + r_ioport_event_config(p_cfg->p_extend); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Resets IOPORT registers. Implements @ref ioport_api_t::close + * + * @retval FSP_SUCCESS The IOPORT was successfully uninitialized + * @retval FSP_ERR_ASSERTION p_ctrl was NULL + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_Close (ioport_ctrl_t * const p_ctrl) +{ + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Set state to closed */ + p_instance_ctrl->open = IOPORT_CLOSED; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the functions of multiple pins by loading configuration data into the multiple registers. + * Implements @ref ioport_api_t::pinsCfg. + * + * This function initializes the supplied list of the multiple registers with the supplied values. This data can be generated + * by the Pins tab of the RZ/N2L Configuration editor or manually by the developer. Different pin configurations can be + * loaded for different situations such as low power modes and testing. + * + * @retval FSP_SUCCESS Pin configuration data written to the multiple registers + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinsCfg (ioport_ctrl_t * const p_ctrl, const ioport_cfg_t * p_cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_pin_cfg_data); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + r_ioport_pins_config(p_cfg); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Configures the settings of a pin. Implements @ref ioport_api_t::pinCfg. + * + * @retval FSP_SUCCESS Pin configured + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different pins. + * This function will change the configuration of the pin with the new configuration. For example it is not possible + * with this function to change the drive strength of a pin while leaving all the other pin settings unchanged. To + * achieve this the original settings with the required change will need to be written using this function. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinCfg (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_BSP_PinAccessEnable(); + + r_ioport_pin_set(pin, (ioport_cfg_data_t *) &cfg); + + R_BSP_PinAccessDisable(); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the level on a pin. Implements @ref ioport_api_t::pinRead. + * + * The level for the specifed pin will be reterned by PINm register. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different pins. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + *p_pin_value = (bsp_io_level_t) R_BSP_FastPinRead(R_BSP_IoRegionGet(pin), pin); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value on an IO port. Implements @ref ioport_api_t::portRead. + * + * The specified port will be read, and the levels for all the pins will be returned by PINm register. + * Each bit in the returned value corresponds to a pin on the port. For example, bit 7 corresponds + * to pin 7, bit 6 to pin 6, and so on. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_port_value) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_port_value); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_PORT_COMMON_Type * p_ioport_regs; + ioport_size_t safe_value; + ioport_size_t nsafe_value; + + /* Get port number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET; + + /* Get the RSELP register value */ + ioport_size_t rselp_value = (ioport_size_t) R_PTADR->RSELP[port_num]; + + /* Get the port register address in non safety region */ + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Read the specified port states in non safety region */ + nsafe_value = (ioport_size_t) (p_ioport_regs->PIN[port_num] & rselp_value); + + /* Get the port register address in safety region */ + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE); + + /* Read the specified port states in safety region */ + safe_value = (ioport_size_t) (p_ioport_regs->PIN[port_num] & ~(rselp_value)); + + /* Read the specified port states */ + *p_port_value = nsafe_value | safe_value; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Writes to multiple pins on a port. Implements @ref ioport_api_t::portWrite. + * + * The output value will be written to the specified port. Each bit in the value parameter corresponds to a bit + * on the port. For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * Each bit in the mask parameter corresponds to a pin on the port. + * + * Only the bits with the corresponding bit in the mask value set will be updated. + * For example, value = 0x00FF, mask = 0x0003 results in only bits 0 and 1 being updated. + * + * @retval FSP_SUCCESS Port written to + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointerd + * + * @note This function is re-entrant for different ports. This function makes use of the Pm register to atomically + * modify the levels on the specified pins on a port. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_PORT_COMMON_Type * p_ioport_regs; + ioport_size_t temp_value; + ioport_size_t write_mask; + + /* mask value: lower word is valid, upper word is invalid */ + mask &= IOPORT_PRV_8BIT_MASK; + + /* Get port number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET; + + /* Get the RSELP register value */ + ioport_size_t rselp_value = R_PTADR->RSELP[port_num]; + + /* Set value to non safety region register */ + write_mask = rselp_value & mask; + if (write_mask) + { + /* Get the port register address */ + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Output data store of the specified pins sets to low output */ + temp_value = (ioport_size_t) (p_ioport_regs->P[port_num] & (~write_mask)); + + /* Write output data to P register of the specified pins */ + p_ioport_regs->P[port_num] = (uint8_t) (temp_value | (value & write_mask)); + } + + /* Set value to safety region register */ + write_mask = (ioport_size_t) ((~rselp_value) & mask); + if (write_mask) + { + /* Get the port register address */ + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE); + + /* Output data store of the specified pins sets to low output */ + temp_value = (ioport_size_t) (p_ioport_regs->P[port_num] & (~write_mask)); + + /* Write output data to P register of the specified pins */ + p_ioport_regs->P[port_num] = (uint8_t) (temp_value | (value & write_mask)); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets a pin's output either high or low. Implements @ref ioport_api_t::pinWrite. + * + * @retval FSP_SUCCESS Pin written to + * @retval FSP_ERR_INVALID_ARGUMENT The pin and/or level not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opene + * @retval FSP_ERR_ASSERTION NULL pointerd + * + * @note This function is re-entrant for different pins. This function makes use of the Pm register to atomically + * modify the level on the specified pin on a port. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level) +{ +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(level <= BSP_IO_LEVEL_HIGH, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_PORT_COMMON_Type * p_ioport_regs; + + /* Get port and pin number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin) >> IOPORT_PRV_PORT_OFFSET; + uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin); + + /* Get the port register address */ + p_ioport_regs = (IOPORT_PRV_PORT_ADDRESS(((uint16_t) (R_PTADR->RSELP[port_num] >> pin_num) & + IOPORT_RSEL_MASK))); + + /* Set output level to P register of the specified pin */ + if (BSP_IO_LEVEL_LOW == level) + { + p_ioport_regs->P[port_num] &= (uint8_t) (~(1U << pin_num)); + } + else + { + p_ioport_regs->P[port_num] |= (uint8_t) (1U << pin_num); + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Sets the direction of individual pins on a port. Implements @ref ioport_api_t::portDirectionSet(). + * + * Multiple pins on a port can be set to inputs or outputs at once. + * Each bit in the mask parameter corresponds to a pin on the port. For example, bit 7 corresponds to + * pin 7, bit 6 to pin 6, and so on. If a mask bit is set to 1 then the corresponding pin will be changed to + * an input or an output as specified by the direction values. If a mask bit is set to 0 then the direction of + * the pin will not be changed. + * + * @retval FSP_SUCCESS Port direction updated + * @retval FSP_ERR_INVALID_ARGUMENT The port and/or mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + * + * @note This function is re-entrant for different ports. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortDirectionSet (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t direction_values, + ioport_size_t mask) +{ + uint32_t pin_num; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask > (uint16_t) 0, FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* mask value: lower word is valid, upper word is invalid */ + mask &= IOPORT_PRV_8BIT_MASK; + + for (pin_num = 0U; pin_num < IOPORT_PIN_NUM_MUX; pin_num++) + { + if (mask & (1U << pin_num)) + { + /* Get port number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) port) >> IOPORT_PRV_PORT_OFFSET; + + /* Get the port register address */ + R_PORT_COMMON_Type * p_ioport_regs = + IOPORT_PRV_PORT_ADDRESS(((uint16_t) (R_PTADR->RSELP[port_num] >> pin_num) & + IOPORT_RSEL_MASK)); + + /* Set */ + uint16_t set_bits = (uint16_t) (direction_values & (IOPORT_PM_BIT_MASK << (pin_num * 2U))); + + /* Set the direction value */ + uint16_t temp_value = (uint16_t) (p_ioport_regs->PM[port_num] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U))); + p_ioport_regs->PM[port_num] = temp_value | set_bits; + } + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data. Implements @ref ioport_api_t::portEventInputRead(). + * + * The event input data for the port will be read. Each bit in the returned value corresponds to a pin on the port. + * For example, bit 7 corresponds to pin 7, bit 6 to pin 6, and so on. + * + * The port event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Port read + * @retval FSP_ERR_INVALID_ARGUMENT Port not a valid ELC port + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_t port, ioport_size_t * p_event_data) +{ + uint8_t portgroup = 0U; + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_event_data); + FSP_ERROR_RETURN((port == BSP_IO_PORT_16) || (port == BSP_IO_PORT_18), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + const ioport_extend_cfg_t * elc_cfg = p_instance_ctrl->p_cfg->p_extend; + + /* Get register address */ + R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Get port group number for the specified port */ + if (BSP_IO_PORT_16 == port) + { + portgroup = 0U; + } + else if (BSP_IO_PORT_18 == port) + { + portgroup = 1U; + } + else + { + /* Do Nothing */ + } + + /* Read current value of buffer value from ELC_PDBF register for the specified port group */ + *p_event_data = + (uint16_t) (p_ioport_regs->ELC_PDBF[portgroup].BY & elc_cfg->port_group_input_cfg[portgroup].pin_select); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reads the value of the event input data of a specific pin. Implements @ref ioport_api_t::pinEventInputRead. + * + * The pin event data is captured in response to a trigger from the ELC. This function enables this data to be read. + * Using the event system allows the captured data to be stored when it occurs and then read back at a later time. + * + * @retval FSP_SUCCESS Pin read + * @retval FSP_ERR_ASSERTION NULL pointer + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_INVALID_ARGUMENT Port is not valid ELC PORT. + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventInputRead (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t * p_pin_event) +{ + uint8_t portgroup = 0U; + uint8_t portvalue; + uint8_t mask; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_pin_event); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((port_number == BSP_IO_PORT_16 >> IOPORT_PRV_PORT_OFFSET) || + (port_number == BSP_IO_PORT_18 >> IOPORT_PRV_PORT_OFFSET), + FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + /* Get port and pin number */ + uint32_t port_num = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin); + uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin); + + /* Get register address */ + R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Get port group number for the specified port */ + if (BSP_IO_PORT_16 == port_num) + { + portgroup = 0U; + } + else if (BSP_IO_PORT_18 == port_num) + { + portgroup = 1U; + } + else + { + /* Do Nothing */ + } + + /* Read current value of buffer value from ELC_PDBF register for the specified port group */ + portvalue = p_ioport_regs->ELC_PDBF[portgroup].BY; + mask = (uint8_t) (1U << pin_num); + + if ((portvalue & mask) == mask) + { + *p_pin_event = BSP_IO_LEVEL_HIGH; + } + else + { + *p_pin_event = BSP_IO_LEVEL_LOW; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function writes the set and reset event output data for a port. Implements + * @ref ioport_api_t::portEventOutputWrite. + * + * Using the event system enables a port state to be stored by this function in advance of being output on the port. + * The output to the port will occur when the ELC event occurs. + * + * The input value will be written to the specified port when an ELC event configured for that port occurs. + * Each bit in the value parameter corresponds to a bit on the port. For example, bit 7 corresponds to pin 7, + * bit 6 to pin 6, and so on. Each bit in the mask parameter corresponds to a pin on the port. + * + * @retval FSP_SUCCESS Port event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Mask not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PortEventOutputWrite (ioport_ctrl_t * const p_ctrl, + bsp_io_port_t port, + ioport_size_t event_data, + ioport_size_t mask_value) +{ + uint8_t portgroup = 0U; + ioport_size_t temp_value; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(mask_value > (ioport_size_t) 0, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((port == BSP_IO_PORT_16) || (port == BSP_IO_PORT_18), FSP_ERR_INVALID_ARGUMENT); +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + + R_BSP_PinAccessEnable(); // Unlock Register Write Protection + + /* Get register address */ + R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Get port group number for the specified port */ + if (BSP_IO_PORT_16 == port) + { + portgroup = 0U; + } + else if (BSP_IO_PORT_18 == port) + { + portgroup = 1U; + } + else + { + /* Do Nothing */ + } + + temp_value = p_ioport_regs->ELC_PDBF[portgroup].BY; + temp_value &= (ioport_size_t) (~mask_value); + + p_ioport_regs->ELC_PDBF[portgroup].BY = (uint8_t) (temp_value | event_data); + + R_BSP_PinAccessDisable(); // Lock Register Write Protection + + return FSP_SUCCESS; +} + +/**********************************************************************************************************************//** + * This function writes the event output data value to a pin. Implements @ref ioport_api_t::pinEventOutputWrite. + * + * Using the event system enables a pin state to be stored by this function in advance of being output on the pin. + * The output to the pin will occur when the ELC event occurs. + * + * @retval FSP_SUCCESS Pin event data written + * @retval FSP_ERR_INVALID_ARGUMENT Port or Pin or value not valid + * @retval FSP_ERR_NOT_OPEN The module has not been opened + * @retval FSP_ERR_ASSERTION NULL pointer + **********************************************************************************************************************/ +fsp_err_t R_IOPORT_PinEventOutputWrite (ioport_ctrl_t * const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value) +{ + uint8_t singleport = 0U; + uint8_t cnt; + ioport_instance_ctrl_t * p_instance_ctrl = (ioport_instance_ctrl_t *) p_ctrl; + +#if (1 == IOPORT_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_instance_ctrl); + FSP_ERROR_RETURN(IOPORT_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((pin_value == BSP_IO_LEVEL_HIGH) || (pin_value == BSP_IO_LEVEL_LOW), FSP_ERR_INVALID_ARGUMENT); + uint32_t port_number = pin >> IOPORT_PRV_PORT_OFFSET; + FSP_ERROR_RETURN((port_number == BSP_IO_PORT_16 >> IOPORT_PRV_PORT_OFFSET) || + (port_number == BSP_IO_PORT_18 >> IOPORT_PRV_PORT_OFFSET), + FSP_ERR_INVALID_ARGUMENT); +#endif + + const ioport_extend_cfg_t * elc_cfg = p_instance_ctrl->p_cfg->p_extend; + + R_BSP_PinAccessEnable(); // Unlock Register Write Protection + + /* Get register address */ + R_PORT_COMMON_Type * p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + for (cnt = 0; cnt < IOPORT_SINGLE_PORT_NUM; cnt++) + { + if ((bsp_io_port_pin_t) elc_cfg->single_port_cfg[cnt].port_num == pin) + { + singleport = cnt; + } + } + + if (BSP_IO_LEVEL_HIGH == pin_value) + { + p_ioport_regs->ELC_PEL[singleport] |= (uint8_t) IOPORT_ELC_PEL_PSM_HIGH; + } + else + { + p_ioport_regs->ELC_PEL[singleport] &= (uint8_t) (~IOPORT_ELC_PEL_PSM_HIGH); + } + + R_BSP_PinAccessDisable(); // Lock Register Write Protection + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup IOPORT) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures pins. + * + * @param[in] p_cfg Pin configuration data + **********************************************************************************************************************/ +void r_ioport_pins_config (const ioport_cfg_t * p_cfg) +{ + uint16_t pin_count; + ioport_cfg_t * p_pin_data; + + p_pin_data = (ioport_cfg_t *) p_cfg; + + R_BSP_PinAccessEnable(); // Unlock Register Write Protection + + for (pin_count = 0U; pin_count < p_pin_data->number_of_pins; pin_count++) + { + r_ioport_pin_set(p_pin_data->p_pin_cfg_data[pin_count].pin, + (ioport_cfg_data_t *) &p_pin_data->p_pin_cfg_data[pin_count].pin_cfg); + } + + R_BSP_PinAccessDisable(); // Lock Register Write Protection +} + +/*******************************************************************************************************************//** + * Writes to the specified pin's multiple registers + * + * @param[in] pin Pin to write parameter data for + * @param[in] p_cfg_data Value to be written to the multiple registers + * + **********************************************************************************************************************/ +static void r_ioport_pin_set (bsp_io_port_pin_t pin, ioport_cfg_data_t * p_cfg_data) +{ + R_PORT_COMMON_Type * p_ioport_regs; + uint32_t temp_value; + + /* Get port and pin number */ + uint32_t port = (IOPORT_PRV_PORT_BITS & (ioport_size_t) pin) >> IOPORT_PRV_PORT_OFFSET; + uint32_t pin_num = (IOPORT_PRV_PIN_BITS & (ioport_size_t) pin); + + /* Setting for Safety region or Non safety region */ + if (p_cfg_data->rsel_reg == 1U) // Setting for Non safety region + { + R_PTADR->RSELP[port] |= (uint8_t) (1U << pin_num); + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + } + else // Setting for Safety region + { + R_PTADR->RSELP[port] &= (uint8_t) (~(1U << pin_num)); + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_SAFE); + } + + /* Setting DRCTL register */ + if (3U >= pin_num) + { + temp_value = p_ioport_regs->DRCTL[port].L & ~(IOPORT_DRTCL_BIT_MASK << (pin_num * 8U)); + p_ioport_regs->DRCTL[port].L = temp_value | (uint32_t) (p_cfg_data->drct_reg << (pin_num * 8U)); + } + else if (3U < pin_num) + { + temp_value = p_ioport_regs->DRCTL[port].H & ~(IOPORT_DRTCL_BIT_MASK << ((pin_num - 4U) * 8U)); + p_ioport_regs->DRCTL[port].H = temp_value | (uint32_t) (p_cfg_data->drct_reg << ((pin_num - 4U) * 8U)); + } + else + { + /* Do Nothing */ + } + + /* Setting for GPIO or peripheral */ + if (1U == p_cfg_data->pmc_reg) // Setting for peripheral + { + temp_value = p_ioport_regs->PFC[port] & ~(IOPORT_PFC_BIT_MASK << (pin_num * 4U)); + p_ioport_regs->PFC[port] = temp_value | (uint32_t) (p_cfg_data->pfc_reg << (pin_num * 4U)); // Setting PFC register + + /* Setting peripheral for port mode */ + p_ioport_regs->PMC[port] |= (uint8_t) (p_cfg_data->pmc_reg << pin_num); // Setting PMC register + } + else // Setting for GPIO + { + /* Setting GPIO for port mode */ + p_ioport_regs->PMC[port] &= (uint8_t) (~(1U << pin_num)); // Setting PMC register + + /* Setting for input or output */ + if (1U == p_cfg_data->pm_reg) // Setting for input + { + /* Setting PM register. */ + /* 01b: Input */ + temp_value = (uint32_t) (p_ioport_regs->PM[port] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U))); + p_ioport_regs->PM[port] = (uint16_t) (temp_value | (uint32_t) (1U << (pin_num * 2U))); + } + else if (1U < p_cfg_data->pm_reg) // Setting for two kinds of Output + { + /* Setting P register */ + if (0U == p_cfg_data->p_reg) // Low output setting + { + p_ioport_regs->P[port] &= (uint8_t) (~(1U << pin_num)); + } + else if (1U == p_cfg_data->p_reg) // High output setting + { + p_ioport_regs->P[port] |= (uint8_t) (1U << pin_num); + } + else + { + /* Do Nothing */ + } + + /* Setting PM register. */ + /* 10b: Output */ + /* 11b: Output(output data is input to input buffer) */ + temp_value = (uint32_t) (p_ioport_regs->PM[port] & ~(IOPORT_PM_BIT_MASK << (pin_num * 2U))); + p_ioport_regs->PM[port] = (uint16_t) (temp_value | (uint32_t) (p_cfg_data->pm_reg << (pin_num * 2U))); + } + else + { + /* Do Nothing */ + } + } +} + +/*******************************************************************************************************************//** + * Writes to the specified pin's multiple registers to generate event link function + * + * @param[in] p_extend_cfg_data Value to be written to the multiple registers + * + **********************************************************************************************************************/ +static void r_ioport_event_config (const ioport_extend_cfg_t * p_extend_cfg_data) +{ + uint8_t event_num; + uint8_t temp_value = 0x00; + uint8_t single_enable = 0x00; + uint8_t group_enable = 0x00; + R_PORT_COMMON_Type * p_ioport_regs; + ioport_extend_cfg_t * ex_cfg; + + ex_cfg = (ioport_extend_cfg_t *) p_extend_cfg_data; + + R_BSP_PinAccessEnable(); // Unlock Register Write Protection + + /* Get register address */ + p_ioport_regs = IOPORT_PRV_PORT_ADDRESS(IOPORT_REGION_SEL_NSAFE); + + /* Single port configuration */ + for (event_num = 0U; event_num < IOPORT_SINGLE_PORT_NUM; event_num++) + { + uint8_t port = + (uint8_t) ((ex_cfg->single_port_cfg[event_num].port_num & IOPORT_PRV_PORT_BITS) >> IOPORT_PRV_PORT_OFFSET); + uint8_t pin_num = (uint8_t) ex_cfg->single_port_cfg[event_num].port_num & IOPORT_PRV_PIN_BITS; + + temp_value = p_ioport_regs->ELC_PEL[event_num] & IOPORT_ELC_PEL_MASK; + + /* Port selection */ + if ((BSP_IO_PORT_16 >> IOPORT_PRV_PORT_OFFSET) == port) + { + temp_value |= 1U << 3; + } + else if ((BSP_IO_PORT_18 >> IOPORT_PRV_PORT_OFFSET) == port) + { + temp_value |= 1U << 4; + } + else + { + /* Do Nothing */ + } + + temp_value |= pin_num; // Pin number setting + + /* When the pin specified as single input port, Set edge detection */ + /* When the pin specified as single output port, Set output operation */ + if (IOPORT_EVENT_DIRECTION_INPUT == ex_cfg->single_port_cfg[event_num].direction) + { + temp_value |= (uint8_t) (ex_cfg->single_port_cfg[event_num].edge_detection << 5); // Edge detection + + /* Edge detection enable */ + p_ioport_regs->ELC_DPTC |= (uint8_t) (1U << event_num); + } + else + { + temp_value |= (uint8_t) (ex_cfg->single_port_cfg[event_num].operation << 5); // Output operation + } + + /* Set to ELC port setting register */ + p_ioport_regs->ELC_PEL[event_num] = temp_value; + + /* Single port event link function enable */ + if (IOPORT_EVENT_CONTROL_ENABLE == ex_cfg->single_port_cfg[event_num].event_control) + { + single_enable |= (uint8_t) (1U << event_num); + } + } + + /* Port group configuration */ + for (event_num = 0U; event_num < IOPORT_PORT_GROUP_NUM; event_num++) + { + /* Pin selection */ + uint8_t group_pin = ex_cfg->port_group_input_cfg[event_num].pin_select | + ex_cfg->port_group_output_cfg[event_num].pin_select; + p_ioport_regs->ELC_PGR[event_num] = group_pin; + + if (IOPORT_EVENT_CONTROL_ENABLE == ex_cfg->port_group_input_cfg[event_num].event_control) + { + /* Input port group control */ + temp_value = p_ioport_regs->ELC_PGC[event_num] & IOOPRT_ELC_PGC_MASK; + temp_value |= ex_cfg->port_group_input_cfg[event_num].edge_detection; // Edge detection + temp_value |= (uint8_t) (ex_cfg->port_group_input_cfg[event_num].overwrite_control << 2U); // Overwrite setting + + /* Buffer register initialization */ + p_ioport_regs->ELC_PDBF[event_num].BY = ex_cfg->port_group_input_cfg[event_num].buffer_init_value; + + /* Input port group event link function enable */ + group_enable |= (uint8_t) (1U << event_num); + } + + /* Output port group operation */ + temp_value |= (uint8_t) (ex_cfg->port_group_output_cfg[event_num].operation << 4); + + /* Set to port group control register */ + p_ioport_regs->ELC_PGC[event_num] = temp_value; + } + + /* Set to ELC port event control register */ + p_ioport_regs->ELC_ELSR2 = (uint8_t) ((single_enable << 4) | (group_enable << 2)); + + R_BSP_PinAccessDisable(); // Lock Register Write Protection +} diff --git a/bsp/renesas/rzn2l_rsk/rzn/fsp/src/r_sci_uart/r_sci_uart.c b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/r_sci_uart/r_sci_uart.c new file mode 100644 index 00000000000..dff83ec6b74 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn/fsp/src/r_sci_uart/r_sci_uart.c @@ -0,0 +1,1934 @@ +/*********************************************************************************************************************** + * Copyright [2020-2024] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics Corporation and/or its affiliates and may only + * be used with products of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. + * Renesas products are sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for + * the selection and use of Renesas products and Renesas assumes no liability. No license, express or implied, to any + * intellectual property right is granted by Renesas. This software is protected under all applicable laws, including + * copyright laws. Renesas reserves the right to change or discontinue this software and/or this documentation. + * THE SOFTWARE AND DOCUMENTATION IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND + * TO THE FULLEST EXTENT PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, + * INCLUDING WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE + * SOFTWARE OR DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. + * TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR + * DOCUMENTATION (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, + * INCLUDING, WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY + * LOST PROFITS, OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE + * POSSIBILITY OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_sci_uart.h" +#include + +#if SCI_UART_CFG_DMAC_SUPPORTED + #include "r_dmac.h" +#endif + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ +#ifndef SCI_UART_CFG_RX_ENABLE + #define SCI_UART_CFG_RX_ENABLE 1 +#endif +#ifndef SCI_UART_CFG_TX_ENABLE + #define SCI_UART_CFG_TX_ENABLE 1 +#endif + +/** Number of divisors in the data table used for baud rate calculation. */ +#define SCI_UART_NUM_DIVISORS_ASYNC (13U) + +/** Valid range of values for the modulation duty register is 128 - 256 (256 = modulation disabled). */ +#define SCI_UART_MDDR_MIN (128U) +#define SCI_UART_MDDR_MAX (256U) + +/** The bit rate register is 8-bits, so the maximum value is 255. */ +#define SCI_UART_BRR_MAX (255U) + +/** No limit to the number of bytes to read or write if DMAC is not used. */ +#define SCI_UART_MAX_READ_WRITE_NO_DMAC (0xFFFFFFFFU) + +/** Mask of invalid data bits in 9-bit mode. */ +#define SCI_UART_ALIGN_2_BYTES (0x1U) + +/** Clock frequency 96MHz. */ +#define SCI_UART_CLOCK_96MHZ (96000000) + +/** "SCIU" in ASCII. Used to determine if the control block is open. */ +#define SCI_UART_OPEN (0x53434955U) + +#define SCI_UART_BRR_DEFAULT_VALUE (0xFFU) +#define SCI_UART_MDDR_DEFAULT_VALUE (0xFFU) +#define SCI_UART_FCR_DEFAULT_VALUE (0x1F1F0000) + +#define SCI_UART_CCR0_DEFAULT_VALUE (0x00000000) +#define SCI_UART_CCR1_DEFAULT_VALUE (0x00000010) +#define SCI_UART_CCR2_DEFAULT_VALUE (0xFF00FF04) +#define SCI_UART_CCR3_DEFAULT_VALUE (0x00001203) +#define SCI_UART_CCR4_DEFAULT_VALUE (0x00000000) + +#define SCI_UART_CFCLR_ALL_FLAG_CLEAR (0xBD070010) +#define SCI_UART_FFCLR_ALL_FLAG_CLEAR (0x00000001) + +/** SCI CCR0 register bit masks */ +#define SCI_UART_CCR0_IDSEL_MASK (0x00000400) +#define SCI_UART_CCR0_TEIE_MASK (0x00200000) +#define SCI_UART_CCR0_RE_MASK (0x00000001) +#define SCI_UART_CCR0_TE_MASK (0x00000010) +#define SCI_UART_CCR0_RIE_MASK (0x00010000) +#define SCI_UART_CCR0_TIE_MASK (0x00100000) + +/** SCI CCR1 register bit offsets */ +#define SCI_UART_CCR1_CTSE_OFFSET (0U) +#define SCI_UART_CCR1_SPB2DT_BIT (4U) +#define SCI_UART_CCR1_OUTPUT_ENABLE_MASK (0x00000020) +#define SCI_UART_CCR1_PARITY_OFFSET (8U) +#define SCI_UART_CCR1_PARITY_MASK (0x00000300U) +#define SCI_UART_CCR1_FLOW_CTSRTS_MASK (0x00000003U) +#define SCI_UART_CCR1_NFCS_OFFSET (24U) +#define SCI_UART_CCR1_NFCS_VALUE_MASK (0x07U) +#define SCI_UART_CCR1_NFEN_OFFSET (28U) + +/** SCI CCR2 register bit offsets */ +#define SCI_UART_CCR2_BRME_OFFSET (16U) +#define SCI_UART_CCR2_ABCSE_OFFSET (6U) +#define SCI_UART_CCR2_ABCS_OFFSET (5U) +#define SCI_UART_CCR2_BDGM_OFFSET (4U) +#define SCI_UART_CCR2_CKS_OFFSET (20U) +#define SCI_UART_CCR2_CKS_VALUE_MASK (0x03U) ///< CKS: 2 bits +#define SCI_UART_CCR2_BRR_OFFSET (8U) +#define SCI_UART_CCR2_BRR_VALUE_MASK (0xFFU) ///< BRR: 8bits +#define SCI_UART_CCR2_MDDR_OFFSET (24U) +#define SCI_UART_CCR2_MDDR_VALUE_MASK (0xFFU) ///< MDDR: 8bits + +#define SCI_UART_CCR2_BAUD_SETTING_MASK ((1U << SCI_UART_CCR2_BRME_OFFSET) | \ + (1U << SCI_UART_CCR2_ABCSE_OFFSET) | \ + (1U << SCI_UART_CCR2_ABCS_OFFSET) | \ + (1U << SCI_UART_CCR2_BDGM_OFFSET) | \ + (SCI_UART_CCR2_CKS_VALUE_MASK << SCI_UART_CCR2_CKS_OFFSET) | \ + (SCI_UART_CCR2_BRR_VALUE_MASK << SCI_UART_CCR2_BRR_OFFSET) | \ + (SCI_UART_CCR2_MDDR_VALUE_MASK << SCI_UART_CCR2_MDDR_OFFSET)) + +/** SCI CCR3 register bit masks */ +#define SCI_UART_CCR3_BPEN_OFFSET (7U) +#define SCI_UART_CCR3_CHR_OFFSET (8U) +#define SCI_UART_CCR3_STP_OFFSET (14U) +#define SCI_UART_CCR3_RxDSEL_OFFSET (15U) +#define SCI_UART_CCR3_FM_OFFSET (20U) +#define SCI_UART_CCR3_CKE_OFFSET (24U) +#define SCI_UART_CCR3_CKE_MASK (0x03000000U) +#define SCI_UART_CCR3_CKE_VALUE_MASK (0x03U) + +/** SCI CSR register receiver error bit masks */ +#define SCI_UART_CSR_ORER_MASK (0x01000000) +#define SCI_UART_CSR_FER_MASK (0x10000000) +#define SCI_UART_CSR_PER_MASK (0x08000000) +#define SCI_UART_RCVR_ERR_MASK (SCI_UART_CSR_ORER_MASK | SCI_UART_CSR_FER_MASK | SCI_UART_CSR_PER_MASK) + +/** SCI CFCLR register receiver clear error bit masks */ +#define SCI_UART_CFCLR_ORERC_MASK (0x01000000) +#define SCI_UART_CFCLR_FERC_MASK (0x10000000) +#define SCI_UART_CFCLE_PERC_MASK (0x08000000) +#define SCI_UART_RCVR_ERRCLR_MASK (SCI_UART_CFCLR_ORERC_MASK | SCI_UART_CFCLR_FERC_MASK | \ + SCI_UART_CFCLE_PERC_MASK) + +#define SCI_REG_SIZE (R_SCI1_BASE - R_SCI0_BASE) + +#define SCI_UART_INVALID_8BIT_PARAM (0xFFU) +#define SCI_UART_INVALID_16BIT_PARAM (0xFFFFU) + +#define SCI_UART_TDR_9BIT_MASK (0x1FFU) + +#define SCI_UART_FCR_TRIGGER_MASK (0xF) +#define SCI_UART_FCR_RSTRG_OFFSET (24U) +#define SCI_UART_FCR_RTRG_OFFSET (16U) +#define SCI_UART_FCR_TTRG_OFFSET (8U) +#define SCI_UART_FCR_TTRG_DMAC_VALUE (0x0F) +#define SCI_UART_FCR_RESET_TX_RX (0x00808000) + +#define SCI_UART_DMAC_MAX_TRANSFER (0xFFFFFFFFU) + +/*********************************************************************************************************************** + * Private constants + **********************************************************************************************************************/ +static const int32_t SCI_UART_100_PERCENT_X_1000 = 100000; +static const int32_t SCI_UART_MDDR_DIVISOR = 256; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) +static const uint32_t SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 = 15000; +#endif + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +typedef struct st_baud_setting_const_t +{ + uint8_t bgdm : 1; /**< BGDM value to get divisor */ + uint8_t abcs : 1; /**< ABCS value to get divisor */ + uint8_t abcse : 1; /**< ABCSE value to get divisor */ + uint8_t cks : 2; /**< CKS value to get divisor (CKS = N) */ +} baud_setting_const_t; + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + +static fsp_err_t r_sci_read_write_param_check(sci_uart_instance_ctrl_t const * const p_instance_ctrl, + uint8_t const * const addr, + uint32_t const bytes); + +#endif + +static void r_sci_uart_config_set(sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg); + +#if SCI_UART_CFG_DMAC_SUPPORTED +static fsp_err_t r_sci_uart_transfer_configure(sci_uart_instance_ctrl_t * const p_instance_ctrl, + transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t address); + +static fsp_err_t r_sci_uart_transfer_open(sci_uart_instance_ctrl_t * const p_instance_ctrl, + uart_cfg_t const * const p_cfg); + +static void r_sci_uart_transfer_close(sci_uart_instance_ctrl_t * p_instance_ctrl); + +#endif + +static void r_sci_uart_baud_set(R_SCI0_Type * p_sci_reg, sci_baud_setting_t const * const p_baud_setting); +static void r_sci_uart_call_callback(sci_uart_instance_ctrl_t * p_instance_ctrl, uint32_t data, uart_event_t event); + +#if SCI_UART_CFG_FIFO_SUPPORT +static void r_sci_uart_fifo_cfg(sci_uart_instance_ctrl_t * const p_instance_ctrl); + +#endif + +static void r_sci_irq_cfg(sci_uart_instance_ctrl_t * const p_instance_ctrl, uint8_t const ipl, IRQn_Type const p_irq); + +static void r_sci_irqs_cfg(sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg); + +#if (SCI_UART_CFG_TX_ENABLE) +void r_sci_uart_write_no_transfer(sci_uart_instance_ctrl_t * const p_instance_ctrl); + +#endif + +#if (SCI_UART_CFG_RX_ENABLE) +void r_sci_uart_rxi_read_no_transfer(sci_uart_instance_ctrl_t * const p_instance_ctrl); + +static void sci_uart_rxi_common(sci_uart_instance_ctrl_t * p_instance_ctrl); + +void sci_uart_rxi_isr(void); + +void sci_uart_rx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl); + +void r_sci_uart_read_data(sci_uart_instance_ctrl_t * const p_instance_ctrl, uint32_t * const p_data); + +void sci_uart_eri_isr(void); + +#endif + +#if (SCI_UART_CFG_TX_ENABLE) +static void sci_uart_txi_common(sci_uart_instance_ctrl_t * p_instance_ctrl); + +void sci_uart_txi_isr(void); + +void sci_uart_tx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl); + +void sci_uart_tei_isr(void); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/** Name of module used by error logger macro */ +#if BSP_CFG_ERROR_LOG != 0 +static const char g_module_name[] = "sci_uart"; +#endif + +/** Baud rate divisor information (UART mode) */ +static const baud_setting_const_t g_async_baud[SCI_UART_NUM_DIVISORS_ASYNC] = +{ + {0U, 0U, 1U, 0U}, /* BGDM, ABCS, ABCSE, n */ + {1U, 1U, 0U, 0U}, + {1U, 0U, 0U, 0U}, + {0U, 0U, 1U, 1U}, + {0U, 0U, 0U, 0U}, + {1U, 0U, 0U, 1U}, + {0U, 0U, 1U, 2U}, + {0U, 0U, 0U, 1U}, + {1U, 0U, 0U, 2U}, + {0U, 0U, 1U, 3U}, + {0U, 0U, 0U, 2U}, + {1U, 0U, 0U, 3U}, + {0U, 0U, 0U, 3U} +}; + +static const uint16_t g_div_coefficient[SCI_UART_NUM_DIVISORS_ASYNC] = +{ + 6U, + 8U, + 16U, + 24U, + 32U, + 64U, + 96U, + 128U, + 256U, + 384U, + 512U, + 1024U, + 2048U, +}; + +/** UART on SCI HAL API mapping for UART interface */ +const uart_api_t g_uart_on_sci = +{ + .open = R_SCI_UART_Open, + .close = R_SCI_UART_Close, + .write = R_SCI_UART_Write, + .read = R_SCI_UART_Read, + .infoGet = R_SCI_UART_InfoGet, + .baudSet = R_SCI_UART_BaudSet, + .communicationAbort = R_SCI_UART_Abort, + .callbackSet = R_SCI_UART_CallbackSet, + .readStop = R_SCI_UART_ReadStop, +}; + +/*******************************************************************************************************************//** + * @addtogroup SCI_UART + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configures the UART driver based on the input configurations. If reception is enabled at compile time, reception is + * enabled at the end of this function. Implements @ref uart_api_t::open + * + * @retval FSP_SUCCESS Channel opened successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The requested channel does not exist on this MCU. + * @retval FSP_ERR_ALREADY_OPEN Control block has already been opened or channel is being used by another + * instance. Call close() then open() to reconfigure. + * @retval FSP_ERR_INVALID_ARGUMENT Invalid input parameter. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Open (uart_ctrl_t * const p_ctrl, uart_cfg_t const * const p_cfg) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + + /* Check parameters. */ + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_cfg); + FSP_ASSERT(p_cfg->p_callback); + FSP_ASSERT(p_cfg->p_extend); + FSP_ASSERT(((sci_uart_extended_cfg_t *) p_cfg->p_extend)->p_baud_setting); + FSP_ERROR_RETURN(SCI_UART_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); + + /* Make sure this channel exists. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_CHANNELS & (1U << p_cfg->channel), FSP_ERR_IP_CHANNEL_NOT_PRESENT); + + #if SCI_UART_CFG_DMAC_SUPPORTED + #if (SCI_UART_CFG_RX_ENABLE) + if (NULL != p_cfg->p_transfer_rx) + { + /* DMAC activation is not available for safety channel. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_SAFETY_CHANNEL != p_cfg->channel, FSP_ERR_INVALID_ARGUMENT); + } + #endif + #if (SCI_UART_CFG_TX_ENABLE) + if (NULL != p_cfg->p_transfer_tx) + { + /* DMAC activation is not available for safety channel. */ + FSP_ERROR_RETURN(BSP_FEATURE_SCI_SAFETY_CHANNEL != p_cfg->channel, FSP_ERR_INVALID_ARGUMENT); + } + #endif + #endif + + if (SCI_UART_FLOW_CONTROL_CTSRTS == ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control) + { + FSP_ERROR_RETURN( + ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM, + FSP_ERR_INVALID_ARGUMENT); + } + + if (SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS == ((sci_uart_extended_cfg_t *) p_cfg->p_extend)->flow_control) + { + FSP_ERROR_RETURN((0U != (((1U << (p_cfg->channel)) & BSP_FEATURE_SCI_UART_CSTPEN_CHANNELS))), + FSP_ERR_INVALID_ARGUMENT); + } + + FSP_ASSERT(UART_PARITY_ZERO != p_cfg->parity); + FSP_ASSERT(p_cfg->rxi_irq >= 0); + FSP_ASSERT(p_cfg->txi_irq >= 0); + FSP_ASSERT(p_cfg->tei_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); +#endif + + p_instance_ctrl->fifo_depth = 0U; +#if SCI_UART_CFG_FIFO_SUPPORT + + /* Check if the channel supports fifo */ + if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS & (1U << p_cfg->channel)) + { + p_instance_ctrl->fifo_depth = BSP_FEATURE_SCI_UART_FIFO_DEPTH; + } +#endif + + p_instance_ctrl->p_cfg = p_cfg; + + p_instance_ctrl->p_callback = p_cfg->p_callback; + p_instance_ctrl->p_context = p_cfg->p_context; + p_instance_ctrl->p_callback_memory = NULL; + sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_cfg->p_extend; + + p_instance_ctrl->data_bytes = 1U; + if (UART_DATA_BITS_9 == p_cfg->data_bits) + { + p_instance_ctrl->data_bytes = 2U; + } + + /* Configure the interrupts. */ + r_sci_irqs_cfg(p_instance_ctrl, p_cfg); + + /* Enable the SCI channel and reset the registers to their initial state. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET); + R_BSP_MODULE_START(FSP_IP_SCI, p_cfg->channel); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET); + + if (p_cfg->channel != BSP_FEATURE_SCI_SAFETY_CHANNEL) + { + /* Non-Safety Peripheral */ + p_instance_ctrl->p_reg = + (R_SCI0_Type *) ((uint32_t) R_SCI0 + (p_cfg->channel * ((uint32_t) R_SCI1 - (uint32_t) R_SCI0))); + } + else + { + /* Safety Peripheral */ + p_instance_ctrl->p_reg = (R_SCI0_Type *) BSP_FEATURE_SCI_SAFETY_CHANNEL_BASE_ADDRESS; + } + +#if SCI_UART_CFG_DMAC_SUPPORTED + + /* Configure the transfer interface for transmission and reception if provided. */ + fsp_err_t err = r_sci_uart_transfer_open(p_instance_ctrl, p_cfg); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + p_instance_ctrl->p_reg->CCR0 = SCI_UART_CCR0_DEFAULT_VALUE; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 0); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 0); + p_instance_ctrl->p_reg->CCR1 = SCI_UART_CCR1_DEFAULT_VALUE; + p_instance_ctrl->p_reg->CCR2 = SCI_UART_CCR2_DEFAULT_VALUE; + p_instance_ctrl->p_reg->CCR3 = SCI_UART_CCR3_DEFAULT_VALUE; + p_instance_ctrl->p_reg->CCR4 = SCI_UART_CCR4_DEFAULT_VALUE; + + /* Set the UART configuration settings provided in ::uart_cfg_t and ::sci_uart_extended_cfg_t. */ + r_sci_uart_config_set(p_instance_ctrl, p_cfg); + + p_instance_ctrl->p_reg->CFCLR = SCI_UART_CFCLR_ALL_FLAG_CLEAR; + +#if SCI_UART_CFG_FIFO_SUPPORT + p_instance_ctrl->p_reg->FFCLR = SCI_UART_FFCLR_ALL_FLAG_CLEAR; +#endif + + p_instance_ctrl->p_tx_src = NULL; + p_instance_ctrl->tx_src_bytes = 0U; + p_instance_ctrl->p_rx_dest = NULL; + p_instance_ctrl->rx_dest_bytes = 0; + + uint32_t ccr0 = SCI_UART_CCR0_IDSEL_MASK; +#if (SCI_UART_CFG_RX_ENABLE) + + /* If reception is enabled at build time, enable reception. */ + /* NOTE: Transmitter and its interrupt are enabled in R_SCI_UART_Write(). */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq); + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->eri_irq); + + ccr0 |= (SCI_UART_CCR0_RIE_MASK | SCI_UART_CCR0_RE_MASK); +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->txi_irq); + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->tei_irq); + + ccr0 |= SCI_UART_CCR0_TE_MASK; +#endif + p_instance_ctrl->p_reg->CCR0 = ccr0; + + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 1); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 1); + + /* Set flow control pins. */ + p_instance_ctrl->flow_pin = p_extend->flow_control_pin; + +#if SCI_UART_CFG_FLOW_CONTROL_SUPPORT + if (p_instance_ctrl->flow_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM) + { + R_BSP_PinAccessEnable(); + R_BSP_PinClear(R_BSP_IoRegionGet(p_instance_ctrl->flow_pin), p_instance_ctrl->flow_pin); + R_BSP_PinAccessDisable(); + } +#endif + + p_instance_ctrl->open = SCI_UART_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Aborts any in progress transfers. Disables interrupts, receiver, and transmitter. Closes lower level transfer + * drivers if used. Removes power. Implements @ref uart_api_t::close + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Close (uart_ctrl_t * const p_ctrl) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Mark the channel not open so other APIs cannot use it. */ + p_instance_ctrl->open = 0U; + + /* Disable interrupts, receiver, and transmitter. Disable baud clock output.*/ + p_instance_ctrl->p_reg->CCR0 = SCI_UART_CCR0_DEFAULT_VALUE; + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 0); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 0); + p_instance_ctrl->p_reg->CCR3 &= ~(SCI_UART_CCR3_CKE_MASK); + +#if (SCI_UART_CFG_RX_ENABLE) + + /* If reception is enabled at build time, disable reception irqs. */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->eri_irq); +#endif +#if (SCI_UART_CFG_TX_ENABLE) + + /* If transmission is enabled at build time, disable transmission irqs. */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->tei_irq); +#endif +#if SCI_UART_CFG_DMAC_SUPPORTED + + /* Close the lower level transfer instances. */ + r_sci_uart_transfer_close(p_instance_ctrl); +#endif + + /* Remove power to the channel. */ + /* Disable the clock to the SCI channel. */ + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET); + R_BSP_MODULE_STOP(FSP_IP_SCI, p_instance_ctrl->p_cfg->channel); + R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Receives user specified number of bytes into destination buffer pointer. Implements @ref uart_api_t::read + * + * @retval FSP_SUCCESS Data reception successfully ends. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Destination address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A previous read operation is still in progress. + * @retval FSP_ERR_UNSUPPORTED SCI_UART_CFG_RX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reconfigure + * + * @note If 9-bit data length is specified at R_SCI_UART_Open call, p_dest must be aligned 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Read (uart_ctrl_t * const p_ctrl, uint8_t * const p_dest, uint32_t const bytes) +{ +#if (SCI_UART_CFG_RX_ENABLE) + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_SUCCESS; + + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sci_read_write_param_check(p_instance_ctrl, p_dest, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_instance_ctrl->rx_dest_bytes, FSP_ERR_IN_USE); + #endif + + #if SCI_UART_CFG_DMAC_SUPPORTED + + /* Configure transfer instance to receive the requested number of bytes if transfer is used for reception. */ + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + p_instance_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = (void *) p_dest; + p_instance_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->length = bytes; + + /* Disable the corresponding IRQ when transferring using DMAC. */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->rxi_irq); + + err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->reconfigure(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl, + p_instance_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Save the destination address and size for use in rxi_isr. */ + p_instance_ctrl->p_rx_dest = p_dest; + p_instance_ctrl->rx_dest_bytes = bytes; + + return err; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_dest); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Transmits user specified number of bytes from the source buffer pointer. Implements @ref uart_api_t::write + * + * @retval FSP_SUCCESS Data transmission finished successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_INVALID_ARGUMENT Source address or data size is not valid for 9-bit mode. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_IN_USE A UART transmission is in progress + * @retval FSP_ERR_UNSUPPORTED SCI_UART_CFG_TX_ENABLE is set to 0 + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::reconfigure + * + * @note If 9-bit data length is specified at R_SCI_UART_Open call, p_src must be aligned on a 16-bit boundary. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Write (uart_ctrl_t * const p_ctrl, uint8_t const * const p_src, uint32_t const bytes) +{ +#if (SCI_UART_CFG_TX_ENABLE) + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + #if SCI_UART_CFG_PARAM_CHECKING_ENABLE || SCI_UART_CFG_DMAC_SUPPORTED + fsp_err_t err = FSP_SUCCESS; + #endif + + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + err = r_sci_read_write_param_check(p_instance_ctrl, p_src, bytes); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + FSP_ERROR_RETURN(0U == p_instance_ctrl->tx_src_bytes, FSP_ERR_IN_USE); + #endif + + /* Transmit interrupts must be disabled to start with. */ + p_instance_ctrl->p_reg->CCR0 &= (uint32_t) ~(SCI_UART_CCR0_TIE_MASK | SCI_UART_CCR0_TEIE_MASK); + + p_instance_ctrl->tx_src_bytes = bytes - p_instance_ctrl->data_bytes; + p_instance_ctrl->p_tx_src = p_src + p_instance_ctrl->data_bytes; + + #if SCI_UART_CFG_DMAC_SUPPORTED + + /* If a transfer instance is used for transmission, reset the transfer instance to transmit the requested + * data. */ + if ((NULL != p_instance_ctrl->p_cfg->p_transfer_tx) && p_instance_ctrl->tx_src_bytes) + { + uint32_t num_transfers = p_instance_ctrl->tx_src_bytes; + p_instance_ctrl->tx_src_bytes = 0U; + + p_instance_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = (void const *) p_instance_ctrl->p_tx_src; + p_instance_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length = num_transfers; + + /* Disable the corresponding IRQ when transferring using DMAC. */ + R_BSP_IrqDisable(p_instance_ctrl->p_cfg->txi_irq); + + err = p_instance_ctrl->p_cfg->p_transfer_tx->p_api->reconfigure(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl, + p_instance_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + /* Trigger a TXI interrupt. This triggers the transfer instance or a TXI interrupt if the transfer instance is + * not used. */ + p_instance_ctrl->p_reg->CCR0 |= SCI_UART_CCR0_TIE_MASK; + + /* The first byte is sent from this function to trigger the first TXI event. This + * method is used instead of setting TE and TIE at the same time as recommended in the hardware manual to avoid + * the one frame delay that occurs when the TE bit is set. */ + if (2U == p_instance_ctrl->data_bytes) + { + p_instance_ctrl->p_reg->TDR_b.TDAT = (*(uint16_t *) (p_src)) & SCI_UART_TDR_9BIT_MASK; + } + else + { + p_instance_ctrl->p_reg->TDR_b.TDAT = *(p_src); + } + + #if SCI_UART_CFG_FIFO_SUPPORT + + /* The behavior of the TDRE flag differs between when FIFO is used and not used. + * When using FIFO, clear the flag manually to detect the interrupt at the edge. */ + p_instance_ctrl->p_reg->CFCLR_b.TDREC = 1; + #endif + + return FSP_SUCCESS; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); + FSP_PARAMETER_NOT_USED(p_src); + FSP_PARAMETER_NOT_USED(bytes); + + return FSP_ERR_UNSUPPORTED; +#endif +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements uart_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_CallbackSet (uart_ctrl_t * const p_ctrl, + void ( * p_callback)(uart_callback_args_t *), + void const * const p_context, + uart_callback_args_t * const p_callback_memory) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Store callback and context */ + p_instance_ctrl->p_callback = p_callback; + p_instance_ctrl->p_context = p_context; + p_instance_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Updates the baud rate using the clock selected in Open. p_baud_setting is a pointer to a sci_baud_setting_t structure. + * Implements @ref uart_api_t::baudSet + * + * @warning This terminates any in-progress transmission. + * + * @retval FSP_SUCCESS Baud rate was successfully changed. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL or the UART is not configured to use the + * internal clock. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_BaudSet (uart_ctrl_t * const p_ctrl, void const * const p_baud_setting) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + /* Verify that the On-Chip baud rate generator is currently selected. */ + FSP_ASSERT((p_instance_ctrl->p_reg->CCR3_b.CKE & 0x2) == 0U); +#endif + + /* Save CCR0 configurations except transmit interrupts. Resuming transmission after reconfiguring baud settings is + * not supported. */ + uint32_t preserved_ccr0 = p_instance_ctrl->p_reg->CCR0 & (uint32_t) ~(R_SCI0_CCR0_TIE_Msk | R_SCI0_CCR0_TEIE_Msk); + + /* Disables transmitter and receiver. This terminates any in-progress transmission. */ + p_instance_ctrl->p_reg->CCR0 = preserved_ccr0 & + (uint32_t) ~(R_SCI0_CCR0_TE_Msk | R_SCI0_CCR0_RE_Msk | R_SCI0_CCR0_RIE_Msk); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.RE, 0); + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CCR0_b.TE, 0); + p_instance_ctrl->p_tx_src = NULL; + + /* Apply new baud rate register settings. */ + r_sci_uart_baud_set(p_instance_ctrl->p_reg, p_baud_setting); + + /* Restore all settings except transmit interrupts. */ + p_instance_ctrl->p_reg->CCR0 = preserved_ccr0; + FSP_HARDWARE_REGISTER_WAIT((p_instance_ctrl->p_reg->CCR0 & R_SCI0_CCR0_RE_Msk), + (preserved_ccr0 & R_SCI0_CCR0_RE_Msk)); + FSP_HARDWARE_REGISTER_WAIT((p_instance_ctrl->p_reg->CCR0 & R_SCI0_CCR0_TE_Msk), + (preserved_ccr0 & R_SCI0_CCR0_TE_Msk)); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides the driver information, including the maximum number of bytes that can be received or transmitted at a time. + * Implements @ref uart_api_t::infoGet + * + * @retval FSP_SUCCESS Information stored in provided p_info. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_InfoGet (uart_ctrl_t * const p_ctrl, uart_info_t * const p_info) +{ +#if SCI_UART_CFG_PARAM_CHECKING_ENABLE || SCI_UART_CFG_DMAC_SUPPORTED + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; +#else + FSP_PARAMETER_NOT_USED(p_ctrl); +#endif + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(p_info); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_info->read_bytes_max = SCI_UART_MAX_READ_WRITE_NO_DMAC; + p_info->write_bytes_max = SCI_UART_MAX_READ_WRITE_NO_DMAC; + +#if (SCI_UART_CFG_RX_ENABLE) + + /* Store number of bytes that can be read at a time. */ + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + p_info->read_bytes_max = SCI_UART_DMAC_MAX_TRANSFER; + } + #endif +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + + /* Store number of bytes that can be written at a time. */ + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx) + { + p_info->write_bytes_max = SCI_UART_DMAC_MAX_TRANSFER; + } + #endif +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing transfer. Transmission is aborted after the current character is transmitted. + * Reception is still enabled after abort(). Any characters received after abort() and before the transfer + * is reset in the next call to read(), will arrive via the callback function with event UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::communicationAbort + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_Abort (uart_ctrl_t * const p_ctrl, uart_dir_t communication_to_abort) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + fsp_err_t err = FSP_ERR_UNSUPPORTED; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + if (UART_DIR_TX & communication_to_abort) + { + err = FSP_SUCCESS; + p_instance_ctrl->p_reg->CCR0 &= (uint32_t) ~(SCI_UART_CCR0_TIE_MASK | SCI_UART_CCR0_TEIE_MASK); + + /* Make sure no transmission is in progress. */ + FSP_HARDWARE_REGISTER_WAIT(p_instance_ctrl->p_reg->CSR_b.TEND, 1U); + + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx) + { + err = p_instance_ctrl->p_cfg->p_transfer_tx->p_api->disable(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl); + + /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->txi_irq); + } + #endif + + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_instance_ctrl->fifo_depth) + { + /* Reset the transmit fifo */ + p_instance_ctrl->p_reg->FCR_b.TFRST = 1U; + } + #endif + p_instance_ctrl->tx_src_bytes = 0U; + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } +#endif +#if (SCI_UART_CFG_RX_ENABLE) + if (UART_DIR_RX & communication_to_abort) + { + err = FSP_SUCCESS; + + p_instance_ctrl->rx_dest_bytes = 0U; + + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->disable(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl); + + /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq); + } + #endif + + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_instance_ctrl->fifo_depth) + { + /* Reset the receive fifo */ + p_instance_ctrl->p_reg->FCR_b.RFRST = 1U; + } + #endif + } +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Provides API to abort ongoing read. Reception is still enabled after abort(). Any characters received after abort() + * and before the transfer is reset in the next call to read(), will arrive via the callback function with event + * UART_EVENT_RX_CHAR. + * Implements @ref uart_api_t::readStop + * + * @retval FSP_SUCCESS UART transaction aborted successfully. + * @retval FSP_ERR_ASSERTION Pointer to UART control block or remaining_bytes is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_UNSUPPORTED The requested Abort direction is unsupported. + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::disable + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_ReadStop (uart_ctrl_t * const p_ctrl, uint32_t * remaining_bytes) +{ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) p_ctrl; + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(remaining_bytes); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if (SCI_UART_CFG_RX_ENABLE) + *remaining_bytes = p_instance_ctrl->rx_dest_bytes; + p_instance_ctrl->rx_dest_bytes = 0U; + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + fsp_err_t err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->disable( + p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq); + + transfer_properties_t transfer_info; + err = p_instance_ctrl->p_cfg->p_transfer_rx->p_api->infoGet(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl, + &transfer_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + *remaining_bytes = transfer_info.transfer_length_remaining; + } + #endif + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_instance_ctrl->fifo_depth) + { + /* Reset the receive fifo */ + p_instance_ctrl->p_reg->FCR_b.RFRST = 1U; + } + #endif +#else + + return FSP_ERR_UNSUPPORTED; +#endif + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates baud rate register settings. Evaluates and determines the best possible settings set to the baud rate + * related registers. + * + * @param[in] p_baud_target Baudrate calculation configuration. + * @param[in] clock_source Clock source (PCLKM or SCInASYNCCLK) used for baudrate calculation. + * @param[out] p_baud_setting Baud setting information stored here if successful + * + * @retval FSP_SUCCESS Baud rate is set successfully + * @retval FSP_ERR_ASSERTION Null pointer + * @retval FSP_ERR_INVALID_ARGUMENT Baud rate is '0', error in calculated baud rate is larger than requested + * max error, or requested max error in baud rate is larger than 15%. + * Clock source frequency could not be get. + **********************************************************************************************************************/ +fsp_err_t R_SCI_UART_BaudCalculate (sci_uart_baud_calculation_t const * const p_baud_target, + sci_uart_clock_source_t clock_source, + sci_baud_setting_t * const p_baud_setting) +{ +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_baud_target); + FSP_ASSERT(p_baud_setting); + FSP_ERROR_RETURN(SCI_UART_MAX_BAUD_RATE_ERROR_X_1000 >= p_baud_target->baud_rate_error_x_1000, + FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((0U != p_baud_target->baudrate), FSP_ERR_INVALID_ARGUMENT); +#endif + + p_baud_setting->baudrate_bits_b.brr = SCI_UART_BRR_MAX; + p_baud_setting->baudrate_bits_b.brme = 0U; + p_baud_setting->baudrate_bits_b.mddr = SCI_UART_MDDR_MIN; + + /* Find the best BRR (bit rate register) value. + * In table g_async_baud, divisor values are stored for BGDM, ABCS, ABCSE and N values. Each set of divisors + * is tried, and the settings with the lowest bit rate error are stored. The formula to calculate BRR is as + * follows and it must be 255 or less: + * BRR = (PCLK / (div_coefficient * baud)) - 1 + */ + int32_t hit_bit_err = SCI_UART_100_PERCENT_X_1000; + uint32_t hit_mddr = 0U; + uint32_t divisor = 0U; + + uint32_t freq_hz = 0U; + if (SCI_UART_CLOCK_SOURCE_PCLKM == clock_source) + { + freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKM); + } + else + { + freq_hz = + R_FSP_SystemClockHzGet((fsp_priv_clock_t) ((uint8_t) FSP_PRIV_CLOCK_PCLKSCI0 + (uint8_t) clock_source)); + } + + FSP_ERROR_RETURN(0U != freq_hz, FSP_ERR_INVALID_ARGUMENT); + + for (uint32_t select_16_base_clk_cycles = 0U; + select_16_base_clk_cycles <= 1U && (hit_bit_err > ((int32_t) p_baud_target->baud_rate_error_x_1000)); + select_16_base_clk_cycles++) + { + for (uint32_t i = 0U; i < SCI_UART_NUM_DIVISORS_ASYNC; i++) + { + /* if select_16_base_clk_cycles == true: Skip this calculation for divisors that are not acheivable with 16 base clk cycles per bit. + * if select_16_base_clk_cycles == false: Skip this calculation for divisors that are only acheivable without 16 base clk cycles per bit. + */ + if (((uint8_t) select_16_base_clk_cycles) ^ (g_async_baud[i].abcs | g_async_baud[i].abcse)) + { + continue; + } + + divisor = (uint32_t) g_div_coefficient[i] * p_baud_target->baudrate; + uint32_t temp_brr = freq_hz / divisor; + + if (temp_brr <= (SCI_UART_BRR_MAX + 1U)) + { + while (temp_brr > 0U) + { + temp_brr -= 1U; + + /* Calculate the bit rate error. The formula is as follows: + * bit rate error[%] = {(PCLK / (baud * div_coefficient * (BRR + 1)) - 1} x 100 + * calculates bit rate error[%] to three decimal places + */ + int32_t err_divisor = (int32_t) (divisor * (temp_brr + 1U)); + + /* Promoting to 64 bits for calculation, but the final value can never be more than 32 bits, as + * described below, so this cast is safe. + * 1. (temp_brr + 1) can be off by an upper limit of 1 due to rounding from the calculation: + * freq_hz / divisor, or: + * freq_hz / divisor <= (temp_brr + 1) < (freq_hz / divisor) + 1 + * 2. Solving for err_divisor: + * freq_hz <= err_divisor < freq_hz + divisor + * 3. Solving for bit_err: + * 0 >= bit_err >= (freq_hz * 100000 / (freq_hz + divisor)) - 100000 + * 4. freq_hz >= divisor (or temp_brr would be -1 and we would never enter this while loop), so: + * 0 >= bit_err >= 100000 / freq_hz - 100000 + * 5. Larger frequencies yield larger bit errors (absolute value). As the frequency grows, + * the bit_err approaches -100000, so: + * 0 >= bit_err >= -100000 + * 6. bit_err is between -100000 and 0. This entire range fits in an int32_t type, so the cast + * to (int32_t) is safe. + */ + int32_t bit_err = (int32_t) (((((int64_t) freq_hz) * SCI_UART_100_PERCENT_X_1000) / + err_divisor) - SCI_UART_100_PERCENT_X_1000); + + uint32_t mddr = 0U; + if (p_baud_target->bitrate_modulation) + { + /* Calculate the MDDR (M) value if bit rate modulation is enabled, + * The formula to calculate MBBR (from the M and N relationship given in the hardware manual) is as follows + * and it must be between 128 and 256. + * MDDR = ((div_coefficient * baud * 256) * (BRR + 1)) / PCLK */ + mddr = (uint32_t) err_divisor / (freq_hz / SCI_UART_MDDR_MAX); + + /* The maximum value that could result from the calculation above is 256, which is a valid MDDR + * value, so only the lower bound is checked. */ + if (mddr < SCI_UART_MDDR_MIN) + { + break; + } + + /* Adjust bit rate error for bit rate modulation. The following formula is used: + * bit rate error [%] = ((bit rate error [%, no modulation] + 100) * MDDR / 256) - 100 + */ + bit_err = (((bit_err + SCI_UART_100_PERCENT_X_1000) * (int32_t) mddr) / + SCI_UART_MDDR_DIVISOR) - SCI_UART_100_PERCENT_X_1000; + } + + /* Take the absolute value of the bit rate error. */ + if (bit_err < 0) + { + bit_err = -bit_err; + } + + /* If the absolute value of the bit rate error is less than the previous lowest absolute value of + * bit rate error, then store these settings as the best value. + */ + if (bit_err < hit_bit_err) + { + p_baud_setting->baudrate_bits_b.bgdm = g_async_baud[i].bgdm; + p_baud_setting->baudrate_bits_b.abcs = g_async_baud[i].abcs; + p_baud_setting->baudrate_bits_b.abcse = g_async_baud[i].abcse; + p_baud_setting->baudrate_bits_b.cks = g_async_baud[i].cks; + p_baud_setting->baudrate_bits_b.brr = (uint8_t) temp_brr; + hit_bit_err = bit_err; + hit_mddr = mddr; + } + + if (p_baud_target->bitrate_modulation) + { + p_baud_setting->baudrate_bits_b.brme = 1U; + p_baud_setting->baudrate_bits_b.mddr = (uint8_t) hit_mddr; + } + else + { + break; + } + } + } + } + } + + /* Return an error if the percent error is larger than the maximum percent error allowed for this instance */ + FSP_ERROR_RETURN((hit_bit_err <= (int32_t) p_baud_target->baud_rate_error_x_1000), FSP_ERR_INVALID_ARGUMENT); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SCI_UART) + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Private Functions + **********************************************************************************************************************/ + +#if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + +/*******************************************************************************************************************//** + * Parameter error check function for read/write. + * + * @param[in] p_instance_ctrl Pointer to the control block for the channel + * @param[in] addr Pointer to the buffer + * @param[in] bytes Number of bytes to read or write + * + * @retval FSP_SUCCESS No parameter error found + * @retval FSP_ERR_NOT_OPEN The control block has not been opened + * @retval FSP_ERR_ASSERTION Pointer to UART control block or configuration structure is NULL + * @retval FSP_ERR_INVALID_ARGUMENT Address is not aligned to 2-byte boundary or size is the odd number when the data + * length is 9-bit + **********************************************************************************************************************/ +static fsp_err_t r_sci_read_write_param_check (sci_uart_instance_ctrl_t const * const p_instance_ctrl, + uint8_t const * const addr, + uint32_t const bytes) +{ + FSP_ASSERT(p_instance_ctrl); + FSP_ASSERT(addr); + FSP_ASSERT(0U != bytes); + FSP_ERROR_RETURN(SCI_UART_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + + if (2U == p_instance_ctrl->data_bytes) + { + /* Do not allow odd buffer address if data length is 9 bits. */ + FSP_ERROR_RETURN((0U == ((uint32_t) addr & SCI_UART_ALIGN_2_BYTES)), FSP_ERR_INVALID_ARGUMENT); + + /* Do not allow odd number of data bytes if data length is 9 bits. */ + FSP_ERROR_RETURN(0U == (bytes % 2U), FSP_ERR_INVALID_ARGUMENT); + } + + return FSP_SUCCESS; +} + +#endif + +#if SCI_UART_CFG_DMAC_SUPPORTED + +/*******************************************************************************************************************//** + * Subroutine to apply common UART transfer settings. + * + * @param[in] p_cfg Pointer to UART specific configuration structure + * @param[in] p_transfer Pointer to transfer instance to configure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer + **********************************************************************************************************************/ +static fsp_err_t r_sci_uart_transfer_configure (sci_uart_instance_ctrl_t * const p_instance_ctrl, + transfer_instance_t const * p_transfer, + uint32_t * p_transfer_reg, + uint32_t sci_buffer_address) +{ + /* Configure the transfer instance, if enabled. */ + #if (SCI_UART_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(NULL != p_transfer->p_api); + FSP_ASSERT(NULL != p_transfer->p_ctrl); + FSP_ASSERT(NULL != p_transfer->p_cfg); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_info); + FSP_ASSERT(NULL != p_transfer->p_cfg->p_extend); + #endif + + /* Casting for compatibility with 7 or 8 bit mode. */ + *p_transfer_reg = sci_buffer_address; + + transfer_info_t * p_info = p_transfer->p_cfg->p_info; + if (UART_DATA_BITS_9 == p_instance_ctrl->p_cfg->data_bits) + { + p_info->src_size = TRANSFER_SIZE_2_BYTE; + p_info->dest_size = TRANSFER_SIZE_2_BYTE; + } + else + { + p_info->src_size = TRANSFER_SIZE_1_BYTE; + p_info->dest_size = TRANSFER_SIZE_1_BYTE; + } + + fsp_err_t err = p_transfer->p_api->open(p_transfer->p_ctrl, p_transfer->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + return FSP_SUCCESS; +} + +#endif + +#if SCI_UART_CFG_DMAC_SUPPORTED + +/*******************************************************************************************************************//** + * Configures UART related transfer drivers (if enabled). + * + * @param[in] p_instance_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + * + * @retval FSP_SUCCESS UART transfer drivers successfully configured + * @retval FSP_ERR_ASSERTION Invalid pointer or required interrupt not enabled in vector table + * + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible + * return codes. This function calls: + * * @ref transfer_api_t::open + **********************************************************************************************************************/ +static fsp_err_t r_sci_uart_transfer_open (sci_uart_instance_ctrl_t * const p_instance_ctrl, + uart_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + #if (SCI_UART_CFG_RX_ENABLE) + + /* If a transfer instance is used for reception, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_rx) + { + transfer_info_t * p_info = p_cfg->p_transfer_rx->p_cfg->p_info; + + p_info->mode = TRANSFER_MODE_NORMAL; + p_info->src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_info->dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + + err = + r_sci_uart_transfer_configure(p_instance_ctrl, + p_cfg->p_transfer_rx, + (uint32_t *) &p_info->p_src, + (uint32_t) &(p_instance_ctrl->p_reg->RDR)); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + #if (SCI_UART_CFG_TX_ENABLE) + + /* If a transfer instance is used for transmission, apply UART specific settings and open the transfer instance. */ + if (NULL != p_cfg->p_transfer_tx) + { + transfer_info_t * p_info = p_cfg->p_transfer_tx->p_cfg->p_info; + + p_info->mode = TRANSFER_MODE_NORMAL; + p_info->src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_info->dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + + err = + r_sci_uart_transfer_configure(p_instance_ctrl, + p_cfg->p_transfer_tx, + (uint32_t *) &p_info->p_dest, + (uint32_t) &p_instance_ctrl->p_reg->TDR); + + #if (SCI_UART_CFG_RX_ENABLE) + if ((err != FSP_SUCCESS) && (NULL != p_cfg->p_transfer_rx)) + { + p_cfg->p_transfer_rx->p_api->close(p_cfg->p_transfer_rx->p_ctrl); + } + #endif + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + #endif + + return err; +} + +#endif + +/*******************************************************************************************************************//** + * Configures UART related registers based on user configurations. + * + * @param[in] p_instance_ctrl Pointer to UART control structure + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sci_uart_config_set (sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg) +{ + /* CCR3 register setting. */ + uint32_t ccr3 = SCI_UART_CCR3_DEFAULT_VALUE; + +#if SCI_UART_CFG_FIFO_SUPPORT + ccr3 |= (1U << SCI_UART_CCR3_FM_OFFSET); + + /* Configure FIFO related registers. */ + r_sci_uart_fifo_cfg(p_instance_ctrl); +#else + + /* If fifo support is disabled and the current channel supports fifo make sure it's disabled. */ + if (BSP_FEATURE_SCI_UART_FIFO_CHANNELS & (1U << p_cfg->channel)) + { + p_instance_ctrl->p_reg->FCR = SCI_UART_FCR_DEFAULT_VALUE; + } +#endif + + /* Configure data size. */ + if (UART_DATA_BITS_7 == p_cfg->data_bits) + { + ccr3 |= (1U << SCI_UART_CCR3_CHR_OFFSET); + } + else if (UART_DATA_BITS_9 == p_cfg->data_bits) + { + ccr3 &= ~(1U << (SCI_UART_CCR3_CHR_OFFSET + 1)); + } + else + { + /* Do nothing. Default is 8-bit mode. */ + } + + /* Configure stop bits. */ + ccr3 |= (uint32_t) p_cfg->stop_bits << SCI_UART_CCR3_STP_OFFSET; + + /* Configure CKE bits. */ + sci_uart_extended_cfg_t * p_extend = (sci_uart_extended_cfg_t *) p_cfg->p_extend; + ccr3 |= (p_extend->clock & SCI_UART_CCR3_CKE_VALUE_MASK) << SCI_UART_CCR3_CKE_OFFSET; + + /* Starts reception on falling edge of RXD if enabled in extension (otherwise reception starts at low level + * of RXD). */ + ccr3 |= (p_extend->rx_edge_start & 1U) << SCI_UART_CCR3_RxDSEL_OFFSET; + + ccr3 |= ((uint32_t) p_extend->rs485_setting.enable << R_SCI0_CCR3_DEN_Pos) & R_SCI0_CCR3_DEN_Msk; + + /* Configure SPEN bit. */ + if (SCI_UART_CLOCK_SOURCE_PCLKM == p_extend->clock_source) + { + ccr3 |= 1U << SCI_UART_CCR3_BPEN_OFFSET; + } + + /* Write to the CCR3 register. */ + p_instance_ctrl->p_reg->CCR3 = ccr3; + + /* CCR1 register setting. */ + uint32_t ccr1 = SCI_UART_CCR1_DEFAULT_VALUE; + + /* Configure flow control pin. */ + ccr1 |= ((uint32_t) (p_extend->flow_control << R_SCI0_CCR1_CTSE_Pos) & SCI_UART_CCR1_FLOW_CTSRTS_MASK); + + /* Set the default level of the TX pin to 1. */ + ccr1 |= (uint32_t) (1U << SCI_UART_CCR1_SPB2DT_BIT | SCI_UART_CCR1_OUTPUT_ENABLE_MASK); + + /* Configure parity bits. */ + if (0 != p_cfg->parity) + { + ccr1 |= + (((UART_PARITY_EVEN == + p_cfg->parity) ? 1U : 3U) << SCI_UART_CCR1_PARITY_OFFSET) & SCI_UART_CCR1_PARITY_MASK; + } + + if (SCI_UART_NOISE_CANCELLATION_DISABLE != p_extend->noise_cancel) + { + /* Select noise filter clock */ + ccr1 |= (uint32_t) (((p_extend->noise_cancel & 0x07U) - 1) & SCI_UART_CCR1_NFCS_VALUE_MASK) << + SCI_UART_CCR1_NFCS_OFFSET; + + /* Enables the noise cancellation */ + ccr1 |= (uint32_t) 1 << SCI_UART_CCR1_NFEN_OFFSET; + } + + p_instance_ctrl->p_reg->CCR1 = ccr1; + + if ((SCI_UART_CLOCK_EXT8X == p_extend->clock) || (SCI_UART_CLOCK_EXT16X == p_extend->clock)) + { + /* Use external clock for baud rate */ + p_instance_ctrl->p_reg->CCR2_b.BRR = SCI_UART_BRR_DEFAULT_VALUE; + + if (SCI_UART_CLOCK_EXT8X == p_extend->clock) + { + /* Set baud rate as (external clock / 8) */ + p_instance_ctrl->p_reg->CCR2 |= 1U << SCI_UART_CCR2_ABCS_OFFSET; + } + } + else + { + /* Set the baud rate settings for the internal baud rate generator. */ + r_sci_uart_baud_set(p_instance_ctrl->p_reg, p_extend->p_baud_setting); + } + + /* Configure RS-485 DE assertion settings. */ + uint32_t dcr = ((uint32_t) (p_extend->rs485_setting.polarity << R_SCI0_DCR_DEPOL_Pos)) & R_SCI0_DCR_DEPOL_Msk; + dcr |= ((uint32_t) p_extend->rs485_setting.assertion_time << R_SCI0_DCR_DEAST_Pos) & + R_SCI0_DCR_DEAST_Msk; + dcr |= ((uint32_t) p_extend->rs485_setting.negation_time << R_SCI0_DCR_DENGT_Pos) & + R_SCI0_DCR_DENGT_Msk; + p_instance_ctrl->p_reg->DCR = dcr; +} + +#if SCI_UART_CFG_FIFO_SUPPORT + +/*******************************************************************************************************************//** + * Resets FIFO related registers. + * + * @param[in] p_instance_ctrl Pointer to UART instance control + * @param[in] p_cfg Pointer to UART configuration structure + **********************************************************************************************************************/ +static void r_sci_uart_fifo_cfg (sci_uart_instance_ctrl_t * const p_instance_ctrl) +{ + if (0U != p_instance_ctrl->fifo_depth) + { + /* Set the tx and rx reset bits */ + uint32_t fcr = 0U; + + #if (SCI_UART_CFG_TX_ENABLE) + #if SCI_UART_CFG_DMAC_SUPPORTED + if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx) + { + /* When DMAC transfer is used, set TTRG[4:0] = 0x0F. */ + fcr |= SCI_UART_FCR_TTRG_DMAC_VALUE << SCI_UART_FCR_TTRG_OFFSET; + } + #endif + #endif + + #if (SCI_UART_CFG_RX_ENABLE) + #if SCI_UART_CFG_DMAC_SUPPORTED + + /* If DMAC is used keep the receive trigger at the default level of 0. */ + if (NULL == p_instance_ctrl->p_cfg->p_transfer_rx) + #endif + { + /* Otherwise, set receive trigger number as configured by the user. */ + sci_uart_extended_cfg_t const * p_extend = p_instance_ctrl->p_cfg->p_extend; + + /* RTRG(Receive FIFO Data Trigger Number) controls when the RXI interrupt will be generated. If data is + * received but the trigger number is not met the RXI interrupt will be generated after 15 ETUs from + * the last stop bit in asynchronous mode. */ + fcr |= (((p_instance_ctrl->fifo_depth - 1U) & p_extend->rx_fifo_trigger) & SCI_UART_FCR_TRIGGER_MASK) << + SCI_UART_FCR_RTRG_OFFSET; + } + + /* RTS asserts when the amount of received data stored in the fifo is equal or less than this value. */ + fcr |= ((p_instance_ctrl->fifo_depth - 1U) & SCI_UART_FCR_TRIGGER_MASK) << SCI_UART_FCR_RSTRG_OFFSET; + #endif + + /* Set the FCR and reset the fifos. */ + p_instance_ctrl->p_reg->FCR = (uint32_t) (fcr | SCI_UART_FCR_RESET_TX_RX); + } +} + +#endif + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info. + * + * @param[in] p_instance_ctrl Pointer to driver control block + * @param[in] ipl Interrupt priority level + * @param[in] irq IRQ number for this interrupt + **********************************************************************************************************************/ +static void r_sci_irq_cfg (sci_uart_instance_ctrl_t * const p_instance_ctrl, uint8_t const ipl, IRQn_Type const irq) +{ + /* Disable interrupts, set priority, and store control block in the vector information so it can be accessed + * from the callback. */ + R_BSP_IrqDisable(irq); + + R_BSP_IrqCfg(irq, ipl, p_instance_ctrl); +} + +/*******************************************************************************************************************//** + * Sets interrupt priority and initializes vector info for all interrupts. + * + * @param[in] p_instance_ctrl Pointer to UART instance control block + * @param[in] p_cfg Pointer to UART specific configuration structure + **********************************************************************************************************************/ +static void r_sci_irqs_cfg (sci_uart_instance_ctrl_t * const p_instance_ctrl, uart_cfg_t const * const p_cfg) +{ +#if (SCI_UART_CFG_RX_ENABLE) + + /* ERI is optional. */ + r_sci_irq_cfg(p_instance_ctrl, p_cfg->eri_ipl, p_cfg->eri_irq); + r_sci_irq_cfg(p_instance_ctrl, p_cfg->rxi_ipl, p_cfg->rxi_irq); +#endif +#if (SCI_UART_CFG_TX_ENABLE) + r_sci_irq_cfg(p_instance_ctrl, p_cfg->txi_ipl, p_cfg->txi_irq); + + r_sci_irq_cfg(p_instance_ctrl, p_cfg->tei_ipl, p_cfg->tei_irq); +#endif +} + +#if SCI_UART_CFG_DMAC_SUPPORTED + +/*******************************************************************************************************************//** + * Closes transfer interfaces. + * + * @param[in] p_instance_ctrl Pointer to UART instance control block + **********************************************************************************************************************/ +static void r_sci_uart_transfer_close (sci_uart_instance_ctrl_t * p_instance_ctrl) +{ + #if (SCI_UART_CFG_RX_ENABLE) + if (NULL != p_instance_ctrl->p_cfg->p_transfer_rx) + { + p_instance_ctrl->p_cfg->p_transfer_rx->p_api->close(p_instance_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + #endif + #if (SCI_UART_CFG_TX_ENABLE) + if (NULL != p_instance_ctrl->p_cfg->p_transfer_tx) + { + p_instance_ctrl->p_cfg->p_transfer_tx->p_api->close(p_instance_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } + #endif +} + +#endif + +/*******************************************************************************************************************//** + * Changes baud rate based on predetermined register settings. + * + * @param[in] p_sci_reg Base pointer for SCI registers + * @param[in] p_baud_setting Pointer to other divisor related settings + * + * @note The transmitter and receiver (TE and RE bits in SCR) must be disabled prior to calling this function. + **********************************************************************************************************************/ +static void r_sci_uart_baud_set (R_SCI0_Type * p_sci_reg, sci_baud_setting_t const * const p_baud_setting) +{ + p_sci_reg->CCR2 = (uint32_t) ((p_sci_reg->CCR2 & ~(SCI_UART_CCR2_BAUD_SETTING_MASK)) | + (p_baud_setting->baudrate_bits & SCI_UART_CCR2_BAUD_SETTING_MASK)); +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_instance_ctrl Pointer to UART instance control block + * @param[in] data See uart_callback_args_t in r_uart_api.h + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_sci_uart_call_callback (sci_uart_instance_ctrl_t * p_instance_ctrl, uint32_t data, uart_event_t event) +{ + uart_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. */ + uart_callback_args_t * p_args = p_instance_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_instance_ctrl->p_cfg->channel; + p_args->data = data; + p_args->event = event; + p_args->p_context = p_instance_ctrl->p_context; + + p_instance_ctrl->p_callback(p_args); + + if (NULL != p_instance_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_instance_ctrl->p_callback_memory = args; + } +} + +#if (SCI_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * Common processing for TXI interrupt and DMA transfer completion interrupt in UART write mode. This function writes + * the next data. After the last data byte is written, this function disables the TXI interrupt and enables the TEI + * (transmit end) interrupt. + **********************************************************************************************************************/ +static void sci_uart_txi_common (sci_uart_instance_ctrl_t * p_instance_ctrl) +{ + if ((NULL == p_instance_ctrl->p_cfg->p_transfer_tx) && (0U != p_instance_ctrl->tx_src_bytes)) + { + if (2U == p_instance_ctrl->data_bytes) + { + p_instance_ctrl->p_reg->TDR_b.TDAT = (*(uint16_t *) (p_instance_ctrl->p_tx_src)) & SCI_UART_TDR_9BIT_MASK; + } + else + { + p_instance_ctrl->p_reg->TDR_b.TDAT = *(p_instance_ctrl->p_tx_src); + } + + /* Update pointer to the next data and number of remaining bytes in the control block. */ + p_instance_ctrl->tx_src_bytes -= p_instance_ctrl->data_bytes; + p_instance_ctrl->p_tx_src += p_instance_ctrl->data_bytes; + + /* If transfer is not used, write data until FIFO is full. */ + #if SCI_UART_CFG_FIFO_SUPPORT + if (0U != p_instance_ctrl->fifo_depth) + { + uint32_t fifo_count = p_instance_ctrl->p_reg->FTSR_b.T; + for (uint32_t cnt = fifo_count; (cnt < p_instance_ctrl->fifo_depth) && p_instance_ctrl->tx_src_bytes; cnt++) + { + if (2U == p_instance_ctrl->data_bytes) + { + p_instance_ctrl->p_reg->TDR_b.TDAT = (*(uint16_t *) (p_instance_ctrl->p_tx_src)) & + SCI_UART_TDR_9BIT_MASK; + } + else + { + p_instance_ctrl->p_reg->TDR_b.TDAT = *(p_instance_ctrl->p_tx_src); + } + + p_instance_ctrl->tx_src_bytes -= p_instance_ctrl->data_bytes; + p_instance_ctrl->p_tx_src += p_instance_ctrl->data_bytes; + } + + /* Clear TDRE flag */ + p_instance_ctrl->p_reg->CFCLR_b.TDREC = 1; + } + #endif + } + + if (0U == p_instance_ctrl->tx_src_bytes) + { + /* After all data has been transmitted, disable transmit interrupts and enable the transmit end interrupt. */ + uint32_t ccr0_temp = p_instance_ctrl->p_reg->CCR0; + ccr0_temp |= SCI_UART_CCR0_TEIE_MASK; + ccr0_temp &= (uint32_t) ~SCI_UART_CCR0_TIE_MASK; + p_instance_ctrl->p_reg->CCR0 = ccr0_temp; + + p_instance_ctrl->p_tx_src = NULL; + r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_TX_DATA_EMPTY); + } +} + +/*******************************************************************************************************************//** + * TXI interrupt handler for UART mode. TXI interrupt fires when the data in the data register or FIFO register has been + * transferred to the data shift register, and the next data can be written. This function calls sci_uart_txi_common(). + **********************************************************************************************************************/ +void sci_uart_txi_isr (void) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + sci_uart_txi_common(p_instance_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +/*******************************************************************************************************************//** + * Callback that must be called after a TX DMAC transfer completes. + * + * @param[in] p_instance_ctrl Pointer to SCI_UART instance control block + **********************************************************************************************************************/ +void sci_uart_tx_dmac_callback (sci_uart_instance_ctrl_t * p_instance_ctrl) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->txi_irq); + + sci_uart_txi_common(p_instance_ctrl); + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +#endif + +#if (SCI_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * Common processing for RXI interrupt and DMA transfer completion interrupt in UART read mode. This function calls + * callback function when it meets conditions below. + * - UART_EVENT_RX_COMPLETE: The number of data which has been read reaches to the number specified in R_SCI_UART_Read() + * if a transfer instance is used for reception. + * - UART_EVENT_RX_CHAR: Data is received asynchronously (read has not been called) + * + * This function also calls the callback function for RTS pin control if it is registered in R_SCI_UART_Open(). This is + * special functionality to expand SCI hardware capability and make RTS/CTS hardware flow control possible. If macro + * 'SCI_UART_CFG_FLOW_CONTROL_SUPPORT' is set, it is called at the beginning in this function to set the RTS pin high, + * then it is called again just before leaving this function to set the RTS pin low. + * @retval none + **********************************************************************************************************************/ +static void sci_uart_rxi_common (sci_uart_instance_ctrl_t * p_instance_ctrl) +{ + #if SCI_UART_CFG_DMAC_SUPPORTED + if ((p_instance_ctrl->p_cfg->p_transfer_rx == NULL) || (0 == p_instance_ctrl->rx_dest_bytes)) + #endif + { + #if (SCI_UART_CFG_FLOW_CONTROL_SUPPORT) + if (p_instance_ctrl->flow_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM) + { + R_BSP_PinAccessEnable(); + + /* Pause the transmission of data from the other device. */ + R_BSP_PinSet(R_BSP_IoRegionGet(p_instance_ctrl->flow_pin), p_instance_ctrl->flow_pin); + } + #endif + + uint32_t data; + #if SCI_UART_CFG_FIFO_SUPPORT + do + { + if ((p_instance_ctrl->fifo_depth > 0U)) + { + if (p_instance_ctrl->p_reg->FRSR_b.R > 0U) + { + data = p_instance_ctrl->p_reg->RDR_b.RDAT; + } + else + { + break; + } + } + else + { + data = p_instance_ctrl->p_reg->RDR_b.RDAT; + } + + #else + { + data = p_instance_ctrl->p_reg->RDR_b.RDAT; + #endif + if (0 == p_instance_ctrl->rx_dest_bytes) + { + /* Call user callback with the data. */ + r_sci_uart_call_callback(p_instance_ctrl, data, UART_EVENT_RX_CHAR); + } + else + { + memcpy((void *) p_instance_ctrl->p_rx_dest, &data, p_instance_ctrl->data_bytes); + p_instance_ctrl->p_rx_dest += p_instance_ctrl->data_bytes; + p_instance_ctrl->rx_dest_bytes -= p_instance_ctrl->data_bytes; + + if (0 == p_instance_ctrl->rx_dest_bytes) + { + r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + } + + #if SCI_UART_CFG_FIFO_SUPPORT + } while ((p_instance_ctrl->fifo_depth > 0U) && ((p_instance_ctrl->p_reg->FRSR_b.R) > 0U)); + + if (p_instance_ctrl->fifo_depth > 0U) + { + p_instance_ctrl->p_reg->CFCLR_b.RDRFC = 1; + } + + #else + } + #endif + #if (SCI_UART_CFG_FLOW_CONTROL_SUPPORT) + if (p_instance_ctrl->flow_pin != (bsp_io_port_pin_t) SCI_UART_INVALID_16BIT_PARAM) + { + /* Resume the transmission of data from the other device. */ + R_BSP_PinClear(R_BSP_IoRegionGet(p_instance_ctrl->flow_pin), p_instance_ctrl->flow_pin); + R_BSP_PinAccessDisable(); + } + #endif + } + + #if SCI_UART_CFG_DMAC_SUPPORTED + else + { + p_instance_ctrl->rx_dest_bytes = 0; + p_instance_ctrl->p_rx_dest = NULL; + + /* Call callback */ + r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_RX_COMPLETE); + } + #endif +} + +/*******************************************************************************************************************//** + * RXI interrupt handler for UART mode. RXI interrupt happens when data arrives to the data register or the FIFO + * register. This function calls sci_uart_rxi_common(). + **********************************************************************************************************************/ +void sci_uart_rxi_isr (void) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + sci_uart_rxi_common(p_instance_ctrl); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +/*******************************************************************************************************************//** + * Callback that must be called after a RX DMAC transfer completes. + * + * @param[in] p_instance_ctrl Pointer to SCI_UART instance control block + **********************************************************************************************************************/ +void sci_uart_rx_dmac_callback (sci_uart_instance_ctrl_t * p_instance_ctrl) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Now that the transfer using DMAC is finished, enable the corresponding IRQ. */ + R_BSP_IrqEnable(p_instance_ctrl->p_cfg->rxi_irq); + + sci_uart_rxi_common(p_instance_ctrl); + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +#endif + +#if (SCI_UART_CFG_TX_ENABLE) + +/*******************************************************************************************************************//** + * TEI interrupt processing for UART mode. The TEI interrupt fires after the last byte is transmitted on the TX pin. + * The user callback function is called with the UART_EVENT_TX_COMPLETE event code (if it is registered in + * R_SCI_UART_Open()). + **********************************************************************************************************************/ +void sci_uart_tei_isr (void) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Receiving TEI(transmit end interrupt) means the completion of transmission, so call callback function here. */ + p_instance_ctrl->p_reg->CCR0 &= (uint32_t) ~(SCI_UART_CCR0_TIE_MASK | SCI_UART_CCR0_TEIE_MASK); + + /* Dummy read to ensure that interrupts are disabled. */ + volatile uint32_t dummy = p_instance_ctrl->p_reg->CCR0; + FSP_PARAMETER_NOT_USED(dummy); + + r_sci_uart_call_callback(p_instance_ctrl, 0U, UART_EVENT_TX_COMPLETE); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +#endif + +#if (SCI_UART_CFG_RX_ENABLE) + +/*******************************************************************************************************************//** + * ERI interrupt processing for UART mode. When an ERI interrupt fires, the user callback function is called if it is + * registered in R_SCI_UART_Open() with the event code that triggered the interrupt. + **********************************************************************************************************************/ +void sci_uart_eri_isr (void) +{ + SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE; + + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + + /* Recover ISR context saved in open. */ + sci_uart_instance_ctrl_t * p_instance_ctrl = (sci_uart_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + uint32_t data = 0U; + uart_event_t event = (uart_event_t) 0U; + + /* Read data. */ + data = p_instance_ctrl->p_reg->RDR_b.RDAT; + + /* Determine cause of error. */ + uint32_t csr = p_instance_ctrl->p_reg->CSR & SCI_UART_RCVR_ERR_MASK; + + if (csr & SCI_UART_CSR_ORER_MASK) + { + event |= UART_EVENT_ERR_OVERFLOW; + } + + if (csr & SCI_UART_CSR_FER_MASK) + { + event |= UART_EVENT_ERR_FRAMING; + } + + if (csr & SCI_UART_CSR_PER_MASK) + { + event |= UART_EVENT_ERR_PARITY; + } + + /* Check if there is a break detected. */ + if ((UART_EVENT_ERR_FRAMING == (event & UART_EVENT_ERR_FRAMING)) && (0U == p_instance_ctrl->p_reg->CSR_b.RXDMON)) + { + event |= UART_EVENT_BREAK_DETECT; + } + + /* Clear error condition. */ + p_instance_ctrl->p_reg->CFCLR |= (uint32_t) (SCI_UART_RCVR_ERRCLR_MASK); + + /* Dummy read to ensure that interrupt event is cleared. */ + volatile uint32_t dummy = p_instance_ctrl->p_reg->CSR; + FSP_PARAMETER_NOT_USED(dummy); + + /* Call callback. */ + r_sci_uart_call_callback(p_instance_ctrl, data, event); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; + + SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE; +} + +#endif diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg.txt b/bsp/renesas/rzn2l_rsk/rzn_cfg.txt new file mode 100644 index 00000000000..91026057183 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg.txt @@ -0,0 +1,1158 @@ +FSP Configuration + Board "RSK+RZN2L (xSPI0 x1 boot mode)" + Parameter information for the loader: CACHE_FLG: 0x00000000 + Parameter information for the loader: WRAPCFG_V: 0x00000000 + Parameter information for the loader: COMCFG_V: 0x00000000 + Parameter information for the loader: BMCFG_V: 0x00000000 + Parameter information for the loader: xSPI_FLG: 0x00000000 + Parameter information for the loader: LDR_ADDR_NML: 0x6000004C + Parameter information for the loader: LDR_SIZE_NML: 0x00006000 + Parameter information for the loader: DEST_ADDR_NML: 0x00102000 + Parameter information for the loader: CSSCTL_V: 0x0000003F + Parameter information for the loader: LIOCFGCS0_V: 0x00070000 + Parameter information for the loader: ACCESS_SPEED: 0x00000006 + Parameter information for the loader: CHECK_SUM: Auto Calculate. + + R9A07G084M04GBG + part_number: R9A07G084M04GBG + atcm_size_bytes: 131072 + btcm_size_bytes: 131072 + system_ram_size_bytes: 1572864 + package_style: FBGA + package_pins: 225 + Cortex-R52 CPU core: CPU0 + + RZN2L Memory Config + Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 0: Disabled + Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 0: Disabled + Master MPU: MPU0 : DMAC Unit0: Region 0 Start: 0x00000000 + Master MPU: MPU0 : DMAC Unit0: Region 0 End: 0x00000C00 + Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 1: Disabled + Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 1: Disabled + Master MPU: MPU0 : DMAC Unit0: Region 1 Start: 0x00000000 + Master MPU: MPU0 : DMAC Unit0: Region 1 End: 0x00000C00 + Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 2: Disabled + Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 2: Disabled + Master MPU: MPU0 : DMAC Unit0: Region 2 Start: 0x00000000 + Master MPU: MPU0 : DMAC Unit0: Region 2 End: 0x00000C00 + Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 3: Disabled + Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 3: Disabled + Master MPU: MPU0 : DMAC Unit0: Region 3 Start: 0x00000000 + Master MPU: MPU0 : DMAC Unit0: Region 3 End: 0x00000C00 + Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 4: Disabled + Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 4: Disabled + Master MPU: MPU0 : DMAC Unit0: Region 4 Start: 0x00000000 + Master MPU: MPU0 : DMAC Unit0: Region 4 End: 0x00000C00 + Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 5: Disabled + Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 5: Disabled + Master MPU: MPU0 : DMAC Unit0: Region 5 Start: 0x00000000 + Master MPU: MPU0 : DMAC Unit0: Region 5 End: 0x00000C00 + Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 6: Disabled + Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 6: Disabled + Master MPU: MPU0 : DMAC Unit0: Region 6 Start: 0x00000000 + Master MPU: MPU0 : DMAC Unit0: Region 6 End: 0x00000C00 + Master MPU: MPU0 : DMAC Unit0: Enable or disable read control for Region 7: Disabled + Master MPU: MPU0 : DMAC Unit0: Enable or disable write control for Region 7: Disabled + Master MPU: MPU0 : DMAC Unit0: Region 7 Start: 0x00000000 + Master MPU: MPU0 : DMAC Unit0: Region 7 End: 0x00000C00 + Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 0: Disabled + Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 0: Disabled + Master MPU: MPU1 : DMAC Unit1: Region 0 Start: 0x00000000 + Master MPU: MPU1 : DMAC Unit1: Region 0 End: 0x00000C00 + Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 1: Disabled + Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 1: Disabled + Master MPU: MPU1 : DMAC Unit1: Region 1 Start: 0x00000000 + Master MPU: MPU1 : DMAC Unit1: Region 1 End: 0x00000C00 + Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 2: Disabled + Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 2: Disabled + Master MPU: MPU1 : DMAC Unit1: Region 2 Start: 0x00000000 + Master MPU: MPU1 : DMAC Unit1: Region 2 End: 0x00000C00 + Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 3: Disabled + Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 3: Disabled + Master MPU: MPU1 : DMAC Unit1: Region 3 Start: 0x00000000 + Master MPU: MPU1 : DMAC Unit1: Region 3 End: 0x00000C00 + Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 4: Disabled + Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 4: Disabled + Master MPU: MPU1 : DMAC Unit1: Region 4 Start: 0x00000000 + Master MPU: MPU1 : DMAC Unit1: Region 4 End: 0x00000C00 + Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 5: Disabled + Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 5: Disabled + Master MPU: MPU1 : DMAC Unit1: Region 5 Start: 0x00000000 + Master MPU: MPU1 : DMAC Unit1: Region 5 End: 0x00000C00 + Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 6: Disabled + Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 6: Disabled + Master MPU: MPU1 : DMAC Unit1: Region 6 Start: 0x00000000 + Master MPU: MPU1 : DMAC Unit1: Region 6 End: 0x00000C00 + Master MPU: MPU1 : DMAC Unit1: Enable or disable read control for Region 7: Disabled + Master MPU: MPU1 : DMAC Unit1: Enable or disable write control for Region 7: Disabled + Master MPU: MPU1 : DMAC Unit1: Region 7 Start: 0x00000000 + Master MPU: MPU1 : DMAC Unit1: Region 7 End: 0x00000C00 + Master MPU: MPU2 : GMAC: Enable or disable read control for Region 0: Disabled + Master MPU: MPU2 : GMAC: Enable or disable write control for Region 0: Disabled + Master MPU: MPU2 : GMAC: Region 0 Start: 0x00000000 + Master MPU: MPU2 : GMAC: Region 0 End: 0x00000C00 + Master MPU: MPU2 : GMAC: Enable or disable read control for Region 1: Disabled + Master MPU: MPU2 : GMAC: Enable or disable write control for Region 1: Disabled + Master MPU: MPU2 : GMAC: Region 1 Start: 0x00000000 + Master MPU: MPU2 : GMAC: Region 1 End: 0x00000C00 + Master MPU: MPU2 : GMAC: Enable or disable read control for Region 2: Disabled + Master MPU: MPU2 : GMAC: Enable or disable write control for Region 2: Disabled + Master MPU: MPU2 : GMAC: Region 2 Start: 0x00000000 + Master MPU: MPU2 : GMAC: Region 2 End: 0x00000C00 + Master MPU: MPU2 : GMAC: Enable or disable read control for Region 3: Disabled + Master MPU: MPU2 : GMAC: Enable or disable write control for Region 3: Disabled + Master MPU: MPU2 : GMAC: Region 3 Start: 0x00000000 + Master MPU: MPU2 : GMAC: Region 3 End: 0x00000C00 + Master MPU: MPU2 : GMAC: Enable or disable read control for Region 4: Disabled + Master MPU: MPU2 : GMAC: Enable or disable write control for Region 4: Disabled + Master MPU: MPU2 : GMAC: Region 4 Start: 0x00000000 + Master MPU: MPU2 : GMAC: Region 4 End: 0x00000C00 + Master MPU: MPU2 : GMAC: Enable or disable read control for Region 5: Disabled + Master MPU: MPU2 : GMAC: Enable or disable write control for Region 5: Disabled + Master MPU: MPU2 : GMAC: Region 5 Start: 0x00000000 + Master MPU: MPU2 : GMAC: Region 5 End: 0x00000C00 + Master MPU: MPU2 : GMAC: Enable or disable read control for Region 6: Disabled + Master MPU: MPU2 : GMAC: Enable or disable write control for Region 6: Disabled + Master MPU: MPU2 : GMAC: Region 6 Start: 0x00000000 + Master MPU: MPU2 : GMAC: Region 6 End: 0x00000C00 + Master MPU: MPU2 : GMAC: Enable or disable read control for Region 7: Disabled + Master MPU: MPU2 : GMAC: Enable or disable write control for Region 7: Disabled + Master MPU: MPU2 : GMAC: Region 7 Start: 0x00000000 + Master MPU: MPU2 : GMAC: Region 7 End: 0x00000C00 + Master MPU: MPU3 : USB Host: Enable or disable read control for Region 0: Disabled + Master MPU: MPU3 : USB Host: Enable or disable write control for Region 0: Disabled + Master MPU: MPU3 : USB Host: Region 0 Start: 0x00000000 + Master MPU: MPU3 : USB Host: Region 0 End: 0x00000000 + Master MPU: MPU3 : USB Host: Enable or disable read control for Region 1: Disabled + Master MPU: MPU3 : USB Host: Enable or disable write control for Region 1: Disabled + Master MPU: MPU3 : USB Host: Region 1 Start: 0x00000000 + Master MPU: MPU3 : USB Host: Region 1 End: 0x00000000 + Master MPU: MPU3 : USB Host: Enable or disable read control for Region 2: Disabled + Master MPU: MPU3 : USB Host: Enable or disable write control for Region 2: Disabled + Master MPU: MPU3 : USB Host: Region 2 Start: 0x00000000 + Master MPU: MPU3 : USB Host: Region 2 End: 0x00000000 + Master MPU: MPU3 : USB Host: Enable or disable read control for Region 3: Disabled + Master MPU: MPU3 : USB Host: Enable or disable write control for Region 3: Disabled + Master MPU: MPU3 : USB Host: Region 3 Start: 0x00000000 + Master MPU: MPU3 : USB Host: Region 3 End: 0x00000000 + Master MPU: MPU3 : USB Host: Enable or disable read control for Region 4: Disabled + Master MPU: MPU3 : USB Host: Enable or disable write control for Region 4: Disabled + Master MPU: MPU3 : USB Host: Region 4 Start: 0x00000000 + Master MPU: MPU3 : USB Host: Region 4 End: 0x00000000 + Master MPU: MPU3 : USB Host: Enable or disable read control for Region 5: Disabled + Master MPU: MPU3 : USB Host: Enable or disable write control for Region 5: Disabled + Master MPU: MPU3 : USB Host: Region 5 Start: 0x00000000 + Master MPU: MPU3 : USB Host: Region 5 End: 0x00000000 + Master MPU: MPU3 : USB Host: Enable or disable read control for Region 6: Disabled + Master MPU: MPU3 : USB Host: Enable or disable write control for Region 6: Disabled + Master MPU: MPU3 : USB Host: Region 6 Start: 0x00000000 + Master MPU: MPU3 : USB Host: Region 6 End: 0x00000000 + Master MPU: MPU3 : USB Host: Enable or disable read control for Region 7: Disabled + Master MPU: MPU3 : USB Host: Enable or disable write control for Region 7: Disabled + Master MPU: MPU3 : USB Host: Region 7 Start: 0x00000000 + Master MPU: MPU3 : USB Host: Region 7 End: 0x00000000 + Master MPU: MPU4 : USB Function: Enable or disable read control for Region 0: Disabled + Master MPU: MPU4 : USB Function: Enable or disable write control for Region 0: Disabled + Master MPU: MPU4 : USB Function: Region 0 Start: 0x00000000 + Master MPU: MPU4 : USB Function: Region 0 End: 0x00000000 + Master MPU: MPU4 : USB Function: Enable or disable read control for Region 1: Disabled + Master MPU: MPU4 : USB Function: Enable or disable write control for Region 1: Disabled + Master MPU: MPU4 : USB Function: Region 1 Start: 0x00000000 + Master MPU: MPU4 : USB Function: Region 1 End: 0x00000000 + Master MPU: MPU4 : USB Function: Enable or disable read control for Region 2: Disabled + Master MPU: MPU4 : USB Function: Enable or disable write control for Region 2: Disabled + Master MPU: MPU4 : USB Function: Region 2 Start: 0x00000000 + Master MPU: MPU4 : USB Function: Region 2 End: 0x00000000 + Master MPU: MPU4 : USB Function: Enable or disable read control for Region 3: Disabled + Master MPU: MPU4 : USB Function: Enable or disable write control for Region 3: Disabled + Master MPU: MPU4 : USB Function: Region 3 Start: 0x00000000 + Master MPU: MPU4 : USB Function: Region 3 End: 0x00000000 + Master MPU: MPU4 : USB Function: Enable or disable read control for Region 4: Disabled + Master MPU: MPU4 : USB Function: Enable or disable write control for Region 4: Disabled + Master MPU: MPU4 : USB Function: Region 4 Start: 0x00000000 + Master MPU: MPU4 : USB Function: Region 4 End: 0x00000000 + Master MPU: MPU4 : USB Function: Enable or disable read control for Region 5: Disabled + Master MPU: MPU4 : USB Function: Enable or disable write control for Region 5: Disabled + Master MPU: MPU4 : USB Function: Region 5 Start: 0x00000000 + Master MPU: MPU4 : USB Function: Region 5 End: 0x00000000 + Master MPU: MPU4 : USB Function: Enable or disable read control for Region 6: Disabled + Master MPU: MPU4 : USB Function: Enable or disable write control for Region 6: Disabled + Master MPU: MPU4 : USB Function: Region 6 Start: 0x00000000 + Master MPU: MPU4 : USB Function: Region 6 End: 0x00000000 + Master MPU: MPU4 : USB Function: Enable or disable read control for Region 7: Disabled + Master MPU: MPU4 : USB Function: Enable or disable write control for Region 7: Disabled + Master MPU: MPU4 : USB Function: Region 7 Start: 0x00000000 + Master MPU: MPU4 : USB Function: Region 7 End: 0x00000000 + Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 0: Disabled + Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 0: Disabled + Master MPU: MPU6 : CoreSight: Region 0 Start: 0x00000000 + Master MPU: MPU6 : CoreSight: Region 0 End: 0x00000C00 + Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 1: Disabled + Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 1: Disabled + Master MPU: MPU6 : CoreSight: Region 1 Start: 0x00000000 + Master MPU: MPU6 : CoreSight: Region 1 End: 0x00000C00 + Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 2: Disabled + Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 2: Disabled + Master MPU: MPU6 : CoreSight: Region 2 Start: 0x00000000 + Master MPU: MPU6 : CoreSight: Region 2 End: 0x00000C00 + Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 3: Disabled + Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 3: Disabled + Master MPU: MPU6 : CoreSight: Region 3 Start: 0x00000000 + Master MPU: MPU6 : CoreSight: Region 3 End: 0x00000C00 + Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 4: Disabled + Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 4: Disabled + Master MPU: MPU6 : CoreSight: Region 4 Start: 0x00000000 + Master MPU: MPU6 : CoreSight: Region 4 End: 0x00000C00 + Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 5: Disabled + Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 5: Disabled + Master MPU: MPU6 : CoreSight: Region 5 Start: 0x00000000 + Master MPU: MPU6 : CoreSight: Region 5 End: 0x00000C00 + Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 6: Disabled + Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 6: Disabled + Master MPU: MPU6 : CoreSight: Region 6 Start: 0x00000000 + Master MPU: MPU6 : CoreSight: Region 6 End: 0x00000C00 + Master MPU: MPU6 : CoreSight: Enable or disable read control for Region 7: Disabled + Master MPU: MPU6 : CoreSight: Enable or disable write control for Region 7: Disabled + Master MPU: MPU6 : CoreSight: Region 7 Start: 0x00000000 + Master MPU: MPU6 : CoreSight: Region 7 End: 0x00000C00 + Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 0: Disabled + Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 0: Disabled + Master MPU: MPU7 : SHOSTIF: Region 0 Start: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Region 0 End: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 1: Disabled + Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 1: Disabled + Master MPU: MPU7 : SHOSTIF: Region 1 Start: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Region 1 End: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 2: Disabled + Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 2: Disabled + Master MPU: MPU7 : SHOSTIF: Region 2 Start: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Region 2 End: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 3: Disabled + Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 3: Disabled + Master MPU: MPU7 : SHOSTIF: Region 3 Start: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Region 3 End: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 4: Disabled + Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 4: Disabled + Master MPU: MPU7 : SHOSTIF: Region 4 Start: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Region 4 End: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 5: Disabled + Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 5: Disabled + Master MPU: MPU7 : SHOSTIF: Region 5 Start: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Region 5 End: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 6: Disabled + Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 6: Disabled + Master MPU: MPU7 : SHOSTIF: Region 6 Start: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Region 6 End: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Enable or disable read control for Region 7: Disabled + Master MPU: MPU7 : SHOSTIF: Enable or disable write control for Region 7: Disabled + Master MPU: MPU7 : SHOSTIF: Region 7 Start: 0x00000000 + Master MPU: MPU7 : SHOSTIF: Region 7 End: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 0: Disabled + Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 0: Disabled + Master MPU: MPU8 : PHOSTIF: Region 0 Start: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Region 0 End: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 1: Disabled + Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 1: Disabled + Master MPU: MPU8 : PHOSTIF: Region 1 Start: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Region 1 End: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 2: Disabled + Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 2: Disabled + Master MPU: MPU8 : PHOSTIF: Region 2 Start: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Region 2 End: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 3: Disabled + Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 3: Disabled + Master MPU: MPU8 : PHOSTIF: Region 3 Start: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Region 3 End: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 4: Disabled + Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 4: Disabled + Master MPU: MPU8 : PHOSTIF: Region 4 Start: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Region 4 End: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 5: Disabled + Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 5: Disabled + Master MPU: MPU8 : PHOSTIF: Region 5 Start: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Region 5 End: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 6: Disabled + Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 6: Disabled + Master MPU: MPU8 : PHOSTIF: Region 6 Start: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Region 6 End: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Enable or disable read control for Region 7: Disabled + Master MPU: MPU8 : PHOSTIF: Enable or disable write control for Region 7: Disabled + Master MPU: MPU8 : PHOSTIF: Region 7 Start: 0x00000000 + Master MPU: MPU8 : PHOSTIF: Region 7 End: 0x00000000 + CPU MPU: Attribute: Attribute 0: Memory Type: Normal memory + CPU MPU: Attribute: Attribute 0: Normal Memory: Inner: Memory Attribute Indirection: Write-Back non-transient + CPU MPU: Attribute: Attribute 0: Normal Memory: Inner: Read: Allocate + CPU MPU: Attribute: Attribute 0: Normal Memory: Inner: Write: Allocate + CPU MPU: Attribute: Attribute 0: Normal Memory: Outer: Memory Attribute Indirection: Write-Back non-transient + CPU MPU: Attribute: Attribute 0: Normal Memory: Outer: Read: Allocate + CPU MPU: Attribute: Attribute 0: Normal Memory: Outer: Write: Allocate + CPU MPU: Attribute: Attribute 0: Device Memory: Device Type: Device-nGnRnE memory + CPU MPU: Attribute: Attribute 1: Memory Type: Normal memory + CPU MPU: Attribute: Attribute 1: Normal Memory: Inner: Memory Attribute Indirection: Write-Through non-transient + CPU MPU: Attribute: Attribute 1: Normal Memory: Inner: Read: Allocate + CPU MPU: Attribute: Attribute 1: Normal Memory: Inner: Write: Allocate + CPU MPU: Attribute: Attribute 1: Normal Memory: Outer: Memory Attribute Indirection: Write-Through non-transient + CPU MPU: Attribute: Attribute 1: Normal Memory: Outer: Read: Allocate + CPU MPU: Attribute: Attribute 1: Normal Memory: Outer: Write: Allocate + CPU MPU: Attribute: Attribute 1: Device Memory: Device Type: Device-nGnRnE memory + CPU MPU: Attribute: Attribute 2: Memory Type: Normal memory + CPU MPU: Attribute: Attribute 2: Normal Memory: Inner: Memory Attribute Indirection: Write-Through non-transient + CPU MPU: Attribute: Attribute 2: Normal Memory: Inner: Read: Do not allocate + CPU MPU: Attribute: Attribute 2: Normal Memory: Inner: Write: Do not allocate + CPU MPU: Attribute: Attribute 2: Normal Memory: Outer: Memory Attribute Indirection: Write-Through non-transient + CPU MPU: Attribute: Attribute 2: Normal Memory: Outer: Read: Do not allocate + CPU MPU: Attribute: Attribute 2: Normal Memory: Outer: Write: Do not allocate + CPU MPU: Attribute: Attribute 2: Device Memory: Device Type: Device-nGnRnE memory + CPU MPU: Attribute: Attribute 3: Memory Type: Normal memory + CPU MPU: Attribute: Attribute 3: Normal Memory: Inner: Memory Attribute Indirection: Non-Cacheable + CPU MPU: Attribute: Attribute 3: Normal Memory: Inner: Read: Do not allocate + CPU MPU: Attribute: Attribute 3: Normal Memory: Inner: Write: Do not allocate + CPU MPU: Attribute: Attribute 3: Normal Memory: Outer: Memory Attribute Indirection: Non-Cacheable + CPU MPU: Attribute: Attribute 3: Normal Memory: Outer: Read: Do not allocate + CPU MPU: Attribute: Attribute 3: Normal Memory: Outer: Write: Do not allocate + CPU MPU: Attribute: Attribute 3: Device Memory: Device Type: Device-nGnRnE memory + CPU MPU: Attribute: Attribute 4: Memory Type: Device memory + CPU MPU: Attribute: Attribute 4: Normal Memory: Inner: Memory Attribute Indirection: Write-Through transient + CPU MPU: Attribute: Attribute 4: Normal Memory: Inner: Read: Do not allocate + CPU MPU: Attribute: Attribute 4: Normal Memory: Inner: Write: Do not allocate + CPU MPU: Attribute: Attribute 4: Normal Memory: Outer: Memory Attribute Indirection: Write-Through transient + CPU MPU: Attribute: Attribute 4: Normal Memory: Outer: Read: Do not allocate + CPU MPU: Attribute: Attribute 4: Normal Memory: Outer: Write: Do not allocate + CPU MPU: Attribute: Attribute 4: Device Memory: Device Type: Device-nGnRnE memory + CPU MPU: Attribute: Attribute 5: Memory Type: Device memory + CPU MPU: Attribute: Attribute 5: Normal Memory: Inner: Memory Attribute Indirection: Write-Through transient + CPU MPU: Attribute: Attribute 5: Normal Memory: Inner: Read: Do not allocate + CPU MPU: Attribute: Attribute 5: Normal Memory: Inner: Write: Do not allocate + CPU MPU: Attribute: Attribute 5: Normal Memory: Outer: Memory Attribute Indirection: Write-Through transient + CPU MPU: Attribute: Attribute 5: Normal Memory: Outer: Read: Do not allocate + CPU MPU: Attribute: Attribute 5: Normal Memory: Outer: Write: Do not allocate + CPU MPU: Attribute: Attribute 5: Device Memory: Device Type: Device-nGnRE memory + CPU MPU: Attribute: Attribute 6: Memory Type: Device memory + CPU MPU: Attribute: Attribute 6: Normal Memory: Inner: Memory Attribute Indirection: Write-Through transient + CPU MPU: Attribute: Attribute 6: Normal Memory: Inner: Read: Do not allocate + CPU MPU: Attribute: Attribute 6: Normal Memory: Inner: Write: Do not allocate + CPU MPU: Attribute: Attribute 6: Normal Memory: Outer: Memory Attribute Indirection: Write-Through transient + CPU MPU: Attribute: Attribute 6: Normal Memory: Outer: Read: Do not allocate + CPU MPU: Attribute: Attribute 6: Normal Memory: Outer: Write: Do not allocate + CPU MPU: Attribute: Attribute 6: Device Memory: Device Type: Device-nGRE memory + CPU MPU: Attribute: Attribute 7: Memory Type: Device memory + CPU MPU: Attribute: Attribute 7: Normal Memory: Inner: Memory Attribute Indirection: Write-Through transient + CPU MPU: Attribute: Attribute 7: Normal Memory: Inner: Read: Do not allocate + CPU MPU: Attribute: Attribute 7: Normal Memory: Inner: Write: Do not allocate + CPU MPU: Attribute: Attribute 7: Normal Memory: Outer: Memory Attribute Indirection: Write-Through transient + CPU MPU: Attribute: Attribute 7: Normal Memory: Outer: Read: Do not allocate + CPU MPU: Attribute: Attribute 7: Normal Memory: Outer: Write: Do not allocate + CPU MPU: Attribute: Attribute 7: Device Memory: Device Type: Device-GRE memory + CPU MPU: Region: Region 00: Name: ATCM + CPU MPU: Region: Region 00: Base: 0x00000000 + CPU MPU: Region: Region 00: Limit: 0x0001FFFF + CPU MPU: Region: Region 00: Sharebility field: Outer Shareable + CPU MPU: Region: Region 00: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 00: Execute never: Execute Enable + CPU MPU: Region: Region 00: Attribute Index: Attribute 3 + CPU MPU: Region: Region 00: Region enable: Enabled + CPU MPU: Region: Region 01: Name: BTCM + CPU MPU: Region: Region 01: Base: 0x00100000 + CPU MPU: Region: Region 01: Limit: 0x0011FFFF + CPU MPU: Region: Region 01: Sharebility field: Outer Shareable + CPU MPU: Region: Region 01: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 01: Execute never: Execute Enable + CPU MPU: Region: Region 01: Attribute Index: Attribute 3 + CPU MPU: Region: Region 01: Region enable: Enabled + CPU MPU: Region: Region 02: Name: System RAM + CPU MPU: Region: Region 02: Base: 0x10000000 + CPU MPU: Region: Region 02: Limit: 0x1017FFFF + CPU MPU: Region: Region 02: Sharebility field: Non-shareable + CPU MPU: Region: Region 02: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 02: Execute never: Execute Enable + CPU MPU: Region: Region 02: Attribute Index: Attribute 1 + CPU MPU: Region: Region 02: Region enable: Enabled + CPU MPU: Region: Region 03: Name: Mirror area of System RAM + CPU MPU: Region: Region 03: Base: 0x30000000 + CPU MPU: Region: Region 03: Limit: 0x3017FFFF + CPU MPU: Region: Region 03: Sharebility field: Outer Shareable + CPU MPU: Region: Region 03: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 03: Execute never: Execute Enable + CPU MPU: Region: Region 03: Attribute Index: Attribute 3 + CPU MPU: Region: Region 03: Region enable: Enabled + CPU MPU: Region: Region 04: Name: Mirror area of external address space + CPU MPU: Region: Region 04: Base: 0x40000000 + CPU MPU: Region: Region 04: Limit: 0x5FFFFFFF + CPU MPU: Region: Region 04: Sharebility field: Outer Shareable + CPU MPU: Region: Region 04: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 04: Execute never: Execute Enable + CPU MPU: Region: Region 04: Attribute Index: Attribute 3 + CPU MPU: Region: Region 04: Region enable: Enabled + CPU MPU: Region: Region 05: Name: External address space + CPU MPU: Region: Region 05: Base: 0x60000000 + CPU MPU: Region: Region 05: Limit: 0x7FFFFFFF + CPU MPU: Region: Region 05: Sharebility field: Non-shareable + CPU MPU: Region: Region 05: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 05: Execute never: Execute Enable + CPU MPU: Region: Region 05: Attribute Index: Attribute 1 + CPU MPU: Region: Region 05: Region enable: Enabled + CPU MPU: Region: Region 06: Name: Non-Safety Peripheral + CPU MPU: Region: Region 06: Base: 0x80000000 + CPU MPU: Region: Region 06: Limit: 0x80FFFFFF + CPU MPU: Region: Region 06: Sharebility field: Outer Shareable + CPU MPU: Region: Region 06: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 06: Execute never: Execute Never + CPU MPU: Region: Region 06: Attribute Index: Attribute 5 + CPU MPU: Region: Region 06: Region enable: Enabled + CPU MPU: Region: Region 07: Name: Safety Peripheral + CPU MPU: Region: Region 07: Base: 0x81000000 + CPU MPU: Region: Region 07: Limit: 0x81FFFFFF + CPU MPU: Region: Region 07: Sharebility field: Outer Shareable + CPU MPU: Region: Region 07: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 07: Execute never: Execute Never + CPU MPU: Region: Region 07: Attribute Index: Attribute 5 + CPU MPU: Region: Region 07: Region enable: Enabled + CPU MPU: Region: Region 08: Name: LLPP Peripheral + CPU MPU: Region: Region 08: Base: 0x90000000 + CPU MPU: Region: Region 08: Limit: 0x901FFFFF + CPU MPU: Region: Region 08: Sharebility field: Outer Shareable + CPU MPU: Region: Region 08: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 08: Execute never: Execute Never + CPU MPU: Region: Region 08: Attribute Index: Attribute 5 + CPU MPU: Region: Region 08: Region enable: Enabled + CPU MPU: Region: Region 09: Name: GIC0 + CPU MPU: Region: Region 09: Base: 0x94000000 + CPU MPU: Region: Region 09: Limit: 0x941FFFFF + CPU MPU: Region: Region 09: Sharebility field: Outer Shareable + CPU MPU: Region: Region 09: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 09: Execute never: Execute Never + CPU MPU: Region: Region 09: Attribute Index: Attribute 4 + CPU MPU: Region: Region 09: Region enable: Enabled + CPU MPU: Region: Region 10: Name: Debug Private + CPU MPU: Region: Region 10: Base: 0xC0000000 + CPU MPU: Region: Region 10: Limit: 0xC0FFFFFF + CPU MPU: Region: Region 10: Sharebility field: Outer Shareable + CPU MPU: Region: Region 10: Access Permission(EL1 / EL0): ReadWrite / ReadWrite + CPU MPU: Region: Region 10: Execute never: Execute Never + CPU MPU: Region: Region 10: Attribute Index: Attribute 4 + CPU MPU: Region: Region 10: Region enable: Enabled + CPU MPU: Region: Region 11: Name: Not Used + CPU MPU: Region: Region 11: Base: 0x00000000 + CPU MPU: Region: Region 11: Limit: 0x00000000 + CPU MPU: Region: Region 11: Sharebility field: Non-shareable + CPU MPU: Region: Region 11: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 11: Execute never: Execute Enable + CPU MPU: Region: Region 11: Attribute Index: Attribute 0 + CPU MPU: Region: Region 11: Region enable: Disabled + CPU MPU: Region: Region 12: Name: Not Used + CPU MPU: Region: Region 12: Base: 0x00000000 + CPU MPU: Region: Region 12: Limit: 0x00000000 + CPU MPU: Region: Region 12: Sharebility field: Non-shareable + CPU MPU: Region: Region 12: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 12: Execute never: Execute Enable + CPU MPU: Region: Region 12: Attribute Index: Attribute 0 + CPU MPU: Region: Region 12: Region enable: Disabled + CPU MPU: Region: Region 13: Name: Not Used + CPU MPU: Region: Region 13: Base: 0x00000000 + CPU MPU: Region: Region 13: Limit: 0x00000000 + CPU MPU: Region: Region 13: Sharebility field: Non-shareable + CPU MPU: Region: Region 13: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 13: Execute never: Execute Enable + CPU MPU: Region: Region 13: Attribute Index: Attribute 0 + CPU MPU: Region: Region 13: Region enable: Disabled + CPU MPU: Region: Region 14: Name: Not Used + CPU MPU: Region: Region 14: Base: 0x00000000 + CPU MPU: Region: Region 14: Limit: 0x00000000 + CPU MPU: Region: Region 14: Sharebility field: Non-shareable + CPU MPU: Region: Region 14: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 14: Execute never: Execute Enable + CPU MPU: Region: Region 14: Attribute Index: Attribute 0 + CPU MPU: Region: Region 14: Region enable: Disabled + CPU MPU: Region: Region 15: Name: Not Used + CPU MPU: Region: Region 15: Base: 0x00000000 + CPU MPU: Region: Region 15: Limit: 0x00000000 + CPU MPU: Region: Region 15: Sharebility field: Non-shareable + CPU MPU: Region: Region 15: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 15: Execute never: Execute Enable + CPU MPU: Region: Region 15: Attribute Index: Attribute 0 + CPU MPU: Region: Region 15: Region enable: Disabled + CPU MPU: Region: Region 16: Name: Not Used + CPU MPU: Region: Region 16: Base: 0x00000000 + CPU MPU: Region: Region 16: Limit: 0x00000000 + CPU MPU: Region: Region 16: Sharebility field: Non-shareable + CPU MPU: Region: Region 16: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 16: Execute never: Execute Enable + CPU MPU: Region: Region 16: Attribute Index: Attribute 0 + CPU MPU: Region: Region 16: Region enable: Disabled + CPU MPU: Region: Region 17: Name: Not Used + CPU MPU: Region: Region 17: Base: 0x00000000 + CPU MPU: Region: Region 17: Limit: 0x00000000 + CPU MPU: Region: Region 17: Sharebility field: Non-shareable + CPU MPU: Region: Region 17: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 17: Execute never: Execute Enable + CPU MPU: Region: Region 17: Attribute Index: Attribute 0 + CPU MPU: Region: Region 17: Region enable: Disabled + CPU MPU: Region: Region 18: Name: Not Used + CPU MPU: Region: Region 18: Base: 0x00000000 + CPU MPU: Region: Region 18: Limit: 0x00000000 + CPU MPU: Region: Region 18: Sharebility field: Non-shareable + CPU MPU: Region: Region 18: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 18: Execute never: Execute Enable + CPU MPU: Region: Region 18: Attribute Index: Attribute 0 + CPU MPU: Region: Region 18: Region enable: Disabled + CPU MPU: Region: Region 19: Name: Not Used + CPU MPU: Region: Region 19: Base: 0x00000000 + CPU MPU: Region: Region 19: Limit: 0x00000000 + CPU MPU: Region: Region 19: Sharebility field: Non-shareable + CPU MPU: Region: Region 19: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 19: Execute never: Execute Enable + CPU MPU: Region: Region 19: Attribute Index: Attribute 0 + CPU MPU: Region: Region 19: Region enable: Disabled + CPU MPU: Region: Region 20: Name: Not Used + CPU MPU: Region: Region 20: Base: 0x00000000 + CPU MPU: Region: Region 20: Limit: 0x00000000 + CPU MPU: Region: Region 20: Sharebility field: Non-shareable + CPU MPU: Region: Region 20: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 20: Execute never: Execute Enable + CPU MPU: Region: Region 20: Attribute Index: Attribute 0 + CPU MPU: Region: Region 20: Region enable: Disabled + CPU MPU: Region: Region 21: Name: Not Used + CPU MPU: Region: Region 21: Base: 0x00000000 + CPU MPU: Region: Region 21: Limit: 0x00000000 + CPU MPU: Region: Region 21: Sharebility field: Non-shareable + CPU MPU: Region: Region 21: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 21: Execute never: Execute Enable + CPU MPU: Region: Region 21: Attribute Index: Attribute 0 + CPU MPU: Region: Region 21: Region enable: Disabled + CPU MPU: Region: Region 22: Name: Not Used + CPU MPU: Region: Region 22: Base: 0x00000000 + CPU MPU: Region: Region 22: Limit: 0x00000000 + CPU MPU: Region: Region 22: Sharebility field: Non-shareable + CPU MPU: Region: Region 22: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 22: Execute never: Execute Enable + CPU MPU: Region: Region 22: Attribute Index: Attribute 0 + CPU MPU: Region: Region 22: Region enable: Disabled + CPU MPU: Region: Region 23: Name: Not Used + CPU MPU: Region: Region 23: Base: 0x00000000 + CPU MPU: Region: Region 23: Limit: 0x00000000 + CPU MPU: Region: Region 23: Sharebility field: Non-shareable + CPU MPU: Region: Region 23: Access Permission(EL1 / EL0): ReadWrite / None + CPU MPU: Region: Region 23: Execute never: Execute Enable + CPU MPU: Region: Region 23: Attribute Index: Attribute 0 + CPU MPU: Region: Region 23: Region enable: Disabled + CPU MPU: Background Region: Disabled + CPU MPU: Instruction Cache: Enabled + CPU MPU: Data Cache: Enabled + + RZN2L + stack size (bytes): FIQ stack size: 0x400 + stack size (bytes): IRQ stack size: 0x400 + stack size (bytes): ABT stack size: 0x400 + stack size (bytes): UND stack size: 0x400 + stack size (bytes): SYS stack size: 0x400 + stack size (bytes): SVC stack size: 0x400 + Heap size (bytes): 0x2000 + C Runtime Initialization : Enabled + TFU Mathlib: Enabled + + RZN2L Family + + RZN Common + MCU Vcc (mV): 3300 + Parameter checking: Disabled + Assert Failures: Return FSP_ERR_ASSERTION + Error Log: No Error Log + Soft Reset: Disabled + Port Protect: Enabled + Early BSP Initialization : Disabled + Multiplex Interrupt: Disabled + + Clocks + LOCO Enabled + PLL1 is initial state + Ethernet Clock src: Main clock oscillator + CLMA0 Enabled + CLMA0 error not mask + CLMA3 error not mask + CLMA1 error mask + CLMA3 Enabled + CLMA1 Enabled + CLMA2 Enabled + CLMA0 CMPL 1 + CLMA1 CMPL 1 + CLMA2 CMPL 1 + CLMA3 CMPL 1 + Alternative clock: LOCO + CLMA0 CMPH 1023 + CLMA1 CMPH 1023 + CLMA2 CMPH 1023 + CLMA3 CMPH 1023 + ICLK 200MHz + CPU0CLK Mulx2 + CKIO Div/4 + SCI0ASYNCCLK: 96MHz + SCI1ASYNCCLK: 96MHz + SCI2ASYNCCLK: 96MHz + SCI3ASYNCCLK: 96MHz + SCI4ASYNCCLK: 96MHz + SCI5ASYNCCLK: 96MHz + SPI0ASYNCCLK: 96MHz + SPI1ASYNCCLK: 96MHz + SPI2ASYNCCLK: 96MHz + SPI3ASYNCCLK: 96MHz + PCLKCAN 40MHz + XSPI_CLK0 12.5MHz + XSPI_CLK1 12.5MHz + + Pin Configurations + RSK+RZN2L -> g_bsp_pin_cfg + AN000 B13 SYSTEM_AN000 - - - - - - - - I "Read only" - + AN001 C12 SYSTEM_AN001 - - - - - - - - I "Read only" - + AN002 B14 SYSTEM_AN002 - - - - - - - - I "Read only" - + AN003 C13 SYSTEM_AN003 - - - - - - - - I "Read only" - + AN100 B12 SYSTEM_AN100 - - - - - - - - I "Read only" - + AN101 A14 SYSTEM_AN101 - - - - - - - - I "Read only" - + AN102 B11 SYSTEM_AN102 - - - - - - - - I "Read only" - + AN103 A13 SYSTEM_AN103 - - - - - - - - I "Read only" - + AN104 A12 SYSTEM_AN104 - - - - - - - - I "Read only" - + AN105 B10 SYSTEM_AN105 - - - - - - - - I "Read only" - + AN106 A11 SYSTEM_AN106 - - - - - - - - I "Read only" - + AN107 C9 SYSTEM_AN107 - - - - - - - - I "Read only" - + AVCC18_TSU C14 SYSTEM_AVCC18_TSU - - - - - - - - I "Read only" - + AVCC18_USB P10 SYSTEM_AVCC18_USB - - - - - - - - I "Read only" - + AVCC18_USB R10 SYSTEM_AVCC18_USB - - - - - - - - I "Read only" - + BSCANP G2 SYSTEM_BSCANP - - - - - - - - I "Read only" - + EXTAL R7 CGC_EXTAL - - - - - - - - I "Read only" - + EXTCLKIN R6 CGC_EXTCLKIN - - - - - - - - I "Read only" - + MDX P5 SYSTEM_MDX - - - - - - - - IO "Read only" - + P00_0 C4 - ETH2_RXD3 - - Disabled - - "BSC: D15; ETHER_ETH2: ETH2_RXD3; PHOSTIF: HD15; SCI2: DE2; SCI2: SCK2" - None - - + P00_1 D5 - ETH2_RXDV - - Disabled - - "BSC: A13; ETHER_ETH2: ETH2_RXDV_CRSDV_RXCTL; IRQ: IRQ0; MTU35: MTIC5U; SCI2: RXD_MISO2; SCI2: SCL2" - None - - + P00_2 A3 - ETH2_TXEN - - Disabled - - "BSC: RD#; ETHER_ETH2: ETH2_TXEN_TXCTL; MTU35: MTIC5V; SCI2: SDA2; SCI2: TXD_MOSI2; USB_HS: USB_OVRCUR" - None - - + P00_3 B3 - ETH2_REFCLK - - Disabled - - "BSC: RD_WR#; ETHER_ETH2: ETH2_REFCLK; ETHER_ETH2: ETH2_RMII2_REFCLK; IRQ: IRQ1; MTU35: MTIC5W; SCI2: CTS_RTS_SS2#" - None - - + P00_4 A4 - - - - Disabled - - "BSC: WAIT#; DSMIF0: MCLK0; ETHER_ETH2: ETH2_RXER; GPT0: GTIOC0A; IRQ: IRQ13; MTU33: MTIOC3A; PHOSTIF: HWAIT#" - None - - + P00_5 B4 - ETH2_LINK - - Disabled - - "BSC: CS0#; DSMIF0: MDAT0; ETHER_ESC: ESC_PHYLINK0; ETHER_ESC: ESC_PHYLINK2; ETHER_ETHSW: ETHSW_PHYLINK0; ETHER_ETHSW: ETHSW_PHYLINK2; GPT0: GTIOC0B; MTU33: MTIOC3C" - None - - + P00_6 C3 - ETH2_TXCLK - - Disabled - - "BSC: CS5#; ETHER_ETH2: ETH2_TXCLK_TXC; GPT1: GTIOC1A; MTU33: MTIOC3B" - None - - + P00_7 D4 - - - - Disabled - - "BSC: RAS#; GPT2: GTIOC2A; IRQ: IRQ13; MTU34: MTIOC4A" - None - - + P01_0 A2 - - - - Disabled - - "BSC: CAS#; DSMIF1: MCLK1; ETHER_ESC: ESC_MDIO; ETHER_ETHSW: ETHSW_MDIO; ETHER_GMAC: GMAC_MDIO; GPT3: GTIOC3A; MTU34: MTIOC4C; SCI2: CTS2#" - None - - + P01_1 D3 - - - - Disabled - - "BSC: CKE; DSMIF1: MDAT1; ETHER_ESC: ESC_MDC; ETHER_ETHSW: ETHSW_MDC; ETHER_GMAC: GMAC_MDC; GPT1: GTIOC1B; MTU33: MTIOC3D; SCI2: DE2" - None - - + P01_2 B2 - ETH2_TXD3 - - Disabled - - "BSC: CS2#; ETHER_ETH2: ETH2_TXD3; GPT2: GTIOC2B; IRQ: IRQ2; MTU34: MTIOC4B" - None - - + P01_3 C2 - ETH2_TXD2 - - Disabled - - "BSC: AH#; ETHER_ETH2: ETH2_TXD2; GPT3: GTIOC3B; MTU34: MTIOC4D" - None - - + P01_4 E4 - ETH2_TXD1 - - Disabled - - "BSC: WE1#_DQMLU; ETHER_ETH2: ETH2_TXD1; IRQ: IRQ3; MTU_POE3: POE0#" - None - - + P01_5 B1 - ETH2_TXD0 - - Disabled - - "BSC: WE0#_DQMLL; ETHER_ETH2: ETH2_TXD0" - None - - + P01_6 D2 - - - - Disabled - - "BSC: A20; CANFD1: CANTXDP1; ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG1; GPT9: GTIOC9A; MTU31: MTIOC1A; PHOSTIF: HA20; SCI1: CTS1#; TRACE: TRACEDATA0" - None - - + P01_7 C1 CANFD0_CANRX0 CAN_RX Middle - "Peripheral mode" - - "ADC0: ADTRG0#; BSC: A19; CANFD0: CANRX0; ETHER_ETHSW: ETHSW_LPI1; GPT9: GTIOC9B; MTU31: MTIOC1B; PHOSTIF: HA19; SCI1: SCK1; SPI3: SPI_RSPCK3; TRACE: TRACEDATA1" - I - - + P02_0 E3 - - - - Disabled - - "BSC: A18; CANFD1: CANTX1; ETHER_ETHSW: ETHSW_LPI2; GPT: GTADSML0; IRQ: IRQ4; PHOSTIF: HA18; SCI1: RXD_MISO1; SCI1: SCL1; SPI3: SPI_MISO3; TRACE: TRACEDATA2; USB_HS: USB_OTGID" - None - - + P02_1 D1 - - - - Disabled - - "BSC: A17; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; PHOSTIF: HA17; SCI1: DE1" - None - - + P02_2 F3 CANFD0_CANTX0 CAN_TX Middle - "Peripheral mode" - - "BSC: A16; CANFD0: CANTX0; ETHER_ETHSW: ETHSW_TDMAOUT0; GPT10: GTIOC10A; IRQ: IRQ14; MTU32: MTIOC2A; MTU_POE3: POE10#; PHOSTIF: HA16; RTC: RTCAT1HZ; SCI1: SDA1; SCI1: TXD_MOSI1; SPI3: SPI_MOSI3" - O - - + P02_3 E1 - - - - Disabled - - "BSC: A15; BSC: AH#; CANFD1: CANRX1; ETHER_ETHSW: ETHSW_TDMAOUT1; GPT10: GTIOC10B; IRQ: IRQ15; MTU32: MTIOC2B; MTU_POE3: POE11#; PHOSTIF: HA15; SCI1: CTS_RTS_SS1#; SPI3: SPI_SSL30" - None - - + P02_4 F4 JTAG/SWD_TDO TDO High - "Peripheral mode" - - "BSC: WE0#_DQMLL; JTAG/SWD: TDO; SCI1: DE1; SPI3: SPI_SSL33" - O - - + P02_5 F2 JTAG/SWD_TDI TDI Low - "Peripheral mode" - - "BSC: WE1#_DQMLU; ETHER_ETHSW: ETHSW_TDMAOUT3; JTAG/SWD: TDI; SCI5: SCK5; SPI3: SPI_SSL31" - I - - + P02_6 F5 JTAG/SWD_TMS_SWDIO TMS High - "Peripheral mode" - - "JTAG/SWD: TMS_SWDIO; SCI5: RXD_MISO5; SCI5: SCL5" - IO - - + P02_7 F1 JTAG/SWD_TCK_SWCLK TCK Low - "Peripheral mode" - - "JTAG/SWD: TCK_SWCLK; SCI5: SDA5; SCI5: TXD_MOSI5" - I - - + P03_0 G3 GPIO ETH_LED4 Low - "Output mode (Low & Not Into Input)" - - "BSC: A14; BSC: CS5#; CANFD1: CANTXDP1; GPT: GTADSML1; IRQ: IRQ14; PHOSTIF: HA14; SCI2: SCK2; SPI3: SPI_SSL32; TRACE: TRACEDATA3" - IO - - + P03_5 G1 - - - - Disabled - - "BSC: A12; DSMIF2: MCLK2; ETHER_ETH2: ETH2_CRS; GPT4: GTIOC4A; IRQ: IRQ5; MTU33: MTIOC3A; PHOSTIF: HA12; SCI2: RXD_MISO2; SCI2: SCL2" - None - - + P03_6 G4 - - - - Disabled - - "BSC: A11; DSMIF2: MDAT2; ETHER_ETH2: ETH2_COL; GPT4: GTIOC4B; IRQ: IRQ8; MTU33: MTIOC3B; PHOSTIF: HA11; SCI2: SDA2; SCI2: TXD_MOSI2; SPI1: SPI_SSL13; TRACE: TRACEDATA4" - None - - + P03_7 G5 - - - - Disabled - - "BSC: A10; ETHER_ETH2: ETH2_TXER; GPT5: GTIOC5A; IRQ: IRQ9; MTU33: MTIOC3C; PHOSTIF: HA10; SCI3: SCK3; TRACE: TRACEDATA5" - None - - + P04_0 H1 - - - - Disabled - - "BSC: A9; GPT5: GTIOC5B; MTU33: MTIOC3D; PHOSTIF: HA9; SCI3: RXD_MISO3; SCI3: SCL3; TRACE: TRACEDATA6" - None - - + P04_1 H2 GPIO LED_RED1 Low - "Output mode (Low & Not Into Input)" - - "BSC: CKIO; IIC2: IIC_SDA2; PHOSTIF: HCKIO; SCI3: SDA3; SCI3: TXD_MOSI3; SPI0: SPI_MOSI0" - IO - - + P04_4 H4 GPIO ETH_LED6 Low - "Output mode (Low & Not Into Input)" - - "BSC: A8; GPT: GTADSMP0; IRQ: IRQ10; MTU_POE3: POE10#; PHOSTIF: HA8; SCI3: CTS3#; SPI1: SPI_RSPCK1; TRACE: TRACEDATA7" - IO - - + P04_5 H3 - - - - Disabled - - "BSC: A7; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT0; PHOSTIF: HA7; SCI3: DE3" - None - - + P04_6 H5 - - - - Disabled - - "BSC: A6; DMAC: DACK; ETHER_ETH1: ETH1_TXER; PHOSTIF: HA6; RTC: RTCAT1HZ" - None - - + P04_7 J1 - - - - Disabled - - "BSC: A5; ETHER_ETH0: ETH0_TXER; ETHER_ETH2: ETH2_TXER; PHOSTIF: HA5; SPI2: SPI_SSL21" - None - - + P05_0 J5 GPIO ETH_LED7 Low - "Output mode (Low & Not Into Input)" - - "BSC: A4; CANFD0: CANTXDP0; CMTW0: CMTW0_TOC0; DSMIF3: MCLK3; ETHER_ETH1: ETH1_CRS; GPT6: GTIOC6A; IRQ: IRQ12; MTU34: MTIOC4A; PHOSTIF: HA4; SCI5: CTS_RTS_SS5#; USB_HS: USB_VBUSEN" - IO - - + P05_1 J2 - - - - Disabled - - "BSC: A3; CANFD0: CANRXDP0; CMTW0: CMTW0_TIC1; DSMIF3: MDAT3; ETHER_ETH1: ETH1_COL; GPT6: GTIOC6B; IRQ: IRQ13; MTU34: MTIOC4B; PHOSTIF: HA3; SCI5: CTS5#; USB_HS: USB_EXICEN" - None - - + P05_2 J4 IIC1_IIC_SCL1 SCL Middle - "Peripheral mode" - - "BSC: A2; CANFD0: CANRX0; CMTW0: CMTW0_TOC0; DMAC: DREQ; ETHER_ETH0: ETH0_CRS; GPT7: GTIOC7A; GPT_POEG: GTETRGSA; IIC1: IIC_SCL1; IRQ: IRQ14; MTU34: MTIOC4C; PHOSTIF: HA2; SCI5: DE5; USB_HS: USB_VBUSEN" - IO - - + P05_3 J3 IIC1_IIC_SDA1 SDA Middle - "Peripheral mode" - - "BSC: A1; CANFD0: CANTX0; CMTW0: CMTW0_TIC0; ETHER_ETH0: ETH0_COL; GPT7: GTIOC7B; GPT_POEG: GTETRGSB; IIC1: IIC_SDA1; IRQ: IRQ15; MTU34: MTIOC4D; MTU_POE3: POE11#; PHOSTIF: HA1; SCI4: SCK4; USB_HS: USB_EXICEN" - IO - - + P05_4 K1 GPIO SW2 - - "Input mode" - - "BSC: A0; CANFD0: CANTXDP0; DMAC: DACK; ETHER_ETHSW: ETHSW_LPI0; GPT14: GTIOC14A; IRQ: IRQ12; PHOSTIF: HA0; SCI4: RXD_MISO4; SCI4: SCL4; SPI0: SPI_SSL00; USB_HS: USB_OVRCUR" - IO - - + P05_5 K2 - ETH1_LINK - - Disabled - - "CMTW0: CMTW0_TOC1; ETHER_ESC: ESC_PHYLINK1; ETHER_ETHSW: ETHSW_PHYLINK1; GPT14: GTIOC14B; SPI2: SPI_RSPCK2" - None - - + P05_6 K3 - - - - Disabled - - "CMTW1: CMTW1_TIC0; ETHER_ETH1: ETH1_RXER; GPT15: GTIOC15A; IRQ: IRQ12; SPI2: SPI_SSL22" - None - - + P05_7 M1 - ETH1_TXD2 - - Disabled - - "CMTW1: CMTW1_TOC1; ETHER_ETH1: ETH1_TXD2; GPT15: GTIOC15B; SCI4: SDA4; SCI4: TXD_MOSI4; SPI2: SPI_SSL23" - None - - + P06_0 L2 - ETH1_TXD3 - - Disabled - - "CANFD1: CANRX1; CMTW1: CMTW1_TOC0; ETHER_ETH1: ETH1_TXD3; GPT16: GTIOC16A; SCI4: CTS_RTS_SS4#; SPI2: SPI_SSL23" - None - - + P06_1 L3 - ETH1_REFCLK - - Disabled - - "CANFD1: CANTX1; ETHER_ETH1: ETH1_REFCLK; ETHER_ETH1: ETH1_RMII1_REFCLK; GPT16: GTIOC16B; SCI4: CTS4#; SPI2: SPI_SSL22" - None - - + P06_2 M2 - ETH1_TXD1 - - Disabled - - "CANFD1: CANRXDP1; ETHER_ETH1: ETH1_TXD1; GPT17: GTIOC17A" - None - - + P06_3 K4 - ETH1_TXD0 - - Disabled - - "CANFD1: CANTXDP1; CMTW1: CMTW1_TIC1; ETHER_ETH1: ETH1_TXD0; GPT17: GTIOC17B; SCI4: DE4; SPI1: SPI_MISO1" - None - - + P06_4 N1 - ETH1_TXCLK - - Disabled - - "ETHER_ETH1: ETH1_TXCLK_TXC; GPT11: GTIOC11A; SPI1: SPI_MOSI1" - None - - + P06_5 N2 - ETH1_TXEN - - Disabled - - "ETHER_ETH1: ETH1_TXEN_TXCTL; GPT11: GTIOC11B" - None - - + P06_6 L4 - ETH1_RXD0 - - Disabled - - "ETHER_ETH1: ETH1_RXD0; GPT12: GTIOC12A; SPI1: SPI_SSL10" - None - - + P06_7 M3 - ETH1_RXD1 - - Disabled - - "ETHER_ETH1: ETH1_RXD1; GPT12: GTIOC12B; SPI1: SPI_SSL11" - None - - + P07_0 P1 - ETH1_RXD2 - - Disabled - - "ETHER_ETH1: ETH1_RXD2; GPT13: GTIOC13A" - None - - + P07_1 N3 - ETH1_RXD3 - - Disabled - - "ETHER_ETH1: ETH1_RXD3; GPT13: GTIOC13B" - None - - + P07_2 P2 - ETH1_RXDV - - Disabled - - "ETHER_ETH1: ETH1_RXDV_CRSDV_RXCTL" - None - - + P07_3 M4 - ETH1_RXCLK - - Disabled - - "ETHER_ETH1: ETH1_RXCLK_REF_CLK_RXC" - None - - + P07_4 R2 USB_HS_USB_VBUSIN USB_VBUSIN - - "Peripheral mode" - - "ADC0: ADTRG0#; IRQ: IRQ1; USB_HS: USB_VBUSIN" - I - - + P08_4 N4 - ETH0_RXD3 - - Disabled - - "ETHER_ETH0: ETH0_RXD3; MTU36: MTIOC6A" - None - - + P08_5 P3 - ETH0_RXDV - - Disabled - - "ETHER_ETH0: ETH0_RXDV_CRSDV_RXCTL; MTU36: MTIOC6B" - None - - + P08_6 M5 - ETH0_RXCLK - - Disabled - - "ETHER_ETH0: ETH0_RXCLK_REF_CLK_RXC; MTU36: MTIOC6C" - None - - + P08_7 N5 ETHER_GMAC_GMAC_MDC ETH_MDC Low - "Peripheral mode" - - "ETHER_ESC: ESC_MDC; ETHER_ETHSW: ETHSW_MDC; ETHER_GMAC: GMAC_MDC; MTU36: MTIOC6D" - O - - + P09_0 P4 ETHER_GMAC_GMAC_MDIO ETH_MDIO Low - "Peripheral mode" - - "ETHER_ESC: ESC_MDIO; ETHER_ETHSW: ETHSW_MDIO; ETHER_GMAC: GMAC_MDIO; MTU37: MTIOC7A" - IO - - + P09_1 R3 - ETH0_REFCLK - - Disabled - - "ETHER_ETH0: ETH0_REFCLK; ETHER_ETH0: ETH0_RMII0_REFCLK; MTU37: MTIOC7B" - None - - + P09_2 N6 - - - - Disabled - - "ETHER_ETH0: ETH0_RXER; IRQ: IRQ0; MTU37: MTIOC7C" - None - - + P09_3 R4 - ETH0_TXD3 - - Disabled - - "ETHER_ETH0: ETH0_TXD3; MTU37: MTIOC7D" - None - - + P09_4 M6 - ETH0_TXD2 - - Disabled - - "ETHER_ETH0: ETH0_TXD2" - None - - + P09_5 N7 - ETH0_TXD1 - - Disabled - - "ETHER_ETH0: ETH0_TXD1" - None - - + P09_6 M7 - ETH0_TXD0 - - Disabled - - "ETHER_ETH0: ETH0_TXD0" - None - - + P09_7 L7 - ETH0_TXCLK - - Disabled - - "ETHER_ETH0: ETH0_TXCLK_TXC" - None - - + P10_0 N8 - ETH0_TXEN - - Disabled - - "ETHER_ETH0: ETH0_TXEN_TXCTL" - None - - + P10_1 M8 - ETH0_RXD0 - - Disabled - - "ETHER_ETH0: ETH0_RXD0" - None - - + P10_2 L8 - ETH0_RXD1 - - Disabled - - "ETHER_ETH0: ETH0_RXD1" - None - - + P10_3 L9 - ETH0_RXD2 - - Disabled - - "ETHER_ETH0: ETH0_RXD2; RTC: RTCAT1HZ" - None - - + P10_4 M9 - ETH0_LINK - - Disabled - - "ETHER_ESC: ESC_PHYLINK0; ETHER_ETHSW: ETHSW_PHYLINK0; IRQ: IRQ11" - None - - + P12_4 N11 - - - - Disabled - - "BSC: D15; ETHER_ETH1: ETH1_CRS; GPT8: GTIOC8B; MBXSEM: MBX_HINT#; MTU38: MTIOC8B; SPI0: SPI_SSL01; TRACE: TRACEDATA0" - None - - + P13_2 L10 IIC0_IIC_SCL0 EEPROM_SCL Middle - "Peripheral mode" - - "BSC: A13; BSC: D9; DSMIF4: MCLK4; ETHER_ESC: ESC_I2CCLK; ETHER_ETHSW: ETHSW_PTPOUT2; GPT10: GTIOC10A; IIC0: IIC_SCL0; IRQ: IRQ5; MTU30: MTIOC0A; MTU_POE3: POE8#; SCI1: CTS_RTS_SS1#; SPI0: SPI_MISO0; TRACE: TRACEDATA6" - IO - - + P13_3 N12 IIC0_IIC_SDA0 EEPROM_SDA Middle - "Peripheral mode" - - "BSC: D8; BSC: RD#; CMTW1: CMTW1_TOC0; DSMIF4: MDAT4; ETHER_ESC: ESC_I2CDATA; ETHER_ETHSW: ETHSW_PTPOUT3; GPT10: GTIOC10B; IIC0: IIC_SDA0; MTU30: MTIOC0B; MTU30: MTIOC0C; SCI1: CTS1#; SPI0: SPI_RSPCK0; TRACE: TRACEDATA7" - IO - - + P13_4 L12 GPIO ESC_RESETOUT Low - "Output mode (Low & Not Into Input)" - - "BSC: A0; ETHER_ESC: ESC_RESETOUT#; GPT8: GTIOC8B; MTU30: MTIOC0D" - IO - - + P13_5 M12 GPIO SW3_Pin2 - - "Input mode" - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG0; IIC2: IIC_SCL2; MTU3: MTCLKA; SPI1: SPI_RSPCK1; XSPI0: XSPI0_WP1#" - IO - - + P13_6 M13 GPIO SW3_Pin1 - - "Input mode" - - "ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT0; MTU3: MTCLKB; XSPI0: XSPI0_WP0#" - IO - - + P13_7 M11 GPIO SW3_Pin4 - - "Input mode" - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG1; MBXSEM: MBX_HINT#; MTU3: MTCLKC; XSPI0: XSPI0_ECS1#" - IO - - + P14_0 L13 GPIO SW3_Pin3 - - "Input mode" - - "ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; MTU3: MTCLKD; XSPI0: XSPI0_INT0#" - IO - - + P14_1 L14 - - - - Disabled - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_ETH1: ETH1_COL; ETHER_GMAC: GMAC_PTPTRG1; GPT8: GTIOC8A; MTU38: MTIOC8A; SHOSTIF: HSPI_IO0; XSPI0: XSPI0_INT1#" - None - - + P14_2 K12 XSPI0_XSPI0_ECS0# XSPI0_ECS Low - "Peripheral mode" - - "ETHER_ETH0: ETH0_CRS; ETHER_ETH2: ETH2_CRS; GPT8: GTIOC8B; IRQ: IRQ6; MTU38: MTIOC8B; SHOSTIF: HSPI_CK; XSPI0: XSPI0_ECS0#" - I - - + P14_3 M14 - - - - Disabled - - "ETHER_ETH0: ETH0_COL; ETHER_ETH2: ETH2_COL; MTU30: MTIOC0A; SHOSTIF: HSPI_IO1; XSPI0: XSPI0_RSTO1#" - None - - + P14_4 J13 XSPI0_XSPI0_DS XSPI0_DS High - "Peripheral mode" - - "BSC: BS#; ETHER_ESC: ESC_IRQ; MTU30: MTIOC0B; PHOSTIF: HBS#; XSPI0: XSPI0_DS" - IO - - + P14_5 J12 XSPI0_XSPI0_CKN XSPI0_CKN High - "Peripheral mode" - - "BSC: CS3#; MTU_POE3: POE8#; SHOSTIF: HSPI_INT#; XSPI0: XSPI0_CKN" - O - - + P14_6 K13 XSPI0_XSPI0_CKP XSPI0_CKP High - "Peripheral mode" - - "BSC: A21; XSPI0: XSPI0_CKP" - O - - + P14_7 M15 XSPI0_XSPI0_IO0 XSPI0_IO0 High - "Peripheral mode" - - "BSC: A22; BSC: BS#; SCI5: SCK5; SPI1: SPI_MISO1; XSPI0: XSPI0_IO0" - IO - - + P15_0 L11 XSPI0_XSPI0_IO1 XSPI0_IO1 High - "Peripheral mode" - - "BSC: A23; BSC: CKE; SCI5: RXD_MISO5; SCI5: SCL5; SPI1: SPI_MOSI1; XSPI0: XSPI0_IO1" - IO - - + P15_1 K14 XSPI0_XSPI0_IO2 XSPI0_IO2 High - "Peripheral mode" - - "BSC: A24; BSC: CAS#; MTU30: MTIOC0C; SCI5: SDA5; SCI5: TXD_MOSI5; SPI1: SPI_SSL10; XSPI0: XSPI0_IO2" - IO - - + P15_2 K15 XSPI0_XSPI0_IO3 XSPI0_IO3 High - "Peripheral mode" - - "BSC: A25; BSC: RAS#; MTU30: MTIOC0D; SCI5: CTS_RTS_SS5#; SPI1: SPI_SSL11; XSPI0: XSPI0_IO3" - IO - - + P15_3 K11 XSPI0_XSPI0_IO4 XSPI0_IO4 High - "Peripheral mode" - - "BSC: D11; DSMIF1: MCLK1; MTU38: MTIOC8C; XSPI0: XSPI0_IO4" - IO - - + P15_4 H13 XSPI0_XSPI0_IO5 XSPI0_IO5 High - "Peripheral mode" - - "BSC: D12; DSMIF1: MDAT1; MTU38: MTIOC8D; XSPI0: XSPI0_IO5" - IO - - + P15_5 J14 XSPI0_XSPI0_IO6 XSPI0_IO6 High - "Peripheral mode" - - "BSC: D13; DSMIF2: MCLK2; XSPI0: XSPI0_IO6" - IO - - + P15_6 H12 XSPI0_XSPI0_IO7 XSPI0_IO7 High - "Peripheral mode" - - "BSC: D14; DSMIF2: MDAT2; SPI1: SPI_SSL12; XSPI0: XSPI0_IO7" - IO - - + P15_7 J15 XSPI0_XSPI0_CS0# OSPI_CS High - "Peripheral mode" - - "DMAC: TEND; SCI5: CTS5#; SPI1: SPI_SSL13; XSPI0: XSPI0_CS0#" - O - - + P16_0 G13 XSPI0_XSPI0_CS1# ORAM_CS0 High - "Peripheral mode" - - "DSMIF3: MCLK3; ETHER_ETH0: ETH0_TXER; ETHER_ETH2: ETH2_REFCLK; SCI0: SDA0; SCI0: TXD_MOSI0; SHOSTIF: HSPI_CS#; SPI3: SPI_MOSI3; XSPI0: XSPI0_CS1#" - O - - + P16_1 H11 XSPI0_XSPI0_RESET0# XSPI0_RESET0 Low - "Peripheral mode" - - "ADC0: ADTRG0#; BSC: CS2#; CMTW0: CMTW0_TOC1; DSMIF3: MDAT3; PHOSTIF: HCS1#; SCI0: RXD_MISO0; SCI0: SCL0; SPI3: SPI_MISO3; XSPI0: XSPI0_RESET0#" - O - - + P16_2 H14 - - - - Disabled - - "IRQ: NMI; PHOSTIF: HERROUT#; SCI0: CTS0#; SHOSTIF: HSPI_IO2; SPI3: SPI_RSPCK3; USB_HS: USB_EXICEN; XSPI0: XSPI0_RESET1#" - None - - + P16_3 G12 GPIO SW1 - - "Input mode" - - "BSC: CS3#; ETHER_ETH1: ETH1_CRS; ETHER_ETH1: ETH1_TXER; GPT: GTADSMP1; IRQ: IRQ7; SCI0: SCK0; SHOSTIF: HSPI_IO3; SPI3: SPI_SSL30; XSPI0: XSPI0_RSTO0#" - IO - - + P16_5 H15 SCI0_TXD_MOSI0 UART_USB_TX High - "Peripheral mode" - - "BSC: A15; MTU35: MTIC5U; SCI0: SDA0; SCI0: TXD_MOSI0; SHOSTIF: HSPI_IO4" - IO - - + P16_6 G11 SCI0_RXD_MISO0 UART_USB_RX High - "Peripheral mode" - - "BSC: CS0#; IRQ: IRQ8; MTU35: MTIC5V; PHOSTIF: HCS0#; SCI0: RXD_MISO0; SCI0: SCL0; SHOSTIF: HSPI_IO5" - IO - - + P16_7 G14 - - - - Disabled - - "BSC: A13; MTU35: MTIC5W; PHOSTIF: HA13; SCI0: SCK0; XSPI1: XSPI1_IO0" - None - - + P17_0 F12 - - - - Disabled - - "ETHER_ESC: ESC_IRQ; SCI0: CTS_RTS_SS0#; XSPI1: XSPI1_IO1" - None - - + P17_3 F14 GPIO LED_RED2 Low - "Output mode (Low & Not Into Input)" - - "ADC1: ADTRG1#; DMAC: DREQ; GPT_POEG: GTETRGA; MTU_POE3: POE0#; SPI3: SPI_SSL31; TRACE: TRACECTL; XSPI1: XSPI1_IO2" - IO - - + P17_4 F13 - - - - Disabled - - "DMAC: DACK; GPT0: GTIOC0A; GPT_POEG: GTETRGB; MTU33: MTIOC3C; SCI3: CTS3#; SPI3: SPI_SSL32; TRACE: TRACECLK; XSPI1: XSPI1_IO3" - None - - + P17_5 F15 USB_HS_USB_OVRCUR USB_OVRCUR Low - "Peripheral mode" - - "DMAC: TEND; GPT0: GTIOC0B; GPT_POEG: GTETRGC; MTU33: MTIOC3A; USB_HS: USB_OVRCUR" - I - - + P17_6 G15 - - - - Disabled - - "BSC: RD_WR#; GPT1: GTIOC1A; MTU33: MTIOC3B; PHOSTIF: HWRSTB#; SCI3: SCK3; XSPI1: XSPI1_DS" - None - - + P17_7 E15 SCI3_RXD_MISO3 SCI_RXD High - "Peripheral mode" - - "BSC: RD#; DMAC: DACK; GPT2: GTIOC2A; GPT3: GTIOC3A; MTU34: MTIOC4A; MTU34: MTIOC4C; PHOSTIF: HRD#; SCI3: RXD_MISO3; SCI3: SCL3; XSPI1: XSPI1_CKP" - IO - - + P18_0 E14 SCI3_TXD_MOSI3 SCI_TXD High - "Peripheral mode" - - "BSC: WE0#_DQMLL; GPT2: GTIOC2A; GPT3: GTIOC3A; MTU34: MTIOC4A; MTU34: MTIOC4C; PHOSTIF: HWR0#; SCI3: SDA3; SCI3: TXD_MOSI3; SHOSTIF: HSPI_IO6" - IO - - + P18_1 D15 - - - - Disabled - - "ADC1: ADTRG1#; BSC: WE1#_DQMLU; GPT1: GTIOC1B; IRQ: IRQ10; MTU33: MTIOC3D; PHOSTIF: HWR1#; SCI3: CTS_RTS_SS3#; SHOSTIF: HSPI_IO7" - None - - + P18_2 D14 GPIO LED_GREEN Low - "Output mode (Low & Not Into Input)" - - "BSC: BS#; ETHER_ETH1: ETH1_COL; GPT2: GTIOC2B; GPT3: GTIOC3B; IIC2: IIC_SDA2; MTU34: MTIOC4B; MTU34: MTIOC4D; SCI0: SCK0; XSPI1: XSPI1_CS0#" - IO - - + P18_3 E13 - - - - Disabled - - "BSC: CKE; CANFD1: CANRXDP1; CMTW1: CMTW1_TIC1; ETHER_ETH2: ETH2_CRS; GPT2: GTIOC2B; GPT3: GTIOC3B; IRQ: IRQ0; MTU34: MTIOC4B; MTU34: MTIOC4D; XSPI1: XSPI1_IO4" - None - - + P18_4 E12 SPI2_SPI_RSPCK2 SCK High - "Peripheral mode" - - "BSC: CAS#; CANFD0: CANTX0; ETHER_ETH1: ETH1_CRS; IRQ: IRQ1; MTU35: MTIC5U; SCI4: SDA4; SCI4: TXD_MOSI4; SPI2: SPI_RSPCK2; XSPI1: XSPI1_IO5" - IO - - + P18_5 D13 SPI2_SPI_MOSI2 MOSI High - "Peripheral mode" - - "BSC: RAS#; CANFD0: CANRX0; ETHER_ETH2: ETH2_COL; MTU35: MTIC5V; SCI4: RXD_MISO4; SCI4: SCL4; SPI2: SPI_MOSI2; TRACE: TRACECTL; XSPI1: XSPI1_IO6" - IO - - + P18_6 C15 SPI2_SPI_MISO2 MISO High - "Peripheral mode" - - "ADC0: ADTRG0#; ETHER_ETH1: ETH1_COL; IIC2: IIC_SCL2; IRQ: IRQ11; MTU35: MTIC5W; SCI4: DE4; SCI4: SCK4; SPI2: SPI_MISO2; TRACE: TRACECLK; XSPI1: XSPI1_IO7" - IO - - + P19_0 B15 USB_HS_USB_VBUSEN USB_VBUSEN Low - "Peripheral mode" - - "USB_HS: USB_VBUSEN" - O - - + P20_1 B9 - ETH_LED2_MDV0 - - Disabled - - "ETHER_ESC: ESC_LINKACT0; ETHER_ETHSW: ETHSW_PTPOUT3; ETHER_ETHSW: ETHSW_TDMAOUT0" - None - - + P20_2 D8 - ETH_LED0_MDV1 - - Disabled - - "ETHER_ESC: ESC_LEDRUN; ETHER_ESC: ESC_LEDSTER; ETHER_ETHSW: ETHSW_PTPOUT2; ETHER_ETHSW: ETHSW_TDMAOUT1; SCI3: DE3" - None - - + P20_3 D9 - ETH_LED1_MDV2 - - Disabled - - "ETHER_ESC: ESC_LEDERR; ETHER_ETHSW: ETHSW_PTPOUT1; ETHER_ETHSW: ETHSW_TDMAOUT2" - None - - + P20_4 A9 - ETH_LED3_MDV3 - - Disabled - - "ETHER_ESC: ESC_LINKACT1; ETHER_ETHSW: ETHSW_PTPOUT0; ETHER_ETHSW: ETHSW_TDMAOUT3" - None - - + P21_1 B8 SPI2_SPI_SSL20 CS High - "Peripheral mode" - - "BSC: D0; CMTW0: CMTW0_TIC0; DSMIF0: MCLK0; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; GPT14: GTIOC14A; IIC1: IIC_SCL1; MTU36: MTIOC6A; PHOSTIF: HD0; SCI5: SCK5; SHOSTIF: HSPI_INT#; SPI2: SPI_SSL20; TRACE: TRACEDATA0" - IO - - + P21_2 C8 - - - - Disabled - - "BSC: D1; CMTW0: CMTW0_TIC1; DSMIF0: MDAT0; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; GPT14: GTIOC14B; IIC1: IIC_SDA1; MTU36: MTIOC6B; PHOSTIF: HD1; SCI5: RXD_MISO5; SCI5: SCL5; SPI2: SPI_MISO2; TRACE: TRACEDATA1" - None - - + P21_3 A8 - - - - Disabled - - "BSC: D2; DSMIF1: MCLK1; GPT15: GTIOC15A; IRQ: NMI; MTU36: MTIOC6C; PHOSTIF: HD2; SCI5: SDA5; SCI5: TXD_MOSI5; SPI3: SPI_SSL33; TRACE: TRACEDATA2" - None - - + P21_4 E7 - - - - Disabled - - "BSC: D3; DSMIF1: MDAT1; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; GPT15: GTIOC15B; MBXSEM: MBX_HINT#; MTU36: MTIOC6D; PHOSTIF: HD3; SCI5: CTS_RTS_SS5#; SPI0: SPI_SSL02; TRACE: TRACEDATA3" - None - - + P21_5 C7 - - - - Disabled - - "ADC1: ADTRG1#; BSC: D4; CMTW1: CMTW1_TOC1; DSMIF2: MCLK2; GPT16: GTIOC16A; IRQ: IRQ6; MTU37: MTIOC7A; PHOSTIF: HD4; SCI5: CTS5#; SPI0: SPI_MISO0; TRACE: TRACEDATA4" - None - - + P21_6 D7 - - - - Disabled - - "BSC: D5; DMAC: TEND; DSMIF2: MDAT2; GPT16: GTIOC16B; IRQ: IRQ9; MTU37: MTIOC7B; PHOSTIF: HD5; SCI0: CTS0#; TRACE: TRACEDATA5" - None - - + P21_7 B7 - - - - Disabled - - "BSC: D6; DMAC: DREQ; DSMIF3: MCLK3; GPT17: GTIOC17A; IRQ: IRQ10; MTU37: MTIOC7C; PHOSTIF: HD6; SCI0: DE0; TRACE: TRACEDATA6" - None - - + P22_0 A7 - - - - Disabled - - "BSC: D7; DSMIF3: MDAT3; GPT17: GTIOC17B; IRQ: IRQ15; MTU37: MTIOC7D; PHOSTIF: HD7; SCI5: DE5; TRACE: TRACEDATA7" - None - - + P22_1 A6 GPIO ETH_LED5 Low - "Output mode (Low & Not Into Input)" - - "BSC: D8; ETHER_ESC: ESC_LINKACT2; GPT_POEG: GTETRGB; MTU_POE3: POE4#; PHOSTIF: HD8; SCI4: CTS_RTS_SS4#; TRACE: TRACECTL" - IO - - + P22_2 C6 - - - - Disabled - - "BSC: D9; DSMIF1: MCLK1; GPT_POEG: GTETRGSA; IRQ: IRQ4; MTU38: MTIOC8C; PHOSTIF: HD9; SPI1: SPI_SSL12; TRACE: TRACECLK" - None - - + P22_3 B6 GPIO LED_ORANGE Low - "Output mode (Low & Not Into Input)" - - "BSC: D10; GPT_POEG: GTETRGSB; MTU38: MTIOC8D; PHOSTIF: HD10; SCI5: RXD_MISO5; SCI5: SCL5" - IO - - + P23_7 D6 - ETH2_RXD0 - - Disabled - - "BSC: BS#; BSC: D11; DSMIF4: MCLK4; ETHER_ETH2: ETH2_RXD0; GPT_POEG: GTETRGA; MTU30: MTIOC0A; PHOSTIF: HD11; SCI1: SCK1" - None - - + P24_0 A5 - ETH2_RXD1 - - Disabled - - "BSC: CKE; BSC: D12; DMAC: DREQ; DSMIF4: MDAT4; ETHER_ETH2: ETH2_RXD1; GPT_POEG: GTETRGB; MTU30: MTIOC0B; PHOSTIF: HD12; SCI1: RXD_MISO1; SCI1: SCL1" - None - - + P24_1 B5 - ETH2_RXCLK - - Disabled - - "BSC: CAS#; BSC: D13; DSMIF5: MCLK5; ETHER_ETH2: ETH2_RXCLK_REF_CLK_RXC; GPT_POEG: GTETRGC; MTU30: MTIOC0C; MTU_POE3: POE8#; PHOSTIF: HD13" - None - - + P24_2 C5 - ETH2_RXD2 - - Disabled - - "BSC: D14; BSC: RAS#; DSMIF5: MDAT5; ETHER_ETH2: ETH2_RXD2; GPT_POEG: GTETRGD; MTU30: MTIOC0D; PHOSTIF: HD14; SCI1: SDA1; SCI1: TXD_MOSI1" - None - - + RES# P6 SYSTEM_RES# - - - - - - - - I "Read only" - + TRST# E2 SYSTEM_TRST# - - - - - - - - I "Read only" - + USB_DM P13 SYSTEM_USB_DM - - - - - - - - IO "Read only" - + USB_DP R13 SYSTEM_USB_DP - - - - - - - - IO "Read only" - + USB_RREF P15 SYSTEM_USB_RREF - - - - - - - - I "Read only" - + VCC1833_0 L6 SYSTEM_VCC1833_0 - - - - - - - - I "Read only" - + VCC1833_1 K5 SYSTEM_VCC1833_1 - - - - - - - - I "Read only" - + VCC1833_2 E5 SYSTEM_VCC1833_2 - - - - - - - - I "Read only" - + VCC1833_3 J11 SYSTEM_VCC1833_3 - - - - - - - - I "Read only" - + VCC1833_4 F11 SYSTEM_VCC1833_4 - - - - - - - - I "Read only" - + VCC18_ADC0 E11 SYSTEM_VCC18_ADC0 - - - - - - - - I "Read only" - + VCC18_ADC1 E9 SYSTEM_VCC18_ADC1 - - - - - - - - I "Read only" - + VCC18_PLL0 P9 SYSTEM_VCC18_PLL0 - - - - - - - - I "Read only" - + VCC18_PLL1 N9 SYSTEM_VCC18_PLL1 - - - - - - - - I "Read only" - + VCC18_USB P11 SYSTEM_VCC18_USB - - - - - - - - I "Read only" - + VCC33 E6 SYSTEM_VCC33 - - - - - - - - I "Read only" - + VCC33 E8 SYSTEM_VCC33 - - - - - - - - I "Read only" - + VCC33 M10 SYSTEM_VCC33 - - - - - - - - I "Read only" - + VCC33 L5 SYSTEM_VCC33 - - - - - - - - I "Read only" - + VCC33_USB R11 SYSTEM_VCC33_USB - - - - - - - - I "Read only" - + VDD H10 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD G10 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD F6 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD F8 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD F9 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD G6 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD F10 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD H6 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD J6 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD K6 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD K7 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD K8 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD K10 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD P7 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD J10 SYSTEM_VDD - - - - - - - - I "Read only" - + VREFH0 C11 SYSTEM_VREFH0 - - - - - - - - I "Read only" - + VREFH1 C10 SYSTEM_VREFH1 - - - - - - - - I "Read only" - + VSS A1 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS R1 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS A10 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS R5 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS A15 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS R9 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS F7 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS G7 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS G8 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS G9 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS N10 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS H7 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS N14 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS H8 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS H9 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS E10 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS J7 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS J8 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS J9 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS K9 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS D10 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS D11 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS L1 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS L15 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS P8 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS R15 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS_ADC D12 SYSTEM_VSS_ADC - - - - - - - - I "Read only" - + VSS_USB P12 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + VSS_USB P14 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + VSS_USB N13 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + VSS_USB N15 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + VSS_USB R12 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + VSS_USB R14 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + XTAL R8 CGC_XTAL - - - - - - - - O "Read only" - + R9A07G084M04GBG.pincfg -> + AN000 B13 SYSTEM_AN000 - - - - - - - - I "Read only" - + AN001 C12 SYSTEM_AN001 - - - - - - - - I "Read only" - + AN002 B14 SYSTEM_AN002 - - - - - - - - I "Read only" - + AN003 C13 SYSTEM_AN003 - - - - - - - - I "Read only" - + AN100 B12 SYSTEM_AN100 - - - - - - - - I "Read only" - + AN101 A14 SYSTEM_AN101 - - - - - - - - I "Read only" - + AN102 B11 SYSTEM_AN102 - - - - - - - - I "Read only" - + AN103 A13 SYSTEM_AN103 - - - - - - - - I "Read only" - + AN104 A12 SYSTEM_AN104 - - - - - - - - I "Read only" - + AN105 B10 SYSTEM_AN105 - - - - - - - - I "Read only" - + AN106 A11 SYSTEM_AN106 - - - - - - - - I "Read only" - + AN107 C9 SYSTEM_AN107 - - - - - - - - I "Read only" - + AVCC18_TSU C14 SYSTEM_AVCC18_TSU - - - - - - - - I "Read only" - + AVCC18_USB P10 SYSTEM_AVCC18_USB - - - - - - - - I "Read only" - + AVCC18_USB R10 SYSTEM_AVCC18_USB - - - - - - - - I "Read only" - + BSCANP G2 SYSTEM_BSCANP - - - - - - - - I "Read only" - + EXTAL R7 CGC_EXTAL - - - - - - - - I "Read only" - + EXTCLKIN R6 CGC_EXTCLKIN - - - - - - - - I "Read only" - + MDX P5 SYSTEM_MDX - - - - - - - - IO "Read only" - + P00_0 C4 - ETH2_RXD3 - - Disabled - - "BSC: D15; ETHER_ETH2: ETH2_RXD3; PHOSTIF: HD15; SCI2: DE2; SCI2: SCK2" - None - - + P00_1 D5 - ETH2_RXDV - - Disabled - - "BSC: A13; ETHER_ETH2: ETH2_RXDV_CRSDV_RXCTL; IRQ: IRQ0; MTU35: MTIC5U; SCI2: RXD_MISO2; SCI2: SCL2" - None - - + P00_2 A3 - ETH2_TXEN - - Disabled - - "BSC: RD#; ETHER_ETH2: ETH2_TXEN_TXCTL; MTU35: MTIC5V; SCI2: SDA2; SCI2: TXD_MOSI2; USB_HS: USB_OVRCUR" - None - - + P00_3 B3 - ETH2_REFCLK - - Disabled - - "BSC: RD_WR#; ETHER_ETH2: ETH2_REFCLK; ETHER_ETH2: ETH2_RMII2_REFCLK; IRQ: IRQ1; MTU35: MTIC5W; SCI2: CTS_RTS_SS2#" - None - - + P00_4 A4 - - - - Disabled - - "BSC: WAIT#; DSMIF0: MCLK0; ETHER_ETH2: ETH2_RXER; GPT0: GTIOC0A; IRQ: IRQ13; MTU33: MTIOC3A; PHOSTIF: HWAIT#" - None - - + P00_5 B4 - ETH2_LINK - - Disabled - - "BSC: CS0#; DSMIF0: MDAT0; ETHER_ESC: ESC_PHYLINK0; ETHER_ESC: ESC_PHYLINK2; ETHER_ETHSW: ETHSW_PHYLINK0; ETHER_ETHSW: ETHSW_PHYLINK2; GPT0: GTIOC0B; MTU33: MTIOC3C" - None - - + P00_6 C3 - ETH2_TXCLK - - Disabled - - "BSC: CS5#; ETHER_ETH2: ETH2_TXCLK_TXC; GPT1: GTIOC1A; MTU33: MTIOC3B" - None - - + P00_7 D4 - - - - Disabled - - "BSC: RAS#; GPT2: GTIOC2A; IRQ: IRQ13; MTU34: MTIOC4A" - None - - + P01_0 A2 - - - - Disabled - - "BSC: CAS#; DSMIF1: MCLK1; ETHER_ESC: ESC_MDIO; ETHER_ETHSW: ETHSW_MDIO; ETHER_GMAC: GMAC_MDIO; GPT3: GTIOC3A; MTU34: MTIOC4C; SCI2: CTS2#" - None - - + P01_1 D3 - - - - Disabled - - "BSC: CKE; DSMIF1: MDAT1; ETHER_ESC: ESC_MDC; ETHER_ETHSW: ETHSW_MDC; ETHER_GMAC: GMAC_MDC; GPT1: GTIOC1B; MTU33: MTIOC3D; SCI2: DE2" - None - - + P01_2 B2 - ETH2_TXD3 - - Disabled - - "BSC: CS2#; ETHER_ETH2: ETH2_TXD3; GPT2: GTIOC2B; IRQ: IRQ2; MTU34: MTIOC4B" - None - - + P01_3 C2 - ETH2_TXD2 - - Disabled - - "BSC: AH#; ETHER_ETH2: ETH2_TXD2; GPT3: GTIOC3B; MTU34: MTIOC4D" - None - - + P01_4 E4 - ETH2_TXD1 - - Disabled - - "BSC: WE1#_DQMLU; ETHER_ETH2: ETH2_TXD1; IRQ: IRQ3; MTU_POE3: POE0#" - None - - + P01_5 B1 - ETH2_TXD0 - - Disabled - - "BSC: WE0#_DQMLL; ETHER_ETH2: ETH2_TXD0" - None - - + P01_6 D2 - - - - Disabled - - "BSC: A20; CANFD1: CANTXDP1; ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG1; GPT9: GTIOC9A; MTU31: MTIOC1A; PHOSTIF: HA20; SCI1: CTS1#; TRACE: TRACEDATA0" - None - - + P01_7 C1 - CAN_RX Low - Disabled - - "ADC0: ADTRG0#; BSC: A19; CANFD0: CANRX0; ETHER_ETHSW: ETHSW_LPI1; GPT9: GTIOC9B; MTU31: MTIOC1B; PHOSTIF: HA19; SCI1: SCK1; SPI3: SPI_RSPCK3; TRACE: TRACEDATA1" - I - - + P02_0 E3 - - - - Disabled - - "BSC: A18; CANFD1: CANTX1; ETHER_ETHSW: ETHSW_LPI2; GPT: GTADSML0; IRQ: IRQ4; PHOSTIF: HA18; SCI1: RXD_MISO1; SCI1: SCL1; SPI3: SPI_MISO3; TRACE: TRACEDATA2; USB_HS: USB_OTGID" - None - - + P02_1 D1 - - - - Disabled - - "BSC: A17; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; PHOSTIF: HA17; SCI1: DE1" - None - - + P02_2 F3 - CAN_TX Low - Disabled - - "BSC: A16; CANFD0: CANTX0; ETHER_ETHSW: ETHSW_TDMAOUT0; GPT10: GTIOC10A; IRQ: IRQ14; MTU32: MTIOC2A; MTU_POE3: POE10#; PHOSTIF: HA16; RTC: RTCAT1HZ; SCI1: SDA1; SCI1: TXD_MOSI1; SPI3: SPI_MOSI3" - O - - + P02_3 E1 - - - - Disabled - - "BSC: A15; BSC: AH#; CANFD1: CANRX1; ETHER_ETHSW: ETHSW_TDMAOUT1; GPT10: GTIOC10B; IRQ: IRQ15; MTU32: MTIOC2B; MTU_POE3: POE11#; PHOSTIF: HA15; SCI1: CTS_RTS_SS1#; SPI3: SPI_SSL30" - None - - + P02_4 F4 JTAG/SWD_TDO TDO High - "Peripheral mode" - - "BSC: WE0#_DQMLL; JTAG/SWD: TDO; SCI1: DE1; SPI3: SPI_SSL33" - O - - + P02_5 F2 JTAG/SWD_TDI TDI Low - "Peripheral mode" - - "BSC: WE1#_DQMLU; ETHER_ETHSW: ETHSW_TDMAOUT3; JTAG/SWD: TDI; SCI5: SCK5; SPI3: SPI_SSL31" - I - - + P02_6 F5 JTAG/SWD_TMS_SWDIO TMS High - "Peripheral mode" - - "JTAG/SWD: TMS_SWDIO; SCI5: RXD_MISO5; SCI5: SCL5" - IO - - + P02_7 F1 JTAG/SWD_TCK_SWCLK TCK Low - "Peripheral mode" - - "JTAG/SWD: TCK_SWCLK; SCI5: SDA5; SCI5: TXD_MOSI5" - I - - + P03_0 G3 - ETH_LED4 Low - Disabled - - "BSC: A14; BSC: CS5#; CANFD1: CANTXDP1; GPT: GTADSML1; IRQ: IRQ14; PHOSTIF: HA14; SCI2: SCK2; SPI3: SPI_SSL32; TRACE: TRACEDATA3" - IO - - + P03_5 G1 - - - - Disabled - - "BSC: A12; DSMIF2: MCLK2; ETHER_ETH2: ETH2_CRS; GPT4: GTIOC4A; IRQ: IRQ5; MTU33: MTIOC3A; PHOSTIF: HA12; SCI2: RXD_MISO2; SCI2: SCL2" - None - - + P03_6 G4 - - - - Disabled - - "BSC: A11; DSMIF2: MDAT2; ETHER_ETH2: ETH2_COL; GPT4: GTIOC4B; IRQ: IRQ8; MTU33: MTIOC3B; PHOSTIF: HA11; SCI2: SDA2; SCI2: TXD_MOSI2; SPI1: SPI_SSL13; TRACE: TRACEDATA4" - None - - + P03_7 G5 - - - - Disabled - - "BSC: A10; ETHER_ETH2: ETH2_TXER; GPT5: GTIOC5A; IRQ: IRQ9; MTU33: MTIOC3C; PHOSTIF: HA10; SCI3: SCK3; TRACE: TRACEDATA5" - None - - + P04_0 H1 - - - - Disabled - - "BSC: A9; GPT5: GTIOC5B; MTU33: MTIOC3D; PHOSTIF: HA9; SCI3: RXD_MISO3; SCI3: SCL3; TRACE: TRACEDATA6" - None - - + P04_1 H2 - LED_RED1 Low - Disabled - - "BSC: CKIO; IIC2: IIC_SDA2; PHOSTIF: HCKIO; SCI3: SDA3; SCI3: TXD_MOSI3; SPI0: SPI_MOSI0" - IO - - + P04_4 H4 - ETH_LED6 Low - Disabled - - "BSC: A8; GPT: GTADSMP0; IRQ: IRQ10; MTU_POE3: POE10#; PHOSTIF: HA8; SCI3: CTS3#; SPI1: SPI_RSPCK1; TRACE: TRACEDATA7" - IO - - + P04_5 H3 - - - - Disabled - - "BSC: A7; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT0; PHOSTIF: HA7; SCI3: DE3" - None - - + P04_6 H5 - - - - Disabled - - "BSC: A6; DMAC: DACK; ETHER_ETH1: ETH1_TXER; PHOSTIF: HA6; RTC: RTCAT1HZ" - None - - + P04_7 J1 - - - - Disabled - - "BSC: A5; ETHER_ETH0: ETH0_TXER; ETHER_ETH2: ETH2_TXER; PHOSTIF: HA5; SPI2: SPI_SSL21" - None - - + P05_0 J5 - ETH_LED7 Low - Disabled - - "BSC: A4; CANFD0: CANTXDP0; CMTW0: CMTW0_TOC0; DSMIF3: MCLK3; ETHER_ETH1: ETH1_CRS; GPT6: GTIOC6A; IRQ: IRQ12; MTU34: MTIOC4A; PHOSTIF: HA4; SCI5: CTS_RTS_SS5#; USB_HS: USB_VBUSEN" - IO - - + P05_1 J2 - - - - Disabled - - "BSC: A3; CANFD0: CANRXDP0; CMTW0: CMTW0_TIC1; DSMIF3: MDAT3; ETHER_ETH1: ETH1_COL; GPT6: GTIOC6B; IRQ: IRQ13; MTU34: MTIOC4B; PHOSTIF: HA3; SCI5: CTS5#; USB_HS: USB_EXICEN" - None - - + P05_2 J4 - SCL Low - Disabled - - "BSC: A2; CANFD0: CANRX0; CMTW0: CMTW0_TOC0; DMAC: DREQ; ETHER_ETH0: ETH0_CRS; GPT7: GTIOC7A; GPT_POEG: GTETRGSA; IIC1: IIC_SCL1; IRQ: IRQ14; MTU34: MTIOC4C; PHOSTIF: HA2; SCI5: DE5; USB_HS: USB_VBUSEN" - IO - - + P05_3 J3 - SDA Low - Disabled - - "BSC: A1; CANFD0: CANTX0; CMTW0: CMTW0_TIC0; ETHER_ETH0: ETH0_COL; GPT7: GTIOC7B; GPT_POEG: GTETRGSB; IIC1: IIC_SDA1; IRQ: IRQ15; MTU34: MTIOC4D; MTU_POE3: POE11#; PHOSTIF: HA1; SCI4: SCK4; USB_HS: USB_EXICEN" - IO - - + P05_4 K1 - SW2 - - Disabled - - "BSC: A0; CANFD0: CANTXDP0; DMAC: DACK; ETHER_ETHSW: ETHSW_LPI0; GPT14: GTIOC14A; IRQ: IRQ12; PHOSTIF: HA0; SCI4: RXD_MISO4; SCI4: SCL4; SPI0: SPI_SSL00; USB_HS: USB_OVRCUR" - IO - - + P05_5 K2 - ETH1_LINK - - Disabled - - "CMTW0: CMTW0_TOC1; ETHER_ESC: ESC_PHYLINK1; ETHER_ETHSW: ETHSW_PHYLINK1; GPT14: GTIOC14B; SPI2: SPI_RSPCK2" - None - - + P05_6 K3 - - - - Disabled - - "CMTW1: CMTW1_TIC0; ETHER_ETH1: ETH1_RXER; GPT15: GTIOC15A; IRQ: IRQ12; SPI2: SPI_SSL22" - None - - + P05_7 M1 - ETH1_TXD2 - - Disabled - - "CMTW1: CMTW1_TOC1; ETHER_ETH1: ETH1_TXD2; GPT15: GTIOC15B; SCI4: SDA4; SCI4: TXD_MOSI4; SPI2: SPI_SSL23" - None - - + P06_0 L2 - ETH1_TXD3 - - Disabled - - "CANFD1: CANRX1; CMTW1: CMTW1_TOC0; ETHER_ETH1: ETH1_TXD3; GPT16: GTIOC16A; SCI4: CTS_RTS_SS4#; SPI2: SPI_SSL23" - None - - + P06_1 L3 - ETH1_REFCLK - - Disabled - - "CANFD1: CANTX1; ETHER_ETH1: ETH1_REFCLK; ETHER_ETH1: ETH1_RMII1_REFCLK; GPT16: GTIOC16B; SCI4: CTS4#; SPI2: SPI_SSL22" - None - - + P06_2 M2 - ETH1_TXD1 - - Disabled - - "CANFD1: CANRXDP1; ETHER_ETH1: ETH1_TXD1; GPT17: GTIOC17A" - None - - + P06_3 K4 - ETH1_TXD0 - - Disabled - - "CANFD1: CANTXDP1; CMTW1: CMTW1_TIC1; ETHER_ETH1: ETH1_TXD0; GPT17: GTIOC17B; SCI4: DE4; SPI1: SPI_MISO1" - None - - + P06_4 N1 - ETH1_TXCLK - - Disabled - - "ETHER_ETH1: ETH1_TXCLK_TXC; GPT11: GTIOC11A; SPI1: SPI_MOSI1" - None - - + P06_5 N2 - ETH1_TXEN - - Disabled - - "ETHER_ETH1: ETH1_TXEN_TXCTL; GPT11: GTIOC11B" - None - - + P06_6 L4 - ETH1_RXD0 - - Disabled - - "ETHER_ETH1: ETH1_RXD0; GPT12: GTIOC12A; SPI1: SPI_SSL10" - None - - + P06_7 M3 - ETH1_RXD1 - - Disabled - - "ETHER_ETH1: ETH1_RXD1; GPT12: GTIOC12B; SPI1: SPI_SSL11" - None - - + P07_0 P1 - ETH1_RXD2 - - Disabled - - "ETHER_ETH1: ETH1_RXD2; GPT13: GTIOC13A" - None - - + P07_1 N3 - ETH1_RXD3 - - Disabled - - "ETHER_ETH1: ETH1_RXD3; GPT13: GTIOC13B" - None - - + P07_2 P2 - ETH1_RXDV - - Disabled - - "ETHER_ETH1: ETH1_RXDV_CRSDV_RXCTL" - None - - + P07_3 M4 - ETH1_RXCLK - - Disabled - - "ETHER_ETH1: ETH1_RXCLK_REF_CLK_RXC" - None - - + P07_4 R2 - USB_VBUSIN - - Disabled - - "ADC0: ADTRG0#; IRQ: IRQ1; USB_HS: USB_VBUSIN" - I - - + P08_4 N4 - ETH0_RXD3 - - Disabled - - "ETHER_ETH0: ETH0_RXD3; MTU36: MTIOC6A" - None - - + P08_5 P3 - ETH0_RXDV - - Disabled - - "ETHER_ETH0: ETH0_RXDV_CRSDV_RXCTL; MTU36: MTIOC6B" - None - - + P08_6 M5 - ETH0_RXCLK - - Disabled - - "ETHER_ETH0: ETH0_RXCLK_REF_CLK_RXC; MTU36: MTIOC6C" - None - - + P08_7 N5 - ETH_MDC Low - Disabled - - "ETHER_ESC: ESC_MDC; ETHER_ETHSW: ETHSW_MDC; ETHER_GMAC: GMAC_MDC; MTU36: MTIOC6D" - O - - + P09_0 P4 - ETH_MDIO Low - Disabled - - "ETHER_ESC: ESC_MDIO; ETHER_ETHSW: ETHSW_MDIO; ETHER_GMAC: GMAC_MDIO; MTU37: MTIOC7A" - IO - - + P09_1 R3 - ETH0_REFCLK - - Disabled - - "ETHER_ETH0: ETH0_REFCLK; ETHER_ETH0: ETH0_RMII0_REFCLK; MTU37: MTIOC7B" - None - - + P09_2 N6 - - - - Disabled - - "ETHER_ETH0: ETH0_RXER; IRQ: IRQ0; MTU37: MTIOC7C" - None - - + P09_3 R4 - ETH0_TXD3 - - Disabled - - "ETHER_ETH0: ETH0_TXD3; MTU37: MTIOC7D" - None - - + P09_4 M6 - ETH0_TXD2 - - Disabled - - "ETHER_ETH0: ETH0_TXD2" - None - - + P09_5 N7 - ETH0_TXD1 - - Disabled - - "ETHER_ETH0: ETH0_TXD1" - None - - + P09_6 M7 - ETH0_TXD0 - - Disabled - - "ETHER_ETH0: ETH0_TXD0" - None - - + P09_7 L7 - ETH0_TXCLK - - Disabled - - "ETHER_ETH0: ETH0_TXCLK_TXC" - None - - + P10_0 N8 - ETH0_TXEN - - Disabled - - "ETHER_ETH0: ETH0_TXEN_TXCTL" - None - - + P10_1 M8 - ETH0_RXD0 - - Disabled - - "ETHER_ETH0: ETH0_RXD0" - None - - + P10_2 L8 - ETH0_RXD1 - - Disabled - - "ETHER_ETH0: ETH0_RXD1" - None - - + P10_3 L9 - ETH0_RXD2 - - Disabled - - "ETHER_ETH0: ETH0_RXD2; RTC: RTCAT1HZ" - None - - + P10_4 M9 - ETH0_LINK - - Disabled - - "ETHER_ESC: ESC_PHYLINK0; ETHER_ETHSW: ETHSW_PHYLINK0; IRQ: IRQ11" - None - - + P12_4 N11 - - - - Disabled - - "BSC: D15; ETHER_ETH1: ETH1_CRS; GPT8: GTIOC8B; MBXSEM: MBX_HINT#; MTU38: MTIOC8B; SPI0: SPI_SSL01; TRACE: TRACEDATA0" - None - - + P13_2 L10 - EEPROM_SCL Low - Disabled - - "BSC: A13; BSC: D9; DSMIF4: MCLK4; ETHER_ESC: ESC_I2CCLK; ETHER_ETHSW: ETHSW_PTPOUT2; GPT10: GTIOC10A; IIC0: IIC_SCL0; IRQ: IRQ5; MTU30: MTIOC0A; MTU_POE3: POE8#; SCI1: CTS_RTS_SS1#; SPI0: SPI_MISO0; TRACE: TRACEDATA6" - IO - - + P13_3 N12 - EEPROM_SDA Low - Disabled - - "BSC: D8; BSC: RD#; CMTW1: CMTW1_TOC0; DSMIF4: MDAT4; ETHER_ESC: ESC_I2CDATA; ETHER_ETHSW: ETHSW_PTPOUT3; GPT10: GTIOC10B; IIC0: IIC_SDA0; MTU30: MTIOC0B; MTU30: MTIOC0C; SCI1: CTS1#; SPI0: SPI_RSPCK0; TRACE: TRACEDATA7" - IO - - + P13_4 L12 - ESC_RESETOUT Low - Disabled - - "BSC: A0; ETHER_ESC: ESC_RESETOUT#; GPT8: GTIOC8B; MTU30: MTIOC0D" - IO - - + P13_5 M12 - SW3_Pin2 - - Disabled - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG0; IIC2: IIC_SCL2; MTU3: MTCLKA; SPI1: SPI_RSPCK1; XSPI0: XSPI0_WP1#" - IO - - + P13_6 M13 - SW3_Pin1 - - Disabled - - "ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT0; MTU3: MTCLKB; XSPI0: XSPI0_WP0#" - IO - - + P13_7 M11 - SW3_Pin4 - - Disabled - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_GMAC: GMAC_PTPTRG1; MBXSEM: MBX_HINT#; MTU3: MTCLKC; XSPI0: XSPI0_ECS1#" - IO - - + P14_0 L13 - SW3_Pin3 - - Disabled - - "ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; MTU3: MTCLKD; XSPI0: XSPI0_INT0#" - IO - - + P14_1 L14 - - - - Disabled - - "ETHER_ESC: ESC_LATCH0; ETHER_ESC: ESC_LATCH1; ETHER_ETH1: ETH1_COL; ETHER_GMAC: GMAC_PTPTRG1; GPT8: GTIOC8A; MTU38: MTIOC8A; SHOSTIF: HSPI_IO0; XSPI0: XSPI0_INT1#" - None - - + P14_2 K12 - XSPI0_ECS Low - Disabled - - "ETHER_ETH0: ETH0_CRS; ETHER_ETH2: ETH2_CRS; GPT8: GTIOC8B; IRQ: IRQ6; MTU38: MTIOC8B; SHOSTIF: HSPI_CK; XSPI0: XSPI0_ECS0#" - I - - + P14_3 M14 - - - - Disabled - - "ETHER_ETH0: ETH0_COL; ETHER_ETH2: ETH2_COL; MTU30: MTIOC0A; SHOSTIF: HSPI_IO1; XSPI0: XSPI0_RSTO1#" - None - - + P14_4 J13 - XSPI0_DS Low - Disabled - - "BSC: BS#; ETHER_ESC: ESC_IRQ; MTU30: MTIOC0B; PHOSTIF: HBS#; XSPI0: XSPI0_DS" - IO - - + P14_5 J12 - XSPI0_CKN Low - Disabled - - "BSC: CS3#; MTU_POE3: POE8#; SHOSTIF: HSPI_INT#; XSPI0: XSPI0_CKN" - O - - + P14_6 K13 - XSPI0_CKP Low - Disabled - - "BSC: A21; XSPI0: XSPI0_CKP" - O - - + P14_7 M15 - XSPI0_IO0 Low - Disabled - - "BSC: A22; BSC: BS#; SCI5: SCK5; SPI1: SPI_MISO1; XSPI0: XSPI0_IO0" - IO - - + P15_0 L11 - XSPI0_IO1 Low - Disabled - - "BSC: A23; BSC: CKE; SCI5: RXD_MISO5; SCI5: SCL5; SPI1: SPI_MOSI1; XSPI0: XSPI0_IO1" - IO - - + P15_1 K14 - XSPI0_IO2 Low - Disabled - - "BSC: A24; BSC: CAS#; MTU30: MTIOC0C; SCI5: SDA5; SCI5: TXD_MOSI5; SPI1: SPI_SSL10; XSPI0: XSPI0_IO2" - IO - - + P15_2 K15 - XSPI0_IO3 Low - Disabled - - "BSC: A25; BSC: RAS#; MTU30: MTIOC0D; SCI5: CTS_RTS_SS5#; SPI1: SPI_SSL11; XSPI0: XSPI0_IO3" - IO - - + P15_3 K11 - XSPI0_IO4 Low - Disabled - - "BSC: D11; DSMIF1: MCLK1; MTU38: MTIOC8C; XSPI0: XSPI0_IO4" - IO - - + P15_4 H13 - XSPI0_IO5 Low - Disabled - - "BSC: D12; DSMIF1: MDAT1; MTU38: MTIOC8D; XSPI0: XSPI0_IO5" - IO - - + P15_5 J14 - XSPI0_IO6 Low - Disabled - - "BSC: D13; DSMIF2: MCLK2; XSPI0: XSPI0_IO6" - IO - - + P15_6 H12 - XSPI0_IO7 Low - Disabled - - "BSC: D14; DSMIF2: MDAT2; SPI1: SPI_SSL12; XSPI0: XSPI0_IO7" - IO - - + P15_7 J15 - OSPI_CS Low - Disabled - - "DMAC: TEND; SCI5: CTS5#; SPI1: SPI_SSL13; XSPI0: XSPI0_CS0#" - O - - + P16_0 G13 - ORAM_CS0 Low - Disabled - - "DSMIF3: MCLK3; ETHER_ETH0: ETH0_TXER; ETHER_ETH2: ETH2_REFCLK; SCI0: SDA0; SCI0: TXD_MOSI0; SHOSTIF: HSPI_CS#; SPI3: SPI_MOSI3; XSPI0: XSPI0_CS1#" - O - - + P16_1 H11 - XSPI0_RESET0 Low - Disabled - - "ADC0: ADTRG0#; BSC: CS2#; CMTW0: CMTW0_TOC1; DSMIF3: MDAT3; PHOSTIF: HCS1#; SCI0: RXD_MISO0; SCI0: SCL0; SPI3: SPI_MISO3; XSPI0: XSPI0_RESET0#" - O - - + P16_2 H14 - - - - Disabled - - "IRQ: NMI; PHOSTIF: HERROUT#; SCI0: CTS0#; SHOSTIF: HSPI_IO2; SPI3: SPI_RSPCK3; USB_HS: USB_EXICEN; XSPI0: XSPI0_RESET1#" - None - - + P16_3 G12 - SW1 - - Disabled - - "BSC: CS3#; ETHER_ETH1: ETH1_CRS; ETHER_ETH1: ETH1_TXER; GPT: GTADSMP1; IRQ: IRQ7; SCI0: SCK0; SHOSTIF: HSPI_IO3; SPI3: SPI_SSL30; XSPI0: XSPI0_RSTO0#" - IO - - + P16_5 H15 - UART_USB_TX Low - Disabled - - "BSC: A15; MTU35: MTIC5U; SCI0: SDA0; SCI0: TXD_MOSI0; SHOSTIF: HSPI_IO4" - IO - - + P16_6 G11 - UART_USB_RX Low - Disabled - - "BSC: CS0#; IRQ: IRQ8; MTU35: MTIC5V; PHOSTIF: HCS0#; SCI0: RXD_MISO0; SCI0: SCL0; SHOSTIF: HSPI_IO5" - IO - - + P16_7 G14 - - - - Disabled - - "BSC: A13; MTU35: MTIC5W; PHOSTIF: HA13; SCI0: SCK0; XSPI1: XSPI1_IO0" - None - - + P17_0 F12 - - - - Disabled - - "ETHER_ESC: ESC_IRQ; SCI0: CTS_RTS_SS0#; XSPI1: XSPI1_IO1" - None - - + P17_3 F14 - LED_RED2 Low - Disabled - - "ADC1: ADTRG1#; DMAC: DREQ; GPT_POEG: GTETRGA; MTU_POE3: POE0#; SPI3: SPI_SSL31; TRACE: TRACECTL; XSPI1: XSPI1_IO2" - IO - - + P17_4 F13 - - - - Disabled - - "DMAC: DACK; GPT0: GTIOC0A; GPT_POEG: GTETRGB; MTU33: MTIOC3C; SCI3: CTS3#; SPI3: SPI_SSL32; TRACE: TRACECLK; XSPI1: XSPI1_IO3" - None - - + P17_5 F15 - USB_OVRCUR Low - Disabled - - "DMAC: TEND; GPT0: GTIOC0B; GPT_POEG: GTETRGC; MTU33: MTIOC3A; USB_HS: USB_OVRCUR" - I - - + P17_6 G15 - - - - Disabled - - "BSC: RD_WR#; GPT1: GTIOC1A; MTU33: MTIOC3B; PHOSTIF: HWRSTB#; SCI3: SCK3; XSPI1: XSPI1_DS" - None - - + P17_7 E15 - SCI_RXD Low - Disabled - - "BSC: RD#; DMAC: DACK; GPT2: GTIOC2A; GPT3: GTIOC3A; MTU34: MTIOC4A; MTU34: MTIOC4C; PHOSTIF: HRD#; SCI3: RXD_MISO3; SCI3: SCL3; XSPI1: XSPI1_CKP" - IO - - + P18_0 E14 - SCI_TXD Low - Disabled - - "BSC: WE0#_DQMLL; GPT2: GTIOC2A; GPT3: GTIOC3A; MTU34: MTIOC4A; MTU34: MTIOC4C; PHOSTIF: HWR0#; SCI3: SDA3; SCI3: TXD_MOSI3; SHOSTIF: HSPI_IO6" - IO - - + P18_1 D15 - - - - Disabled - - "ADC1: ADTRG1#; BSC: WE1#_DQMLU; GPT1: GTIOC1B; IRQ: IRQ10; MTU33: MTIOC3D; PHOSTIF: HWR1#; SCI3: CTS_RTS_SS3#; SHOSTIF: HSPI_IO7" - None - - + P18_2 D14 - LED_GREEN Low - Disabled - - "BSC: BS#; ETHER_ETH1: ETH1_COL; GPT2: GTIOC2B; GPT3: GTIOC3B; IIC2: IIC_SDA2; MTU34: MTIOC4B; MTU34: MTIOC4D; SCI0: SCK0; XSPI1: XSPI1_CS0#" - IO - - + P18_3 E13 - - - - Disabled - - "BSC: CKE; CANFD1: CANRXDP1; CMTW1: CMTW1_TIC1; ETHER_ETH2: ETH2_CRS; GPT2: GTIOC2B; GPT3: GTIOC3B; IRQ: IRQ0; MTU34: MTIOC4B; MTU34: MTIOC4D; XSPI1: XSPI1_IO4" - None - - + P18_4 E12 - SCK Low - Disabled - - "BSC: CAS#; CANFD0: CANTX0; ETHER_ETH1: ETH1_CRS; IRQ: IRQ1; MTU35: MTIC5U; SCI4: SDA4; SCI4: TXD_MOSI4; SPI2: SPI_RSPCK2; XSPI1: XSPI1_IO5" - IO - - + P18_5 D13 - MOSI Low - Disabled - - "BSC: RAS#; CANFD0: CANRX0; ETHER_ETH2: ETH2_COL; MTU35: MTIC5V; SCI4: RXD_MISO4; SCI4: SCL4; SPI2: SPI_MOSI2; TRACE: TRACECTL; XSPI1: XSPI1_IO6" - IO - - + P18_6 C15 - MISO Low - Disabled - - "ADC0: ADTRG0#; ETHER_ETH1: ETH1_COL; IIC2: IIC_SCL2; IRQ: IRQ11; MTU35: MTIC5W; SCI4: DE4; SCI4: SCK4; SPI2: SPI_MISO2; TRACE: TRACECLK; XSPI1: XSPI1_IO7" - IO - - + P19_0 B15 - USB_VBUSEN Low - Disabled - - "USB_HS: USB_VBUSEN" - O - - + P20_1 B9 - ETH_LED2_MDV0 - - Disabled - - "ETHER_ESC: ESC_LINKACT0; ETHER_ETHSW: ETHSW_PTPOUT3; ETHER_ETHSW: ETHSW_TDMAOUT0" - None - - + P20_2 D8 - ETH_LED0_MDV1 - - Disabled - - "ETHER_ESC: ESC_LEDRUN; ETHER_ESC: ESC_LEDSTER; ETHER_ETHSW: ETHSW_PTPOUT2; ETHER_ETHSW: ETHSW_TDMAOUT1; SCI3: DE3" - None - - + P20_3 D9 - ETH_LED1_MDV2 - - Disabled - - "ETHER_ESC: ESC_LEDERR; ETHER_ETHSW: ETHSW_PTPOUT1; ETHER_ETHSW: ETHSW_TDMAOUT2" - None - - + P20_4 A9 - ETH_LED3_MDV3 - - Disabled - - "ETHER_ESC: ESC_LINKACT1; ETHER_ETHSW: ETHSW_PTPOUT0; ETHER_ETHSW: ETHSW_TDMAOUT3" - None - - + P21_1 B8 - CS Low - Disabled - - "BSC: D0; CMTW0: CMTW0_TIC0; DSMIF0: MCLK0; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; GPT14: GTIOC14A; IIC1: IIC_SCL1; MTU36: MTIOC6A; PHOSTIF: HD0; SCI5: SCK5; SHOSTIF: HSPI_INT#; SPI2: SPI_SSL20; TRACE: TRACEDATA0" - IO - - + P21_2 C8 - - - - Disabled - - "BSC: D1; CMTW0: CMTW0_TIC1; DSMIF0: MDAT0; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; GPT14: GTIOC14B; IIC1: IIC_SDA1; MTU36: MTIOC6B; PHOSTIF: HD1; SCI5: RXD_MISO5; SCI5: SCL5; SPI2: SPI_MISO2; TRACE: TRACEDATA1" - None - - + P21_3 A8 - - - - Disabled - - "BSC: D2; DSMIF1: MCLK1; GPT15: GTIOC15A; IRQ: NMI; MTU36: MTIOC6C; PHOSTIF: HD2; SCI5: SDA5; SCI5: TXD_MOSI5; SPI3: SPI_SSL33; TRACE: TRACEDATA2" - None - - + P21_4 E7 - - - - Disabled - - "BSC: D3; DSMIF1: MDAT1; ETHER_ESC: ESC_SYNC0; ETHER_ESC: ESC_SYNC1; ETHER_ETHSW: ETHSW_PTPOUT1; GPT15: GTIOC15B; MBXSEM: MBX_HINT#; MTU36: MTIOC6D; PHOSTIF: HD3; SCI5: CTS_RTS_SS5#; SPI0: SPI_SSL02; TRACE: TRACEDATA3" - None - - + P21_5 C7 - - - - Disabled - - "ADC1: ADTRG1#; BSC: D4; CMTW1: CMTW1_TOC1; DSMIF2: MCLK2; GPT16: GTIOC16A; IRQ: IRQ6; MTU37: MTIOC7A; PHOSTIF: HD4; SCI5: CTS5#; SPI0: SPI_MISO0; TRACE: TRACEDATA4" - None - - + P21_6 D7 - - - - Disabled - - "BSC: D5; DMAC: TEND; DSMIF2: MDAT2; GPT16: GTIOC16B; IRQ: IRQ9; MTU37: MTIOC7B; PHOSTIF: HD5; SCI0: CTS0#; TRACE: TRACEDATA5" - None - - + P21_7 B7 - - - - Disabled - - "BSC: D6; DMAC: DREQ; DSMIF3: MCLK3; GPT17: GTIOC17A; IRQ: IRQ10; MTU37: MTIOC7C; PHOSTIF: HD6; SCI0: DE0; TRACE: TRACEDATA6" - None - - + P22_0 A7 - - - - Disabled - - "BSC: D7; DSMIF3: MDAT3; GPT17: GTIOC17B; IRQ: IRQ15; MTU37: MTIOC7D; PHOSTIF: HD7; SCI5: DE5; TRACE: TRACEDATA7" - None - - + P22_1 A6 - ETH_LED5 Low - Disabled - - "BSC: D8; ETHER_ESC: ESC_LINKACT2; GPT_POEG: GTETRGB; MTU_POE3: POE4#; PHOSTIF: HD8; SCI4: CTS_RTS_SS4#; TRACE: TRACECTL" - IO - - + P22_2 C6 - - - - Disabled - - "BSC: D9; DSMIF1: MCLK1; GPT_POEG: GTETRGSA; IRQ: IRQ4; MTU38: MTIOC8C; PHOSTIF: HD9; SPI1: SPI_SSL12; TRACE: TRACECLK" - None - - + P22_3 B6 - LED_ORANGE Low - Disabled - - "BSC: D10; GPT_POEG: GTETRGSB; MTU38: MTIOC8D; PHOSTIF: HD10; SCI5: RXD_MISO5; SCI5: SCL5" - IO - - + P23_7 D6 - ETH2_RXD0 - - Disabled - - "BSC: BS#; BSC: D11; DSMIF4: MCLK4; ETHER_ETH2: ETH2_RXD0; GPT_POEG: GTETRGA; MTU30: MTIOC0A; PHOSTIF: HD11; SCI1: SCK1" - None - - + P24_0 A5 - ETH2_RXD1 - - Disabled - - "BSC: CKE; BSC: D12; DMAC: DREQ; DSMIF4: MDAT4; ETHER_ETH2: ETH2_RXD1; GPT_POEG: GTETRGB; MTU30: MTIOC0B; PHOSTIF: HD12; SCI1: RXD_MISO1; SCI1: SCL1" - None - - + P24_1 B5 - ETH2_RXCLK - - Disabled - - "BSC: CAS#; BSC: D13; DSMIF5: MCLK5; ETHER_ETH2: ETH2_RXCLK_REF_CLK_RXC; GPT_POEG: GTETRGC; MTU30: MTIOC0C; MTU_POE3: POE8#; PHOSTIF: HD13" - None - - + P24_2 C5 - ETH2_RXD2 - - Disabled - - "BSC: D14; BSC: RAS#; DSMIF5: MDAT5; ETHER_ETH2: ETH2_RXD2; GPT_POEG: GTETRGD; MTU30: MTIOC0D; PHOSTIF: HD14; SCI1: SDA1; SCI1: TXD_MOSI1" - None - - + RES# P6 SYSTEM_RES# - - - - - - - - I "Read only" - + TRST# E2 SYSTEM_TRST# - - - - - - - - I "Read only" - + USB_DM P13 SYSTEM_USB_DM - - - - - - - - IO "Read only" - + USB_DP R13 SYSTEM_USB_DP - - - - - - - - IO "Read only" - + USB_RREF P15 SYSTEM_USB_RREF - - - - - - - - I "Read only" - + VCC1833_0 L6 SYSTEM_VCC1833_0 - - - - - - - - I "Read only" - + VCC1833_1 K5 SYSTEM_VCC1833_1 - - - - - - - - I "Read only" - + VCC1833_2 E5 SYSTEM_VCC1833_2 - - - - - - - - I "Read only" - + VCC1833_3 J11 SYSTEM_VCC1833_3 - - - - - - - - I "Read only" - + VCC1833_4 F11 SYSTEM_VCC1833_4 - - - - - - - - I "Read only" - + VCC18_ADC0 E11 SYSTEM_VCC18_ADC0 - - - - - - - - I "Read only" - + VCC18_ADC1 E9 SYSTEM_VCC18_ADC1 - - - - - - - - I "Read only" - + VCC18_PLL0 P9 SYSTEM_VCC18_PLL0 - - - - - - - - I "Read only" - + VCC18_PLL1 N9 SYSTEM_VCC18_PLL1 - - - - - - - - I "Read only" - + VCC18_USB P11 SYSTEM_VCC18_USB - - - - - - - - I "Read only" - + VCC33 E6 SYSTEM_VCC33 - - - - - - - - I "Read only" - + VCC33 E8 SYSTEM_VCC33 - - - - - - - - I "Read only" - + VCC33 M10 SYSTEM_VCC33 - - - - - - - - I "Read only" - + VCC33 L5 SYSTEM_VCC33 - - - - - - - - I "Read only" - + VCC33_USB R11 SYSTEM_VCC33_USB - - - - - - - - I "Read only" - + VDD H10 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD G10 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD F6 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD F8 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD F9 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD G6 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD F10 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD H6 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD J6 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD K6 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD K7 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD K8 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD K10 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD P7 SYSTEM_VDD - - - - - - - - I "Read only" - + VDD J10 SYSTEM_VDD - - - - - - - - I "Read only" - + VREFH0 C11 SYSTEM_VREFH0 - - - - - - - - I "Read only" - + VREFH1 C10 SYSTEM_VREFH1 - - - - - - - - I "Read only" - + VSS A1 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS R1 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS A10 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS R5 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS A15 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS R9 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS F7 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS G7 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS G8 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS G9 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS N10 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS H7 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS N14 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS H8 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS H9 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS E10 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS J7 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS J8 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS J9 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS K9 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS D10 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS D11 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS L1 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS L15 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS P8 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS R15 SYSTEM_VSS - - - - - - - - I "Read only" - + VSS_ADC D12 SYSTEM_VSS_ADC - - - - - - - - I "Read only" - + VSS_USB P12 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + VSS_USB P14 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + VSS_USB N13 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + VSS_USB N15 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + VSS_USB R12 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + VSS_USB R14 SYSTEM_VSS_USB - - - - - - - - I "Read only" - + XTAL R8 CGC_XTAL - - - - - - - - O "Read only" - + + User Events + + User Event Links + + Module "I/O Port (r_ioport)" + Parameter Checking: Default (BSP) + + Module "Memory config check" + MPU/MMU Type: MPU + + Module "UART (r_sci_uart)" + Parameter Checking: Default (BSP) + FIFO Support: Enable + DMAC Support: Disable + Flow Control Support: Disable + Multiplex Interrupt: Disabled + + HAL + Instance "g_ioport I/O Port (r_ioport)" + General: Name: g_ioport + ELC Output Port Group 1: Trigger Source: Disabled + ELC Output Port Group 1: Port Selection: + ELC Output Port Group 1: Output Operation: Low output + ELC Output Port Group 2: Trigger Source: Disabled + ELC Output Port Group 2: Port Selection: + ELC Output Port Group 2: Output Operation: Low output + ELC Input Port Group 1: Trigger Source: Disabled + ELC Input Port Group 1: Event Link Control: Disabled + ELC Input Port Group 1: Port Selection: + ELC Input Port Group 1: Edge Detection: Rising edge + ELC Input Port Group 1: Buffer Overwrite: Disabled + ELC Input Port Group 1: Buffer Initial Value: P16_0: Low input + ELC Input Port Group 1: Buffer Initial Value: P16_1: Low input + ELC Input Port Group 1: Buffer Initial Value: P16_2: Low input + ELC Input Port Group 1: Buffer Initial Value: P16_3: Low input + ELC Input Port Group 1: Buffer Initial Value: P16_5: Low input + ELC Input Port Group 1: Buffer Initial Value: P16_6: Low input + ELC Input Port Group 1: Buffer Initial Value: P16_7: Low input + ELC Input Port Group 2: Trigger Source: Disabled + ELC Input Port Group 2: Event Link Control: Disabled + ELC Input Port Group 2: Port Selection: + ELC Input Port Group 2: Edge Detection: Rising edge + ELC Input Port Group 2: Buffer Overwrite: Disabled + ELC Input Port Group 2: Buffer Initial Value: P18_0: Low input + ELC Input Port Group 2: Buffer Initial Value: P18_1: Low input + ELC Input Port Group 2: Buffer Initial Value: P18_2: Low input + ELC Input Port Group 2: Buffer Initial Value: P18_3: Low input + ELC Input Port Group 2: Buffer Initial Value: P18_4: Low input + ELC Input Port Group 2: Buffer Initial Value: P18_5: Low input + ELC Input Port Group 2: Buffer Initial Value: P18_6: Low input + ELC Single Port 0: Common: Event Link Control: Disabled + ELC Single Port 0: Common: Event Direction: Output direction + ELC Single Port 0: Common: Port selection: P16_0 + ELC Single Port 0: Output Direction Setting: Trigger Source: Disabled + ELC Single Port 0: Output Direction Setting: Output Operation: Low output + ELC Single Port 0: Input Direction Setting: Edge Detection: Rising edge + ELC Single Port 1: Common: Event Link Control: Disabled + ELC Single Port 1: Common: Event Direction: Output direction + ELC Single Port 1: Common: Port selection: P16_0 + ELC Single Port 1: Output Direction Setting: Trigger Source: Disabled + ELC Single Port 1: Output Direction Setting: Output Operation: Low output + ELC Single Port 1: Input Direction Setting: Edge Detection: Rising edge + ELC Single Port 2: Common: Event Link Control: Disabled + ELC Single Port 2: Common: Event Direction: Output direction + ELC Single Port 2: Common: Port selection: P16_0 + ELC Single Port 2: Output Direction Setting: Trigger Source: Disabled + ELC Single Port 2: Output Direction Setting: Output Operation: Low output + ELC Single Port 2: Input Direction Setting: Edge Detection: Rising edge + ELC Single Port 3: Common: Event Link Control: Disabled + ELC Single Port 3: Common: Event Direction: Output direction + ELC Single Port 3: Common: Port selection: P16_0 + ELC Single Port 3: Output Direction Setting: Trigger Source: Disabled + ELC Single Port 3: Output Direction Setting: Output Operation: Low output + ELC Single Port 3: Input Direction Setting: Edge Detection: Rising edge + + Instance "Memory config check" + Instance "g_uart0 UART (r_sci_uart)" + General: Name: g_uart0 + General: Channel: 0 + General: Data Bits: 8bits + General: Parity: None + General: Stop Bits: 1bit + Baud: Baud Rate: 115200 + Baud: Baud Rate Modulation: Disabled + Baud: Max Error (%): 5 + Baud: Synchronizer Bypass: Not Bypassed (The operation clock is SCInASYNCCLK) + Flow Control: CTS/RTS Selection: Hardware RTS + Flow Control: Software RTS Port: Disabled + Flow Control: Software RTS Pin: Disabled + Extra: Clock Source: Internal Clock + Extra: Start bit detection: Falling Edge + Extra: Noise Filter: Disable + Extra: Receive FIFO Trigger Level: Max + Extra: RS-485: DE Pin: Disable + Extra: RS-485: DE Pin Polarity: Active High + Extra: RS-485: DE Pin Assertion Time: 1 + Extra: RS-485: DE Pin Negation Time: 1 + Interrupts: Callback: user_uart0_callback + Interrupts: Receive Interrupt Priority: Priority 12 + Interrupts: Transmit Data Empty Interrupt Priority: Priority 12 + Interrupts: Transmit End Interrupt Priority: Priority 12 + Interrupts: Error Interrupt Priority: Priority 12 + diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/SConscript b/bsp/renesas/rzn2l_rsk/rzn_cfg/SConscript new file mode 100644 index 00000000000..8d63460c645 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/SConscript @@ -0,0 +1,19 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm']: + Return('group') +elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): + if GetOption('target') != 'mdk5': + src = Glob('*.c') + CPPPATH = [cwd+'/fsp_cfg', cwd + '/fsp_cfg/bsp'] + +group += DefineGroup('rz_cfg', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/board_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 00000000000..b6d6335983d --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,25 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "../../../rzn/board/rzn2l_rsk/board.h" + #define BSP_CFG_XSPI0_X1_BOOT (1) + #define BSP_CFG_CACHE_FLG (0x00000000) + #define BSP_CFG_CS0BCR_V_WRAPCFG_V (0x00000000) + #define BSP_CFG_CS0WCR_V_COMCFG_V (0x00000000) + #define BSP_CFG_DUMMY0_BMCFG_V (0x00000000) + #define BSP_CFG_BSC_FLG_xSPI_FLG (0x00000000) + #define BSP_CFG_LDR_ADDR_NML (0x6000004C) + #define BSP_CFG_LDR_SIZE_NML (0x00006000) + #define BSP_CFG_DEST_ADDR_NML (0x00102000) + #define BSP_CFG_DUMMY1 (0x00000000) + #define BSP_CFG_DUMMY2 (0x00000000) + #define BSP_CFG_DUMMY3_CSSCTL_V (0x0000003F) + #define BSP_CFG_DUMMY4_LIOCFGCS0_V (0x00070000) + #define BSP_CFG_DUMMY5 (0x00000000) + #define BSP_CFG_DUMMY6 (0x00000000) + #define BSP_CFG_DUMMY7 (0x00000000) + #define BSP_CFG_DUMMY8 (0x00000000) + #define BSP_CFG_DUMMY9 (0x00000000) + #define BSP_CFG_DUMMY10_ACCESS_SPEED (0x00000006) + #define BSP_CFG_CHECK_SUM (0xE0A8) +#endif /* BOARD_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 00000000000..989932e34d3 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,37 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define FSP_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #undef FSP_NOT_DEFINED + #define BSP_CFG_MCU_VCC_MV (3300) + + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PORT_PROTECT (1) + + #define BSP_CFG_SOFT_RESET_SUPPORTED (0) + #define BSP_CFG_EARLY_INIT (0) + + #define BSP_CFG_MULTIPLEX_INTERRUPT_SUPPORTED (0) + #if BSP_CFG_MULTIPLEX_INTERRUPT_SUPPORTED + #define BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE BSP_INTERRUPT_ENABLE + #define BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE BSP_INTERRUPT_DISABLE + #else + #define BSP_CFG_MULTIPLEX_INTERRUPT_ENABLE + #define BSP_CFG_MULTIPLEX_INTERRUPT_DISABLE + #endif +#endif /* BSP_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 00000000000..d0551c4e16a --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,14 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_STACK_FIQ_BYTES (0x400) + #define BSP_CFG_STACK_IRQ_BYTES (0x400) + #define BSP_CFG_STACK_ABT_BYTES (0x400) + #define BSP_CFG_STACK_UND_BYTES (0x400) + #define BSP_CFG_STACK_SYS_BYTES (0x400) + #define BSP_CFG_STACK_SVC_BYTES (0x400) + #define BSP_CFG_HEAP_BYTES (0x2000) + + #define BSP_CFG_C_RUNTIME_INIT (1) + #define BSP_CFG_USE_TFU_MATHLIB ((1)) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h new file mode 100644 index 00000000000..359058b8e74 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_memory_cfg.h @@ -0,0 +1,552 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_MEMORY_CFG_H_ +#define BSP_MCU_DEVICE_MEMORY_CFG_H_ +#define BSP_CFG_MPU0_READ0 (0) + #define BSP_CFG_MPU0_WRITE0 (0) + #define BSP_CFG_MPU0_STADD0 (0x00000000) + #define BSP_CFG_MPU0_ENDADD0 (0x00000C00) + #define BSP_CFG_MPU0_READ1 (0) + #define BSP_CFG_MPU0_WRITE1 (0) + #define BSP_CFG_MPU0_STADD1 (0x00000000) + #define BSP_CFG_MPU0_ENDADD1 (0x00000C00) + #define BSP_CFG_MPU0_READ2 (0) + #define BSP_CFG_MPU0_WRITE2 (0) + #define BSP_CFG_MPU0_STADD2 (0x00000000) + #define BSP_CFG_MPU0_ENDADD2 (0x00000C00) + #define BSP_CFG_MPU0_READ3 (0) + #define BSP_CFG_MPU0_WRITE3 (0) + #define BSP_CFG_MPU0_STADD3 (0x00000000) + #define BSP_CFG_MPU0_ENDADD3 (0x00000C00) + #define BSP_CFG_MPU0_READ4 (0) + #define BSP_CFG_MPU0_WRITE4 (0) + #define BSP_CFG_MPU0_STADD4 (0x00000000) + #define BSP_CFG_MPU0_ENDADD4 (0x00000C00) + #define BSP_CFG_MPU0_READ5 (0) + #define BSP_CFG_MPU0_WRITE5 (0) + #define BSP_CFG_MPU0_STADD5 (0x00000000) + #define BSP_CFG_MPU0_ENDADD5 (0x00000C00) + #define BSP_CFG_MPU0_READ6 (0) + #define BSP_CFG_MPU0_WRITE6 (0) + #define BSP_CFG_MPU0_STADD6 (0x00000000) + #define BSP_CFG_MPU0_ENDADD6 (0x00000C00) + #define BSP_CFG_MPU0_READ7 (0) + #define BSP_CFG_MPU0_WRITE7 (0) + #define BSP_CFG_MPU0_STADD7 (0x00000000) + #define BSP_CFG_MPU0_ENDADD7 (0x00000C00) + #define BSP_CFG_MPU1_READ0 (0) + #define BSP_CFG_MPU1_WRITE0 (0) + #define BSP_CFG_MPU1_STADD0 (0x00000000) + #define BSP_CFG_MPU1_ENDADD0 (0x00000C00) + #define BSP_CFG_MPU1_READ1 (0) + #define BSP_CFG_MPU1_WRITE1 (0) + #define BSP_CFG_MPU1_STADD1 (0x00000000) + #define BSP_CFG_MPU1_ENDADD1 (0x00000C00) + #define BSP_CFG_MPU1_READ2 (0) + #define BSP_CFG_MPU1_WRITE2 (0) + #define BSP_CFG_MPU1_STADD2 (0x00000000) + #define BSP_CFG_MPU1_ENDADD2 (0x00000C00) + #define BSP_CFG_MPU1_READ3 (0) + #define BSP_CFG_MPU1_WRITE3 (0) + #define BSP_CFG_MPU1_STADD3 (0x00000000) + #define BSP_CFG_MPU1_ENDADD3 (0x00000C00) + #define BSP_CFG_MPU1_READ4 (0) + #define BSP_CFG_MPU1_WRITE4 (0) + #define BSP_CFG_MPU1_STADD4 (0x00000000) + #define BSP_CFG_MPU1_ENDADD4 (0x00000C00) + #define BSP_CFG_MPU1_READ5 (0) + #define BSP_CFG_MPU1_WRITE5 (0) + #define BSP_CFG_MPU1_STADD5 (0x00000000) + #define BSP_CFG_MPU1_ENDADD5 (0x00000C00) + #define BSP_CFG_MPU1_READ6 (0) + #define BSP_CFG_MPU1_WRITE6 (0) + #define BSP_CFG_MPU1_STADD6 (0x00000000) + #define BSP_CFG_MPU1_ENDADD6 (0x00000C00) + #define BSP_CFG_MPU1_READ7 (0) + #define BSP_CFG_MPU1_WRITE7 (0) + #define BSP_CFG_MPU1_STADD7 (0x00000000) + #define BSP_CFG_MPU1_ENDADD7 (0x00000C00) + #define BSP_CFG_MPU2_READ0 (0) + #define BSP_CFG_MPU2_WRITE0 (0) + #define BSP_CFG_MPU2_STADD0 (0x00000000) + #define BSP_CFG_MPU2_ENDADD0 (0x00000C00) + #define BSP_CFG_MPU2_READ1 (0) + #define BSP_CFG_MPU2_WRITE1 (0) + #define BSP_CFG_MPU2_STADD1 (0x00000000) + #define BSP_CFG_MPU2_ENDADD1 (0x00000C00) + #define BSP_CFG_MPU2_READ2 (0) + #define BSP_CFG_MPU2_WRITE2 (0) + #define BSP_CFG_MPU2_STADD2 (0x00000000) + #define BSP_CFG_MPU2_ENDADD2 (0x00000C00) + #define BSP_CFG_MPU2_READ3 (0) + #define BSP_CFG_MPU2_WRITE3 (0) + #define BSP_CFG_MPU2_STADD3 (0x00000000) + #define BSP_CFG_MPU2_ENDADD3 (0x00000C00) + #define BSP_CFG_MPU2_READ4 (0) + #define BSP_CFG_MPU2_WRITE4 (0) + #define BSP_CFG_MPU2_STADD4 (0x00000000) + #define BSP_CFG_MPU2_ENDADD4 (0x00000C00) + #define BSP_CFG_MPU2_READ5 (0) + #define BSP_CFG_MPU2_WRITE5 (0) + #define BSP_CFG_MPU2_STADD5 (0x00000000) + #define BSP_CFG_MPU2_ENDADD5 (0x00000C00) + #define BSP_CFG_MPU2_READ6 (0) + #define BSP_CFG_MPU2_WRITE6 (0) + #define BSP_CFG_MPU2_STADD6 (0x00000000) + #define BSP_CFG_MPU2_ENDADD6 (0x00000C00) + #define BSP_CFG_MPU2_READ7 (0) + #define BSP_CFG_MPU2_WRITE7 (0) + #define BSP_CFG_MPU2_STADD7 (0x00000000) + #define BSP_CFG_MPU2_ENDADD7 (0x00000C00) + #define BSP_CFG_MPU3_READ0 (0) + #define BSP_CFG_MPU3_WRITE0 (0) + #define BSP_CFG_MPU3_STADD0 (0x00000000) + #define BSP_CFG_MPU3_ENDADD0 (0x00000000) + #define BSP_CFG_MPU3_READ1 (0) + #define BSP_CFG_MPU3_WRITE1 (0) + #define BSP_CFG_MPU3_STADD1 (0x00000000) + #define BSP_CFG_MPU3_ENDADD1 (0x00000000) + #define BSP_CFG_MPU3_READ2 (0) + #define BSP_CFG_MPU3_WRITE2 (0) + #define BSP_CFG_MPU3_STADD2 (0x00000000) + #define BSP_CFG_MPU3_ENDADD2 (0x00000000) + #define BSP_CFG_MPU3_READ3 (0) + #define BSP_CFG_MPU3_WRITE3 (0) + #define BSP_CFG_MPU3_STADD3 (0x00000000) + #define BSP_CFG_MPU3_ENDADD3 (0x00000000) + #define BSP_CFG_MPU3_READ4 (0) + #define BSP_CFG_MPU3_WRITE4 (0) + #define BSP_CFG_MPU3_STADD4 (0x00000000) + #define BSP_CFG_MPU3_ENDADD4 (0x00000000) + #define BSP_CFG_MPU3_READ5 (0) + #define BSP_CFG_MPU3_WRITE5 (0) + #define BSP_CFG_MPU3_STADD5 (0x00000000) + #define BSP_CFG_MPU3_ENDADD5 (0x00000000) + #define BSP_CFG_MPU3_READ6 (0) + #define BSP_CFG_MPU3_WRITE6 (0) + #define BSP_CFG_MPU3_STADD6 (0x00000000) + #define BSP_CFG_MPU3_ENDADD6 (0x00000000) + #define BSP_CFG_MPU3_READ7 (0) + #define BSP_CFG_MPU3_WRITE7 (0) + #define BSP_CFG_MPU3_STADD7 (0x00000000) + #define BSP_CFG_MPU3_ENDADD7 (0x00000000) + #define BSP_CFG_MPU4_READ0 (0) + #define BSP_CFG_MPU4_WRITE0 (0) + #define BSP_CFG_MPU4_STADD0 (0x00000000) + #define BSP_CFG_MPU4_ENDADD0 (0x00000000) + #define BSP_CFG_MPU4_READ1 (0) + #define BSP_CFG_MPU4_WRITE1 (0) + #define BSP_CFG_MPU4_STADD1 (0x00000000) + #define BSP_CFG_MPU4_ENDADD1 (0x00000000) + #define BSP_CFG_MPU4_READ2 (0) + #define BSP_CFG_MPU4_WRITE2 (0) + #define BSP_CFG_MPU4_STADD2 (0x00000000) + #define BSP_CFG_MPU4_ENDADD2 (0x00000000) + #define BSP_CFG_MPU4_READ3 (0) + #define BSP_CFG_MPU4_WRITE3 (0) + #define BSP_CFG_MPU4_STADD3 (0x00000000) + #define BSP_CFG_MPU4_ENDADD3 (0x00000000) + #define BSP_CFG_MPU4_READ4 (0) + #define BSP_CFG_MPU4_WRITE4 (0) + #define BSP_CFG_MPU4_STADD4 (0x00000000) + #define BSP_CFG_MPU4_ENDADD4 (0x00000000) + #define BSP_CFG_MPU4_READ5 (0) + #define BSP_CFG_MPU4_WRITE5 (0) + #define BSP_CFG_MPU4_STADD5 (0x00000000) + #define BSP_CFG_MPU4_ENDADD5 (0x00000000) + #define BSP_CFG_MPU4_READ6 (0) + #define BSP_CFG_MPU4_WRITE6 (0) + #define BSP_CFG_MPU4_STADD6 (0x00000000) + #define BSP_CFG_MPU4_ENDADD6 (0x00000000) + #define BSP_CFG_MPU4_READ7 (0) + #define BSP_CFG_MPU4_WRITE7 (0) + #define BSP_CFG_MPU4_STADD7 (0x00000000) + #define BSP_CFG_MPU4_ENDADD7 (0x00000000) + #define BSP_CFG_MPU6_READ0 (0) + #define BSP_CFG_MPU6_WRITE0 (0) + #define BSP_CFG_MPU6_STADD0 (0x00000000) + #define BSP_CFG_MPU6_ENDADD0 (0x00000C00) + #define BSP_CFG_MPU6_READ1 (0) + #define BSP_CFG_MPU6_WRITE1 (0) + #define BSP_CFG_MPU6_STADD1 (0x00000000) + #define BSP_CFG_MPU6_ENDADD1 (0x00000C00) + #define BSP_CFG_MPU6_READ2 (0) + #define BSP_CFG_MPU6_WRITE2 (0) + #define BSP_CFG_MPU6_STADD2 (0x00000000) + #define BSP_CFG_MPU6_ENDADD2 (0x00000C00) + #define BSP_CFG_MPU6_READ3 (0) + #define BSP_CFG_MPU6_WRITE3 (0) + #define BSP_CFG_MPU6_STADD3 (0x00000000) + #define BSP_CFG_MPU6_ENDADD3 (0x00000C00) + #define BSP_CFG_MPU6_READ4 (0) + #define BSP_CFG_MPU6_WRITE4 (0) + #define BSP_CFG_MPU6_STADD4 (0x00000000) + #define BSP_CFG_MPU6_ENDADD4 (0x00000C00) + #define BSP_CFG_MPU6_READ5 (0) + #define BSP_CFG_MPU6_WRITE5 (0) + #define BSP_CFG_MPU6_STADD5 (0x00000000) + #define BSP_CFG_MPU6_ENDADD5 (0x00000C00) + #define BSP_CFG_MPU6_READ6 (0) + #define BSP_CFG_MPU6_WRITE6 (0) + #define BSP_CFG_MPU6_STADD6 (0x00000000) + #define BSP_CFG_MPU6_ENDADD6 (0x00000C00) + #define BSP_CFG_MPU6_READ7 (0) + #define BSP_CFG_MPU6_WRITE7 (0) + #define BSP_CFG_MPU6_STADD7 (0x00000000) + #define BSP_CFG_MPU6_ENDADD7 (0x00000C00) + #define BSP_CFG_MPU7_READ0 (0) + #define BSP_CFG_MPU7_WRITE0 (0) + #define BSP_CFG_MPU7_STADD0 (0x00000000) + #define BSP_CFG_MPU7_ENDADD0 (0x00000000) + #define BSP_CFG_MPU7_READ1 (0) + #define BSP_CFG_MPU7_WRITE1 (0) + #define BSP_CFG_MPU7_STADD1 (0x00000000) + #define BSP_CFG_MPU7_ENDADD1 (0x00000000) + #define BSP_CFG_MPU7_READ2 (0) + #define BSP_CFG_MPU7_WRITE2 (0) + #define BSP_CFG_MPU7_STADD2 (0x00000000) + #define BSP_CFG_MPU7_ENDADD2 (0x00000000) + #define BSP_CFG_MPU7_READ3 (0) + #define BSP_CFG_MPU7_WRITE3 (0) + #define BSP_CFG_MPU7_STADD3 (0x00000000) + #define BSP_CFG_MPU7_ENDADD3 (0x00000000) + #define BSP_CFG_MPU7_READ4 (0) + #define BSP_CFG_MPU7_WRITE4 (0) + #define BSP_CFG_MPU7_STADD4 (0x00000000) + #define BSP_CFG_MPU7_ENDADD4 (0x00000000) + #define BSP_CFG_MPU7_READ5 (0) + #define BSP_CFG_MPU7_WRITE5 (0) + #define BSP_CFG_MPU7_STADD5 (0x00000000) + #define BSP_CFG_MPU7_ENDADD5 (0x00000000) + #define BSP_CFG_MPU7_READ6 (0) + #define BSP_CFG_MPU7_WRITE6 (0) + #define BSP_CFG_MPU7_STADD6 (0x00000000) + #define BSP_CFG_MPU7_ENDADD6 (0x00000000) + #define BSP_CFG_MPU7_READ7 (0) + #define BSP_CFG_MPU7_WRITE7 (0) + #define BSP_CFG_MPU7_STADD7 (0x00000000) + #define BSP_CFG_MPU7_ENDADD7 (0x00000000) + #define BSP_CFG_MPU8_READ0 (0) + #define BSP_CFG_MPU8_WRITE0 (0) + #define BSP_CFG_MPU8_STADD0 (0x00000000) + #define BSP_CFG_MPU8_ENDADD0 (0x00000000) + #define BSP_CFG_MPU8_READ1 (0) + #define BSP_CFG_MPU8_WRITE1 (0) + #define BSP_CFG_MPU8_STADD1 (0x00000000) + #define BSP_CFG_MPU8_ENDADD1 (0x00000000) + #define BSP_CFG_MPU8_READ2 (0) + #define BSP_CFG_MPU8_WRITE2 (0) + #define BSP_CFG_MPU8_STADD2 (0x00000000) + #define BSP_CFG_MPU8_ENDADD2 (0x00000000) + #define BSP_CFG_MPU8_READ3 (0) + #define BSP_CFG_MPU8_WRITE3 (0) + #define BSP_CFG_MPU8_STADD3 (0x00000000) + #define BSP_CFG_MPU8_ENDADD3 (0x00000000) + #define BSP_CFG_MPU8_READ4 (0) + #define BSP_CFG_MPU8_WRITE4 (0) + #define BSP_CFG_MPU8_STADD4 (0x00000000) + #define BSP_CFG_MPU8_ENDADD4 (0x00000000) + #define BSP_CFG_MPU8_READ5 (0) + #define BSP_CFG_MPU8_WRITE5 (0) + #define BSP_CFG_MPU8_STADD5 (0x00000000) + #define BSP_CFG_MPU8_ENDADD5 (0x00000000) + #define BSP_CFG_MPU8_READ6 (0) + #define BSP_CFG_MPU8_WRITE6 (0) + #define BSP_CFG_MPU8_STADD6 (0x00000000) + #define BSP_CFG_MPU8_ENDADD6 (0x00000000) + #define BSP_CFG_MPU8_READ7 (0) + #define BSP_CFG_MPU8_WRITE7 (0) + #define BSP_CFG_MPU8_STADD7 (0x00000000) + #define BSP_CFG_MPU8_ENDADD7 (0x00000000) + + #define BSP_CFG_CPU_MPU_ATTR0_TYPE (BSP_TYPE_NORMAL_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR0_INNER (BSP_WRITE_BACK_NON_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR0_INNER_READ (BSP_READ_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR0_INNER_WRITE (BSP_WRITE_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR0_OUTER (BSP_WRITE_BACK_NON_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR0_OUTER_READ (BSP_READ_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR0_OUTER_WRITE (BSP_WRITE_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR0_DEVICE_TYPE (BSP_DEVICE_NGNRNE) + + #define BSP_CFG_CPU_MPU_ATTR1_TYPE (BSP_TYPE_NORMAL_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR1_INNER (BSP_WRITE_NON_THROUGH) + #define BSP_CFG_CPU_MPU_ATTR1_INNER_READ (BSP_READ_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR1_INNER_WRITE (BSP_WRITE_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR1_OUTER (BSP_WRITE_NON_THROUGH) + #define BSP_CFG_CPU_MPU_ATTR1_OUTER_READ (BSP_READ_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR1_OUTER_WRITE (BSP_WRITE_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR1_DEVICE_TYPE (BSP_DEVICE_NGNRNE) + + #define BSP_CFG_CPU_MPU_ATTR2_TYPE (BSP_TYPE_NORMAL_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR2_INNER (BSP_WRITE_NON_THROUGH) + #define BSP_CFG_CPU_MPU_ATTR2_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR2_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR2_OUTER (BSP_WRITE_NON_THROUGH) + #define BSP_CFG_CPU_MPU_ATTR2_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR2_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR2_DEVICE_TYPE (BSP_DEVICE_NGNRNE) + + #define BSP_CFG_CPU_MPU_ATTR3_TYPE (BSP_TYPE_NORMAL_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR3_INNER (BSP_NON_CACHEABLE) + #define BSP_CFG_CPU_MPU_ATTR3_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR3_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR3_OUTER (BSP_NON_CACHEABLE) + #define BSP_CFG_CPU_MPU_ATTR3_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR3_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR3_DEVICE_TYPE (BSP_DEVICE_NGNRNE) + + #define BSP_CFG_CPU_MPU_ATTR4_TYPE (BSP_TYPE_DEVICE_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR4_INNER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR4_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR4_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR4_OUTER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR4_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR4_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR4_DEVICE_TYPE (BSP_DEVICE_NGNRNE) + + #define BSP_CFG_CPU_MPU_ATTR5_TYPE (BSP_TYPE_DEVICE_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR5_INNER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR5_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR5_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR5_OUTER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR5_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR5_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR5_DEVICE_TYPE (BSP_DEVICE_NGNRE) + + #define BSP_CFG_CPU_MPU_ATTR6_TYPE (BSP_TYPE_DEVICE_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR6_INNER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR6_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR6_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR6_OUTER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR6_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR6_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR6_DEVICE_TYPE (BSP_DEVICE_NGRE) + + #define BSP_CFG_CPU_MPU_ATTR7_TYPE (BSP_TYPE_DEVICE_MEMORY) + #define BSP_CFG_CPU_MPU_ATTR7_INNER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR7_INNER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR7_INNER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR7_OUTER (BSP_WRITE_THROUGH_TRANSIENT) + #define BSP_CFG_CPU_MPU_ATTR7_OUTER_READ (BSP_READ_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR7_OUTER_WRITE (BSP_WRITE_NOT_ALLOCATE) + #define BSP_CFG_CPU_MPU_ATTR7_DEVICE_TYPE (BSP_DEVICE_GRE) + + /* Region00 : ATCM */ + #define BSP_CFG_EL1_MPU_REGION00_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION00_LIMIT (0x0001FFFF) + #define BSP_CFG_EL1_MPU_REGION00_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION00_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION00_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION00_ATTRINDEX (BSP_ATTRINDEX3) + #define BSP_CFG_EL1_MPU_REGION00_ENABLE (BSP_REGION_ENABLE) + + /* Region01 : BTCM */ + #define BSP_CFG_EL1_MPU_REGION01_BASE (0x00100000) + #define BSP_CFG_EL1_MPU_REGION01_LIMIT (0x0011FFFF) + #define BSP_CFG_EL1_MPU_REGION01_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION01_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION01_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION01_ATTRINDEX (BSP_ATTRINDEX3) + #define BSP_CFG_EL1_MPU_REGION01_ENABLE (BSP_REGION_ENABLE) + + /* Region02 : System RAM */ + #define BSP_CFG_EL1_MPU_REGION02_BASE (0x10000000) + #define BSP_CFG_EL1_MPU_REGION02_LIMIT (0x1017FFFF) + #define BSP_CFG_EL1_MPU_REGION02_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION02_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION02_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION02_ATTRINDEX (BSP_ATTRINDEX1) + #define BSP_CFG_EL1_MPU_REGION02_ENABLE (BSP_REGION_ENABLE) + + /* Region03 : Mirror area of System RAM */ + #define BSP_CFG_EL1_MPU_REGION03_BASE (0x30000000) + #define BSP_CFG_EL1_MPU_REGION03_LIMIT (0x3017FFFF) + #define BSP_CFG_EL1_MPU_REGION03_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION03_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION03_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION03_ATTRINDEX (BSP_ATTRINDEX3) + #define BSP_CFG_EL1_MPU_REGION03_ENABLE (BSP_REGION_ENABLE) + + /* Region04 : Mirror area of external address space */ + #define BSP_CFG_EL1_MPU_REGION04_BASE (0x40000000) + #define BSP_CFG_EL1_MPU_REGION04_LIMIT (0x5FFFFFFF) + #define BSP_CFG_EL1_MPU_REGION04_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION04_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION04_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION04_ATTRINDEX (BSP_ATTRINDEX3) + #define BSP_CFG_EL1_MPU_REGION04_ENABLE (BSP_REGION_ENABLE) + + /* Region05 : External address space */ + #define BSP_CFG_EL1_MPU_REGION05_BASE (0x60000000) + #define BSP_CFG_EL1_MPU_REGION05_LIMIT (0x7FFFFFFF) + #define BSP_CFG_EL1_MPU_REGION05_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION05_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION05_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION05_ATTRINDEX (BSP_ATTRINDEX1) + #define BSP_CFG_EL1_MPU_REGION05_ENABLE (BSP_REGION_ENABLE) + + /* Region06 : Non-Safety Peripheral */ + #define BSP_CFG_EL1_MPU_REGION06_BASE (0x80000000) + #define BSP_CFG_EL1_MPU_REGION06_LIMIT (0x80FFFFFF) + #define BSP_CFG_EL1_MPU_REGION06_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION06_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION06_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION06_ATTRINDEX (BSP_ATTRINDEX5) + #define BSP_CFG_EL1_MPU_REGION06_ENABLE (BSP_REGION_ENABLE) + + /* Region07 : Safety Peripheral */ + #define BSP_CFG_EL1_MPU_REGION07_BASE (0x81000000) + #define BSP_CFG_EL1_MPU_REGION07_LIMIT (0x81FFFFFF) + #define BSP_CFG_EL1_MPU_REGION07_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION07_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION07_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION07_ATTRINDEX (BSP_ATTRINDEX5) + #define BSP_CFG_EL1_MPU_REGION07_ENABLE (BSP_REGION_ENABLE) + + /* Region08 : LLPP Peripheral */ + #define BSP_CFG_EL1_MPU_REGION08_BASE (0x90000000) + #define BSP_CFG_EL1_MPU_REGION08_LIMIT (0x901FFFFF) + #define BSP_CFG_EL1_MPU_REGION08_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION08_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION08_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION08_ATTRINDEX (BSP_ATTRINDEX5) + #define BSP_CFG_EL1_MPU_REGION08_ENABLE (BSP_REGION_ENABLE) + + /* Region09 : GIC0 */ + #define BSP_CFG_EL1_MPU_REGION09_BASE (0x94000000) + #define BSP_CFG_EL1_MPU_REGION09_LIMIT (0x941FFFFF) + #define BSP_CFG_EL1_MPU_REGION09_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION09_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION09_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION09_ATTRINDEX (BSP_ATTRINDEX4) + #define BSP_CFG_EL1_MPU_REGION09_ENABLE (BSP_REGION_ENABLE) + + /* Region10 : Debug Private */ + #define BSP_CFG_EL1_MPU_REGION10_BASE (0xC0000000) + #define BSP_CFG_EL1_MPU_REGION10_LIMIT (0xC0FFFFFF) + #define BSP_CFG_EL1_MPU_REGION10_SH (BSP_OUTER_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION10_AP (BSP_EL1RW_EL0RW) + #define BSP_CFG_EL1_MPU_REGION10_XN (BSP_EXECUTE_NEVER) + #define BSP_CFG_EL1_MPU_REGION10_ATTRINDEX (BSP_ATTRINDEX4) + #define BSP_CFG_EL1_MPU_REGION10_ENABLE (BSP_REGION_ENABLE) + + /* Region11 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION11_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION11_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION11_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION11_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION11_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION11_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION11_ENABLE (BSP_REGION_DISABLE) + + /* Region12 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION12_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION12_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION12_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION12_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION12_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION12_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION12_ENABLE (BSP_REGION_DISABLE) + + /* Region13 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION13_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION13_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION13_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION13_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION13_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION13_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION13_ENABLE (BSP_REGION_DISABLE) + + /* Region14 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION14_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION14_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION14_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION14_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION14_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION14_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION14_ENABLE (BSP_REGION_DISABLE) + + /* Region15 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION15_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION15_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION15_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION15_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION15_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION15_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION15_ENABLE (BSP_REGION_DISABLE) + + /* Region16 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION16_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION16_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION16_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION16_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION16_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION16_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION16_ENABLE (BSP_REGION_DISABLE) + + /* Region17 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION17_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION17_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION17_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION17_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION17_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION17_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION17_ENABLE (BSP_REGION_DISABLE) + + /* Region18 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION18_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION18_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION18_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION18_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION18_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION18_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION18_ENABLE (BSP_REGION_DISABLE) + + /* Region19 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION19_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION19_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION19_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION19_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION19_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION19_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION19_ENABLE (BSP_REGION_DISABLE) + + /* Region20 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION20_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION20_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION20_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION20_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION20_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION20_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION20_ENABLE (BSP_REGION_DISABLE) + + /* Region21 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION21_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION21_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION21_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION21_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION21_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION21_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION21_ENABLE (BSP_REGION_DISABLE) + + /* Region22 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION22_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION22_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION22_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION22_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION22_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION22_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION22_ENABLE (BSP_REGION_DISABLE) + + /* Region23 : Not Used */ + #define BSP_CFG_EL1_MPU_REGION23_BASE (0x00000000) + #define BSP_CFG_EL1_MPU_REGION23_LIMIT (0x00000000) + #define BSP_CFG_EL1_MPU_REGION23_SH (BSP_NON_SHAREABLE) + #define BSP_CFG_EL1_MPU_REGION23_AP (BSP_EL1RW_EL0NO) + #define BSP_CFG_EL1_MPU_REGION23_XN (BSP_EXECUTE_ENABLE) + #define BSP_CFG_EL1_MPU_REGION23_ATTRINDEX (BSP_ATTRINDEX0) + #define BSP_CFG_EL1_MPU_REGION23_ENABLE (BSP_REGION_DISABLE) + + #define BSP_CFG_SCTLR_BR_BIT (BSP_BG_REGION_DISABLE) + #define BSP_CFG_SCTLR_I_BIT (BSP_ICACHE_ENABLE) + #define BSP_CFG_SCTLR_C_BIT (BSP_DATACACHE_ENABLE) +#endif /* BSP_MCU_DEVICE_MEMORY_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 00000000000..70e28786cb9 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,12 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R9A07G084M04GBG + #define BSP_ATCM_SIZE_BYTES (131072) + #define BSP_BTCM_SIZE_BYTES (131072) + #define BSP_SYSTEM_RAM_SIZE_BYTES (1572864) + #define BSP_PACKAGE_FBGA + #define BSP_PACKAGE_PINS (225) + + #define BSP_CFG_CORE_CR52 (0) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 00000000000..3bfed56a45b --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,15 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "bsp_mcu_device_memory_cfg.h" + #include "../../../rzn/fsp/src/bsp/mcu/rzn2l/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_API_OVERRIDE "../../src/bsp/mcu/rzn2l/bsp_override.h" + #define BSP_MCU_GROUP_RZN2L (1) + #define BSP_LOCO_HZ (240000) + #define BSP_GLOBAL_SYSTEM_COUNTER_CLOCK_HZ (25000000) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (32) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (448) +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_memory_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_memory_cfg.h new file mode 100644 index 00000000000..baaa5be87a3 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_memory_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MEMORY_CFG_H_ +#define BSP_MEMORY_CFG_H_ +#define BSP_MPU_SUPPORT +#endif /* BSP_MEMORY_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 00000000000..c0d922b3a00 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,105 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" +#define ETH2_RXD3 (BSP_IO_PORT_00_PIN_0) +#define ETH2_RXDV (BSP_IO_PORT_00_PIN_1) +#define ETH2_TXEN (BSP_IO_PORT_00_PIN_2) +#define ETH2_REFCLK (BSP_IO_PORT_00_PIN_3) +#define ETH2_LINK (BSP_IO_PORT_00_PIN_5) +#define ETH2_TXCLK (BSP_IO_PORT_00_PIN_6) +#define ETH2_TXD3 (BSP_IO_PORT_01_PIN_2) +#define ETH2_TXD2 (BSP_IO_PORT_01_PIN_3) +#define ETH2_TXD1 (BSP_IO_PORT_01_PIN_4) +#define ETH2_TXD0 (BSP_IO_PORT_01_PIN_5) +#define CAN_RX (BSP_IO_PORT_01_PIN_7) +#define CAN_TX (BSP_IO_PORT_02_PIN_2) +#define TDO (BSP_IO_PORT_02_PIN_4) +#define TDI (BSP_IO_PORT_02_PIN_5) +#define TMS (BSP_IO_PORT_02_PIN_6) +#define TCK (BSP_IO_PORT_02_PIN_7) +#define ETH_LED4 (BSP_IO_PORT_03_PIN_0) +#define LED_RED1 (BSP_IO_PORT_04_PIN_1) +#define ETH_LED6 (BSP_IO_PORT_04_PIN_4) +#define ETH_LED7 (BSP_IO_PORT_05_PIN_0) +#define SCL (BSP_IO_PORT_05_PIN_2) +#define SDA (BSP_IO_PORT_05_PIN_3) +#define SW2 (BSP_IO_PORT_05_PIN_4) +#define ETH1_LINK (BSP_IO_PORT_05_PIN_5) +#define ETH1_TXD2 (BSP_IO_PORT_05_PIN_7) +#define ETH1_TXD3 (BSP_IO_PORT_06_PIN_0) +#define ETH1_REFCLK (BSP_IO_PORT_06_PIN_1) +#define ETH1_TXD1 (BSP_IO_PORT_06_PIN_2) +#define ETH1_TXD0 (BSP_IO_PORT_06_PIN_3) +#define ETH1_TXCLK (BSP_IO_PORT_06_PIN_4) +#define ETH1_TXEN (BSP_IO_PORT_06_PIN_5) +#define ETH1_RXD0 (BSP_IO_PORT_06_PIN_6) +#define ETH1_RXD1 (BSP_IO_PORT_06_PIN_7) +#define ETH1_RXD2 (BSP_IO_PORT_07_PIN_0) +#define ETH1_RXD3 (BSP_IO_PORT_07_PIN_1) +#define ETH1_RXDV (BSP_IO_PORT_07_PIN_2) +#define ETH1_RXCLK (BSP_IO_PORT_07_PIN_3) +#define USB_VBUSIN (BSP_IO_PORT_07_PIN_4) +#define ETH0_RXD3 (BSP_IO_PORT_08_PIN_4) +#define ETH0_RXDV (BSP_IO_PORT_08_PIN_5) +#define ETH0_RXCLK (BSP_IO_PORT_08_PIN_6) +#define ETH_MDC (BSP_IO_PORT_08_PIN_7) +#define ETH_MDIO (BSP_IO_PORT_09_PIN_0) +#define ETH0_REFCLK (BSP_IO_PORT_09_PIN_1) +#define ETH0_TXD3 (BSP_IO_PORT_09_PIN_3) +#define ETH0_TXD2 (BSP_IO_PORT_09_PIN_4) +#define ETH0_TXD1 (BSP_IO_PORT_09_PIN_5) +#define ETH0_TXD0 (BSP_IO_PORT_09_PIN_6) +#define ETH0_TXCLK (BSP_IO_PORT_09_PIN_7) +#define ETH0_TXEN (BSP_IO_PORT_10_PIN_0) +#define ETH0_RXD0 (BSP_IO_PORT_10_PIN_1) +#define ETH0_RXD1 (BSP_IO_PORT_10_PIN_2) +#define ETH0_RXD2 (BSP_IO_PORT_10_PIN_3) +#define ETH0_LINK (BSP_IO_PORT_10_PIN_4) +#define EEPROM_SCL (BSP_IO_PORT_13_PIN_2) +#define EEPROM_SDA (BSP_IO_PORT_13_PIN_3) +#define ESC_RESETOUT (BSP_IO_PORT_13_PIN_4) +#define SW3_Pin2 (BSP_IO_PORT_13_PIN_5) +#define SW3_Pin1 (BSP_IO_PORT_13_PIN_6) +#define SW3_Pin4 (BSP_IO_PORT_13_PIN_7) +#define SW3_Pin3 (BSP_IO_PORT_14_PIN_0) +#define XSPI0_ECS (BSP_IO_PORT_14_PIN_2) +#define XSPI0_DS (BSP_IO_PORT_14_PIN_4) +#define XSPI0_CKN (BSP_IO_PORT_14_PIN_5) +#define XSPI0_CKP (BSP_IO_PORT_14_PIN_6) +#define XSPI0_IO0 (BSP_IO_PORT_14_PIN_7) +#define XSPI0_IO1 (BSP_IO_PORT_15_PIN_0) +#define XSPI0_IO2 (BSP_IO_PORT_15_PIN_1) +#define XSPI0_IO3 (BSP_IO_PORT_15_PIN_2) +#define XSPI0_IO4 (BSP_IO_PORT_15_PIN_3) +#define XSPI0_IO5 (BSP_IO_PORT_15_PIN_4) +#define XSPI0_IO6 (BSP_IO_PORT_15_PIN_5) +#define XSPI0_IO7 (BSP_IO_PORT_15_PIN_6) +#define OSPI_CS (BSP_IO_PORT_15_PIN_7) +#define ORAM_CS0 (BSP_IO_PORT_16_PIN_0) +#define XSPI0_RESET0 (BSP_IO_PORT_16_PIN_1) +#define SW1 (BSP_IO_PORT_16_PIN_3) +#define UART_USB_TX (BSP_IO_PORT_16_PIN_5) +#define UART_USB_RX (BSP_IO_PORT_16_PIN_6) +#define LED_RED2 (BSP_IO_PORT_17_PIN_3) +#define USB_OVRCUR (BSP_IO_PORT_17_PIN_5) +#define SCI_RXD (BSP_IO_PORT_17_PIN_7) +#define SCI_TXD (BSP_IO_PORT_18_PIN_0) +#define LED_GREEN (BSP_IO_PORT_18_PIN_2) +#define SCK (BSP_IO_PORT_18_PIN_4) +#define MOSI (BSP_IO_PORT_18_PIN_5) +#define MISO (BSP_IO_PORT_18_PIN_6) +#define USB_VBUSEN (BSP_IO_PORT_19_PIN_0) +#define ETH_LED2_MDV0 (BSP_IO_PORT_20_PIN_1) +#define ETH_LED0_MDV1 (BSP_IO_PORT_20_PIN_2) +#define ETH_LED1_MDV2 (BSP_IO_PORT_20_PIN_3) +#define ETH_LED3_MDV3 (BSP_IO_PORT_20_PIN_4) +#define CS (BSP_IO_PORT_21_PIN_1) +#define ETH_LED5 (BSP_IO_PORT_22_PIN_1) +#define LED_ORANGE (BSP_IO_PORT_22_PIN_3) +#define ETH2_RXD0 (BSP_IO_PORT_23_PIN_7) +#define ETH2_RXD1 (BSP_IO_PORT_24_PIN_0) +#define ETH2_RXCLK (BSP_IO_PORT_24_PIN_1) +#define ETH2_RXD2 (BSP_IO_PORT_24_PIN_2) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RSK+RZN2L */ +#endif /* BSP_PIN_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/r_ioport_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 00000000000..d2688bf5ba3 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/r_sci_uart_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/r_sci_uart_cfg.h new file mode 100644 index 00000000000..fe4cc09bf17 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_cfg/fsp_cfg/r_sci_uart_cfg.h @@ -0,0 +1,16 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_UART_CFG_FIFO_SUPPORT (1) +#define SCI_UART_CFG_DMAC_SUPPORTED (0) +#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) +#define SCI_UART_CFG_MULTIPLEX_INTERRUPT_SUPPORTED (0) +#if SCI_UART_CFG_MULTIPLEX_INTERRUPT_SUPPORTED + #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE BSP_INTERRUPT_ENABLE + #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE BSP_INTERRUPT_DISABLE +#else + #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_ENABLE + #define SCI_UART_CFG_MULTIPLEX_INTERRUPT_DISABLE +#endif +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_gen/SConscript b/bsp/renesas/rzn2l_rsk/rzn_gen/SConscript new file mode 100644 index 00000000000..33e4f94e073 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_gen/SConscript @@ -0,0 +1,19 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +from gcc import * + +cwd = GetCurrentDir() +src = [] +group = [] +CPPPATH = [] + +if rtconfig.PLATFORM in ['iccarm']: + Return('group') +elif rtconfig.PLATFORM in GetGCCLikePLATFORM(): + if GetOption('target') != 'mdk5': + src = Glob('*.c') + CPPPATH = [cwd, ] + +group = DefineGroup('rz_gen', src, depend = [''], CPPPATH = CPPPATH) +Return('group') diff --git a/bsp/renesas/rzn2l_rsk/rzn_gen/bsp_clock_cfg.h b/bsp/renesas/rzn2l_rsk/rzn_gen/bsp_clock_cfg.h new file mode 100644 index 00000000000..eb168da8f5d --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_gen/bsp_clock_cfg.h @@ -0,0 +1,42 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_MAIN_CLOCK_HZ (25000000) /* Main Clock: 25MHz */ +#define BSP_CFG_LOCO_ENABLE (BSP_CLOCKS_LOCO_ENABLE) /* LOCO Enabled */ +#define BSP_CFG_PLL1 (BSP_CLOCKS_PLL1_INITIAL) /* PLL1 is initial state */ +#define BSP_CFG_PHYSEL (BSP_CLOCKS_PHYSEL_MAINOSC_DIV) /* Ethernet Clock src: Main clock oscillator */ +#define BSP_CFG_CLMA0_ENABLE (BSP_CLOCKS_CLMA0_ENABLE) /* CLMA0 Enabled */ +#define BSP_CFG_CLMA0MASK (BSP_CLOCKS_CLMA0_ERROR_NOT_MASK) /* CLMA0 error not mask */ +#define BSP_CFG_CLMA3MASK (BSP_CLOCKS_CLMA3_ERROR_NOT_MASK) /* CLMA3 error not mask */ +#define BSP_CFG_CLMA1MASK (BSP_CLOCKS_CLMA1_ERROR_MASK) /* CLMA1 error mask */ +#define BSP_CFG_CLMA3_ENABLE (BSP_CLOCKS_CLMA3_ENABLE) /* CLMA3 Enabled */ +#define BSP_CFG_CLMA1_ENABLE (BSP_CLOCKS_CLMA1_ENABLE) /* CLMA1 Enabled */ +#define BSP_CFG_CLMA2_ENABLE (BSP_CLOCKS_CLMA2_ENABLE) /* CLMA2 Enabled */ +#define BSP_CFG_CLMA0_CMPL (1) /* CLMA0 CMPL 1 */ +#define BSP_CFG_CLMA1_CMPL (1) /* CLMA1 CMPL 1 */ +#define BSP_CFG_CLMA2_CMPL (1) /* CLMA2 CMPL 1 */ +#define BSP_CFG_CLMA3_CMPL (1) /* CLMA3 CMPL 1 */ +#define BSP_CFG_CLMASEL (BSP_CLOCKS_CLMASEL_LOCO) /* Alternative clock: LOCO */ +#define BSP_CFG_CLMA0_CMPH (1023) /* CLMA0 CMPH 1023 */ +#define BSP_CFG_CLMA1_CMPH (1023) /* CLMA1 CMPH 1023 */ +#define BSP_CFG_CLMA2_CMPH (1023) /* CLMA2 CMPH 1023 */ +#define BSP_CFG_CLMA3_CMPH (1023) /* CLMA3 CMPH 1023 */ +#define BSP_CFG_DIVSELSUB (BSP_CLOCKS_DIVSELSUB_0) /* ICLK 200MHz */ +#define BSP_CFG_FSELCPU0 (BSP_CLOCKS_FSELCPU0_ICLK_MUL2) /* CPU0CLK Mulx2 */ +#define BSP_CFG_CKIO (BSP_CLOCKS_CKIO_ICLK_DIV4) /* CKIO Div/4 */ +#define BSP_CFG_SCI0ASYNCCLK (BSP_CLOCKS_SCI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI0ASYNCCLK: 96MHz */ +#define BSP_CFG_SCI1ASYNCCLK (BSP_CLOCKS_SCI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI1ASYNCCLK: 96MHz */ +#define BSP_CFG_SCI2ASYNCCLK (BSP_CLOCKS_SCI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI2ASYNCCLK: 96MHz */ +#define BSP_CFG_SCI3ASYNCCLK (BSP_CLOCKS_SCI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI3ASYNCCLK: 96MHz */ +#define BSP_CFG_SCI4ASYNCCLK (BSP_CLOCKS_SCI4_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI4ASYNCCLK: 96MHz */ +#define BSP_CFG_SCI5ASYNCCLK (BSP_CLOCKS_SCI5_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SCI5ASYNCCLK: 96MHz */ +#define BSP_CFG_SPI0ASYNCCLK (BSP_CLOCKS_SPI0_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI0ASYNCCLK: 96MHz */ +#define BSP_CFG_SPI1ASYNCCLK (BSP_CLOCKS_SPI1_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI1ASYNCCLK: 96MHz */ +#define BSP_CFG_SPI2ASYNCCLK (BSP_CLOCKS_SPI2_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI2ASYNCCLK: 96MHz */ +#define BSP_CFG_SPI3ASYNCCLK (BSP_CLOCKS_SPI3_ASYNCHRONOUS_SERIAL_CLOCK_96_MHZ) /* SPI3ASYNCCLK: 96MHz */ +#define BSP_CFG_FSELCANFD (BSP_CLOCKS_CANFD_CLOCK_40_MHZ) /* PCLKCAN 40MHz */ +#define BSP_CFG_FSELXSPI0_DIVSELXSPI0 (BSP_CLOCKS_XSPI0_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK0 12.5MHz */ +#define BSP_CFG_FSELXSPI1_DIVSELXSPI1 (BSP_CLOCKS_XSPI1_CLOCK_DIV0_12_5_MHZ) /* XSPI_CLK1 12.5MHz */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_gen/common_data.c b/bsp/renesas/rzn2l_rsk/rzn_gen/common_data.c new file mode 100644 index 00000000000..f9b7a5039f4 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_gen/common_data.c @@ -0,0 +1,75 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +/** IOPORT interface configuration for event link **/ + const ioport_extend_cfg_t g_ioport_cfg_extend = + { + .port_group_output_cfg[IOPORT_PORT_GROUP_1] = + { + .pin_select = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE), + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW + }, + .port_group_output_cfg[IOPORT_PORT_GROUP_2] = + { + .pin_select = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE), + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW + }, + .port_group_input_cfg[IOPORT_PORT_GROUP_1] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .pin_select = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE), + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE, + .overwrite_control = IOPORT_EVENT_CONTROL_DISABLE, + .buffer_init_value = IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 7U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 6U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 5U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 3U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 2U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 1U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW + }, + .port_group_input_cfg[IOPORT_PORT_GROUP_2] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .pin_select = (uint8_t)( IOPORT_EVENT_PIN_SELECTION_NONE), + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE, + .overwrite_control = IOPORT_EVENT_CONTROL_DISABLE, + .buffer_init_value = IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 6U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 5U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 4U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 3U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 2U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW << 1U | IOPORT_EVENT_INITIAL_BUFFER_VALUE_LOW + }, + .single_port_cfg[IOPORT_SINGLE_PORT_0] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .direction = IOPORT_EVENT_DIRECTION_OUTPUT, + .port_num = (uint16_t)BSP_IO_PORT_16_PIN_0, + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW, + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE + }, + .single_port_cfg[IOPORT_SINGLE_PORT_1] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .direction = IOPORT_EVENT_DIRECTION_OUTPUT, + .port_num = (uint16_t)BSP_IO_PORT_16_PIN_0, + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW, + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE + }, + .single_port_cfg[IOPORT_SINGLE_PORT_2] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .direction = IOPORT_EVENT_DIRECTION_OUTPUT, + .port_num = (uint16_t)BSP_IO_PORT_16_PIN_0, + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW, + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE + }, + .single_port_cfg[IOPORT_SINGLE_PORT_3] = + { + .event_control = IOPORT_EVENT_CONTROL_DISABLE, + .direction = IOPORT_EVENT_DIRECTION_OUTPUT, + .port_num = (uint16_t)BSP_IO_PORT_16_PIN_0, + .operation = IOPORT_EVENT_OUTPUT_OPERATION_LOW, + .edge_detection = IOPORT_EVENT_DETECTION_RISING_EDGE + } + }; + +ioport_instance_ctrl_t g_ioport_ctrl; + +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg + }; +void g_common_init(void) { +} diff --git a/bsp/renesas/rzn2l_rsk/rzn_gen/common_data.h b/bsp/renesas/rzn2l_rsk/rzn_gen/common_data.h new file mode 100644 index 00000000000..e2eb70836ba --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_gen/common_data.h @@ -0,0 +1,16 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_gen/hal_data.c b/bsp/renesas/rzn2l_rsk/rzn_gen/hal_data.c new file mode 100644 index 00000000000..2ddb428c13d --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_gen/hal_data.c @@ -0,0 +1,110 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" +sci_uart_instance_ctrl_t g_uart0_ctrl; + + #define FSP_NOT_DEFINED (1) + #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) + + /* If the transfer module is DMAC, define a DMAC transfer callback. */ + extern void sci_uart_tx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl); + + void g_uart0_tx_transfer_callback (transfer_callback_args_t * p_args) + { + FSP_PARAMETER_NOT_USED(p_args); + sci_uart_tx_dmac_callback(&g_uart0_ctrl); + } + #endif + + #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) + + /* If the transfer module is DMAC, define a DMAC transfer callback. */ + extern void sci_uart_rx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl); + + void g_uart0_rx_transfer_callback (transfer_callback_args_t * p_args) + { + FSP_PARAMETER_NOT_USED(p_args); + sci_uart_rx_dmac_callback(&g_uart0_ctrl); + } + #endif + #undef FSP_NOT_DEFINED + + sci_baud_setting_t g_uart0_baud_setting = + { + /* Baud rate calculated with 0.160% error. */ .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 51, .baudrate_bits_b.mddr = (uint8_t) 256, .baudrate_bits_b.brme = false + }; + + /** UART extended configuration for UARTonSCI HAL driver */ + const sci_uart_extended_cfg_t g_uart0_cfg_extend = + { + .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart0_baud_setting, +#if 1 + .clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK, +#else + .clock_source = SCI_UART_CLOCK_SOURCE_PCLKM, +#endif + .flow_control = SCI_UART_FLOW_CONTROL_RTS, + #if 0xFF != 0xFF + .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, + #else + .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, + #endif + .rs485_setting = { + .enable = SCI_UART_RS485_DISABLE, + .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, + .assertion_time = 1, + .negation_time = 1, + }, + }; + + /** UART interface configuration */ + const uart_cfg_t g_uart0_cfg = + { + .channel = 0, + .data_bits = UART_DATA_BITS_8, + .parity = UART_PARITY_OFF, + .stop_bits = UART_STOP_BITS_1, + .p_callback = user_uart0_callback, + .p_context = NULL, + .p_extend = &g_uart0_cfg_extend, + .p_transfer_tx = g_uart0_P_TRANSFER_TX, + .p_transfer_rx = g_uart0_P_TRANSFER_RX, + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), +#if defined(VECTOR_NUMBER_SCI0_RXI) + .rxi_irq = VECTOR_NUMBER_SCI0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_TXI) + .txi_irq = VECTOR_NUMBER_SCI0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_TEI) + .tei_irq = VECTOR_NUMBER_SCI0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SCI0_ERI) + .eri_irq = VECTOR_NUMBER_SCI0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + }; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart0 = +{ + .p_ctrl = &g_uart0_ctrl, + .p_cfg = &g_uart0_cfg, + .p_api = &g_uart_on_sci +}; +void g_hal_init(void) { +g_common_init(); +} diff --git a/bsp/renesas/rzn2l_rsk/rzn_gen/hal_data.h b/bsp/renesas/rzn2l_rsk/rzn_gen/hal_data.h new file mode 100644 index 00000000000..983bc881f4a --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_gen/hal_data.h @@ -0,0 +1,37 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include +#include "bsp_api.h" +#include "common_data.h" +#include "r_sci_uart.h" + #include "r_uart_api.h" +FSP_HEADER +/** UART on SCI Instance. */ + extern const uart_instance_t g_uart0; + + /** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ + extern sci_uart_instance_ctrl_t g_uart0_ctrl; + extern const uart_cfg_t g_uart0_cfg; + extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; + + #ifndef user_uart0_callback + void user_uart0_callback(uart_callback_args_t * p_args); + #endif + + #define FSP_NOT_DEFINED (1) + #if (FSP_NOT_DEFINED == FSP_NOT_DEFINED) + #define g_uart0_P_TRANSFER_TX (NULL) + #else + #define g_uart0_P_TRANSFER_TX (&FSP_NOT_DEFINED) + #endif + #if (FSP_NOT_DEFINED == FSP_NOT_DEFINED) + #define g_uart0_P_TRANSFER_RX (NULL) + #else + #define g_uart0_P_TRANSFER_RX (&FSP_NOT_DEFINED) + #endif + #undef FSP_NOT_DEFINED +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/bsp/renesas/rzn2l_rsk/rzn_gen/main.c b/bsp/renesas/rzn2l_rsk/rzn_gen/main.c new file mode 100644 index 00000000000..42c5904834c --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_gen/main.c @@ -0,0 +1,6 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" + int main(void) { + hal_entry(); + return 0; + } diff --git a/bsp/renesas/rzn2l_rsk/rzn_gen/pin_data.c b/bsp/renesas/rzn2l_rsk/rzn_gen/pin_data.c new file mode 100644 index 00000000000..16c236af9a5 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_gen/pin_data.c @@ -0,0 +1,228 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" +#include "r_ioport.h" + +extern const ioport_extend_cfg_t g_ioport_cfg_extend; + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_01_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P017_PFC_08_CANRX0) + }, + { + .pin = BSP_IO_PORT_02_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P022_PFC_08_CANTX0) + }, + { + .pin = BSP_IO_PORT_02_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P024_PFC_00_TDO) + }, + { + .pin = BSP_IO_PORT_02_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P025_PFC_01_TDI) + }, + { + .pin = BSP_IO_PORT_02_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P026_PFC_00_TMS_SWDIO) + }, + { + .pin = BSP_IO_PORT_02_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P027_PFC_00_TCK_SWCLK) + }, + { + .pin = BSP_IO_PORT_03_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_05_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_05_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P052_PFC_08_IIC_SCL1) + }, + { + .pin = BSP_IO_PORT_05_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P053_PFC_09_IIC_SDA1) + }, + { + .pin = BSP_IO_PORT_05_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_07_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P074_PFC_02_USB_VBUSIN) + }, + { + .pin = BSP_IO_PORT_08_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P087_PFC_00_GMAC_MDC) + }, + { + .pin = BSP_IO_PORT_09_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P090_PFC_00_GMAC_MDIO) + }, + { + .pin = BSP_IO_PORT_13_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P132_PFC_0B_IIC_SCL0) + }, + { + .pin = BSP_IO_PORT_13_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P133_PFC_0B_IIC_SDA0) + }, + { + .pin = BSP_IO_PORT_13_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_13_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_13_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_13_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_14_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_14_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P142_PFC_01_XSPI0_ECS0) + }, + { + .pin = BSP_IO_PORT_14_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P144_PFC_00_XSPI0_DS) + }, + { + .pin = BSP_IO_PORT_14_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P145_PFC_00_XSPI0_CKN) + }, + { + .pin = BSP_IO_PORT_14_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P146_PFC_00_XSPI0_CKP) + }, + { + .pin = BSP_IO_PORT_14_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P147_PFC_00_XSPI0_IO0) + }, + { + .pin = BSP_IO_PORT_15_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P150_PFC_00_XSPI0_IO1) + }, + { + .pin = BSP_IO_PORT_15_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P151_PFC_00_XSPI0_IO2) + }, + { + .pin = BSP_IO_PORT_15_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P152_PFC_00_XSPI0_IO3) + }, + { + .pin = BSP_IO_PORT_15_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P153_PFC_00_XSPI0_IO4) + }, + { + .pin = BSP_IO_PORT_15_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P154_PFC_00_XSPI0_IO5) + }, + { + .pin = BSP_IO_PORT_15_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P155_PFC_00_XSPI0_IO6) + }, + { + .pin = BSP_IO_PORT_15_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P156_PFC_00_XSPI0_IO7) + }, + { + .pin = BSP_IO_PORT_15_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P157_PFC_00_XSPI0_CS0) + }, + { + .pin = BSP_IO_PORT_16_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P160_PFC_00_XSPI0_CS1) + }, + { + .pin = BSP_IO_PORT_16_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P161_PFC_00_XSPI0_RESET0) + }, + { + .pin = BSP_IO_PORT_16_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_16_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P165_PFC_01_TXD0_SDA0_MOSI0) + }, + { + .pin = BSP_IO_PORT_16_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P166_PFC_02_RXD0_SCL0_MISO0) + }, + { + .pin = BSP_IO_PORT_17_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_17_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P175_PFC_05_USB_OVRCUR) + }, + { + .pin = BSP_IO_PORT_17_PIN_7, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P177_PFC_04_RXD3_SCL3_MISO3) + }, + { + .pin = BSP_IO_PORT_18_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P180_PFC_04_TXD3_SDA3_MOSI3) + }, + { + .pin = BSP_IO_PORT_18_PIN_2, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_18_PIN_4, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P184_PFC_03_SPI_RSPCK2) + }, + { + .pin = BSP_IO_PORT_18_PIN_5, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P185_PFC_03_SPI_MOSI2) + }, + { + .pin = BSP_IO_PORT_18_PIN_6, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P186_PFC_05_SPI_MISO2) + }, + { + .pin = BSP_IO_PORT_19_PIN_0, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_PIN_P190_PFC_00_USB_VBUSEN) + }, + { + .pin = BSP_IO_PORT_21_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_PERI | (uint32_t) IOPORT_CFG_SLEW_RATE_FAST | (uint32_t) IOPORT_PIN_P211_PFC_06_SPI_SSL20) + }, + { + .pin = BSP_IO_PORT_22_PIN_1, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_22_PIN_3, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], + .p_extend = &g_ioport_cfg_extend, +}; diff --git a/bsp/renesas/rzn2l_rsk/rzn_gen/vector_data.c b/bsp/renesas/rzn2l_rsk/rzn_gen/vector_data.c new file mode 100644 index 00000000000..c02f2f69daf --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_gen/vector_data.c @@ -0,0 +1,12 @@ +/* generated vector source file - do not edit */ + #include "bsp_api.h" + /* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ + #if VECTOR_DATA_IRQ_COUNT > 0 + BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] = + { + [288] = sci_uart_eri_isr, /* SCI0_ERI (SCI0 Receive error) */ + [289] = sci_uart_rxi_isr, /* SCI0_RXI (SCI0 Receive data full) */ + [290] = sci_uart_txi_isr, /* SCI0_TXI (SCI0 Transmit data empty) */ + [291] = sci_uart_tei_isr, /* SCI0_TEI (SCI0 Transmit end) */ + }; + #endif \ No newline at end of file diff --git a/bsp/renesas/rzn2l_rsk/rzn_gen/vector_data.h b/bsp/renesas/rzn2l_rsk/rzn_gen/vector_data.h new file mode 100644 index 00000000000..852c5ecf779 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/rzn_gen/vector_data.h @@ -0,0 +1,50 @@ +/* generated vector header file - do not edit */ + #ifndef VECTOR_DATA_H + #define VECTOR_DATA_H + #include "bsp_api.h" + /* Number of interrupts allocated */ + #ifndef VECTOR_DATA_IRQ_COUNT + #define VECTOR_DATA_IRQ_COUNT (4) + #endif + /* ISR prototypes */ + void sci_uart_eri_isr(void); + void sci_uart_rxi_isr(void); + void sci_uart_txi_isr(void); + void sci_uart_tei_isr(void); + + /* Vector table allocations */ + #define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type) 288) /* SCI0_ERI (SCI0 Receive error) */ + #define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type) 289) /* SCI0_RXI (SCI0 Receive data full) */ + #define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type) 290) /* SCI0_TXI (SCI0 Transmit data empty) */ + #define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type) 291) /* SCI0_TEI (SCI0 Transmit end) */ + typedef enum IRQn { + SoftwareGeneratedInt0 = -32, + SoftwareGeneratedInt1 = -31, + SoftwareGeneratedInt2 = -30, + SoftwareGeneratedInt3 = -29, + SoftwareGeneratedInt4 = -28, + SoftwareGeneratedInt5 = -27, + SoftwareGeneratedInt6 = -26, + SoftwareGeneratedInt7 = -25, + SoftwareGeneratedInt8 = -24, + SoftwareGeneratedInt9 = -23, + SoftwareGeneratedInt10 = -22, + SoftwareGeneratedInt11 = -21, + SoftwareGeneratedInt12 = -20, + SoftwareGeneratedInt13 = -19, + SoftwareGeneratedInt14 = -18, + SoftwareGeneratedInt15 = -17, + DebugCommunicationsChannelInt = -10, + PerformanceMonitorCounterOverflowInt = -9, + CrossTriggerInterfaceInt = -8, + VritualCPUInterfaceMaintenanceInt = -7, + HypervisorTimerInt = -6, + VirtualTimerInt = -5, + NonSecurePhysicalTimerInt = -2, + SCI0_ERI_IRQn = 288, /* SCI0_ERI (SCI0 Receive error) */ + SCI0_RXI_IRQn = 289, /* SCI0_RXI (SCI0 Receive data full) */ + SCI0_TXI_IRQn = 290, /* SCI0_TXI (SCI0 Transmit data empty) */ + SCI0_TEI_IRQn = 291, /* SCI0_TEI (SCI0 Transmit end) */ + SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = BSP_VECTOR_TABLE_MAX_ENTRIES + } IRQn_Type; + #endif /* VECTOR_DATA_H */ \ No newline at end of file diff --git a/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.icf b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.icf new file mode 100644 index 00000000000..2f14001fa05 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.icf @@ -0,0 +1,684 @@ +include "memory_regions.icf"; + +/* The memory information for each device is done in memory regions file. + * The starting address and length of memory not defined in memory regions file are defined as 0. */ + +if (isdefinedsymbol(ATCM_START)) +{ + define symbol ATCM_PRV_START = ATCM_START; +} +else +{ + define symbol ATCM_PRV_START = 0; +} + +if (isdefinedsymbol(ATCM_LENGTH)) +{ + define symbol ATCM_PRV_LENGTH = ATCM_LENGTH; +} +else +{ + define symbol ATCM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(BTCM_START)) +{ + define symbol BTCM_PRV_START = BTCM_START; +} +else +{ + define symbol BTCM_PRV_START = 0; +} + +if (isdefinedsymbol(BTCM_LENGTH)) +{ + define symbol BTCM_PRV_LENGTH = BTCM_LENGTH; +} +else +{ + define symbol BTCM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_START)) +{ + define symbol SYSTEM_RAM_PRV_START = SYSTEM_RAM_START; +} +else +{ + define symbol SYSTEM_RAM_PRV_START = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_LENGTH)) +{ + define symbol SYSTEM_RAM_PRV_LENGTH = SYSTEM_RAM_LENGTH; +} +else +{ + define symbol SYSTEM_RAM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_MIRROR_START)) +{ + define symbol SYSTEM_RAM_MIRROR_PRV_START = SYSTEM_RAM_MIRROR_START; +} +else +{ + define symbol SYSTEM_RAM_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_MIRROR_LENGTH)) +{ + define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = SYSTEM_RAM_MIRROR_LENGTH; +} +else +{ + define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_START)) +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = xSPI0_CS0_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_START)) +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = xSPI0_CS1_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS1_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_START)) +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = xSPI1_CS0_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_START)) +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = xSPI1_CS1_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS1_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS0_SPACE_MIRROR_START)) +{ + define symbol CS0_SPACE_MIRROR_PRV_START = CS0_SPACE_MIRROR_START; +} +else +{ + define symbol CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol CS0_SPACE_MIRROR_PRV_LENGTH = CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS2_SPACE_MIRROR_START)) +{ + define symbol CS2_SPACE_MIRROR_PRV_START = CS2_SPACE_MIRROR_START; +} +else +{ + define symbol CS2_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS2_SPACE_MIRROR_LENGTH)) +{ + define symbol CS2_SPACE_MIRROR_PRV_LENGTH = CS2_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS2_SPACE_MIRROR_PRV_LENGTH = 0; +} + + +if (isdefinedsymbol(CS3_SPACE_MIRROR_START)) +{ + define symbol CS3_SPACE_MIRROR_PRV_START = CS3_SPACE_MIRROR_START; +} +else +{ + define symbol CS3_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS3_SPACE_MIRROR_LENGTH)) +{ + define symbol CS3_SPACE_MIRROR_PRV_LENGTH = CS3_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS3_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS5_SPACE_MIRROR_START)) +{ + define symbol CS5_SPACE_MIRROR_PRV_START = CS5_SPACE_MIRROR_START; +} +else +{ + define symbol CS5_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS5_SPACE_MIRROR_LENGTH)) +{ + define symbol CS5_SPACE_MIRROR_PRV_LENGTH = CS5_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS5_SPACE_MIRROR_PRV_LENGTH = 0; +} + + +if (isdefinedsymbol(xSPI0_CS0_SPACE_START)) +{ + define symbol xSPI0_CS0_SPACE_PRV_START = xSPI0_CS0_SPACE_START; +} +else +{ + define symbol xSPI0_CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_LENGTH)) +{ + define symbol xSPI0_CS0_SPACE_PRV_LENGTH = xSPI0_CS0_SPACE_LENGTH; +} +else +{ + define symbol xSPI0_CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_START)) +{ + define symbol xSPI0_CS1_SPACE_PRV_START = xSPI0_CS1_SPACE_START; +} +else +{ + define symbol xSPI0_CS1_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_LENGTH)) +{ + define symbol xSPI0_CS1_SPACE_PRV_LENGTH = xSPI0_CS1_SPACE_LENGTH; +} +else +{ + define symbol xSPI0_CS1_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_START)) +{ + define symbol xSPI1_CS0_SPACE_PRV_START = xSPI1_CS0_SPACE_START; +} +else +{ + define symbol xSPI1_CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_LENGTH)) +{ + define symbol xSPI1_CS0_SPACE_PRV_LENGTH = xSPI1_CS0_SPACE_LENGTH; +} +else +{ + define symbol xSPI1_CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_START)) +{ + define symbol xSPI1_CS1_SPACE_PRV_START = xSPI1_CS1_SPACE_START; +} +else +{ + define symbol xSPI1_CS1_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_LENGTH)) +{ + define symbol xSPI1_CS1_SPACE_PRV_LENGTH = xSPI1_CS1_SPACE_LENGTH; +} +else +{ + define symbol xSPI1_CS1_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS0_SPACE_START)) +{ + define symbol CS0_SPACE_PRV_START = CS0_SPACE_START; +} +else +{ + define symbol CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS0_SPACE_LENGTH)) +{ + define symbol CS0_SPACE_PRV_LENGTH = CS0_SPACE_LENGTH; +} +else +{ + define symbol CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS2_SPACE_START)) +{ + define symbol CS2_SPACE_PRV_START = CS2_SPACE_START; +} +else +{ + define symbol CS2_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS2_SPACE_LENGTH)) +{ + define symbol CS2_SPACE_PRV_LENGTH = CS2_SPACE_LENGTH; +} +else +{ + define symbol CS2_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS3_SPACE_START)) +{ + define symbol CS3_SPACE_PRV_START = CS3_SPACE_START; +} +else +{ + define symbol CS3_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS3_SPACE_LENGTH)) +{ + define symbol CS3_SPACE_PRV_LENGTH = CS3_SPACE_LENGTH; +} +else +{ + define symbol CS3_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS5_SPACE_START)) +{ + define symbol CS5_SPACE_PRV_START = CS5_SPACE_START; +} +else +{ + define symbol CS5_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS5_SPACE_LENGTH)) +{ + define symbol CS5_SPACE_PRV_LENGTH = CS5_SPACE_LENGTH; +} +else +{ + define symbol CS5_SPACE_PRV_LENGTH = 0; +} + +define symbol SYSTEM_RAM_END_OFFSET = 0x00048000; +define symbol FLASH_ADDRESS = xSPI0_CS0_SPACE_PRV_START; + +define symbol INTVEC_ADDRESS = ATCM_PRV_START; +define symbol RAM_ADDRESS = (ATCM_PRV_START + 0x100); +define symbol RAM_END_ADDRESS = (ATCM_PRV_START + ATCM_PRV_LENGTH - 1); +define symbol LOADER_STACK_ADDRESS = (BTCM_PRV_START + 0x2000); +define symbol LOADER_STACK_END_ADDRESS = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1); +define symbol DATA_NONCACHE_OFFSET = 0x00048000; +define symbol DATA_NONCACHE_END_OFFSET = 0x00044000; +define symbol DMAC_LINK_MODE_OFFSET = 0x00044000; +define symbol DMAC_LINK_MODE_END_OFFSET = 0x00040000; +define symbol NONCACHE_BUFFER_OFFSET = 0x00020000; +define symbol NONCACHE_BUFFER_END_OFFSET = 0; + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = INTVEC_ADDRESS; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = FLASH_ADDRESS + 0x20100; +define symbol __ICFEDIT_region_ROM_end__ = FLASH_ADDRESS + 0x6FFFF; +define symbol __ICFEDIT_region_RAM_start__ = RAM_ADDRESS; +define symbol __ICFEDIT_region_RAM_end__ = RAM_END_ADDRESS; +/**** End of ICF editor section. ###ICF###*/ + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +define symbol __region_D_LOADER_STACK_start__ = LOADER_STACK_ADDRESS; +define symbol __region_D_LOADER_STACK_end__ = LOADER_STACK_END_ADDRESS; + +define symbol __region_DATA_NONCACHE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_OFFSET; +define symbol __region_DATA_NONCACHE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_END_OFFSET - 1; +define symbol __region_DMAC_LINK_MODE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_OFFSET; +define symbol __region_DMAC_LINK_MODE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_END_OFFSET - 1; +define symbol __region_SHARED_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00040000; +define symbol __region_SHARED_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00020000 - 1; +define symbol __region_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_OFFSET; +define symbol __region_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_END_OFFSET - 1; + +define symbol __region_ATCM_start__ = ATCM_PRV_START; +define symbol __region_ATCM_end__ = ATCM_PRV_START + ATCM_PRV_LENGTH - 1; +define symbol __region_BTCM_start__ = BTCM_PRV_START; +define symbol __region_BTCM_end__ = BTCM_PRV_START + BTCM_PRV_LENGTH - 1; +define symbol __region_SYSTEM_RAM_start__ = SYSTEM_RAM_PRV_START; +define symbol __region_SYSTEM_RAM_end__ = SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; +define symbol __region_SYSTEM_RAM_MIRROR_start__ = SYSTEM_RAM_MIRROR_PRV_START; +define symbol __region_SYSTEM_RAM_MIRROR_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; + +define symbol __region_XSPI0_CS0_MIRROR_start__ = xSPI0_CS0_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI0_CS0_MIRROR_end__ = xSPI0_CS0_SPACE_MIRROR_PRV_START + xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS1_MIRROR_start__ = xSPI0_CS1_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI0_CS1_MIRROR_end__ = xSPI0_CS1_SPACE_MIRROR_PRV_START + xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS0_MIRROR_start__ = xSPI1_CS0_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI1_CS0_MIRROR_end__ = xSPI1_CS0_SPACE_MIRROR_PRV_START + xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS1_MIRROR_start__ = xSPI1_CS1_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI1_CS1_MIRROR_end__ = xSPI1_CS1_SPACE_MIRROR_PRV_START + xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS0_MIRROR_start__ = CS0_SPACE_MIRROR_PRV_START; +define symbol __region_CS0_MIRROR_end__ = CS0_SPACE_MIRROR_PRV_START + CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS2_MIRROR_start__ = CS2_SPACE_MIRROR_PRV_START; +define symbol __region_CS2_MIRROR_end__ = CS2_SPACE_MIRROR_PRV_START + CS2_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS3_MIRROR_start__ = CS3_SPACE_MIRROR_PRV_START; +define symbol __region_CS3_MIRROR_end__ = CS3_SPACE_MIRROR_PRV_START + CS3_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS5_MIRROR_start__ = CS5_SPACE_MIRROR_PRV_START; +define symbol __region_CS5_MIRROR_end__ = CS5_SPACE_MIRROR_PRV_START + CS5_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS0_start__ = xSPI0_CS0_SPACE_PRV_START; +define symbol __region_XSPI0_CS0_end__ = xSPI0_CS0_SPACE_PRV_START + xSPI0_CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS1_start__ = xSPI0_CS1_SPACE_PRV_START; +define symbol __region_XSPI0_CS1_end__ = xSPI0_CS1_SPACE_PRV_START + xSPI0_CS1_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS0_start__ = xSPI1_CS0_SPACE_PRV_START; +define symbol __region_XSPI1_CS0_end__ = xSPI1_CS0_SPACE_PRV_START + xSPI1_CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS1_start__ = xSPI1_CS1_SPACE_PRV_START; +define symbol __region_XSPI1_CS1_end__ = xSPI1_CS1_SPACE_PRV_START + xSPI1_CS1_SPACE_PRV_LENGTH - 1; +define symbol __region_CS0_start__ = CS0_SPACE_PRV_START; +define symbol __region_CS0_end__ = CS0_SPACE_PRV_START + CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_CS2_start__ = CS2_SPACE_PRV_START; +define symbol __region_CS2_end__ = CS2_SPACE_PRV_START + CS2_SPACE_PRV_LENGTH - 1; +define symbol __region_CS3_start__ = CS3_SPACE_PRV_START; +define symbol __region_CS3_end__ = CS3_SPACE_PRV_START + CS3_SPACE_PRV_LENGTH - 1; +define symbol __region_CS5_start__ = CS5_SPACE_PRV_START; +define symbol __region_CS5_end__ = CS5_SPACE_PRV_START + CS5_SPACE_PRV_LENGTH - 1; + +/************** SPI boot mode setting **************/ +define symbol __region_LDR_PARAM_start__ = FLASH_ADDRESS; +define symbol __region_LDR_PARAM_end__ = FLASH_ADDRESS + 0x0000004B; +define symbol __region_S_LOADER_STACK_start__ = FLASH_ADDRESS + 0x0000004C; +define symbol __region_S_LOADER_STACK_end__ = FLASH_ADDRESS + 0x0000804B; + +define symbol __region_S_intvec_start__ = FLASH_ADDRESS + 0x20000; +define symbol __region_S_intvec_end__ = FLASH_ADDRESS + 0x200FF; +define symbol __region_S_RAM_start__ = FLASH_ADDRESS + 0x70000; +define symbol __region_S_RAM_end__ = FLASH_ADDRESS + 0x7FFFF; +/****************************************************/ + +define region D_LOADER_STACK_region = mem:[from __region_D_LOADER_STACK_start__ to __region_D_LOADER_STACK_end__]; + +define region LDR_PARAM_region = mem:[from __region_LDR_PARAM_start__ to __region_LDR_PARAM_end__]; +define region S_LOADER_STACK_region = mem:[from __region_S_LOADER_STACK_start__ to __region_S_LOADER_STACK_end__]; + +define region S_intvec_region = mem:[from __region_S_intvec_start__ to __region_S_intvec_end__]; +define region S_RAM_region = mem:[from __region_S_RAM_start__ to __region_S_RAM_end__]; + +define region DATA_NONCACHE_region = mem:[from __region_DATA_NONCACHE_start__ to __region_DATA_NONCACHE_end__]; +define region DMAC_LINK_MODE_region = mem:[from __region_DMAC_LINK_MODE_start__ to __region_DMAC_LINK_MODE_end__]; +define region SHARED_NONCACHE_BUFFER_region = mem:[from __region_SHARED_NONCACHE_BUFFER_start__ to __region_SHARED_NONCACHE_BUFFER_end__]; +define region NONCACHE_BUFFER_region = mem:[from __region_NONCACHE_BUFFER_start__ to __region_NONCACHE_BUFFER_end__]; + +define region ATCM_region = mem:[from __region_ATCM_start__ to __region_ATCM_end__ ]; +define region BTCM_region = mem:[from __region_BTCM_start__ to __region_BTCM_end__ ]; +define region SYSTEM_RAM_region = mem:[from __region_SYSTEM_RAM_start__ to __region_SYSTEM_RAM_end__ ]; +define region SYSTEM_RAM_MIRROR_region = mem:[from __region_SYSTEM_RAM_MIRROR_start__ to __region_SYSTEM_RAM_MIRROR_end__ ]; +define region XSPI0_CS0_MIRROR_region = mem:[from __region_XSPI0_CS0_MIRROR_start__ to __region_XSPI0_CS0_MIRROR_end__ ]; +define region XSPI0_CS1_MIRROR_region = mem:[from __region_XSPI0_CS1_MIRROR_start__ to __region_XSPI0_CS1_MIRROR_end__ ]; +define region XSPI1_CS0_MIRROR_region = mem:[from __region_XSPI1_CS0_MIRROR_start__ to __region_XSPI1_CS0_MIRROR_end__ ]; +define region XSPI1_CS1_MIRROR_region = mem:[from __region_XSPI1_CS1_MIRROR_start__ to __region_XSPI1_CS1_MIRROR_end__ ]; +define region CS0_MIRROR_region = mem:[from __region_CS0_MIRROR_start__ to __region_CS0_MIRROR_end__ ]; +define region CS2_MIRROR_region = mem:[from __region_CS2_MIRROR_start__ to __region_CS2_MIRROR_end__ ]; +define region CS3_MIRROR_region = mem:[from __region_CS3_MIRROR_start__ to __region_CS3_MIRROR_end__ ]; +define region CS5_MIRROR_region = mem:[from __region_CS5_MIRROR_start__ to __region_CS5_MIRROR_end__ ]; +define region XSPI0_CS0_region = mem:[from __region_XSPI0_CS0_start__ to __region_XSPI0_CS0_end__ ]; +define region XSPI0_CS1_region = mem:[from __region_XSPI0_CS1_start__ to __region_XSPI0_CS1_end__ ]; +define region XSPI1_CS0_region = mem:[from __region_XSPI1_CS0_start__ to __region_XSPI1_CS0_end__ ]; +define region XSPI1_CS1_region = mem:[from __region_XSPI1_CS1_start__ to __region_XSPI1_CS1_end__ ]; +define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__ ]; +define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__ ]; +define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__ ]; +define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__ ]; + +define block LDR_PRG_RBLOCK with fixed order + { ro code section .loader_text_init object startup_core.o, + ro code object startup_core.o, + ro code object system_core.o, + ro code object startup.o, + ro code object system.o, + ro code object bsp_clocks.o, + ro code object bsp_irq_core.o, + ro code object bsp_irq.o, + ro code object bsp_register_protection.o, + ro code object r_ioport.o, + ro code object bsp_cache.o, + ro code section .warm_start_init } + except { ro code section .intvec_init, + ro code section .reset_handler_init }; +define block LDR_PRG_WBLOCK with fixed order + { rw code section .loader_text object startup_core.o, + rw code object startup_core.o, + rw code object system_core.o, + rw code object startup.o, + rw code object system.o, + rw code object bsp_clocks.o, + rw code object bsp_irq_core.o, + rw code object bsp_irq.o, + rw code object bsp_register_protection.o, + rw code object r_ioport.o, + rw code object bsp_cache.o, + rw code section .warm_start } + except { rw code section .intvec, + rw code section .reset_handler }; +define block LDR_DATA_ZBLOCK with alignment = 4 + { section .bss object startup_core.o, + section .bss object system_core.o, + section .bss object startup.o, + section .bss object system.o, + section .bss object bsp_clocks.o, + section .bss object bsp_irq_core.o, + section .bss object bsp_irq.o, + section .bss object bsp_register_protection.o, + section .bss object r_ioport.o, + section .bss object bsp_cache.o, + section .bss object bsp_io.o }; +define block LDR_DATA_RBLOCK with fixed order, alignment = 4 + { section .data_init object startup_core.o, + section .data_init object system_core.o, + section .data_init object startup.o, + section .data_init object system.o, + section .data_init object bsp_clocks.o, + section .data_init object bsp_irq_core.o, + section .data_init object bsp_irq.o, + section .data_init object bsp_register_protection.o, + section .data_init object r_ioport.o, + section .data_init object bsp_cache.o, + section .rodata_init object system_core.o }; +define block LDR_DATA_WBLOCK with fixed order, alignment = 4 + { section .data object startup_core.o, + section .data object system_core.o, + section .data object startup.o, + section .data object system.o, + section .data object bsp_clocks.o, + section .data object bsp_irq_core.o, + section .data object bsp_irq.o, + section .data object bsp_register_protection.o, + section .data object r_ioport.o, + section .data object bsp_cache.o, + section .rodata object system_core.o }; + +define block HEAP_BLOCK with alignment = 8 { rw section HEAP }; +define block THREAD_STACK with alignment = 8 { rw section .stack* }; +define block SYS_STACK with alignment = 8 { rw section .sys_stack }; +define block SVC_STACK with alignment = 8 { rw section .svc_stack }; +define block IRQ_STACK with alignment = 8 { rw section .irq_stack }; +define block FIQ_STACK with alignment = 8 { rw section .fiq_stack }; +define block UND_STACK with alignment = 8 { rw section .und_stack }; +define block ABT_STACK with alignment = 8 { rw section .abt_stack }; + +define block VECTOR_RBLOCK with alignment = 32 { ro code section .intvec_init}; +define block VECTOR_WBLOCK with alignment = 32 { rw code section .intvec}; +define block USER_PRG_RBLOCK with alignment = 4 { ro code }; +define block USER_PRG_WBLOCK with alignment = 4 { rw code }; +define block USER_DATA_ZBLOCK with alignment = 4 { section .bss }; +define block USER_DATA_RBLOCK with fixed order, alignment = 4 + { section .data_init, + section __DLIB_PERTHREAD_init, + section .rodata_init, + section .version_init }; +define block USER_DATA_WBLOCK with fixed order, alignment = 4 + { section .data, + section __DLIB_PERTHREAD, + section .rodata, + section .version }; +define block USER_DATA_NONCACHE_RBLOCK with alignment = 4 { section .data_noncache_init }; +define block USER_DATA_NONCACHE_WBLOCK with alignment = 4 { section .data_noncache }; +define block DMAC_LINK_MODE_ZBLOCK with alignment = 4 { section .dmac_link_mode* }; +define block SHARED_NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .shared_noncache_buffer* }; +define block NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .noncache_buffer* }; + +initialize manually { ro code object startup_core.o, + ro code object system_core.o, + ro code object startup.o, + ro code object system.o, + ro code object bsp_clocks.o, + ro code object bsp_irq_core.o, + ro code object bsp_irq.o, + ro code object bsp_register_protection.o, + ro code object r_ioport.o, + ro code object bsp_cache.o, + ro code section .intvec, + ro code section .reset_handler, + ro code section .warm_start, + ro code, + section .data, + section __DLIB_PERTHREAD, + section .rodata, + section .version, + section .data_noncache }; + +do not initialize { section .noinit, + section .bss, + section .dmac_link_mode*, + section .shared_noncache_buffer*, + section .noncache_buffer*, + rw section HEAP, + rw section .stack*, + rw section .sys_stack, + rw section .svc_stack, + rw section .irq_stack, + rw section .fiq_stack, + rw section .und_stack, + rw section .abt_stack }; + +place at address mem: __ICFEDIT_intvec_start__ { block VECTOR_WBLOCK }; + +place in LDR_PARAM_region { readonly section .loader_param }; +place at start of S_LOADER_STACK_region { block LDR_PRG_RBLOCK }; +place in S_LOADER_STACK_region { section LDR_DATA_RBLOCK, block LDR_DATA_RBLOCK }; +place in S_intvec_region { block VECTOR_RBLOCK }; +place in ROM_region { block USER_PRG_RBLOCK, readonly }; +place in S_RAM_region { block USER_DATA_RBLOCK, block USER_DATA_NONCACHE_RBLOCK }; + +place at start of D_LOADER_STACK_region { block LDR_PRG_WBLOCK }; +place in D_LOADER_STACK_region { section LDR_DATA_WBLOCK, block LDR_DATA_WBLOCK, + section LDR_DATA_ZBLOCK, block LDR_DATA_ZBLOCK }; +place in D_LOADER_STACK_region { section SYS_STACK, block SYS_STACK, + section SVC_STACK, block SVC_STACK, + section IRQ_STACK, block IRQ_STACK, + section FIQ_STACK, block FIQ_STACK, + section UND_STACK, block UND_STACK, + section ABT_STACK, block ABT_STACK }; +place in RAM_region { block USER_PRG_WBLOCK }; +place in RAM_region { readwrite, last block CSTACK }; +place in RAM_region { block USER_DATA_WBLOCK, + block USER_DATA_ZBLOCK }; +place in RAM_region { section HEAP_BLOCK, block HEAP_BLOCK, + section THREAD_STACK, block THREAD_STACK }; + +place in DATA_NONCACHE_region { block USER_DATA_NONCACHE_WBLOCK }; +place in DMAC_LINK_MODE_region { block DMAC_LINK_MODE_ZBLOCK }; +place in SHARED_NONCACHE_BUFFER_region { block SHARED_NONCACHE_BUFFER_ZBLOCK }; +place in NONCACHE_BUFFER_region { block NONCACHE_BUFFER_ZBLOCK }; +place in ATCM_region { }; +place in BTCM_region { }; +place in SYSTEM_RAM_region { }; +place in SYSTEM_RAM_MIRROR_region { }; +place in XSPI0_CS0_MIRROR_region { }; +place in XSPI0_CS1_MIRROR_region { }; +place in XSPI1_CS0_MIRROR_region { }; +place in XSPI1_CS1_MIRROR_region { }; +place in CS0_MIRROR_region { }; +place in CS2_MIRROR_region { }; +place in CS3_MIRROR_region { }; +place in CS5_MIRROR_region { }; +place in XSPI0_CS0_region { }; +place in XSPI0_CS1_region { }; +place in XSPI1_CS0_region { }; +place in XSPI1_CS1_region { }; +place in CS0_region { }; +place in CS2_region { }; +place in CS3_region { }; +place in CS5_region { }; diff --git a/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.ld b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.ld new file mode 100644 index 00000000000..d0ee38a6586 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot.ld @@ -0,0 +1,398 @@ +/* + Linker File for Renesas RZ/N2L FSP +*/ + +INCLUDE memory_regions.ld + +/* The memory information for each device is done in memory regions file. + * The starting address and length of memory not defined in memory regions file are defined as 0. */ + +ATCM_PRV_START = DEFINED(ATCM_START) ? ATCM_START : 0; +ATCM_PRV_LENGTH = DEFINED(ATCM_LENGTH) ? ATCM_LENGTH : 0; +BTCM_PRV_START = DEFINED(BTCM_START) ? BTCM_START : 0; +BTCM_PRV_LENGTH = DEFINED(BTCM_LENGTH) ? BTCM_LENGTH : 0; +SYSTEM_RAM_PRV_START = DEFINED(SYSTEM_RAM_START) ? SYSTEM_RAM_START : 0; +SYSTEM_RAM_PRV_LENGTH = DEFINED(SYSTEM_RAM_LENGTH) ? SYSTEM_RAM_LENGTH : 0; +SYSTEM_RAM_MIRROR_PRV_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START : 0; +SYSTEM_RAM_MIRROR_PRV_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? SYSTEM_RAM_MIRROR_LENGTH : 0; +xSPI0_CS0_SPACE_MIRROR_PRV_START = DEFINED(xSPI0_CS0_SPACE_MIRROR_START) ? xSPI0_CS0_SPACE_MIRROR_START : 0; +xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI0_CS0_SPACE_MIRROR_LENGTH) ? xSPI0_CS0_SPACE_MIRROR_LENGTH : 0; +xSPI0_CS1_SPACE_MIRROR_PRV_START = DEFINED(xSPI0_CS1_SPACE_MIRROR_START) ? xSPI0_CS1_SPACE_MIRROR_START : 0; +xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI0_CS1_SPACE_MIRROR_LENGTH) ? xSPI0_CS1_SPACE_MIRROR_LENGTH : 0; +xSPI1_CS0_SPACE_MIRROR_PRV_START = DEFINED(xSPI1_CS0_SPACE_MIRROR_START) ? xSPI1_CS0_SPACE_MIRROR_START : 0; +xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI1_CS0_SPACE_MIRROR_LENGTH) ? xSPI1_CS0_SPACE_MIRROR_LENGTH : 0; +xSPI1_CS1_SPACE_MIRROR_PRV_START = DEFINED(xSPI1_CS1_SPACE_MIRROR_START) ? xSPI1_CS1_SPACE_MIRROR_START : 0; +xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = DEFINED(xSPI1_CS1_SPACE_MIRROR_LENGTH) ? xSPI1_CS1_SPACE_MIRROR_LENGTH : 0; +CS0_SPACE_MIRROR_PRV_START = DEFINED(CS0_SPACE_MIRROR_START) ? CS0_SPACE_MIRROR_START : 0; +CS0_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS0_SPACE_MIRROR_LENGTH) ? CS0_SPACE_MIRROR_LENGTH : 0; +CS2_SPACE_MIRROR_PRV_START = DEFINED(CS2_SPACE_MIRROR_START) ? CS2_SPACE_MIRROR_START : 0; +CS2_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS2_SPACE_MIRROR_LENGTH) ? CS2_SPACE_MIRROR_LENGTH : 0; +CS3_SPACE_MIRROR_PRV_START = DEFINED(CS3_SPACE_MIRROR_START) ? CS3_SPACE_MIRROR_START : 0; +CS3_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS3_SPACE_MIRROR_LENGTH) ? CS3_SPACE_MIRROR_LENGTH : 0; +CS5_SPACE_MIRROR_PRV_START = DEFINED(CS5_SPACE_MIRROR_START) ? CS5_SPACE_MIRROR_START : 0; +CS5_SPACE_MIRROR_PRV_LENGTH = DEFINED(CS5_SPACE_MIRROR_LENGTH) ? CS5_SPACE_MIRROR_LENGTH : 0; +xSPI0_CS0_SPACE_PRV_START = DEFINED(xSPI0_CS0_SPACE_START) ? xSPI0_CS0_SPACE_START : 0; +xSPI0_CS0_SPACE_PRV_LENGTH = DEFINED(xSPI0_CS0_SPACE_LENGTH) ? xSPI0_CS0_SPACE_LENGTH : 0; +xSPI0_CS1_SPACE_PRV_START = DEFINED(xSPI0_CS1_SPACE_START) ? xSPI0_CS1_SPACE_START : 0; +xSPI0_CS1_SPACE_PRV_LENGTH = DEFINED(xSPI0_CS1_SPACE_LENGTH) ? xSPI0_CS1_SPACE_LENGTH : 0; +xSPI1_CS0_SPACE_PRV_START = DEFINED(xSPI1_CS0_SPACE_START) ? xSPI1_CS0_SPACE_START : 0; +xSPI1_CS0_SPACE_PRV_LENGTH = DEFINED(xSPI1_CS0_SPACE_LENGTH) ? xSPI1_CS0_SPACE_LENGTH : 0; +xSPI1_CS1_SPACE_PRV_START = DEFINED(xSPI1_CS1_SPACE_START) ? xSPI1_CS1_SPACE_START : 0; +xSPI1_CS1_SPACE_PRV_LENGTH = DEFINED(xSPI1_CS1_SPACE_LENGTH) ? xSPI1_CS1_SPACE_LENGTH : 0; +CS0_SPACE_PRV_START = DEFINED(CS0_SPACE_START) ? CS0_SPACE_START : 0; +CS0_SPACE_PRV_LENGTH = DEFINED(CS0_SPACE_LENGTH) ? CS0_SPACE_LENGTH : 0; +CS2_SPACE_PRV_START = DEFINED(CS2_SPACE_START) ? CS2_SPACE_START : 0; +CS2_SPACE_PRV_LENGTH = DEFINED(CS2_SPACE_LENGTH) ? CS2_SPACE_LENGTH : 0; +CS3_SPACE_PRV_START = DEFINED(CS3_SPACE_START) ? CS3_SPACE_START : 0; +CS3_SPACE_PRV_LENGTH = DEFINED(CS3_SPACE_LENGTH) ? CS3_SPACE_LENGTH : 0; +CS5_SPACE_PRV_START = DEFINED(CS5_SPACE_START) ? CS5_SPACE_START : 0; +CS5_SPACE_PRV_LENGTH = DEFINED(CS5_SPACE_LENGTH) ? CS5_SPACE_LENGTH : 0; + +LOADER_PARAM_ADDRESS = xSPI0_CS0_SPACE_PRV_START; +FLASH_CONTENTS_ADDRESS = LOADER_PARAM_ADDRESS + 0x0000004C; +LOADER_TEXT_ADDRESS = 0x00102000; +INTVEC_ADDRESS = 0x00000000; +TEXT_ADDRESS = 0x00000100; +NONCACHE_BUFFER_OFFSET = 0x00020000; +DMAC_LINK_MODE_OFFSET = 0x00044000; +DATA_NONCACHE_OFFSET = 0x00048000; +RAM_START = ATCM_PRV_START; +RAM_LENGTH = ATCM_PRV_LENGTH; +LOADER_START = BTCM_PRV_START; +LOADER_LENGTH = BTCM_PRV_LENGTH; + +/* Define starting addresses and length for data_noncache, DMAC link mode data, CPU-shared non-cache, and CPU-specific non-cache areas. */ +DATA_NONCACHE_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - DATA_NONCACHE_OFFSET : 0; +DATA_NONCACHE_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00004000 : 0; +DMAC_LINK_MODE_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - DMAC_LINK_MODE_OFFSET : 0; +DMAC_LINK_MODE_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00004000 : 0; +SHARED_NONCACHE_BUFFER_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - 0x00040000 : 0; +SHARED_NONCACHE_BUFFER_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00020000 : 0; +NONCACHE_BUFFER_START = DEFINED(SYSTEM_RAM_MIRROR_START) ? SYSTEM_RAM_MIRROR_START + SYSTEM_RAM_MIRROR_LENGTH - NONCACHE_BUFFER_OFFSET : 0; +NONCACHE_BUFFER_LENGTH = DEFINED(SYSTEM_RAM_MIRROR_LENGTH) ? 0x00020000 : 0; + +MEMORY +{ + ATCM : ORIGIN = ATCM_PRV_START, LENGTH = ATCM_PRV_LENGTH + BTCM : ORIGIN = BTCM_PRV_START, LENGTH = BTCM_PRV_LENGTH + SYSTEM_RAM : ORIGIN = SYSTEM_RAM_PRV_START, LENGTH = SYSTEM_RAM_PRV_LENGTH + SYSTEM_RAM_MIRROR : ORIGIN = SYSTEM_RAM_MIRROR_PRV_START, LENGTH = SYSTEM_RAM_MIRROR_PRV_LENGTH + xSPI0_CS0_SPACE_MIRROR : ORIGIN = xSPI0_CS0_SPACE_MIRROR_PRV_START, LENGTH = xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH + xSPI0_CS1_SPACE_MIRROR : ORIGIN = xSPI0_CS1_SPACE_MIRROR_PRV_START, LENGTH = xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH + xSPI1_CS0_SPACE_MIRROR : ORIGIN = xSPI1_CS0_SPACE_MIRROR_PRV_START, LENGTH = xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH + xSPI1_CS1_SPACE_MIRROR : ORIGIN = xSPI1_CS1_SPACE_MIRROR_PRV_START, LENGTH = xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH + CS0_SPACE_MIRROR : ORIGIN = CS0_SPACE_MIRROR_PRV_START, LENGTH = CS0_SPACE_MIRROR_PRV_LENGTH + CS2_SPACE_MIRROR : ORIGIN = CS2_SPACE_MIRROR_PRV_START, LENGTH = CS2_SPACE_MIRROR_PRV_LENGTH + CS3_SPACE_MIRROR : ORIGIN = CS3_SPACE_MIRROR_PRV_START, LENGTH = CS3_SPACE_MIRROR_PRV_LENGTH + CS5_SPACE_MIRROR : ORIGIN = CS5_SPACE_MIRROR_PRV_START, LENGTH = CS5_SPACE_MIRROR_PRV_LENGTH + xSPI0_CS0_SPACE : ORIGIN = xSPI0_CS0_SPACE_PRV_START, LENGTH = xSPI0_CS0_SPACE_PRV_LENGTH + xSPI0_CS1_SPACE : ORIGIN = xSPI0_CS1_SPACE_PRV_START, LENGTH = xSPI0_CS1_SPACE_PRV_LENGTH + xSPI1_CS0_SPACE : ORIGIN = xSPI1_CS0_SPACE_PRV_START, LENGTH = xSPI1_CS0_SPACE_PRV_LENGTH + xSPI1_CS1_SPACE : ORIGIN = xSPI1_CS1_SPACE_PRV_START, LENGTH = xSPI1_CS1_SPACE_PRV_LENGTH + CS0_SPACE : ORIGIN = CS0_SPACE_PRV_START, LENGTH = CS0_SPACE_PRV_LENGTH + CS2_SPACE : ORIGIN = CS2_SPACE_PRV_START, LENGTH = CS2_SPACE_PRV_LENGTH + CS3_SPACE : ORIGIN = CS3_SPACE_PRV_START, LENGTH = CS3_SPACE_PRV_LENGTH + CS5_SPACE : ORIGIN = CS5_SPACE_PRV_START, LENGTH = CS5_SPACE_PRV_LENGTH + RAM : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + LOADER_STACK : ORIGIN = LOADER_START, LENGTH = LOADER_LENGTH + DUMMY : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_NONCACHE : ORIGIN = DATA_NONCACHE_START, LENGTH = DATA_NONCACHE_LENGTH + DMAC_LINK_MODE : ORIGIN = DMAC_LINK_MODE_START, LENGTH = DMAC_LINK_MODE_LENGTH + SHARED_NONCACHE_BUFFER : ORIGIN = SHARED_NONCACHE_BUFFER_START, LENGTH = SHARED_NONCACHE_BUFFER_LENGTH + NONCACHE_BUFFER : ORIGIN = NONCACHE_BUFFER_START, LENGTH = NONCACHE_BUFFER_LENGTH +} + +SECTIONS +{ + .loader_param LOADER_PARAM_ADDRESS : AT (LOADER_PARAM_ADDRESS) + { + KEEP(*(.loader_param)) + } > xSPI0_CS0_SPACE + .flash_contents FLASH_CONTENTS_ADDRESS : AT (FLASH_CONTENTS_ADDRESS) + { + _mloader_text = .; + . = . + (_loader_text_end - _loader_text_start); + _mloader_data = .; + . = . + (_loader_data_end - _loader_data_start); + _mfvector = .; + . = . + (_fvector_end - _fvector_start); + _mtext = .; + . = . + (_text_end - _text_start); + _mdummy = .; + . = . + (_dummy_end - _dummy_start); + _mdata = .; + . = . + (_data_end - _data_start); + _mdata_noncache = .; + . = . + (_data_noncache_end - _data_noncache_start); + flash_contents_end = .; + } > xSPI0_CS0_SPACE + .loader_text LOADER_TEXT_ADDRESS : AT (_mloader_text) + { + _loader_text_start = .; + *(.loader_text) + */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.text*) + */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.text*) + */fsp/src/bsp/mcu/all/bsp_clocks.o(.text*) + */fsp/src/bsp/mcu/all/bsp_irq.o(.text*) + */fsp/src/bsp/mcu/all/bsp_register_protection.o(.text*) + */fsp/src/bsp/mcu/all/bsp_cache.o(.text*) + */fsp/src/r_ioport/r_ioport.o(.text*) + KEEP(*(.warm_start)) + . = . + (512 - ((. - _loader_text_start) % 512)); + _loader_text_end = .; + } > LOADER_STACK + .loader_data : AT (_mloader_data) + { + _loader_data_start = .; + __loader_data_start = .; + */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.data*) + */fsp/src/bsp/cmsis/Device/RENESAS/Source/*/system_core.o(.rodata*) + */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.data*) + */fsp/src/bsp/mcu/all/bsp_clocks.o(.data*) + */fsp/src/bsp/mcu/all/bsp_irq.o(.data*) + */fsp/src/bsp/mcu/all/bsp_register_protection.o(.data*) + */fsp/src/bsp/mcu/all/bsp_cache.o(.data*) + */fsp/src/r_ioport/r_ioport.o(.data*) + . = ALIGN(4); + __loader_data_end = .; + __loader_bss_start = .; + */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(.bss*) + */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(.bss*) + */fsp/src/bsp/mcu/all/bsp_clocks.o(.bss*) + */fsp/src/bsp/mcu/all/bsp_irq.o(.bss*) + */fsp/src/bsp/mcu/all/bsp_register_protection.o(.bss*) + */fsp/src/bsp/mcu/all/bsp_cache.o(.bss*) + */fsp/src/r_ioport/r_ioport.o(.bss*) + */fsp/src/bsp/cmsis/Device/RENESAS/Source/*.o(COMMON) + */fsp/src/bsp/mcu/all/*/bsp_irq_core.o(COMMON) + */fsp/src/bsp/mcu/all/bsp_clocks.o(COMMON) + */fsp/src/bsp/mcu/all/bsp_irq.o(COMMON) + */fsp/src/bsp/mcu/all/bsp_register_protection.o(.COMMON) + */fsp/src/bsp/mcu/all/bsp_cache.o(COMMON) + */fsp/src/r_ioport/r_ioport.o(.COMMON) + . = ALIGN(4); + __loader_bss_end = . ; + _loader_data_end = .; + } > LOADER_STACK + .intvec INTVEC_ADDRESS : AT (_mfvector) + { + _fvector_start = .; + KEEP(*(.intvec)) + _fvector_end = .; + } > RAM + .text TEXT_ADDRESS : AT (_mtext) + { + _text_start = .; + *(.text*) + + KEEP(*(.reset_handler)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + _ctor_end = .; + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + _dtor_end = .; + + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + + + . = ALIGN(4); + KEEP(*(FalPartTable)) + + KEEP(*(.eh_frame*)) + } > RAM + .rvectors : + { + _rvectors_start = .; + KEEP(*(.rvectors)) + _rvectors_end = .; + } > RAM + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > RAM + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > RAM + __exidx_end = .; + .got : + { + *(.got) + *(.got.plt) + . = ALIGN(4); + _text_end = .; + } > RAM + .dummy _fvector_end : AT (_mdummy) + { + _dummy_start = .; + KEEP(*(.dummy)); + _dummy_end = .; + } > DUMMY + .data : AT (_mdata) + { + _data_start = .; + + *(vtable) + *(.data.*) + *(.data) + + *(.rodata*) + _erodata = .; + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + _data_end = .; + } > RAM + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _bss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + _end = .; + } > RAM + .heap (NOLOAD) : + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > ATCM + .thread_stack (NOLOAD): + { + . = ALIGN(8); + __ThreadStackBase = .; + /* Place the Thread stacks here. */ + KEEP(*(.stack*)) + __ThreadStackLimit = .; + } > RAM + .sys_stack (NOLOAD) : + { + . = ALIGN(8); + __SysStackBase = .; + /* Place the sys_stack here. */ + KEEP(*(.sys_stack)) + __SysStackLimit = .; + } > LOADER_STACK + .svc_stack (NOLOAD) : + { + . = ALIGN(8); + __SvcStackBase = .; + /* Place the svc_stack here. */ + KEEP(*(.svc_stack)) + __SvcStackLimit = .; + } > LOADER_STACK + .irq_stack (NOLOAD) : + { + . = ALIGN(8); + __IrqStackBase = .; + /* Place the irq_stack here. */ + KEEP(*(.irq_stack)) + __IrqStackLimit = .; + } > LOADER_STACK + .fiq_stack (NOLOAD) : + { + . = ALIGN(8); + __FiqStackBase = .; + /* Place the fiq_stack here. */ + KEEP(*(.fiq_stack)) + __FiqStackLimit = .; + } > LOADER_STACK + .und_stack (NOLOAD) : + { + . = ALIGN(8); + __UndStackBase = .; + /* Place the und_stack here. */ + KEEP(*(.und_stack)) + __UndStackLimit = .; + } > LOADER_STACK + .abt_stack (NOLOAD) : + { + . = ALIGN(8); + __AbtStackBase = .; + /* Place the abt_stack here. */ + KEEP(*(.abt_stack)) + __AbtStackLimit = .; + } > LOADER_STACK + .data_noncache DATA_NONCACHE_START : AT (_mdata_noncache) + { + . = ALIGN(4); + _data_noncache_start = .; + KEEP(*(.data_noncache*)) + _data_noncache_end = .; + } > DATA_NONCACHE + .dmac_link_mode DMAC_LINK_MODE_START : AT (DMAC_LINK_MODE_START) + { + . = ALIGN(4); + _DmacLinkMode_start = .; + KEEP(*(.dmac_link_mode*)) + _DmacLinkMode_end = .; + } > DMAC_LINK_MODE + .shared_noncache_buffer SHARED_NONCACHE_BUFFER_START (NOLOAD) : AT (SHARED_NONCACHE_BUFFER_START) + { + . = ALIGN(32); + _sncbuffer_start = .; + KEEP(*(.shared_noncache_buffer*)) + _sncbuffer_end = .; + } > SHARED_NONCACHE_BUFFER + .noncache_buffer NONCACHE_BUFFER_START (NOLOAD) : AT (NONCACHE_BUFFER_START) + { + . = ALIGN(32); + _ncbuffer_start = .; + KEEP(*(.noncache_buffer*)) + _ncbuffer_end = .; + } > NONCACHE_BUFFER +} diff --git a/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot_systemRAM.icf b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot_systemRAM.icf new file mode 100644 index 00000000000..0e3f984c5f9 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/script/fsp_xspi0_boot_systemRAM.icf @@ -0,0 +1,699 @@ +include "memory_regions.icf"; + +/* The memory information for each device is done in memory regions file. + * The starting address and length of memory not defined in memory regions file are defined as 0. */ + +if (isdefinedsymbol(ATCM_START)) +{ + define symbol ATCM_PRV_START = ATCM_START; +} +else +{ + define symbol ATCM_PRV_START = 0; +} + +if (isdefinedsymbol(ATCM_LENGTH)) +{ + define symbol ATCM_PRV_LENGTH = ATCM_LENGTH; +} +else +{ + define symbol ATCM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(BTCM_START)) +{ + define symbol BTCM_PRV_START = BTCM_START; +} +else +{ + define symbol BTCM_PRV_START = 0; +} + +if (isdefinedsymbol(BTCM_LENGTH)) +{ + define symbol BTCM_PRV_LENGTH = BTCM_LENGTH; +} +else +{ + define symbol BTCM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_START)) +{ + define symbol SYSTEM_RAM_PRV_START = SYSTEM_RAM_START; +} +else +{ + define symbol SYSTEM_RAM_PRV_START = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_LENGTH)) +{ + define symbol SYSTEM_RAM_PRV_LENGTH = SYSTEM_RAM_LENGTH; +} +else +{ + define symbol SYSTEM_RAM_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_MIRROR_START)) +{ + define symbol SYSTEM_RAM_MIRROR_PRV_START = SYSTEM_RAM_MIRROR_START; +} +else +{ + define symbol SYSTEM_RAM_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(SYSTEM_RAM_MIRROR_LENGTH)) +{ + define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = SYSTEM_RAM_MIRROR_LENGTH; +} +else +{ + define symbol SYSTEM_RAM_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_START)) +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = xSPI0_CS0_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_START)) +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = xSPI0_CS1_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI0_CS1_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_START)) +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = xSPI1_CS0_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_START)) +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = xSPI1_CS1_SPACE_MIRROR_START; +} +else +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_MIRROR_LENGTH)) +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = xSPI1_CS1_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS0_SPACE_MIRROR_START)) +{ + define symbol CS0_SPACE_MIRROR_PRV_START = CS0_SPACE_MIRROR_START; +} +else +{ + define symbol CS0_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS0_SPACE_MIRROR_LENGTH)) +{ + define symbol CS0_SPACE_MIRROR_PRV_LENGTH = CS0_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS0_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS2_SPACE_MIRROR_START)) +{ + define symbol CS2_SPACE_MIRROR_PRV_START = CS2_SPACE_MIRROR_START; +} +else +{ + define symbol CS2_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS2_SPACE_MIRROR_LENGTH)) +{ + define symbol CS2_SPACE_MIRROR_PRV_LENGTH = CS2_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS2_SPACE_MIRROR_PRV_LENGTH = 0; +} + + +if (isdefinedsymbol(CS3_SPACE_MIRROR_START)) +{ + define symbol CS3_SPACE_MIRROR_PRV_START = CS3_SPACE_MIRROR_START; +} +else +{ + define symbol CS3_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS3_SPACE_MIRROR_LENGTH)) +{ + define symbol CS3_SPACE_MIRROR_PRV_LENGTH = CS3_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS3_SPACE_MIRROR_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS5_SPACE_MIRROR_START)) +{ + define symbol CS5_SPACE_MIRROR_PRV_START = CS5_SPACE_MIRROR_START; +} +else +{ + define symbol CS5_SPACE_MIRROR_PRV_START = 0; +} + +if (isdefinedsymbol(CS5_SPACE_MIRROR_LENGTH)) +{ + define symbol CS5_SPACE_MIRROR_PRV_LENGTH = CS5_SPACE_MIRROR_LENGTH; +} +else +{ + define symbol CS5_SPACE_MIRROR_PRV_LENGTH = 0; +} + + +if (isdefinedsymbol(xSPI0_CS0_SPACE_START)) +{ + define symbol xSPI0_CS0_SPACE_PRV_START = xSPI0_CS0_SPACE_START; +} +else +{ + define symbol xSPI0_CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS0_SPACE_LENGTH)) +{ + define symbol xSPI0_CS0_SPACE_PRV_LENGTH = xSPI0_CS0_SPACE_LENGTH; +} +else +{ + define symbol xSPI0_CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_START)) +{ + define symbol xSPI0_CS1_SPACE_PRV_START = xSPI0_CS1_SPACE_START; +} +else +{ + define symbol xSPI0_CS1_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI0_CS1_SPACE_LENGTH)) +{ + define symbol xSPI0_CS1_SPACE_PRV_LENGTH = xSPI0_CS1_SPACE_LENGTH; +} +else +{ + define symbol xSPI0_CS1_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_START)) +{ + define symbol xSPI1_CS0_SPACE_PRV_START = xSPI1_CS0_SPACE_START; +} +else +{ + define symbol xSPI1_CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS0_SPACE_LENGTH)) +{ + define symbol xSPI1_CS0_SPACE_PRV_LENGTH = xSPI1_CS0_SPACE_LENGTH; +} +else +{ + define symbol xSPI1_CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_START)) +{ + define symbol xSPI1_CS1_SPACE_PRV_START = xSPI1_CS1_SPACE_START; +} +else +{ + define symbol xSPI1_CS1_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(xSPI1_CS1_SPACE_LENGTH)) +{ + define symbol xSPI1_CS1_SPACE_PRV_LENGTH = xSPI1_CS1_SPACE_LENGTH; +} +else +{ + define symbol xSPI1_CS1_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS0_SPACE_START)) +{ + define symbol CS0_SPACE_PRV_START = CS0_SPACE_START; +} +else +{ + define symbol CS0_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS0_SPACE_LENGTH)) +{ + define symbol CS0_SPACE_PRV_LENGTH = CS0_SPACE_LENGTH; +} +else +{ + define symbol CS0_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS2_SPACE_START)) +{ + define symbol CS2_SPACE_PRV_START = CS2_SPACE_START; +} +else +{ + define symbol CS2_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS2_SPACE_LENGTH)) +{ + define symbol CS2_SPACE_PRV_LENGTH = CS2_SPACE_LENGTH; +} +else +{ + define symbol CS2_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS3_SPACE_START)) +{ + define symbol CS3_SPACE_PRV_START = CS3_SPACE_START; +} +else +{ + define symbol CS3_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS3_SPACE_LENGTH)) +{ + define symbol CS3_SPACE_PRV_LENGTH = CS3_SPACE_LENGTH; +} +else +{ + define symbol CS3_SPACE_PRV_LENGTH = 0; +} + +if (isdefinedsymbol(CS5_SPACE_START)) +{ + define symbol CS5_SPACE_PRV_START = CS5_SPACE_START; +} +else +{ + define symbol CS5_SPACE_PRV_START = 0; +} + +if (isdefinedsymbol(CS5_SPACE_LENGTH)) +{ + define symbol CS5_SPACE_PRV_LENGTH = CS5_SPACE_LENGTH; +} +else +{ + define symbol CS5_SPACE_PRV_LENGTH = 0; +} + +define symbol SYSTEM_RAM_END_OFFSET = 0x00048000; +define symbol FLASH_ADDRESS = xSPI0_CS0_SPACE_PRV_START; + +/* +define symbol INTVEC_ADDRESS = ATCM_PRV_START; +define symbol RAM_ADDRESS = (ATCM_PRV_START + 0x100); +define symbol RAM_END_ADDRESS = (ATCM_PRV_START + ATCM_PRV_LENGTH - 1); +define symbol LOADER_STACK_ADDRESS = (BTCM_PRV_START + 0x2000); +define symbol LOADER_STACK_END_ADDRESS = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1); +define symbol DATA_NONCACHE_OFFSET = 0x00048000; +define symbol DATA_NONCACHE_END_OFFSET = 0x00044000; +define symbol DMAC_LINK_MODE_OFFSET = 0x00044000; +define symbol DMAC_LINK_MODE_END_OFFSET = 0x00040000; +define symbol NONCACHE_BUFFER_OFFSET = 0x00020000; +define symbol NONCACHE_BUFFER_END_OFFSET = 0; +*/ +/************* Override define symbol to place EtherCAT protocol into SystemRAM ************/ +define symbol INTVEC_ADDRESS = SYSTEM_RAM_PRV_START; +define symbol RAM_ADDRESS = (SYSTEM_RAM_PRV_START + 0x100); +define symbol RAM_END_ADDRESS = (SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - 1); +define symbol LOADER_STACK_ADDRESS = (BTCM_PRV_START + 0x2000); +define symbol LOADER_STACK_END_ADDRESS = (BTCM_PRV_START + BTCM_PRV_LENGTH - 1); +define symbol DATA_NONCACHE_OFFSET = 0x00048000; +define symbol DATA_NONCACHE_END_OFFSET = 0x00044000; +define symbol DMAC_LINK_MODE_OFFSET = 0x00044000; +define symbol DMAC_LINK_MODE_END_OFFSET = 0x00040000; +define symbol NONCACHE_BUFFER_OFFSET = 0x00020000; +define symbol NONCACHE_BUFFER_END_OFFSET = 0; +/*********************************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = INTVEC_ADDRESS; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = FLASH_ADDRESS + 0x20100; +define symbol __ICFEDIT_region_ROM_end__ = FLASH_ADDRESS + 0x6FFFF; +define symbol __ICFEDIT_region_RAM_start__ = RAM_ADDRESS; +define symbol __ICFEDIT_region_RAM_end__ = RAM_END_ADDRESS; +/**** End of ICF editor section. ###ICF###*/ + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; + +define symbol __region_D_LOADER_STACK_start__ = LOADER_STACK_ADDRESS; +define symbol __region_D_LOADER_STACK_end__ = LOADER_STACK_END_ADDRESS; + +define symbol __region_DATA_NONCACHE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_OFFSET; +define symbol __region_DATA_NONCACHE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DATA_NONCACHE_END_OFFSET - 1; +define symbol __region_DMAC_LINK_MODE_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_OFFSET; +define symbol __region_DMAC_LINK_MODE_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - DMAC_LINK_MODE_END_OFFSET - 1; +define symbol __region_SHARED_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00040000; +define symbol __region_SHARED_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - 0x00020000 - 1; +define symbol __region_NONCACHE_BUFFER_start__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_OFFSET; +define symbol __region_NONCACHE_BUFFER_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - NONCACHE_BUFFER_END_OFFSET - 1; + +define symbol __region_ATCM_start__ = ATCM_PRV_START; +define symbol __region_ATCM_end__ = ATCM_PRV_START + ATCM_PRV_LENGTH - 1; +define symbol __region_BTCM_start__ = BTCM_PRV_START; +define symbol __region_BTCM_end__ = BTCM_PRV_START + BTCM_PRV_LENGTH - 1; +define symbol __region_SYSTEM_RAM_start__ = SYSTEM_RAM_PRV_START; +define symbol __region_SYSTEM_RAM_end__ = SYSTEM_RAM_PRV_START + SYSTEM_RAM_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; +define symbol __region_SYSTEM_RAM_MIRROR_start__ = SYSTEM_RAM_MIRROR_PRV_START; +define symbol __region_SYSTEM_RAM_MIRROR_end__ = SYSTEM_RAM_MIRROR_PRV_START + SYSTEM_RAM_MIRROR_PRV_LENGTH - SYSTEM_RAM_END_OFFSET - 1; + +define symbol __region_XSPI0_CS0_MIRROR_start__ = xSPI0_CS0_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI0_CS0_MIRROR_end__ = xSPI0_CS0_SPACE_MIRROR_PRV_START + xSPI0_CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS1_MIRROR_start__ = xSPI0_CS1_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI0_CS1_MIRROR_end__ = xSPI0_CS1_SPACE_MIRROR_PRV_START + xSPI0_CS1_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS0_MIRROR_start__ = xSPI1_CS0_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI1_CS0_MIRROR_end__ = xSPI1_CS0_SPACE_MIRROR_PRV_START + xSPI1_CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS1_MIRROR_start__ = xSPI1_CS1_SPACE_MIRROR_PRV_START; +define symbol __region_XSPI1_CS1_MIRROR_end__ = xSPI1_CS1_SPACE_MIRROR_PRV_START + xSPI1_CS1_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS0_MIRROR_start__ = CS0_SPACE_MIRROR_PRV_START; +define symbol __region_CS0_MIRROR_end__ = CS0_SPACE_MIRROR_PRV_START + CS0_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS2_MIRROR_start__ = CS2_SPACE_MIRROR_PRV_START; +define symbol __region_CS2_MIRROR_end__ = CS2_SPACE_MIRROR_PRV_START + CS2_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS3_MIRROR_start__ = CS3_SPACE_MIRROR_PRV_START; +define symbol __region_CS3_MIRROR_end__ = CS3_SPACE_MIRROR_PRV_START + CS3_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_CS5_MIRROR_start__ = CS5_SPACE_MIRROR_PRV_START; +define symbol __region_CS5_MIRROR_end__ = CS5_SPACE_MIRROR_PRV_START + CS5_SPACE_MIRROR_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS0_start__ = xSPI0_CS0_SPACE_PRV_START; +define symbol __region_XSPI0_CS0_end__ = xSPI0_CS0_SPACE_PRV_START + xSPI0_CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI0_CS1_start__ = xSPI0_CS1_SPACE_PRV_START; +define symbol __region_XSPI0_CS1_end__ = xSPI0_CS1_SPACE_PRV_START + xSPI0_CS1_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS0_start__ = xSPI1_CS0_SPACE_PRV_START; +define symbol __region_XSPI1_CS0_end__ = xSPI1_CS0_SPACE_PRV_START + xSPI1_CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_XSPI1_CS1_start__ = xSPI1_CS1_SPACE_PRV_START; +define symbol __region_XSPI1_CS1_end__ = xSPI1_CS1_SPACE_PRV_START + xSPI1_CS1_SPACE_PRV_LENGTH - 1; +define symbol __region_CS0_start__ = CS0_SPACE_PRV_START; +define symbol __region_CS0_end__ = CS0_SPACE_PRV_START + CS0_SPACE_PRV_LENGTH - 1; +define symbol __region_CS2_start__ = CS2_SPACE_PRV_START; +define symbol __region_CS2_end__ = CS2_SPACE_PRV_START + CS2_SPACE_PRV_LENGTH - 1; +define symbol __region_CS3_start__ = CS3_SPACE_PRV_START; +define symbol __region_CS3_end__ = CS3_SPACE_PRV_START + CS3_SPACE_PRV_LENGTH - 1; +define symbol __region_CS5_start__ = CS5_SPACE_PRV_START; +define symbol __region_CS5_end__ = CS5_SPACE_PRV_START + CS5_SPACE_PRV_LENGTH - 1; + +/************** SPI boot mode setting **************/ +define symbol __region_LDR_PARAM_start__ = FLASH_ADDRESS; +define symbol __region_LDR_PARAM_end__ = FLASH_ADDRESS + 0x0000004B; +define symbol __region_S_LOADER_STACK_start__ = FLASH_ADDRESS + 0x0000004C; +define symbol __region_S_LOADER_STACK_end__ = FLASH_ADDRESS + 0x0000804B; + +define symbol __region_S_intvec_start__ = FLASH_ADDRESS + 0x20000; +define symbol __region_S_intvec_end__ = FLASH_ADDRESS + 0x200FF; +define symbol __region_S_RAM_start__ = FLASH_ADDRESS + 0x70000; +define symbol __region_S_RAM_end__ = FLASH_ADDRESS + 0x7FFFF; +/****************************************************/ + +define region D_LOADER_STACK_region = mem:[from __region_D_LOADER_STACK_start__ to __region_D_LOADER_STACK_end__]; + +define region LDR_PARAM_region = mem:[from __region_LDR_PARAM_start__ to __region_LDR_PARAM_end__]; +define region S_LOADER_STACK_region = mem:[from __region_S_LOADER_STACK_start__ to __region_S_LOADER_STACK_end__]; + +define region S_intvec_region = mem:[from __region_S_intvec_start__ to __region_S_intvec_end__]; +define region S_RAM_region = mem:[from __region_S_RAM_start__ to __region_S_RAM_end__]; + +define region DATA_NONCACHE_region = mem:[from __region_DATA_NONCACHE_start__ to __region_DATA_NONCACHE_end__]; +define region DMAC_LINK_MODE_region = mem:[from __region_DMAC_LINK_MODE_start__ to __region_DMAC_LINK_MODE_end__]; +define region SHARED_NONCACHE_BUFFER_region = mem:[from __region_SHARED_NONCACHE_BUFFER_start__ to __region_SHARED_NONCACHE_BUFFER_end__]; +define region NONCACHE_BUFFER_region = mem:[from __region_NONCACHE_BUFFER_start__ to __region_NONCACHE_BUFFER_end__]; + +define region ATCM_region = mem:[from __region_ATCM_start__ to __region_ATCM_end__ ]; +define region BTCM_region = mem:[from __region_BTCM_start__ to __region_BTCM_end__ ]; +define region SYSTEM_RAM_region = mem:[from __region_SYSTEM_RAM_start__ to __region_SYSTEM_RAM_end__ ]; +define region SYSTEM_RAM_MIRROR_region = mem:[from __region_SYSTEM_RAM_MIRROR_start__ to __region_SYSTEM_RAM_MIRROR_end__ ]; +define region XSPI0_CS0_MIRROR_region = mem:[from __region_XSPI0_CS0_MIRROR_start__ to __region_XSPI0_CS0_MIRROR_end__ ]; +define region XSPI0_CS1_MIRROR_region = mem:[from __region_XSPI0_CS1_MIRROR_start__ to __region_XSPI0_CS1_MIRROR_end__ ]; +define region XSPI1_CS0_MIRROR_region = mem:[from __region_XSPI1_CS0_MIRROR_start__ to __region_XSPI1_CS0_MIRROR_end__ ]; +define region XSPI1_CS1_MIRROR_region = mem:[from __region_XSPI1_CS1_MIRROR_start__ to __region_XSPI1_CS1_MIRROR_end__ ]; +define region CS0_MIRROR_region = mem:[from __region_CS0_MIRROR_start__ to __region_CS0_MIRROR_end__ ]; +define region CS2_MIRROR_region = mem:[from __region_CS2_MIRROR_start__ to __region_CS2_MIRROR_end__ ]; +define region CS3_MIRROR_region = mem:[from __region_CS3_MIRROR_start__ to __region_CS3_MIRROR_end__ ]; +define region CS5_MIRROR_region = mem:[from __region_CS5_MIRROR_start__ to __region_CS5_MIRROR_end__ ]; +define region XSPI0_CS0_region = mem:[from __region_XSPI0_CS0_start__ to __region_XSPI0_CS0_end__ ]; +define region XSPI0_CS1_region = mem:[from __region_XSPI0_CS1_start__ to __region_XSPI0_CS1_end__ ]; +define region XSPI1_CS0_region = mem:[from __region_XSPI1_CS0_start__ to __region_XSPI1_CS0_end__ ]; +define region XSPI1_CS1_region = mem:[from __region_XSPI1_CS1_start__ to __region_XSPI1_CS1_end__ ]; +define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__ ]; +define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__ ]; +define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__ ]; +define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__ ]; + +define block LDR_PRG_RBLOCK with fixed order + { ro code section .loader_text_init object startup_core.o, + ro code object startup_core.o, + ro code object system_core.o, + ro code object startup.o, + ro code object system.o, + ro code object bsp_clocks.o, + ro code object bsp_irq_core.o, + ro code object bsp_irq.o, + ro code object bsp_register_protection.o, + ro code object r_ioport.o, + ro code object bsp_cache.o, + ro code section .warm_start_init } + except { ro code section .intvec_init, + ro code section .reset_handler_init }; +define block LDR_PRG_WBLOCK with fixed order + { rw code section .loader_text object startup_core.o, + rw code object startup_core.o, + rw code object system_core.o, + rw code object startup.o, + rw code object system.o, + rw code object bsp_clocks.o, + rw code object bsp_irq_core.o, + rw code object bsp_irq.o, + rw code object bsp_register_protection.o, + rw code object r_ioport.o, + rw code object bsp_cache.o, + rw code section .warm_start } + except { rw code section .intvec, + rw code section .reset_handler }; +define block LDR_DATA_ZBLOCK with alignment = 4 + { section .bss object startup_core.o, + section .bss object system_core.o, + section .bss object startup.o, + section .bss object system.o, + section .bss object bsp_clocks.o, + section .bss object bsp_irq_core.o, + section .bss object bsp_irq.o, + section .bss object bsp_register_protection.o, + section .bss object r_ioport.o, + section .bss object bsp_cache.o, + section .bss object bsp_io.o }; +define block LDR_DATA_RBLOCK with fixed order, alignment = 4 + { section .data_init object startup_core.o, + section .data_init object system_core.o, + section .data_init object startup.o, + section .data_init object system.o, + section .data_init object bsp_clocks.o, + section .data_init object bsp_irq_core.o, + section .data_init object bsp_irq.o, + section .data_init object bsp_register_protection.o, + section .data_init object r_ioport.o, + section .data_init object bsp_cache.o, + section .rodata_init object system_core.o }; +define block LDR_DATA_WBLOCK with fixed order, alignment = 4 + { section .data object startup_core.o, + section .data object system_core.o, + section .data object startup.o, + section .data object system.o, + section .data object bsp_clocks.o, + section .data object bsp_irq_core.o, + section .data object bsp_irq.o, + section .data object bsp_register_protection.o, + section .data object r_ioport.o, + section .data object bsp_cache.o, + section .rodata object system_core.o }; + +define block HEAP_BLOCK with alignment = 8 { rw section HEAP }; +define block THREAD_STACK with alignment = 8 { rw section .stack* }; +define block SYS_STACK with alignment = 8 { rw section .sys_stack }; +define block SVC_STACK with alignment = 8 { rw section .svc_stack }; +define block IRQ_STACK with alignment = 8 { rw section .irq_stack }; +define block FIQ_STACK with alignment = 8 { rw section .fiq_stack }; +define block UND_STACK with alignment = 8 { rw section .und_stack }; +define block ABT_STACK with alignment = 8 { rw section .abt_stack }; + +define block VECTOR_RBLOCK with alignment = 32 { ro code section .intvec_init}; +define block VECTOR_WBLOCK with alignment = 32 { rw code section .intvec}; +define block USER_PRG_RBLOCK with alignment = 4 { ro code }; +define block USER_PRG_WBLOCK with alignment = 4 { rw code }; +define block USER_DATA_ZBLOCK with alignment = 4 { section .bss }; +define block USER_DATA_RBLOCK with fixed order, alignment = 4 + { section .data_init, + section __DLIB_PERTHREAD_init, + section .rodata_init, + section .version_init }; +define block USER_DATA_WBLOCK with fixed order, alignment = 4 + { section .data, + section __DLIB_PERTHREAD, + section .rodata, + section .version }; +define block USER_DATA_NONCACHE_RBLOCK with alignment = 4 { section .data_noncache_init }; +define block USER_DATA_NONCACHE_WBLOCK with alignment = 4 { section .data_noncache }; +define block DMAC_LINK_MODE_ZBLOCK with alignment = 4 { section .dmac_link_mode* }; +define block SHARED_NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .shared_noncache_buffer* }; +define block NONCACHE_BUFFER_ZBLOCK with alignment = 32 { section .noncache_buffer* }; + +initialize manually { ro code object startup_core.o, + ro code object system_core.o, + ro code object startup.o, + ro code object system.o, + ro code object bsp_clocks.o, + ro code object bsp_irq_core.o, + ro code object bsp_irq.o, + ro code object bsp_register_protection.o, + ro code object r_ioport.o, + ro code object bsp_cache.o, + ro code section .intvec, + ro code section .reset_handler, + ro code section .warm_start, + ro code, + section .data, + section __DLIB_PERTHREAD, + section .rodata, + section .version, + section .data_noncache }; + +do not initialize { section .noinit, + section .bss, + section .dmac_link_mode*, + section .shared_noncache_buffer*, + section .noncache_buffer*, + rw section HEAP, + rw section .stack*, + rw section .sys_stack, + rw section .svc_stack, + rw section .irq_stack, + rw section .fiq_stack, + rw section .und_stack, + rw section .abt_stack }; + +place at address mem: __ICFEDIT_intvec_start__ { block VECTOR_WBLOCK }; + +place in LDR_PARAM_region { readonly section .loader_param }; +place at start of S_LOADER_STACK_region { block LDR_PRG_RBLOCK }; +place in S_LOADER_STACK_region { section LDR_DATA_RBLOCK, block LDR_DATA_RBLOCK }; +place in S_intvec_region { block VECTOR_RBLOCK }; +place in ROM_region { block USER_PRG_RBLOCK, readonly }; +place in S_RAM_region { block USER_DATA_RBLOCK, block USER_DATA_NONCACHE_RBLOCK }; + +place at start of D_LOADER_STACK_region { block LDR_PRG_WBLOCK }; +place in D_LOADER_STACK_region { section LDR_DATA_WBLOCK, block LDR_DATA_WBLOCK, + section LDR_DATA_ZBLOCK, block LDR_DATA_ZBLOCK }; +place in D_LOADER_STACK_region { section SYS_STACK, block SYS_STACK, + section SVC_STACK, block SVC_STACK, + section IRQ_STACK, block IRQ_STACK, + section FIQ_STACK, block FIQ_STACK, + section UND_STACK, block UND_STACK, + section ABT_STACK, block ABT_STACK }; +place in RAM_region { block USER_PRG_WBLOCK }; +place in RAM_region { readwrite, last block CSTACK }; +place in RAM_region { block USER_DATA_WBLOCK, + block USER_DATA_ZBLOCK }; +place in RAM_region { section HEAP_BLOCK, block HEAP_BLOCK, + section THREAD_STACK, block THREAD_STACK }; + +place in DATA_NONCACHE_region { block USER_DATA_NONCACHE_WBLOCK }; +place in DMAC_LINK_MODE_region { block DMAC_LINK_MODE_ZBLOCK }; +place in SHARED_NONCACHE_BUFFER_region { block SHARED_NONCACHE_BUFFER_ZBLOCK }; +place in NONCACHE_BUFFER_region { block NONCACHE_BUFFER_ZBLOCK }; +place in ATCM_region { }; +place in BTCM_region { }; +place in SYSTEM_RAM_region { }; +place in SYSTEM_RAM_MIRROR_region { }; +place in XSPI0_CS0_MIRROR_region { }; +place in XSPI0_CS1_MIRROR_region { }; +place in XSPI1_CS0_MIRROR_region { }; +place in XSPI1_CS1_MIRROR_region { }; +place in CS0_MIRROR_region { }; +place in CS2_MIRROR_region { }; +place in CS3_MIRROR_region { }; +place in CS5_MIRROR_region { }; +place in XSPI0_CS0_region { }; +place in XSPI0_CS1_region { }; +place in XSPI1_CS0_region { }; +place in XSPI1_CS1_region { }; +place in CS0_region { }; +place in CS2_region { }; +place in CS3_region { }; +place in CS5_region { }; diff --git a/bsp/renesas/rzn2l_rsk/script/memory_regions.ld b/bsp/renesas/rzn2l_rsk/script/memory_regions.ld new file mode 100644 index 00000000000..227ab3ebb17 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/script/memory_regions.ld @@ -0,0 +1,38 @@ + + /* generated memory regions file - do not edit */ + ATCM_START = 0x00000000; + ATCM_LENGTH = 0x20000; + BTCM_START = 0x00100000; + BTCM_LENGTH = 0x20000; + SYSTEM_RAM_START = 0x10000000; + SYSTEM_RAM_LENGTH = 0x180000; + SYSTEM_RAM_MIRROR_START = 0x30000000; + SYSTEM_RAM_MIRROR_LENGTH = 0x180000; + xSPI0_CS0_SPACE_MIRROR_START = 0x40000000; + xSPI0_CS0_SPACE_MIRROR_LENGTH = 0x4000000; + xSPI0_CS1_SPACE_MIRROR_START = 0x44000000; + xSPI0_CS1_SPACE_MIRROR_LENGTH = 0x4000000; + xSPI1_CS0_SPACE_MIRROR_START = 0x48000000; + xSPI1_CS0_SPACE_MIRROR_LENGTH = 0x4000000; + CS0_SPACE_MIRROR_START = 0x50000000; + CS0_SPACE_MIRROR_LENGTH = 0x4000000; + CS2_SPACE_MIRROR_START = 0x54000000; + CS2_SPACE_MIRROR_LENGTH = 0x4000000; + CS3_SPACE_MIRROR_START = 0x58000000; + CS3_SPACE_MIRROR_LENGTH = 0x4000000; + CS5_SPACE_MIRROR_START = 0x5C000000; + CS5_SPACE_MIRROR_LENGTH = 0x4000000; + xSPI0_CS0_SPACE_START = 0x60000000; + xSPI0_CS0_SPACE_LENGTH = 0x4000000; + xSPI0_CS1_SPACE_START = 0x64000000; + xSPI0_CS1_SPACE_LENGTH = 0x4000000; + xSPI1_CS0_SPACE_START = 0x68000000; + xSPI1_CS0_SPACE_LENGTH = 0x4000000; + CS0_SPACE_START = 0x70000000; + CS0_SPACE_LENGTH = 0x4000000; + CS2_SPACE_START = 0x74000000; + CS2_SPACE_LENGTH = 0x4000000; + CS3_SPACE_START = 0x78000000; + CS3_SPACE_LENGTH = 0x4000000; + CS5_SPACE_START = 0x7C000000; + CS5_SPACE_LENGTH = 0x4000000; diff --git a/bsp/renesas/rzn2l_rsk/src/hal_entry.c b/bsp/renesas/rzn2l_rsk/src/hal_entry.c new file mode 100644 index 00000000000..416d9f8702b --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/src/hal_entry.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-03-11 Wangyuqiang first version + */ + +#include +#include "hal_data.h" +#include +#include + +#define LED_PIN BSP_IO_PORT_18_PIN_2 /* Onboard LED pins */ + +void hal_entry(void) +{ + rt_kprintf("\nHello RT-Thread!\n"); + rt_kprintf("==================================================\n"); + rt_kprintf("This is a iar project which mode is xspi0 execution!\n"); + rt_kprintf("==================================================\n"); + + while (1) + { + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} diff --git a/bsp/renesas/rzn2l_rsk/template.ewd b/bsp/renesas/rzn2l_rsk/template.ewd new file mode 100644 index 00000000000..f1b21119308 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/template.ewd @@ -0,0 +1,3276 @@ + + + 4 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 33 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 1 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 1 + + + + + + + IJET_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 1 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 1 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 1 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 1 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 1 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + ARM + + 0 + + C-SPY + 2 + + 33 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + E2_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + GPLINK_ID + 2 + + 0 + 1 + 0 + + + + + + + IJET_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + JLINK_ID + 2 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 3 + 1 + 0 + + + + + + + + + + + + + NULINK_ID + 2 + + 0 + 1 + 0 + + + + + + + PEMICRO_ID + 2 + + 3 + 1 + 0 + + + + + + + + STLINK_ID + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + THIRDPARTY_ID + 2 + + 0 + 1 + 0 + + + + + + + + TIFET_ID + 2 + + 1 + 1 + 0 + + + + + + + + + + + + + + + + + + + XDS100_ID + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\Azure\AzureArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9a.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + diff --git a/bsp/renesas/rzn2l_rsk/template.ewp b/bsp/renesas/rzn2l_rsk/template.ewp new file mode 100644 index 00000000000..839155dd146 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/template.ewp @@ -0,0 +1,2616 @@ + + + 4 + + Debug + + ARM + + 1 + + General + 3 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 1 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BUILDACTION + 2 + + + + + Release + + ARM + + 0 + + General + 3 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 38 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 12 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + inputOutputBased + + + + ILINK + 0 + + 27 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BUILDACTION + 2 + + + + cmd /c ""$RASC_EXE_PATH$" -nosplash --launcher.suppressErrors --generate --compiler IAR --devicefamily rzn "$PROJ_DIR$\configuration.xml" 2> "%TEMP%\rasc_stderr.out"" + $PROJ_DIR$ + preCompile + + + $BUILD_FILES_DIR$/.prebuild + + + + + cmd /c ""$RASC_EXE_PATH$" -nosplash --launcher.suppressErrors --gensmartbundle --compiler IAR --devicefamily rzn "$PROJ_DIR$\configuration.xml" "$TARGET_PATH$" 2> "%TEMP%\rasc_stderr.out"" && echo > "$BUILD_FILES_DIR$/.postbuild" + $PROJ_DIR$ + postLink + + + $BUILD_FILES_DIR$/.postbuild + + + + + + + + + Flex Software + + Build Configuration + + $PROJ_DIR$\rzn_cfg\fsp_cfg\bsp\board_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\bsp\bsp_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\bsp\bsp_mcu_device_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\bsp\bsp_mcu_device_memory_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\bsp\bsp_mcu_device_pn_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\bsp\bsp_mcu_family_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\bsp\bsp_memory_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\bsp\bsp_pin_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\r_cmt_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\r_ether_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\r_ether_phy_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\r_ether_selector_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\r_ether_switch_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\r_ioport_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\r_sci_uart_cfg.h + + + $PROJ_DIR$\rzn_cfg\fsp_cfg\rm_ethercat_ssc_port_cfg.h + + + + Components + + $PROJ_DIR$\rzn\board\rzn2l_rsk\board.h + + + $PROJ_DIR$\rzn\board\rzn2l_rsk\board_ethernet_phy.h + + + $PROJ_DIR$\rzn\board\rzn2l_rsk\board_init.c + + + $PROJ_DIR$\rzn\board\rzn2l_rsk\board_init.h + + + $PROJ_DIR$\rzn\board\rzn2l_rsk\board_leds.c + + + $PROJ_DIR$\rzn\board\rzn2l_rsk\board_leds.h + + + $PROJ_DIR$\rzn\fsp\inc\api\bsp_api.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_cache.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_cache.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_cache_core.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_cache_core.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_clocks.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_clocks.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_common.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_common.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_compiler_support.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_delay.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_delay.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_delay_core.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_delay_core.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_elc.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_exceptions.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_feature.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_io.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_io.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_irq.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_irq.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_irq_core.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\cr\bsp_irq_core.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_irq_sense.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_loader_param.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_mcu_api.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_mcu_info.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_module_stop.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\rzn2l\bsp_override.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_register_protection.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_register_protection.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_reset.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_reset.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_sbrk.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\mcu\all\bsp_tfu.h + + + $PROJ_DIR$\rzn\arm\CMSIS_5\CMSIS\Core_R\Include\cmsis_compiler.h + + + $PROJ_DIR$\rzn\arm\CMSIS_5\CMSIS\Core_R\Include\cmsis_cp15.h + + + $PROJ_DIR$\rzn\arm\CMSIS_5\CMSIS\Core_R\Include\cmsis_gcc.h + + + $PROJ_DIR$\rzn\arm\CMSIS_5\CMSIS\Core_R\Include\cmsis_iccarm.h + + + $PROJ_DIR$\rzn\arm\CMSIS_5\CMSIS\Core_R\Include\cmsis_version.h + + + $PROJ_DIR$\rzn\arm\CMSIS_5\CMSIS\Core_R\Include\core_cr52.h + + + $PROJ_DIR$\rzn\fsp\inc\fsp_common_api.h + + + $PROJ_DIR$\rzn\fsp\inc\fsp_features.h + + + $PROJ_DIR$\rzn\fsp\inc\fsp_version.h + + + $PROJ_DIR$\rzn\arm\CMSIS_5\LICENSE.txt + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Include\R9A07G084.h + + + $PROJ_DIR$\rzn\fsp\src\r_cmt\r_cmt.c + + + $PROJ_DIR$\rzn\fsp\inc\instances\r_cmt.h + + + $PROJ_DIR$\rzn\fsp\inc\api\r_ether_api.h + + + $PROJ_DIR$\rzn\fsp\src\r_ether_phy\r_ether_phy.c + + + $PROJ_DIR$\rzn\fsp\inc\instances\r_ether_phy.h + + + $PROJ_DIR$\rzn\fsp\inc\api\r_ether_phy_api.h + + + $PROJ_DIR$\rzn\fsp\src\r_ether_selector\r_ether_selector.c + + + $PROJ_DIR$\rzn\fsp\inc\instances\r_ether_selector.h + + + $PROJ_DIR$\rzn\fsp\inc\api\r_ether_selector_api.h + + + $PROJ_DIR$\rzn\fsp\inc\api\r_ether_switch_api.h + + + $PROJ_DIR$\rzn\fsp\src\r_ethsw\r_ethsw.c + + + $PROJ_DIR$\rzn\fsp\inc\instances\r_ethsw.h + + + $PROJ_DIR$\rzn\fsp\src\r_gmac\r_gmac.c + + + $PROJ_DIR$\rzn\fsp\inc\instances\r_gmac.h + + + $PROJ_DIR$\rzn\fsp\src\r_ioport\r_ioport.c + + + $PROJ_DIR$\rzn\fsp\inc\instances\r_ioport.h + + + $PROJ_DIR$\rzn\fsp\inc\api\r_ioport_api.h + + + $PROJ_DIR$\rzn\fsp\src\r_sci_uart\r_sci_uart.c + + + $PROJ_DIR$\rzn\fsp\inc\instances\r_sci_uart.h + + + $PROJ_DIR$\rzn\fsp\inc\api\r_timer_api.h + + + $PROJ_DIR$\rzn\fsp\inc\api\r_transfer_api.h + + + $PROJ_DIR$\rzn\fsp\inc\api\r_uart_api.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Include\renesas.h + + + $PROJ_DIR$\rzn\fsp\src\rm_ethercat_ssc_port\renesashw.h + + + $PROJ_DIR$\rzn\fsp\src\rm_ethercat_ssc_port\rm_ethercat_ssc_port.c + + + $PROJ_DIR$\rzn\fsp\inc\instances\rm_ethercat_ssc_port.h + + + $PROJ_DIR$\rzn\fsp\inc\api\rm_ethercat_ssc_port_api.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\startup.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\startup_core.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\system.c + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Include\system.h + + + $PROJ_DIR$\rzn\fsp\src\bsp\cmsis\Device\RENESAS\Source\cr\system_core.c + + + + Generated Data + + $PROJ_DIR$\rzn_gen\bsp_clock_cfg.h + + + $PROJ_DIR$\rzn_gen\common_data.c + + + $PROJ_DIR$\rzn_gen\common_data.h + + + $PROJ_DIR$\rzn_gen\hal_data.c + + + $PROJ_DIR$\rzn_gen\hal_data.h + + + $PROJ_DIR$\rzn_gen\main.c + + + $PROJ_DIR$\rzn_gen\pin_data.c + + + $PROJ_DIR$\rzn_gen\vector_data.c + + + $PROJ_DIR$\rzn_gen\vector_data.h + + + + Program Entry + + $PROJ_DIR$\src\hal_entry.c + + + + + $PROJ_DIR$\buildinfo.ipcf + IAR.ControlFile + + diff --git a/bsp/renesas/rzn2l_rsk/template.eww b/bsp/renesas/rzn2l_rsk/template.eww new file mode 100644 index 00000000000..53e2ec6f096 --- /dev/null +++ b/bsp/renesas/rzn2l_rsk/template.eww @@ -0,0 +1,7 @@ + + + + $WS_DIR$\template.ewp + + + diff --git a/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md b/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md index b57dfda12a2..ff0ead3e28c 100644 --- a/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md +++ b/bsp/stm32/docs/How to make a STM32 BSP for RT-Thread.md @@ -68,21 +68,27 @@ Create a CubeMX project based on the target chip. The default CubeMX project is Change the chip model to STM32F103C8Tx in the CubeMX project. +Note:The version of CubeMX used in this article is 6.12.0 + #### 3.2.1 Generate CubeMX project Configure the system clock, peripheral pins, etc. The steps are shown in the figure below: 1. Turn on the external clock, set the download mode, and turn on the serial peripherals (note that only the pins of the serial peripherals need to be selected, no other parameters need to be configured): - ![Configure chip pins](./figures_en/CubeMX_1.png) + ![Turn on the clock](./figures_en/CubeMX_1.png) + + ![Configuring the download Mode](figures_en/CubeMX_2.png) + + ![Open the serial port](figures_en/CubeMX_3.png) 2. Configure the system clock: - ![Configuring the System Clock](./figures_en/CubeMX_2.png) + ![Configuring the System Clock](./figures_en/CubeMX_4.png) 3. Set the project name and regenerate the CubeMX project at a specified address: - ![Generate the corresponding configuration code](./figures_en/CubeMX_4.png) + ![Generate the corresponding configuration code](./figures_en/CubeMX_5.png) Note: When generating the code, do not check the following options (ie: Do not let it generate a peripheral initialization as a pair of .c/.h files per perioheral.) @@ -90,7 +96,7 @@ Configure the system clock, peripheral pins, etc. The steps are shown in the fig 4. The final project directory structure generated by CubeMX is shown in the figure below: - ![CubeMX 7](./figures_en/CubeMX_5.png) + ![CubeMX 7](./figures_en/CubeMX_6.png) #### 3.2.2 Copy initialization function diff --git "a/bsp/stm32/docs/STM32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" "b/bsp/stm32/docs/STM32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" index fc32ecdcdc6..b70fa1439b7 100644 --- "a/bsp/stm32/docs/STM32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" +++ "b/bsp/stm32/docs/STM32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" @@ -101,21 +101,33 @@ BSP 的制作过程分为如下五个步骤： 在 CubeMX 工程中将芯片型号为修改芯片型号为 STM32F103RBTx 。 +注意：本文使用的CubeMX版本为6.12.0 + #### 3.2.1 生成 CubeMX 工程 配置系统时钟、外设引脚等，步骤如下图所示： 1. 打开外部时钟、设置下载方式、打开串口外设（注意只需要选择串口外设引脚即可，无需配置其他参数）： -![配置芯片引脚](./figures/CubeMX_1.png) +![打开外部时钟](./figures/CubeMX_1.png) + +![设置下载方式](./figures/CubeMX_2.png) + + + +![配置串口](figures/CubeMX_3.png) + + + + 2. 配置系统时钟： -![配置系统时钟](./figures/CubeMX_2.png) +![配置系统时钟](figures/CubeMX_4.png) 3. 设置项目名称，并在指定地址重新生成 CubeMX 工程： -![生成对应的配置代码](./figures/CubeMX_4.png) +![生成对应的配置代码](figures/CubeMX_5.png) 注意：在生成代码时，不要勾选以下选项（即：不让其生成单独的 .c/.h 驱动文件，直接全部更新到 rt-thread 要使用的 stm32xxx_hal_msp.c 文件中） @@ -123,7 +135,7 @@ BSP 的制作过程分为如下五个步骤： 最终 CubeMX 生成的工程目录结构如下图所示： -![CubeMX 图7](./figures/CubeMX_5.png) +![CubeMX 图7](./figures/CubeMX_6.png) #### 3.2.2 拷贝初始化函数 diff --git a/bsp/stm32/docs/figures/CubeMX_1.png b/bsp/stm32/docs/figures/CubeMX_1.png index 676238dd62c..07a60f7b7c7 100644 Binary files a/bsp/stm32/docs/figures/CubeMX_1.png and b/bsp/stm32/docs/figures/CubeMX_1.png differ diff --git a/bsp/stm32/docs/figures/CubeMX_2.png b/bsp/stm32/docs/figures/CubeMX_2.png index 2a15bcb9fbf..352a36db483 100644 Binary files a/bsp/stm32/docs/figures/CubeMX_2.png and b/bsp/stm32/docs/figures/CubeMX_2.png differ diff --git a/bsp/stm32/docs/figures/CubeMX_3.png b/bsp/stm32/docs/figures/CubeMX_3.png index 6926aed72d5..6683b05f78b 100644 Binary files a/bsp/stm32/docs/figures/CubeMX_3.png and b/bsp/stm32/docs/figures/CubeMX_3.png differ diff --git a/bsp/stm32/docs/figures/CubeMX_4.png b/bsp/stm32/docs/figures/CubeMX_4.png index 055e1a5d56b..54433b53841 100644 Binary files a/bsp/stm32/docs/figures/CubeMX_4.png and b/bsp/stm32/docs/figures/CubeMX_4.png differ diff --git a/bsp/stm32/docs/figures/CubeMX_5.png b/bsp/stm32/docs/figures/CubeMX_5.png index ec5f929abdf..937e7a47802 100644 Binary files a/bsp/stm32/docs/figures/CubeMX_5.png and b/bsp/stm32/docs/figures/CubeMX_5.png differ diff --git a/bsp/stm32/docs/figures/CubeMX_6.png b/bsp/stm32/docs/figures/CubeMX_6.png new file mode 100644 index 00000000000..ec5f929abdf Binary files /dev/null and b/bsp/stm32/docs/figures/CubeMX_6.png differ diff --git a/bsp/stm32/docs/figures_en/CubeMX_1.png b/bsp/stm32/docs/figures_en/CubeMX_1.png index df1501aa3d2..07a60f7b7c7 100644 Binary files a/bsp/stm32/docs/figures_en/CubeMX_1.png and b/bsp/stm32/docs/figures_en/CubeMX_1.png differ diff --git a/bsp/stm32/docs/figures_en/CubeMX_2.png b/bsp/stm32/docs/figures_en/CubeMX_2.png index f4d55c961dc..352a36db483 100644 Binary files a/bsp/stm32/docs/figures_en/CubeMX_2.png and b/bsp/stm32/docs/figures_en/CubeMX_2.png differ diff --git a/bsp/stm32/docs/figures_en/CubeMX_3.png b/bsp/stm32/docs/figures_en/CubeMX_3.png index 4b5fc8870a0..6683b05f78b 100644 Binary files a/bsp/stm32/docs/figures_en/CubeMX_3.png and b/bsp/stm32/docs/figures_en/CubeMX_3.png differ diff --git a/bsp/stm32/docs/figures_en/CubeMX_4.png b/bsp/stm32/docs/figures_en/CubeMX_4.png index de0c6188cd6..54433b53841 100644 Binary files a/bsp/stm32/docs/figures_en/CubeMX_4.png and b/bsp/stm32/docs/figures_en/CubeMX_4.png differ diff --git a/bsp/stm32/docs/figures_en/CubeMX_5.png b/bsp/stm32/docs/figures_en/CubeMX_5.png index 501bf306599..937e7a47802 100644 Binary files a/bsp/stm32/docs/figures_en/CubeMX_5.png and b/bsp/stm32/docs/figures_en/CubeMX_5.png differ diff --git a/bsp/stm32/docs/figures_en/CubeMX_6.png b/bsp/stm32/docs/figures_en/CubeMX_6.png new file mode 100644 index 00000000000..501bf306599 Binary files /dev/null and b/bsp/stm32/docs/figures_en/CubeMX_6.png differ diff --git a/bsp/stm32/stm32f407-rt-spark/board/ports/lvgl/lv_conf.h b/bsp/stm32/stm32f407-rt-spark/board/ports/lvgl/lv_conf.h index ad815137f15..666d6d6c5dc 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/ports/lvgl/lv_conf.h +++ b/bsp/stm32/stm32f407-rt-spark/board/ports/lvgl/lv_conf.h @@ -14,30 +14,25 @@ #include #define LV_COLOR_DEPTH 16 -#define LV_USE_PERF_MONITOR 1 #define MY_DISP_HOR_RES 240 #define MY_DISP_VER_RES 240 -//#define LV_USE_LOG 1 -#ifdef PKG_USING_LV_MUSIC_DEMO /* music player demo */ -#define LV_HOR_RES_MAX MY_DISP_HOR_RES -#define LV_VER_RES_MAX MY_DISP_VER_RES -#define LV_USE_DEMO_RTT_MUSIC 1 -#define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1 -#define LV_FONT_MONTSERRAT_12 1 -#define LV_FONT_MONTSERRAT_16 1 -#define LV_COLOR_SCREEN_TRANSP 1 - +#ifdef PKG_USING_LV_MUSIC_DEMO + #define LV_USE_DEMO_MUSIC 1 + #define LV_HOR_RES_MAX MY_DISP_HOR_RES + #define LV_VER_RES_MAX MY_DISP_VER_RES + #define LV_USE_DEMO_RTT_MUSIC 1 + #define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1 + #define LV_FONT_MONTSERRAT_12 1 + #define LV_FONT_MONTSERRAT_16 1 + #define LV_COLOR_SCREEN_TRANSP 1 #endif - +#define LV_USE_SYSMON 1 +#define LV_USE_PERF_MONITOR 1 +#define LV_USE_DEMO_WIDGETS 1 +#define LV_FONT_MONTSERRAT_24 1 #define LV_USE_DEMO_BENCHMARK 1 - -//#define LV_USE_DEMO_WIDGETS 1 - - -//#define LV_USE_DEMO_MUSIC 1 - #endif diff --git a/bsp/stm32/stm32f407-rt-spark/board/ports/lvgl/lv_port_disp.c b/bsp/stm32/stm32f407-rt-spark/board/ports/lvgl/lv_port_disp.c index b615edb4c68..ff5ac4e9a4b 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/ports/lvgl/lv_port_disp.c +++ b/bsp/stm32/stm32f407-rt-spark/board/ports/lvgl/lv_port_disp.c @@ -26,6 +26,14 @@ #define MY_DISP_VER_RES 240 #endif +#if (PKG_LVGL_VER_NUM >= 0x0803FF) + #define LV_DISP_TYPE lv_display_t + #define lv_COLOR_TYPE uint8_t +#else + #define LV_DISP_TYPE lv_disp_drv_t + #define lv_COLOR_TYPE lv_color_t +#endif + /********************** * TYPEDEFS **********************/ @@ -35,9 +43,7 @@ **********************/ static void disp_init(void); -static void disp_flush(lv_disp_drv_t * disp_drv, const lv_area_t * area, lv_color_t * color_p); -//static void gpu_fill(lv_disp_drv_t * disp_drv, lv_color_t * dest_buf, lv_coord_t dest_width, -// const lv_area_t * fill_area, lv_color_t color); +static void disp_flush(LV_DISP_TYPE * disp_drv, const lv_area_t * area, lv_COLOR_TYPE * color_p); /********************** * STATIC VARIABLES @@ -83,9 +89,6 @@ void lv_port_disp_init(void) * and you only need to change the frame buffer's address. */ - /* Example for 1) */ - static lv_disp_draw_buf_t draw_buf_dsc_1; - /*GCC*/ #if defined ( __GNUC__ ) static lv_color_t buf_1[MY_DISP_HOR_RES * MY_DISP_HOR_RES / 2] __attribute__((section(".LVGLccm"))); /*A buffer for 10 rows*/ @@ -94,16 +97,29 @@ void lv_port_disp_init(void) __attribute__((at(0x10000000))) lv_color_t buf_1[LCD_H * LCD_W / 2]; #endif - lv_disp_draw_buf_init(&draw_buf_dsc_1, buf_1, NULL, MY_DISP_HOR_RES * MY_DISP_HOR_RES / 2); /*Initialize the display buffer*/ /*----------------------------------- * Register the display in LVGL *----------------------------------*/ +#if (PKG_LVGL_VER_NUM >= 0x0803FF) + + lv_display_t *display = lv_display_create(MY_DISP_HOR_RES, MY_DISP_VER_RES); + lv_display_set_buffers(display, buf_1, NULL, sizeof(buf_1), LV_DISPLAY_RENDER_MODE_PARTIAL); /*Initialize the display buffer.*/ + lv_display_set_flush_cb(display, disp_flush); + +#else + + /* Example for 1) */ + static lv_disp_draw_buf_t draw_buf_dsc_1; + + lv_disp_draw_buf_init(&draw_buf_dsc_1, buf_1, NULL, MY_DISP_HOR_RES * MY_DISP_HOR_RES / 2); /*Initialize the display buffer*/ + + /*----------------------------------- + * Register the display in LVGL + *----------------------------------*/ static lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/ lv_disp_drv_init(&disp_drv); /*Basic initialization*/ - /*Set up the functions to access to your display*/ - /*Set the resolution of the display*/ disp_drv.hor_res = MY_DISP_HOR_RES; disp_drv.ver_res = MY_DISP_VER_RES; @@ -114,16 +130,11 @@ void lv_port_disp_init(void) /*Set a display buffer*/ disp_drv.draw_buf = &draw_buf_dsc_1; - /*Required for Example 3)*/ - //disp_drv.full_refresh = 1; - - /* Fill a memory array with a color if you have GPU. - * Note that, in lv_conf.h you can enable GPUs that has built-in support in LVGL. - * But if you have a different GPU you can use with this callback.*/ - //disp_drv.gpu_fill_cb = gpu_fill; - /*Finally register the driver*/ lv_disp_drv_register(&disp_drv); + +#endif + } /********************** @@ -155,35 +166,16 @@ void disp_disable_update(void) /*Flush the content of the internal buffer the specific area on the display *You can use DMA or any hardware acceleration to do this operation in the background but *'lv_disp_flush_ready()' has to be called when finished.*/ -static void disp_flush(lv_disp_drv_t * disp_drv, const lv_area_t * area, lv_color_t * color_p) +static void disp_flush(LV_DISP_TYPE * disp_drv, const lv_area_t * area, lv_COLOR_TYPE * color_p) { extern void lcd_fill_array(rt_uint16_t x_start, rt_uint16_t y_start, rt_uint16_t x_end, rt_uint16_t y_end, void *pcolor); lcd_fill_array(area->x1, area->y1, area->x2, area->y2, color_p); - lv_disp_flush_ready(disp_drv); } -/*OPTIONAL: GPU INTERFACE*/ - -/*If your MCU has hardware accelerator (GPU) then you can use it to fill a memory with a color*/ -//static void gpu_fill(lv_disp_drv_t * disp_drv, lv_color_t * dest_buf, lv_coord_t dest_width, -// const lv_area_t * fill_area, lv_color_t color) -//{ -// /*It's an example code which should be done by your GPU*/ -// int32_t x, y; -// dest_buf += dest_width * fill_area->y1; /*Go to the first line*/ -// -// for(y = fill_area->y1; y <= fill_area->y2; y++) { -// for(x = fill_area->x1; x <= fill_area->x2; x++) { -// dest_buf[x] = color; -// } -// dest_buf+=dest_width; /*Go to the next line*/ -// } -//} - #else /*Enable this file at the top*/ /*This dummy typedef exists purely to silence -Wpedantic.*/ typedef int keep_pedantic_happy; -#endif +#endif \ No newline at end of file diff --git a/components/dfs/dfs_v2/filesystems/devfs/devfs.c b/components/dfs/dfs_v2/filesystems/devfs/devfs.c index c8c66667dbc..22d24bd684b 100644 --- a/components/dfs/dfs_v2/filesystems/devfs/devfs.c +++ b/components/dfs/dfs_v2/filesystems/devfs/devfs.c @@ -408,16 +408,16 @@ mode_t dfs_devfs_device_to_mode(struct rt_device *device) switch (device->type) { case RT_Device_Class_Char: - mode = S_IFCHR | 0777; + mode = S_IFCHR | 0666; break; case RT_Device_Class_Block: - mode = S_IFBLK | 0777; + mode = S_IFBLK | 0666; break; case RT_Device_Class_Pipe: - mode = S_IFIFO | 0777; + mode = S_IFIFO | 0666; break; default: - mode = S_IFCHR | 0777; + mode = S_IFCHR | 0666; break; } diff --git a/components/dfs/dfs_v2/include/dfs_seq_file.h b/components/dfs/dfs_v2/include/dfs_seq_file.h index 6dbc30f24d5..f0c1de7ddeb 100644 --- a/components/dfs/dfs_v2/include/dfs_seq_file.h +++ b/components/dfs/dfs_v2/include/dfs_seq_file.h @@ -56,7 +56,7 @@ static inline void dfs_seq_setwidth(struct dfs_seq_file *seq, size_t size) int dfs_seq_open(struct dfs_file *file, const struct dfs_seq_ops *ops); ssize_t dfs_seq_read(struct dfs_file *file, void *buf, size_t size, off_t *pos); -ssize_t dfs_seq_lseek(struct dfs_file *file, off_t offset, int whence); +off_t dfs_seq_lseek(struct dfs_file *file, off_t offset, int whence); int dfs_seq_release(struct dfs_file *file); int dfs_seq_write(struct dfs_seq_file *seq, const void *data, size_t len); diff --git a/components/dfs/dfs_v2/src/dfs_seq_file.c b/components/dfs/dfs_v2/src/dfs_seq_file.c index 9521f530380..2980b03cc12 100644 --- a/components/dfs/dfs_v2/src/dfs_seq_file.c +++ b/components/dfs/dfs_v2/src/dfs_seq_file.c @@ -256,7 +256,7 @@ ssize_t dfs_seq_read(struct dfs_file *file, void *buf, size_t size, off_t *pos) goto Done; } -ssize_t dfs_seq_lseek(struct dfs_file *file, off_t offset, int whence) +off_t dfs_seq_lseek(struct dfs_file *file, off_t offset, int whence) { struct dfs_seq_file *seq = file->data; off_t retval = -EINVAL; diff --git a/components/drivers/core/device.c b/components/drivers/core/device.c index 49b428a5771..5dfd0c4653e 100644 --- a/components/drivers/core/device.c +++ b/components/drivers/core/device.c @@ -13,6 +13,8 @@ * 2013-07-09 Grissiom add ref_count support * 2016-04-02 Bernard fix the open_flag initialization issue. * 2021-03-19 Meco Man remove rt_device_init_all() + * 2024-09-15 milo fix log format issue + * fix reopen with a different oflag issue */ #include @@ -195,8 +197,8 @@ rt_err_t rt_device_init(rt_device_t dev) result = device_init(dev); if (result != RT_EOK) { - LOG_E("To initialize device:%s failed. The error code is %d", - dev->parent.name, result); + LOG_E("To initialize device:%.*s failed. The error code is %d", + RT_NAME_MAX, dev->parent.name, result); } else { @@ -233,8 +235,8 @@ rt_err_t rt_device_open(rt_device_t dev, rt_uint16_t oflag) result = device_init(dev); if (result != RT_EOK) { - LOG_E("To initialize device:%s failed. The error code is %d", - dev->parent.name, result); + LOG_E("To initialize device:%.*s failed. The error code is %d", + RT_NAME_MAX, dev->parent.name, result); return result; } @@ -252,7 +254,7 @@ rt_err_t rt_device_open(rt_device_t dev, rt_uint16_t oflag) /* device is not opened or opened by other oflag, call device_open interface */ if (!(dev->open_flag & RT_DEVICE_OFLAG_OPEN) || - ((dev->open_flag & RT_DEVICE_OFLAG_MASK) != (oflag & RT_DEVICE_OFLAG_MASK))) + ((dev->open_flag & RT_DEVICE_OFLAG_MASK) != ((oflag & RT_DEVICE_OFLAG_MASK) | RT_DEVICE_OFLAG_OPEN))) { if (device_open != RT_NULL) { diff --git a/components/drivers/include/drivers/adc.h b/components/drivers/include/drivers/adc.h index 7c35f1eac63..cdb7b2704a5 100644 --- a/components/drivers/include/drivers/adc.h +++ b/components/drivers/include/drivers/adc.h @@ -14,12 +14,65 @@ #define __ADC_H__ #include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup ADC ADC + * + * @brief ADC driver api + * + * Example + * @code {.c} + * #define ADC_DEV_NAME "adc1" + * #define ADC_DEV_CHANNEL 5 + * #define REFER_VOLTAGE 330 + * #define CONVERT_BITS (1 << 12) + * + * static int adc_vol_sample(int argc, char *argv[]) + * { + * rt_adc_device_t adc_dev; + * rt_uint32_t value, vol; + * + * rt_err_t ret = RT_EOK; + * + * adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME); + * if (adc_dev == RT_NULL) + * { + * rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME); + * return RT_ERROR; + * } + * + * ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL); + * + * value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL); + * rt_kprintf("the value is :%d \n", value); + * + * vol = value * REFER_VOLTAGE / CONVERT_BITS; + * rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + * + * ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL); + * + * return ret; + * } + * MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample); + * + * @endcode + * + * @ingroup Drivers + */ + +/*! + * @addtogroup ADC + * @{ + */ #define RT_ADC_INTERN_CH_TEMPER (-1) #define RT_ADC_INTERN_CH_VREF (-2) #define RT_ADC_INTERN_CH_VBAT (-3) struct rt_adc_device; +/** + * @brief Configure the adc device + */ struct rt_adc_ops { rt_err_t (*enabled)(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled); @@ -27,7 +80,9 @@ struct rt_adc_ops rt_uint8_t (*get_resolution)(struct rt_adc_device *device); rt_int16_t (*get_vref) (struct rt_adc_device *device); }; - +/** + * @brief adc device + */ struct rt_adc_device { struct rt_device parent; @@ -43,10 +98,53 @@ typedef enum RT_ADC_CMD_GET_VREF = RT_DEVICE_CTRL_BASE(ADC) + 4, /* get reference voltage */ } rt_adc_cmd_t; +/** + * @brief register the adc device + * @param adc adc device + * @param name device name + * @param ops device ops + * @param user_data device private data + * @return rt_err_t error code + * @ingroup ADC + */ rt_err_t rt_hw_adc_register(rt_adc_device_t adc,const char *name, const struct rt_adc_ops *ops, const void *user_data); + +/** + * @brief read the adc value + * @param dev adc device + * @param channel adc channel + * @return rt_uint32_t adc value + * @ingroup ADC + */ rt_uint32_t rt_adc_read(rt_adc_device_t dev, rt_int8_t channel); + +/** + * @brief enable the adc channel + * @param dev adc device + * @param channel adc channel + * @return rt_err_t error code + * @ingroup ADC + */ rt_err_t rt_adc_enable(rt_adc_device_t dev, rt_int8_t channel); + +/** + * @brief disable the adc channel + * @param dev adc device + * @param channel adc channel + * @return rt_err_t error code + * @ingroup ADC + */ rt_err_t rt_adc_disable(rt_adc_device_t dev, rt_int8_t channel); + +/** + * @brief get the adc resolution + * @param dev adc device + * @param channel adc channel + * @return rt_int16_t adc resolution + * @ingroup ADC + */ rt_int16_t rt_adc_voltage(rt_adc_device_t dev, rt_int8_t channel); +/*! @}*/ + #endif /* __ADC_H__ */ diff --git a/components/drivers/include/drivers/dac.h b/components/drivers/include/drivers/dac.h index c03fa109295..f3635d50b62 100644 --- a/components/drivers/include/drivers/dac.h +++ b/components/drivers/include/drivers/dac.h @@ -11,8 +11,66 @@ #ifndef __DAC_H__ #define __DAC_H__ #include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup DAC DAC + * + * @brief DAC driver api + * + * Example + * @code {.c} + * + * #include + * #include + * #include + * #define DAC_DEV_NAME "dac1" + * #define DAC_DEV_CHANNEL 1 + * #define REFER_VOLTAGE 330 + * #define CONVERT_BITS (1 << 12) + * + * static int dac_vol_sample(int argc, char *argv[]) + * { + * rt_dac_device_t dac_dev; + * rt_uint32_t value, vol; + * rt_err_t ret = RT_EOK; + * + * dac_dev = (rt_dac_device_t)rt_device_find(DAC_DEV_NAME); + * if (dac_dev == RT_NULL) + * { + * rt_kprintf("dac sample run failed! can't find %s device!\n", DAC_DEV_NAME); + * return RT_ERROR; + * } + * + * ret = rt_dac_enable(dac_dev, DAC_DEV_CHANNEL); + * + * value = atoi(argv[1]); + * rt_dac_write(dac_dev, DAC_DEV_NAME, DAC_DEV_CHANNEL, value); + * rt_kprintf("the value is :%d \n", value); + * + * vol = value * REFER_VOLTAGE / CONVERT_BITS; + * rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100); + * + * rt_thread_mdelay(500); + * + * ret = rt_dac_disable(dac_dev, DAC_DEV_CHANNEL); + * + * return ret; + * } + * MSH_CMD_EXPORT(dac_vol_sample, dac voltage convert sample); + * + * @endcode + * + * @ingroup Drivers + */ +/*! + * @addtogroup DAC + * @{ + */ struct rt_dac_device; +/** + * @brief Configuration of DAC device + */ struct rt_dac_ops { rt_err_t (*disabled)(struct rt_dac_device *device, rt_uint32_t channel); @@ -20,7 +78,10 @@ struct rt_dac_ops rt_err_t (*convert)(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value); rt_uint8_t (*get_resolution)(struct rt_dac_device *device); }; - +/** + * @brief DAC device structure + * + */ struct rt_dac_device { struct rt_device parent; @@ -35,10 +96,41 @@ typedef enum RT_DAC_CMD_GET_RESOLUTION = RT_DEVICE_CTRL_BASE(DAC) + 2, } rt_dac_cmd_t; +/** + * @brief Register a DAC device + * @param dac DAC device + * @param name DAC name + * @param ops the operations of DAC device + * @param user_data device private data + * @return rt_err_t error code + */ rt_err_t rt_hw_dac_register(rt_dac_device_t dac,const char *name, const struct rt_dac_ops *ops, const void *user_data); +/** + * @brief set the value of DAC + * @param dev DAC device + * @param channel DAC channel + * @param value the value of DAC + * @return rt_err_t error code + */ rt_err_t rt_dac_write(rt_dac_device_t dev, rt_uint32_t channel, rt_uint32_t value); + +/** + * @brief enable the DAC channel + * @param dev DAC device + * @param channel DAC channel + * @return rt_err_t error code + */ rt_err_t rt_dac_enable(rt_dac_device_t dev, rt_uint32_t channel); + +/** + * @brief disable the DAC channel + * @param dev DAC device + * @param channel DAC channel + * @return rt_err_t error code + */ rt_err_t rt_dac_disable(rt_dac_device_t dev, rt_uint32_t channel); +/*! @}*/ + #endif /* __dac_H__ */ diff --git a/components/drivers/include/drivers/dev_can.h b/components/drivers/include/drivers/dev_can.h index 9f2d7c06778..6881d5d613a 100644 --- a/components/drivers/include/drivers/dev_can.h +++ b/components/drivers/include/drivers/dev_can.h @@ -63,9 +63,16 @@ enum CANBAUD #define RT_CAN_MODE_PRIV 0x01 #define RT_CAN_MODE_NOPRIV 0x00 -/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number - * @{ - */ +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup CAN_Device CAN Driver + * @ingroup Drivers + */ + +/*! + * @addtogroup CAN_Device + * @{ + */ #define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ #define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ @@ -360,5 +367,8 @@ rt_err_t rt_hw_can_register(struct rt_can_device *can, const struct rt_can_ops *ops, void *data); void rt_hw_can_isr(struct rt_can_device *can, int event); -#endif /*__DEV_CAN_H*/ +/*! @} +*/ + +#endif /*__DEV_CAN_H*/ \ No newline at end of file diff --git a/components/drivers/include/drivers/dev_rtc.h b/components/drivers/include/drivers/dev_rtc.h index 96658968e56..740142d3d78 100644 --- a/components/drivers/include/drivers/dev_rtc.h +++ b/components/drivers/include/drivers/dev_rtc.h @@ -16,7 +16,70 @@ #include #include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup RTC RTC + * + * @brief RTC driver api + * + * Example + * @code {.c} + * + * #include + * #include + * + * #define RTC_NAME "rtc" + * + * static int rtc_sample(int argc, char *argv[]) + * { + * rt_err_t ret = RT_EOK; + * time_t now; + * rt_device_t device = RT_NULL; + * + * device = rt_device_find(RTC_NAME); + * if (!device) + * { + * LOG_E("find %s failed!", RTC_NAME); + * return RT_ERROR; + * } + * + * if(rt_device_open(device, 0) != RT_EOK) + * { + * LOG_E("open %s failed!", RTC_NAME); + * return RT_ERROR; + * } + * + * ret = set_date(2018, 12, 3); + * if (ret != RT_EOK) + * { + * rt_kprintf("set RTC date failed\n"); + * return ret; + * } + * + * ret = set_time(11, 15, 50); + * if (ret != RT_EOK) + * { + * rt_kprintf("set RTC time failed\n"); + * return ret; + * } + * + * rt_thread_mdelay(3000); + * + * now = time(RT_NULL); + * rt_kprintf("%s\n", ctime(&now)); + * + * return ret; + * } + * MSH_CMD_EXPORT(rtc_sample, rtc sample); + * @endcode + * + * @ingroup Drivers + */ +/*! + * @addtogroup RTC + * @{ + */ #ifdef __cplusplus extern "C" { #endif @@ -31,7 +94,9 @@ extern "C" { #define RT_DEVICE_CTRL_RTC_SET_TIMESPEC (RT_DEVICE_CTRL_BASE(RTC) + 0x08) /**< set timespec for clock_settime */ #define RT_DEVICE_CTRL_RTC_GET_TIMERES (RT_DEVICE_CTRL_BASE(RTC) + 0x09) /**< get resolution for clock_getres */ -/* used for alarm function */ +/** + * @brief RTC alarm structure + */ struct rt_rtc_wkalarm { rt_bool_t enable; /* 0 = alarm disabled, 1 = alarm enabled */ @@ -42,7 +107,9 @@ struct rt_rtc_wkalarm rt_int32_t tm_mon; /* alarm at tm_mon */ rt_int32_t tm_year; /* alarm at tm_year */ }; - +/** + * @brief RTC operations + */ struct rt_rtc_ops { rt_err_t (*init)(void); @@ -54,20 +121,63 @@ struct rt_rtc_ops rt_err_t (*set_timeval)(struct timeval *tv); }; +/** + * @brief RTC device structure + */ typedef struct rt_rtc_device { struct rt_device parent; const struct rt_rtc_ops *ops; } rt_rtc_dev_t; +/** + * @brief Register a RTC device + * + * @param rtc RTC device + * @param name RTC device name + * @param flag RTC device flag + * @param data RTC device data + * @return rt_err_t error code + */ rt_err_t rt_hw_rtc_register(rt_rtc_dev_t *rtc, const char *name, rt_uint32_t flag, void *data); +/** + * @brief set date + * + * @param year year + * @param month month + * @param day day + * @return rt_err_t error code + */ rt_err_t set_date(rt_uint32_t year, rt_uint32_t month, rt_uint32_t day); + +/** + * @brief set time + * + * @param hour hour + * @param minute minute + * @param second second + * @return rt_err_t error code +*/ rt_err_t set_time(rt_uint32_t hour, rt_uint32_t minute, rt_uint32_t second); + +/** + * @brief set timestamp + * + * @param timestamp A pointer to time + * @return rt_err_t error code + */ rt_err_t set_timestamp(time_t timestamp); + +/** + * @brief get timestamp + * + * @param timestamp A secondary pointer to time + * @return rt_err_t error code + */ rt_err_t get_timestamp(time_t *timestamp); #ifdef RT_USING_SYSTEM_WORKQUEUE @@ -79,4 +189,6 @@ rt_err_t rt_soft_rtc_set_source(const char *name); } #endif +/*! @}*/ + #endif /* __DEV_RTC_H__ */ diff --git a/components/drivers/include/drivers/dev_serial.h b/components/drivers/include/drivers/dev_serial.h index 418c25fa1d9..df2a62030aa 100644 --- a/components/drivers/include/drivers/dev_serial.h +++ b/components/drivers/include/drivers/dev_serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2006-2024 RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,7 +15,105 @@ #define __DEV_SERIAL_H__ #include +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup Serial Serial + * + * @brief Serial driver api + * + * Example + * @code {.c} + * + * #include + * + * #define SAMPLE_UART_NAME "uart2" + * static struct rt_semaphore rx_sem; + * static rt_device_t serial; + * + * static rt_err_t uart_input(rt_device_t dev, rt_size_t size) + * { + * + * rt_sem_release(&rx_sem); + * + * return RT_EOK; + * } + * + * static void serial_thread_entry(void *parameter) + * { + * char ch; + * + * while (1) + * { + * + * while (rt_device_read(serial, -1, &ch, 1) != 1) + * { + * + * rt_sem_take(&rx_sem, RT_WAITING_FOREVER); + * } + * + * ch = ch + 1; + * rt_device_write(serial, 0, &ch, 1); + * } + * } + * + * static int uart_sample(int argc, char *argv[]) + * { + * rt_err_t ret = RT_EOK; + * char uart_name[RT_NAME_MAX]; + * char str[] = "hello RT-Thread!\r\n"; + * + * if (argc == 2) + * { + * rt_strncpy(uart_name, argv[1], RT_NAME_MAX); + * } + * else + * { + * rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX); + * } + * + * + * serial = rt_device_find(uart_name); + * if (!serial) + * { + * rt_kprintf("find %s failed!\n", uart_name); + * return RT_ERROR; + * } + * + * + * rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO); + * + * rt_device_open(serial, RT_DEVICE_FLAG_INT_RX); + * + * rt_device_set_rx_indicate(serial, uart_input); + * + * rt_device_write(serial, 0, str, (sizeof(str) - 1)); + * + * + * rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10); + * + * if (thread != RT_NULL) + * { + * rt_thread_startup(thread); + * } + * else + * { + * ret = RT_ERROR; + * } + * + * return ret; + * } + * + * MSH_CMD_EXPORT(uart_sample, uart device sample); + * @endcode + * + * @ingroup Drivers + */ + +/*! + * @addtogroup Serial + * @{ + */ #define BAUD_RATE_2400 2400 #define BAUD_RATE_4800 4800 #define BAUD_RATE_9600 9600 @@ -105,7 +203,6 @@ /** * @brief Sets a hook function when RX indicate is called * - * @param thread is the target thread that initializing */ typedef void (*rt_hw_serial_rxind_hookproto_t)(rt_device_t dev, rt_size_t size); RT_OBJECT_HOOKLIST_DECLARE(rt_hw_serial_rxind_hookproto_t, rt_hw_serial_rxind); @@ -173,7 +270,7 @@ struct rt_serial_device typedef struct rt_serial_device rt_serial_t; /** - * uart operators + * @brief Configure the serial device */ struct rt_uart_ops { @@ -186,13 +283,41 @@ struct rt_uart_ops rt_ssize_t (*dma_transmit)(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction); }; +/** + * @brief Serial interrupt service routine + * @param serial serial device + * @param event event mask + * @ingroup Serial + */ void rt_hw_serial_isr(struct rt_serial_device *serial, int event); +/** + * @brief Register a serial device to device list + * + * @param serial serial device + * @param name device name + * @param flag device flag + * @param data device private data + * @return rt_err_t error code + * @note This function will register a serial device to system device list, + * and add a device object to system object list. + * @ingroup Serial + */ rt_err_t rt_hw_serial_register(struct rt_serial_device *serial, const char *name, rt_uint32_t flag, void *data); +/** + * @brief register a serial device to system device list and add a device object to system object list + * + * @param serial serial device + * @return rt_err_t error code + * + * @ingroup Serial + */ rt_err_t rt_hw_serial_register_tty(struct rt_serial_device *serial); +/*! @}*/ + #endif diff --git a/components/drivers/include/drivers/dev_serial_v2.h b/components/drivers/include/drivers/dev_serial_v2.h index 0c3d095ab31..0bdc51b7baf 100644 --- a/components/drivers/include/drivers/dev_serial_v2.h +++ b/components/drivers/include/drivers/dev_serial_v2.h @@ -13,6 +13,122 @@ #include + +/** + * @addtogroup Drivers RTTHREAD Driver + * @defgroup Serial_v2 Serial v2 + * + * @brief Serial v2 driver api + * + * Example + * @code {.c} + * + * #include + * #include + * + * #define SAMPLE_UART_NAME "uart1" + * + * struct rx_msg + * { + * rt_device_t dev; + * rt_size_t size; + * }; + * static rt_device_t serial; + * static struct rt_messagequeue rx_mq; + * + * static rt_err_t uart_input(rt_device_t dev, rt_size_t size) + * { + * struct rx_msg msg; + * rt_err_t result; + * msg.dev = dev; + * msg.size = size; + * + * result = rt_mq_send(&rx_mq, &msg, sizeof(msg)); + * if (result == -RT_EFULL) + * { + * rt_kprintf("message queue full！\n"); + * } + * return result; + * } + * + * static void serial_thread_entry(void *parameter) + * { + * struct rx_msg msg; + * rt_err_t result; + * rt_uint32_t rx_length; + * static char rx_buffer[BSP_UART1_RX_BUFSIZE + 1]; + * + * while (1) + * { + * rt_memset(&msg, 0, sizeof(msg)); + * result = rt_mq_recv(&rx_mq, &msg, sizeof(msg), RT_WAITING_FOREVER); + * if (result > 0) + * { + * rx_length = rt_device_read(msg.dev, 0, rx_buffer, msg.size); + * rx_buffer[rx_length] = '\0'; + * rt_device_write(serial, 0, rx_buffer, rx_length); + * rt_kprintf("%s\n",rx_buffer); + * } + * } + * } + * + * static int uart_dma_sample(int argc, char *argv[]) + * { + * rt_err_t ret = RT_EOK; + * char uart_name[RT_NAME_MAX]; + * static char msg_pool[256]; + * char str[] = "hello RT-Thread!\r\n"; + * + * if (argc == 2) + * { + * rt_strncpy(uart_name, argv[1], RT_NAME_MAX); + * } + * else + * { + * rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX); + * } + * + * serial = rt_device_find(uart_name); + * if (!serial) + * { + * rt_kprintf("find %s failed!\n", uart_name); + * return RT_ERROR; + * } + * + * rt_mq_init(&rx_mq, "rx_mq", + * msg_pool, + * sizeof(struct rx_msg), + * sizeof(msg_pool), + * RT_IPC_FLAG_FIFO); + * + * rt_device_open(serial, RT_DEVICE_FLAG_RX_NON_BLOCKING | RT_DEVICE_FLAG_TX_BLOCKING); + * rt_device_set_rx_indicate(serial, uart_input); + * rt_device_write(serial, 0, str, (sizeof(str) - 1)); + * + * rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10); + * if (thread != RT_NULL) + * { + * rt_thread_startup(thread); + * } + * else + * { + * ret = RT_ERROR; + * } + * + * return ret; + * } + * MSH_CMD_EXPORT(uart_dma_sample, uart device dma sample); + * @endcode + * + * @ingroup Drivers + */ + + +/*! + * @addtogroup Serial_v2 + * @{ + */ + #define BAUD_RATE_2400 2400 #define BAUD_RATE_4800 4800 #define BAUD_RATE_9600 9600 @@ -104,9 +220,8 @@ } /** - * @brief Sets a hook function when RX indicate is called - * - * @param thread is the target thread that initializing + * @brief Serial receive indicate hook function type + * */ typedef void (*rt_hw_serial_rxind_hookproto_t)(rt_device_t dev, rt_size_t size); RT_OBJECT_HOOKLIST_DECLARE(rt_hw_serial_rxind_hookproto_t, rt_hw_serial_rxind); @@ -126,8 +241,8 @@ struct serial_configure rt_uint32_t reserved :5; }; -/* - * Serial Receive FIFO mode +/** + * @brief Serial Receive FIFO mode */ struct rt_serial_rx_fifo { @@ -141,8 +256,9 @@ struct rt_serial_rx_fifo rt_uint8_t buffer[]; }; -/* - * Serial Transmit FIFO mode +/** + * @brief Serial Transmit FIFO mode + * */ struct rt_serial_tx_fifo { @@ -158,6 +274,10 @@ struct rt_serial_tx_fifo rt_uint8_t buffer[]; }; +/** + * @brief serial device structure + * + */ struct rt_serial_device { struct rt_device parent; @@ -172,7 +292,8 @@ struct rt_serial_device }; /** - * uart operators + * @brief uart device operations + * */ struct rt_uart_ops { @@ -192,12 +313,43 @@ struct rt_uart_ops rt_uint32_t tx_flag); }; +/** + * @brief Serial interrupt service routine + * @param serial serial device + * @param event event mask + * @ingroup Serial_v2 + */ void rt_hw_serial_isr(struct rt_serial_device *serial, int event); + +/** + * @brief Register a serial device to device list + * + * @param serial serial device + * @param name device name + * @param flag device flag + * @param data device private data + * @return rt_err_t error code + * @note This function will register a serial device to system device list, + * and add a device object to system object list. + * @ingroup Serial_v2 + */ rt_err_t rt_hw_serial_register(struct rt_serial_device *serial, const char *name, rt_uint32_t flag, void *data); +/** + * @brief register a serial device to system device list and add a device object to system object list + * + * @param serial serial device + * @return rt_err_t error code + * + * @ingroup Serial_v2 + */ rt_err_t rt_hw_serial_register_tty(struct rt_serial_device *serial); + + +/*! @}*/ + #endif diff --git a/components/drivers/include/drivers/pic.h b/components/drivers/include/drivers/pic.h index fa1941abbc5..c624d249d1f 100755 --- a/components/drivers/include/drivers/pic.h +++ b/components/drivers/include/drivers/pic.h @@ -148,6 +148,7 @@ void rt_pic_default_name(struct rt_pic *pic); struct rt_pic *rt_pic_dynamic_cast(void *ptr); rt_err_t rt_pic_linear_irq(struct rt_pic *pic, rt_size_t irq_nr); +rt_err_t rt_pic_cancel_irq(struct rt_pic *pic); int rt_pic_config_ipi(struct rt_pic *pic, int ipi_index, int hwirq); int rt_pic_config_irq(struct rt_pic *pic, int irq_index, int hwirq); diff --git a/components/drivers/ofw/fdt.c b/components/drivers/ofw/fdt.c index b9e02e02e56..d1ee385f0f4 100644 --- a/components/drivers/ofw/fdt.c +++ b/components/drivers/ofw/fdt.c @@ -85,15 +85,15 @@ rt_uint64_t rt_fdt_translate_address(void *fdt, int nodeoffset, rt_uint64_t addr if (parent >= 0) { - ranges = fdt_getprop(fdt, nodeoffset, "ranges", &length); + ranges = fdt_getprop(fdt, parent, "ranges", &length); } if (ranges && length > 0) { - local.addr_cells = fdt_address_cells(fdt, nodeoffset); - local.size_cells = fdt_size_cells(fdt, nodeoffset); - cpu.addr_cells = fdt_io_addr_cells(fdt, nodeoffset); - cpu.size_cells = fdt_io_size_cells(fdt, nodeoffset); + local.addr_cells = fdt_address_cells(fdt, parent); + local.size_cells = fdt_size_cells(fdt, parent); + cpu.addr_cells = fdt_io_addr_cells(fdt, parent); + cpu.size_cells = fdt_io_size_cells(fdt, parent); group_len = local.addr_cells + cpu.addr_cells + local.size_cells; @@ -105,7 +105,7 @@ rt_uint64_t rt_fdt_translate_address(void *fdt, int nodeoffset, rt_uint64_t addr if (local.addr <= address && local.addr + local.size > address) { - ret += address - cpu.addr; + ret = address - local.addr + cpu.addr; break; } @@ -247,9 +247,9 @@ static rt_err_t fdt_reserved_memory_reg(int nodeoffset, const char *uname) rt_bool_t is_nomap = fdt_getprop(_fdt, nodeoffset, "no-map", RT_NULL) ? RT_TRUE : RT_FALSE; base = rt_fdt_translate_address(_fdt, nodeoffset, base); - rt_memblock_reserve_memory(uname, base, base + size, is_nomap); - len -= t_len; + rt_memblock_reserve_memory(fdt_get_name(_fdt, nodeoffset, RT_NULL), + base, base + size, is_nomap); } } } diff --git a/components/drivers/pic/Kconfig b/components/drivers/pic/Kconfig index 16c14105a0f..d8d077fb762 100755 --- a/components/drivers/pic/Kconfig +++ b/components/drivers/pic/Kconfig @@ -1,6 +1,7 @@ menuconfig RT_USING_PIC bool "Using Programmable Interrupt Controller (PIC)" - select RT_USING_BITMAP + select RT_USING_ADT + select RT_USING_ADT_BITMAP depends on RT_USING_DM default n @@ -22,12 +23,31 @@ config RT_PIC_ARM_GIC select RT_USING_OFW default n +config RT_PIC_ARM_GIC_V2M + bool "ARM GIC V2M" if RT_PIC_ARM_GIC && RT_PCI_MSI + depends on RT_USING_OFW + default n + config RT_PIC_ARM_GIC_V3 bool "ARM GICv3" depends on RT_USING_PIC select RT_USING_OFW default n +config RT_PIC_ARM_GIC_V3_ITS + bool "ARM GICv3 ITS (Interrupt Translation Service)" if RT_PIC_ARM_GIC_V3 && RT_PCI_MSI + depends on RT_USING_OFW + select RT_USING_ADT_REF + default n + +config RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX + int "IRQ maximum used" + depends on RT_PIC_ARM_GIC_V3_ITS + default 127 if ARCH_CPU_64BIT + default 63 + help + Recommended to be based on the bit length (full bits) of maximum usage. + config RT_PIC_ARM_GIC_MAX_NR int depends on RT_USING_PIC diff --git a/components/drivers/pic/SConscript b/components/drivers/pic/SConscript index e820792aa62..53cb66e1ff0 100644 --- a/components/drivers/pic/SConscript +++ b/components/drivers/pic/SConscript @@ -16,9 +16,15 @@ if GetDepend(['RT_PIC_ARM_GIC']) or GetDepend(['RT_PIC_ARM_GIC_V3']): if GetDepend(['RT_PIC_ARM_GIC']): src += ['pic-gicv2.c'] +if GetDepend(['RT_PIC_ARM_GIC_V2M']): + src += ['pic-gicv2m.c'] + if GetDepend(['RT_PIC_ARM_GIC_V3']): src += ['pic-gicv3.c'] +if GetDepend(['RT_PIC_ARM_GIC_V3_ITS']): + src += ['pic-gicv3-its.c'] + group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/components/drivers/pic/pic-gic-common.h b/components/drivers/pic/pic-gic-common.h index 46841e8ca73..d78e0688d6a 100644 --- a/components/drivers/pic/pic-gic-common.h +++ b/components/drivers/pic/pic-gic-common.h @@ -8,10 +8,14 @@ * 2023-01-30 GuEe-GUI first version */ -#ifndef __IRQ_GIC_COMMON_H__ -#define __IRQ_GIC_COMMON_H__ +#ifndef __PIC_GIC_COMMON_H__ +#define __PIC_GIC_COMMON_H__ #include + +#ifdef RT_PCI_MSI +#include +#endif #include #define GIC_SGI_NR 16 @@ -52,4 +56,4 @@ rt_err_t gicv2m_ofw_probe(struct rt_ofw_node *ic_np, const struct rt_ofw_node_id rt_err_t gicv3_its_ofw_probe(struct rt_ofw_node *ic_np, const struct rt_ofw_node_id *id); #endif -#endif /* __IRQ_GIC_COMMON_H__ */ +#endif /* __PIC_GIC_COMMON_H__ */ diff --git a/components/drivers/pic/pic-gicv2.c b/components/drivers/pic/pic-gicv2.c index adce046a8d3..c92172dd1cd 100644 --- a/components/drivers/pic/pic-gicv2.c +++ b/components/drivers/pic/pic-gicv2.c @@ -128,6 +128,8 @@ static void gicv2_cpu_init(struct gicv2 *gic) #ifdef ARCH_SUPPORT_HYP _gicv2_eoi_mode_ns = RT_TRUE; +#else + _gicv2_eoi_mode_ns = !!rt_ofw_bootargs_select("pic.gicv2_eoimode", 0); #endif if (_gicv2_eoi_mode_ns) diff --git a/components/drivers/pic/pic-gicv2m.c b/components/drivers/pic/pic-gicv2m.c new file mode 100755 index 00000000000..fb18a67d1e5 --- /dev/null +++ b/components/drivers/pic/pic-gicv2m.c @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-07 GuEe-GUI first version + */ + +#include +#include +#include + +#define DBG_TAG "pic.gicv2m" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include "pic-gic-common.h" + +/* +* MSI_TYPER: +* [31:26] Reserved +* [25:16] lowest SPI assigned to MSI +* [15:10] Reserved +* [9:0] Numer of SPIs assigned to MSI +*/ +#define V2M_MSI_TYPER 0x008 +#define V2M_MSI_TYPER_BASE_SHIFT 16 +#define V2M_MSI_TYPER_BASE_MASK 0x3ff +#define V2M_MSI_TYPER_NUM_MASK 0x3ff +#define V2M_MSI_SETSPI_NS 0x040 +#define V2M_MIN_SPI 32 +#define V2M_MAX_SPI 1019 +#define V2M_MSI_IIDR 0xfcc + +#define V2M_MSI_TYPER_BASE_SPI(x) (((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK) +#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK) + +/* APM X-Gene with GICv2m MSI_IIDR register value */ +#define XGENE_GICV2M_MSI_IIDR 0x06000170 +/* Broadcom NS2 GICv2m MSI_IIDR register value */ +#define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f + +/* List of flags for specific v2m implementation */ +#define GICV2M_NEEDS_SPI_OFFSET 0x00000001 +#define GICV2M_GRAVITON_ADDRESS_ONLY 0x00000002 + +struct gicv2m +{ + struct rt_pic parent; + + void *base; + void *base_phy; + rt_uint32_t spi_start; /* The SPI number that MSIs start */ + rt_uint32_t spis_nr; /* The number of SPIs for MSIs */ + rt_uint32_t spi_offset; /* Offset to be subtracted from SPI number */ + + rt_bitmap_t *vectors; /* MSI vector bitmap */ + rt_uint32_t flags; /* Flags for v2m's specific implementation */ + + void *gic; + struct rt_spinlock lock; +}; + +#define raw_to_gicv2m(raw) rt_container_of(raw, struct gicv2m, parent) + +static rt_ubase_t gicv2m_get_msi_addr(struct gicv2m *v2m, int hwirq) +{ + rt_ubase_t addr; + + if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) + { + addr = (rt_ubase_t)v2m->base_phy | ((hwirq - 32) << 3); + } + else + { + addr = (rt_ubase_t)v2m->base_phy + V2M_MSI_SETSPI_NS; + } + + return addr; +} + +static rt_bool_t is_msi_spi_valid(rt_uint32_t base, rt_uint32_t num) +{ + if (base < V2M_MIN_SPI) + { + LOG_E("Invalid MSI base SPI (base: %u)", base); + + return RT_FALSE; + } + else if ((num == 0) || (base + num > V2M_MAX_SPI)) + { + LOG_E("Number of SPIs (%u) exceed maximum (%u)", num, V2M_MAX_SPI - V2M_MIN_SPI + 1); + + return RT_FALSE; + } + + return RT_TRUE; +} + +static void gicv2m_irq_mask(struct rt_pic_irq *pirq) +{ + rt_pci_msi_mask_irq(pirq); + rt_pic_irq_parent_mask(pirq); +} + +static void gicv2m_irq_unmask(struct rt_pic_irq *pirq) +{ + rt_pci_msi_unmask_irq(pirq); + rt_pic_irq_parent_unmask(pirq); +} + +static void gicv2m_compose_msi_msg(struct rt_pic_irq *pirq, struct rt_pci_msi_msg *msg) +{ + rt_ubase_t addr; + struct gicv2m *v2m = raw_to_gicv2m(pirq->pic); + + addr = gicv2m_get_msi_addr(v2m, pirq->hwirq); + + msg->address_hi = rt_upper_32_bits(addr); + msg->address_lo = rt_lower_32_bits(addr); + + if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) + { + msg->data = 0; + } + else + { + msg->data = pirq->hwirq; + } + + if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET) + { + msg->data -= v2m->spi_offset; + } +} + +static int gicv2m_irq_alloc_msi(struct rt_pic *pic, struct rt_pci_msi_desc *msi_desc) +{ + rt_ubase_t level; + int irq, parent_irq, hwirq, hwirq_index; + struct rt_pic_irq *pirq; + struct gicv2m *v2m = raw_to_gicv2m(pic); + struct rt_pic *ppic = v2m->gic; + + level = rt_spin_lock_irqsave(&v2m->lock); + hwirq_index = rt_bitmap_next_clear_bit(v2m->vectors, 0, v2m->spis_nr); + + if (hwirq_index >= v2m->spis_nr) + { + irq = -RT_EEMPTY; + goto _out_lock; + } + + hwirq = v2m->spi_start + v2m->spi_offset + hwirq_index; + + parent_irq = ppic->ops->irq_map(ppic, hwirq, RT_IRQ_MODE_EDGE_RISING); + if (parent_irq < 0) + { + irq = parent_irq; + goto _out_lock; + } + + irq = rt_pic_config_irq(pic, hwirq_index, hwirq); + if (irq < 0) + { + goto _out_lock; + } + pirq = rt_pic_find_irq(pic, hwirq_index); + + pirq->mode = RT_IRQ_MODE_EDGE_RISING; + rt_pic_cascade(pirq, parent_irq); + + rt_bitmap_set_bit(v2m->vectors, hwirq_index); + +_out_lock: + rt_spin_unlock_irqrestore(&v2m->lock, level); + + return irq; +} + +static void gicv2m_irq_free_msi(struct rt_pic *pic, int irq) +{ + rt_ubase_t level; + struct rt_pic_irq *pirq; + struct gicv2m *v2m = raw_to_gicv2m(pic); + + pirq = rt_pic_find_pirq(pic, irq); + + if (!pirq) + { + return; + } + + rt_pic_uncascade(pirq); + + level = rt_spin_lock_irqsave(&v2m->lock); + rt_bitmap_clear_bit(v2m->vectors, pirq->hwirq - (v2m->spi_start + v2m->spi_offset)); + rt_spin_unlock_irqrestore(&v2m->lock, level); +} + +static rt_err_t gicv2m_irq_set_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t state) +{ + struct gicv2m *v2m = raw_to_gicv2m(pic); + struct rt_pic *ppic = v2m->gic; + + return ppic->ops->irq_set_state(ppic, hwirq, type, state); +} + +static rt_err_t gicv2m_irq_get_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t *out_state) +{ + struct gicv2m *v2m = raw_to_gicv2m(pic); + struct rt_pic *ppic = v2m->gic; + + return ppic->ops->irq_get_state(ppic, hwirq, type, out_state); +} + +const static struct rt_pic_ops gicv2m_ops = +{ + .name = "GICv2m", + .irq_ack = rt_pic_irq_parent_ack, + .irq_mask = gicv2m_irq_mask, + .irq_unmask = gicv2m_irq_unmask, + .irq_eoi = rt_pic_irq_parent_eoi, + .irq_set_priority = rt_pic_irq_parent_set_priority, + .irq_set_affinity = rt_pic_irq_parent_set_affinity, + .irq_compose_msi_msg = gicv2m_compose_msi_msg, + .irq_alloc_msi = gicv2m_irq_alloc_msi, + .irq_free_msi = gicv2m_irq_free_msi, + .irq_set_state = gicv2m_irq_set_state, + .irq_get_state = gicv2m_irq_get_state, + .flags = RT_PIC_F_IRQ_ROUTING, +}; + +static const struct rt_ofw_node_id gicv2m_ofw_match[] = +{ + { .compatible = "arm,gic-v2m-frame" }, + { /* sentinel */ } +}; + +rt_err_t gicv2m_ofw_probe(struct rt_ofw_node *np, const struct rt_ofw_node_id *id) +{ + rt_err_t err = RT_EOK; + struct rt_ofw_node *v2m_np; + + rt_ofw_foreach_available_child_node(np, v2m_np) + { + struct gicv2m *v2m; + rt_size_t bitmap_size; + rt_uint32_t spi_start = 0, spis_nr = 0; + + if (!rt_ofw_node_match(v2m_np, gicv2m_ofw_match)) + { + continue; + } + + if (!rt_ofw_prop_read_bool(v2m_np, "msi-controller")) + { + continue; + } + + if (!(v2m = rt_malloc(sizeof(*v2m)))) + { + rt_ofw_node_put(v2m_np); + + err = -RT_ENOMEM; + break; + } + + v2m->base = rt_ofw_iomap(v2m_np, 0); + + if (!v2m->base) + { + LOG_E("%s: IO map failed", rt_ofw_node_full_name(v2m_np)); + continue; + } + + v2m->base_phy = rt_kmem_v2p(v2m->base); + v2m->flags = 0; + + if (!rt_ofw_prop_read_u32(v2m_np, "arm,msi-base-spi", &spi_start) && + !rt_ofw_prop_read_u32(v2m_np, "arm,msi-num-spis", &spis_nr)) + { + LOG_I("DT overriding V2M MSI_TYPER (base:%u, num:%u)", spi_start, spis_nr); + } + + if (spi_start && spis_nr) + { + v2m->spi_start = spi_start; + v2m->spis_nr = spis_nr; + } + else + { + rt_uint32_t typer; + + /* Graviton should always have explicit spi_start/spis_nr */ + if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) + { + goto _fail; + } + typer = HWREG32(v2m->base + V2M_MSI_TYPER); + + v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer); + v2m->spis_nr = V2M_MSI_TYPER_NUM_SPI(typer); + } + + if (!is_msi_spi_valid(v2m->spi_start, v2m->spis_nr)) + { + goto _fail; + } + + /* + * APM X-Gene GICv2m implementation has an erratum where + * the MSI data needs to be the offset from the spi_start + * in order to trigger the correct MSI interrupt. This is + * different from the standard GICv2m implementation where + * the MSI data is the absolute value within the range from + * spi_start to (spi_start + num_spis). + * + * Broadcom NS2 GICv2m implementation has an erratum where the MSI data + * is 'spi_number - 32' + * + * Reading that register fails on the Graviton implementation + */ + if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) + { + switch (HWREG32(v2m->base + V2M_MSI_IIDR)) + { + case XGENE_GICV2M_MSI_IIDR: + v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; + v2m->spi_offset = v2m->spi_start; + break; + + case BCM_NS2_GICV2M_MSI_IIDR: + v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; + v2m->spi_offset = 32; + break; + } + } + + bitmap_size = RT_BITMAP_LEN(v2m->spis_nr) * sizeof(bitmap_t); + + if (!(v2m->vectors = rt_calloc(1, bitmap_size))) + { + err = -RT_ENOMEM; + goto _fail; + } + + rt_spin_lock_init(&v2m->lock); + + v2m->parent.priv_data = v2m; + v2m->parent.ops = &gicv2m_ops; + v2m->gic = rt_ofw_data(np); + + rt_pic_linear_irq(&v2m->parent, v2m->spis_nr); + rt_pic_user_extends(&v2m->parent); + + rt_ofw_data(v2m_np) = &v2m->parent; + rt_ofw_node_set_flag(v2m_np, RT_OFW_F_READLY); + + continue; + + _fail: + rt_iounmap(v2m->base); + rt_free(v2m); + + if (err) + { + rt_ofw_node_put(v2m_np); + break; + } + } + + return err; +} diff --git a/components/drivers/pic/pic-gicv3-its.c b/components/drivers/pic/pic-gicv3-its.c new file mode 100755 index 00000000000..f0772d91710 --- /dev/null +++ b/components/drivers/pic/pic-gicv3-its.c @@ -0,0 +1,1584 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-01-30 GuEe-GUI first version + */ + +#include +#include +#include + +#define DBG_TAG "pic.gicv3-its" +#define DBG_LVL DBG_INFO +#include + +#include +#include +#include +#include +#include "pic-gicv3.h" +#include "pic-gic-common.h" + +#define ITS_CMD_QUEUE_SIZE (64 * SIZE_KB) +#define ITS_CMD_QUEUE_ALIGN (64 * SIZE_KB) +#define ITS_CMD_QUEUE_NR (ITS_CMD_QUEUE_SIZE / sizeof(struct its_command)) + +#define ITS_ITT_ALIGN (256 * SIZE_KB) + +#define ITS_LPI_CONFIG_TABLE_ALIGN (64 * SIZE_KB) +#define ITS_LPI_CONFIG_PROP_DEFAULT_PRIO GICD_INT_DEF_PRI +#define ITS_LPI_CONFIG_PROP_SHIFT 2 +#define ITS_LPI_CONFIG_PROP_MASK RT_GENMASK(7, ITS_LPI_CONFIG_PROP_SHIFT) +#define ITS_LPI_PENDING_TABLE_ALIGN (64 * SIZE_KB) + +#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING RT_BIT(0) +#define RDIST_FLAGS_RD_TABLES_PREALLOCATED RT_BIT(1) +#define RDIST_FLAGS_FORCE_NON_SHAREABLE RT_BIT(2) + +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING RT_BIT(0) +#define ITS_FLAGS_WORKAROUND_CAVIUM_22375 RT_BIT(1) +#define ITS_FLAGS_FORCE_NON_SHAREABLE RT_BIT(2) + +#define RD_LOCAL_LPI_ENABLED RT_BIT(0) +#define RD_LOCAL_PENDTABLE_PREALLOCATED RT_BIT(1) +#define RD_LOCAL_MEMRESERVE_DONE RT_BIT(2) + +struct its_command +{ + union + { + rt_le64_t code_raw[4]; + rt_uint64_t code[4]; + }; +}; + +struct its_table +{ + void *base; + rt_uint64_t val; + rt_uint32_t size_bits; + rt_uint32_t page_size; + union + { + struct + { + rt_uint32_t itt_entries; + rt_uint32_t lvl2_bits; + }; + }; +}; + +struct its_collection +{ + rt_uint64_t target_address; + rt_uint16_t id; +}; + +struct gicv3_its; + +struct its_map +{ + rt_list_t list; + struct rt_ref ref; + struct gicv3_its *its; + + int device_id; + int lpi_base; + int cpu_id; + + void *itt; + void *lvl2_dte; +}; + +struct gicv3_its +{ + struct rt_pic parent; + rt_list_t list; + + void *base; + void *base_phy; + + void *cmd_base; + rt_ubase_t cmd_idx; + rt_uint32_t flags; + struct rt_spinlock cmd_lock; + + struct its_table tbls[GITS_BASER_NR_REGS]; + struct its_collection collections[RT_CPUS_NR]; + + struct gicv3 *gic; + struct rt_ofw_node *np; +}; + +#define raw_to_gicv3_its(raw) rt_container_of(raw, struct gicv3_its, parent) + +static rt_size_t lpi_nr; +static rt_uint32_t lpi_id_bits; +static void *lpi_table; +static void *lpi_pending_table; +static rt_bitmap_t *lpis_vectors = RT_NULL; +static struct rt_spinlock lpis_lock = {}, map_lock = {}; +static rt_list_t its_nodes = RT_LIST_OBJECT_INIT(its_nodes); +static rt_list_t map_nodes = RT_LIST_OBJECT_INIT(map_nodes); + +rt_inline rt_uint64_t its_readq(struct gicv3_its *its, int off) +{ + return HWREG32(its->base + off) | + (rt_uint64_t)HWREG32(its->base + off + 4) << 32; +} + +rt_inline void its_writeq(struct gicv3_its *its, int off, rt_uint64_t value) +{ + HWREG32(its->base + off) = (rt_uint32_t)value; + HWREG32(its->base + off + 4) = (rt_uint32_t)(value >> 32); +} + +rt_inline rt_uint32_t its_readl(struct gicv3_its *its, int off) +{ + return HWREG32(its->base + off); +} + +rt_inline void its_writel(struct gicv3_its *its, int off, rt_uint32_t value) +{ + HWREG32(its->base + off) = value; +} + +rt_inline rt_uint32_t its_pirq_event_id(struct gicv3_its *its, struct rt_pic_irq *pirq) +{ + return pirq->hwirq - 8192; +} + +rt_inline rt_uint32_t its_pirq_device_id(struct gicv3_its *its, struct rt_pic_irq *pirq) +{ + struct its_map *map = pirq->msi_desc->priv; + + return map->device_id; +} + +rt_inline rt_size_t its_device_id_bits(struct gicv3_its *its) +{ + return RT_FIELD_GET(GITS_TYPER_DEVBITS, HWREG64(its->base + GITS_TYPER)) + 1; +} + +rt_inline void *lpi_base_config(int index) +{ + return &((rt_uint8_t *)lpi_table)[index - 8192]; +} + +static void its_mask_encode(rt_uint64_t *raw_code, rt_uint64_t val, int h, int l) +{ + rt_uint64_t mask = RT_GENMASK_ULL(h, l); + *raw_code &= ~mask; + *raw_code |= (val << l) & mask; +} + +rt_inline void its_encode_cmd(struct its_command *cmd, rt_uint8_t cmd_nr) +{ + its_mask_encode(&cmd->code[0], cmd_nr, 7, 0); +} + +rt_inline void its_encode_valid(struct its_command *cmd, rt_bool_t valid) +{ + its_mask_encode(&cmd->code[2], !!valid, 63, 63); +} + +rt_inline void its_encode_phys_id(struct its_command *cmd, rt_uint32_t phys_id) +{ + its_mask_encode(&cmd->code[1], phys_id, 63, 32); +} + +rt_inline void its_encode_size(struct its_command *cmd, rt_uint8_t size) +{ + its_mask_encode(&cmd->code[1], size, 4, 0); +} + +rt_inline void its_encode_itt(struct its_command *cmd, rt_uint64_t itt_addr) +{ + its_mask_encode(&cmd->code[2], itt_addr >> 8, 51, 8); +} + +rt_inline void its_encode_target(struct its_command *cmd, rt_uint64_t target_addr) +{ + its_mask_encode(&cmd->code[2], target_addr >> 16, 51, 16); +} + +rt_inline void its_encode_device_id(struct its_command *cmd, rt_uint32_t device_id) +{ + its_mask_encode(&cmd->code[0], device_id, 63, 32); +} + +rt_inline void its_encode_event_id(struct its_command *cmd, rt_uint32_t event_id) +{ + its_mask_encode(&cmd->code[1], event_id, 31, 0); +} + +rt_inline void its_encode_collection(struct its_command *cmd, rt_uint16_t collection_id) +{ + its_mask_encode(&cmd->code[2], collection_id, 15, 0); +} + +static struct its_table *its_baser_type(struct gicv3_its *its, int type) +{ + for (int i = 0; i < RT_ARRAY_SIZE(its->tbls); ++i) + { + if (GITS_BASER_TYPE(its->tbls[i].val) == type) + { + return &its->tbls[i]; + } + } + + return RT_NULL; +} + +static struct its_command *its_cmd_alloc(struct gicv3_its *its) +{ + struct its_command *cmd = RT_NULL; + + for (rt_uint32_t count = 0; count <= 10000; ++count) + { + if ((its->cmd_idx + 1) % ITS_CMD_QUEUE_NR != its_readl(its, GITS_CREADR) / sizeof(*cmd)) + { + struct its_command *cmds = its->cmd_base; + + cmd = &cmds[its->cmd_idx++]; + its->cmd_idx %= ITS_CMD_QUEUE_NR; + + rt_memset(cmd, 0, sizeof(*cmd)); + + break; + } + + rt_hw_us_delay(10); + } + + return cmd; +} + +static rt_err_t its_cmd_submit_raw(struct gicv3_its *its, struct its_command *cmd) +{ + rt_uint64_t cwriter; + rt_bool_t retry = RT_FALSE; + + cwriter = (void *)(cmd + 1) - its->cmd_base; + rt_hw_rmb(); + +#ifdef ARCH_CPU_BIG_ENDIAN + cmd->code_raw[0] = rt_cpu_to_le64(cmd->code[0]); + cmd->code_raw[1] = rt_cpu_to_le64(cmd->code[1]); + cmd->code_raw[2] = rt_cpu_to_le64(cmd->code[2]); + cmd->code_raw[3] = rt_cpu_to_le64(cmd->code[3]); +#endif /* ARCH_CPU_BIG_ENDIAN */ + + /* Make sure the commands written to memory are observable by the ITS */ + if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, cmd, sizeof(*cmd)); + } + else + { + rt_hw_wmb(); + } + + its_writel(its, GITS_CWRITER, cwriter); + + for (rt_uint32_t count = 0; count < 10000; ++count) + { + if (its_readl(its, GITS_CREADR) == cwriter) + { + return RT_EOK; + } + + /* Stalled */ + if (!retry && its_readl(its, GITS_CREADR) & 1) + { + /* Retry */ + its_writel(its, GITS_CWRITER, cwriter); + retry = RT_TRUE; + } + else if (retry) + { + LOG_E("Retry command 0x%02x fail", cmd->code[0] & 0xff); + + return -RT_EIO; + } + + rt_hw_us_delay(10); + } + + return -RT_ETIMEOUT; +} + +static rt_err_t its_cmd_submit_nomap(struct gicv3_its *its, struct its_command *cmd, + int cpu_id, rt_bool_t sync) +{ + rt_err_t err; + struct its_command *hw_cmd; + + rt_hw_spin_lock(&its->cmd_lock.lock); + + if (!(hw_cmd = its_cmd_alloc(its))) + { + err = -RT_EBUSY; + goto _out_lock; + } + + rt_memcpy(hw_cmd, cmd, sizeof(*hw_cmd)); + + if ((err = its_cmd_submit_raw(its, hw_cmd))) + { + goto _out_lock; + } + + if (sync) + { + if (!(hw_cmd = its_cmd_alloc(its))) + { + err = -RT_EBUSY; + goto _out_lock; + } + + its_encode_cmd(hw_cmd, GITS_CMD_SYNC); + its_encode_target(hw_cmd, its->collections[cpu_id].target_address); + + err = its_cmd_submit_raw(its, hw_cmd); + } + +_out_lock: + rt_hw_spin_unlock(&its->cmd_lock.lock); + + return err; +} + +static rt_err_t its_cmd_submit(struct gicv3_its *its, struct its_command *cmd, + struct its_map *map, rt_bool_t sync) +{ + return its_cmd_submit_nomap(its, cmd, map->cpu_id, sync); +} + +static rt_err_t lpi_flush_config(struct gicv3_its *its, rt_uint8_t *conf, + struct rt_pic_irq *pirq) +{ + struct its_command cmd; + struct its_map *map = pirq->msi_desc->priv; + + if (its->gic->redist_flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) + { + /* Clean D-cache under command */ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, conf, sizeof(*conf)); + } + else + { + /* DSB inner shareable, store */ + rt_hw_wmb(); + } + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_INV); + its_encode_device_id(&cmd, its_pirq_device_id(its, pirq)); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + + return its_cmd_submit(its, &cmd, map, RT_FALSE); +} + +rt_inline void *gicr_rd_base_percpu(struct gicv3 *gic) +{ + return gic->redist_regions[rt_hw_cpu_id()].base; +} + +rt_inline void *gicr_rd_base(struct gicv3_its *its) +{ + return its->gic->redist_percpu_base[rt_hw_cpu_id()]; +} + +rt_inline rt_uint64_t *gicr_rd_flags(struct gicv3_its *its) +{ + return &its->gic->redist_percpu_flags[rt_hw_cpu_id()]; +} + +static rt_bool_t gicr_supports_plpis(struct gicv3_its *its) +{ + return !!(HWREG64(gicr_rd_base(its) + GICR_TYPER) & GICR_TYPER_PLPIS); +} + +static rt_err_t redist_disable_lpis(struct gicv3_its *its) +{ + void *gicr = gicr_rd_base(its); + rt_uint64_t timeout = 1000000L, val; + + if (!gicr_supports_plpis(its)) + { + LOG_E("CPU#%d: LPIs not supported", rt_hw_cpu_id()); + return -RT_ENOSYS; + } + + val = HWREG32(gicr + GICR_CTLR); + if (!(val & GICR_CTLR_ENABLE_LPIS)) + { + return RT_EOK; + } + + /* + * If coming via a CPU hotplug event, we don't need to disable + * LPIs before trying to re-enable them. They are already + * configured and all is well in the world. + * + * If running with preallocated tables, there is nothing to do. + */ + if ((*gicr_rd_flags(its) & RD_LOCAL_LPI_ENABLED) || + (its->gic->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED)) + { + return RT_EOK; + } + + /* From that point on, we only try to do some damage control */ + LOG_W("CPU%d: Booted with LPIs enabled, memory probably corrupted", rt_hw_cpu_id()); + + /* Disable LPIs */ + val &= ~GICR_CTLR_ENABLE_LPIS; + HWREG32(gicr + GICR_CTLR) = val; + + /* Make sure any change to GICR_CTLR is observable by the GIC */ + rt_hw_barrier(dsb, sy); + + /* + * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs + * from 1 to 0 before programming GICR_PEND{PROP}BASER registers. + * Error out if we time out waiting for RWP to clear. + */ + while (HWREG32(gicr + GICR_CTLR) & GICR_CTLR_RWP) + { + if (!timeout) + { + LOG_E("CPU#%d: Timeout while disabling LPIs", rt_hw_cpu_id()); + + return -RT_ETIMEOUT; + } + + rt_hw_us_delay(1); + --timeout; + } + + /* + * After it has been written to 1, it is IMPLEMENTATION + * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be + * cleared to 0. Error out if clearing the bit failed. + */ + if (HWREG32(gicr + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) + { + LOG_E("CPU#%d: Failed to disable LPIs", rt_hw_cpu_id()); + + return -RT_EBUSY; + } + + return RT_EOK; +} + +static void gicv3_its_cpu_init_lpis(struct gicv3_its *its) +{ + void *gicr; + rt_ubase_t paddr; + rt_uint64_t val, tmp; + + if (*gicr_rd_flags(its) & RD_LOCAL_LPI_ENABLED) + { + return; + } + + gicr = gicr_rd_base(its); + + val = HWREG32(gicr + GICR_CTLR); + + if ((its->gic->redist_flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) && + (val & GICR_CTLR_ENABLE_LPIS)) + { + *gicr_rd_flags(its) |= RD_LOCAL_PENDTABLE_PREALLOCATED; + + goto _out; + } + + paddr = (rt_ubase_t)rt_kmem_v2p(lpi_pending_table); + + /* Set PROPBASE */ + val = ((rt_ubase_t)rt_kmem_v2p(lpi_table) | + GITS_CBASER_InnerShareable | + GITS_CBASER_RaWaWb | + ((lpi_id_bits - 1) & GICR_PROPBASER_IDBITS_MASK)); + + HWREG64(gicr + GICR_PROPBASER) = val; + tmp = HWREG64(gicr + GICR_PROPBASER); + + if (its->gic->redist_flags & RDIST_FLAGS_FORCE_NON_SHAREABLE) + { + tmp &= ~GICR_PBASER_SHARE_MASK_ALL; + } + + if ((tmp ^ val) & GICR_PBASER_SHARE_MASK_ALL) + { + if (!(tmp & GICR_PBASER_SHARE_MASK_ALL)) + { + /* + * The HW reports non-shareable, + * we must remove the cacheability attributes as well. + */ + val &= ~(GICR_PBASER_SHARE_MASK_ALL | GICR_PBASER_INNER_MASK_ALL); + val |= GICR_PBASER_nC; + HWREG64(gicr + GICR_PROPBASER) = val; + } + + if (!rt_hw_cpu_id()) + { + LOG_I("Using cache flushing for LPI property table"); + } + its->gic->redist_flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; + } + + val = (paddr | GICR_PBASER_InnerShareable | GICR_PBASER_RaWaWb); + + HWREG64(gicr + GICR_PENDBASER) = val; + tmp = HWREG64(gicr + GICR_PENDBASER); + + if (its->gic->redist_flags & RDIST_FLAGS_FORCE_NON_SHAREABLE) + { + tmp &= ~GICR_PBASER_SHARE_MASK_ALL; + } + + if (!(tmp & GICR_PBASER_SHARE_MASK_ALL)) + { + /* + * The HW reports non-shareable, we must remove the + * cacheability attributes as well. + */ + val &= ~(GICR_PBASER_SHARE_MASK_ALL | GICR_PBASER_INNER_MASK_ALL); + val |= GICR_PBASER_nC; + HWREG64(gicr + GICR_PENDBASER) = val; + } + + /* Enable LPIs */ + val = HWREG32(gicr + GICR_CTLR); + val |= GICR_CTLR_ENABLE_LPIS; + HWREG32(gicr + GICR_CTLR) = val; + + rt_hw_barrier(dsb, sy); + +_out: + *gicr_rd_flags(its) |= RD_LOCAL_LPI_ENABLED; +} + +static void gicv3_its_cpu_init_collection(struct gicv3_its *its) +{ + rt_uint64_t target; + int cpu_id = rt_hw_cpu_id(); + struct its_command cmd; + struct its_collection *collection; + + if (HWREG64(its->base + GITS_TYPER) & GITS_TYPER_PTA) + { + target = (rt_uint64_t)rt_kmem_v2p(gicr_rd_base(its)); + } + else + { + /* Linear by GICR processor number */ + target = HWREG64(gicr_rd_base(its) + GICR_TYPER); + target = GICR_TYPER_CPU_NO(target) << 16; + } + + collection = &its->collections[cpu_id]; + collection->target_address = target; + collection->id = cpu_id; + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_MAPC); + its_encode_collection(&cmd, collection->id); + its_encode_target(&cmd, target); + its_encode_valid(&cmd, RT_TRUE); + its_cmd_submit_nomap(its, &cmd, cpu_id, RT_TRUE); + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_INVALL); + its_encode_collection(&cmd, collection->id); + its_cmd_submit_nomap(its, &cmd, cpu_id, RT_TRUE); +} + +static rt_err_t gicv3_its_irq_init(struct rt_pic *pic) +{ + rt_err_t err; + struct gicv3_its *its = raw_to_gicv3_its(pic); + + if ((err = redist_disable_lpis(its))) + { + return err; + } + + gicv3_its_cpu_init_lpis(its); + gicv3_its_cpu_init_collection(its); + + return RT_EOK; +} + +static void gicv3_its_irq_mask(struct rt_pic_irq *pirq) +{ + rt_uint8_t *conf = lpi_base_config(pirq->hwirq); + struct gicv3_its *its = raw_to_gicv3_its(pirq->pic); + + *conf &= ~GITS_LPI_CFG_ENABLED; + lpi_flush_config(its, conf, pirq); + + rt_pci_msi_mask_irq(pirq); +} + +static void gicv3_its_irq_unmask(struct rt_pic_irq *pirq) +{ + rt_uint8_t *conf = lpi_base_config(pirq->hwirq); + struct gicv3_its *its = raw_to_gicv3_its(pirq->pic); + + *conf |= GITS_LPI_CFG_ENABLED; + lpi_flush_config(its, conf, pirq); + + rt_pci_msi_unmask_irq(pirq); +} + +static rt_err_t gicv3_its_irq_set_priority(struct rt_pic_irq *pirq, rt_uint32_t priority) +{ + rt_uint8_t *conf = lpi_base_config(pirq->hwirq); + struct gicv3_its *its = raw_to_gicv3_its(pirq->pic); + + *conf = (priority << ITS_LPI_CONFIG_PROP_SHIFT) | (*conf & (~ITS_LPI_CONFIG_PROP_MASK)); + + return lpi_flush_config(its, conf, pirq); +} + +static rt_err_t gicv3_its_irq_set_affinity(struct rt_pic_irq *pirq, rt_bitmap_t *affinity) +{ + int cpu_id; + rt_err_t err; + struct its_map *map; + struct its_command cmd; + struct its_collection *collection; + struct gicv3_its *its = raw_to_gicv3_its(pirq->pic); + + map = pirq->msi_desc->priv; + cpu_id = rt_bitmap_next_set_bit(affinity, 0, RT_CPUS_NR); + collection = &its->collections[cpu_id]; + + if (collection->target_address == ~0ULL) + { + return -RT_EIO; + } + + if (map->cpu_id == cpu_id) + { + return RT_EOK; + } + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_MOVI); + its_encode_device_id(&cmd, map->device_id); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + its_encode_collection(&cmd, collection->id); + + if (!(err = its_cmd_submit(its, &cmd, map, RT_TRUE))) + { + map->cpu_id = cpu_id; + } + + return err; +} + +static void gicv3_its_irq_compose_msi_msg(struct rt_pic_irq *pirq, struct rt_pci_msi_msg *msg) +{ + rt_ubase_t addr; + struct gicv3_its *its = raw_to_gicv3_its(pirq->pic); + + addr = (rt_ubase_t)its->base_phy + GITS_TRANSLATER; + + msg->address_hi = rt_upper_32_bits(addr); + msg->address_lo = rt_lower_32_bits(addr); + msg->data = its_pirq_event_id(its, pirq); +} + +static int gicv3_its_irq_alloc_msi(struct rt_pic *pic, struct rt_pci_msi_desc *msi_desc) +{ + rt_ubase_t level; + rt_uint32_t device_id = -1; + int irq = -1, hwirq, parent_irq, hwirq_index, lpi_base = 0; + struct its_map *map = RT_NULL, *map_tmp; + struct its_table *tbl; + struct its_command cmd; + struct rt_pic_irq *pirq; + struct rt_pci_device *pdev = msi_desc->pdev; + struct gicv3_its *its = raw_to_gicv3_its(pic); + struct rt_pic *ppic = &its->gic->parent; + + tbl = its_baser_type(its, GITS_BASER_TYPE_DEVICE); + RT_ASSERT(tbl != RT_NULL); + + if (!pdev->parent.ofw_node) + { + device_id = rt_pci_dev_id(pdev); + } + else + { + struct rt_ofw_cell_args args; + + for (int index = 0; ; ++index) + { + rt_err_t err = rt_ofw_parse_phandle_cells(pdev->parent.ofw_node, + "msi-parent", "#msi-cells", index, &args); + + if (err) + { + return (int)err; + } + + if (args.data == its->np) + { + device_id = args.args[0]; + } + + rt_ofw_node_put(args.data); + + if ((rt_int32_t)device_id >= 0) + { + break; + } + } + } + + if (device_id >= (1 << tbl->size_bits)) + { + LOG_E("Device ID = is %x not supported", device_id); + + return -RT_EINVAL; + } + + /* Find old map info */ + level = rt_spin_lock_irqsave(&map_lock); + rt_list_for_each_entry(map_tmp, &map_nodes, list) + { + if (map_tmp->device_id == device_id) + { + map = map_tmp; + lpi_base = map->lpi_base - 8192; + break; + } + } + rt_spin_unlock_irqrestore(&map_lock, level); + + if (!map) + { + rt_size_t itt_size; + + if (!(map = rt_calloc(1, sizeof(*map)))) + { + return -RT_ENOMEM; + } + + itt_size = tbl->itt_entries * (RT_FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, + HWREG64(its->base + GITS_TYPER)) + 1); + itt_size = rt_max_t(rt_size_t, itt_size, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; + + map->itt = rt_malloc_align(itt_size, ITS_ITT_ALIGN); + + if (!map->itt) + { + rt_free(map); + return -RT_ENOMEM; + } + + if (tbl->lvl2_bits) + { + void *lvl2_dte; + rt_uint64_t *entry; + + entry = tbl->base; + entry += device_id / (tbl->page_size / GITS_LVL1_ENTRY_SIZE); + + if (*entry) + { + lvl2_dte = (void *)(*entry - PV_OFFSET); + rt_page_ref_inc(lvl2_dte, tbl->lvl2_bits); + } + else + { + rt_size_t dte_size; + + lvl2_dte = rt_pages_alloc(tbl->lvl2_bits); + + if (!lvl2_dte) + { + rt_free_align(map->itt); + rt_free(map); + return -RT_ENOMEM; + } + + dte_size = rt_page_bits(tbl->lvl2_bits); + rt_memset(lvl2_dte, 0, dte_size); + + if (!(tbl->val & GITS_BASER_SHARE_MASK_ALL)) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, lvl2_dte, dte_size); + } + + *entry = rt_cpu_to_le64((rt_uint64_t)rt_kmem_v2p(lvl2_dte) | GITS_BASER_VALID); + + if (!(tbl->val & GITS_BASER_SHARE_MASK_ALL)) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, entry, sizeof(*entry)); + } + + rt_hw_dsb(); + } + + map->lvl2_dte = lvl2_dte; + } + + rt_memset(map->itt, 0, itt_size); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, map->itt, itt_size); + } + msi_desc->priv = map; + + /* Alloc the LPI base on the first LPI */ + level = rt_spin_lock_irqsave(&lpis_lock); + hwirq_index = rt_bitmap_next_clear_bit(lpis_vectors, lpi_base, lpi_nr); + + if (hwirq_index >= lpi_nr) + { + irq = -RT_EEMPTY; + goto _out_lock; + } + + hwirq = 8192 + hwirq_index; + parent_irq = ppic->ops->irq_map(ppic, hwirq, RT_IRQ_MODE_EDGE_RISING); + if (parent_irq < 0) + { + irq = parent_irq; + goto _out_lock; + } + + irq = rt_pic_config_irq(pic, hwirq_index, hwirq); + if (irq < 0) + { + goto _out_lock; + } + pirq = rt_pic_find_irq(pic, hwirq_index); + + pirq->mode = RT_IRQ_MODE_EDGE_RISING; + rt_pic_cascade(pirq, parent_irq); + + rt_bitmap_set_bit(lpis_vectors, hwirq_index); + +_out_lock: + rt_spin_unlock_irqrestore(&lpis_lock, level); + + if (irq < 0) + { + return irq; + } + + if (map->its) + { + rt_ref_get(&map->ref); + } + else + { + rt_list_init(&map->list); + rt_ref_init(&map->ref); + map->its = its; + map->device_id = device_id; + map->lpi_base = hwirq; + + level = rt_spin_lock_irqsave(&map_lock); + rt_list_insert_before(&map_nodes, &map->list); + rt_spin_unlock_irqrestore(&map_lock, level); + } + + /* Default to CPU#0 */ + map->cpu_id = 0; + RT_IRQ_AFFINITY_SET(pirq->affinity, map->cpu_id); + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_MAPD); + its_encode_device_id(&cmd, device_id); + its_encode_size(&cmd, rt_ilog2(tbl->itt_entries) - 1); + its_encode_itt(&cmd, (rt_uint64_t)rt_kmem_v2p(map->itt)); + its_encode_valid(&cmd, RT_TRUE); + its_cmd_submit(its, &cmd, map, RT_FALSE); + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_MAPTI); + its_encode_device_id(&cmd, device_id); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + its_encode_phys_id(&cmd, hwirq); + its_encode_collection(&cmd, its->collections[map->cpu_id].id); + its_cmd_submit(its, &cmd, map, RT_TRUE); + + return irq; +} + +static void its_map_release(struct rt_ref *r) +{ + rt_ubase_t level; + struct gicv3_its *its; + struct its_table *tbl; + struct its_command cmd; + struct its_map *map = rt_container_of(r, struct its_map, ref); + + its = map->its; + tbl = its_baser_type(its, GITS_BASER_TYPE_DEVICE); + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_MAPD); + its_encode_device_id(&cmd, map->device_id); + its_encode_size(&cmd, rt_ilog2(tbl->itt_entries) - 1); + its_encode_itt(&cmd, (rt_uint64_t)rt_kmem_v2p(map->itt)); + its_encode_valid(&cmd, RT_FALSE); + its_cmd_submit(its, &cmd, map, RT_TRUE); + + level = rt_spin_lock_irqsave(&map_lock); + rt_list_insert_before(&map_nodes, &map->list); + rt_spin_unlock_irqrestore(&map_lock, level); + + if (map->itt) + { + rt_free_align(map->itt); + } + if (map->lvl2_dte) + { + if (rt_page_ref_get(map->lvl2_dte, tbl->lvl2_bits) == 1) + { + rt_uint64_t *entry; + + entry = tbl->base + (map->device_id / (tbl->page_size / GITS_LVL1_ENTRY_SIZE)); + *entry = rt_cpu_to_le64(0); + + if (!(tbl->val & GITS_BASER_SHARE_MASK_ALL)) + { + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, entry, sizeof(*entry)); + } + } + rt_pages_free(map->lvl2_dte, tbl->lvl2_bits); + } + rt_free(map); +} + +static void gicv3_its_irq_free_msi(struct rt_pic *pic, int irq) +{ + rt_ubase_t level; + struct its_map *map; + struct its_command cmd; + struct rt_pic_irq *pirq; + struct gicv3_its *its = raw_to_gicv3_its(pic); + + pirq = rt_pic_find_pirq(pic, irq); + + if (!pirq) + { + return; + } + + map = pirq->msi_desc->priv; + + rt_memset(&cmd, 0, sizeof(cmd)); + its_encode_cmd(&cmd, GITS_CMD_DISCARD); + its_encode_device_id(&cmd, map->device_id); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + its_cmd_submit(its, &cmd, map, RT_TRUE); + + rt_pic_uncascade(pirq); + + level = rt_spin_lock_irqsave(&lpis_lock); + rt_bitmap_clear_bit(lpis_vectors, pirq->hwirq - 8192); + rt_spin_unlock_irqrestore(&lpis_lock, level); + + rt_ref_put(&map->ref, its_map_release); +} + +static rt_err_t gicv3_its_irq_set_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t state) +{ + struct its_map *map; + struct its_command cmd; + struct rt_pic_irq *pirq; + struct gicv3_its *its = raw_to_gicv3_its(pic); + + if (type != RT_IRQ_STATE_PENDING || hwirq > 8192 + lpi_nr) + { + return -RT_ENOSYS; + } + + if (!(pirq = rt_pic_find_irq(pic, hwirq - 8192))) + { + return -RT_ENOSYS; + } + + map = pirq->msi_desc->priv; + rt_memset(&cmd, 0, sizeof(cmd)); + + if (state) + { + its_encode_cmd(&cmd, GITS_CMD_INT); + its_encode_device_id(&cmd, map->device_id); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + } + else + { + its_encode_cmd(&cmd, GITS_CMD_CLEAR); + its_encode_device_id(&cmd, map->device_id); + its_encode_event_id(&cmd, its_pirq_event_id(its, pirq)); + } + + its_cmd_submit(its, &cmd, map, RT_TRUE); + + return RT_EOK; +} + +const static struct rt_pic_ops gicv3_its_ops = +{ + .name = "GICv3-ITS", + .irq_init = gicv3_its_irq_init, + .irq_ack = rt_pic_irq_parent_ack, + .irq_mask = gicv3_its_irq_mask, + .irq_unmask = gicv3_its_irq_unmask, + .irq_eoi = rt_pic_irq_parent_eoi, + .irq_set_priority = gicv3_its_irq_set_priority, + .irq_set_affinity = gicv3_its_irq_set_affinity, + .irq_compose_msi_msg = gicv3_its_irq_compose_msi_msg, + .irq_alloc_msi = gicv3_its_irq_alloc_msi, + .irq_free_msi = gicv3_its_irq_free_msi, + .irq_set_state = gicv3_its_irq_set_state, + .flags = RT_PIC_F_IRQ_ROUTING, +}; + +static rt_ssize_t its_baser_page_size(struct gicv3_its *its, struct its_table *tbl) +{ + rt_size_t page_size = 64 * SIZE_KB; + + while (page_size) + { + rt_uint64_t val, baser_page_size; + rt_off_t baser = GITS_BASERn((int)(tbl - its->tbls)); + + val = its_readq(its, baser); + val &= ~GITS_BASER_PAGE_SIZE_MASK; + + switch (page_size) + { + case 64 * SIZE_KB: + baser_page_size = GITS_BASER_PAGE_SIZE_64K; + break; + case 16 * SIZE_KB: + baser_page_size = GITS_BASER_PAGE_SIZE_16K; + break; + case 4 * SIZE_KB: + default: + baser_page_size = GITS_BASER_PAGE_SIZE_4K; + break; + } + + baser_page_size >>= GITS_BASER_PAGE_SIZE_SHIFT; + + val |= RT_FIELD_PREP(GITS_BASER_PAGE_SIZE_MASK, baser_page_size); + its_writeq(its, baser, val); + tbl->val = its_readq(its, baser); + + if (RT_FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, tbl->val) == baser_page_size) + { + break; + } + + switch (page_size) + { + case 64 * SIZE_KB: + page_size = 16 * SIZE_KB; + break; + case 16 * SIZE_KB: + page_size = 4 * SIZE_KB; + break; + case 4 * SIZE_KB: + default: + return -RT_EINVAL; + } + } + + return page_size; +} + +static rt_err_t its_table_init(struct gicv3_its *its) +{ + int inited = 0; + rt_off_t baser; + rt_bool_t indirect = RT_FALSE; + rt_size_t pages_nr, alloc_size; + rt_uint64_t val, type, entry_size, share, cache; + struct its_table *tbl; + + share = GITS_BASER_InnerShareable; + cache = GITS_BASER_RaWaWb; + + for (int i = 0; i < RT_ARRAY_SIZE(its->tbls); ++i) + { + tbl = &its->tbls[i]; + + val = its_readq(its, GITS_BASERn(i)); + type = GITS_BASER_TYPE(val); + + if (type != GITS_BASER_TYPE_DEVICE && + type != GITS_BASER_TYPE_COLLECTION) + { + continue; + } + + tbl->page_size = its_baser_page_size(its, tbl); + + if (tbl->page_size < 0) + { + continue; + } + + baser = GITS_BASERn((int)(tbl - its->tbls)); + entry_size = GITS_BASER_ENTRY_SIZE(val); + + if (type == GITS_BASER_TYPE_DEVICE) + { + tbl->size_bits = its_device_id_bits(its); + LOG_D("Device Max IDs = %lu", 1UL << tbl->size_bits); + + /* For MSI-X */ + tbl->itt_entries = 2048; + while (MAX_HANDLERS / tbl->itt_entries < (1 << tbl->size_bits) && + tbl->itt_entries > 32) + { + tbl->itt_entries >>= 1; + } + } + + its_writeq(its, baser, tbl->val | GITS_BASER_INDIRECT); + tbl->val = its_readq(its, baser); + + indirect = !!(tbl->val & GITS_BASER_INDIRECT); + if (indirect && type == GITS_BASER_TYPE_DEVICE) + { + /* The size of the level 2 table is equal to ITS page size */ + tbl->lvl2_bits = tbl->size_bits - rt_ilog2(tbl->page_size / (int)entry_size); + + /* Get level 1 entries count */ + alloc_size = (1 << tbl->size_bits) / (tbl->page_size / entry_size); + alloc_size *= GITS_LVL1_ENTRY_SIZE; + } + else + { + alloc_size = (1 << tbl->size_bits) * entry_size; + indirect = RT_FALSE; + } + + tbl->base = rt_malloc_align(alloc_size, tbl->page_size); + pages_nr = alloc_size / tbl->page_size; + + if (!tbl->base) + { + return -RT_ENOMEM; + } + + if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) + { + cache = GITS_BASER_nCnB; + } + + if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) + { + cache = GITS_BASER_nC; + share = 0; + } + + val = ((rt_ubase_t)rt_kmem_v2p(tbl->base) | + (type << GITS_BASER_TYPE_SHIFT) | + ((entry_size - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | + (pages_nr << GITS_BASER_PAGES_SHIFT) | + cache | share | GITS_BASER_VALID); + val |= indirect ? GITS_BASER_INDIRECT : 0; + + switch (tbl->page_size) + { + case 4 * SIZE_KB: + val |= GITS_BASER_PAGE_SIZE_4K; + break; + case 16 * SIZE_KB: + val |= GITS_BASER_PAGE_SIZE_16K; + break; + case 64 * SIZE_KB: + val |= GITS_BASER_PAGE_SIZE_64K; + break; + } + + its_writeq(its, baser, val); + tbl->val = its_readq(its, baser); + + rt_memset(tbl->base, 0, alloc_size); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, tbl->base, alloc_size); + + cache = tbl->val & GITS_BASER_INNER_MASK_ALL; + share = tbl->val & GITS_BASER_SHARE_MASK_ALL; + + ++inited; + } + + return inited == 2 ? RT_EOK : -RT_ENOSYS; +} + +static rt_err_t its_cmd_queue_init(struct gicv3_its *its) +{ + void *cmd_phy_base; + rt_uint64_t baser, tmp; + + its->cmd_base = rt_malloc_align(ITS_CMD_QUEUE_SIZE, ITS_CMD_QUEUE_ALIGN); + + if (!its->cmd_base) + { + return -RT_ENOMEM; + } + + its->cmd_idx = 0; + rt_memset(its->cmd_base, 0, ITS_CMD_QUEUE_SIZE); + + cmd_phy_base = rt_kmem_v2p(its->cmd_base); + + baser = GITS_CBASER_VALID | GITS_CBASER_RaWaWb | GITS_CBASER_InnerShareable | \ + ((rt_uint64_t)cmd_phy_base) | (ITS_CMD_QUEUE_SIZE / (4 * SIZE_KB) - 1); + + its_writeq(its, GITS_CBASER, baser); + tmp = its_readq(its, GITS_CBASER); + + if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) + { + tmp &= ~GITS_CBASER_SHARE_MASK_ALL; + } + + if ((tmp ^ baser) & GITS_CBASER_SHARE_MASK_ALL) + { + if (!(tmp & GITS_CBASER_SHARE_MASK_ALL)) + { + /* The HW reports non-shareable, we must remove the cacheability attributes as well */ + baser &= ~(GITS_CBASER_SHARE_MASK_ALL | GITS_CBASER_INNER_MASK_ALL); + baser |= GITS_CBASER_nC; + + its_writeq(its, GITS_CBASER, baser); + } + + LOG_I("Using cache flushing for CMD queue"); + its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, its->cmd_base, ITS_CMD_QUEUE_SIZE); + } + + /* Get the next command from the start of the buffer */ + its_writeq(its, GITS_CWRITER, 0); + + return RT_EOK; +} + +static rt_err_t its_lpi_table_init(struct gicv3 *gic) +{ + rt_size_t lpi_table_size, lpi_pending_table_size; + rt_uint32_t numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic->gicd_typer); + + if (HWREG32(gicr_rd_base_percpu(gic) + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) + { + gic->redist_flags |= RDIST_FLAGS_RD_TABLES_PREALLOCATED; + gic->redist_flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; + + LOG_I("Using preallocated redistributor tables"); + } + + lpi_id_bits = GICD_TYPER_ID_BITS(gic->gicd_typer); + + if (gic->redist_flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) + { + rt_uint64_t val = HWREG64(gicr_rd_base_percpu(gic) + GICR_PROPBASER); + lpi_id_bits = rt_min_t(rt_uint32_t, lpi_id_bits, (val & GICR_PROPBASER_IDBITS_MASK) + 1); + } + + lpi_nr = rt_min_t(rt_size_t, (1UL << lpi_id_bits) - 8192, gic->lpi_nr); + lpi_id_bits = __rt_clz(lpi_nr + 8192); + + if (numlpis > 2 && numlpis > lpi_nr) + { + lpi_nr = numlpis; + LOG_W("Using hypervisor restricted LPI range [%u]", lpi_nr); + } + + gic->lpi_nr = lpi_nr; + + /* LPI Configuration table entry is 1 byte, Pending table bytes is N / 8. */ + lpi_table_size = RT_GENMASK(lpi_id_bits, 0); + lpi_pending_table_size = lpi_table_size / 8; + + lpi_table = rt_malloc_align(lpi_table_size, ITS_LPI_CONFIG_TABLE_ALIGN); + lpi_pending_table = rt_malloc_align(lpi_pending_table_size, ITS_LPI_PENDING_TABLE_ALIGN); + lpis_vectors = rt_calloc(1, RT_BITMAP_LEN(lpi_nr) * sizeof(rt_bitmap_t)); + + if (!lpi_table || !lpi_pending_table || !lpis_vectors) + { + if (lpi_table) + { + rt_free_align(lpi_table); + } + if (lpi_pending_table) + { + rt_free_align(lpi_pending_table); + } + if (lpis_vectors) + { + rt_free_align(lpis_vectors); + } + + lpi_table = RT_NULL; + lpi_pending_table = RT_NULL; + lpis_vectors = RT_NULL; + + return -RT_ENOMEM; + } + + /* Set the default configuration */ + rt_memset(lpi_table, ITS_LPI_CONFIG_PROP_DEFAULT_PRIO | GITS_LPI_CFG_GROUP1, lpi_table_size); + /* + * We should make a full mask size with lpi_id_bits, + * otherwise 'undefined' LPI will occur. + */ + rt_memset(lpi_pending_table, 0, lpi_pending_table_size); + + /* Flush the table to memory */ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, lpi_table, lpi_table_size); + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, lpi_pending_table, lpi_pending_table_size); + + LOG_D("ITS: Allocator initialized for %u LPIs", lpi_nr); + + return RT_EOK; +} + +static void its_init_fail(struct gicv3_its *its) +{ + if (its->base) + { + rt_iounmap(its->base); + } + + if (its->cmd_base) + { + rt_free_align(its->cmd_base); + } + + for (int i = 0; i < RT_ARRAY_SIZE(its->tbls); ++i) + { + struct its_table *tbl = &its->tbls[i]; + + if (tbl->base) + { + rt_free_align(tbl->base); + } + } + + rt_list_remove(&its->list); + rt_free(its); +} + +static rt_err_t its_quirk_cavium_22375(void *data) +{ + struct gicv3_its *its = data; + + its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; + + return RT_EOK; +} + +static rt_err_t its_enable_rockchip(void *data) +{ + struct gicv3_its *its = data; + struct gicv3 *gic = its->gic; + + if (!rt_ofw_machine_is_compatible("rockchip,rk3566") && + !rt_ofw_machine_is_compatible("rockchip,rk3567") && + !rt_ofw_machine_is_compatible("rockchip,rk3568") && + !rt_ofw_machine_is_compatible("rockchip,rk3588") && + !rt_ofw_machine_is_compatible("rockchip,rk3588s")) + { + return -RT_EINVAL; + } + + its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; + gic->redist_flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; + + return RT_EOK; +} + +static rt_err_t its_set_non_coherent(void *data) +{ + struct gicv3_its *its = data; + + if (!rt_ofw_prop_read_bool(its->np, "dma-noncoherent")) + { + return -RT_EINVAL; + } + + its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; + + return RT_EOK; +} + +static const struct gic_quirk _its_quirks[] = +{ + { + .desc = "ITS: Cavium ThunderX errata: 22375, 24313", + .iidr = 0xa100034c, + .iidr_mask = 0xffff0fff, + .init = its_quirk_cavium_22375, + }, + { + .desc = "ITS: Rockchip erratum RK3566 ~ RK3588", + .iidr = 0x0201743b, + .iidr_mask = 0xffffffff, + .init = its_enable_rockchip, + }, + { + .desc = "ITS: non-coherent attribute", + .compatible = "arm,gic-v3-its", + .init = its_set_non_coherent, + }, + { /* sentinel */ } +}; + +static const struct rt_ofw_node_id gicv3_its_ofw_match[] = +{ + { .compatible = "arm,gic-v3-its" }, + { /* sentinel */ } +}; + +rt_err_t gicv3_its_ofw_probe(struct rt_ofw_node *np, const struct rt_ofw_node_id *id) +{ + rt_err_t err = -RT_EEMPTY; + struct rt_ofw_node *its_np; + struct gicv3_its *its, *its_next; + + rt_ofw_foreach_available_child_node(np, its_np) + { + if (!rt_ofw_node_match(its_np, gicv3_its_ofw_match)) + { + continue; + } + + if (!rt_ofw_prop_read_bool(its_np, "msi-controller")) + { + continue; + } + + if (!(its = rt_calloc(1, sizeof(struct gicv3_its)))) + { + rt_ofw_node_put(its_np); + + err = -RT_ENOMEM; + goto _free_all; + } + + its->base = rt_ofw_iomap(its_np, 0); + + if (!its->base) + { + LOG_E("%s: IO map failed", rt_ofw_node_full_name(its_np)); + its_init_fail(its); + continue; + } + + /* + * Make sure ALL the ITS are reset before we probe any, + * as they may be sharing memory + */ + for (int i = 0; i < GITS_BASER_NR_REGS; ++i) + { + its_writeq(its, GITS_BASER + (i << 3), 0); + } + + its->np = its_np; + rt_list_init(&its->list); + rt_list_insert_before(&its_nodes, &its->list); + } + + if (!rt_list_isempty(&its_nodes)) + { + if ((err = its_lpi_table_init(rt_ofw_data(np)))) + { + goto _free_all; + } + } + + rt_list_for_each_entry_safe(its, its_next, &its_nodes, list) + { + rt_uint32_t ctlr; + + its->base_phy = rt_kmem_v2p(its->base); + its->gic = rt_ofw_data(np); + + gic_common_init_quirk_hw(HWREG32(its->base + GITS_IIDR), _its_quirks, its); + gic_common_init_quirk_ofw(its->np, _its_quirks, its); + + if ((err = its_cmd_queue_init(its))) + { + goto _fail; + } + rt_spin_lock_init(&its->cmd_lock); + + if ((err = its_table_init(its))) + { + goto _fail; + } + + for (int i = 0; i < RT_CPUS_NR; ++i) + { + its->collections[i].target_address = ~0ULL; + } + + ctlr = its_readl(its, GITS_CTLR); + ctlr |= GITS_CTLR_ENABLE; + its_writel(its, GITS_CTLR, ctlr); + + its->parent.priv_data = its; + its->parent.ops = &gicv3_its_ops; + + rt_pic_linear_irq(&its->parent, its->gic->lpi_nr); + rt_pic_user_extends(&its->parent); + + its_np = its->np; + rt_ofw_data(its_np) = &its->parent; + rt_ofw_node_set_flag(its_np, RT_OFW_F_READLY); + + continue; + + _fail: + its_init_fail(its); + + if (err == -RT_ENOMEM) + { + break; + } + } + + if (rt_list_isempty(&its_nodes) && lpis_vectors) + { + rt_free(lpis_vectors); + rt_free_align(lpi_table); + rt_free_align(lpi_pending_table); + lpis_vectors = RT_NULL; + } + + return err; + +_free_all: + rt_list_for_each_entry_safe(its, its_next, &its_nodes, list) + { + rt_free(its); + rt_list_remove(&its->list); + } + + return err; +} diff --git a/components/drivers/pic/pic-gicv3.c b/components/drivers/pic/pic-gicv3.c index c5e4bc780b8..cb8e0388e47 100644 --- a/components/drivers/pic/pic-gicv3.c +++ b/components/drivers/pic/pic-gicv3.c @@ -266,20 +266,25 @@ static void gicv3_dist_init(void) HWREG64(base + GICD_IROUTERnE + i * 8) = affinity; } - if (GICD_TYPER_NUM_LPIS(_gic.gicd_typer)) + if (GICD_TYPER_NUM_LPIS(_gic.gicd_typer) > 1) { /* Max LPI = 8192 + Math.pow(2, num_LPIs + 1) - 1 */ - rt_size_t num_lpis = (1 << (GICD_TYPER_NUM_LPIS(_gic.gicd_typer) + 1)) + 1; + rt_size_t num_lpis = 1UL << (GICD_TYPER_NUM_LPIS(_gic.gicd_typer) + 1); - _gic.lpi_nr = rt_min_t(int, num_lpis, 1 << GICD_TYPER_ID_BITS(_gic.gicd_typer)); + _gic.lpi_nr = rt_min_t(int, num_lpis, 1UL << GICD_TYPER_ID_BITS(_gic.gicd_typer)); } else { - _gic.lpi_nr = 1 << GICD_TYPER_ID_BITS(_gic.gicd_typer); + _gic.lpi_nr = 1UL << GICD_TYPER_ID_BITS(_gic.gicd_typer); } /* SPI + eSPI + LPIs */ - _gic.irq_nr = _gic.line_nr - 32 + _gic.espi_nr + _gic.lpi_nr; + _gic.irq_nr = _gic.line_nr - 32 + _gic.espi_nr; +#ifdef RT_PIC_ARM_GIC_V3_ITS + /* ITS will allocate the same number of lpi PIRQs */ + _gic.lpi_nr = rt_min_t(rt_size_t, RT_PIC_ARM_GIC_V3_ITS_IRQ_MAX, _gic.lpi_nr); + _gic.irq_nr += _gic.lpi_nr; +#endif } static void gicv3_redist_enable(rt_bool_t enable) @@ -389,6 +394,8 @@ static void gicv3_cpu_init(void) int cpu_id = rt_hw_cpu_id(); #ifdef ARCH_SUPPORT_HYP _gicv3_eoi_mode_ns = RT_TRUE; +#else + _gicv3_eoi_mode_ns = !!rt_ofw_bootargs_select("pic.gicv3_eoimode", 0); #endif base = gicv3_percpu_redist_sgi_base(); @@ -700,6 +707,7 @@ static int gicv3_irq_map(struct rt_pic *pic, int hwirq, rt_uint32_t mode) if (pirq && hwirq >= GIC_SGI_NR) { pirq->mode = mode; + pirq->priority = GICD_INT_DEF_PRI; switch (gicv3_hwirq_type(hwirq)) { @@ -708,7 +716,6 @@ static int gicv3_irq_map(struct rt_pic *pic, int hwirq, rt_uint32_t mode) break; case SPI_TYPE: case ESPI_TYPE: - pirq->priority = GICD_INT_DEF_PRI; RT_IRQ_AFFINITY_SET(pirq->affinity, _init_cpu_id); default: break; @@ -823,7 +830,18 @@ static rt_bool_t gicv3_handler(void *data) } else { - pirq = rt_pic_find_irq(&gic->parent, hwirq - GIC_SGI_NR); + int irq_index; + + if (hwirq < 8192) + { + irq_index = hwirq - GIC_SGI_NR; + } + else + { + irq_index = gic->irq_nr - gic->lpi_nr + hwirq - 8192; + } + + pirq = rt_pic_find_irq(&gic->parent, irq_index); } gicv3_irq_ack(pirq); diff --git a/components/drivers/pic/pic-gicv3.h b/components/drivers/pic/pic-gicv3.h index 6046d9b4318..dcd64d65824 100644 --- a/components/drivers/pic/pic-gicv3.h +++ b/components/drivers/pic/pic-gicv3.h @@ -12,8 +12,8 @@ * 2023-02-01 GuEe-GUI move macros to header */ -#ifndef __IRQ_GICV3_H__ -#define __IRQ_GICV3_H__ +#ifndef __PIC_GICV3_H__ +#define __PIC_GICV3_H__ #include @@ -101,6 +101,8 @@ #define GICR_CTLR_IR (1UL << 2) #define GICR_CTLR_RWP (1UL << 3) +#define GICR_TYPER_CPU_NO(r) (((r) >> 8) & 0xffff) + #define GICR_RD_BASE_SIZE (64 * SIZE_KB) #define GICR_SGI_OFFSET (64 * SIZE_KB) #define GICR_SGI_BASE_SIZE GICR_SGI_OFFSET @@ -152,66 +154,142 @@ #define GITS_CTLR 0x0000 #define GITS_IIDR 0x0004 #define GITS_TYPER 0x0008 -#define GITS_MPAMIDR 0x0010 -#define GITS_PARTIDR 0x0014 #define GITS_MPIDR 0x0018 -#define GITS_STATUSR 0x0040 -#define GITS_UMSIR 0x0048 -#define GITS_CBASER 0x0048 +#define GITS_CBASER 0x0080 #define GITS_CWRITER 0x0088 #define GITS_CREADR 0x0090 -#define GITS_BASER 0x0100 /* 0x0100~0x0138 */ +#define GITS_BASER 0x0100 +#define GITS_IDREGS_BASE 0xffd0 +#define GITS_PIDR0 0xffe0 +#define GITS_PIDR1 0xffe4 +#define GITS_PIDR2 GICR_PIDR2 +#define GITS_PIDR4 0xffd0 +#define GITS_CIDR0 0xfff0 +#define GITS_CIDR1 0xfff4 +#define GITS_CIDR2 0xfff8 +#define GITS_CIDR3 0xfffc + +#define GITS_TRANSLATER 0x10040 + +#define GITS_SGIR 0x20020 + +#define GITS_SGIR_VPEID RT_GENMASK_ULL(47, 32) +#define GITS_SGIR_VINTID RT_GENMASK_ULL(3, 0) + +#define GITS_CTLR_ENABLE (1U << 0) +#define GITS_CTLR_ImDe (1U << 1) +#define GITS_CTLR_ITS_NUMBER_SHIFT 4 +#define GITS_CTLR_ITS_NUMBER (0xFU << GITS_CTLR_ITS_NUMBER_SHIFT) +#define GITS_CTLR_QUIESCENT (1U << 31) + +#define GITS_TYPER_PLPIS (1UL << 0) +#define GITS_TYPER_VLPIS (1UL << 1) +#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4 +#define GITS_TYPER_ITT_ENTRY_SIZE RT_GENMASK_ULL(7, 4) +#define GITS_TYPER_IDBITS_SHIFT 8 +#define GITS_TYPER_DEVBITS_SHIFT 13 +#define GITS_TYPER_DEVBITS RT_GENMASK_ULL(17, 13) +#define GITS_TYPER_PTA (1UL << 19) +#define GITS_TYPER_HCC_SHIFT 24 +#define GITS_TYPER_HCC(r) (((r) >> GITS_TYPER_HCC_SHIFT) & 0xff) +#define GITS_TYPER_VMOVP (1ULL << 37) +#define GITS_TYPER_VMAPP (1ULL << 40) +#define GITS_TYPER_SVPET RT_GENMASK_ULL(42, 41) /* * ITS commands */ -#define GITS_CMD_MAPD 0x08 -#define GITS_CMD_MAPC 0x09 -#define GITS_CMD_MAPTI 0x0a -#define GITS_CMD_MAPI 0x0b -#define GITS_CMD_MOVI 0x01 -#define GITS_CMD_DISCARD 0x0f -#define GITS_CMD_INV 0x0c -#define GITS_CMD_MOVALL 0x0e -#define GITS_CMD_INVALL 0x0d -#define GITS_CMD_INT 0x03 -#define GITS_CMD_CLEAR 0x04 -#define GITS_CMD_SYNC 0x05 +#define GITS_CMD_MAPD 0x08 +#define GITS_CMD_MAPC 0x09 +#define GITS_CMD_MAPTI 0x0a +#define GITS_CMD_MAPI 0x0b +#define GITS_CMD_MOVI 0x01 +#define GITS_CMD_DISCARD 0x0f +#define GITS_CMD_INV 0x0c +#define GITS_CMD_MOVALL 0x0e +#define GITS_CMD_INVALL 0x0d +#define GITS_CMD_INT 0x03 +#define GITS_CMD_CLEAR 0x04 +#define GITS_CMD_SYNC 0x05 /* ITS Config Area */ -#define GITS_LPI_CFG_GROUP1 (1 << 1) -#define GITS_LPI_CFG_ENABLED (1 << 0) +#define GITS_LPI_CFG_GROUP1 (1 << 1) +#define GITS_LPI_CFG_ENABLED (1 << 0) /* ITS Command Queue Descriptor */ +#define GITS_BASER_SHAREABILITY_SHIFT 10 +#define GITS_BASER_INNER_CACHEABILITY_SHIFT 59 +#define GITS_BASER_OUTER_CACHEABILITY_SHIFT 53 #define GITS_CBASER_VALID (1UL << 63) -#define GITS_CBASER_SHAREABILITY_SHIFT (10) -#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59) -#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT (53) - -#define GITS_TRANSLATION_TABLE_DESCRIPTORS_NR 8 +#define GITS_CBASER_SHAREABILITY_SHIFT 10 +#define GITS_CBASER_INNER_CACHEABILITY_SHIFT 59 +#define GITS_CBASER_OUTER_CACHEABILITY_SHIFT 53 +#define GICR_PBASER_SHAREABILITY_SHIFT 10 +#define GICR_PBASER_INNER_CACHEABILITY_SHIFT 7 +#define GICR_PBASER_OUTER_CACHEABILITY_SHIFT 56 + +#define GITS_BASER_NR_REGS 8 +#define GITS_BASERn(idx) (GITS_BASER + sizeof(rt_uint64_t) * idx) + +#define GITS_BASER_VALID (1ULL << 63) +#define GITS_BASER_INDIRECT (1ULL << 62) +#define GITS_BASER_TYPE_SHIFT 56 +#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7) +#define GITS_BASER_ENTRY_SIZE_SHIFT 48 +#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1) +#define GITS_BASER_PAGE_SIZE_SHIFT 8 +#define GITS_BASER_PAGE_SIZE_4K (0ULL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_16K (1ULL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_64K (2ULL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGE_SIZE_MASK (3ULL << GITS_BASER_PAGE_SIZE_SHIFT) +#define GITS_BASER_PAGES_SHIFT 0 + +#define GITS_LVL1_ENTRY_SIZE 8UL + +#define GITS_BASER_TYPE_NONE 0 +#define GITS_BASER_TYPE_DEVICE 1 +#define GITS_BASER_TYPE_VPE 2 +#define GITS_BASER_TYPE_RESERVED3 3 +#define GITS_BASER_TYPE_COLLECTION 4 +#define GITS_BASER_TYPE_RESERVED5 5 +#define GITS_BASER_TYPE_RESERVED6 6 +#define GITS_BASER_TYPE_RESERVED7 7 #define GITS_BASER_CACHEABILITY(reg, inner_outer, type) \ - (GITS_CBASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) + (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT) #define GITS_BASER_SHAREABILITY(reg, type) \ - (GITS_CBASER_##type << reg##_SHAREABILITY_SHIFT) - -#define GITS_CBASER_CACHE_DnGnRnE 0x0UL /* Device-nGnRnE. */ -#define GITS_CBASER_CACHE_NIN 0x1UL /* Normal Inner Non-cacheable. */ -#define GITS_CBASER_CACHE_NIRAWT 0x2UL /* Normal Inner Cacheable Read-allocate, Write-through. */ -#define GITS_CBASER_CACHE_NIRAWB 0x3UL /* Normal Inner Cacheable Read-allocate, Write-back. */ -#define GITS_CBASER_CACHE_NIWAWT 0x4UL /* Normal Inner Cacheable Write-allocate, Write-through. */ -#define GITS_CBASER_CACHE_NIWAWB 0x5UL /* Normal Inner Cacheable Write-allocate, Write-back. */ -#define GITS_CBASER_CACHE_NIRAWAWT 0x6UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. */ -#define GITS_CBASER_CACHE_NIRAWAWB 0x7UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. */ -#define GITS_CBASER_CACHE_MASK 0x7UL -#define GITS_CBASER_SHARE_NS 0x0UL /* Non-shareable. */ -#define GITS_CBASER_SHARE_IS 0x1UL /* Inner Shareable. */ -#define GITS_CBASER_SHARE_OS 0x2UL /* Outer Shareable. */ -#define GITS_CBASER_SHARE_RES 0x3UL /* Reserved. Treated as 0b00 */ -#define GITS_CBASER_SHARE_MASK 0x3UL + (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT) + +#define GIC_BASER_CACHE_DnGnRnE 0x0UL /* Device-nGnRnE. */ +#define GIC_BASER_CACHE_NIN 0x1UL /* Normal Inner Non-cacheable. */ +#define GIC_BASER_CACHE_NIRAWT 0x2UL /* Normal Inner Cacheable Read-allocate, Write-through. */ +#define GIC_BASER_CACHE_NIRAWB 0x3UL /* Normal Inner Cacheable Read-allocate, Write-back. */ +#define GIC_BASER_CACHE_NIWAWT 0x4UL /* Normal Inner Cacheable Write-allocate, Write-through. */ +#define GIC_BASER_CACHE_NIWAWB 0x5UL /* Normal Inner Cacheable Write-allocate, Write-back. */ +#define GIC_BASER_CACHE_NIRAWAWT 0x6UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-through. */ +#define GIC_BASER_CACHE_NIRAWAWB 0x7UL /* Normal Inner Cacheable Read-allocate, Write-allocate, Write-back. */ +#define GIC_BASER_CACHE_MASK 0x7UL +#define GIC_BASER_SHARE_NS 0x0UL /* Non-shareable. */ +#define GIC_BASER_SHARE_IS 0x1UL /* Inner Shareable. */ +#define GIC_BASER_SHARE_OS 0x2UL /* Outer Shareable. */ +#define GIC_BASER_SHARE_RES 0x3UL /* Reserved. Treated as 0b00 */ +#define GIC_BASER_SHARE_MASK 0x3UL + +#define GITS_BASER_InnerShareable GITS_BASER_SHAREABILITY(GITS_BASER, SHARE_IS) +#define GITS_BASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GITS_BASER, SHARE_MASK) +#define GITS_BASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GITS_BASER, INNER, MASK) +#define GITS_BASER_nCnB GITS_BASER_CACHEABILITY(GITS_BASER, INNER, DnGnRnE) +#define GITS_BASER_nC GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIN) +#define GITS_BASER_RaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWT) +#define GITS_BASER_RaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWB) +#define GITS_BASER_WaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIWAWT) +#define GITS_BASER_WaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIWAWB) +#define GITS_BASER_RaWaWt GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWAWT) +#define GITS_BASER_RaWaWb GITS_BASER_CACHEABILITY(GITS_BASER, INNER, NIRAWAWB) #define GITS_CBASER_InnerShareable GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_IS) #define GITS_CBASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GITS_CBASER, SHARE_MASK) +#define GITS_CBASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, MASK) #define GITS_CBASER_nCnB GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, DnGnRnE) #define GITS_CBASER_nC GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIN) #define GITS_CBASER_RaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWT) @@ -221,6 +299,18 @@ #define GITS_CBASER_RaWaWt GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWT) #define GITS_CBASER_RaWaWb GITS_BASER_CACHEABILITY(GITS_CBASER, INNER, NIRAWAWB) +#define GICR_PBASER_InnerShareable GITS_BASER_SHAREABILITY(GICR_PBASER, SHARE_IS) +#define GICR_PBASER_SHARE_MASK_ALL GITS_BASER_SHAREABILITY(GICR_PBASER, SHARE_MASK) +#define GICR_PBASER_INNER_MASK_ALL GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, MASK) +#define GICR_PBASER_nCnB GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, DnGnRnE) +#define GICR_PBASER_nC GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIN) +#define GICR_PBASER_RaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWT) +#define GICR_PBASER_RaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWB) +#define GICR_PBASER_WaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIWAWT) +#define GICR_PBASER_WaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIWAWB) +#define GICR_PBASER_RaWaWt GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWAWT) +#define GICR_PBASER_RaWaWb GITS_BASER_CACHEABILITY(GICR_PBASER, INNER, NIRAWAWB) + #define GIC_EPPI_BASE_INTID 1056 #define GIC_ESPI_BASE_INTID 4096 @@ -283,6 +373,7 @@ struct gicv3 rt_size_t dist_size; void *redist_percpu_base[RT_CPUS_NR]; + rt_uint64_t redist_percpu_flags[RT_CPUS_NR]; rt_size_t percpu_ppi_nr[RT_CPUS_NR]; struct @@ -296,4 +387,4 @@ struct gicv3 rt_size_t redist_regions_nr; }; -#endif /* __IRQ_GICV3_H__ */ +#endif /* __PIC_GICV3_H__ */ diff --git a/components/drivers/pic/pic.c b/components/drivers/pic/pic.c index 4525c7d49eb..9f8f6f3cf74 100644 --- a/components/drivers/pic/pic.c +++ b/components/drivers/pic/pic.c @@ -173,19 +173,52 @@ rt_err_t rt_pic_linear_irq(struct rt_pic *pic, rt_size_t irq_nr) return err; } +rt_err_t rt_pic_cancel_irq(struct rt_pic *pic) +{ + rt_err_t err = RT_EOK; + + if (pic && pic->pirqs) + { + rt_ubase_t level = rt_spin_lock_irqsave(&_pic_lock); + + /* + * This is only to make system runtime safely, + * we don't recommend PICs to unregister. + */ + rt_list_remove(&pic->list); + + rt_spin_unlock_irqrestore(&_pic_lock, level); + } + else + { + err = -RT_EINVAL; + } + + return err; +} + static void config_pirq(struct rt_pic *pic, struct rt_pic_irq *pirq, int irq, int hwirq) { rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock); + if (pirq->irq < 0) + { + rt_list_init(&pirq->list); + rt_list_init(&pirq->children_nodes); + rt_list_init(&pirq->isr.list); + } + else if (pirq->pic != pic) + { + RT_ASSERT(rt_list_isempty(&pirq->list) == RT_TRUE); + RT_ASSERT(rt_list_isempty(&pirq->children_nodes) == RT_TRUE); + RT_ASSERT(rt_list_isempty(&pirq->isr.list) == RT_TRUE); + } + pirq->irq = irq; pirq->hwirq = hwirq; pirq->pic = pic; - rt_list_init(&pirq->list); - rt_list_init(&pirq->children_nodes); - rt_list_init(&pirq->isr.list); - rt_spin_unlock_irqrestore(&pirq->rw_lock, level); } @@ -494,6 +527,8 @@ rt_err_t rt_pic_do_traps(void) rt_err_t err = -RT_ERROR; struct irq_traps *traps; + rt_interrupt_enter(); + rt_list_for_each_entry(traps, &_traps_nodes, list) { if (traps->handler(traps->data)) @@ -504,6 +539,8 @@ rt_err_t rt_pic_do_traps(void) } } + rt_interrupt_leave(); + return err; } @@ -535,11 +572,17 @@ rt_err_t rt_pic_handle_isr(struct rt_pic_irq *pirq) rt_list_for_each_entry(child, &pirq->children_nodes, list) { - rt_pic_irq_ack(child->irq); + if (child->pic->ops->irq_ack) + { + child->pic->ops->irq_ack(child); + } err = rt_pic_handle_isr(child); - rt_pic_irq_eoi(child->irq); + if (child->pic->ops->irq_eoi) + { + child->pic->ops->irq_eoi(child); + } } } diff --git a/components/drivers/smp/SConscript b/components/drivers/smp/SConscript new file mode 100644 index 00000000000..2f4fe0b8ec4 --- /dev/null +++ b/components/drivers/smp/SConscript @@ -0,0 +1,10 @@ +from building import * + +cwd = GetCurrentDir() +src = [] +if GetDepend("RT_USING_SMP"): + src += Glob('*.c') +CPPPATH = [cwd] +group = DefineGroup('smp', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/components/drivers/smp/smp.c b/components/drivers/smp/smp.c new file mode 100644 index 00000000000..aa0071c576a --- /dev/null +++ b/components/drivers/smp/smp.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2006-2024 RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/9/12 zhujiale the first version + */ + +#include "smp.h" + +#define DBG_TAG "SMP" +#define DBG_LVL DBG_INFO +#include + +static struct rt_smp_call rt_smp_work[RT_CPUS_NR]; +static rt_atomic_t rt_smp_wait; + +static rt_err_t smp_call_handler(struct rt_smp_event *event) +{ + switch (event->event_id) + { + case SMP_CALL_EVENT_FUNC: + event->func(event->data); + rt_atomic_add(&rt_smp_wait, 1); + break; + default: + LOG_E("error event id\n"); + return -RT_ERROR; + } + return RT_EOK; +} +void rt_smp_call_ipi_handler(int vector, void *param) +{ + int err; + int cur_cpu = rt_hw_cpu_id(); + rt_spin_lock(&rt_smp_work[cur_cpu].lock); + + if (rt_smp_work[cur_cpu].event.event_id) + { + err = smp_call_handler(&rt_smp_work[cur_cpu].event); + if (err) + { + LOG_E("Have no event\n"); + rt_memset(&rt_smp_work[cur_cpu].event, 0, sizeof(struct rt_smp_event)); + rt_spin_unlock(&rt_smp_work[cur_cpu].lock); + } + rt_memset(&rt_smp_work[cur_cpu].event, 0, sizeof(struct rt_smp_event)); + } + rt_spin_unlock(&rt_smp_work[cur_cpu].lock); +} + +/** + * @brief call function on specified CPU , + * + * @param cpu_mask cpu mask for call + * @param func the function pointer + * @param data the data pointer + * @param flag call flag if you set SMP_CALL_WAIT_ALL + * then it will wait all cpu call finish and return + * else it will call function on specified CPU and return immediately + * @param cond the condition function pointer,if you set it then it will call function only when cond return true + */ +void rt_smp_call_func_cond(int cpu_mask, rt_smp_call_func_back func, void *data, rt_uint8_t flag, rt_smp_cond cond) +{ + RT_DEBUG_NOT_IN_INTERRUPT; + struct rt_smp_event event; + rt_bool_t need_call = RT_TRUE, need_wait = RT_FALSE; + int cur_cpu = rt_hw_cpu_id(); + int cpuid = 1 << cur_cpu; + int tmp_id = 0, cpu_nr = 0; + int tmp_mask; + int irq_flag; + + if (flag == SMP_CALL_WAIT_ALL) + { + need_wait = RT_TRUE; + rt_atomic_store(&rt_smp_wait, 0); + } + + if (cpuid & cpu_mask) + { + func(data); + cpu_mask = cpu_mask & (~cpuid); + } + + if (!cpu_mask) + need_call = RT_FALSE; + + tmp_mask = cpu_mask; + if (need_call) + { + while (tmp_mask) + { + if ((tmp_mask & 1) && (tmp_id < RT_CPUS_NR)) + { + if (cond && !cond(tmp_id, data)) + continue; + cpu_nr++; + event.event_id = SMP_CALL_EVENT_FUNC; + event.func = func; + event.data = data; + event.cpu_mask = cpu_mask; + irq_flag = rt_spin_lock_irqsave(&rt_smp_work[tmp_id].lock); + rt_smp_work[tmp_id].event = event; + rt_spin_unlock_irqrestore(&rt_smp_work[tmp_id].lock,irq_flag); + } + tmp_id++; + tmp_mask = tmp_mask >> 1; + } + rt_hw_ipi_send(RT_FUNC_IPI, cpu_mask); + } + + if (need_wait) + { + while (rt_atomic_load(&rt_smp_wait) != cpu_nr); + } +} + +void rt_smp_call_each_cpu(rt_smp_call_func_back func, void *data, rt_uint8_t flag) +{ + rt_smp_call_func_cond(RT_ALL_CPU, func, data, flag, RT_NULL); +} + +void rt_smp_call_each_cpu_cond(rt_smp_call_func_back func, void *data, rt_uint8_t flag, rt_smp_cond cond_func) +{ + rt_smp_call_func_cond(RT_ALL_CPU, func, data, flag, cond_func); +} +void rt_smp_call_any_cpu(int cpu_mask, rt_smp_call_func_back func, void *data, rt_uint8_t flag) +{ + rt_smp_call_func_cond(cpu_mask, func, data, flag, RT_NULL); +} + +void rt_smp_call_any_cpu_cond(int cpu_mask, rt_smp_call_func_back func, void *data, rt_uint8_t flag, rt_smp_cond cond_func) +{ + rt_smp_call_func_cond(cpu_mask, func, data, flag, cond_func); +} + +void rt_smp_init(void) +{ + for (int i = 0; i < RT_CPUS_NR; i++) + { + rt_memset(&rt_smp_work[i], 0, sizeof(struct rt_smp_call)); + rt_spin_lock_init(&rt_smp_work[i].lock); + } +} diff --git a/components/drivers/smp/smp.h b/components/drivers/smp/smp.h new file mode 100644 index 00000000000..6932fd1a7f8 --- /dev/null +++ b/components/drivers/smp/smp.h @@ -0,0 +1,34 @@ +#ifndef __SMP_IPI_H__ +#define __SMP_IPI_H__ +#include +typedef void (*rt_smp_call_func_back)(void *data); +typedef rt_bool_t (*rt_smp_cond)(int cpu, void *info); + +#define SMP_CALL_EVENT_FUNC 0x1 + +#define SMP_CALL_WAIT_ALL (1 << 0) +#define SMP_CALL_NO_WAIT (1 << 1) + +#define RT_ALL_CPU ((1 << RT_CPUS_NR) - 1) +struct rt_smp_event +{ + int cpu_mask; + int event_id; + void *data; + rt_smp_call_func_back func; +}; +struct rt_smp_call +{ + struct rt_spinlock lock; + struct rt_smp_event event; +}; + + +void rt_smp_call_ipi_handler(int vector, void *param); +void rt_smp_call_each_cpu(rt_smp_call_func_back func, void *data, rt_uint8_t flag); +void rt_smp_call_each_cpu_cond(rt_smp_call_func_back func, void *data, rt_uint8_t flag, rt_smp_cond cond_func); +void rt_smp_call_any_cpu(int cpu_mask, rt_smp_call_func_back func, void *data, rt_uint8_t flag); +void rt_smp_call_any_cpu_cond(int cpu_mask, rt_smp_call_func_back func, void *data, rt_uint8_t flag, rt_smp_cond cond_func); +void rt_smp_init(void); + +#endif diff --git a/components/finsh/finsh.h b/components/finsh/finsh.h index 9fe36fae5a2..530ab9baae7 100644 --- a/components/finsh/finsh.h +++ b/components/finsh/finsh.h @@ -130,13 +130,13 @@ typedef long (*syscall_func)(void); #define FINSH_FUNCTION_EXPORT_ALIAS(name, alias, desc) /** - * @ingroup msh + * @ingroup finsh * * This macro exports a command to module shell. * - * @param command is the name of the command. - * @param desc is the description of the command, which will show in help list. - * @param opt This is an option, enter any content to enable option completion + * param command is the name of the command. + * param desc is the description of the command, which will show in help list. + * param opt This is an option, enter any content to enable option completion */ /* MSH_CMD_EXPORT(command, desc) or MSH_CMD_EXPORT(command, desc, opt) */ #define MSH_CMD_EXPORT(...) \ @@ -144,17 +144,18 @@ typedef long (*syscall_func)(void); _MSH_FUNCTION_CMD2)(__VA_ARGS__) /** - * @ingroup msh + * @ingroup finsh * * This macro exports a command with alias to module shell. * - * @param command is the name of the command. - * @param alias is the alias of the command. - * @param desc is the description of the command, which will show in help list. - * @param opt This is an option, enter any content to enable option completion - * @note + * param command is the name of the command. + * param alias is the alias of the command. + * param desc is the description of the command, which will show in help list. + * param opt This is an option, enter any content to enable option completion + * @code * #define MSH_CMD_EXPORT_ALIAS(command, alias, desc) or * #define MSH_CMD_EXPORT_ALIAS(command, alias, desc, opt) + * @endcode */ #define MSH_CMD_EXPORT_ALIAS(...) \ __MSH_GET_EXPORT_MACRO(__VA_ARGS__, _MSH_FUNCTION_EXPORT_CMD3_OPT, \ diff --git a/components/finsh/msh.c b/components/finsh/msh.c index 9cc0c6b3406..d8586e54a42 100644 --- a/components/finsh/msh.c +++ b/components/finsh/msh.c @@ -755,10 +755,10 @@ void msh_auto_complete_path(char *path) } else if (S_ISLNK(buffer.st_mode)) { - DIR *dir = opendir(path); - if (dir) + DIR *link_dir = opendir(path); + if (link_dir) { - closedir(dir); + closedir(link_dir); strcat(path, "/"); } } diff --git a/components/lwp/Kconfig b/components/lwp/Kconfig index d88a0b6a9d5..f815c7da998 100644 --- a/components/lwp/Kconfig +++ b/components/lwp/Kconfig @@ -29,10 +29,6 @@ if RT_USING_LWP int "The maximum number of channel messages" default 1024 - config LWP_CONSOLE_INPUT_BUFFER_SIZE - int "The input buffer size of lwp console device" - default 1024 - config LWP_TID_MAX_NR int "The maximum number of lwp thread id" default 64 diff --git a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S index 571f422a745..9c4b7ebe626 100644 --- a/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S +++ b/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -105,6 +106,7 @@ arch_get_user_sp: .global arch_clone_exit arch_fork_exit: arch_clone_exit: + mov x0, xzr b arch_syscall_exit /* @@ -131,12 +133,31 @@ START_POINT(SVC_Handler) /* x0 is initial sp */ mov sp, x0 + bl _SVC_Handler + + /* jump explictly, make this code position independant */ + b arch_syscall_exit +START_POINT_END(SVC_Handler) + +TRACE_SYMBOL(_SVC_Handler) +#define FRAME_REG x19 + +/** + * x0 -> frame_addr + */ +_SVC_Handler: + .local _SVC_Handler + + stp fp, lr, [sp, -16]! + mov fp, sp + + mov FRAME_REG, x0 /* save the value of frame address */ msr daifclr, #3 /* enable interrupt */ GET_THREAD_SELF x0 bl lwp_user_setting_save - ldp x8, x9, [sp, #(CONTEXT_OFFSET_X8)] + ldp x8, x9, [FRAME_REG, #(CONTEXT_OFFSET_X8)] and x0, x8, #0xf000 cmp x0, #0xe000 beq arch_signal_quit @@ -149,78 +170,46 @@ START_POINT(SVC_Handler) cmp x0, xzr mov x30, x0 beq arch_syscall_exit - ldp x0, x1, [sp, #(CONTEXT_OFFSET_X0)] - ldp x2, x3, [sp, #(CONTEXT_OFFSET_X2)] - ldp x4, x5, [sp, #(CONTEXT_OFFSET_X4)] - ldp x6, x7, [sp, #(CONTEXT_OFFSET_X6)] + ldp x0, x1, [FRAME_REG, #(CONTEXT_OFFSET_X0)] + ldp x2, x3, [FRAME_REG, #(CONTEXT_OFFSET_X2)] + ldp x4, x5, [FRAME_REG, #(CONTEXT_OFFSET_X4)] + ldp x6, x7, [FRAME_REG, #(CONTEXT_OFFSET_X6)] blr x30 - /* jump explictly, make this code position independant */ - b arch_syscall_exit -START_POINT_END(SVC_Handler) -.global arch_syscall_exit + ldp fp, lr, [sp], 16 + ret + +/** + * void arch_syscall_exit(long rc) + */ arch_syscall_exit: + .global arch_syscall_exit /** - * @brief back up former x0 which is required to restart syscall, then setup + * backup former x0 which is required to restart syscall, then setup * syscall return value in stack frame */ mov x1, sp bl arch_syscall_prepare_signal + /** + * disable local irq so we don't messup with the spsr_el1 witch is not saved + * for kernel space IRQ/EXCEPTION + */ msr daifset, #3 - ldp x2, x3, [sp], #0x10 /* SPSR and ELR. */ - msr spsr_el1, x3 - msr elr_el1, x2 - - ldp x29, x30, [sp], #0x10 - msr sp_el0, x29 - ldp x28, x29, [sp], #0x10 - msr fpcr, x28 - msr fpsr, x29 - ldp x28, x29, [sp], #0x10 - ldp x26, x27, [sp], #0x10 - ldp x24, x25, [sp], #0x10 - ldp x22, x23, [sp], #0x10 - ldp x20, x21, [sp], #0x10 - ldp x18, x19, [sp], #0x10 - ldp x16, x17, [sp], #0x10 - ldp x14, x15, [sp], #0x10 - ldp x12, x13, [sp], #0x10 - ldp x10, x11, [sp], #0x10 - ldp x8, x9, [sp], #0x10 - ldp x6, x7, [sp], #0x10 - ldp x4, x5, [sp], #0x10 - ldp x2, x3, [sp], #0x10 - ldp x0, x1, [sp], #0x10 - RESTORE_FPU sp + b arch_ret_to_user /* the sp is reset to the outer most level, irq and fiq are disabled */ START_POINT(arch_ret_to_user) msr daifset, #3 - /* save exception frame */ - SAVE_FPU sp - stp x0, x1, [sp, #-0x10]! - stp x2, x3, [sp, #-0x10]! - stp x4, x5, [sp, #-0x10]! - stp x6, x7, [sp, #-0x10]! - stp x8, x9, [sp, #-0x10]! - stp x10, x11, [sp, #-0x10]! - stp x12, x13, [sp, #-0x10]! - stp x14, x15, [sp, #-0x10]! - stp x16, x17, [sp, #-0x10]! - stp x18, x19, [sp, #-0x10]! - stp x20, x21, [sp, #-0x10]! - stp x22, x23, [sp, #-0x10]! - stp x24, x25, [sp, #-0x10]! - stp x26, x27, [sp, #-0x10]! - stp x28, x29, [sp, #-0x10]! - - mrs x0, fpcr - mrs x1, fpsr - stp x0, x1, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! + + ldr x2, [sp, #CONTEXT_OFFSET_SP_EL0] + msr sp_el0, x2 + ldr x2, [sp, #CONTEXT_OFFSET_ELR_EL1] + msr elr_el1, x2 + ldr x3, [sp, #CONTEXT_OFFSET_SPSR_EL1] + msr spsr_el1, x3 /* pre-action */ bl lwp_check_debug @@ -231,7 +220,8 @@ START_POINT(arch_ret_to_user) msr daifclr, #3 mov x0, xzr b sys_exit -1: + +1: /* handling dbg */ /* check if dbg ops exist */ ldr x0, =rt_dbg_ops ldr x0, [x0] @@ -243,104 +233,42 @@ START_POINT(arch_ret_to_user) orr x2, x2, x1 msr spsr_el1, x2 b 3f -2: +2: /* clear software step */ bic x2, x2, x1 msr spsr_el1, x2 -3: +3: /* handling signal */ /** - * push 2 dummy words to simulate a exception frame of interrupt - * Note: in kernel state, the context switch dont saved the context + * push updated spsr & elr to exception frame. + * Note: these 2 maybe updated after handling dbg */ mrs x0, spsr_el1 + str x0, [sp, #CONTEXT_OFFSET_SPSR_EL1] mrs x1, elr_el1 - stp x1, x0, [sp, #-0x10]! + str x1, [sp, #CONTEXT_OFFSET_ELR_EL1] mov x0, sp + + /* restore the thread execution environment */ msr daifclr, #3 bl lwp_thread_signal_catch + + /* restore the exception-return exec-flow */ msr daifset, #3 - ldp x1, x0, [sp], #0x10 - msr spsr_el1, x0 - msr elr_el1, x1 /* check debug */ - /* restore exception frame */ - ldp x29, x30, [sp], #0x10 - ldp x0, x1, [sp], #0x10 - msr fpcr, x0 - msr fpsr, x1 - - ldp x28, x29, [sp], #0x10 - ldp x26, x27, [sp], #0x10 - ldp x24, x25, [sp], #0x10 - ldp x22, x23, [sp], #0x10 - ldp x20, x21, [sp], #0x10 - ldp x18, x19, [sp], #0x10 - ldp x16, x17, [sp], #0x10 - ldp x14, x15, [sp], #0x10 - ldp x12, x13, [sp], #0x10 - ldp x10, x11, [sp], #0x10 - ldp x8, x9, [sp], #0x10 - ldp x6, x7, [sp], #0x10 - ldp x4, x5, [sp], #0x10 - ldp x2, x3, [sp], #0x10 - ldp x0, x1, [sp], #0x10 - RESTORE_FPU sp - stp x0, x1, [sp, #-0x10]! ldr x0, =rt_dbg_ops ldr x0, [x0] cmp x0, xzr - ldp x0, x1, [sp], #0x10 - beq 1f - /* save */ - SAVE_FPU sp - stp x0, x1, [sp, #-0x10]! - stp x2, x3, [sp, #-0x10]! - stp x4, x5, [sp, #-0x10]! - stp x6, x7, [sp, #-0x10]! - stp x8, x9, [sp, #-0x10]! - stp x10, x11, [sp, #-0x10]! - stp x12, x13, [sp, #-0x10]! - stp x14, x15, [sp, #-0x10]! - stp x16, x17, [sp, #-0x10]! - stp x18, x19, [sp, #-0x10]! - stp x20, x21, [sp, #-0x10]! - stp x22, x23, [sp, #-0x10]! - stp x24, x25, [sp, #-0x10]! - stp x26, x27, [sp, #-0x10]! - stp x28, x29, [sp, #-0x10]! - mrs x0, fpcr - mrs x1, fpsr - stp x0, x1, [sp, #-0x10]! - stp x29, x30, [sp, #-0x10]! + beq 1f - mrs x0, elr_el1 + ldr x0, [sp, #CONTEXT_OFFSET_ELR_EL1] bl dbg_attach_req - /* restore */ - ldp x29, x30, [sp], #0x10 - ldp x0, x1, [sp], #0x10 - msr fpcr, x0 - msr fpsr, x1 - ldp x28, x29, [sp], #0x10 - ldp x26, x27, [sp], #0x10 - ldp x24, x25, [sp], #0x10 - ldp x22, x23, [sp], #0x10 - ldp x20, x21, [sp], #0x10 - ldp x18, x19, [sp], #0x10 - ldp x16, x17, [sp], #0x10 - ldp x14, x15, [sp], #0x10 - ldp x12, x13, [sp], #0x10 - ldp x10, x11, [sp], #0x10 - ldp x8, x9, [sp], #0x10 - ldp x6, x7, [sp], #0x10 - ldp x4, x5, [sp], #0x10 - ldp x2, x3, [sp], #0x10 - ldp x0, x1, [sp], #0x10 - RESTORE_FPU sp 1: + RESTORE_IRQ_CONTEXT_NO_SPEL0 + eret START_POINT_END(arch_ret_to_user) @@ -410,32 +338,7 @@ arch_syscall_restart: /* restore previous exception frame */ msr spsel, #0 - ldp x2, x3, [sp], #0x10 - msr elr_el1, x2 - msr spsr_el1, x3 - - ldp x29, x30, [sp], #0x10 - - ldp x28, x29, [sp], #0x10 - msr fpcr, x28 - msr fpsr, x29 - - ldp x28, x29, [sp], #0x10 - ldp x26, x27, [sp], #0x10 - ldp x24, x25, [sp], #0x10 - ldp x22, x23, [sp], #0x10 - ldp x20, x21, [sp], #0x10 - ldp x18, x19, [sp], #0x10 - ldp x16, x17, [sp], #0x10 - ldp x14, x15, [sp], #0x10 - ldp x12, x13, [sp], #0x10 - ldp x10, x11, [sp], #0x10 - ldp x8, x9, [sp], #0x10 - ldp x6, x7, [sp], #0x10 - ldp x4, x5, [sp], #0x10 - ldp x2, x3, [sp], #0x10 - ldp x0, x1, [sp], #0x10 - RESTORE_FPU sp + RESTORE_IRQ_CONTEXT_NO_SPEL0 msr spsel, #1 @@ -443,8 +346,8 @@ arch_syscall_restart: arch_signal_quit: - /* drop current exception frame */ - add sp, sp, #CONTEXT_SIZE + /* drop current exception frame & sigreturn */ + add sp, sp, #(CONTEXT_SIZE + 0x10) mov x1, sp mrs x0, sp_el0 bl arch_signal_ucontext_restore @@ -460,35 +363,12 @@ arch_signal_quit: /* restore previous exception frame */ msr spsel, #0 - ldp x2, x3, [sp], #0x10 - msr elr_el1, x2 - msr spsr_el1, x3 - - ldp x29, x30, [sp], #0x10 - - ldp x28, x29, [sp], #0x10 - msr fpcr, x28 - msr fpsr, x29 - - ldp x28, x29, [sp], #0x10 - ldp x26, x27, [sp], #0x10 - ldp x24, x25, [sp], #0x10 - ldp x22, x23, [sp], #0x10 - ldp x20, x21, [sp], #0x10 - ldp x18, x19, [sp], #0x10 - ldp x16, x17, [sp], #0x10 - ldp x14, x15, [sp], #0x10 - ldp x12, x13, [sp], #0x10 - ldp x10, x11, [sp], #0x10 - ldp x8, x9, [sp], #0x10 - ldp x6, x7, [sp], #0x10 - ldp x4, x5, [sp], #0x10 - ldp x2, x3, [sp], #0x10 - ldp x0, x1, [sp], #0x10 - RESTORE_FPU sp + RESTORE_IRQ_CONTEXT_NO_SPEL0 msr spsel, #1 + SAVE_IRQ_CONTEXT + b arch_ret_to_user /** diff --git a/components/lwp/terminal/tty_ptmx.c b/components/lwp/terminal/tty_ptmx.c index 8daebc099aa..371c27a26b0 100644 --- a/components/lwp/terminal/tty_ptmx.c +++ b/components/lwp/terminal/tty_ptmx.c @@ -27,7 +27,6 @@ static int ptm_fops_open(struct dfs_file *file) rt_uint32_t oflags = file->flags; rt_thread_t cur_thr = rt_thread_self(); - /* we don't check refcnt because each open will create a new device */ if (file->vnode && file->vnode->data) { /** @@ -62,16 +61,9 @@ static int ptm_fops_close(struct dfs_file *file) if (file->data) { - if (file->vnode->ref_count != 1) - { - rc = 0; - } - else - { - device = (rt_device_t)file->data; - tp = rt_container_of(device, struct lwp_tty, parent); - rc = bsd_ptsdev_methods.fo_close(tp, rt_thread_self()); - } + device = (rt_device_t)file->data; + tp = rt_container_of(device, struct lwp_tty, parent); + rc = bsd_ptsdev_methods.fo_close(tp, rt_thread_self()); } else { diff --git a/components/net/netdev/include/netdev.h b/components/net/netdev/include/netdev.h index 5dc68bf216f..cafa73d4c29 100644 --- a/components/net/netdev/include/netdev.h +++ b/components/net/netdev/include/netdev.h @@ -111,8 +111,6 @@ struct netdev extern struct netdev *netdev_list; /* The default network interface device */ extern struct netdev *netdev_default; -/* The local virtual network device */ -extern struct netdev *netdev_lo; /* The network interface device ping response object */ struct netdev_ping_resp { diff --git a/components/net/netdev/src/netdev.c b/components/net/netdev/src/netdev.c index 8d21db756c0..2f4cea5120e 100644 --- a/components/net/netdev/src/netdev.c +++ b/components/net/netdev/src/netdev.c @@ -35,8 +35,6 @@ struct netdev *netdev_list = RT_NULL; /* The default network interface device */ struct netdev *netdev_default = RT_NULL; -/* The local virtual network device */ -struct netdev *netdev_lo = RT_NULL; /* The global network register callback */ static netdev_callback_fn g_netdev_register_callback = RT_NULL; static netdev_callback_fn g_netdev_default_change_callback = RT_NULL; diff --git a/components/net/sal/src/sal_socket.c b/components/net/sal/src/sal_socket.c index 1317c5c1bdd..6cd2caeea39 100644 --- a/components/net/sal/src/sal_socket.c +++ b/components/net/sal/src/sal_socket.c @@ -444,11 +444,6 @@ static int socket_init(int family, int type, int protocol, struct sal_socket **r struct netdev *netdev = RT_NULL; rt_bool_t flag = RT_FALSE; - if (family == AF_UNIX) - { - netdv_def = netdev_lo; - } - if (family < 0 || family > AF_MAX) { return -1; @@ -684,7 +679,8 @@ int sal_bind(int socket, const struct sockaddr *name, socklen_t namelen) addr_un = (struct sockaddr_un *)name; - if ((addr_un->sa_family != AF_UNIX) && (addr_un->sa_family != AF_NETLINK)) +#define IS_INET_ADDR_FAMILY(_af) ((_af) == AF_INET) || ((_af) == AF_INET6) + if (IS_INET_ADDR_FAMILY(name->sa_family)) { /* bind network interface by ip address */ sal_sockaddr_to_ipaddr(name, &input_ipaddr); @@ -1171,12 +1167,9 @@ int sal_ioctlsocket(int socket, long cmd, void *arg) /* get the socket object by socket descriptor */ SAL_SOCKET_OBJ_GET(sock, socket); - /* check the network interface socket opreation */ - SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, ioctlsocket); - struct sal_ifreq *ifr = (struct sal_ifreq *)arg; - if((sock->domain == AF_INET)&&(sock->netdev)&&(ifr != RT_NULL)) + if (ifr != RT_NULL) { switch (cmd) { @@ -1478,6 +1471,10 @@ int sal_ioctlsocket(int socket, long cmd, void *arg) break; } } + + /* check the network interface socket opreation */ + SAL_NETDEV_SOCKETOPS_VALID(sock->netdev, pf, ioctlsocket); + return pf->skt_ops->ioctlsocket((int)(size_t)sock->user_data, cmd, arg); } diff --git a/documentation/doxygen/Doxyfile b/documentation/doxygen/Doxyfile index 412d93d0dc9..44a09c85d10 100644 --- a/documentation/doxygen/Doxyfile +++ b/documentation/doxygen/Doxyfile @@ -868,6 +868,7 @@ INPUT = ../../src \ ../../include \ . \ ../../components/finsh \ + ../../components/drivers/include/drivers \ ../../components/dfs/dfs_v2/src \ ../../components/dfs/dfs_v2/include diff --git a/examples/utest/testcases/Kconfig b/examples/utest/testcases/Kconfig index cc13e4e70ee..890c2b234bc 100644 --- a/examples/utest/testcases/Kconfig +++ b/examples/utest/testcases/Kconfig @@ -15,6 +15,7 @@ rsource "drivers/ipc/Kconfig" rsource "posix/Kconfig" rsource "mm/Kconfig" rsource "tmpfs/Kconfig" +rsource "smp_ipi/Kconfig" endif endmenu diff --git a/examples/utest/testcases/smp_ipi/Kconfig b/examples/utest/testcases/smp_ipi/Kconfig new file mode 100644 index 00000000000..2e144c5b60a --- /dev/null +++ b/examples/utest/testcases/smp_ipi/Kconfig @@ -0,0 +1,6 @@ +menu "SMP Testcase" + +config UTEST_SMP_CALL_FUNC + bool "Call random cpu to run func" + default n +endmenu diff --git a/examples/utest/testcases/smp_ipi/SConscript b/examples/utest/testcases/smp_ipi/SConscript new file mode 100644 index 00000000000..b3570fd0404 --- /dev/null +++ b/examples/utest/testcases/smp_ipi/SConscript @@ -0,0 +1,13 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = [] +CPPPATH = [cwd] + +if GetDepend(['RT_USING_SMP','UTEST_SMP_CALL_FUNC']): + src += ['smp.c'] + +group = DefineGroup('utestcases', src, depend = ['RT_USING_UTESTCASES'], CPPPATH = CPPPATH) + +Return('group') diff --git a/examples/utest/testcases/smp_ipi/smp.c b/examples/utest/testcases/smp_ipi/smp.c new file mode 100644 index 00000000000..e7bbcbe199a --- /dev/null +++ b/examples/utest/testcases/smp_ipi/smp.c @@ -0,0 +1,75 @@ +#include +#include "utest.h" +#include "utest_assert.h" +#include "smp.h" +static int pass_count = 0; +static int pass = 1000; +static struct rt_spinlock lock; + +static void test_call(void *data) +{ + rt_spin_lock(&lock); + int *i = (int *)data; + int id = rt_hw_cpu_id(); + *i &= ~(1 << id); + if (*i == 0) + pass_count++; + rt_spin_unlock(&lock); +} + + +static void test1() +{ + int cpu_mask = 0xf; + for (int i = 0; i < 1000; i++) + { + cpu_mask = rand() % 0xf; + if (cpu_mask == 0) + pass--; + rt_smp_call_any_cpu(cpu_mask,test_call, &cpu_mask, SMP_CALL_WAIT_ALL); + if (i % 20 == 0) + rt_kprintf("#"); + } + rt_kprintf("\n"); + uassert_true(pass_count == pass); +} + +static void test_call2(void *data) +{ + rt_spin_lock(&lock); + int a = 100000; + while (a--); + int *i = (int *)data; + (*i)++; + rt_spin_unlock(&lock); +} +static void test2(void) +{ + int data = 0; + rt_smp_call_each_cpu(test_call2, &data, SMP_CALL_WAIT_ALL); + uassert_true(data == RT_CPUS_NR); + rt_thread_mdelay(10); + data = 0; + rt_smp_call_each_cpu(test_call2, &data, SMP_CALL_NO_WAIT); + uassert_true(data != RT_CPUS_NR); +} + +static rt_err_t utest_tc_init(void) +{ + pass_count = 0; + pass = 1000; + rt_spin_lock_init(&lock); + return RT_EOK; +} + +static rt_err_t utest_tc_cleanup(void) +{ + return RT_EOK; +} +static void testcase(void) +{ + UTEST_UNIT_RUN(test1); + UTEST_UNIT_RUN(test2); +} + +UTEST_TC_EXPORT(testcase, "testcase.smp.smp", utest_tc_init, utest_tc_cleanup, 10); diff --git a/include/klibc/kerrno.h b/include/klibc/kerrno.h new file mode 100644 index 00000000000..2f7699923f6 --- /dev/null +++ b/include/klibc/kerrno.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-09-22 Meco Man the first version + */ + +#ifndef __RT_KERRNO_H__ +#define __RT_KERRNO_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_LIBC) && !defined(RT_USING_NANO) +/* POSIX error code compatible */ +#define RT_EOK 0 /**< There is no error */ +#define RT_ERROR 255 /**< A generic/unknown error happens */ +#define RT_ETIMEOUT ETIMEDOUT /**< Timed out */ +#define RT_EFULL ENOSPC /**< The resource is full */ +#define RT_EEMPTY ENODATA /**< The resource is empty */ +#define RT_ENOMEM ENOMEM /**< No memory */ +#define RT_ENOSYS ENOSYS /**< Function not implemented */ +#define RT_EBUSY EBUSY /**< Busy */ +#define RT_EIO EIO /**< IO error */ +#define RT_EINTR EINTR /**< Interrupted system call */ +#define RT_EINVAL EINVAL /**< Invalid argument */ +#define RT_ENOENT ENOENT /**< No entry */ +#define RT_ENOSPC ENOSPC /**< No space left */ +#define RT_EPERM EPERM /**< Operation not permitted */ +#define RT_EFAULT EFAULT /**< Bad address */ +#define RT_ENOBUFS ENOBUFS /**< No buffer space is available */ +#define RT_ESCHEDISR 253 /**< scheduler failure in isr context */ +#define RT_ESCHEDLOCKED 252 /**< scheduler failure in critical region */ +#define RT_ETRAP 254 /**< Trap event */ +#else +#define RT_EOK 0 /**< There is no error */ +#define RT_ERROR 1 /**< A generic/unknown error happens */ +#define RT_ETIMEOUT 2 /**< Timed out */ +#define RT_EFULL 3 /**< The resource is full */ +#define RT_EEMPTY 4 /**< The resource is empty */ +#define RT_ENOMEM 5 /**< No memory */ +#define RT_ENOSYS 6 /**< Function not implemented */ +#define RT_EBUSY 7 /**< Busy */ +#define RT_EIO 8 /**< IO error */ +#define RT_EINTR 9 /**< Interrupted system call */ +#define RT_EINVAL 10 /**< Invalid argument */ +#define RT_ENOENT 11 /**< No entry */ +#define RT_ENOSPC 12 /**< No space left */ +#define RT_EPERM 13 /**< Operation not permitted */ +#define RT_ETRAP 14 /**< Trap event */ +#define RT_EFAULT 15 /**< Bad address */ +#define RT_ENOBUFS 16 /**< No buffer space is available */ +#define RT_ESCHEDISR 17 /**< scheduler failure in isr context */ +#define RT_ESCHEDLOCKED 18 /**< scheduler failure in critical region */ +#endif /* defined(RT_USING_LIBC) && !defined(RT_USING_NANO) */ + +rt_err_t rt_get_errno(void); +void rt_set_errno(rt_err_t no); +int *_rt_errno(void); +const char *rt_strerror(rt_err_t error); +#if !defined(RT_USING_NEWLIBC) && !defined(_WIN32) +#ifndef errno +#define errno *_rt_errno() +#endif +#endif /* !defined(RT_USING_NEWLIBC) && !defined(_WIN32) */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/klibc/kstdio.h b/include/klibc/kstdio.h new file mode 100644 index 00000000000..215e9a9245a --- /dev/null +++ b/include/klibc/kstdio.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-09-22 Meco Man the first version + */ + +#ifndef __RT_KSTDIO_H__ +#define __RT_KSTDIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +int rt_vsprintf(char *dest, const char *format, va_list arg_ptr); +int rt_vsnprintf(char *buf, rt_size_t size, const char *fmt, va_list args); +int rt_sprintf(char *buf, const char *format, ...); +int rt_snprintf(char *buf, rt_size_t size, const char *format, ...); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/klibc/kstring.h b/include/klibc/kstring.h new file mode 100644 index 00000000000..48fbe600914 --- /dev/null +++ b/include/klibc/kstring.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-09-22 Meco Man the first version + */ + +#ifndef __RT_KSTRING_H__ +#define __RT_KSTRING_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +void *rt_memset(void *src, int c, rt_ubase_t n); +void *rt_memcpy(void *dest, const void *src, rt_ubase_t n); +void *rt_memmove(void *dest, const void *src, rt_size_t n); +rt_int32_t rt_memcmp(const void *cs, const void *ct, rt_size_t count); +char *rt_strdup(const char *s); +rt_size_t rt_strnlen(const char *s, rt_ubase_t maxlen); +char *rt_strstr(const char *str1, const char *str2); +rt_int32_t rt_strcasecmp(const char *a, const char *b); +char *rt_strcpy(char *dst, const char *src); +char *rt_strncpy(char *dest, const char *src, rt_size_t n); +rt_int32_t rt_strncmp(const char *cs, const char *ct, rt_size_t count); +rt_int32_t rt_strcmp(const char *cs, const char *ct); +rt_size_t rt_strlen(const char *src); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/include/rtdef.h b/include/rtdef.h index 6985bb8f51a..34bb283ae71 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -68,6 +68,8 @@ #include "rtsched.h" #include "rttypes.h" +#include "klibc/kerrno.h" + #ifdef __cplusplus extern "C" { #endif @@ -84,12 +86,11 @@ extern "C" { #define RT_VERSION_PATCH 0 /**< Patch version number (x.x.X) */ /* e.g. #if (RTTHREAD_VERSION >= RT_VERSION_CHECK(4, 1, 0) */ -#define RT_VERSION_CHECK(major, minor, revise) ((major * 10000) + (minor * 100) + revise) +#define RT_VERSION_CHECK(major, minor, revise) ((major * 10000U) + (minor * 100U) + revise) /* RT-Thread version */ #define RTTHREAD_VERSION RT_VERSION_CHECK(RT_VERSION_MAJOR, RT_VERSION_MINOR, RT_VERSION_PATCH) - /**@}*/ /* maximum value of base type */ @@ -99,10 +100,10 @@ extern "C" { #define RT_UINT32_MAX UINT32_MAX /**< Maximum number of UINT32 */ #define RT_UINT64_MAX UINT64_MAX /**< Maximum number of UINT64 */ #else -#define RT_UINT8_MAX 0xff /**< Maximum number of UINT8 */ -#define RT_UINT16_MAX 0xffff /**< Maximum number of UINT16 */ -#define RT_UINT32_MAX 0xffffffff /**< Maximum number of UINT32 */ -#define RT_UINT64_MAX 0xffffffffffffffff +#define RT_UINT8_MAX 0xFFU /**< Maximum number of UINT8 */ +#define RT_UINT16_MAX 0xFFFFU /**< Maximum number of UINT16 */ +#define RT_UINT32_MAX 0xFFFFFFFFUL /**< Maximum number of UINT32 */ +#define RT_UINT64_MAX 0xFFFFFFFFFFFFFFFFULL /**< Maximum number of UINT64 */ #endif /* RT_USING_LIBC */ #define RT_TICK_MAX RT_UINT32_MAX /**< Maximum number of tick */ @@ -238,58 +239,6 @@ typedef int (*init_fn_t)(void); #define RT_KERNEL_REALLOC(ptr, size) rt_realloc(ptr, size) #endif /* RT_KERNEL_REALLOC */ -/** - * @addtogroup Error - */ - -/**@{*/ - -/* RT-Thread error code definitions */ -#if defined(RT_USING_LIBC) && !defined(RT_USING_NANO) -/* POSIX error code compatible */ -#define RT_EOK 0 /**< There is no error */ -#define RT_ERROR 255 /**< A generic/unknown error happens */ -#define RT_ETIMEOUT ETIMEDOUT /**< Timed out */ -#define RT_EFULL ENOSPC /**< The resource is full */ -#define RT_EEMPTY ENODATA /**< The resource is empty */ -#define RT_ENOMEM ENOMEM /**< No memory */ -#define RT_ENOSYS ENOSYS /**< Function not implemented */ -#define RT_EBUSY EBUSY /**< Busy */ -#define RT_EIO EIO /**< IO error */ -#define RT_EINTR EINTR /**< Interrupted system call */ -#define RT_EINVAL EINVAL /**< Invalid argument */ -#define RT_ENOENT ENOENT /**< No entry */ -#define RT_ENOSPC ENOSPC /**< No space left */ -#define RT_EPERM EPERM /**< Operation not permitted */ -#define RT_EFAULT EFAULT /**< Bad address */ -#define RT_ENOBUFS ENOBUFS /**< No buffer space is available */ -#define RT_ESCHEDISR 253 /**< scheduler failure in isr context */ -#define RT_ESCHEDLOCKED 252 /**< scheduler failure in critical region */ -#define RT_ETRAP 254 /**< Trap event */ -#else -#define RT_EOK 0 /**< There is no error */ -#define RT_ERROR 1 /**< A generic/unknown error happens */ -#define RT_ETIMEOUT 2 /**< Timed out */ -#define RT_EFULL 3 /**< The resource is full */ -#define RT_EEMPTY 4 /**< The resource is empty */ -#define RT_ENOMEM 5 /**< No memory */ -#define RT_ENOSYS 6 /**< Function not implemented */ -#define RT_EBUSY 7 /**< Busy */ -#define RT_EIO 8 /**< IO error */ -#define RT_EINTR 9 /**< Interrupted system call */ -#define RT_EINVAL 10 /**< Invalid argument */ -#define RT_ENOENT 11 /**< No entry */ -#define RT_ENOSPC 12 /**< No space left */ -#define RT_EPERM 13 /**< Operation not permitted */ -#define RT_ETRAP 14 /**< Trap event */ -#define RT_EFAULT 15 /**< Bad address */ -#define RT_ENOBUFS 16 /**< No buffer space is available */ -#define RT_ESCHEDISR 17 /**< scheduler failure in isr context */ -#define RT_ESCHEDLOCKED 18 /**< scheduler failure in critical region */ -#endif /* defined(RT_USING_LIBC) && !defined(RT_USING_NANO) */ - -/**@}*/ - /** * @ingroup BasicDef * @@ -725,6 +674,12 @@ typedef struct rt_cpu_usage_stats *rt_cpu_usage_stats_t; #define RT_STOP_IPI 1 #endif /* RT_STOP_IPI */ +#ifndef RT_FUNC_IPI +#define RT_FUNC_IPI 2 +#endif + +#define RT_MAX_IPI 3 + #define _SCHEDULER_CONTEXT(fileds) fileds /** diff --git a/include/rtklibc.h b/include/rtklibc.h index 52fd8b9f1c5..1577c20a6fe 100644 --- a/include/rtklibc.h +++ b/include/rtklibc.h @@ -14,44 +14,8 @@ #include #include -#ifdef __cplusplus -extern "C" { -#endif - -/* kstdio */ -int rt_vsprintf(char *dest, const char *format, va_list arg_ptr); -int rt_vsnprintf(char *buf, rt_size_t size, const char *fmt, va_list args); -int rt_sprintf(char *buf, const char *format, ...); -int rt_snprintf(char *buf, rt_size_t size, const char *format, ...); - -rt_err_t rt_get_errno(void); -void rt_set_errno(rt_err_t no); -int *_rt_errno(void); -const char *rt_strerror(rt_err_t error); -#if !defined(RT_USING_NEWLIBC) && !defined(_WIN32) -#ifndef errno -#define errno *_rt_errno() -#endif -#endif /* !defined(RT_USING_NEWLIBC) && !defined(_WIN32) */ - -/* kstring */ - -void *rt_memset(void *src, int c, rt_ubase_t n); -void *rt_memcpy(void *dest, const void *src, rt_ubase_t n); -void *rt_memmove(void *dest, const void *src, rt_size_t n); -rt_int32_t rt_memcmp(const void *cs, const void *ct, rt_size_t count); -char *rt_strdup(const char *s); -rt_size_t rt_strnlen(const char *s, rt_ubase_t maxlen); -char *rt_strstr(const char *str1, const char *str2); -rt_int32_t rt_strcasecmp(const char *a, const char *b); -char *rt_strcpy(char *dst, const char *src); -char *rt_strncpy(char *dest, const char *src, rt_size_t n); -rt_int32_t rt_strncmp(const char *cs, const char *ct, rt_size_t count); -rt_int32_t rt_strcmp(const char *cs, const char *ct); -rt_size_t rt_strlen(const char *src); - -#ifdef __cplusplus -} -#endif +#include "klibc/kstring.h" +#include "klibc/kstdio.h" +#include "klibc/kerrno.h" #endif /* __RT_KLIBC_H__ */ diff --git a/libcpu/aarch64/common/include/vector_gcc.h b/libcpu/aarch64/common/include/vector_gcc.h index 31c532316e0..63df0c59e30 100644 --- a/libcpu/aarch64/common/include/vector_gcc.h +++ b/libcpu/aarch64/common/include/vector_gcc.h @@ -54,6 +54,52 @@ #include "../up/context_gcc.h" #endif +.macro RESTORE_IRQ_CONTEXT_NO_SPEL0 + ldp x2, x3, [sp], #0x10 + msr elr_el1, x2 + msr spsr_el1, x3 + + ldp x29, x30, [sp], #0x10 + + ldp x28, x29, [sp], #0x10 + msr fpcr, x28 + msr fpsr, x29 + + ldp x28, x29, [sp], #0x10 + ldp x26, x27, [sp], #0x10 + ldp x24, x25, [sp], #0x10 + ldp x22, x23, [sp], #0x10 + ldp x20, x21, [sp], #0x10 + ldp x18, x19, [sp], #0x10 + ldp x16, x17, [sp], #0x10 + ldp x14, x15, [sp], #0x10 + ldp x12, x13, [sp], #0x10 + ldp x10, x11, [sp], #0x10 + ldp x8, x9, [sp], #0x10 + ldp x6, x7, [sp], #0x10 + ldp x4, x5, [sp], #0x10 + ldp x2, x3, [sp], #0x10 + ldp x0, x1, [sp], #0x10 + + RESTORE_FPU sp +.endm + +.macro EXCEPTION_SWITCH, eframex, tmpx +#ifdef RT_USING_SMART + /** + * test the spsr for execution level 0 + * That is { PSTATE.[NZCV] := SPSR_EL1 & M.EL0t } + */ + ldr \tmpx, [\eframex, #CONTEXT_OFFSET_SPSR_EL1] + and \tmpx, \tmpx, 0x1f + cbz \tmpx, 1f + b 2f +1: + b arch_ret_to_user +2: +#endif /* RT_USING_SMART */ +.endm + .macro SAVE_USER_CTX, eframex, tmpx #ifdef RT_USING_SMART mrs \tmpx, spsr_el1 diff --git a/libcpu/aarch64/common/setup.c b/libcpu/aarch64/common/setup.c index 304e8565fbc..6c16801a107 100644 --- a/libcpu/aarch64/common/setup.c +++ b/libcpu/aarch64/common/setup.c @@ -13,7 +13,7 @@ #define DBG_TAG "cpu.aa64" #define DBG_LVL DBG_INFO #include - +#include #include #include #include @@ -302,11 +302,14 @@ void rt_hw_common_setup(void) rt_thread_idle_sethook(rt_hw_idle_wfi); #ifdef RT_USING_SMP + rt_smp_init(); /* Install the IPI handle */ rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler); rt_hw_ipi_handler_install(RT_STOP_IPI, rt_scheduler_ipi_handler); + rt_hw_ipi_handler_install(RT_FUNC_IPI, rt_smp_call_ipi_handler); rt_hw_interrupt_umask(RT_SCHEDULE_IPI); rt_hw_interrupt_umask(RT_STOP_IPI); + rt_hw_interrupt_umask(RT_FUNC_IPI); #endif } diff --git a/libcpu/aarch64/common/up/context_gcc.h b/libcpu/aarch64/common/up/context_gcc.h index cb48e5f2446..d2f6e9a755e 100644 --- a/libcpu/aarch64/common/up/context_gcc.h +++ b/libcpu/aarch64/common/up/context_gcc.h @@ -19,17 +19,23 @@ #include #include -.macro RESTORE_CONTEXT_SWITCH using_sp - /* Set the SP to point to the stack of the task being restored. */ - mov sp, \using_sp - +/* restore address space */ +.macro RESTORE_ADDRESS_SPACE #ifdef RT_USING_SMART bl rt_thread_self mov x19, x0 bl lwp_aspace_switch mov x0, x19 bl lwp_user_setting_restore -#endif /* RT_USING_SMART */ +#endif +.endm + +.macro RESTORE_CONTEXT_SWITCH using_sp + /* Set the SP to point to the stack of the task being restored. */ + mov sp, \using_sp + + RESTORE_ADDRESS_SPACE + _RESTORE_CONTEXT_SWITCH .endm diff --git a/libcpu/aarch64/common/up/vector_gcc.S b/libcpu/aarch64/common/up/vector_gcc.S index 26428fa597b..8b51a482827 100644 --- a/libcpu/aarch64/common/up/vector_gcc.S +++ b/libcpu/aarch64/common/up/vector_gcc.S @@ -28,7 +28,8 @@ vector_fiq: SAVE_IRQ_CONTEXT bl rt_hw_trap_fiq - RESTORE_IRQ_CONTEXT + + b rt_hw_irq_exit .globl rt_thread_switch_interrupt_flag .globl rt_hw_context_switch_interrupt_do diff --git a/libcpu/aarch64/common/vector_gcc.S b/libcpu/aarch64/common/vector_gcc.S index aaa172fcf9e..d4c6223bcf1 100644 --- a/libcpu/aarch64/common/vector_gcc.S +++ b/libcpu/aarch64/common/vector_gcc.S @@ -79,7 +79,11 @@ START_POINT(vector_exception) bl rt_hw_trap_exception RESTORE_USER_CTX EFRAMEX, x0 + /* do exception switch for IRQ/exception handlers */ + EXCEPTION_SWITCH sp, x0 + RESTORE_IRQ_CONTEXT + eret START_POINT_END(vector_exception) START_POINT(vector_serror) @@ -123,4 +127,8 @@ START_POINT_END(vector_irq) rt_hw_irq_exit: .globl rt_hw_irq_exit + /* do exception switch for IRQ/exception handlers */ + EXCEPTION_SWITCH sp, x0 + RESTORE_IRQ_CONTEXT + eret diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript index 0f3ce9f233b..273c997e8eb 100644 --- a/libcpu/risc-v/SConscript +++ b/libcpu/risc-v/SConscript @@ -5,7 +5,7 @@ from building import * Import('rtconfig') -common64_arch = ['virt64', 'c906'] +common64_arch = ['virt64', 'c906', 'c908'] cwd = GetCurrentDir() group = [] list = os.listdir(cwd) @@ -17,7 +17,7 @@ else : group += SConscript(os.path.join('common', 'SConscript')) # cpu porting code files -if rtconfig.CPU == "c906": +if 'VENDOR' in vars(rtconfig) and rtconfig.VENDOR != '': group = group + SConscript(os.path.join(rtconfig.VENDOR, rtconfig.CPU, 'SConscript')) elif rtconfig.CPU in list: group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) diff --git a/libcpu/risc-v/t-head/c908/SConscript b/libcpu/risc-v/t-head/c908/SConscript new file mode 100644 index 00000000000..5f750ad65f4 --- /dev/null +++ b/libcpu/risc-v/t-head/c908/SConscript @@ -0,0 +1,13 @@ +# RT-Thread building script for component + +from building import * +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') +CPPPATH = [cwd] + +if not GetDepend('ARCH_USING_ASID'): + SrcRemove(src, ['asid.c']) + +group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/risc-v/t-head/c908/asm/sbiasm.h b/libcpu/risc-v/t-head/c908/asm/sbiasm.h new file mode 100644 index 00000000000..4639fba68cf --- /dev/null +++ b/libcpu/risc-v/t-head/c908/asm/sbiasm.h @@ -0,0 +1,10 @@ +#ifndef _SBI_ASM_H +#define _SBI_ASM_H + +.macro SBI_CALL which + li a7, \which + ecall + nop +.endm + +#endif /* _SBI_ASM_H */ diff --git a/libcpu/risc-v/t-head/c908/asm/sbidef.h b/libcpu/risc-v/t-head/c908/asm/sbidef.h new file mode 100644 index 00000000000..5bcf58ade7c --- /dev/null +++ b/libcpu/risc-v/t-head/c908/asm/sbidef.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2019-2020, Xim + * + * SPDX-License-Identifier: Apache-2.0 + * + */ +#ifndef _ASM_SBI_DEF_H +#define _ASM_SBI_DEF_H + +#define SBI_SET_TIMER 0 +#define SBI_CONSOLE_PUTCHAR 1 +#define SBI_CONSOLE_GETCHAR 2 +#define SBI_CLEAR_IPI 3 +#define SBI_SEND_IPI 4 +#define SBI_REMOTE_FENCE_I 5 +#define SBI_REMOTE_SFENCE_VMA 6 +#define SBI_REMOTE_SFENCE_VMA_ASID 7 +#define SBI_SHUTDOWN 8 + +#define SBI_CONSOLE_PUTSTR 9 + +#define SBI_SD_WRITE 10 +#define SBI_SD_READ 11 +#define SBI_NET_WRITE 12 +#define SBI_NET_READ 13 + +#endif /* _ASM_SBI_DEF_H */ diff --git a/libcpu/risc-v/t-head/c908/cache.c b/libcpu/risc-v/t-head/c908/cache.c new file mode 100644 index 00000000000..db573fa5f81 --- /dev/null +++ b/libcpu/risc-v/t-head/c908/cache.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-29 lizhirui first version + * 2021-11-05 JasonHu add C908 cache inst + * 2022-11-09 WangXiaoyao Support cache coherence operations; + * improve portability and make + * no assumption on undefined behavior + */ + +#include +#include +#include +#include + +#include "opcode.h" +#include "cache.h" + +#define L1_CACHE_BYTES (64) + +/** + * GCC version not support t-head cache flush, so we use fixed code to achieve. + * The following function cannot be optimized. + */ +static void dcache_wb_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))); +static void dcache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))); +static void dcache_wbinv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))); +static void icache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))); + +#define CACHE_OP_RS1 %0 +#define CACHE_OP_RANGE(instr) \ + { \ + rt_ubase_t i = start & ~(L1_CACHE_BYTES - 1); \ + for (; i < end; i += L1_CACHE_BYTES) \ + { \ + __asm__ volatile(instr ::"r"(i) \ + : "memory"); \ + } \ + } + +static void dcache_wb_range(unsigned long start, unsigned long end) +{ + CACHE_OP_RANGE(OPC_DCACHE_CVA(CACHE_OP_RS1)); +} + +static void dcachel1_wb_range(unsigned long start, unsigned long end) +{ + CACHE_OP_RANGE(OPC_DCACHE_CVAL1(CACHE_OP_RS1)); +} + +static void dcache_inv_range(unsigned long start, unsigned long end) +{ + CACHE_OP_RANGE(OPC_DCACHE_IVA(CACHE_OP_RS1)); +} + +static void dcache_wbinv_range(unsigned long start, unsigned long end) +{ + CACHE_OP_RANGE(OPC_DCACHE_CIVA(CACHE_OP_RS1)); +} + +static void icache_inv_range(unsigned long start, unsigned long end) +{ + CACHE_OP_RANGE(OPC_ICACHE_IVA(CACHE_OP_RS1)); +} + +rt_inline rt_uint32_t rt_cpu_icache_line_size(void) +{ + return L1_CACHE_BYTES; +} + +rt_inline rt_uint32_t rt_cpu_dcache_line_size(void) +{ + return L1_CACHE_BYTES; +} + +void rt_hw_cpu_icache_invalidate_local(void *addr, int size) +{ + icache_inv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); + rt_hw_cpu_sync_i(); +} + +void rt_hw_cpu_dcache_invalidate_local(void *addr, int size) +{ + dcache_inv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); + rt_hw_cpu_sync(); +} + +void rt_hw_cpu_dcache_clean_local(void *addr, int size) +{ + dcache_wb_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); + rt_hw_cpu_sync(); +} + +void rt_hw_cpu_dcache_clean_invalidate_local(void *addr, int size) +{ + dcache_wbinv_range((unsigned long)addr, (unsigned long)((unsigned char *)addr + size)); + rt_hw_cpu_sync(); +} + +void rt_hw_cpu_dcachel1_clean_local(void *addr, int size) +{ + __asm__ volatile(OPC_DCACHE_CVAL1(a0):: + : "memory"); +} + +/** + * ===================================================== + * Architecture Independent API + * ===================================================== + */ + +void rt_hw_cpu_icache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_INVALIDATE) + { + rt_hw_cpu_icache_invalidate(addr, size); + } +} + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) + { + rt_hw_cpu_dcache_clean(addr, size); + } + else + { + rt_hw_cpu_dcache_invalidate(addr, size); + } +} + +void rt_hw_sync_cache_local(void *addr, int size) +{ + rt_hw_cpu_dcachel1_clean_local(addr, size); + rt_hw_cpu_icache_invalidate_local(addr, size); +} diff --git a/libcpu/risc-v/t-head/c908/cache.h b/libcpu/risc-v/t-head/c908/cache.h new file mode 100644 index 00000000000..09ebce6861f --- /dev/null +++ b/libcpu/risc-v/t-head/c908/cache.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-11-05 JasonHu The first version + * 2022-11-09 WangXiaoyao Distinguish local and broadcast operations + */ + +#ifndef CACHE_H__ +#define CACHE_H__ + +#include "opcode.h" + +#ifndef ALWAYS_INLINE +#define ALWAYS_INLINE inline __attribute__((always_inline)) +#endif + +ALWAYS_INLINE void rt_hw_cpu_sync(void) +{ + asm volatile(OPC_SYNC:: + : "memory"); +} + +ALWAYS_INLINE void rt_hw_cpu_sync_i(void) +{ + asm volatile(OPC_SYNC_I:: + : "memory"); +} + +ALWAYS_INLINE void rt_hw_cpu_sync_s(void) +{ + asm volatile(OPC_SYNC_S:: + : "memory"); +} + +ALWAYS_INLINE void rt_hw_cpu_sync_is(void) +{ + asm volatile(OPC_SYNC_IS:: + : "memory"); +} + +/** + * ======================================== + * Local cpu cache maintainence operations + * ======================================== + */ + +void rt_hw_cpu_dcache_clean_local(void *addr, int size); +void rt_hw_cpu_dcache_invalidate_local(void *addr, int size); +void rt_hw_cpu_dcache_clean_invalidate_local(void *addr, int size); + +void rt_hw_cpu_icache_invalidate_local(void *addr, int size); + +ALWAYS_INLINE void rt_hw_cpu_dcache_clean_all_local(void) +{ + __asm__ volatile(OPC_DCACHE_CALL :: + : "memory"); + rt_hw_cpu_sync(); +} + +ALWAYS_INLINE void rt_hw_cpu_dcache_invalidate_all_local(void) +{ + __asm__ volatile(OPC_DCACHE_IALL :: + : "memory"); + rt_hw_cpu_sync(); +} + +ALWAYS_INLINE void rt_hw_cpu_dcache_clean_invalidate_all_local(void) +{ + __asm__ volatile(OPC_DCACHE_CIALL :: + : "memory"); + rt_hw_cpu_sync(); +} + +ALWAYS_INLINE void rt_hw_cpu_icache_invalidate_all_local(void) +{ + __asm__ volatile(OPC_ICACHE_IALL :: + : "memory"); + rt_hw_cpu_sync_i(); +} + +#define rt_hw_icache_invalidate_all rt_hw_cpu_icache_invalidate_all + +/** + * ======================================== + * Multi-core cache maintainence operations + * ======================================== + */ + +#ifdef RT_USING_SMP +#error "TODO: cache maintainence have not ported to RISC-V SMP yet" + +void rt_hw_cpu_dcache_clean(void *addr, int size); +void rt_hw_cpu_dcache_invalidate(void *addr, int size); +void rt_hw_cpu_dcache_clean_invalidate(void *addr, int size); + +void rt_hw_cpu_dcache_clean_all(void); +void rt_hw_cpu_dcache_invalidate_all(void); +void rt_hw_cpu_dcache_clean_invalidate_all(void); + +void rt_hw_cpu_icache_invalidate(void *addr, int size); +void rt_hw_cpu_icache_invalidate_all(void); + +#else /* !RT_USING_SMP */ + +#define rt_hw_cpu_dcache_clean rt_hw_cpu_dcache_clean_local +#define rt_hw_cpu_dcache_invalidate rt_hw_cpu_dcache_invalidate_local +#define rt_hw_cpu_dcache_clean_and_invalidate rt_hw_cpu_dcache_clean_invalidate_local + +#define rt_hw_cpu_dcache_clean_all rt_hw_cpu_dcache_clean_all_local +#define rt_hw_cpu_dcache_invalidate_all rt_hw_cpu_dcache_invalidate_all_local +#define rt_hw_cpu_dcache_clean_invalidate_all rt_hw_cpu_dcache_clean_invalidate_all_local + +#define rt_hw_cpu_icache_invalidate rt_hw_cpu_icache_invalidate_local +#define rt_hw_cpu_icache_invalidate_all rt_hw_cpu_icache_invalidate_all_local + +#endif /* RT_USING_SMP */ + +/** + * @brief Synchronize cache to Point of Unification + */ +void rt_hw_sync_cache_local(void *addr, int size); + +#endif /* CACHE_H__ */ diff --git a/libcpu/risc-v/t-head/c908/interrupt.c b/libcpu/risc-v/t-head/c908/interrupt.c new file mode 100644 index 00000000000..9e4cf2f1579 --- /dev/null +++ b/libcpu/risc-v/t-head/c908/interrupt.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-19 JasonHu first version + */ + +#include +#include + +#include "interrupt.h" +#include "riscv.h" +#include "plic.h" + +extern rt_uint32_t rt_interrupt_nest; +extern rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; +extern rt_uint32_t rt_thread_switch_interrupt_flag; + +struct rt_irq_desc isr_table[INTERRUPTS_MAX]; + +static void rt_hw_interrupt_handler(int vector, void *param) +{ + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); +} + +/** + * This function will initialize hardware interrupt + */ +void rt_hw_interrupt_init(void) +{ + /* init interrupt controller */ + plic_init(); + + rt_int32_t idx; + + rt_memset(isr_table, 0x00, sizeof(isr_table)); + for (idx = 0; idx < INTERRUPTS_MAX; idx++) + { + isr_table[idx].handler = rt_hw_interrupt_handler; + } + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; +} + +/** + * This function will mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_mask(int vector) +{ + if ((vector < 0) || (vector > IRQ_MAX_NR)) + { + return; + } + plic_disable_irq(vector); +} + +/** + + * This function will un-mask a interrupt. + * @param vector the interrupt number + */ +void rt_hw_interrupt_umask(int vector) +{ + if ((vector < 0) || (vector > IRQ_MAX_NR)) + { + return; + } + plic_enable_irq(vector); +} + +/** + * This function will install a interrupt service routine to a interrupt. + * @param vector the interrupt number + * @param handler the interrupt service routine to be installed + * @param param the interrupt service function parameter + * @param name the interrupt name + * @return old handler + */ +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) +{ + rt_isr_handler_t old_handler = RT_NULL; + if ((vector < 0) || (vector > IRQ_MAX_NR)) + { + return old_handler; + } + + old_handler = isr_table[IRQ_OFFSET + vector].handler; + +#ifdef RT_USING_INTERRUPT_INFO + rt_strncpy(isr_table[IRQ_OFFSET + vector].name, name, RT_NAME_MAX); +#endif /* RT_USING_INTERRUPT_INFO */ + isr_table[IRQ_OFFSET + vector].handler = handler; + isr_table[IRQ_OFFSET + vector].param = param; + + return old_handler; +} diff --git a/libcpu/risc-v/t-head/c908/interrupt.h b/libcpu/risc-v/t-head/c908/interrupt.h new file mode 100644 index 00000000000..2ee08248375 --- /dev/null +++ b/libcpu/risc-v/t-head/c908/interrupt.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-19 JasonHu first version + */ + +#ifndef __INTERRUPT_H__ +#define __INTERRUPT_H__ + +#include + +#define NR_CPUS 1 + +#define IRQ_OFFSET 16 +#ifndef IRQ_MAX_NR +#define IRQ_MAX_NR 200 +#endif +#define INTERRUPTS_MAX (IRQ_OFFSET + IRQ_MAX_NR) + +enum { + EP_INSTRUCTION_ADDRESS_MISALIGNED = 0, + EP_INSTRUCTION_ACCESS_FAULT, + EP_ILLEGAL_INSTRUCTION, + EP_BREAKPOINT, + EP_LOAD_ADDRESS_MISALIGNED, + EP_LOAD_ACCESS_FAULT, + EP_STORE_ADDRESS_MISALIGNED, + EP_STORE_ACCESS_FAULT, + EP_ENVIRONMENT_CALL_U_MODE, + EP_ENVIRONMENT_CALL_S_MODE, + EP_RESERVED10, + EP_ENVIRONMENT_CALL_M_MODE, + EP_INSTRUCTION_PAGE_FAULT, /* page attr */ + EP_LOAD_PAGE_FAULT, /* read data */ + EP_RESERVED14, + EP_STORE_PAGE_FAULT, /* write data */ +}; + +void rt_hw_interrupt_init(void); +void rt_hw_interrupt_mask(int vector); +void rt_hw_interrupt_umask(int vector); +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name); + +#endif diff --git a/libcpu/risc-v/t-head/c908/opcode.h b/libcpu/risc-v/t-head/c908/opcode.h new file mode 100644 index 00000000000..90b002dc4eb --- /dev/null +++ b/libcpu/risc-v/t-head/c908/opcode.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-11-09 WangXiaoyao Add portable asm support + * 2022-03-16 WangXiaoyao Porting to xtheadsync & xtheadcmo ISA extension + */ +#ifndef __OPCODE_H__ +#define __OPCODE_H__ + +/** + * @brief binary opcode pseudo operations + * Used to bypass toolchain restriction on extension ISA + * + * WARNING: Xuantie ISAs are not compatible to each other in opcode. + * It's painful to port this file, and should be really careful. + */ + +/** + * @brief RISC-V instruction formats + */ + +/** + * R type: .insn r opcode6, func3, func7, rd, rs1, rs2 + * + * +-------+-----+-----+-------+----+---------+ + * | func7 | rs2 | rs1 | func3 | rd | opcode6 | + * +-------+-----+-----+-------+----+---------+ + * 31 25 20 15 12 7 0 + */ +#define __OPC_INSN_FORMAT_R(opcode, func3, func7, rd, rs1, rs2) \ + ".insn r "RT_STRINGIFY(opcode)","RT_STRINGIFY(func3)","RT_STRINGIFY(func7)","RT_STRINGIFY(rd)","RT_STRINGIFY(rs1)","RT_STRINGIFY(rs2) + +/** + * @brief Xuantie T-HEAD extension ISA format + * Compatible to Xuantie C908 user manual v03 + */ +#define __OPC_INSN_FORMAT_CACHE(func7, rs2, rs1) \ + __OPC_INSN_FORMAT_R(0x0b, 0x0, func7, x0, rs1, rs2) + +#ifdef _TOOLCHAIN_SUPP_XTHEADE_ISA_ +#define OPC_SYNC "sync" +#define OPC_SYNC_S "sync.s" +#define OPC_SYNC_I "sync.i" +#define OPC_SYNC_IS "sync.is" + +#define OPC_DCACHE_CALL "dcache.call" +#define OPC_DCACHE_IALL "dcache.iall" +#define OPC_DCACHE_CIALL "dcache.ciall" +#define OPC_DCACHE_CVAL1(rs1) "dcache.cval1 "_TOSTR(rs1) + +#define OPC_ICACHE_IALL "icache.iall" + +#define OPC_DCACHE_CVA(rs1) "dcache.cva "RT_STRINGIFY(rs1) +#define OPC_DCACHE_IVA(rs1) "dcache.iva "RT_STRINGIFY(rs1) +#define OPC_DCACHE_CIVA(rs1) "dcache.civa "RT_STRINGIFY(rs1) + +#define OPC_ICACHE_IVA(rs1) "icache.iva "RT_STRINGIFY(rs1) +#else /* !_TOOLCHAIN_NOT_SUPP_THEAD_ISA_ */ + +#define OPC_SYNC ".long 0x0180000B" +#define OPC_SYNC_S ".long 0x0190000B" +#define OPC_SYNC_I ".long 0x01A0000B" +#define OPC_SYNC_IS ".long 0x01B0000B" + +#define OPC_DCACHE_CALL ".long 0x0010000B" +#define OPC_DCACHE_IALL ".long 0x0020000B" +#define OPC_DCACHE_CIALL ".long 0x0030000B" +#define OPC_DCACHE_CVAL1(rs1) __OPC_INSN_FORMAT_CACHE(0x1, x4, rs1) + +#define OPC_ICACHE_IALL ".long 0x0100000B" + +#define OPC_DCACHE_CVA(rs1) __OPC_INSN_FORMAT_CACHE(0x1, x5, rs1) +#define OPC_DCACHE_IVA(rs1) __OPC_INSN_FORMAT_CACHE(0x1, x6, rs1) +#define OPC_DCACHE_CIVA(rs1) __OPC_INSN_FORMAT_CACHE(0x1, x7, rs1) + +#define OPC_ICACHE_IVA(rs1) __OPC_INSN_FORMAT_CACHE(0x1, x16, rs1) +#endif /* _TOOLCHAIN_NOT_SUPP_THEAD_ISA_ */ + +/** + * @brief RISC-V zifencei ISA + */ +#ifdef _TOOLCHAIN_SUPP_ZIFENCEI_ISA_ +#define OPC_FENCE_I "fence.i" +#else /* !_TOOLCHAIN_SUPP_ZIFENCEI_ISA_ */ +#define OPC_FENCE_I ".long 0x0000100F" +#endif /* _TOOLCHAIN_SUPP_ZIFENCEI_ISA_ */ + +#endif /* __OPCODE_H__ */ diff --git a/libcpu/risc-v/t-head/c908/plic.c b/libcpu/risc-v/t-head/c908/plic.c new file mode 100644 index 00000000000..08cb6c18d2f --- /dev/null +++ b/libcpu/risc-v/t-head/c908/plic.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-19 JasonHu first version + * 2021-11-12 JasonHu fix bug that not intr on f133 + * 2023-04-22 flyingcys add plic register ioremap + */ + +#include + +#include + +#include "plic.h" +#include "interrupt.h" +#include "io.h" +#include "encoding.h" +#include "ioremap.h" + +static void *plic_regs = RT_NULL; +extern struct rt_irq_desc isr_table[]; + +struct plic_handler +{ + rt_bool_t present; + void *hart_base; + void *enable_base; +}; + +rt_inline void plic_toggle(struct plic_handler *handler, int hwirq, int enable); +struct plic_handler plic_handlers[C908_NR_CPUS]; +static void *plic_irq_priority[INTERRUPTS_MAX] = {RT_NULL}; + +rt_inline void plic_irq_toggle(int hwirq, int enable) +{ + int cpu = 0; + void *priority_addr; + + /* set priority of interrupt, interrupt 0 is zero. */ + priority_addr = (void *)((rt_size_t)plic_regs + PRIORITY_BASE + hwirq * PRIORITY_PER_ID); +#ifdef RT_USING_SMART + if (plic_irq_priority[hwirq] == RT_NULL) + { + plic_irq_priority[hwirq] = (void *)rt_ioremap(priority_addr, 0x1000); + } + priority_addr = plic_irq_priority[hwirq]; +#endif + writel(enable, priority_addr); + struct plic_handler *handler = &plic_handlers[cpu]; + + if (handler->present) + { + plic_toggle(handler, hwirq, enable); + } +} + +static void generic_handle_irq(int irq) +{ + rt_isr_handler_t isr; + void *param; + + if (irq < 0 || irq >= IRQ_MAX_NR) + { + LOG_E("bad irq number %d!\n", irq); + return; + } + + if (!irq) // irq = 0 => no irq + { + LOG_W("no irq!\n"); + return; + } + isr = isr_table[IRQ_OFFSET + irq].handler; + param = isr_table[IRQ_OFFSET + irq].param; + if (isr != RT_NULL) + { + isr(irq, param); + } + /* complete irq. */ + plic_complete(irq); +} + +void plic_complete(int irqno) +{ + int cpu = 0; + struct plic_handler *handler = &plic_handlers[cpu]; + + writel(irqno, (void *)((rt_size_t)handler->hart_base + CONTEXT_CLAIM)); +} + +void plic_disable_irq(int irqno) +{ + plic_irq_toggle(irqno, 0); +} + +void plic_enable_irq(int irqno) +{ + plic_irq_toggle(irqno, 1); +} + +/* + * Handling an interrupt is a two-step process: first you claim the interrupt + * by reading the claim register, then you complete the interrupt by writing + * that source ID back to the same claim register. This automatically enables + * and disables the interrupt, so there's nothing else to do. + */ +void plic_handle_irq(void) +{ + int cpu = 0; + unsigned int irq; + + struct plic_handler *handler = &plic_handlers[cpu]; + void *claim = (void *)((rt_size_t)handler->hart_base + CONTEXT_CLAIM); + + if (plic_regs == RT_NULL || !handler->present) + { + LOG_E("plic state not initialized."); + return; + } + + clear_csr(sie, SIE_SEIE); + + while ((irq = readl(claim))) + { + /* ID0 is diabled permantually from spec. */ + if (irq == 0) + { + LOG_E("irq no is zero."); + } + else + { + generic_handle_irq(irq); + } + } + set_csr(sie, SIE_SEIE); +} + +rt_inline void plic_toggle(struct plic_handler *handler, int hwirq, int enable) +{ + uint32_t *reg = (uint32_t *)((rt_size_t)handler->enable_base + (hwirq / 32) * sizeof(uint32_t)); + uint32_t hwirq_mask = 1 << (hwirq % 32); + + if (enable) + { + writel(readl(reg) | hwirq_mask, reg); + } + else + { + writel(readl(reg) & ~hwirq_mask, reg); + } +} + +void plic_init(void) +{ + int nr_irqs; + int nr_context; + int i; + unsigned long hwirq; + int cpu = 0; + + if (plic_regs) + { + LOG_E("plic already initialized!"); + return; + } + + nr_context = C908_NR_CONTEXT; + + plic_regs = (void *)C908_PLIC_PHY_ADDR; + if (!plic_regs) + { + LOG_E("fatal error, plic is reg space is null."); + return; + } + + nr_irqs = C908_PLIC_NR_EXT_IRQS; + + for (i = 0; i < nr_context; i ++) + { + struct plic_handler *handler; + uint32_t threshold = 0; + + cpu = 0; + + /* skip contexts other than supervisor external interrupt */ + if (i == 0) + { + continue; + } + + // we always use CPU0 M-mode target register. + handler = &plic_handlers[cpu]; + if (handler->present) + { + threshold = 0xffffffff; + goto done; + } + + handler->present = RT_TRUE; + handler->hart_base = (void *)((rt_size_t)plic_regs + CONTEXT_BASE + i * CONTEXT_PER_HART); + handler->enable_base = (void *)((rt_size_t)plic_regs + ENABLE_BASE + i * ENABLE_PER_HART); +#ifdef RT_USING_SMART + handler->hart_base = (void *)rt_ioremap(handler->hart_base, 0x1000); + handler->enable_base = (void *)rt_ioremap(handler->enable_base, 0x1000); +#endif +done: + /* priority must be > threshold to trigger an interrupt */ + writel(threshold, (void *)((rt_size_t)handler->hart_base + CONTEXT_THRESHOLD)); + for (hwirq = 1; hwirq <= nr_irqs; hwirq++) + { + plic_toggle(handler, hwirq, 0); + } + } + + /* Enable supervisor external interrupts. */ + set_csr(sie, SIE_SEIE); +} diff --git a/libcpu/risc-v/t-head/c908/plic.h b/libcpu/risc-v/t-head/c908/plic.h new file mode 100644 index 00000000000..94f00eacdb8 --- /dev/null +++ b/libcpu/risc-v/t-head/c908/plic.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-10-19 JasonHu first version + * 2023-04-22 flyingcys add C906_PLIC_PHY_ADDR macro judge + */ + +#ifndef __RISCV64_PLIC_H__ +#define __RISCV64_PLIC_H__ + +#include + +#ifndef C908_PLIC_PHY_ADDR +#define C908_PLIC_PHY_ADDR (0xF00000000UL) +#endif +#define C908_PLIC_NR_EXT_IRQS (IRQ_MAX_NR) +#define C908_NR_CPUS (NR_CPUS) + +/* M and S mode context. */ +#define C908_NR_CONTEXT (2) + +#define MAX_DEVICES 1024 +#define MAX_CONTEXTS 15872 + +/* + * Each interrupt source has a priority register associated with it. + * We always hardwire it to one in Linux. + */ +#define PRIORITY_BASE 0 +#define PRIORITY_PER_ID 4 + +/* + * Each hart context has a vector of interrupt enable bits associated with it. + * There's one bit for each interrupt source. + */ +#define ENABLE_BASE 0x2000 +#define ENABLE_PER_HART 0x80 + +/* + * Each hart context has a set of control registers associated with it. Right + * now there's only two: a source priority threshold over which the hart will + * take an interrupt, and a register to claim interrupts. + */ +#define CONTEXT_BASE 0x200000 +#define CONTEXT_PER_HART 0x1000 +#define CONTEXT_THRESHOLD 0x00 +#define CONTEXT_CLAIM 0x04 + +void plic_init(void); +void plic_enable_irq(int irqno); +void plic_disable_irq(int irqno); +// tell PLIC that we've served this IRQ +void plic_complete(int irq); +void plic_handle_irq(void); + +#endif diff --git a/libcpu/risc-v/t-head/c908/riscv_mmu.h b/libcpu/risc-v/t-head/c908/riscv_mmu.h new file mode 100644 index 00000000000..8fbe241f657 --- /dev/null +++ b/libcpu/risc-v/t-head/c908/riscv_mmu.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-01-30 lizhirui first version + * 2021-05-03 lizhirui porting to C906 + * 2023-10-12 Shell Add permission control API + */ + +#ifndef __RISCV_MMU_H__ +#define __RISCV_MMU_H__ + +#include +#include +#include "riscv.h" + +#undef PAGE_SIZE + +/* C-SKY extend */ +#define PTE_SEC (1UL << 59) /* Security */ +#define PTE_SHARE (1UL << 60) /* Shareable */ +#define PTE_BUF (1UL << 61) /* Bufferable */ +#define PTE_CACHE (1UL << 62) /* Cacheable */ +#define PTE_SO (1UL << 63) /* Strong Order */ + +#define PAGE_OFFSET_SHIFT 0 +#define PAGE_OFFSET_BIT 12 +#define PAGE_SIZE __SIZE(PAGE_OFFSET_BIT) +#define PAGE_OFFSET_MASK __MASK(PAGE_OFFSET_BIT) +#define VPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT) +#define VPN0_BIT 9 +#define VPN1_SHIFT (VPN0_SHIFT + VPN0_BIT) +#define VPN1_BIT 9 +#define VPN2_SHIFT (VPN1_SHIFT + VPN1_BIT) +#define VPN2_BIT 9 + +#define PPN0_SHIFT (PAGE_OFFSET_SHIFT + PAGE_OFFSET_BIT) +#define PPN0_BIT 9 +#define PPN1_SHIFT (PPN0_SHIFT + PPN0_BIT) +#define PPN1_BIT 9 +#define PPN2_SHIFT (PPN1_SHIFT + PPN1_BIT) +#define PPN2_BIT 26 + +#define L1_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT + VPN1_BIT) +#define L2_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT + VPN0_BIT) +#define L3_PAGE_SIZE __SIZE(PAGE_OFFSET_BIT) + +#define ARCH_ADDRESS_WIDTH_BITS 64 + +#define PHYSICAL_ADDRESS_WIDTH_BITS 56 + +#define PAGE_ATTR_NEXT_LEVEL (0) +#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R) +#define PAGE_ATTR_READONLY (PTE_R) +#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R) + +#define PAGE_ATTR_USER (PTE_U) +#define PAGE_ATTR_SYSTEM (0) + +#define PAGE_DEFAULT_ATTR_LEAF \ + (PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | \ + PTE_CACHE | PTE_A | PTE_D) + +#define PAGE_DEFAULT_ATTR_NEXT \ + (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G | PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D) + +#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX) + +#define PTE_USED(pte) __MASKVALUE(pte, PTE_V) +#define PTE_WRAP(attr) (attr | PTE_A | PTE_D) + +/** + * encoding of SATP (Supervisor Address Translation and Protection register) + */ +#define SATP_MODE_OFFSET 60 +#define SATP_MODE_BARE 0 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 + +#define ARCH_VADDR_WIDTH 39 +#define SATP_MODE SATP_MODE_SV39 + +//compatible to rt-smart new version +#define MMU_MAP_K_DEVICE (PTE_BUF | PTE_SO | PTE_A | PTE_D | PTE_G | PTE_W | PTE_R | PTE_V) +#define MMU_MAP_K_RW (PTE_SHARE | PTE_A | PTE_D | PTE_G | PAGE_ATTR_RWX | PTE_V) +#define MMU_MAP_K_RWCB (MMU_MAP_K_RW | PTE_BUF | PTE_CACHE) + +#define MMU_MAP_U_RW (PTE_SHARE | PTE_U | PTE_A | PTE_D | PAGE_ATTR_RWX | PTE_V) +#define MMU_MAP_U_RWCB (MMU_MAP_U_RW | PTE_BUF | PTE_CACHE) +#define MMU_MAP_EARLY \ + PTE_WRAP(PAGE_ATTR_RWX | PTE_G | PTE_V | PTE_CACHE | PTE_SHARE | PTE_BUF) +#define MMU_MAP_TRACE(attr) (attr) + +#define PTE_XWR_MASK 0xe + +#define ARCH_PAGE_SIZE PAGE_SIZE +#define ARCH_PAGE_MASK (ARCH_PAGE_SIZE - 1) +#define ARCH_PAGE_SHIFT PAGE_OFFSET_BIT +#define ARCH_INDEX_WIDTH 9 + +#define ARCH_MAP_FAILED ((void *)0x8000000000000000) + +void mmu_set_pagetable(rt_ubase_t addr); +void mmu_enable_user_page_access(void); +void mmu_disable_user_page_access(void); + +#define RT_HW_MMU_PROT_READ 1 +#define RT_HW_MMU_PROT_WRITE 2 +#define RT_HW_MMU_PROT_EXECUTE 4 +#define RT_HW_MMU_PROT_KERNEL 8 +#define RT_HW_MMU_PROT_USER 16 +#define RT_HW_MMU_PROT_CACHE 32 + +void rt_hw_asid_init(void); +struct rt_aspace; +void rt_hw_asid_switch_pgtbl(struct rt_aspace *aspace, rt_ubase_t pgtbl); + +/** + * @brief Remove permission from attribution + * + * @param attr architecture specified mmu attribution + * @param prot protect that will be removed + * @return size_t returned attribution + */ +rt_inline size_t rt_hw_mmu_attr_rm_perm(size_t attr, rt_base_t prot) +{ + switch (prot) + { + /* remove write permission for user */ + case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER: + attr &= ~PTE_W; + break; + /* remove write permission for kernel */ + case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_KERNEL: + attr &= ~PTE_W; + break; + default: + RT_ASSERT(0); + } + return attr; +} + +/** + * @brief Add permission from attribution + * + * @param attr architecture specified mmu attribution + * @param prot protect that will be added + * @return size_t returned attribution + */ +rt_inline size_t rt_hw_mmu_attr_add_perm(size_t attr, rt_base_t prot) +{ + switch (prot) + { + /* add write permission for user */ + case RT_HW_MMU_PROT_WRITE | RT_HW_MMU_PROT_USER: + attr |= (PTE_R | PTE_W | PTE_U); + break; + default: + RT_ASSERT(0); + } + return attr; +} + +/** + * @brief Test permission from attribution + * + * @param attr architecture specified mmu attribution + * @param prot protect that will be test + * @return rt_bool_t RT_TRUE if the prot is allowed, otherwise RT_FALSE + */ +rt_inline rt_bool_t rt_hw_mmu_attr_test_perm(size_t attr, rt_base_t prot) +{ + rt_bool_t rc = 0; + switch (prot & ~RT_HW_MMU_PROT_USER) + { + /* test write permission for user */ + case RT_HW_MMU_PROT_WRITE: + rc = ((attr & PTE_W) && (attr & PTE_R)); + break; + case RT_HW_MMU_PROT_READ: + rc = !!(attr & PTE_R); + break; + case RT_HW_MMU_PROT_EXECUTE: + rc = !!(attr & PTE_X); + break; + default: + RT_ASSERT(0); + } + + if (rc && (prot & RT_HW_MMU_PROT_USER)) + { + rc = !!(attr & PTE_U); + } + return rc; +} + +#endif diff --git a/libcpu/risc-v/t-head/c908/symbol_analysis.c b/libcpu/risc-v/t-head/c908/symbol_analysis.c new file mode 100644 index 00000000000..83edacb1c43 --- /dev/null +++ b/libcpu/risc-v/t-head/c908/symbol_analysis.c @@ -0,0 +1,298 @@ +/* + * Copyright lizhirui + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 lizhirui the first version + * 2021-05-20 lizhirui add os debug support + */ + +#include +#include "symbol_analysis.h" + +#define MEMORY_BASE 0x40000000 +#define MEMORY_SIZE (128 * 0x100000) + +extern rt_size_t _osdebug_start; + +static os_symtab_header *symtab_header = (os_symtab_header *)&_osdebug_start; + +//该函数用于在指定的表中查找某个地址对应的符号的描述结构体指针，返回值的符号遵循规则详见文档 +os_symtab_item *find_symbol_table(rt_size_t symbol_table_addr,rt_size_t symbol_num,rt_size_t address) +{ + rt_size_t left = 0; + rt_size_t right = symbol_num; + os_symtab_item *sym_table = (os_symtab_item *)((rt_size_t)&_osdebug_start + symbol_table_addr); + + while(left < right) + { + rt_size_t mid = (left + right) >> 1; + //rt_kprintf("left = %d,right = %d,mid = %d\n",left,right,mid); + + if(address < sym_table[mid].address) + { + right = mid; + + while((right < symbol_num) && ((right - 1) >= 0) && (sym_table[right].address == sym_table[right - 1].address)) + { + right--; + } + } + else if(address == sym_table[mid].address) + { + left = mid + 1; + break; + } + else + { + left = mid; + + while((left >= 0) && ((left + 1) < symbol_num) && (sym_table[left].address == sym_table[left + 1].address)) + { + left++; + } + + left++; + } + } + + left--; + + if(left == ((rt_size_t)-1)) + { + return RT_NULL; + } + + while((left < symbol_num) && ((left - 1) >= 0) && (sym_table[left].address == sym_table[left - 1].address)) + { + left--; + } + + return &sym_table[left]; +} + +//该函数用于根据给定的符号指针从字符串表中找到对应的符号名指针并返回 +const char *get_symbol_name(os_symtab_item *symbol) +{ + return (const char *)((rt_size_t)&_osdebug_start + symtab_header -> string_table_offset + symbol -> name_offset); +} + +//该函数可以根据给定的符号和地址向中断打印出标准格式的符号信息 +void print_symbol(os_symtab_item *symbol,rt_size_t address) +{ + rt_kprintf("<%s(0x%p)",get_symbol_name(symbol),symbol -> address); + + if(symbol -> size) + { + rt_kprintf(" : 0x%x>",symbol -> size); + } + else + { + rt_kprintf(">"); + } + + if(address > symbol -> address) + { + rt_kprintf(" + 0x%x",address - symbol -> address); + } +} + +//该函数用于打印出一个地址关联的全部符号信息 +void print_symbol_info(rt_size_t address,rt_bool_t function) +{ + os_symtab_item *function_symbol = find_symbol_table(symtab_header -> function_table_offset,symtab_header -> function_table_num,address); + os_symtab_item *object_symbol = find_symbol_table(symtab_header -> object_table_offset,symtab_header -> object_table_num,address); + os_symtab_item *general_symbol = find_symbol_table(symtab_header -> general_symbol_table_offset,symtab_header -> general_symbol_table_num,address); + const char *dot = ""; + rt_bool_t valid = RT_FALSE; + + if(function) + { + while(function_symbol != RT_NULL) + { + if((function_symbol -> address + function_symbol -> size) > address) + { + rt_kprintf(dot); + print_symbol(function_symbol,address); + dot = ","; + valid = RT_TRUE; + } + + if(((rt_size_t)(function_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> function_table_offset + symtab_header -> function_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(function_symbol[0].address == function_symbol[1].address) + { + function_symbol++; + } + + break; + } + + if(!valid) + { + while(general_symbol != RT_NULL) + { + rt_kprintf(dot); + print_symbol(general_symbol,address); + dot = ","; + valid = RT_TRUE; + + if(((rt_size_t)(general_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> general_symbol_table_offset + symtab_header -> general_symbol_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(general_symbol[0].address == general_symbol[1].address) + { + general_symbol++; + } + + break; + } + + while(object_symbol != RT_NULL) + { + if((object_symbol -> address + object_symbol -> size) > address) + { + rt_kprintf(dot); + print_symbol(object_symbol,address); + dot = ","; + valid = RT_TRUE; + } + + if(((rt_size_t)(object_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> object_table_offset + symtab_header -> object_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(object_symbol[0].address == object_symbol[1].address) + { + object_symbol++; + } + + break; + } + } + } + else + { + while(object_symbol != RT_NULL) + { + if((object_symbol -> address + object_symbol -> size) > address) + { + rt_kprintf(dot); + print_symbol(object_symbol,address); + dot = ","; + valid = RT_TRUE; + } + + if(((rt_size_t)(object_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> object_table_offset + symtab_header -> object_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(object_symbol[0].address == object_symbol[1].address) + { + object_symbol++; + } + + break; + } + + if(!valid) + { + while(general_symbol != RT_NULL) + { + rt_kprintf(dot); + print_symbol(general_symbol,address); + dot = ","; + valid = RT_TRUE; + + if(((rt_size_t)(general_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> general_symbol_table_offset + symtab_header -> general_symbol_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(general_symbol[0].address == general_symbol[1].address) + { + general_symbol++; + } + + break; + } + + while(function_symbol != RT_NULL) + { + if((function_symbol -> address + function_symbol -> size) > address) + { + rt_kprintf(dot); + print_symbol(function_symbol,address); + dot = ","; + valid = RT_TRUE; + } + + if(((rt_size_t)(function_symbol + 1)) >= (((rt_size_t)&_osdebug_start) + symtab_header -> function_table_offset + symtab_header -> function_table_num * sizeof(os_symtab_item))) + { + break; + } + + if(function_symbol[0].address == function_symbol[1].address) + { + function_symbol++; + } + + break; + } + } + } + + if(dot == "") + { + rt_kprintf(""); + } +} + +//该函数用于在出错时打印出栈跟踪信息 +void print_stacktrace(rt_size_t epc,rt_size_t fp) +{ + rt_kprintf("-----------------------------Dump Stacktrace----------------------------\n\n"); + rt_size_t sp = fp; + rt_size_t i = 0; + + rt_kprintf("address 0x%p(",epc); + print_symbol_info(epc,RT_TRUE); + rt_kprintf(")\n\n"); + + while(1) + { + if((sp >= MEMORY_BASE) && (sp < (MEMORY_BASE + MEMORY_SIZE))) + { + //rt_kprintf("%d: 0x%p\n",i,sp); + rt_size_t *stack = (rt_size_t *)(sp - sizeof(rt_size_t) * 2); + rt_size_t ra = stack[1]; + + if(!ra) + { + break; + } + + rt_kprintf("return to 0x%p(",ra); + print_symbol_info(ra,RT_TRUE); + rt_kprintf(")\n\n"); + //rt_kprintf("ra = 0x%p,fp = 0x%p\n",stack[1],stack[0]); + sp = stack[0]; + i++; + } + else + { + break; + } + } + + rt_kprintf("---------------------------------Dump OK--------------------------------\n"); +} diff --git a/libcpu/risc-v/t-head/c908/symbol_analysis.h b/libcpu/risc-v/t-head/c908/symbol_analysis.h new file mode 100644 index 00000000000..a9db46ffd39 --- /dev/null +++ b/libcpu/risc-v/t-head/c908/symbol_analysis.h @@ -0,0 +1,44 @@ +/* + * Copyright lizhirui + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021-05-18 lizhirui the first version + * 2021-05-20 lizhirui add os debug support + */ + +#ifndef __SYMBOL_ANALYSIS_H__ +#define __SYMBOL_ANALYSIS_H__ + + #include + + //osdebug节区头描述结构体 + typedef struct os_symtab_header + { + rt_size_t function_table_offset;//函数表的偏移地址（相对于节区起始地址，下同） + rt_size_t function_table_num;//函数表中的符号数量 + rt_size_t object_table_offset;//对象表的偏移地址 + rt_size_t object_table_num;//对象表中的符号数量 + rt_size_t general_symbol_table_offset;//一般符号（指代类型虽为NONE但带有GLOBAL的符号）表的偏移地址 + rt_size_t general_symbol_table_num;//一般符号表中的符号数量 + rt_size_t string_table_offset;//字符串表的偏移地址 + rt_size_t string_table_size;//字符串表的大小（字节为单位） + }os_symtab_header; + + //符号描述结构体 + typedef struct os_symtab_item + { + rt_size_t name_offset;//符号名称在字符串表中的偏移地址 + rt_size_t address;//该符号所代表的地址 + rt_size_t size;//该符号所代表的大小 + }os_symtab_item; + + os_symtab_item *find_symbol_table(rt_size_t symbol_table_addr,rt_size_t symbol_num,rt_size_t address); + const char *get_symbol_name(os_symtab_item *symbol); + void print_symbol(os_symtab_item *symbol,rt_size_t address); + void print_symbol_info(rt_size_t address,rt_bool_t function); + void print_stacktrace(rt_size_t epc,rt_size_t fp); + +#endif diff --git a/src/klibc/kerrno.c b/src/klibc/kerrno.c new file mode 100644 index 00000000000..4d83b133cba --- /dev/null +++ b/src/klibc/kerrno.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-09-22 Meco Man the first version + */ + +#include + +#define DBG_TAG "kernel.errno" +#ifdef RT_DEBUG_DEVICE +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_WARNING +#endif /* defined (RT_DEBUG_DEVICE) */ +#include + +/** + * @brief A global variable used to store the error code. + * + * This volatile static integer is used to store the most recent error code globally. + * Its volatile nature ensures that every read operation fetches the most current value, + * providing real-time error status across different parts of the program. + */ +static volatile int __rt_errno; + +/** + * @struct _errno_str_t + * @brief Structure for mapping error codes to corresponding error strings. + * + * This structure is used to create a mapping that associates an rt_err_t type error code + * with a corresponding error description string. + */ +struct _errno_str_t +{ + rt_err_t error; /**< Error code of type rt_err_t, representing different kinds of errors. */ + const char *str; /**< Pointer to the error description string. */ +}; + +/** + * @brief An array containing mappings of error codes to their corresponding error strings. + * + * This array uses the _errno_str_t structure to define several error codes and their + * corresponding error description strings. These mappings can be used at runtime + * to provide more readable error information. + */ +static struct _errno_str_t rt_errno_strs[] = +{ + {RT_EOK , "OK "}, /**< Operation successful. */ + {RT_ERROR , "ERROR "}, /**< General error. */ + {RT_ETIMEOUT, "ETIMOUT"}, /**< Operation timed out. */ + {RT_EFULL , "ERSFULL"}, /**< Resource is full. */ + {RT_EEMPTY , "ERSEPTY"}, /**< Resource is empty. */ + {RT_ENOMEM , "ENOMEM "}, /**< Not enough memory. */ + {RT_ENOSYS , "ENOSYS "}, /**< Function not implemented. */ + {RT_EBUSY , "EBUSY "}, /**< Resource is busy. */ + {RT_EIO , "EIO "}, /**< Input/output error. */ + {RT_EINTR , "EINTRPT"}, /**< Interrupted system call. */ + {RT_EINVAL , "EINVAL "}, /**< Invalid argument. */ + {RT_ENOENT , "ENOENT "}, /**< No such file or directory. */ + {RT_ENOSPC , "ENOSPC "}, /**< No space left on device. */ + {RT_EPERM , "EPERM "}, /**< Operation not permitted. */ + {RT_ETRAP , "ETRAP "}, /**< Trap error. */ +}; + +/** + * @brief This function return a pointer to a string that contains the + * message of error. + * + * @param error the errorno code + * @return a point to error message string + */ +const char *rt_strerror(rt_err_t error) +{ + int i = 0; + + if (error < 0) + error = -error; + + for (i = 0; i < sizeof(rt_errno_strs) / sizeof(rt_errno_strs[0]); i++) + { + if (rt_errno_strs[i].error == error) + return rt_errno_strs[i].str; + } + + return "EUNKNOW"; +} +RTM_EXPORT(rt_strerror); + +/** + * @brief This function gets the global errno for the current thread. + * + * @return errno + */ +rt_err_t rt_get_errno(void) +{ + rt_thread_t tid = RT_NULL; + + if (rt_interrupt_get_nest() != 0) + { + /* it's in interrupt context */ + return __rt_errno; + } + + tid = rt_thread_self(); + if (tid == RT_NULL) + { + return __rt_errno; + } + + return tid->error; +} +RTM_EXPORT(rt_get_errno); + +/** + * @brief This function sets the global errno for the current thread. + * + * @param error is the errno shall be set. + */ +void rt_set_errno(rt_err_t error) +{ + rt_thread_t tid = RT_NULL; + + if (rt_interrupt_get_nest() != 0) + { + /* it's in interrupt context */ + __rt_errno = error; + + return; + } + + tid = rt_thread_self(); + if (tid == RT_NULL) + { + __rt_errno = error; + + return; + } + + tid->error = error; +} +RTM_EXPORT(rt_set_errno); + +/** + * @brief This function returns the address of the current thread errno. + * + * @return The errno address. + */ +int *_rt_errno(void) +{ + rt_thread_t tid = RT_NULL; + + if (rt_interrupt_get_nest() != 0) + { + return (int *)&__rt_errno; + } + + tid = rt_thread_self(); + if (tid != RT_NULL) + { + return (int *) & (tid->error); + } + + return (int *)&__rt_errno; +} +RTM_EXPORT(_rt_errno); diff --git a/src/klibc/kstdio.c b/src/klibc/kstdio.c index 44ff758e92c..4bcd5d460ac 100644 --- a/src/klibc/kstdio.c +++ b/src/klibc/kstdio.c @@ -8,10 +8,7 @@ * 2024-03-10 Meco Man the first version */ -#include -#include -#include -#include +#include #define DBG_TAG "kernel.stdio" #ifdef RT_DEBUG_DEVICE @@ -287,11 +284,12 @@ static char *print_number(char *buf, return buf; } -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* GCC */ +#if (defined(__GNUC__) && !defined(__ARMCC_VERSION) /* GCC */) && (__GNUC__ >= 7) +/* Disable "-Wimplicit-fallthrough" below GNUC V7 */ #pragma GCC diagnostic push /* ignore warning: this statement may fall through */ #pragma GCC diagnostic ignored "-Wimplicit-fallthrough" -#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */ +#endif /* (defined(__GNUC__) && !defined(__ARMCC_VERSION)) && (__GNUC__ >= 7 */ /** * @brief This function will fill a formatted string to buffer. * @@ -617,9 +615,9 @@ rt_weak int rt_vsnprintf(char *buf, rt_size_t size, const char *fmt, va_list arg return str - buf; } RTM_EXPORT(rt_vsnprintf); -#if defined(__GNUC__) && !defined(__ARMCC_VERSION) /* GCC */ +#if (defined(__GNUC__) && !defined(__ARMCC_VERSION) /* GCC */) && (__GNUC__ >= 7) #pragma GCC diagnostic pop /* ignored "-Wimplicit-fallthrough" */ -#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */ +#endif /* (defined(__GNUC__) && !defined(__ARMCC_VERSION)) && (__GNUC__ >= 7 */ /** * @brief This function will fill a formatted string to buffer. @@ -683,155 +681,3 @@ int rt_sprintf(char *buf, const char *format, ...) return n; } RTM_EXPORT(rt_sprintf); - -/* errno functions */ - -/** - * @brief A global variable used to store the error code. - * - * This volatile static integer is used to store the most recent error code globally. - * Its volatile nature ensures that every read operation fetches the most current value, - * providing real-time error status across different parts of the program. - */ -static volatile int __rt_errno; - -/** - * @struct _errno_str_t - * @brief Structure for mapping error codes to corresponding error strings. - * - * This structure is used to create a mapping that associates an rt_err_t type error code - * with a corresponding error description string. - */ -struct _errno_str_t -{ - rt_err_t error; /**< Error code of type rt_err_t, representing different kinds of errors. */ - const char *str; /**< Pointer to the error description string. */ -}; - -/** - * @brief An array containing mappings of error codes to their corresponding error strings. - * - * This array uses the _errno_str_t structure to define several error codes and their - * corresponding error description strings. These mappings can be used at runtime - * to provide more readable error information. - */ -static struct _errno_str_t rt_errno_strs[] = -{ - {RT_EOK , "OK "}, /**< Operation successful. */ - {RT_ERROR , "ERROR "}, /**< General error. */ - {RT_ETIMEOUT, "ETIMOUT"}, /**< Operation timed out. */ - {RT_EFULL , "ERSFULL"}, /**< Resource is full. */ - {RT_EEMPTY , "ERSEPTY"}, /**< Resource is empty. */ - {RT_ENOMEM , "ENOMEM "}, /**< Not enough memory. */ - {RT_ENOSYS , "ENOSYS "}, /**< Function not implemented. */ - {RT_EBUSY , "EBUSY "}, /**< Resource is busy. */ - {RT_EIO , "EIO "}, /**< Input/output error. */ - {RT_EINTR , "EINTRPT"}, /**< Interrupted system call. */ - {RT_EINVAL , "EINVAL "}, /**< Invalid argument. */ - {RT_ENOENT , "ENOENT "}, /**< No such file or directory. */ - {RT_ENOSPC , "ENOSPC "}, /**< No space left on device. */ - {RT_EPERM , "EPERM "}, /**< Operation not permitted. */ - {RT_ETRAP , "ETRAP "}, /**< Trap error. */ -}; - -/** - * @brief This function return a pointer to a string that contains the - * message of error. - * - * @param error the errorno code - * @return a point to error message string - */ -const char *rt_strerror(rt_err_t error) -{ - int i = 0; - - if (error < 0) - error = -error; - - for (i = 0; i < sizeof(rt_errno_strs) / sizeof(rt_errno_strs[0]); i++) - { - if (rt_errno_strs[i].error == error) - return rt_errno_strs[i].str; - } - - return "EUNKNOW"; -} -RTM_EXPORT(rt_strerror); - -/** - * @brief This function gets the global errno for the current thread. - * - * @return errno - */ -rt_err_t rt_get_errno(void) -{ - rt_thread_t tid = RT_NULL; - - if (rt_interrupt_get_nest() != 0) - { - /* it's in interrupt context */ - return __rt_errno; - } - - tid = rt_thread_self(); - if (tid == RT_NULL) - { - return __rt_errno; - } - - return tid->error; -} -RTM_EXPORT(rt_get_errno); - -/** - * @brief This function sets the global errno for the current thread. - * - * @param error is the errno shall be set. - */ -void rt_set_errno(rt_err_t error) -{ - rt_thread_t tid = RT_NULL; - - if (rt_interrupt_get_nest() != 0) - { - /* it's in interrupt context */ - __rt_errno = error; - - return; - } - - tid = rt_thread_self(); - if (tid == RT_NULL) - { - __rt_errno = error; - - return; - } - - tid->error = error; -} -RTM_EXPORT(rt_set_errno); - -/** - * @brief This function returns the address of the current thread errno. - * - * @return The errno address. - */ -int *_rt_errno(void) -{ - rt_thread_t tid = RT_NULL; - - if (rt_interrupt_get_nest() != 0) - { - return (int *)&__rt_errno; - } - - tid = rt_thread_self(); - if (tid != RT_NULL) - { - return (int *) & (tid->error); - } - - return (int *)&__rt_errno; -} -RTM_EXPORT(_rt_errno); diff --git a/src/klibc/kstring.c b/src/klibc/kstring.c index b3fb3b00299..562c3f7ccdb 100644 --- a/src/klibc/kstring.c +++ b/src/klibc/kstring.c @@ -8,10 +8,7 @@ * 2024-03-10 Meco Man the first version */ -#include -#include -#include -#include +#include #ifdef RT_KLIBC_USING_STDLIB #include #endif /* RT_KLIBC_USING_STDLIB */ diff --git a/tools/ci/toolchain.sh b/tools/ci/toolchain.sh new file mode 100755 index 00000000000..24293b32b7f --- /dev/null +++ b/tools/ci/toolchain.sh @@ -0,0 +1,87 @@ +#!/bin/bash + +declare -A download_urls=( +["arm-none-eabi-gcc"]="https://github.com/RT-Thread/toolchains-ci/releases/download/v1.3/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2" +["mips-sde-elf-gcc"]="https://github.com/RT-Thread/toolchains-ci/releases/download/v1.1/mips-2016.05-7-mips-sde-elf-i686-pc-linux-gnu.tar.bz2" +["aarch64-none-elf-gcc"]="https://github.com/RT-Thread/toolchains-ci/releases/download/v1.6/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz" +["riscv64-unknown-elf-gcc"]="https://github.com/RT-Thread/toolchains-ci/releases/download/v1.4/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz" +["riscv32-unknown-elf-gcc"]="https://github.com/hpmicro/riscv-gnu-toolchain/releases/download/2022.05.15/riscv32-unknown-elf-newlib-multilib_2022.05.15_linux.tar.gz" +["riscv-none-embed-gcc"]="https://github.com/RT-Thread/toolchains-ci/releases/download/v1.5/xpack-riscv-none-embed-gcc-8.3.0-2.3-linux-x64.tar.gz" +["riscv32-esp-elf-gcc"]="https://github.com/espressif/crosstool-NG/releases/download/esp-2022r1-RC1/riscv32-esp-elf-gcc11_2_0-esp-2022r1-RC1-linux-amd64.tar.xz" +["clang"]="https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-16.0.0/LLVMEmbeddedToolchainForArm-16.0.0-Linux-x86_64.tar.gz" + +) + +show_help() { + echo "Available toolchains:" + for key in "${!download_urls[@]}"; do + echo " - $key" + done +} + +extract_file() { + local file_name=$1 + local destination=$2 + echo "Extracting $file_name to $destination..." + case "$file_name" in + *.tar.bz2) tar -xjf "$file_name" -C "$destination" --strip-components=1;; + *.tar.gz) tar -xzf "$file_name" -C "$destination" --strip-components=1;; + *.tar.xz) tar -xJf "$file_name" -C "$destination" --strip-components=1;; + *) echo "Unsupported file format: $file_name"; exit 1;; + esac + echo "Extracted to $destination" +} + + +install_toolchain() { + local toolchain_name=$1 + local url="${download_urls[$toolchain_name]}" + if [ -z "$url" ]; then + echo "Toolchain not found." + exit 1 + fi + local file_name=$(basename "$url") + echo "Downloading $file_name..." + wget -q "$url" + echo "Extracting $file_name..." + + local target_dir="/opt/$toolchain_name" + echo "target_dir $target_dir..." + mkdir -p "$target_dir" + extract_file "$file_name" "$target_dir" + + rm $file_name + + echo "Installed: $target_dir" + + local toolchain_bin="$target_dir/bin" + if [[ ":$PATH:" != *":$toolchain_bin:"* ]]; then + echo "Adding $toolchain_bin to PATH..." + export PATH="$PATH:$toolchain_bin" + echo "export PATH=\$PATH:$toolchain_bin" >> ~/.bashrc + fi + #need source toolchain.sh or source ~/.bashrc to work + + #local toolchain_exec=$(find "$toolchain_bin" -type f -executable | head -n 1) + local toolchain_exec=$(which "$toolchain_name") + if [ -x "$toolchain_exec" ]; then + echo "Testing executable: $toolchain_exec" + $toolchain_exec --version + else + echo "No executable found in $toolchain_bin" + fi +} + +if [[ $# -eq 1 ]]; then + if [[ "$1" == "help" ]]; then + show_help + elif [ "$1" == "all" ]; then + for toolchain in "${!download_urls[@]}"; do + install_toolchain "$toolchain" + done + else + install_toolchain "$1" + fi +else + show_help +fi