From 8a53e6d63947a0ee0c60da53d322c75e0f5048cc Mon Sep 17 00:00:00 2001
From: heyuanjie87 <943313837@qq.com>
Date: Fri, 20 Sep 2024 10:43:13 +0800
Subject: [PATCH] =?UTF-8?q?=E5=88=A0=E9=99=A4=E5=A4=9A=E4=BD=99=E7=A9=BA?=
 =?UTF-8?q?=E6=A0=BC?=
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---
 libcpu/risc-v/t-head/c908/opcode.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/libcpu/risc-v/t-head/c908/opcode.h b/libcpu/risc-v/t-head/c908/opcode.h
index 2952b5465da..90b002dc4eb 100644
--- a/libcpu/risc-v/t-head/c908/opcode.h
+++ b/libcpu/risc-v/t-head/c908/opcode.h
@@ -14,7 +14,7 @@
 /**
  * @brief binary opcode pseudo operations
  * Used to bypass toolchain restriction on extension ISA
- * 
+ *
  * WARNING: Xuantie ISAs are not compatible to each other in opcode.
  * It's painful to port this file, and should be really careful.
  */
@@ -23,9 +23,9 @@
  * @brief RISC-V instruction formats
  */
 
-/** 
+/**
  * R type: .insn r opcode6, func3, func7, rd, rs1, rs2
- * 
+ *
  * +-------+-----+-----+-------+----+---------+
  * | func7 | rs2 | rs1 | func3 | rd | opcode6 |
  * +-------+-----+-----+-------+----+---------+