Update README.md

Author: shivanishah269

Diff for: README.md

@@ -21,9 +21,7 @@ This repository contains all the information needed to build your RISC-V pipelin
   - [Pipelinig the CPU](#pipelining-the-cpu)
   - [Load and store instructions and memory](#load-and-store-instructions-and-memory)
   - [Completing the RISC-V CPU](#completing-the-risc-v-cpu)
-- [Contributors](#contributors)
 - [Acknowledgements](#acknowledgements)
-- [Contact Information](#contact-information)
 
 # Introduction to RISC-V ISA 
 
@@ -267,14 +265,8 @@ Below is final Snapshot of Complete Pipelined RISC-V CPU.
 
 ![Final](Images/Final.png)
 
-# Contributors
-
 # Acknowledgements
 - [Kunal Ghosh](https://github.com/kunalg123), Co-founder, VSD Corp. Pvt. Ltd.
 - [Steve Hoover](https://github.com/stevehoover), Founder, Redwood EDA
 - [Shivam Potdar](https://github.com/shivampotdar), GSoC 2020 @fossi-foundation
 - [Vineet Jain](https://github.com/vineetjain07), GSoC 2020 @fossi-foundation
-
-
-# Contact Information
-