diff --git a/qiskit/circuit/quantumcircuit.py b/qiskit/circuit/quantumcircuit.py index 868da61b95ab..7e1994a45368 100644 --- a/qiskit/circuit/quantumcircuit.py +++ b/qiskit/circuit/quantumcircuit.py @@ -3282,9 +3282,9 @@ def draw( will take less vertical room. Default is ``medium``. Only used by the ``text`` output, will be silently ignored otherwise. idle_wires: Include idle wires (wires with no circuit elements) - in output visualization. Default is ``True`` unless the + in output visualization. Default is ``False`` unless the user config file (usually ``~/.qiskit/settings.conf``) has an - alternative value set. For example, ``circuit_idle_wires = False``. + alternative value set. For example, ``circuit_idle_wires = True``. with_layout: Include layout information, with labels on the physical layout. Default is ``True``. fold: Sets pagination. It can be disabled using -1. In ``text``, diff --git a/qiskit/visualization/circuit/circuit_visualization.py b/qiskit/visualization/circuit/circuit_visualization.py index dc01e69dc41d..339f093cae75 100644 --- a/qiskit/visualization/circuit/circuit_visualization.py +++ b/qiskit/visualization/circuit/circuit_visualization.py @@ -142,9 +142,9 @@ def circuit_drawer( will take less vertical room. Default is ``medium``. Only used by the ``text`` output, will be silently ignored otherwise. idle_wires: Include idle wires (wires with no circuit elements) - in output visualization. Default is ``True`` unless the + in output visualization. Default is ``False`` unless the user config file (usually ``~/.qiskit/settings.conf``) has an - alternative value set. For example, ``circuit_idle_wires = False``. + alternative value set. For example, ``circuit_idle_wires = True``. with_layout: Include layout information, with labels on the physical layout. Default is ``True``. fold: Sets pagination. It can be disabled using -1. In ``text``, @@ -205,7 +205,7 @@ def circuit_drawer( # Get default from config file else use text default_output = "text" default_reverse_bits = False - default_idle_wires = config.get("circuit_idle_wires", True) + default_idle_wires = config.get("circuit_idle_wires", False) if config: default_output = config.get("circuit_drawer", "text") if default_output == "auto": @@ -368,7 +368,7 @@ def _text_circuit_drawer( plot_barriers=True, justify=None, vertical_compression="high", - idle_wires=True, + idle_wires=False, with_layout=True, fold=None, initial_state=True, @@ -388,7 +388,7 @@ def _text_circuit_drawer( the circuit should be justified. vertical_compression (string): `high`, `medium`, or `low`. It merges the lines so the drawing will take less vertical room. Default is `high`. - idle_wires (bool): Include idle wires. Default is True. + idle_wires (bool): Include idle wires. Default is False. with_layout (bool): Include layout information with labels on the physical layout. Default: True fold (int): Optional. Breaks the circuit drawing to this length. This @@ -459,7 +459,7 @@ def _latex_circuit_drawer( plot_barriers=True, reverse_bits=False, justify=None, - idle_wires=True, + idle_wires=False, with_layout=True, initial_state=False, cregbundle=None, @@ -480,7 +480,7 @@ def _latex_circuit_drawer( circuit. Defaults to True. justify (str) : `left`, `right` or `none`. Defaults to `left`. Says how the circuit should be justified. - idle_wires (bool): Include idle wires. Default is True. + idle_wires (bool): Include idle wires. Default is False. with_layout (bool): Include layout information, with labels on the physical layout. Default: True initial_state (bool): Optional. Adds |0> in the beginning of the line. @@ -578,7 +578,7 @@ def _generate_latex_source( reverse_bits=False, plot_barriers=True, justify=None, - idle_wires=True, + idle_wires=False, with_layout=True, initial_state=False, cregbundle=None, @@ -597,7 +597,7 @@ def _generate_latex_source( circuit. Defaults to True. justify (str) : `left`, `right` or `none`. Defaults to `left`. Says how the circuit should be justified. - idle_wires (bool): Include idle wires. Default is True. + idle_wires (bool): Include idle wires. Default is False. with_layout (bool): Include layout information, with labels on the physical layout. Default: True initial_state (bool): Optional. Adds |0> in the beginning of the line. @@ -651,7 +651,7 @@ def _matplotlib_circuit_drawer( plot_barriers=True, reverse_bits=False, justify=None, - idle_wires=True, + idle_wires=False, with_layout=True, fold=None, ax=None, @@ -675,7 +675,7 @@ def _matplotlib_circuit_drawer( circuit. Defaults to True. justify (str): `left`, `right` or `none`. Defaults to `left`. Says how the circuit should be justified. - idle_wires (bool): Include idle wires. Default is True. + idle_wires (bool): Include idle wires. Default is False. with_layout (bool): Include layout information, with labels on the physical layout. Default: True. fold (int): Number of vertical layers allowed before folding. Default is 25. diff --git a/releasenotes/notes/closes_12361-d3ea2c442a4a74a7.yaml b/releasenotes/notes/closes_12361-d3ea2c442a4a74a7.yaml new file mode 100644 index 000000000000..e3cd2dfbe584 --- /dev/null +++ b/releasenotes/notes/closes_12361-d3ea2c442a4a74a7.yaml @@ -0,0 +1,4 @@ +--- +upgrade_visualization: + - | + The default for the parameter ``idle_wires`` changed to ``False`` in all the circuit drawers. If you still want to see wires without instructions, set ``idle_wires=True`` explicitly. diff --git a/test/python/visualization/test_circuit_drawer.py b/test/python/visualization/test_circuit_drawer.py index 9eb4e3ad2c88..5e88c782decf 100644 --- a/test/python/visualization/test_circuit_drawer.py +++ b/test/python/visualization/test_circuit_drawer.py @@ -171,7 +171,9 @@ def test_wire_order(self): " ", ] ) - result = visualization.circuit_drawer(circuit, output="text", wire_order=[2, 3, 0, 1]) + result = visualization.circuit_drawer( + circuit, output="text", idle_wires=True, wire_order=[2, 3, 0, 1] + ) self.assertEqual(result.__str__(), expected) def test_wire_order_cregbundle(self): @@ -205,7 +207,7 @@ def test_wire_order_cregbundle(self): ] ) result = visualization.circuit_drawer( - circuit, output="text", wire_order=[2, 3, 0, 1], cregbundle=True + circuit, output="text", wire_order=[2, 3, 0, 1], cregbundle=True, idle_wires=True ) self.assertEqual(result.__str__(), expected) @@ -240,7 +242,9 @@ def test_reverse_bits(self): " ", ] ) - result = visualization.circuit_drawer(circuit, output="text", reverse_bits=True) + result = visualization.circuit_drawer( + circuit, output="text", reverse_bits=True, idle_wires=True + ) self.assertEqual(result.__str__(), expected) def test_warning_for_bad_justify_argument(self): @@ -282,7 +286,7 @@ def test_no_explict_cregbundle(self): " ", ] ) - result = circuit.draw("text") + result = circuit.draw("text", idle_wires=True) self.assertEqual(result.__str__(), expected) # Extra tests that no cregbundle (or any other) warning is raised with the default settings # for the other drawers, if they're available to test. diff --git a/test/python/visualization/test_circuit_latex.py b/test/python/visualization/test_circuit_latex.py index f4cce43881fb..fb869204a4a6 100644 --- a/test/python/visualization/test_circuit_latex.py +++ b/test/python/visualization/test_circuit_latex.py @@ -53,7 +53,7 @@ def test_empty_circuit(self): """Test draw an empty circuit""" filename = self._get_resource_path("test_latex_empty.tex") circuit = QuantumCircuit(1) - circuit_drawer(circuit, filename=filename, output="latex_source") + circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True) self.assertEqualToReference(filename) @@ -76,8 +76,12 @@ def test_multi_underscore_reg_names(self): c_reg1 = ClassicalRegister(1, "c1_re_g__g") c_reg3 = ClassicalRegister(3, "c3_re_g__g") circuit = QuantumCircuit(q_reg1, q_reg3, c_reg1, c_reg3) - circuit_drawer(circuit, cregbundle=True, filename=filename1, output="latex_source") - circuit_drawer(circuit, cregbundle=False, filename=filename2, output="latex_source") + circuit_drawer( + circuit, cregbundle=True, filename=filename1, output="latex_source", idle_wires=True + ) + circuit_drawer( + circuit, cregbundle=False, filename=filename2, output="latex_source", idle_wires=True + ) self.assertEqualToReference(filename1) self.assertEqualToReference(filename2) @@ -101,9 +105,9 @@ def test_4597(self): circuit = QuantumCircuit(qr, cr) with self.assertWarns(DeprecationWarning): circuit.x(qr[2]).c_if(cr, 2) - circuit.draw(output="latex_source", cregbundle=True) + circuit.draw(output="latex_source", cregbundle=True, idle_wires=True) - circuit_drawer(circuit, filename=filename, output="latex_source") + circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True) self.assertEqualToReference(filename) @@ -174,7 +178,7 @@ def test_no_ops(self): See https://github.com/Qiskit/qiskit-terra/issues/5393""" filename = self._get_resource_path("test_latex_no_ops.tex") circuit = QuantumCircuit(2, 3) - circuit_drawer(circuit, filename=filename, output="latex_source") + circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True) self.assertEqualToReference(filename) @@ -195,7 +199,7 @@ def test_long_name(self): circuit.h(qr) circuit.h(qr) - circuit_drawer(circuit, filename=filename, output="latex_source") + circuit_drawer(circuit, filename=filename, idle_wires=True, output="latex_source") self.assertEqualToReference(filename) @@ -230,7 +234,7 @@ def test_plot_partial_barrier(self): circuit.barrier(0) circuit.h(q[0]) - circuit_drawer(circuit, filename=filename, output="latex_source") + circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True) self.assertEqualToReference(filename) @@ -253,10 +257,14 @@ def test_plot_barriers(self): circuit.h(q[1]) # check the barriers plot properly when plot_barriers= True - circuit_drawer(circuit, filename=filename1, output="latex_source", plot_barriers=True) + circuit_drawer( + circuit, filename=filename1, output="latex_source", plot_barriers=True, idle_wires=True + ) self.assertEqualToReference(filename1) - circuit_drawer(circuit, filename=filename2, output="latex_source", plot_barriers=False) + circuit_drawer( + circuit, filename=filename2, output="latex_source", plot_barriers=False, idle_wires=True + ) self.assertEqualToReference(filename2) @@ -270,7 +278,7 @@ def test_no_barriers_false(self): circuit.h(q1[0]) circuit.h(q1[1]) - circuit_drawer(circuit, filename=filename, output="latex_source") + circuit_drawer(circuit, filename=filename, idle_wires=True, output="latex_source") self.assertEqualToReference(filename) @@ -388,7 +396,12 @@ def test_creg_initial(self): circuit.x(1) circuit_drawer( - circuit, filename=filename1, output="latex_source", cregbundle=True, initial_state=True + circuit, + filename=filename1, + output="latex_source", + cregbundle=True, + initial_state=True, + idle_wires=True, ) self.assertEqualToReference(filename1) @@ -398,6 +411,7 @@ def test_creg_initial(self): output="latex_source", cregbundle=False, initial_state=False, + idle_wires=True, ) self.assertEqualToReference(filename2) @@ -503,7 +517,7 @@ def test_partial_layout(self): seed_transpiler=0, ) - circuit_drawer(transpiled, filename=filename, output="latex_source") + circuit_drawer(transpiled, filename=filename, output="latex_source", idle_wires=True) self.assertEqualToReference(filename) @@ -592,7 +606,7 @@ def test_inst_with_cbits(self): cr = ClassicalRegister(4, "cr") circuit = QuantumCircuit(qr, cr) circuit.append(inst, [qr[1], qr[2]], [cr[2], cr[1]]) - circuit_drawer(circuit, filename=filename, output="latex_source") + circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True) self.assertEqualToReference(filename) @@ -633,7 +647,7 @@ def test_registerless_one_bit(self): qry = QuantumRegister(1, "qry") crx = ClassicalRegister(2, "crx") circuit = QuantumCircuit(qrx, [Qubit(), Qubit()], qry, [Clbit(), Clbit()], crx) - circuit_drawer(circuit, filename=filename, output="latex_source") + circuit_drawer(circuit, filename=filename, output="latex_source", idle_wires=True) self.assertEqualToReference(filename) @@ -668,8 +682,12 @@ def test_measures_with_conditions_with_bits(self): with self.assertWarns(DeprecationWarning): circuit.x(0).c_if(crx[1], 0) circuit.measure(0, bits[3]) - circuit_drawer(circuit, cregbundle=False, filename=filename1, output="latex_source") - circuit_drawer(circuit, cregbundle=True, filename=filename2, output="latex_source") + circuit_drawer( + circuit, cregbundle=False, filename=filename1, output="latex_source", idle_wires=True + ) + circuit_drawer( + circuit, cregbundle=True, filename=filename2, output="latex_source", idle_wires=True + ) self.assertEqualToReference(filename1) self.assertEqualToReference(filename2) @@ -683,7 +701,12 @@ def test_conditions_with_bits_reverse(self): with self.assertWarns(DeprecationWarning): circuit.x(0).c_if(bits[3], 0) circuit_drawer( - circuit, cregbundle=False, reverse_bits=True, filename=filename, output="latex_source" + circuit, + cregbundle=False, + reverse_bits=True, + filename=filename, + output="latex_source", + idle_wires=True, ) self.assertEqualToReference(filename) @@ -695,7 +718,9 @@ def test_sidetext_with_condition(self): circuit = QuantumCircuit(qr, cr) with self.assertWarns(DeprecationWarning): circuit.append(CPhaseGate(pi / 2), [qr[0], qr[1]]).c_if(cr[1], 1) - circuit_drawer(circuit, cregbundle=False, filename=filename, output="latex_source") + circuit_drawer( + circuit, cregbundle=False, filename=filename, output="latex_source", idle_wires=True + ) self.assertEqualToReference(filename) def test_idle_wires_barrier(self): @@ -725,6 +750,7 @@ def test_wire_order(self): wire_order=[2, 1, 3, 0, 6, 8, 9, 5, 4, 7], filename=filename, output="latex_source", + idle_wires=True, ) self.assertEqualToReference(filename) diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py index 6ae4adb42b8b..9b9cae48f11f 100644 --- a/test/python/visualization/test_circuit_text_drawer.py +++ b/test/python/visualization/test_circuit_text_drawer.py @@ -320,7 +320,10 @@ def test_text_measure_2(self): cr2 = ClassicalRegister(2, "c2") circuit = QuantumCircuit(qr1, qr2, cr1, cr2) circuit.measure(qr2, cr2) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_text_measure_2_reverse_bits(self): """The measure operator, using some registers, with reverse_bits""" @@ -349,7 +352,11 @@ def test_text_measure_2_reverse_bits(self): circuit = QuantumCircuit(qr1, qr2, cr1, cr2) circuit.measure(qr2, cr2) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, reverse_bits=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, reverse_bits=True, idle_wires=True + ) + ), expected, ) @@ -398,6 +405,7 @@ def test_wire_order(self): initial_state=True, cregbundle=False, wire_order=[2, 1, 3, 0, 6, 8, 9, 5, 4, 7], + idle_wires=True, ) ), expected, @@ -528,12 +536,7 @@ def test_text_idle_wires_read_from_config(self): circuit.h(qr2[0]) self.assertEqual( - str( - circuit_drawer( - circuit, - output="text", - ) - ), + str(circuit_drawer(circuit, output="text", idle_wires=True)), expected_with, ) @@ -848,7 +851,10 @@ def test_text_cu1_condition(self): circuit = QuantumCircuit(qr, cr) with self.assertWarns(DeprecationWarning): circuit.append(CU1Gate(pi / 2), [qr[0], qr[1]]).c_if(cr[1], 1) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=False)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=False, idle_wires=True)), + expected, + ) def test_text_rzz_condition(self): """Test rzz with condition""" @@ -870,7 +876,10 @@ def test_text_rzz_condition(self): circuit = QuantumCircuit(qr, cr) with self.assertWarns(DeprecationWarning): circuit.append(RZZGate(pi / 2), [qr[0], qr[1]]).c_if(cr[1], 1) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=False)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=False, idle_wires=True)), + expected, + ) def test_text_cp_condition(self): """Test cp with condition""" @@ -892,7 +901,10 @@ def test_text_cp_condition(self): circuit = QuantumCircuit(qr, cr) with self.assertWarns(DeprecationWarning): circuit.append(CPhaseGate(pi / 2), [qr[0], qr[1]]).c_if(cr[1], 1) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=False)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=False, idle_wires=True)), + expected, + ) def test_text_cu1_reverse_bits(self): """cu1 drawing with reverse_bits""" @@ -957,7 +969,10 @@ def test_text_reset(self): circuit = QuantumCircuit(qr1, qr2) circuit.reset(qr1) circuit.reset(qr2[1]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_text_single_gate(self): """Single Qbit gate drawing.""" @@ -980,7 +995,10 @@ def test_text_single_gate(self): circuit = QuantumCircuit(qr1, qr2) circuit.h(qr1) circuit.h(qr2[1]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_text_id(self): """Id drawing.""" @@ -1003,7 +1021,10 @@ def test_text_id(self): circuit = QuantumCircuit(qr1, qr2) circuit.id(qr1) circuit.id(qr2[1]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_text_barrier(self): """Barrier drawing.""" @@ -1026,7 +1047,10 @@ def test_text_barrier(self): circuit = QuantumCircuit(qr1, qr2) circuit.barrier(qr1) circuit.barrier(qr2[1]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_text_no_barriers(self): """Drawing without plotbarriers.""" @@ -1385,7 +1409,10 @@ def test_text_box_length(self): circuit.h(qr[0]) circuit.h(qr[0]) circuit.rz(0.0000001, qr[2]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_text_spacing_2378(self): """Small gates in the same layer as long gates. @@ -1616,7 +1643,11 @@ def test_2Qgate_nottogether(self): circuit.append(my_gate2, [qr[0], qr[2]]) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, reverse_bits=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, reverse_bits=True, idle_wires=True + ) + ), expected, ) @@ -1643,7 +1674,11 @@ def test_2Qgate_nottogether_across_4(self): circuit.append(my_gate2, [qr[0], qr[3]]) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, reverse_bits=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, reverse_bits=True, idle_wires=True + ) + ), expected, ) @@ -1668,7 +1703,9 @@ def test_unitary_nottogether_across_4(self): qc.append(random_unitary(4, seed=42), [qr[0], qr[3]]) - self.assertEqual(str(circuit_drawer(qc, initial_state=True, output="text")), expected) + self.assertEqual( + str(circuit_drawer(qc, initial_state=True, output="text", idle_wires=True)), expected + ) def test_kraus(self): """Test Kraus. @@ -2413,6 +2450,7 @@ def test_text_conditional_reverse_bits_true(self): cregbundle=False, reverse_bits=True, vertical_compression="low", + idle_wires=True, ) ), expected, @@ -2465,6 +2503,7 @@ def test_text_conditional_reverse_bits_false(self): vertical_compression="low", cregbundle=False, reverse_bits=False, + idle_wires=True, ) ), expected, @@ -2695,6 +2734,7 @@ def test_text_barrier_med_compress_1(self): initial_state=True, vertical_compression="medium", cregbundle=False, + idle_wires=True, ) ), expected, @@ -2731,6 +2771,7 @@ def test_text_barrier_med_compress_2(self): initial_state=True, vertical_compression="medium", cregbundle=False, + idle_wires=True, ) ), expected, @@ -3142,7 +3183,11 @@ def test_text_conditional_cz_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), expected, ) @@ -3169,7 +3214,11 @@ def test_text_conditional_cz(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -3196,7 +3245,11 @@ def test_text_conditional_cx_ct_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), expected, ) @@ -3223,7 +3276,11 @@ def test_text_conditional_cx_ct(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -3250,7 +3307,11 @@ def test_text_conditional_cx_tc_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), expected, ) @@ -3277,7 +3338,11 @@ def test_text_conditional_cx_tc(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -3304,7 +3369,11 @@ def test_text_conditional_cu3_ct_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), expected, ) @@ -3331,7 +3400,11 @@ def test_text_conditional_cu3_ct(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -3358,7 +3431,11 @@ def test_text_conditional_cu3_tc_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), expected, ) @@ -3385,7 +3462,11 @@ def test_text_conditional_cu3_tc(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -3414,7 +3495,11 @@ def test_text_conditional_ccx_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), expected, ) @@ -3443,7 +3528,11 @@ def test_text_conditional_ccx(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -3530,7 +3619,11 @@ def test_text_conditional_h_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), expected, ) @@ -3555,7 +3648,11 @@ def test_text_conditional_h(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -3582,7 +3679,11 @@ def test_text_conditional_swap_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), expected, ) @@ -3609,7 +3710,11 @@ def test_text_conditional_swap(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -3638,7 +3743,11 @@ def test_text_conditional_cswap_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), expected, ) @@ -3667,7 +3776,11 @@ def test_text_conditional_cswap(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -3693,7 +3806,11 @@ def test_conditional_reset_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=True)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), expected, ) @@ -3719,7 +3836,11 @@ def test_conditional_reset(self): ) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -3747,7 +3868,12 @@ def test_conditional_multiplexer_cregbundle(self): ) self.assertEqual( - str(circuit_drawer(qc, output="text", initial_state=True, cregbundle=True)), expected + str( + circuit_drawer( + qc, output="text", initial_state=True, cregbundle=True, idle_wires=True + ) + ), + expected, ) def test_conditional_multiplexer(self): @@ -3774,7 +3900,12 @@ def test_conditional_multiplexer(self): ) self.assertEqual( - str(circuit_drawer(qc, output="text", initial_state=True, cregbundle=False)), expected + str( + circuit_drawer( + qc, output="text", initial_state=True, cregbundle=False, idle_wires=True + ) + ), + expected, ) def test_text_conditional_measure_cregbundle(self): @@ -3938,7 +4069,11 @@ def test_text_condition_measure_bits_true(self): ] ) self.assertEqual( - str(circuit_drawer(circuit, output="text", cregbundle=True, initial_state=False)), + str( + circuit_drawer( + circuit, output="text", cregbundle=True, initial_state=False, idle_wires=True + ) + ), expected, ) @@ -3979,7 +4114,11 @@ def test_text_condition_measure_bits_false(self): ] ) self.assertEqual( - str(circuit_drawer(circuit, output="text", cregbundle=False, initial_state=False)), + str( + circuit_drawer( + circuit, output="text", cregbundle=False, initial_state=False, idle_wires=True + ) + ), expected, ) @@ -4051,7 +4190,12 @@ def test_text_conditional_reverse_bits_2(self): self.assertEqual( str( circuit_drawer( - circuit, output="text", initial_state=True, cregbundle=False, reverse_bits=True + circuit, + output="text", + initial_state=True, + cregbundle=False, + reverse_bits=True, + idle_wires=True, ) ), expected, @@ -4089,7 +4233,12 @@ def test_text_condition_bits_reverse(self): self.assertEqual( str( circuit_drawer( - circuit, output="text", cregbundle=True, initial_state=False, reverse_bits=True + circuit, + output="text", + cregbundle=True, + initial_state=False, + reverse_bits=True, + idle_wires=True, ) ), expected, @@ -4373,7 +4522,10 @@ def test_text_4q_2c(self): cr6 = ClassicalRegister(6, "c") circuit = QuantumCircuit(qr6, cr6) circuit.append(inst, qr6[1:5], cr6[1:3]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_text_2q_1c(self): """Test q0-c0 in q0-q1-c0 @@ -4396,7 +4548,10 @@ def test_text_2q_1c(self): inst = QuantumCircuit(1, 1, name="Name").to_instruction() circuit.append(inst, [qr[0]], [cr[0]]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_text_3q_3c_qlabels_inverted(self): """Test q3-q0-q1-c0-c1-c_10 in q0-q1-q2-q3-c0-c1-c2-c_10-c_11 @@ -4432,7 +4587,10 @@ def test_text_3q_3c_qlabels_inverted(self): inst = QuantumCircuit(3, 3, name="Name").to_instruction() circuit.append(inst, [qr[3], qr[0], qr[1]], [cr[0], cr[1], cr1[0]]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_text_3q_3c_clabels_inverted(self): """Test q0-q1-q3-c_11-c0-c_10 in q0-q1-q2-q3-c0-c1-c2-c_10-c_11 @@ -4468,7 +4626,10 @@ def test_text_3q_3c_clabels_inverted(self): inst = QuantumCircuit(3, 3, name="Name").to_instruction() circuit.append(inst, [qr[0], qr[1], qr[3]], [cr1[1], cr[0], cr1[0]]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_text_3q_3c_qclabels_inverted(self): """Test q3-q1-q2-c_11-c0-c_10 in q0-q1-q2-q3-c0-c1-c2-c_10-c_11 @@ -4504,7 +4665,10 @@ def test_text_3q_3c_qclabels_inverted(self): inst = QuantumCircuit(3, 3, name="Name").to_instruction() circuit.append(inst, [qr[3], qr[1], qr[2]], [cr1[1], cr[0], cr1[0]]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) class TestTextDrawerAppendedLargeInstructions(QiskitTestCase): @@ -5414,7 +5578,10 @@ def test_open_out_of_order(self): circuit = QuantumCircuit(qr) circuit.append(XGate().control(3, ctrl_state="101"), [qr[0], qr[3], qr[1], qr[2]]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) class TestTextWithLayout(QiskitTestCase): @@ -5436,7 +5603,10 @@ def test_with_no_layout(self): qr = QuantumRegister(3, "q") circuit = QuantumCircuit(qr) circuit.h(qr[1]) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_mixed_layout(self): """With a mixed layout.""" @@ -5463,7 +5633,12 @@ def test_mixed_layout(self): circuit_with_layout = pass_(circuit) self.assertEqual( - str(circuit_drawer(circuit_with_layout, output="text", initial_state=True)), expected + str( + circuit_drawer( + circuit_with_layout, output="text", initial_state=True, idle_wires=True + ) + ), + expected, ) def test_partial_layout(self): @@ -5493,7 +5668,10 @@ def test_partial_layout(self): ) circuit._layout.initial_layout.add_register(qr) - self.assertEqual(str(circuit_drawer(circuit, output="text", initial_state=True)), expected) + self.assertEqual( + str(circuit_drawer(circuit, output="text", initial_state=True, idle_wires=True)), + expected, + ) def test_with_classical_regs(self): """Involving classical registers""" @@ -5525,7 +5703,12 @@ def test_with_classical_regs(self): circuit_with_layout = pass_(circuit) self.assertEqual( - str(circuit_drawer(circuit_with_layout, output="text", initial_state=True)), expected + str( + circuit_drawer( + circuit_with_layout, output="text", initial_state=True, idle_wires=True + ) + ), + expected, ) def test_with_layout_but_disable(self): @@ -5554,7 +5737,11 @@ def test_with_layout_but_disable(self): circuit.measure(pqr[2], cr[0]) circuit.measure(pqr[3], cr[1]) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=True, with_layout=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=True, with_layout=False, idle_wires=True + ) + ), expected, ) @@ -5632,7 +5819,10 @@ def test_after_transpile(self): optimization_level=0, seed_transpiler=0, ) - self.assertEqual(qc_result.draw(output="text", cregbundle=False).single_string(), expected) + self.assertEqual( + qc_result.draw(output="text", cregbundle=False, idle_wires=True).single_string(), + expected, + ) class TestTextInitialValue(QiskitTestCase): @@ -5781,7 +5971,7 @@ def test_empty(self): circuit = QuantumCircuit(qr) circuit.global_phase = 3 - self.assertEqual(circuit.draw(output="text").single_string(), expected) + self.assertEqual(circuit.draw(output="text", idle_wires=True).single_string(), expected) def test_empty_noregs(self): """Text empty circuit (no registers) with phase.""" @@ -5790,7 +5980,7 @@ def test_empty_noregs(self): circuit = QuantumCircuit() circuit.global_phase = 4.21 - self.assertEqual(circuit.draw(output="text").single_string(), expected) + self.assertEqual(circuit.draw(output="text", idle_wires=True).single_string(), expected) def test_registerless_one_bit(self): """Text circuit with one-bit registers and registerless bits.""" @@ -5818,7 +6008,9 @@ def test_registerless_one_bit(self): qry = QuantumRegister(1, "qry") crx = ClassicalRegister(2, "crx") circuit = QuantumCircuit(qrx, [Qubit(), Qubit()], qry, [Clbit(), Clbit()], crx) - self.assertEqual(circuit.draw(output="text", cregbundle=True).single_string(), expected) + self.assertEqual( + circuit.draw(output="text", cregbundle=True, idle_wires=True).single_string(), expected + ) class TestCircuitVisualizationImplementation(QiskitVisualizationTestCase): @@ -5941,7 +6133,11 @@ def test_if_op_bundle_false(self): circuit.h(0) circuit.cx(0, 1) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=False, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=False, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -5971,7 +6167,7 @@ def test_if_op_bundle_true(self): circuit.h(0) circuit.cx(0, 1) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=False)), + str(circuit_drawer(circuit, output="text", initial_state=False, idle_wires=True)), expected, ) @@ -6019,7 +6215,11 @@ def test_if_else_with_body_specified(self): circuit.if_else((cr[1], 1), circuit2, None, [0, 1, 2], [0, 1, 2]) circuit.x(0, label="X1i") self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=False, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=False, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -6109,6 +6309,7 @@ def test_if_op_nested_wire_order(self): fold=77, initial_state=False, wire_order=[2, 0, 3, 1, 4, 5, 6], + idle_wires=True, ) ), expected, @@ -6149,7 +6350,11 @@ def test_while_loop(self): with circuit.if_test((cr[2], 1)): circuit.x(0) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=False, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=False, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -6191,7 +6396,12 @@ def test_for_loop(self): self.assertEqual( str( circuit_drawer( - circuit, output="text", fold=-1, initial_state=False, cregbundle=False + circuit, + output="text", + fold=-1, + initial_state=False, + cregbundle=False, + idle_wires=True, ) ), expected, @@ -6295,7 +6505,12 @@ def test_inner_wire_map_control_op(self): self.assertEqual( str( circuit_drawer( - circuit, output="text", fold=78, initial_state=False, cregbundle=False + circuit, + output="text", + fold=78, + initial_state=False, + cregbundle=False, + idle_wires=True, ) ), expected, @@ -6339,7 +6554,11 @@ def test_if_else_op_from_circuit_with_conditions(self): circuit.if_else((cr[1], 1), qc2, None, [0, 1, 2], [0, 1, 2]) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=False, cregbundle=False)), + str( + circuit_drawer( + circuit, output="text", initial_state=False, cregbundle=False, idle_wires=True + ) + ), expected, ) @@ -6376,7 +6595,7 @@ def test_if_with_expr(self): circuit.z(0) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=False)), + str(circuit_drawer(circuit, output="text", initial_state=False, idle_wires=True)), expected, ) @@ -6415,7 +6634,11 @@ def test_if_with_expr_nested(self): circuit.z(1) self.assertEqual( - str(circuit_drawer(circuit, output="text", initial_state=False, fold=120)), + str( + circuit_drawer( + circuit, output="text", initial_state=False, fold=120, idle_wires=True + ) + ), expected, ) @@ -6470,7 +6693,11 @@ def test_switch_with_expression(self): circuit.cx(0, 1) self.assertEqual( - str(circuit_drawer(circuit, output="text", fold=80, initial_state=False)), + str( + circuit_drawer( + circuit, output="text", fold=80, initial_state=False, idle_wires=True + ) + ), expected, ) @@ -6545,7 +6772,7 @@ def test_nested_switch_op_var(self): c = qc.add_var("c", expr.equal(a, b)) with qc.if_test(c): qc.h(0) - actual = str(qc.draw("text", fold=80, initial_state=False)) + actual = str(qc.draw("text", fold=80, initial_state=False, idle_wires=True)) self.assertEqual(actual, expected) diff --git a/test/visual/mpl/circuit/references/idle_wires_barrier.png b/test/visual/mpl/circuit/references/idle_wires_barrier.png index 2d603f7f9686..e8de1f509609 100644 Binary files a/test/visual/mpl/circuit/references/idle_wires_barrier.png and b/test/visual/mpl/circuit/references/idle_wires_barrier.png differ diff --git a/test/visual/mpl/circuit/test_circuit_matplotlib_drawer.py b/test/visual/mpl/circuit/test_circuit_matplotlib_drawer.py index f52338251438..a6672dbf401b 100644 --- a/test/visual/mpl/circuit/test_circuit_matplotlib_drawer.py +++ b/test/visual/mpl/circuit/test_circuit_matplotlib_drawer.py @@ -103,7 +103,7 @@ def test_empty_circuit(self): circuit = QuantumCircuit() fname = "empty_circut.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -133,7 +133,7 @@ def test_calibrations(self): circuit.add_calibration("h", [0], h_q0) fname = "calibrations.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -171,7 +171,7 @@ def test_calibrations_with_control_gates(self): circuit.add_calibration("ch", [0, 1], ch_q01) fname = "calibrations_with_control_gates.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -209,7 +209,7 @@ def test_calibrations_with_swap_and_reset(self): circuit.add_calibration("reset", [0], reset_q0) fname = "calibrations_with_swap_and_reset.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -246,7 +246,7 @@ def test_calibrations_with_rzz_and_rxx(self): circuit.add_calibration("rxx", [0, 1], rxx_q01) fname = "calibrations_with_rzz_and_rxx.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -263,7 +263,7 @@ def test_no_ops(self): circuit = QuantumCircuit(2, 3) fname = "no_op_circut.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -291,7 +291,7 @@ def test_long_name(self): circuit.h(qr) fname = "long_name.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -311,7 +311,7 @@ def test_multi_underscore_reg_names(self): circuit = QuantumCircuit(q_reg1, q_reg3, c_reg1, c_reg3) fname = "multi_underscore_true.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=True, filename=fname) + self.circuit_drawer(circuit, output="mpl", cregbundle=True, filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -321,7 +321,9 @@ def test_multi_underscore_reg_names(self): FAILURE_PREFIX, ) fname2 = "multi_underscore_false.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname2) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname2, idle_wires=True + ) ratio2 = VisualTestUtilities._save_diff( self._image_path(fname2), @@ -347,7 +349,7 @@ def test_conditional(self): circuit.h(qr[0]).c_if(cr, 2) fname = "reg_conditional.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -373,7 +375,7 @@ def test_bit_conditional_with_cregbundle(self): circuit.x(qr[1]).c_if(cr[1], 0) fname = "bit_conditional_bundle.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -399,7 +401,9 @@ def test_bit_conditional_no_cregbundle(self): circuit.x(qr[1]).c_if(cr[1], 0) fname = "bit_conditional_no_bundle.png" - self.circuit_drawer(circuit, output="mpl", filename=fname, cregbundle=False) + self.circuit_drawer( + circuit, output="mpl", filename=fname, cregbundle=False, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -424,7 +428,9 @@ def test_plot_partial_barrier(self): circuit.h(q[0]) fname = "plot_partial_barrier.png" - self.circuit_drawer(circuit, output="mpl", filename=fname, plot_barriers=True) + self.circuit_drawer( + circuit, output="mpl", filename=fname, plot_barriers=True, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -453,7 +459,9 @@ def test_plot_barriers(self): # check the barriers plot properly when plot_barriers= True fname = "plot_barriers_true.png" - self.circuit_drawer(circuit, output="mpl", filename=fname, plot_barriers=True) + self.circuit_drawer( + circuit, output="mpl", filename=fname, plot_barriers=True, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -463,7 +471,9 @@ def test_plot_barriers(self): FAILURE_PREFIX, ) fname2 = "plot_barriers_false.png" - self.circuit_drawer(circuit, output="mpl", filename=fname2, plot_barriers=False) + self.circuit_drawer( + circuit, output="mpl", filename=fname2, plot_barriers=False, idle_wires=True + ) ratio2 = VisualTestUtilities._save_diff( self._image_path(fname2), @@ -486,7 +496,9 @@ def test_no_barriers_false(self): circuit.h(q1[1]) fname = "no_barriers.png" - self.circuit_drawer(circuit, output="mpl", filename=fname, plot_barriers=False) + self.circuit_drawer( + circuit, output="mpl", filename=fname, plot_barriers=False, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -507,7 +519,7 @@ def test_fold_minus1(self): circuit.x(0) fname = "fold_minus1.png" - self.circuit_drawer(circuit, output="mpl", fold=-1, filename=fname) + self.circuit_drawer(circuit, output="mpl", fold=-1, filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -528,7 +540,7 @@ def test_fold_4(self): circuit.x(0) fname = "fold_4.png" - self.circuit_drawer(circuit, output="mpl", fold=4, filename=fname) + self.circuit_drawer(circuit, output="mpl", fold=4, filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -565,7 +577,7 @@ def test_big_gates(self): circuit.append(Isometry(np.eye(4, 4), 0, 0), list(range(3, 5))) fname = "big_gates.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -588,7 +600,7 @@ def test_cnot(self): circuit.append(MCXVChain(3, dirty_ancillas=True), [qr[0], qr[1], qr[2], qr[3], qr[5]]) fname = "cnot.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -610,7 +622,7 @@ def test_cz(self): circuit.append(ZGate().control(1, ctrl_state="0", label="CZ Gate"), [2, 3]) fname = "cz.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -640,7 +652,7 @@ def test_pauli_clifford(self): circuit.dcx(3, 4) fname = "pauli_clifford.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -662,7 +674,12 @@ def test_creg_initial(self): fname = "creg_initial_true.png" self.circuit_drawer( - circuit, output="mpl", filename=fname, cregbundle=True, initial_state=True + circuit, + output="mpl", + filename=fname, + cregbundle=True, + initial_state=True, + idle_wires=True, ) ratio = VisualTestUtilities._save_diff( @@ -674,7 +691,12 @@ def test_creg_initial(self): ) fname2 = "creg_initial_false.png" self.circuit_drawer( - circuit, output="mpl", filename=fname2, cregbundle=False, initial_state=False + circuit, + output="mpl", + filename=fname2, + cregbundle=False, + initial_state=False, + idle_wires=True, ) ratio2 = VisualTestUtilities._save_diff( @@ -702,7 +724,7 @@ def test_r_gates(self): circuit.rzz(pi / 2, 2, 3) fname = "r_gates.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -726,7 +748,7 @@ def test_ctrl_labels(self): ) fname = "ctrl_labels.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -745,7 +767,7 @@ def test_cswap_rzz(self): circuit.append(RZZGate(3 * pi / 4).control(3, ctrl_state="010"), [2, 1, 4, 3, 0]) fname = "cswap_rzz.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -769,7 +791,7 @@ def test_ghz_to_gate(self): circuit.append(ccghz, [4, 0, 1, 3, 2]) fname = "ghz_to_gate.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -787,7 +809,7 @@ def test_scale(self): circuit.unitary(random_unitary(2**5), circuit.qubits) fname = "scale_default.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -797,7 +819,7 @@ def test_scale(self): FAILURE_PREFIX, ) fname2 = "scale_half.png" - self.circuit_drawer(circuit, output="mpl", filename=fname2, scale=0.5) + self.circuit_drawer(circuit, output="mpl", filename=fname2, scale=0.5, idle_wires=True) ratio2 = VisualTestUtilities._save_diff( self._image_path(fname2), @@ -808,7 +830,7 @@ def test_scale(self): ) fname3 = "scale_double.png" - self.circuit_drawer(circuit, output="mpl", filename=fname3, scale=2) + self.circuit_drawer(circuit, output="mpl", filename=fname3, scale=2, idle_wires=True) ratio3 = VisualTestUtilities._save_diff( self._image_path(fname3), @@ -829,7 +851,7 @@ def test_pi_param_expr(self): circuit.rx((pi - x) * (pi - y), 0) fname = "pi_in_param_expr.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -855,7 +877,7 @@ def test_partial_layout(self): ) fname = "partial_layout.png" - self.circuit_drawer(transpiled, output="mpl", filename=fname) + self.circuit_drawer(transpiled, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -874,7 +896,7 @@ def test_init_reset(self): circuit.initialize([0, 1, 0, 0], [0, 1]) fname = "init_reset.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -891,7 +913,7 @@ def test_with_global_phase(self): circuit.h(range(3)) fname = "global_phase.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -937,7 +959,9 @@ def test_alternative_colors(self): circuit.reset(5) fname = f"{style}_color.png" - self.circuit_drawer(circuit, output="mpl", style={"name": style}, filename=fname) + self.circuit_drawer( + circuit, output="mpl", style={"name": style}, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -956,7 +980,9 @@ def test_reverse_bits(self): circuit.ccx(2, 1, 0) fname = "reverse_bits.png" - self.circuit_drawer(circuit, output="mpl", reverse_bits=True, filename=fname) + self.circuit_drawer( + circuit, output="mpl", reverse_bits=True, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -979,7 +1005,9 @@ def test_bw(self): circuit.measure_all() fname = "bw.png" - self.circuit_drawer(circuit, output="mpl", style={"name": "bw"}, filename=fname) + self.circuit_drawer( + circuit, output="mpl", style={"name": "bw"}, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1025,12 +1053,7 @@ def test_user_style(self): "displaycolor": {"H2": ("#EEDD00", "#FF0000")}, } fname = "user_style.png" - self.circuit_drawer( - circuit, - output="mpl", - style=style, - filename=fname, - ) + self.circuit_drawer(circuit, output="mpl", style=style, filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1063,7 +1086,7 @@ def test_subfont_change(self): style = {"name": "iqp", "subfontsize": 11} fname = "subfont.png" - self.circuit_drawer(circuit, output="mpl", style=style, filename=fname) + self.circuit_drawer(circuit, output="mpl", style=style, filename=fname, idle_wires=True) self.assertEqual(style, {"name": "iqp", "subfontsize": 11}) # check does not change style ratio = VisualTestUtilities._save_diff( @@ -1086,7 +1109,7 @@ def test_meas_condition(self): circuit.h(qr[1]).c_if(cr, 1) fname = "meas_condition.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1114,7 +1137,12 @@ def test_reverse_bits_condition(self): fname = "reverse_bits_cond_true.png" self.circuit_drawer( - circuit, output="mpl", cregbundle=False, reverse_bits=True, filename=fname + circuit, + output="mpl", + cregbundle=False, + reverse_bits=True, + filename=fname, + idle_wires=True, ) ratio = VisualTestUtilities._save_diff( @@ -1126,7 +1154,12 @@ def test_reverse_bits_condition(self): ) fname2 = "reverse_bits_cond_false.png" self.circuit_drawer( - circuit, output="mpl", cregbundle=False, reverse_bits=False, filename=fname2 + circuit, + output="mpl", + cregbundle=False, + reverse_bits=False, + filename=fname2, + idle_wires=True, ) ratio2 = VisualTestUtilities._save_diff( @@ -1167,6 +1200,7 @@ def cnotnot(gate_label): "displaytext": {"CNOTNOT_PRIME": "$\\mathrm{CNOTNOT}'$"}, }, filename=fname, + idle_wires=True, ) ratio = VisualTestUtilities._save_diff( @@ -1191,6 +1225,7 @@ def test_6095(self): output="mpl", style={"displaycolor": {"cp": ("#A27486", "#000000"), "h": ("#A27486", "#000000")}}, filename=fname, + idle_wires=True, ) ratio = VisualTestUtilities._save_diff( @@ -1211,7 +1246,7 @@ def test_instruction_1q_1c(self): circuit.append(inst, [qr[0]], [cr[0]]) fname = "instruction_1q_1c.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1232,7 +1267,7 @@ def test_instruction_3q_3c_circ1(self): circuit.append(inst, [qr[0], qr[1], qr[2]], [cr2[0], cr[0], cr[1]]) fname = "instruction_3q_3c_circ1.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1253,7 +1288,7 @@ def test_instruction_3q_3c_circ2(self): circuit.append(inst, [qr[3], qr[0], qr[2]], [cr[0], cr[1], cr2[0]]) fname = "instruction_3q_3c_circ2.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1275,7 +1310,7 @@ def test_instruction_3q_3c_circ3(self): circuit.append(inst, [qr[3], qr[1], qr[2]], [cr3[1], cr[1], cr3[0]]) fname = "instruction_3q_3c_circ3.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1294,7 +1329,7 @@ def test_overwide_gates(self): circuit.initialize(initial_state) fname = "wide_params.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1316,7 +1351,9 @@ def test_one_bit_regs(self): circuit.measure(0, 0) fname = "one_bit_regs.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1345,7 +1382,7 @@ def test_user_ax_subplot(self): plt.close(fig) fname = "user_ax.png" - self.circuit_drawer(circuit, output="mpl", ax=ax2, filename=fname) + self.circuit_drawer(circuit, output="mpl", ax=ax2, filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1366,7 +1403,9 @@ def test_figwidth(self): circuit.x(2) fname = "figwidth.png" - self.circuit_drawer(circuit, output="mpl", style={"figwidth": 5}, filename=fname) + self.circuit_drawer( + circuit, output="mpl", style={"figwidth": 5}, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1385,7 +1424,7 @@ def test_registerless_one_bit(self): circuit = QuantumCircuit(qrx, [Qubit(), Qubit()], qry, [Clbit(), Clbit()], crx) fname = "registerless_one_bit.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1411,7 +1450,9 @@ def test_measures_with_conditions(self): circuit.h(0).c_if(cr2, 3) fname = "measure_cond_false.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1421,7 +1462,9 @@ def test_measures_with_conditions(self): FAILURE_PREFIX, ) fname2 = "measure_cond_true.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=True, filename=fname2) + self.circuit_drawer( + circuit, output="mpl", cregbundle=True, filename=fname2, idle_wires=True + ) ratio2 = VisualTestUtilities._save_diff( self._image_path(fname2), @@ -1445,7 +1488,9 @@ def test_conditions_measures_with_bits(self): circuit.measure(0, bits[3]) fname = "measure_cond_bits_false.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1455,7 +1500,9 @@ def test_conditions_measures_with_bits(self): FAILURE_PREFIX, ) fname2 = "measure_cond_bits_true.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=True, filename=fname2) + self.circuit_drawer( + circuit, output="mpl", cregbundle=True, filename=fname2, idle_wires=True + ) ratio2 = VisualTestUtilities._save_diff( self._image_path(fname2), @@ -1481,7 +1528,9 @@ def test_conditional_gates_right_of_measures_with_bits(self): circuit.h(qr[2]).c_if(cr[0], 0) fname = "measure_cond_bits_right.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1503,7 +1552,12 @@ def test_conditions_with_bits_reverse(self): fname = "cond_bits_reverse.png" self.circuit_drawer( - circuit, output="mpl", cregbundle=False, reverse_bits=True, filename=fname + circuit, + output="mpl", + cregbundle=False, + reverse_bits=True, + filename=fname, + idle_wires=True, ) ratio = VisualTestUtilities._save_diff( @@ -1524,7 +1578,13 @@ def test_sidetext_with_condition(self): circuit.append(CPhaseGate(pi / 2), [qr[0], qr[1]]).c_if(cr[1], 1) fname = "sidetext_condition.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, + output="mpl", + cregbundle=False, + filename=fname, + idle_wires=True, + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1575,7 +1635,9 @@ def test_fold_with_conditions(self): circuit.append(U1Gate(0).control(1), [1, 0]).c_if(cr, 31) fname = "fold_with_conditions.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1593,7 +1655,9 @@ def test_idle_wires_barrier(self): circuit.barrier() fname = "idle_wires_barrier.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=False + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1623,6 +1687,7 @@ def test_wire_order(self): cregbundle=False, wire_order=[2, 1, 3, 0, 6, 8, 9, 5, 4, 7], filename=fname, + idle_wires=True, ) ratio = VisualTestUtilities._save_diff( @@ -1645,7 +1710,7 @@ def test_barrier_label(self): circuit.barrier(label="End Y/X") fname = "barrier_label.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1667,7 +1732,9 @@ def test_if_op(self): circuit.cx(0, 1) fname = "if_op.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1691,7 +1758,9 @@ def test_if_else_op_bundle_false(self): circuit.cx(0, 1) fname = "if_else_op_false.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1716,7 +1785,7 @@ def test_if_else_op_bundle_true(self): circuit.cx(0, 1) fname = "if_else_op_true.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=True, filename=fname) + self.circuit_drawer(circuit, output="mpl", cregbundle=True, filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1741,7 +1810,12 @@ def test_if_else_op_textbook_style(self): fname = "if_else_op_textbook.png" self.circuit_drawer( - circuit, output="mpl", style="textbook", cregbundle=False, filename=fname + circuit, + output="mpl", + style="textbook", + cregbundle=False, + filename=fname, + idle_wires=True, ) ratio = VisualTestUtilities._save_diff( @@ -1778,7 +1852,9 @@ def test_if_else_with_body(self): circuit.x(0, label="X1i") fname = "if_else_body.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1820,7 +1896,7 @@ def test_if_else_op_nested(self): circuit.x(0) fname = "if_else_op_nested.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=True, filename=fname) + self.circuit_drawer(circuit, output="mpl", cregbundle=True, filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1868,6 +1944,7 @@ def test_if_else_op_wire_order(self): cregbundle=False, wire_order=[2, 0, 3, 1, 4, 5, 6], filename=fname, + idle_wires=True, ) ratio = VisualTestUtilities._save_diff( @@ -1910,7 +1987,7 @@ def test_if_else_op_fold(self): circuit.x(0) fname = "if_else_op_fold.png" - self.circuit_drawer(circuit, output="mpl", fold=7, filename=fname) + self.circuit_drawer(circuit, output="mpl", fold=7, filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1937,7 +2014,9 @@ def test_while_loop_op(self): circuit.x(0) fname = "while_loop.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1966,7 +2045,9 @@ def test_for_loop_op(self): circuit.z(0) fname = "for_loop.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -1995,7 +2076,9 @@ def test_for_loop_op_range(self): circuit.z(0) fname = "for_loop_range.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2023,7 +2106,9 @@ def test_for_loop_op_1_qarg(self): circuit.z(0) fname = "for_loop_1_qarg.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2055,7 +2140,9 @@ def test_switch_case_op(self): circuit.h(0) fname = "switch_case.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2083,7 +2170,9 @@ def test_switch_case_op_1_qarg(self): circuit.h(0) fname = "switch_case_1_qarg.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2111,7 +2200,9 @@ def test_switch_case_op_empty_default(self): circuit.h(0) fname = "switch_case_empty_default.png" - self.circuit_drawer(circuit, output="mpl", cregbundle=False, filename=fname) + self.circuit_drawer( + circuit, output="mpl", cregbundle=False, filename=fname, idle_wires=True + ) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2136,7 +2227,7 @@ def test_if_with_expression(self): circuit.z(0) fname = "if_op_expr.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2163,7 +2254,7 @@ def test_if_with_expression_nested(self): circuit.z(1) fname = "if_op_expr_nested.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2191,7 +2282,7 @@ def test_switch_with_expression(self): circuit.cx(0, 1) fname = "switch_expr.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2222,7 +2313,7 @@ def test_control_flow_layout(self): backend.target.add_instruction(SwitchCaseOp, name="switch_case") tqc = transpile(qc, backend, optimization_level=2, seed_transpiler=671_42) fname = "layout_control_flow.png" - self.circuit_drawer(tqc, output="mpl", filename=fname) + self.circuit_drawer(tqc, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2257,7 +2348,7 @@ def test_control_flow_nested_layout(self): tqc = transpile(qc, backend, optimization_level=2, seed_transpiler=671_42) fname = "nested_layout_control_flow.png" - self.circuit_drawer(tqc, output="mpl", filename=fname) + self.circuit_drawer(tqc, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2278,7 +2369,7 @@ def test_control_flow_with_fold_minus_one(self): circuit.cx(0, 1) fname = "control_flow_fold_minus_one.png" - self.circuit_drawer(circuit, output="mpl", filename=fname, fold=-1) + self.circuit_drawer(circuit, output="mpl", filename=fname, fold=-1, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2304,7 +2395,7 @@ def test_annotated_operation(self): circuit.append(op1, [0, 1, 2]) circuit.append(SXGate(), [1]) fname = "annotated.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2329,7 +2420,7 @@ def test_no_qreg_names_after_layout(self): ) fname = "qreg_names_after_layout.png" - self.circuit_drawer(circuit, output="mpl", filename=fname) + self.circuit_drawer(circuit, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2354,7 +2445,7 @@ def test_if_else_standalone_var(self): with qc.if_test(expr.logic_and(c, expr.equal(a, 128))): qc.h(0) fname = "if_else_standalone_var.png" - self.circuit_drawer(qc, output="mpl", filename=fname) + self.circuit_drawer(qc, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname), @@ -2382,7 +2473,7 @@ def test_switch_standalone_var(self): with qc.if_test(c): qc.h(0) fname = "switch_standalone_var.png" - self.circuit_drawer(qc, output="mpl", filename=fname) + self.circuit_drawer(qc, output="mpl", filename=fname, idle_wires=True) ratio = VisualTestUtilities._save_diff( self._image_path(fname),