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Power estimation #28

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OlinLai opened this issue Nov 15, 2023 · 1 comment
Open

Power estimation #28

OlinLai opened this issue Nov 15, 2023 · 1 comment

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@OlinLai
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OlinLai commented Nov 15, 2023

After completing the entire process, I noticed that in the route.log file, there were analyses related to critical path delay and logic area, but there was no analysis regarding power consumption.

Therefore, I attempted to investigate how to perform power analysis using VPR. However, I discovered that within the PRGA framework, Yosys replaced ODIN and ABC, both of which are essential tools for power estimation in VPR.

Hence, I'm wondering how I can accomplish power estimation while using PRGA?

@angl-dev
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Hi @OlinLai,

PRGA does not come with a power or timing model, because PRGA is designed for real silicon tape-outs. Without knowing the underlying tapeout, PRGA cannot provide any prediction of the power or timing. If you wish to explore novel architectures and get a power/timing estimation, I'd recommend using just VTR. They have power and timing models based on certain technologies.

Best,
Ang

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