diff --git a/src/main/scala/xiangshan/backend/Backend.scala b/src/main/scala/xiangshan/backend/Backend.scala index 91c9c914cf..373b7e9474 100644 --- a/src/main/scala/xiangshan/backend/Backend.scala +++ b/src/main/scala/xiangshan/backend/Backend.scala @@ -592,8 +592,9 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame for (i <- toMem.indices) { for (j <- toMem(i).indices) { val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) + val needIssueTimeout = memExuBlocksHasLDU(i)(j) || memExuBlocksHasVecLoad(i)(j) val issueTimeout = - if (memExuBlocksHasLDU(i)(j)) + if (needIssueTimeout) Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 else false.B @@ -608,6 +609,16 @@ class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parame memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) } + if (memScheduler.io.vecLoadFinalIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { + memScheduler.io.vecLoadFinalIssueResp(i)(j).valid := issueTimeout + memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType + memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.resp := RespType.block + memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx + memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) + memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) + memScheduler.io.vecLoadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) + } + NewPipelineConnect( bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, Mux( diff --git a/src/main/scala/xiangshan/backend/issue/Entries.scala b/src/main/scala/xiangshan/backend/issue/Entries.scala index 8b977f1c8a..26319bcc04 100644 --- a/src/main/scala/xiangshan/backend/issue/Entries.scala +++ b/src/main/scala/xiangshan/backend/issue/Entries.scala @@ -37,11 +37,7 @@ class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule else if (params.isStAddrIQ) //STU Seq(io.fromMem.get.slowResp) else if (params.isVecLduIQ && params.isVecStuIQ) // Vector store IQ need no vecLdIn.resp, but for now vector store share the vector load IQ - Seq(io.vecLdIn.get.resp, io.fromMem.get.slowResp) - else if (params.isVecLduIQ) - Seq(io.vecLdIn.get.resp) - else if (params.isVecStuIQ) - Seq(io.fromMem.get.slowResp) + Seq(io.vecLdIn.get.resp, io.fromMem.get.slowResp, io.vecLdIn.get.finalIssueResp) else Seq() if (params.isMemAddrIQ) { println(s"[${this.desiredName}] resp: {" + @@ -575,6 +571,7 @@ class EntriesIO(implicit p: Parameters, params: IssueBlockParams) extends XSBund val lqDeqPtr = Input(new LqPtr) }) val vecLdIn = OptionWrapper(params.isVecLduIQ, new Bundle { + val finalIssueResp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) val resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) }) val robIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, new RobPtr))) diff --git a/src/main/scala/xiangshan/backend/issue/IssueQueue.scala b/src/main/scala/xiangshan/backend/issue/IssueQueue.scala index 10aff9a6d5..6458d54735 100644 --- a/src/main/scala/xiangshan/backend/issue/IssueQueue.scala +++ b/src/main/scala/xiangshan/backend/issue/IssueQueue.scala @@ -50,7 +50,7 @@ class IssueQueueIO()(implicit p: Parameters, params: IssueBlockParams) extends X val og0Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) val og1Resp = Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle))) val og2Resp = Option.when(params.needOg2Resp)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) - val finalIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) + val finalIssueResp = Option.when(params.LdExuCnt > 0 || params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) val memAddrIssueResp = Option.when(params.LdExuCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) val vecLoadIssueResp = Option.when(params.VlduCnt > 0)(Vec(params.numDeq, Flipped(ValidIO(new IssueQueueDeqRespBundle)))) val wbBusyTableRead = Input(params.genWbFuBusyTableReadBundle) @@ -338,6 +338,9 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va } } if (params.isVecLduIQ) { + entriesIO.vecLdIn.get.finalIssueResp.zipWithIndex.foreach { case (resp, i) => + resp := io.finalIssueResp.get(i) + } entriesIO.vecLdIn.get.resp.zipWithIndex.foreach { case (resp, i) => resp := io.vecLoadIssueResp.get(i) } diff --git a/src/main/scala/xiangshan/backend/issue/Scheduler.scala b/src/main/scala/xiangshan/backend/issue/Scheduler.scala index 307c572eb8..9a73acf7c6 100644 --- a/src/main/scala/xiangshan/backend/issue/Scheduler.scala +++ b/src/main/scala/xiangshan/backend/issue/Scheduler.scala @@ -107,6 +107,7 @@ class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSB } val loadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) + val vecLoadFinalIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.VlduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) val memAddrIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.LdExuCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) val vecLoadIssueResp = MixedVec(params.issueBlockParams.map(x => MixedVec(Vec(x.VlduCnt, Flipped(ValidIO(new IssueQueueDeqRespBundle()(p, x))))))) @@ -416,9 +417,12 @@ abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockPa og1Resp := io.fromDataPath(i)(j).og1resp } iq.io.finalIssueResp.foreach(_.zipWithIndex.foreach { case (finalIssueResp, j) => - if (io.loadFinalIssueResp(i).isDefinedAt(j)) { + if (io.loadFinalIssueResp(i).isDefinedAt(j) && iq.params.isLdAddrIQ) { finalIssueResp := io.loadFinalIssueResp(i)(j) - } else { + } else if (io.vecLoadFinalIssueResp(i).isDefinedAt(j) && iq.params.isVecLduIQ) { + finalIssueResp := io.vecLoadFinalIssueResp(i)(j) + } + else { finalIssueResp := 0.U.asTypeOf(finalIssueResp) } }) diff --git a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala index 5256736be1..97617ce329 100644 --- a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala +++ b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala @@ -1037,7 +1037,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule val vecCommitHasException = (0 until EnsbufferWidth).map{ i => val ptr = rdataPtrExt(i).value val mmioStall = if(i == 0) mmio(rdataPtrExt(0).value) else (mmio(rdataPtrExt(i).value) || mmio(rdataPtrExt(i-1).value)) - val exceptionVliad = allocated(ptr) && committed(ptr) && vecMbCommit(ptr) && !mmioStall && isVec(ptr) && vecDataValid(ptr) && hasException(ptr) + val exceptionVliad = isVec(ptr) && hasException(ptr) && dataBuffer.io.enq(i).fire (exceptionVliad, uop(ptr), vecLastFlow(ptr)) }