From 63e5b8607b671285c46b97c24902dab6b1da8653 Mon Sep 17 00:00:00 2001
From: HeiHuDie <1042519051@qq.com>
Date: Wed, 16 Oct 2024 12:53:28 +0800
Subject: [PATCH] fix(Rename): remove the handling of dest being src in
 bypassCond

---
 coupledL2                                          |  2 +-
 ready-to-run                                       |  2 +-
 .../scala/xiangshan/backend/rename/Rename.scala    | 14 +++++++-------
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/coupledL2 b/coupledL2
index 8d19860274..42f53e9923 160000
--- a/coupledL2
+++ b/coupledL2
@@ -1 +1 @@
-Subproject commit 8d1986027416d30e993cb491aa18176ef4b87d3d
+Subproject commit 42f53e99235de0dfa07db108b7b2eab97a6ee376
diff --git a/ready-to-run b/ready-to-run
index 73d3a85760..fdef845c16 160000
--- a/ready-to-run
+++ b/ready-to-run
@@ -1 +1 @@
-Subproject commit 73d3a85760bb333672565802df20e9e17162e5bb
+Subproject commit fdef845c16dd0d6d0357186d48c7b7e7645a1f89
diff --git a/src/main/scala/xiangshan/backend/rename/Rename.scala b/src/main/scala/xiangshan/backend/rename/Rename.scala
index 424e0891d6..9e99997903 100644
--- a/src/main/scala/xiangshan/backend/rename/Rename.scala
+++ b/src/main/scala/xiangshan/backend/rename/Rename.scala
@@ -491,7 +491,7 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
   io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest)
 
   // psrc(n) + pdest(1)
-  val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))))
+  val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))))
   require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc)
   private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype
   println(s"[Rename] idx of pdest in bypassCond $pdestLoc")
@@ -499,15 +499,15 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
     val v0Cond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) =>
       if (i == 3) (s === SrcType.vp) || (s === SrcType.v0)
       else false.B
-    } :+ needV0Dest(i)
+    }
     val vlCond = io.in(i).bits.srcType.zipWithIndex.map{ case (s, i) =>
       if (i == 4) s === SrcType.vp
       else false.B
-    } :+ needVlDest(i)
-    val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i)
-    val fpCond  = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i)
-    val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i)
-    val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest
+    }
+    val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp)
+    val fpCond  = io.in(i).bits.srcType.map(_ === SrcType.fp)
+    val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp)
+    val target = io.in(i).bits.lsrc
     for ((((((cond1, (condV0, condVl)), cond2), cond3), t), j) <- vecCond.zip(v0Cond.zip(vlCond)).zip(fpCond).zip(intCond).zip(target).zipWithIndex) {
       val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) =>
         val indexMatch = in.bits.ldest === t