diff --git a/Utility b/Utility
index 65e0b86e..8c8189b8 160000
--- a/Utility
+++ b/Utility
@@ -1 +1 @@
-Subproject commit 65e0b86edbc16c81795ea191a1cf744555056892
+Subproject commit 8c8189b85c1aa3f8682bd2c02df01f257c38d0ab
diff --git a/src/main/scala/huancun/HuanCun.scala b/src/main/scala/huancun/HuanCun.scala
index 86a54751..63e30dc0 100644
--- a/src/main/scala/huancun/HuanCun.scala
+++ b/src/main/scala/huancun/HuanCun.scala
@@ -231,6 +231,8 @@ class HuanCun(implicit p: Parameters) extends LazyModule with HasHuanCunParamete
   val intnode = ctrl_unit.map(_.intnode)
 
   val pf_recv_node: Option[BundleBridgeSink[PrefetchRecv]] = prefetchOpt match {
+    case Some(_: L3PrefetchReceiverParams) =>
+      Some(BundleBridgeSink(Some(() => new PrefetchRecv)))
     case Some(_: PrefetchReceiverParams) =>
       Some(BundleBridgeSink(Some(() => new PrefetchRecv)))
     case _ => None
diff --git a/src/main/scala/huancun/noninclusive/MSHR.scala b/src/main/scala/huancun/noninclusive/MSHR.scala
index e67324bc..7cab33a3 100644
--- a/src/main/scala/huancun/noninclusive/MSHR.scala
+++ b/src/main/scala/huancun/noninclusive/MSHR.scala
@@ -991,7 +991,7 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
   val acquire_opcode = if (cacheParams.name == "L2") {
     Mux(req.opcode === AcquirePerm && req.param === BtoT, AcquirePerm, Mux(req.opcode === Hint, AcquireBlock, req.opcode))
   } else {
-    Mux(req_put, AcquireBlock, req.opcode)
+    Mux(req_put, AcquireBlock, Mux(req.opcode === Hint, AcquireBlock, req.opcode))
     // for put & !bypassPut, cache hierachy should have B/T. AcquirePerm is enough
   }
 
@@ -1001,7 +1001,10 @@ class MSHR()(implicit p: Parameters) extends BaseMSHR[DirResult, SelfDirWrite, S
       req.param
     )
   } else {
-    Mux(req.opcode === AcquireBlock && req.param === BtoT, NtoT, Mux(req_put, NtoT, req.param))
+    Mux(req.opcode === Hint,
+      Mux(req_needT, Mux(highest_perm_reg === BRANCH, BtoT, NtoT), NtoB),
+      Mux(req.opcode === AcquireBlock && req.param === BtoT, NtoT, Mux(req_put, NtoT, req.param))
+    )
   }
 
   oa.opcode := Mux(!s_transferput || bypassGet, req.opcode,
diff --git a/src/main/scala/huancun/noninclusive/SliceCtrl.scala b/src/main/scala/huancun/noninclusive/SliceCtrl.scala
index 99dc723b..fe3e3da8 100644
--- a/src/main/scala/huancun/noninclusive/SliceCtrl.scala
+++ b/src/main/scala/huancun/noninclusive/SliceCtrl.scala
@@ -230,6 +230,7 @@ class SliceCtrl()(implicit p: Parameters) extends HuanCunModule {
   io.cmo_req.bits.fromCmoHelper := true.B
   io.cmo_req.bits.needProbeAckData.foreach(_ := false.B)
   io.cmo_req.bits.reqSource := MemReqSource.NoWhere.id.U
+  io.cmo_req.bits.isBop.foreach(_ := false.B)
 
   io.cmo_req.valid := s_cmo
   when(io.cmo_req.fire()){
diff --git a/src/main/scala/huancun/prefetch/PrefetchReceiver.scala b/src/main/scala/huancun/prefetch/PrefetchReceiver.scala
index fb253d4b..23934ead 100644
--- a/src/main/scala/huancun/prefetch/PrefetchReceiver.scala
+++ b/src/main/scala/huancun/prefetch/PrefetchReceiver.scala
@@ -5,13 +5,18 @@ import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
 import huancun._
-import utility.Pipeline
+import utility.{MemReqSource, Pipeline}
 
 case class PrefetchReceiverParams(n: Int = 32) extends PrefetchParameters {
   override val hasPrefetchBit: Boolean = true
   override val inflightEntries: Int = n
 }
 
+case class L3PrefetchReceiverParams(n: Int = 32) extends PrefetchParameters {
+  override val hasPrefetchBit: Boolean = true
+  override val inflightEntries: Int = n
+}
+
 class PrefetchReceiver()(implicit p: Parameters) extends PrefetchModule {
   val io = IO(new PrefetchIO())
   // just ignore train reqs
@@ -21,8 +26,8 @@ class PrefetchReceiver()(implicit p: Parameters) extends PrefetchModule {
   io.req.bits.tag := parseFullAddress(io.recv_addr.bits)._1
   io.req.bits.set := parseFullAddress(io.recv_addr.bits)._2
   io.req.bits.needT := false.B
-  io.req.bits.isBOP := false.B
   io.req.bits.source := 0.U // TODO: ensure source 0 is dcache
+  io.req.bits.pfSource := MemReqSource.Prefetch2L2Stream.id.U // TODO: add L3 pfSource
   io.req.valid := io.recv_addr.valid
 
 }
diff --git a/src/main/scala/huancun/prefetch/Prefetcher.scala b/src/main/scala/huancun/prefetch/Prefetcher.scala
index eb16cb19..98071d58 100644
--- a/src/main/scala/huancun/prefetch/Prefetcher.scala
+++ b/src/main/scala/huancun/prefetch/Prefetcher.scala
@@ -120,6 +120,24 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule {
       bop.io.req.ready := true.B
       pipe.io.in <> pftQueue.io.deq
       io.req <> pipe.io.out
+    case receiver: L3PrefetchReceiverParams =>
+      val l1_pf = Module(new PrefetchReceiver())
+      val pftQueue = Module(new PrefetchQueue)
+      val pipe = Module(new Pipeline(io.req.bits.cloneType, 1))
+
+      l1_pf.io.recv_addr := ValidIODelay(io.recv_addr, 2)
+      l1_pf.io.train <> DontCare
+      l1_pf.io.resp <> DontCare
+
+      io.resp.ready := true.B
+      io.train.ready := true.B
+
+      pftQueue.io.enq.valid := l1_pf.io.req.valid
+      pftQueue.io.enq.bits := l1_pf.io.req.bits
+
+      l1_pf.io.req.ready := true.B
+      pipe.io.in <> pftQueue.io.deq
+      io.req <> pipe.io.out
     case _ => assert(cond = false, "Unknown prefetcher")
   }
 }