diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc index 692518ef38..ec89495712 100644 --- a/src/arch/riscv/faults.cc +++ b/src/arch/riscv/faults.cc @@ -168,16 +168,17 @@ RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) ((v) && ((0 <= _code && _code <= 7 && _code != 2) || _code == INST_PAGE || _code == LOAD_PAGE || _code == STORE_PAGE))); hstatus.spv = v; - if (v) + if (v) { hstatus.spvp = pp; + } if (_code == INST_PAGE || _code == LOAD_PAGE || _code == STORE_PAGE || _code == LOAD_ADDR_MISALIGNED || _code == STORE_ADDR_MISALIGNED || _code == INST_ACCESS || - _code == LOAD_ACCESS || _code == STORE_ACCESS) + _code == LOAD_ACCESS || _code == STORE_ACCESS) { tc->setMiscReg(MISCREG_HTVAL, 0); - else if ((_code != INSTG_PAGE) && (_code != LOADG_PAGE) && (_code != STOREG_PAGE)) + } + else if ((_code != INSTG_PAGE) && (_code != LOADG_PAGE) && (_code != STOREG_PAGE)) { tc->setMiscReg(MISCREG_HTVAL, 0); - - + } tc->setMiscReg(MISCREG_VIRMODE, 0); } break; diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index 1bcfd729a4..f83db1a061 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -318,10 +318,7 @@ void ISA::clear() std::fill(miscRegFile.begin(), miscRegFile.end(), 0); miscRegFile[MISCREG_PRV] = PRV_M; - //miscRegFile[MISCREG_ISA] = 0x800000000034112f; miscRegFile[MISCREG_ISA] = 0x80000000003411af; - //miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x34112D; - //miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x1411ad; miscRegFile[MISCREG_VENDORID] = 0; miscRegFile[MISCREG_ARCHID] = 0; miscRegFile[MISCREG_IMPID] = 0; @@ -334,7 +331,6 @@ void ISA::clear() (1ULL << FS_OFFSET); } miscRegFile[MISCREG_MCOUNTEREN] = 0x0; - // miscRegFile[MISCREG_SCOUNTEREN] = 0x7; miscRegFile[MISCREG_SCOUNTEREN] = 0; // don't set it to zero; software may try to determine the supported // triggers, starting at zero. simply set a different value here. @@ -343,7 +339,6 @@ void ISA::clear() miscRegFile[MISCREG_NMIE] = 1; miscRegFile[MISCREG_VTYPE] = (1lu<<63); - //(HSTATUS) reg_num.vsxl =2; miscRegFile[MISCREG_HSTATUS] = (uint64_t)2<<32; miscRegFile[MISCREG_VSSTATUS] = miscRegFile[MISCREG_STATUS] & NEMU_SSTATUS_RMASK; miscRegFile[MISCREG_ARCHID] = 0x19; @@ -409,16 +404,16 @@ ISA::readMiscReg(int misc_reg) if ((v == 1) && (misc_reg == MISCREG_SATP)) { return readMiscRegNoEffect(MISCREG_VSATP); } - if ((v == 1) && (misc_reg == MISCREG_SEPC)){ + if ((v == 1) && (misc_reg == MISCREG_SEPC)) { return readMiscRegNoEffect(MISCREG_VSEPC); } - if ((v == 1) && (misc_reg == MISCREG_STVAL)){ + if ((v == 1) && (misc_reg == MISCREG_STVAL)) { return readMiscRegNoEffect(MISCREG_VSTVAL); } - if ((v == 1) && (misc_reg == MISCREG_SCAUSE)){ + if ((v == 1) && (misc_reg == MISCREG_SCAUSE)) { return readMiscRegNoEffect(MISCREG_VSCAUSE); } - if ((v == 1) && (misc_reg == MISCREG_STVEC)){ + if ((v == 1) && (misc_reg == MISCREG_STVEC)) { return readMiscRegNoEffect(MISCREG_VSTVEC); } if (misc_reg == MISCREG_HIE) { diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 7ac7d42745..e88ebd9d26 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -4330,14 +4330,14 @@ decode QUADRANT default Unknown::unknown() { auto hstatus_spv = hstatus.spv; auto pm = (PrivilegeMode)xc->readMiscReg( MISCREG_PRV); - bool writeSign = false; + bool write_sign = false; if(v ==0){ hstatus.spv =0; xc->setMiscReg(MISCREG_HSTATUS, hstatus); } else{ - writeSign = true; + write_sign = true; if((pm == PRV_S && hstatus.vtsr) || pm < PRV_S){ panic("todo EX_VI"); } @@ -4358,7 +4358,7 @@ decode QUADRANT default Unknown::unknown() { } NPC = xc->readMiscReg(MISCREG_VSEPC); } - if(!writeSign){ + if(!write_sign){ if (pm == PRV_U || (pm == PRV_S && status.tsr == 1)) { return std::make_shared( diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index 25e94f19ad..b635a091e4 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -345,8 +345,9 @@ def template CSRExecute {{ RegVal data, olddata; auto lowestAllowedMode = (PrivilegeMode)bits(csr, 9, 8); auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV); - if ((pm < lowestAllowedMode)&& - ((csr CSR_HGATP)) && ((csr CSR_VSATP))) { + if ((pm < lowestAllowedMode) && ((csr CSR_HGATP)) && ((csr CSR_VSATP))) { return std::make_shared( csprintf("%s is not accessible in %s\n", csrName, pm), machInst); diff --git a/src/arch/riscv/pagetable.hh b/src/arch/riscv/pagetable.hh index 9ddb17c745..aa026ff174 100644 --- a/src/arch/riscv/pagetable.hh +++ b/src/arch/riscv/pagetable.hh @@ -65,6 +65,8 @@ const Addr TWO_STAGE_L2_LEVEL_MASK = 0x7ff; const Addr VPN_MASK = 0x1ff; const Addr PGSHFT = 12; const Addr PTESIZE = 8; +const Addr L2PageTypeNum = 4; +const Addr L2PageStoreTypeNum = 5; const Addr L2TLB_BLK_OFFSET = 3; const Addr VADDR_CHOOSE_MASK = 7; diff --git a/src/arch/riscv/pagetable_walker.cc b/src/arch/riscv/pagetable_walker.cc index bbb55d8346..e7677ce262 100644 --- a/src/arch/riscv/pagetable_walker.cc +++ b/src/arch/riscv/pagetable_walker.cc @@ -267,8 +267,7 @@ void Walker::WalkerState::initState(ThreadContext *_tc, const RequestPtr &_req, BaseMMU::Mode _mode, bool _isTiming, bool _from_forward_pre_req, bool _from_back_pre_req) { - if (_req == nullptr) - assert(0); + assert(_req != nullptr); if (_req->get_two_stage_state()) { assert(state == Ready); started = false; @@ -602,8 +601,9 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write) if (pte.v && !pte.r && !pte.w && !pte.x) { twoStageLevel--; if (twoStageLevel < 0) { - doEndWalk = true; - assert(0); + endWalk(); + warn("pagefault in Gstage ptw twostagelevel <0\n"); + return endGstageWalk(); } else { nextRead = (pte.ppn << PageShift) + (getGVPNi(gPaddr, twoStageLevel) * PTESIZE); nextcheck = nextRead; @@ -638,19 +638,16 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write) } else if (!pte.v || (!pte.r && pte.w)) { endWalk(); - GstageFault = true; - fault = pageFault(true, true); - return fault; + return endGstageWalk(); } else if (!pte.u) { - doEndWalk = true; - assert(0); - } else if (((mode == BaseMMU::Execute) || (isHInst)) && (!pte.x)) { - doEndWalk = true; - assert(0); + endWalk(); + return endGstageWalk(); + } else if (((mode == BaseMMU::Execute) || isHInst) && (!pte.x)) { + endWalk(); + return endGstageWalk(); } else if ((mode == BaseMMU::Read) && (!pte.r && !(status.mxr && pte.x))) { - doEndWalk = true; - assert(0); - + endWalk(); + return endGstageWalk(); } else if ((mode == BaseMMU::Write) && !(pte.r && pte.w)) { endWalk(); GstageFault = true; @@ -708,19 +705,22 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write) gstage); } - else if (l2_level == 1) // hit level =1 + else if (l2_level == 1) { walker->tlb->L2TLBInsert(inl2Entry.gpaddr, inl2Entry, l2_level, L_L2sp2, l2_i, false, gstage); - else if (l2_level == 2) // + } // hit level =1 + + else if (l2_level == 2) { walker->tlb->L2TLBInsert(inl2Entry.gpaddr, inl2Entry, l2_level, L_L2sp1, l2_i, false, gstage); + } } } } if ((gPaddr & ~(((int64_t)1 << 41) - 1)) != 0) { // this is a excep - assert(0); + panic("address fault\n"); } DPRINTF(PageTableWalkerTwoStage, "twoStageStepWalk gpaddr %lx vaddr %lx\n", gPaddr, entry.vaddr); gpaddrMode =1; @@ -732,10 +732,7 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write) entry.paddr = gPaddr >> 12; entry.pte = pte; int put_level = 0; - if (twoStageLevel < level) - put_level = twoStageLevel; - else - put_level = level; + put_level = std::min(twoStageLevel, level); entry.logBytes = PageShift + (put_level * LEVEL_BITS); entry.level = put_level; @@ -763,7 +760,7 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write) bool tlb_hit = false; if (walker->l2tlb == nullptr) - assert(0); + panic("walker->l2tlb is none\n"); if (inGstage) { for (int i_e = 1; i_e < 6; i_e++) { e[i_e] = walker->l2tlb->lookupL2TLB(nextcheck, hgatp.vmid, mode, false, i_e, true, gstage); @@ -772,7 +769,6 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write) e[0] = e[i_e]; hit_level = e[i_e]->level; } - // assert(0); } if (e[0] && (twoStageLevel == e[0]->level)) { tlbHit = true; @@ -819,10 +815,10 @@ Walker::WalkerState::twoStageStepWalk(PacketPtr &write) DPRINTF(PageTableWalker, "Loading level%d PTE from %#x vaddr %#x\n", level, nextRead, entry.vaddr); } } else { - assert(0); + panic("wrong in G ptw\n"); } } else { - assert(0); + panic("wrong in G ptw\n"); } return fault; @@ -1082,7 +1078,7 @@ Walker::WalkerState::twoStageWalk(PacketPtr &write) } } } else { - assert(0); + panic("wrong in G ptw\n"); } return fault; @@ -1455,6 +1451,13 @@ Walker::WalkerState::endWalk() read = NULL; } Fault +Walker::WalkerState::endGstageWalk() +{ + endWalk(); + GstageFault = true; + return pageFault(true, true); +} +Fault Walker::WalkerState::startTwoStageWalkFromTLBNotInG(Addr ppn, Addr vaddr) { Addr PgBase = ppn << 12; @@ -1469,7 +1472,7 @@ Walker::WalkerState::startTwoStageWalkFromTLBNotInG(Addr ppn, Addr vaddr) warn("missaligned superpage vaddr %lx\n", entry.vaddr); fault = pageFault(true, false); endWalk(); - assert(0); + panic("address check wrong in from tlb ptw\n"); return fault; } PgBase = (PgBase & ~pg_mask) | (gPaddr & pg_mask & ~PGMASK); @@ -1480,7 +1483,7 @@ Walker::WalkerState::startTwoStageWalkFromTLBNotInG(Addr ppn, Addr vaddr) gPaddr = nextRead; if ((gPaddr & ~(((int64_t)1 << 41) - 1)) != 0) { // this is a excep - assert(0); + panic("address check wrong in from tlb ptw\n"); } DPRINTF(PageTableWalkerTwoStage, "twoStageStepWalk gpaddr %lx vaddr %lx\n", gPaddr, entry.vaddr); gpaddrMode = 1; @@ -1524,7 +1527,7 @@ Walker::WalkerState::startTwoStageWalk(Addr ppn, Addr vaddr) Addr TwoLevelTopAddr = 0; if ((ppn & ~(((int64_t)1 << 41) - 1)) != 0) { // this is a excep - assert(0); + panic("address check wrong in start ptw\n"); } TwoLevelTopAddr = (hgatp.ppn << PageShift) + (idx * sizeof(PTESv39)); @@ -1540,7 +1543,7 @@ Walker::WalkerState::startTwoStageWalk(Addr ppn, Addr vaddr) read->allocate(); } else { - assert(0); + panic("hgatp.mode != 8 \n"); } return NoFault; } @@ -1734,13 +1737,11 @@ Walker::WalkerState::recvPacket(PacketPtr pkt) nextState = Ready; PacketPtr write = NULL; read = pkt; - if ((translateMode == twoStageMode) && (inGstage)){ + if ((translateMode == twoStageMode) && (inGstage)) { mainFault = twoStageStepWalk(write); - } - else if ((translateMode == twoStageMode) && (!inGstage)){ + } else if ((translateMode == twoStageMode) && (!inGstage)) { mainFault = twoStageWalk(write); - } - else{ + } else { mainFault = stepWalk(write); } state = Waiting; @@ -1779,7 +1780,7 @@ Walker::WalkerState::recvPacket(PacketPtr pkt) if (mainFault != NoFault) { warn("paddr overflow vaddr: %lx paddr: lx\n", vaddr, paddr); r.translation->finish(mainFault, r.req, r.tc, mode); - assert(0); + panic("paddr overflow\n"); return false; } r.translation->finish(mainFault, r.req, r.tc, mode); @@ -2015,8 +2016,9 @@ Walker::WalkerState::pageFaultOnRequestor(RequestorState &r, bool G) if (r.req->isInstFetch()) { if (r.req->getPC() < page_start) { vaddr = page_start; - } else + } else { vaddr = r.req->getPC(); + } } else { vaddr = r.req->getVaddr(); diff --git a/src/arch/riscv/pagetable_walker.hh b/src/arch/riscv/pagetable_walker.hh index 517805d7dc..f04a5c999b 100644 --- a/src/arch/riscv/pagetable_walker.hh +++ b/src/arch/riscv/pagetable_walker.hh @@ -246,6 +246,7 @@ namespace RiscvISA Fault stepWalk(PacketPtr &write); void sendPackets(); void endWalk(); + Fault endGstageWalk(); Fault pageFault(bool present, bool G); Fault pageFaultOnRequestor(RequestorState &requestor, bool G); Addr getGVPNi(Addr vaddr, int level); diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh index 061ce3e9d1..dc054f7393 100644 --- a/src/arch/riscv/regs/misc.hh +++ b/src/arch/riscv/regs/misc.hh @@ -910,18 +910,6 @@ const RegVal STATUS_UPIE_MASK = 1ULL << 4; const RegVal STATUS_MIE_MASK = 1ULL << 3; const RegVal STATUS_SIE_MASK = 1ULL << 1; const RegVal STATUS_UIE_MASK = 1ULL << 0; -/*const RegVal MSTATUS_MASK = STATUS_SD_MASK | STATUS_SXL_MASK | - STATUS_UXL_MASK | STATUS_TSR_MASK | - STATUS_TW_MASK | STATUS_TVM_MASK | - STATUS_MXR_MASK | STATUS_SUM_MASK | - STATUS_MPRV_MASK | STATUS_XS_MASK | - STATUS_FS_MASK | STATUS_MPP_MASK | - STATUS_VS_MASK | - STATUS_SPP_MASK | STATUS_MPIE_MASK | - STATUS_SPIE_MASK | STATUS_UPIE_MASK | - STATUS_MIE_MASK | STATUS_SIE_MASK | - STATUS_UIE_MASK;*/ -//const RegVal MSTATUS_MASK = (0x7e79aaUL) | (1UL << 63) | (1UL << 39) | (1UL << 38); const RegVal MSTATUS_WMASK_FS = 0x3UL << 13; const RegVal MSTATUS_WMASK_RVH = 3UL << 38; const RegVal MSTATUS_WMASK_RVV = 3UL << 9; @@ -949,9 +937,6 @@ const RegVal UTI_MASK = 1ULL << 4; const RegVal MSI_MASK = 1ULL << 3; const RegVal SSI_MASK = 1ULL << 1; const RegVal USI_MASK = 1ULL << 0; -//const RegVal MIP_MASK = MEI_MASK | SEI_MASK | UEI_MASK | -// MTI_MASK | STI_MASK | UTI_MASK | -// MSI_MASK | SSI_MASK | USI_MASK; const RegVal NEMU_MIP_MASK = ((1 << 9) | (1 << 5) | (1 << 2) |(1 << 1)); const RegVal SI_MASK = SEI_MASK | STI_MASK | SSI_MASK; const RegVal UI_MASK = UEI_MASK | UTI_MASK | USI_MASK; @@ -966,12 +951,8 @@ const std::map CSRMasks = { {CSR_FRM, FRM_MASK}, {CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)}, {CSR_SSTATUS, SSTATUS_MASK}, - // {CSR_SIE, SI_MASK}, {CSR_SIP, SI_MASK}, {CSR_MISA, MISA_MASK} - // {CSR_HSTATUS,HSTATUS_MASK}, - // {CSR_MIE, MIE_MASK}, - //{CSR_MIP, MIP_MASK} }; #define concat_temp(x, y) x ## y @@ -1005,13 +986,6 @@ CSR_STRUCT_START(hstatus) uint64_t vsxl : 2; CSR_STRUCT_END(hstatus) - -// CSR_STRUCT_START(hedeleg) -// CSR_STRUCT_END(hedeleg) - -// CSR_STRUCT_START(hideleg) -// CSR_STRUCT_END(hideleg) - CSR_STRUCT_START(hie) uint64_t pad0 : 2; uint64_t vssie : 1; @@ -1023,15 +997,6 @@ CSR_STRUCT_START(hie) uint64_t sgeie : 1; CSR_STRUCT_END(hie) -// CSR_STRUCT_START(hcounteren) -// CSR_STRUCT_END(hcounteren) - -// CSR_STRUCT_START(hgeie) -// CSR_STRUCT_END(hgeie) - -// CSR_STRUCT_START(htval) -// CSR_STRUCT_END(htval) - CSR_STRUCT_START(hip) uint64_t pad0 : 2; uint64_t vssip : 1; @@ -1052,12 +1017,6 @@ CSR_STRUCT_START(hvip) uint64_t vseip : 1; CSR_STRUCT_END(hvip) -// CSR_STRUCT_START(htinst) -// CSR_STRUCT_END(htinst) - -// CSR_STRUCT_START(hgeip) -// CSR_STRUCT_END(hgeip) - CSR_STRUCT_START(henvcfg) uint64_t fiom : 1; uint64_t pad0 : 3; @@ -1076,9 +1035,6 @@ CSR_STRUCT_START(hgatp) uint64_t mode : 4; CSR_STRUCT_END(hgatp) -// CSR_STRUCT_START(htimedelta) -// CSR_STRUCT_END(htimedelta) - CSR_STRUCT_START(vsstatus) union{ struct{ @@ -1136,12 +1092,6 @@ CSR_STRUCT_START(vstvec) uint64_t base :62; CSR_STRUCT_END(vstvec) -// CSR_STRUCT_START(vsscratch) -// CSR_STRUCT_END(vsscratch) - -// CSR_STRUCT_START(vsepc) -// CSR_STRUCT_END(vsepc) - CSR_STRUCT_START(vscause) union{ struct{ @@ -1155,9 +1105,6 @@ CSR_STRUCT_START(vscause) }; CSR_STRUCT_END(vscause) -// CSR_STRUCT_START(vstval) -// CSR_STRUCT_END(vstval) - CSR_STRUCT_START(vsip) uint64_t pad0 : 1; uint64_t ssip : 1; diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc index fee7b23b7e..db3baa5c2f 100644 --- a/src/arch/riscv/tlb.cc +++ b/src/arch/riscv/tlb.cc @@ -110,10 +110,11 @@ TLB::TLB(const Params &p) : walker = p.walker; walker->setTLB(this); TLB *l2tlb; - if (isStage2) + if (isStage2) { l2tlb = this; - else + } else { l2tlb = static_cast(nextLevel()); + } walker->setL2TLB(l2tlb); DPRINTF(TLBVerbose, "tlb11 tlb_size %d size() %d\n", size, tlb.size()); @@ -356,10 +357,11 @@ TLB::autoOpenNextline() { TLB *l2tlb; - if (isStage2) + if (isStage2) { l2tlb = this; - else + } else { l2tlb = static_cast(nextLevel()); + } int pre_num_c = l2tlb->AllPre; int removePreUnused_c = l2tlb->RemovePreUnused; @@ -654,12 +656,13 @@ TLB::L2TLBInsertIn(Addr vpn, const TlbEntry &entry, int choose, EntryList *List, newEntry->isSquashed = true; stats.squashedInsertL2++; for (int i = 1; i < l2tlbLineSize; i++) { - if (translateMode == gstage) + if (translateMode == gstage) { newEntry = lookupL2TLB(vpn + step * i, entry.vmid, BaseMMU::Read, true, choose, false, translateMode); - else + } else { newEntry = lookupL2TLB(vpn + step * i, entry.asid, BaseMMU::Read, true, choose, false, translateMode); + } stats.squashedInsertL2++; if (newEntry) { newEntry->isSquashed = true; @@ -736,10 +739,11 @@ TLB::L2TLBInsert(Addr vpn, const TlbEntry &entry, int level, int choose, int sig uint8_t translateMode) { TLB *l2tlb; - if (isStage2) + if (isStage2) { l2tlb = this; - else + } else { l2tlb = static_cast(nextLevel()); + } TlbEntry *newEntry = nullptr; DPRINTF(TLB, "choose %d vpn %#x entry->vaddr %#x\n", choose, vpn, entry.vaddr); @@ -777,13 +781,14 @@ TLB::demapPage(Addr vpn, uint64_t asid) size_t i; TLB *l2tlb; - if (isStage2) + if (isStage2) { l2tlb = this; - else + } else { l2tlb = static_cast(nextLevel()); + } if ((l2tlb == nullptr) && (!isStage2)) - assert(0); + panic("l2tlb is fault\n"); if (vpn == 0 && asid == 0) { flushAll(); @@ -827,24 +832,30 @@ TLB::demapPageL2(Addr vpn, uint64_t asid) asid &= 0xFFFF; std::vector vpn_vec; std::vector tlb_lists; - vpn_vec.push_back(0); + std::vector tlb_size; Addr vpnl2l1 = (vpn >> (PageShift + 2 * LEVEL_BITS + L2TLB_BLK_OFFSET)) << (PageShift + 2 * LEVEL_BITS + L2TLB_BLK_OFFSET); vpn_vec.push_back(vpnl2l1); tlb_lists.push_back(tlbL2L1.data()); + tlb_size.push_back(l2TlbL1Size); Addr vpnl2l2 = (vpn >> (PageShift + LEVEL_BITS + L2TLB_BLK_OFFSET)) << (PageShift + LEVEL_BITS + L2TLB_BLK_OFFSET); vpn_vec.push_back(vpnl2l2); tlb_lists.push_back(tlbL2L2.data()); + tlb_size.push_back(l2TlbL2Size); Addr vpnl2l3 = (vpn >> (PageShift + L2TLB_BLK_OFFSET)) << (PageShift + L2TLB_BLK_OFFSET); vpn_vec.push_back(vpnl2l3); tlb_lists.push_back(tlbL2L3.data()); + tlb_size.push_back(l2TlbL3Size); Addr vpnl2sp1 = (vpn >> (PageShift + 2 * LEVEL_BITS + L2TLB_BLK_OFFSET)) << (PageShift + 2 * LEVEL_BITS + L2TLB_BLK_OFFSET); vpn_vec.push_back(vpnl2sp1); tlb_lists.push_back(tlbL2Sp.data()); + tlb_size.push_back(l2TlbSpSize); Addr vpnl2sp2 = (vpn >> (PageShift + LEVEL_BITS + L2TLB_BLK_OFFSET)) << (PageShift + LEVEL_BITS + L2TLB_BLK_OFFSET); vpn_vec.push_back(vpnl2sp2); + tlb_lists.push_back(tlbL2Sp.data()); + tlb_size.push_back(l2TlbSpSize); int i; DPRINTF(TLB, "l2 flush(vpn=%#x, asid=%#x)\n", vpn, asid); @@ -855,34 +866,25 @@ TLB::demapPageL2(Addr vpn, uint64_t asid) TlbEntry *l2_newEntry2[6] = {nullptr, nullptr, nullptr, nullptr, nullptr, nullptr}; for (int ii = 1; ii < 6; ii++) { - l2_newEntry[ii] = lookupL2TLB(vpn_vec[ii], asid, BaseMMU::Read, true, ii, false, direct); + l2_newEntry[ii] = lookupL2TLB(vpn_vec[ii - 1], asid, BaseMMU::Read, true, ii, false, direct); } for (int ii = 1; ii < 6; ii++) { - l2_newEntry1[ii] = lookupL2TLB(vpn_vec[ii], asid, BaseMMU::Read, true, ii, true, gstage); + l2_newEntry1[ii] = lookupL2TLB(vpn_vec[ii - 1], asid, BaseMMU::Read, true, ii, true, gstage); } for (int ii = 1; ii < 6; ii++) { - l2_newEntry2[ii] = lookupL2TLB(vpn_vec[ii], asid, BaseMMU::Read, true, ii, true, vsstage); + l2_newEntry2[ii] = lookupL2TLB(vpn_vec[ii - 1], asid, BaseMMU::Read, true, ii, true, vsstage); } if (vpn != 0 && asid != 0) { if (isStage2 || isTheSharedL2) { - for (i = 0; i < l2TlbL1Size * l2tlbLineSize; i = i + l2tlbLineSize) { - if (tlbL2L1[i].trieHandle) - l2TLBRemove(i, L_L2L1); - } - for (i = 0; i < l2TlbL2Size * l2tlbLineSize; i = i + l2tlbLineSize) { - if (tlbL2L2[i].trieHandle) - l2TLBRemove(i, L_L2L2); - } - for (i = 0; i < l2TlbL3Size * l2tlbLineSize; i = i + l2tlbLineSize) { - if (tlbL2L3[i].trieHandle) - l2TLBRemove(i, L_L2L3); - } - for (i = 0; i < l2TlbSpSize * l2tlbLineSize; i = i + l2tlbLineSize) { - if (tlbL2Sp[i].trieHandle) - l2TLBRemove(i, L_L2sp1); + for (int i_type = 0; i_type < L2PageTypeNum; i_type++) { + for (i = 0; i < tlb_size[i_type] * l2tlbLineSize; i = i + l2tlbLineSize) { + if ((tlb_lists[i_type] + i)->trieHandle) { + l2TLBRemove(i, i_type + 1); + } + } } } for (i = 1; i < 6; i++) { @@ -892,114 +894,46 @@ TLB::demapPageL2(Addr vpn, uint64_t asid) else tlb_i = i - 1; if (l2_newEntry[i]) { - TlbEntry *m_newEntry = lookupL2TLB(vpn_vec[i], asid, BaseMMU::Read, true, i, false,direct); + TlbEntry *m_newEntry = lookupL2TLB(vpn_vec[i - 1], asid, BaseMMU::Read, true, i, false, direct); assert(m_newEntry != nullptr); l2TLBRemove(m_newEntry - tlb_lists[tlb_i], i); } if (l2_newEntry1[i]) { - TlbEntry *m_newEntry = lookupL2TLB(vpn_vec[i], asid, BaseMMU::Read, true, i, true, gstage); + TlbEntry *m_newEntry = lookupL2TLB(vpn_vec[i - 1], asid, BaseMMU::Read, true, i, true, gstage); assert(m_newEntry != nullptr); l2TLBRemove(m_newEntry - tlb_lists[tlb_i], i); } if (l2_newEntry2[i]) { - TlbEntry *m_newEntry = lookupL2TLB(vpn_vec[i], asid, BaseMMU::Read, true, i, true, vsstage); + TlbEntry *m_newEntry = lookupL2TLB(vpn_vec[i - 1], asid, BaseMMU::Read, true, i, true, vsstage); assert(m_newEntry != nullptr); l2TLBRemove(m_newEntry - tlb_lists[tlb_i], i); } } } else { if (isStage2 || isTheSharedL2) { - for (i = 0; i < l2TlbL1Size * l2tlbLineSize; i = i + l2tlbLineSize) { - if (tlbL2L1[i].trieHandle) - l2TLBRemove(i, L_L2L1); - } - for (i = 0; i < l2TlbL2Size * l2tlbLineSize; i = i + l2tlbLineSize) { - if (tlbL2L2[i].trieHandle) - l2TLBRemove(i, L_L2L2); - } - for (i = 0; i < l2TlbL3Size * l2tlbLineSize; i = i + l2tlbLineSize) { - if (tlbL2L3[i].trieHandle) - l2TLBRemove(i, L_L2L3); - } - for (i = 0; i < l2TlbSpSize * l2tlbLineSize; i = i + l2tlbLineSize) { - if (tlbL2Sp[i].trieHandle) - l2TLBRemove(i, L_L2sp1); - } - } - - for (i = 0; i < l2TlbL1Size * l2tlbLineSize; i = i + l2tlbLineSize) { - Addr l2l1_mask = ~(tlbL2L1[i].size() - 1); - if (tlbL2L1[i].trieHandle) { - if ((vpnl2l1 == 0 || (vpnl2l1 & l2l1_mask) == tlbL2L1[i].vaddr) && - (asid == 0 || tlbL2L1[i].asid == asid)) { - l2TLBRemove(i, L_L2L1); - } - } - if (tlbL2L1[i].trieHandle) { - if ((vpnl2l1 == 0 || (vpnl2l1 & l2l1_mask) == (tlbL2L1[i].gpaddr & l2l1_mask)) && - (asid == 0 || tlbL2L1[i].vmid == asid)) { - l2TLBRemove(i, L_L2L1); - } - } - } - for (i = 0; i < l2TlbL2Size * l2tlbLineSize; i = i + l2tlbLineSize) { - Addr l2l2_mask = ~(tlbL2L2[i].size() - 1); - if (tlbL2L2[i].trieHandle) { - if ((vpnl2l2 == 0 || (vpnl2l2 & l2l2_mask) == tlbL2L2[i].vaddr) && - (asid == 0 || tlbL2L2[i].asid == asid)) { - l2TLBRemove(i, L_L2L2); - DPRINTF(TLBVerbose3, "l2l2 remove vaddr %#x vpn %#x vpnl2l3\n", tlbL2L2[i].vaddr, vpn, vpnl2l2); - } - } - if (tlbL2L2[i].trieHandle) { - if ((vpnl2l2 == 0 || (vpnl2l2 & l2l2_mask) == (tlbL2L2[i].gpaddr & l2l2_mask)) && - (asid == 0 || tlbL2L2[i].vmid == asid)) { - l2TLBRemove(i, L_L2L2); - DPRINTF(TLBVerbose3, "l2l2 remove vaddr %#x vpn %#x vpnl2l3\n", tlbL2L2[i].vaddr, vpn, vpnl2l2); - } - } - } - for (i = 0; i < l2TlbL3Size * l2tlbLineSize; i = i + l2tlbLineSize) { - Addr l2l3_mask = ~(tlbL2L3[i].size() - 1); - if (tlbL2L3[i].trieHandle) { - if ((vpnl2l3 == 0 || (vpnl2l3 & l2l3_mask) == tlbL2L3[i].vaddr) && - (asid == 0 || tlbL2L3[i].asid == asid)) { - l2TLBRemove(i, L_L2L3); - DPRINTF(TLBVerbose3, "l2l3 remove vaddr %#x vpn %#x vpnl2l3\n", tlbL2L3[i].vaddr, vpn, vpnl2l3); - } - } - if (tlbL2L3[i].trieHandle) { - if ((vpnl2l3 == 0 || (vpnl2l3 & l2l3_mask) == (tlbL2L3[i].gpaddr & l2l3_mask)) && - (asid == 0 || tlbL2L3[i].vmid == asid)) { - l2TLBRemove(i, L_L2L3); - DPRINTF(TLBVerbose3, "l2l3 remove vaddr %#x vpn %#x vpnl2l3\n", tlbL2L3[i].vaddr, vpn, vpnl2l3); + for (int i_type = 0; i_type < L2PageTypeNum; i_type++) { + for (i = 0; i < tlb_size[i_type] * l2tlbLineSize; i = i + l2tlbLineSize) { + if ((tlb_lists[i_type] + i)->trieHandle) { + l2TLBRemove(i, i_type + 1); + } } } } - for (i = 0; i < l2TlbSpSize * l2tlbLineSize; i++) { - Addr l2sp_mask = ~(tlbL2Sp[i].size() - 1); - if (tlbL2Sp[i].trieHandle) { - if ((vpnl2l1 == 0 || (vpnl2l1 & l2sp_mask) == tlbL2Sp[i].vaddr) && - (asid == 0 || tlbL2Sp[i].asid == asid)) { - l2TLBRemove(i, L_L2sp1); - } - } - if (tlbL2Sp[i].trieHandle) { - if ((vpnl2l1 == 0 || (vpnl2l1 & l2sp_mask) == (tlbL2Sp[i].gpaddr & l2sp_mask)) && - (asid == 0 || tlbL2Sp[i].vmid == asid)) { - l2TLBRemove(i, L_L2sp1); - } - } - if (tlbL2Sp[i].trieHandle) { - if ((vpnl2l2 == 0 || (vpnl2l2 & l2sp_mask) == tlbL2Sp[i].vaddr) && - (asid == 0 || tlbL2Sp[i].asid == asid)) { - l2TLBRemove(i, L_L2sp2); + for (int i_type = 0; i_type < L2PageTypeNum; i_type++) { + for (i = 0; i < tlb_size[i_type] * l2tlbLineSize; i = i + l2tlbLineSize) { + Addr mask = ~((tlb_lists[i_type] + i)->size() - 1); + if ((tlb_lists[i_type] + i)->trieHandle) { + if ((vpn_vec[i_type] == 0 || (vpn_vec[i_type] & mask) == (tlb_lists[i_type] + i)->vaddr) && + (asid == 0 || (tlb_lists[i_type] + i)->asid == asid)) { + l2TLBRemove(i, i_type + 1); + } } - } - if (tlbL2Sp[i].trieHandle) { - if ((vpnl2l2 == 0 || (vpnl2l2 & l2sp_mask) == (tlbL2Sp[i].gpaddr & l2sp_mask)) && - (asid == 0 || tlbL2Sp[i].vmid == asid)) { - l2TLBRemove(i, L_L2sp2); + if ((tlb_lists[i_type] + i)->trieHandle) { + if ((vpn_vec[i_type] == 0 || + (vpn_vec[i_type] & mask) == ((tlb_lists[i_type] + i)->gpaddr & mask)) && + (asid == 0 || (tlb_lists[i_type] + i)->vmid == asid)) { + l2TLBRemove(i, i_type + 1); + } } } } @@ -1185,8 +1119,7 @@ std::pair TLB::checkGPermissions(STATUS status,Addr vaddr,Addr gpaddr,BaseMMU::Mode mode, PTESv39 pte,bool h_inst){ bool continuePtw = false; if (pte.v && !pte.r && !pte.w && !pte.x) { - assert(0); - continuePtw = true; + panic("checkGpremission hit in no leaf node\n"); } else if (!pte.v || (!pte.r && pte.w)) { return std::make_pair(continuePtw,createPagefault(vaddr, gpaddr, mode, true)); } else if (!pte.u) { @@ -1342,10 +1275,11 @@ TLB::sendPreHitOnHitRequest(TlbEntry *e_pre_1, TlbEntry *e_pre_2, const RequestP TlbEntry *e_pre; double pre_precision = 0; TLB *l2tlb; - if (isStage2) + if (isStage2) { l2tlb = this; - else + } else { l2tlb = static_cast(nextLevel()); + } assert(l2tlb != nullptr); pre_entry.vaddr = pre_block; pre_entry.asid = asid; @@ -1422,8 +1356,7 @@ TLB::checkHL1Tlb(const RequestPtr &req, ThreadContext *tc, if (e[0]) { hit_type = h_l1AllstageHit; - if (hgatp.vmid != e[0]->vmid) - assert(0); + assert(hgatp.vmid != e[0]->vmid); if (vsatp.mode != 0) { if ((mode == BaseMMU::Write && !e[0]->pteVS.d) || (!e[0]->pteVS.a)) fault = createPagefault(vaddr, 0, mode, false); @@ -1540,10 +1473,11 @@ TLB::checkHL2Tlb(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation Addr pgBase = vsatp.ppn << PageShift; TLB *l2tlb; - if (isStage2) + if (isStage2) { l2tlb = this; - else + } else { l2tlb = static_cast(nextLevel()); + } assert(l2tlb != nullptr); // first check @@ -1691,12 +1625,7 @@ TLB::checkHL2Tlb(const RequestPtr &req, ThreadContext *tc, BaseMMU::Translation return std::make_pair(hit_type, NoFault); } } - /*else{ - hit_type = h_l2VSstageHitContinue; - req->setTwoPtwWalk(); - req->setgPaddr(); - }*/ } else { hit_type = H_L1miss; req->setTwoPtwWalk(false, level, twoStageLevel, 0, hitInSp); @@ -1726,10 +1655,11 @@ TLB::doTwoStageTranslate(const RequestPtr &req, ThreadContext *tc, int l1tlbtype = H_L1miss; TLB *l2tlb; - if (isStage2) + if (isStage2) { l2tlb = this; - else + } else { l2tlb = static_cast(nextLevel()); + } assert(l2tlb != nullptr); @@ -1829,10 +1759,11 @@ TLB::doTranslate(const RequestPtr &req, ThreadContext *tc, PrivilegeMode pmode = getMemPriv(tc, mode); TLB *l2tlb; - if (isStage2) + if (isStage2) { l2tlb = this; - else + } else { l2tlb = static_cast(nextLevel()); + } assert(l2tlb != nullptr); @@ -2088,8 +2019,7 @@ TLB::isaMMUCheck(ThreadContext *tc, Addr vaddr, BaseMMU::Mode mode) gpf = true; } } - if (!vaMsbsOk) - assert(0); + assert(vaMsbsOk); return MMU_DIRECT; } @@ -2133,8 +2063,7 @@ TLB::translate(const RequestPtr &req, ThreadContext *tc, if (fault == NoFault) { two_stage_translation = hasTwoStageTranslation(tc, req, mode); if (two_stage_translation) { - if (vsatp.mode != 8 && hgatp.mode != 8) - assert(0); + assert((vsatp.mode == 8) || (hgatp.mode == 8)); fault = doTwoStageTranslate(req, tc, translation, mode, delayed); } else { req->setTwoStageState(false, 0, 0); diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 0c1371ee88..21df16d129 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -692,6 +692,12 @@ class BaseCPU : public ClockedObject bool enabledifftesInstTrace{false}; std::shared_ptr diffAllStates{}; + enum diffRegConfig + { + diffAllNum = 96,// 32 regs + 32fprs +32 vprs + diffCsrNum = 36, + }; + virtual void readGem5Regs() { panic("difftest:readGem5Regs() is not implemented\n"); @@ -744,8 +750,8 @@ class BaseCPU : public ClockedObject uint8_t *goldenValue; uint64_t amoOldGoldenValue; // Register address causing difftest error - bool errorRegsValue[96];// 32 regs + 32fprs +32 vprs - bool errorCsrsValue[36];// CsrRegIndex + bool errorRegsValue[diffAllNum]; + bool errorCsrsValue[diffCsrNum]; // CsrRegIndex bool errorPcValue; std::queue lastCommittedMsg; diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc index 8c71e67a7a..6fc5fc1a4f 100644 --- a/src/cpu/o3/commit.cc +++ b/src/cpu/o3/commit.cc @@ -165,6 +165,14 @@ Commit::Commit(CPU *_cpu, branch_prediction::BPredUnit *_bp, const BaseO3CPUPara } simout.close(out_handle); }); + + faultNum.insert(RiscvISA::ExceptionCode::LOAD_PAGE); + faultNum.insert(RiscvISA::ExceptionCode::STORE_PAGE); + faultNum.insert(RiscvISA::ExceptionCode::INST_PAGE); + faultNum.insert(RiscvISA::ExceptionCode::INSTG_PAGE); + faultNum.insert(RiscvISA::ExceptionCode::LOADG_PAGE); + faultNum.insert(RiscvISA::ExceptionCode::STOREG_PAGE); + } std::string Commit::name() const { return cpu->name() + ".commit"; } @@ -1490,13 +1498,9 @@ Commit::commitHead(const DynInstPtr &head_inst, unsigned inst_num) tid, head_inst->seqNum); return false; } - if (inst_fault->exception() == RiscvISA::ExceptionCode::LOAD_PAGE || - inst_fault->exception() == RiscvISA::ExceptionCode::STORE_PAGE || - inst_fault->exception() == RiscvISA::ExceptionCode::INST_PAGE || - inst_fault->exception() == RiscvISA::ExceptionCode::INSTG_PAGE || - inst_fault->exception() == RiscvISA::ExceptionCode::LOADG_PAGE || - inst_fault->exception() == RiscvISA::ExceptionCode::STOREG_PAGE) + if (faultNum.find(inst_fault->exception()) != faultNum.end()) { stats.pagefaulttimes[tid]++; + } head_inst->setCompleted(); @@ -1570,12 +1574,7 @@ Commit::commitHead(const DynInstPtr &head_inst, unsigned inst_num) RiscvISA::MiscRegIndex::MISCREG_UCAUSE, tid); } auto exception_no =inst_fault->exception(); - if (exception_no == RiscvISA::ExceptionCode::LOAD_PAGE || - exception_no == RiscvISA::ExceptionCode::STORE_PAGE || - exception_no == RiscvISA::ExceptionCode::INST_PAGE || - exception_no == RiscvISA::ExceptionCode::INSTG_PAGE || - exception_no == RiscvISA::ExceptionCode::LOADG_PAGE || - exception_no == RiscvISA::ExceptionCode::STOREG_PAGE) { + if (faultNum.find(exception_no) != faultNum.end()) { DPRINTF(Commit, "Force to raise No.%lu exception at page fault\n", inst_fault); cpu->setExceptionGuideExecInfo( exception_no, cpu->readMiscReg(RiscvISA::MiscRegIndex::MISCREG_MTVAL, tid), diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 445bda4322..8228cf010d 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -126,6 +126,7 @@ class Commit CommitStatus _status; /** Next commit status, to be set at the end of the cycle. */ CommitStatus _nextStatus; + std::set faultNum; /** Per-thread status. */ ThreadStatus commitStatus[MaxThreads]; diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc index 51e915a0b6..f9d212b4df 100644 --- a/src/cpu/o3/lsq_unit.cc +++ b/src/cpu/o3/lsq_unit.cc @@ -1819,10 +1819,6 @@ LSQUnit::read(LSQRequest *request, ssize_t load_idx) if (!load_inst->isVector() && request->mainReq()->getSize() > 1 && request->mainReq()->getVaddr() % request->mainReq()->getSize() != 0) { - //DPRINTF(LSQUnit, "request: size: %u, Addr: %#lx, code: %d\n", request->mainReq()->getSize(), - // request->mainReq()->getVaddr(), RiscvISA::ExceptionCode::LOAD_ADDR_MISALIGNED); - //return std::make_shared(request->mainReq()->getVaddr(), - // RiscvISA::ExceptionCode::LOAD_ADDR_MISALIGNED); DPRINTF(LSQUnit, "request: size: %u, Addr: %#lx, code: %d\n", request->mainReq()->getSize(), request->mainReq()->getVaddr(), RiscvISA::ExceptionCode::LOAD_ADDR_MISALIGNED);