From 9392fc0ae6d1f55a4e074aa60a9e9cdfd13b250d Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 3 Feb 2025 12:13:00 -0800 Subject: [PATCH] espi: split port interrupt bits Signed-off-by: Felipe Balbi --- patch/espi.yaml | 25 +++++++++++++- src/espi/intenclr.rs | 82 ++++++++++++++++++++++++++++++++++++++------ src/espi/intenset.rs | 82 ++++++++++++++++++++++++++++++++++++++------ src/espi/intstat.rs | 82 ++++++++++++++++++++++++++++++++++++++------ src/espi/mstat.rs | 79 ++++++++++++++++++++++++++++++++++++++---- 5 files changed, 310 insertions(+), 40 deletions(-) diff --git a/patch/espi.yaml b/patch/espi.yaml index c7db2f9..74c0662 100644 --- a/patch/espi.yaml +++ b/patch/espi.yaml @@ -108,8 +108,8 @@ ESPI: _array: PENA*: {} - # Mark W1C bits accordingly MSTAT: + # Mark W1C bits accordingly _modify: P80Int: modifiedWriteValues: oneToClear @@ -128,3 +128,26 @@ ESPI: GPIO: modifiedWriteValues: oneToClear + + # Split PortInt bits + _split: + PortInt: + name: PORT_INT%s + + INTENSET: + # Split PortInt bits + _split: + PortInt: + name: PORT_INT%s + + INTENCLR: + # Split PortInt bits + _split: + PortInt: + name: PORT_INT%s + + INTSTAT: + # Split PortInt bits + _split: + PortInt: + name: PORT_INT%s diff --git a/src/espi/intenclr.rs b/src/espi/intenclr.rs index 630f17a..e8f587a 100644 --- a/src/espi/intenclr.rs +++ b/src/espi/intenclr.rs @@ -2,10 +2,26 @@ pub type R = crate::R; #[doc = "Register `INTENCLR` writer"] pub type W = crate::W; -#[doc = "Field `PortInt` reader - If set to 1, clears corresponding port interrupt enable"] -pub type PortIntR = crate::FieldReader; -#[doc = "Field `PortInt` writer - If set to 1, clears corresponding port interrupt enable"] -pub type PortIntW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PORT_INT0` reader - If set to 1, clears corresponding port interrupt enable"] +pub type PortInt0R = crate::BitReader; +#[doc = "Field `PORT_INT0` writer - If set to 1, clears corresponding port interrupt enable"] +pub type PortInt0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT1` reader - If set to 1, clears corresponding port interrupt enable"] +pub type PortInt1R = crate::BitReader; +#[doc = "Field `PORT_INT1` writer - If set to 1, clears corresponding port interrupt enable"] +pub type PortInt1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT2` reader - If set to 1, clears corresponding port interrupt enable"] +pub type PortInt2R = crate::BitReader; +#[doc = "Field `PORT_INT2` writer - If set to 1, clears corresponding port interrupt enable"] +pub type PortInt2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT3` reader - If set to 1, clears corresponding port interrupt enable"] +pub type PortInt3R = crate::BitReader; +#[doc = "Field `PORT_INT3` writer - If set to 1, clears corresponding port interrupt enable"] +pub type PortInt3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT4` reader - If set to 1, clears corresponding port interrupt enable"] +pub type PortInt4R = crate::BitReader; +#[doc = "Field `PORT_INT4` writer - If set to 1, clears corresponding port interrupt enable"] +pub type PortInt4W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `P80Int` reader - If set to 1, clears Port80 interrupt enable."] pub type P80intR = crate::BitReader; #[doc = "Field `P80Int` writer - If set to 1, clears Port80 interrupt enable."] @@ -35,10 +51,30 @@ pub type GpioR = crate::BitReader; #[doc = "Field `GPIO` writer - If set to 1, clears GPIO interrupt enable."] pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bits 0:4 - If set to 1, clears corresponding port interrupt enable"] + #[doc = "Bit 0 - If set to 1, clears corresponding port interrupt enable"] #[inline(always)] - pub fn port_int(&self) -> PortIntR { - PortIntR::new((self.bits & 0x1f) as u8) + pub fn port_int0(&self) -> PortInt0R { + PortInt0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If set to 1, clears corresponding port interrupt enable"] + #[inline(always)] + pub fn port_int1(&self) -> PortInt1R { + PortInt1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If set to 1, clears corresponding port interrupt enable"] + #[inline(always)] + pub fn port_int2(&self) -> PortInt2R { + PortInt2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If set to 1, clears corresponding port interrupt enable"] + #[inline(always)] + pub fn port_int3(&self) -> PortInt3R { + PortInt3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If set to 1, clears corresponding port interrupt enable"] + #[inline(always)] + pub fn port_int4(&self) -> PortInt4R { + PortInt4R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 8 - If set to 1, clears Port80 interrupt enable."] #[inline(always)] @@ -80,7 +116,6 @@ impl R { impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INTENCLR") - .field("port_int", &self.port_int()) .field("p80int", &self.p80int()) .field("bus_rst", &self.bus_rst()) .field("irq_upd", &self.irq_upd()) @@ -88,14 +123,39 @@ impl core::fmt::Debug for R { .field("hstall", &self.hstall()) .field("crcerr", &self.crcerr()) .field("gpio", &self.gpio()) + .field("port_int0", &self.port_int0()) + .field("port_int1", &self.port_int1()) + .field("port_int2", &self.port_int2()) + .field("port_int3", &self.port_int3()) + .field("port_int4", &self.port_int4()) .finish() } } impl W { - #[doc = "Bits 0:4 - If set to 1, clears corresponding port interrupt enable"] + #[doc = "Bit 0 - If set to 1, clears corresponding port interrupt enable"] + #[inline(always)] + pub fn port_int0(&mut self) -> PortInt0W { + PortInt0W::new(self, 0) + } + #[doc = "Bit 1 - If set to 1, clears corresponding port interrupt enable"] + #[inline(always)] + pub fn port_int1(&mut self) -> PortInt1W { + PortInt1W::new(self, 1) + } + #[doc = "Bit 2 - If set to 1, clears corresponding port interrupt enable"] + #[inline(always)] + pub fn port_int2(&mut self) -> PortInt2W { + PortInt2W::new(self, 2) + } + #[doc = "Bit 3 - If set to 1, clears corresponding port interrupt enable"] + #[inline(always)] + pub fn port_int3(&mut self) -> PortInt3W { + PortInt3W::new(self, 3) + } + #[doc = "Bit 4 - If set to 1, clears corresponding port interrupt enable"] #[inline(always)] - pub fn port_int(&mut self) -> PortIntW { - PortIntW::new(self, 0) + pub fn port_int4(&mut self) -> PortInt4W { + PortInt4W::new(self, 4) } #[doc = "Bit 8 - If set to 1, clears Port80 interrupt enable."] #[inline(always)] diff --git a/src/espi/intenset.rs b/src/espi/intenset.rs index 727ec1a..2c07ed0 100644 --- a/src/espi/intenset.rs +++ b/src/espi/intenset.rs @@ -2,10 +2,26 @@ pub type R = crate::R; #[doc = "Register `INTENSET` writer"] pub type W = crate::W; -#[doc = "Field `PortInt` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] -pub type PortIntR = crate::FieldReader; -#[doc = "Field `PortInt` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] -pub type PortIntW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PORT_INT0` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt0R = crate::BitReader; +#[doc = "Field `PORT_INT0` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT1` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt1R = crate::BitReader; +#[doc = "Field `PORT_INT1` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT2` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt2R = crate::BitReader; +#[doc = "Field `PORT_INT2` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT3` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt3R = crate::BitReader; +#[doc = "Field `PORT_INT3` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT4` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt4R = crate::BitReader; +#[doc = "Field `PORT_INT4` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt4W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `P80Int` reader - If set to 1, Port80 will interrupt main processor on update from Host."] pub type P80intR = crate::BitReader; #[doc = "Field `P80Int` writer - If set to 1, Port80 will interrupt main processor on update from Host."] @@ -35,10 +51,30 @@ pub type GpioR = crate::BitReader; #[doc = "Field `GPIO` writer - If 1, when ESPICFG GPIO changes input value, will interrupt main processor."] pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bits 0:4 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[doc = "Bit 0 - If set to 1, corresponding port will interrupt main processor if matches IRule"] #[inline(always)] - pub fn port_int(&self) -> PortIntR { - PortIntR::new((self.bits & 0x1f) as u8) + pub fn port_int0(&self) -> PortInt0R { + PortInt0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int1(&self) -> PortInt1R { + PortInt1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int2(&self) -> PortInt2R { + PortInt2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int3(&self) -> PortInt3R { + PortInt3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int4(&self) -> PortInt4R { + PortInt4R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 8 - If set to 1, Port80 will interrupt main processor on update from Host."] #[inline(always)] @@ -80,7 +116,6 @@ impl R { impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INTENSET") - .field("port_int", &self.port_int()) .field("p80int", &self.p80int()) .field("bus_rst", &self.bus_rst()) .field("irq_upd", &self.irq_upd()) @@ -88,14 +123,39 @@ impl core::fmt::Debug for R { .field("hstall", &self.hstall()) .field("crcerr", &self.crcerr()) .field("gpio", &self.gpio()) + .field("port_int0", &self.port_int0()) + .field("port_int1", &self.port_int1()) + .field("port_int2", &self.port_int2()) + .field("port_int3", &self.port_int3()) + .field("port_int4", &self.port_int4()) .finish() } } impl W { - #[doc = "Bits 0:4 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[doc = "Bit 0 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int0(&mut self) -> PortInt0W { + PortInt0W::new(self, 0) + } + #[doc = "Bit 1 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int1(&mut self) -> PortInt1W { + PortInt1W::new(self, 1) + } + #[doc = "Bit 2 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int2(&mut self) -> PortInt2W { + PortInt2W::new(self, 2) + } + #[doc = "Bit 3 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int3(&mut self) -> PortInt3W { + PortInt3W::new(self, 3) + } + #[doc = "Bit 4 - If set to 1, corresponding port will interrupt main processor if matches IRule"] #[inline(always)] - pub fn port_int(&mut self) -> PortIntW { - PortIntW::new(self, 0) + pub fn port_int4(&mut self) -> PortInt4W { + PortInt4W::new(self, 4) } #[doc = "Bit 8 - If set to 1, Port80 will interrupt main processor on update from Host."] #[inline(always)] diff --git a/src/espi/intstat.rs b/src/espi/intstat.rs index 75af01e..a7267e8 100644 --- a/src/espi/intstat.rs +++ b/src/espi/intstat.rs @@ -2,10 +2,26 @@ pub type R = crate::R; #[doc = "Register `INTSTAT` writer"] pub type W = crate::W; -#[doc = "Field `PortInt` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] -pub type PortIntR = crate::FieldReader; -#[doc = "Field `PortInt` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] -pub type PortIntW<'a, REG> = crate::FieldWriter<'a, REG, 5>; +#[doc = "Field `PORT_INT0` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt0R = crate::BitReader; +#[doc = "Field `PORT_INT0` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT1` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt1R = crate::BitReader; +#[doc = "Field `PORT_INT1` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT2` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt2R = crate::BitReader; +#[doc = "Field `PORT_INT2` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT3` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt3R = crate::BitReader; +#[doc = "Field `PORT_INT3` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT4` reader - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt4R = crate::BitReader; +#[doc = "Field `PORT_INT4` writer - If set to 1, corresponding port will interrupt main processor if matches IRule"] +pub type PortInt4W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `P80Int` reader - If set to 1, Port80 will interrupt main processor on update from Host."] pub type P80intR = crate::BitReader; #[doc = "Field `P80Int` writer - If set to 1, Port80 will interrupt main processor on update from Host."] @@ -35,10 +51,30 @@ pub type GpioR = crate::BitReader; #[doc = "Field `GPIO` writer - If 1, when ESPICFG GPIO changes input value, will interrupt main processor."] pub type GpioW<'a, REG> = crate::BitWriter<'a, REG>; impl R { - #[doc = "Bits 0:4 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[doc = "Bit 0 - If set to 1, corresponding port will interrupt main processor if matches IRule"] #[inline(always)] - pub fn port_int(&self) -> PortIntR { - PortIntR::new((self.bits & 0x1f) as u8) + pub fn port_int0(&self) -> PortInt0R { + PortInt0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int1(&self) -> PortInt1R { + PortInt1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int2(&self) -> PortInt2R { + PortInt2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int3(&self) -> PortInt3R { + PortInt3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int4(&self) -> PortInt4R { + PortInt4R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 8 - If set to 1, Port80 will interrupt main processor on update from Host."] #[inline(always)] @@ -80,7 +116,6 @@ impl R { impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("INTSTAT") - .field("port_int", &self.port_int()) .field("p80int", &self.p80int()) .field("bus_rst", &self.bus_rst()) .field("irq_upd", &self.irq_upd()) @@ -88,14 +123,39 @@ impl core::fmt::Debug for R { .field("hstall", &self.hstall()) .field("crcerr", &self.crcerr()) .field("gpio", &self.gpio()) + .field("port_int0", &self.port_int0()) + .field("port_int1", &self.port_int1()) + .field("port_int2", &self.port_int2()) + .field("port_int3", &self.port_int3()) + .field("port_int4", &self.port_int4()) .finish() } } impl W { - #[doc = "Bits 0:4 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[doc = "Bit 0 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int0(&mut self) -> PortInt0W { + PortInt0W::new(self, 0) + } + #[doc = "Bit 1 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int1(&mut self) -> PortInt1W { + PortInt1W::new(self, 1) + } + #[doc = "Bit 2 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int2(&mut self) -> PortInt2W { + PortInt2W::new(self, 2) + } + #[doc = "Bit 3 - If set to 1, corresponding port will interrupt main processor if matches IRule"] + #[inline(always)] + pub fn port_int3(&mut self) -> PortInt3W { + PortInt3W::new(self, 3) + } + #[doc = "Bit 4 - If set to 1, corresponding port will interrupt main processor if matches IRule"] #[inline(always)] - pub fn port_int(&mut self) -> PortIntW { - PortIntW::new(self, 0) + pub fn port_int4(&mut self) -> PortInt4W { + PortInt4W::new(self, 4) } #[doc = "Bit 8 - If set to 1, Port80 will interrupt main processor on update from Host."] #[inline(always)] diff --git a/src/espi/mstat.rs b/src/espi/mstat.rs index ef9618f..d853bde 100644 --- a/src/espi/mstat.rs +++ b/src/espi/mstat.rs @@ -2,8 +2,26 @@ pub type R = crate::R; #[doc = "Register `MSTAT` writer"] pub type W = crate::W; -#[doc = "Field `PortInt` reader - Corresponding port is pending interrupt service"] -pub type PortIntR = crate::FieldReader; +#[doc = "Field `PORT_INT0` reader - Corresponding port is pending interrupt service"] +pub type PortInt0R = crate::BitReader; +#[doc = "Field `PORT_INT0` writer - Corresponding port is pending interrupt service"] +pub type PortInt0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT1` reader - Corresponding port is pending interrupt service"] +pub type PortInt1R = crate::BitReader; +#[doc = "Field `PORT_INT1` writer - Corresponding port is pending interrupt service"] +pub type PortInt1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT2` reader - Corresponding port is pending interrupt service"] +pub type PortInt2R = crate::BitReader; +#[doc = "Field `PORT_INT2` writer - Corresponding port is pending interrupt service"] +pub type PortInt2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT3` reader - Corresponding port is pending interrupt service"] +pub type PortInt3R = crate::BitReader; +#[doc = "Field `PORT_INT3` writer - Corresponding port is pending interrupt service"] +pub type PortInt3W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PORT_INT4` reader - Corresponding port is pending interrupt service"] +pub type PortInt4R = crate::BitReader; +#[doc = "Field `PORT_INT4` writer - Corresponding port is pending interrupt service"] +pub type PortInt4W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `P80Int` reader - Port80 has had a request and is pending service."] pub type P80intR = crate::BitReader; #[doc = "Field `P80Int` writer - Port80 has had a request and is pending service."] @@ -43,10 +61,30 @@ pub type MastPendR = crate::BitReader; #[doc = "Field `AlertPend` reader - If 1, the Alert request pin is pending (whether separate pin or MISO)"] pub type AlertPendR = crate::BitReader; impl R { - #[doc = "Bits 0:4 - Corresponding port is pending interrupt service"] + #[doc = "Bit 0 - Corresponding port is pending interrupt service"] #[inline(always)] - pub fn port_int(&self) -> PortIntR { - PortIntR::new((self.bits & 0x1f) as u8) + pub fn port_int0(&self) -> PortInt0R { + PortInt0R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Corresponding port is pending interrupt service"] + #[inline(always)] + pub fn port_int1(&self) -> PortInt1R { + PortInt1R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Corresponding port is pending interrupt service"] + #[inline(always)] + pub fn port_int2(&self) -> PortInt2R { + PortInt2R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Corresponding port is pending interrupt service"] + #[inline(always)] + pub fn port_int3(&self) -> PortInt3R { + PortInt3R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Corresponding port is pending interrupt service"] + #[inline(always)] + pub fn port_int4(&self) -> PortInt4R { + PortInt4R::new(((self.bits >> 4) & 1) != 0) } #[doc = "Bit 8 - Port80 has had a request and is pending service."] #[inline(always)] @@ -113,7 +151,6 @@ impl R { impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("MSTAT") - .field("port_int", &self.port_int()) .field("p80int", &self.p80int()) .field("bus_rst", &self.bus_rst()) .field("irq_upd", &self.irq_upd()) @@ -126,10 +163,40 @@ impl core::fmt::Debug for R { .field("comp_pend", &self.comp_pend()) .field("mast_pend", &self.mast_pend()) .field("alert_pend", &self.alert_pend()) + .field("port_int0", &self.port_int0()) + .field("port_int1", &self.port_int1()) + .field("port_int2", &self.port_int2()) + .field("port_int3", &self.port_int3()) + .field("port_int4", &self.port_int4()) .finish() } } impl W { + #[doc = "Bit 0 - Corresponding port is pending interrupt service"] + #[inline(always)] + pub fn port_int0(&mut self) -> PortInt0W { + PortInt0W::new(self, 0) + } + #[doc = "Bit 1 - Corresponding port is pending interrupt service"] + #[inline(always)] + pub fn port_int1(&mut self) -> PortInt1W { + PortInt1W::new(self, 1) + } + #[doc = "Bit 2 - Corresponding port is pending interrupt service"] + #[inline(always)] + pub fn port_int2(&mut self) -> PortInt2W { + PortInt2W::new(self, 2) + } + #[doc = "Bit 3 - Corresponding port is pending interrupt service"] + #[inline(always)] + pub fn port_int3(&mut self) -> PortInt3W { + PortInt3W::new(self, 3) + } + #[doc = "Bit 4 - Corresponding port is pending interrupt service"] + #[inline(always)] + pub fn port_int4(&mut self) -> PortInt4W { + PortInt4W::new(self, 4) + } #[doc = "Bit 8 - Port80 has had a request and is pending service."] #[inline(always)] pub fn p80int(&mut self) -> P80intW {