From a1adfc5a38792d8491a39e5531471024f94e1110 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 6 Jan 2025 14:12:25 -0800 Subject: [PATCH] Split INTSPC fields --- patch/espi.yaml | 6 ++++ src/espi/port/irulestat.rs | 67 +++++++++++++++++++++++++++++++------- src/espi/port/stat.rs | 67 +++++++++++++++++++++++++++++++------- 3 files changed, 118 insertions(+), 22 deletions(-) diff --git a/patch/espi.yaml b/patch/espi.yaml index dce9ac9..fa8b365 100644 --- a/patch/espi.yaml +++ b/patch/espi.yaml @@ -24,10 +24,16 @@ ESPI: P[01234]STAT: description: Port Status name: STAT + _split: + INTSPC: + name: INTSPC%s P[01234]IRuleStat: description: Port set interrupt rules and user status name: IRULESTAT + _split: + INTSPC: + name: INTSPC%s P[01234]ADDR: description: Port Address offset to host diff --git a/src/espi/port/irulestat.rs b/src/espi/port/irulestat.rs index 5ec4d36..d0cfe31 100644 --- a/src/espi/port/irulestat.rs +++ b/src/espi/port/irulestat.rs @@ -18,10 +18,22 @@ pub type IntrdW<'a, REG> = crate::BitWriter<'a, REG>; pub type IntwrR = crate::BitReader; #[doc = "Field `INTWR` writer - Interrupt if Write or 1st Write or Bus master Finished."] pub type IntwrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INTSPC` reader - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] -pub type IntspcR = crate::FieldReader; -#[doc = "Field `INTSPC` writer - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] -pub type IntspcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `INTSPC0` reader - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc0R = crate::BitReader; +#[doc = "Field `INTSPC0` writer - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTSPC1` reader - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc1R = crate::BitReader; +#[doc = "Field `INTSPC1` writer - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTSPC2` reader - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc2R = crate::BitReader; +#[doc = "Field `INTSPC2` writer - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTSPC3` reader - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc3R = crate::BitReader; +#[doc = "Field `INTSPC3` writer - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc3W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `SSTCL` writer - Status set/clear"] pub type SstclW<'a, REG> = crate::FieldWriter<'a, REG, 4>; #[doc = "Field `SRST` writer - Resets the RdStatus and WrStatus in PStatus register"] @@ -47,10 +59,25 @@ impl R { pub fn intwr(&self) -> IntwrR { IntwrR::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bits 11:14 - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[doc = "Bit 11 - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] #[inline(always)] - pub fn intspc(&self) -> IntspcR { - IntspcR::new(((self.bits >> 11) & 0x0f) as u8) + pub fn intspc0(&self) -> Intspc0R { + Intspc0R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc1(&self) -> Intspc1R { + Intspc1R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc2(&self) -> Intspc2R { + Intspc2R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc3(&self) -> Intspc3R { + Intspc3R::new(((self.bits >> 14) & 1) != 0) } } #[cfg(feature = "debug")] @@ -61,7 +88,10 @@ impl core::fmt::Debug for R { .field("interr", &self.interr()) .field("intrd", &self.intrd()) .field("intwr", &self.intwr()) - .field("intspc", &self.intspc()) + .field("intspc0", &self.intspc0()) + .field("intspc1", &self.intspc1()) + .field("intspc2", &self.intspc2()) + .field("intspc3", &self.intspc3()) .finish() } } @@ -86,10 +116,25 @@ impl W { pub fn intwr(&mut self) -> IntwrW { IntwrW::new(self, 10) } - #[doc = "Bits 11:14 - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[doc = "Bit 11 - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc0(&mut self) -> Intspc0W { + Intspc0W::new(self, 11) + } + #[doc = "Bit 12 - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc1(&mut self) -> Intspc1W { + Intspc1W::new(self, 12) + } + #[doc = "Bit 13 - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc2(&mut self) -> Intspc2W { + Intspc2W::new(self, 13) + } + #[doc = "Bit 14 - Interrupt if: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] #[inline(always)] - pub fn intspc(&mut self) -> IntspcW { - IntspcW::new(self, 11) + pub fn intspc3(&mut self) -> Intspc3W { + Intspc3W::new(self, 14) } #[doc = "Bits 16:19 - Status set/clear"] #[inline(always)] diff --git a/src/espi/port/stat.rs b/src/espi/port/stat.rs index 73d37a0..54fcf1a 100644 --- a/src/espi/port/stat.rs +++ b/src/espi/port/stat.rs @@ -18,10 +18,22 @@ pub type IntrdW<'a, REG> = crate::BitWriter<'a, REG>; pub type IntwrR = crate::BitReader; #[doc = "Field `INTWR` writer - Interrupt was caused by Write or 1st Write or Bus master Started."] pub type IntwrW<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INTSPC` reader - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] -pub type IntspcR = crate::FieldReader; -#[doc = "Field `INTSPC` writer - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] -pub type IntspcW<'a, REG> = crate::FieldWriter<'a, REG, 4>; +#[doc = "Field `INTSPC0` reader - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc0R = crate::BitReader; +#[doc = "Field `INTSPC0` writer - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc0W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTSPC1` reader - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc1R = crate::BitReader; +#[doc = "Field `INTSPC1` writer - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc1W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTSPC2` reader - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc2R = crate::BitReader; +#[doc = "Field `INTSPC2` writer - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc2W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INTSPC3` reader - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc3R = crate::BitReader; +#[doc = "Field `INTSPC3` writer - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] +pub type Intspc3W<'a, REG> = crate::BitWriter<'a, REG>; #[doc = "Field `ERR` reader - Cause of INTERR: Bit Endpoint, Idx/Data Mbox BusMaster/Flash ERR0 Host Write Over Host Write or Read invalid for Access Failed From-Host (cannot tell on Memory To-Host, but can for Flash write)"] pub type ErrR = crate::FieldReader; impl R { @@ -50,10 +62,25 @@ impl R { pub fn intwr(&self) -> IntwrR { IntwrR::new(((self.bits >> 10) & 1) != 0) } - #[doc = "Bits 11:14 - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[doc = "Bit 11 - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] #[inline(always)] - pub fn intspc(&self) -> IntspcR { - IntspcR::new(((self.bits >> 11) & 0x0f) as u8) + pub fn intspc0(&self) -> Intspc0R { + Intspc0R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc1(&self) -> Intspc1R { + Intspc1R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc2(&self) -> Intspc2R { + Intspc2R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc3(&self) -> Intspc3R { + Intspc3R::new(((self.bits >> 14) & 1) != 0) } #[doc = "Bits 16:19 - Cause of INTERR: Bit Endpoint, Idx/Data Mbox BusMaster/Flash ERR0 Host Write Over Host Write or Read invalid for Access Failed From-Host (cannot tell on Memory To-Host, but can for Flash write)"] #[inline(always)] @@ -70,8 +97,11 @@ impl core::fmt::Debug for R { .field("interr", &self.interr()) .field("intrd", &self.intrd()) .field("intwr", &self.intwr()) - .field("intspc", &self.intspc()) .field("err", &self.err()) + .field("intspc0", &self.intspc0()) + .field("intspc1", &self.intspc1()) + .field("intspc2", &self.intspc2()) + .field("intspc3", &self.intspc3()) .finish() } } @@ -91,10 +121,25 @@ impl W { pub fn intwr(&mut self) -> IntwrW { IntwrW::new(self, 10) } - #[doc = "Bits 11:14 - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[doc = "Bit 11 - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc0(&mut self) -> Intspc0W { + Intspc0W::new(self, 11) + } + #[doc = "Bit 12 - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc1(&mut self) -> Intspc1W { + Intspc1W::new(self, 12) + } + #[doc = "Bit 13 - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] + #[inline(always)] + pub fn intspc2(&mut self) -> Intspc2W { + Intspc2W::new(self, 13) + } + #[doc = "Bit 14 - Interrupt was caused by: Bit Endpoint Idx/Data Mbox BusMaster/Flash SPC0 CMD Idx Change Write 0 Completed SPC1 - - Read 0 - SPC2 - - Write Last - SPC3 - - Read Last -"] #[inline(always)] - pub fn intspc(&mut self) -> IntspcW { - IntspcW::new(self, 11) + pub fn intspc3(&mut self) -> Intspc3W { + Intspc3W::new(self, 14) } } #[doc = "Port Status\n\nYou can [`read`](crate::Reg::read) this register and get [`stat::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`stat::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]