Fix address nack race condition (#308)I

According to NXP, mststate is only accurate and reflect actual HW state
when pending is set. This causes race condition where if the previous
transaction gets an address nack, the next transaction still sees
address nack in the mststate. Checking pending bit first ensure that
mststate is updated already.

Author: jerrysxie

examples/rt685s-evk/src/bin/i2c-master-async.rs

@@ -9,6 +9,8 @@ use embassy_imxrt::{bind_interrupts, i2c, peripherals};
 use embassy_time::Timer;
 use embedded_hal_async::i2c::I2c;
 
+const NACK_ADDR: u8 = 0x07;
+
 const ACC_ADDR: u8 = 0x1E;
 
 const ACC_ID_REG: u8 = 0x0D;
@@ -94,7 +96,33 @@ async fn main(_spawner: Spawner) {
     )
     .unwrap();
 
-    // Read WHO_AM_I register, 0x0D to get value 0xC7 (1100 0111)
+    info!("i2c example - write nack check");
+    let result = i2c.write(NACK_ADDR, &[ACC_ID_REG]).await;
+    if result.is_err_and(|e| e == i2c::TransferError::AddressNack.into()) {
+        info!("i2c example - write nack check gets the right error");
+    } else {
+        error!("i2c example - write nack check error did not get the error {}", result);
+    }
+
+    info!("i2c example - read nack check");
+    let mut reg = [0u8; 1];
+    let result = i2c.read(NACK_ADDR, &mut reg).await;
+    if result.is_err_and(|e| e == i2c::TransferError::AddressNack.into()) {
+        info!("i2c example - write nack check gets the right error");
+    } else {
+        error!("i2c example - write nack check error did not get the error {}", result);
+    }
+
+    info!("i2c example - write_read nack check");
+    let mut reg = [0u8; 1];
+    reg[0] = 0xAA;
+    let result = i2c.write_read(NACK_ADDR, &[ACC_ID_REG], &mut reg).await;
+    if result.is_err_and(|e| e == i2c::TransferError::AddressNack.into()) {
+        info!("i2c example - write nack check gets the right error");
+    } else {
+        error!("i2c example - write nack check error did not get the error {}", result);
+    }
+
     info!("i2c example - ACC WHO_AM_I register check");
     let mut reg = [0u8; 1];
     reg[0] = 0xAA;

src/i2c/master.rs

@@ -321,15 +321,20 @@ impl<'a> I2cMaster<'a, Async> {
                 |me| {
                     let stat = me.info.regs.stat().read();
 
-                    if is_read && stat.mststate().is_receive_ready() || !is_read && stat.mststate().is_transmit_ready()
-                    {
-                        Poll::Ready(Ok::<(), Error>(()))
-                    } else if stat.mststate().is_nack_address() {
-                        Poll::Ready(Err(TransferError::AddressNack.into()))
-                    } else if is_read && stat.mstpending().is_pending() && !stat.mststate().is_receive_ready() {
-                        Poll::Ready(Err(TransferError::ReadFail.into()))
-                    } else if !is_read && stat.mstpending().is_pending() && !stat.mststate().is_transmit_ready() {
-                        Poll::Ready(Err(TransferError::WriteFail.into()))
+                    if stat.mstpending().is_pending() {
+                        if is_read && stat.mststate().is_receive_ready()
+                            || !is_read && stat.mststate().is_transmit_ready()
+                        {
+                            Poll::Ready(Ok::<(), Error>(()))
+                        } else if stat.mststate().is_nack_address() {
+                            Poll::Ready(Err(TransferError::AddressNack.into()))
+                        } else if is_read && !stat.mststate().is_receive_ready() {
+                            Poll::Ready(Err(TransferError::ReadFail.into()))
+                        } else if !is_read && !stat.mststate().is_transmit_ready() {
+                            Poll::Ready(Err(TransferError::WriteFail.into()))
+                        } else {
+                            Poll::<Result<()>>::Pending
+                        }
                     } else if stat.mstarbloss().is_arbitration_loss() {
                         Poll::Ready(Err(TransferError::ArbitrationLoss.into()))
                     } else if stat.mstststperr().is_error() {
@@ -543,7 +548,7 @@ impl<'a> I2cMaster<'a, Async> {
             |me| {
                 let stat = me.info.regs.stat().read();
 
-                if stat.mststate().is_idle() {
+                if stat.mstpending().is_pending() && stat.mststate().is_idle() {
                     Poll::Ready(Ok(()))
                 } else if stat.mstarbloss().is_arbitration_loss() {
                     Poll::Ready(Err(TransferError::ArbitrationLoss.into()))