mem/EmbeddedTLB: fix connections of module EmbeddedTLB_fake (#86)

OSCPU · Jun 25, 2022 · 9009bec · 9009bec
1 parent 3e0b88e
commit 9009bec
Showing 1 changed file with 9 additions and 13 deletions.
diff --git a/src/main/scala/nutcore/mem/EmbeddedTLB.scala b/src/main/scala/nutcore/mem/EmbeddedTLB.scala
@@ -407,6 +407,7 @@ class EmbeddedTLBEmpty(implicit val tlbConfig: TLBConfig) extends TlbModule {
 }
 
 class EmbeddedTLB_fake(implicit val tlbConfig: TLBConfig) extends TlbModule with HasTLBIO {
+  io.mem <> DontCare
   io.out <> io.in
   io.csrMMU.loadPF := false.B
   io.csrMMU.storePF := false.B
@@ -417,20 +418,15 @@ class EmbeddedTLB_fake(implicit val tlbConfig: TLBConfig) extends TlbModule with
 
 object EmbeddedTLB {
   def apply(in: SimpleBusUC, mem: SimpleBusUC, flush: Bool, csrMMU: MMUIO, enable: Boolean = true)(implicit tlbConfig: TLBConfig) = {
-    if (enable) {
-      val tlb = Module(new EmbeddedTLB)
-      tlb.io.in <> in
-      tlb.io.mem <> mem
-      tlb.io.flush := flush
-      tlb.io.csrMMU <> csrMMU
-      tlb
+    val tlb = if (enable) {
+      Module(new EmbeddedTLB)
     } else {
-      val tlb = Module(new EmbeddedTLB_fake)
-      tlb.io.in <> in
-      tlb.io.flush := flush
-      tlb.io.csrMMU <> csrMMU
-      mem := DontCare
-      tlb
+      Module(new EmbeddedTLB_fake)
     }
+    tlb.io.in <> in
+    tlb.io.mem <> mem
+    tlb.io.flush := flush
+    tlb.io.csrMMU <> csrMMU
+    tlb
   }
 }