Skip to content

Commit 9009bec

Browse files
authored
mem/EmbeddedTLB: fix connections of module EmbeddedTLB_fake (#86)
1 parent 3e0b88e commit 9009bec

File tree

1 file changed

+9
-13
lines changed

1 file changed

+9
-13
lines changed

src/main/scala/nutcore/mem/EmbeddedTLB.scala

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -407,6 +407,7 @@ class EmbeddedTLBEmpty(implicit val tlbConfig: TLBConfig) extends TlbModule {
407407
}
408408

409409
class EmbeddedTLB_fake(implicit val tlbConfig: TLBConfig) extends TlbModule with HasTLBIO {
410+
io.mem <> DontCare
410411
io.out <> io.in
411412
io.csrMMU.loadPF := false.B
412413
io.csrMMU.storePF := false.B
@@ -417,20 +418,15 @@ class EmbeddedTLB_fake(implicit val tlbConfig: TLBConfig) extends TlbModule with
417418

418419
object EmbeddedTLB {
419420
def apply(in: SimpleBusUC, mem: SimpleBusUC, flush: Bool, csrMMU: MMUIO, enable: Boolean = true)(implicit tlbConfig: TLBConfig) = {
420-
if (enable) {
421-
val tlb = Module(new EmbeddedTLB)
422-
tlb.io.in <> in
423-
tlb.io.mem <> mem
424-
tlb.io.flush := flush
425-
tlb.io.csrMMU <> csrMMU
426-
tlb
421+
val tlb = if (enable) {
422+
Module(new EmbeddedTLB)
427423
} else {
428-
val tlb = Module(new EmbeddedTLB_fake)
429-
tlb.io.in <> in
430-
tlb.io.flush := flush
431-
tlb.io.csrMMU <> csrMMU
432-
mem := DontCare
433-
tlb
424+
Module(new EmbeddedTLB_fake)
434425
}
426+
tlb.io.in <> in
427+
tlb.io.mem <> mem
428+
tlb.io.flush := flush
429+
tlb.io.csrMMU <> csrMMU
430+
tlb
435431
}
436432
}

0 commit comments

Comments
 (0)