diff --git a/src/main/scala/bus/simplebus/Crossbar.scala b/src/main/scala/bus/simplebus/Crossbar.scala
index 6fce78851..e2b2d535b 100644
--- a/src/main/scala/bus/simplebus/Crossbar.scala
+++ b/src/main/scala/bus/simplebus/Crossbar.scala
@@ -96,7 +96,7 @@ class SimpleBusCrossbarNto1(n: Int, userBits:Int = 0) extends Module {
   (inputArb.io.in zip io.in.map(_.req)).map{ case (arb, in) => arb <> in }
   val thisReq = inputArb.io.out
   assert(!(thisReq.valid && !thisReq.bits.isRead() && !thisReq.bits.isWrite()))
-  val inflightSrc = Reg(UInt(log2Up(n).W))
+  val inflightSrc = RegInit(0.U(log2Up(n).W))
 
   io.out.req.bits := thisReq.bits
   // bind correct valid and ready signals