From ba3dc2da78b8e9d3b5d7ec531a7e4ffadc3ce8fe Mon Sep 17 00:00:00 2001 From: Tony Han Date: Thu, 9 Jan 2025 13:36:29 +0800 Subject: [PATCH] drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in PMC_PLL_UPDT specifies which PLL fields are wrote/read. Setting correct ID to PMC_PLL_UPDT to avoid operating on wrong PMC_PLL_CTRLx. Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5") Signed-off-by: Tony Han --- core/drivers/clk/sam/clk-sam9x60-pll.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/core/drivers/clk/sam/clk-sam9x60-pll.c b/core/drivers/clk/sam/clk-sam9x60-pll.c index e3e79ce209e..84689cb4b50 100644 --- a/core/drivers/clk/sam/clk-sam9x60-pll.c +++ b/core/drivers/clk/sam/clk-sam9x60-pll.c @@ -235,6 +235,9 @@ static TEE_Result sam9x60_frac_pll_set_rate_chg(struct clk *hw, ret = sam9x60_frac_pll_compute_mul_frac(frac, rate, parent_rate, true); if (ret == TEE_SUCCESS) { + io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT, + AT91_PMC_PLL_UPDT_ID_MASK, core->id); + io_write32(regmap + AT91_PMC_PLL_CTRL1, SHIFT_U32(frac->mul, core->layout->mul_shift) | SHIFT_U32(frac->frac, core->layout->frac_shift)); @@ -277,6 +280,9 @@ static TEE_Result sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, uint32_t enable_mask = enable ? core->layout->endiv_mask : 0; uint32_t ena_val = enable ? BIT(core->layout->endiv_shift) : 0; + io_clrsetbits32(regmap + AT91_PMC_PLL_UPDT, + AT91_PMC_PLL_UPDT_ID_MASK, core->id); + io_clrsetbits32(regmap + AT91_PMC_PLL_CTRL0, core->layout->div_mask | enable_mask, SHIFT_U32(div, core->layout->div_shift) | ena_val);