diff --git a/core/arch/riscv/include/kernel/thread_arch.h b/core/arch/riscv/include/kernel/thread_arch.h
index 5e2f100f359..7bc27872c0a 100644
--- a/core/arch/riscv/include/kernel/thread_arch.h
+++ b/core/arch/riscv/include/kernel/thread_arch.h
@@ -8,10 +8,22 @@
 
 #ifndef __ASSEMBLER__
 #include <compiler.h>
-#include <riscv.h>
 #include <types_ext.h>
 #endif
 
+#include <platform_config.h>
+#include <riscv.h>
+
+/*
+ * Each RISC-V platform must define their own values.
+ * See core/arch/riscv/plat-virt/platform_config.h for example.
+ */
+#define THREAD_EXCP_FOREIGN_INTR	PLAT_THREAD_EXCP_FOREIGN_INTR
+#define THREAD_EXCP_NATIVE_INTR		PLAT_THREAD_EXCP_NATIVE_INTR
+
+#define THREAD_EXCP_ALL			(THREAD_EXCP_FOREIGN_INTR |\
+					 THREAD_EXCP_NATIVE_INTR)
+
 #ifndef __ASSEMBLER__
 
 #define THREAD_CORE_LOCAL_ALIGNED __aligned(16)
@@ -154,20 +166,6 @@ struct thread_ctx_regs {
 
 struct user_mode_ctx;
 
-/*
- * These flags should vary according to the privilege mode selected
- * to run OP-TEE core on (M/HS/S). For now default to S-Mode.
- */
-
-#define CSR_XIE_SIE	BIT64(IRQ_XSOFT)
-#define CSR_XIE_TIE	BIT64(IRQ_XTIMER)
-#define CSR_XIE_EIE	BIT64(IRQ_XEXT)
-
-#define THREAD_EXCP_FOREIGN_INTR	CSR_XIE_EIE
-#define THREAD_EXCP_NATIVE_INTR	        (CSR_XIE_SIE | CSR_XIE_TIE)
-#define THREAD_EXCP_ALL			(THREAD_EXCP_FOREIGN_INTR |\
-					 THREAD_EXCP_NATIVE_INTR)
-
 #ifdef CFG_WITH_VFP
 uint32_t thread_kernel_enable_vfp(void);
 void thread_kernel_disable_vfp(uint32_t state);
diff --git a/core/arch/riscv/plat-spike/platform_config.h b/core/arch/riscv/plat-spike/platform_config.h
index 7a3ff4305aa..528dad5e483 100644
--- a/core/arch/riscv/plat-spike/platform_config.h
+++ b/core/arch/riscv/plat-spike/platform_config.h
@@ -9,6 +9,7 @@
 #define PLATFORM_CONFIG_H
 
 #include <mm/generic_ram_layout.h>
+#include <riscv.h>
 
 #ifndef HTIF_BASE
 #define HTIF_BASE	0x40008000
@@ -19,4 +20,7 @@
 #define CLINT_BASE	0x02000000
 #endif
 
+#define PLAT_THREAD_EXCP_FOREIGN_INTR	(CSR_XIE_EIE)
+#define PLAT_THREAD_EXCP_NATIVE_INTR	(CSR_XIE_SIE | CSR_XIE_TIE)
+
 #endif
diff --git a/core/arch/riscv/plat-virt/platform_config.h b/core/arch/riscv/plat-virt/platform_config.h
index 064cca29cf2..6c37ef204d2 100644
--- a/core/arch/riscv/plat-virt/platform_config.h
+++ b/core/arch/riscv/plat-virt/platform_config.h
@@ -9,6 +9,7 @@
 #define PLATFORM_CONFIG_H
 
 #include <mm/generic_ram_layout.h>
+#include <riscv.h>
 
 /* The stack pointer is always kept 16-byte aligned */
 #define STACK_ALIGNMENT		16
@@ -92,4 +93,8 @@
 #define RISCV_MTIME_RATE 1000000
 #endif
 
+#define PLAT_THREAD_EXCP_FOREIGN_INTR	\
+	(CSR_XIE_EIE | CSR_XIE_TIE | CSR_XIE_SIE)
+#define PLAT_THREAD_EXCP_NATIVE_INTR	(0)
+
 #endif /*PLATFORM_CONFIG_H*/