Changelog

All notable changes to the "FPGA Develop Support" extension will be documented in this file.

The format is based on Keep a Changelog, and this project adheres to Semantic Versioning.

Unreleased

[0.1.22] - 2022-01-20

Fix lib files do not display in tree view

[0.1.21] - 2022-01-20

Fix issue #26
Rename as Digital-IDE
Fix generate property.json file

[0.1.20] - 2022-01-12

Fix issue #32

[0.1.18] - 2021-09-12

delete generate tb file
add function netlist show
Fix issue #25
Fix issue #24

[0.1.17] - 2021-09-04

Fix issue #22
Fix issue #21
Fix issue #20

[0.1.16] - 2021-07-26

Optimization of the kernel, fix High CPU usage
Fix some other known bugs
Add Formatter function

[0.1.15] - 2021-05-02

Fix some bugs and add instructions

[0.1.12] - 2021-04-28

Added simulation function, automatically pop up error message

[0.1.10] - 2020-04-16

Added simulation function, automatically pop up error message

[0.1.8] - 2020-03-30

Fixed the problem of repeatedly opening a new project and supported adding devices directly from the Makefile

[0.1.6] - 2020-03-19

Add support for IP design and bd design
Add module jump (Alt + F12 or F12)
Change the startup shortcut key
Fix some bugs to enhance robustness

[0.1.4] - 2020-03-10

Address the BUG existing in 0.1.3

[0.1.2] - 2020-03-03

Add Xilinx IP of Soc's cortexM3
Provide an example for m3_for_xilinx.bd
Resolve the file structure conversion problem

[0.0.2] - 2020-02-28

Added testbench / instance function

[0.0.1] - 2020-02-15

Initial Release