VHDL: cannot visit FOR LOOP within a function

[andrasm62]

Hello!

I tried to parse a VHDL file that contains some functions each with a for loop inside.
The parsing seems to be okey, but after it, when I try to write it into a stream, I get an error.

My function looks like this:

function F_FunctionName(
	v_in		: std_logic_vector)
	return std_logic
is
	variable tmp	: std_logic;
begin
	tmp := '0';
	A: for i in 0 to Ge_Item_Cnt - 1 loop
		if v_in(((i + 1) * 3) - 1 downto i * 3) = C_Value then
			tmp := '1';
		end if;
	end loop;
	return tmp;
end function;

During visiting the AST the code tries to find a FOR ... GENERATE loop, but it throws an exception (raise TypeError("does not support HdlStmForIn", self, o)), because the HdlStmForIn object's in_preproc attribute's value is False.

I think it should be a valid scenario, when a FOR ... LOOP statement is present within a function.

[Nic30]

@andrasm62 it should be fixed you need to update also hdlConvertorAst, please confirm that the fix works for you so I can update pip packages as well.

Nic30/hdlConvertorAst@8607949

[andrasm62]

Thank you, @Nic30 !
It seems to work, I could parse and generate an output from it which is the same (except the comments and whitespaces) as the input.

By the way, what do you think about adding to this new test, when there's a function definition that uses a FOR...LOOP?
I guess, the code won't make any difference that where you place this expression, but who knows, maybe later once it will be usefull.

[Nic30]

except the comments and whitespaces

• whitespaces are expected to differ as the code is completely newly formatted
• comments are missing because there is missing a function call which parses the comments.
  • it is easy to fix but I am quite short on time right now (I can provide an advice if you can fix it.)

what do you think about adding to this new test

• fd1a7c1

It is a least I can do right now as it is easy to write test and it check that specified functionality.

The for loop can appear also on other places, some places do corresponds to a different rules in VHDL grammar. It would be better to walk through the grammar and check if the all unique appearances are tested.

[andrasm62]

it is easy to fix but I am quite short on time right now (I can provide an advice if you can fix it.)

I'm glad to help if it's easy to fix.

[Nic30]

I'm glad to help if it's easy to fix.

If you can provide some examples of comments for the tests it would be nice #148

I am closing this issue as you confirmed that the fix is working.