Fixed doc links to point to new SHLS documentation (#58)

Training4/readme.md

@@ -78,16 +78,16 @@ Later parts of the training involve running steps on the Icicle kit board. The f
   - Either a FlashPro6 external programmer or a micro-USB cable for the embedded FlashPro6
   - Ethernet cable for network connection to the board for SSH access
 
-This training will cover the following sections in the [SmartHLS user guide](https://microchiptech.github.io/fpga-hls-docs/): [SoC
-Features](https://microchiptech.github.io/fpga-hls-docs/userguide.html#soc-features),
+This training will cover the following sections in the [SmartHLS user guide](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-995D69CF-ACC7-4CB0-9635-4434A765470E.html): [SoC
+Features](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-7324A022-0DE8-45E9-9FF0-E06D6CC7AD40.html),
 [AXI4 Initiator
-Interface](https://microchiptech.github.io/fpga-hls-docs/userguide.html#axi4-initiator-interface),
+Interface](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-93A05651-C06B-4805-94D3-0443DC0FED4E.html),
 [AXI4Target
-Interface](https://microchiptech.github.io/fpga-hls-docs/userguide.html#axi4-target-interface),
+Interface](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-16F30D96-8744-48F6-BD42-AC01ED5460ED.html),
 [Driver Functions for AXI4
-Target](https://microchiptech.github.io/fpga-hls-docs/userguide.html#driver-functions-for-axi4-target),
+Target](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-7BBF0DBC-AA2A-4593-9B3F-65EDD8520ACE.html),
 and [User-defined
-SmartDesigns](https://microchiptech.github.io/fpga-hls-docs/userguide.html#user-defined-smartdesigns).
+SmartDesigns](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-8CD9C2D1-7FF3-4C70-8CB7-364597AFDAD7.html).
 
 
 ![](.//media/image3.png) We will use this cursor symbol throughout this tutorial to indicate sections where you need to perform actions to follow along.
@@ -299,7 +299,7 @@ flow on the C++ (compile/run/debug). Then we apply HLS constraints using
 SmartHLS C++ pragmas. These include HLS constraints covered in previous
 trainings such as the target clock period, loop optimizations, and
 memory configuration. For more details see our [optimization
-guide](https://microchiptech.github.io/fpga-hls-docs/optimizationguide.html).
+guide](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-8B9C18AF-E1F4-400A-A369-2668F3632CF5.html).
 
 There are new SmartHLS **interface** pragmas used to specify the data
 transfer method for each top-level function argument. These pragmas
@@ -308,7 +308,7 @@ of the SoC. Figure 6‑10 below contains a summary of the SmartHLS pragmas
 used in the vector-add example. More details on the interfaces will be
 covered in the [SoC Data Transfer Methods](#soc-data-transfer-methods) section. For a complete pragma reference, see our
 [pragma
-guide](https://microchiptech.github.io/fpga-hls-docs/pragmas.html).
+guide](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-B3D89018-0850-487C-A242-A433094D720F.html).
 
 In Figure 6‑9, after specifying the argument interfaces, we can compile
 the software into a hardware IP core using SmartHLS, and review reports
@@ -432,7 +432,7 @@ accelerator will store the data in local memory blocks. The
 `num_elements` field specifies the length of the array that will be
 transferred for each argument. For more information on the required
 pragmas and tradeoffs, please see our [pragma
-manual](https://microchiptech.github.io/fpga-hls-docs/pragmas.html#memory-interface-for-pointer-argument).
+manual](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-37FB7C46-32B5-4CAF-8CA2-3B7F37B7E7B9.html).
 
 In this example, we separated the core C++ algorithm into the
 `vector_add_sw` function. We can then call this function from multiple
@@ -529,7 +529,7 @@ by both the software testbench and hardware functions. I/O memories
 become memory interfaces of the top-level module for the generated
 hardware. For more information on interfaces, please refer to [Top-Level
 RTL
-Interface](https://microchiptech.github.io/fpga-hls-docs/userguide.html#rtl-interface).
+Interface](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-E9EA34CC-B155-4F12-AFFC-B972E037469F.html).
 
 The “I/O Memories” table is shown in Figure 6‑15 and has an entry for
 each top-level function argument, which each have a data width of
@@ -755,7 +755,7 @@ file implements the driver functions. The driver functions are generated
 for arguments and module control if they are configured to use AXI4
 target interface. Figure 6‑22 summarizes the different categories of
 driver functions. Please visit [Driver Functions for AXI4
-Target](https://microchiptech.github.io/fpga-hls-docs/userguide.html#driver-functions-for-axi4-target)
+Target](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-7BBF0DBC-AA2A-4593-9B3F-65EDD8520ACE.html)
 section of our user guide for a more detailed explanation.
 
 <table>
@@ -1112,7 +1112,7 @@ data transfers between the DDR and the accelerator. Any additional
 accelerators would be connected to the same AXI interconnect. For more
 information on the architecture of the Reference SoC, please see our
 [user
-guide](https://microchiptech.github.io/fpga-hls-docs/hwarchitecture.html#smarthls-reference-soc).
+guide](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-0B124EE7-BB34-4CF3-A591-9658F121B533.html).
 
 We can simplify the SmartDesign visualization by clicking
 ![](.//media/image38.png)Hide Nets, ![](.//media/image39.png)Compress
@@ -1145,7 +1145,7 @@ to accelerator’s on-chip memory buffer, or the data can be accessed
 directly in DDR by the accelerator. Any access to DDR, whether data is
 copied or accessed directly, goes through the MSS data cache to maintain
 cache coherency. See the [SoC Data Transfer
-Methods](https://microchiptech.github.io/fpga-hls-docs/userguide.html#soc-data-transfer-methods)
+Methods](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-212067DF-C1B6-4C22-ADDD-3C306CE990E5.html)
 user guide section for further reference.
 
 #### CPU Copy: AXI Target
@@ -1267,7 +1267,7 @@ the data for argument "`a`" with the AXI initiator interface as shown in
 Figure 6‑37. If the `ptr_addr_interface` is not specified, for example
 for argument b, SmartHLS will use the default interface type defined on
 line 123 (`axi_target`). See the [AXI4 Initiator
-Interface](https://microchiptech.github.io/fpga-hls-docs/userguide.html#axi4-initiator-interface)
+Interface](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-93A05651-C06B-4805-94D3-0443DC0FED4E.html)
 section of the user guide.
 
 If users specify the `ptr_addr_interface` or any other interface type as
@@ -1357,7 +1357,7 @@ Figure 6‑42.
 DMA Copy mode and Accelerator Direct Access require the memory to be
 allocated using the `hls_malloc` function from the [SmartHLS Memory
 Allocation
-Library](https://microchiptech.github.io/fpga-hls-docs/userguide.html#memory-allocation-library)
+Library](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-8246D542-5D26-420C-9418-6D798FDFC215.html)
 to keep data in physically contiguous memory for the DMA engine. Using
 `hls_malloc` prevents splitting data across different virtual memory
 pages in physical memory. The accelerators and DMA engine do not perform
@@ -1388,7 +1388,7 @@ SoC reference project is generated.
 
 ![](.//media/image3.png) To prepare your Icicle kit for use with
 SmartHLS, follow the [Icicle Setup
-Instructions](https://microchiptech.github.io/fpga-hls-docs/icicle_setup.html)
+Instructions](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-1F9BA312-87A9-43F0-A66E-B83D805E3F02.html)
 and note down the IP of the board.
 
 ![](.//media/image3.png)Create a new file named `Makefile.user` by right
@@ -1412,7 +1412,7 @@ SmartHLS reads in `Makefile.user` where users can define and modify
 options such as compiler and linker flags. For example, users can modify
 `USER_CXX_FLAG` to append additional C++ compilation flags for their
 project. Visit the [Makefile
-Variable](https://microchiptech.github.io/fpga-hls-docs/userguide.html#makefile-variables)
+Variable](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-398C5B20-F31F-4C97-AA81-DDDC0BE0F469.html)
 section of our user guide for a full list of predefined user flags and
 their uses.
 
@@ -1622,7 +1622,7 @@ set_parameter SOC_CPU_MEM_SIZE            0x60000000
 <p align="center">Figure 8‑3 Default Parameter Values for Integrating SmartHLS</p>
 
 Users can change the default parameters by [creating a
-*custom\_config.tcl*](https://microchiptech.github.io/fpga-hls-docs/constraintsmanual.html?highlight=custom%20tcl#set-custom-config-file-1)
+*custom\_config.tcl*](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-3636C6BE-3977-4267-A5DF-A514D1A46BE3.html)
 file inside their HLS project. For example, if we wanted to change the
 `SOC_FABRIC_BASE_ADDRESS` to start at `0x70100000`, we would include the
 following in our *custom\_config.tcl* file:
@@ -1723,7 +1723,7 @@ As in the [Vector Add On-Board section](#running-vector-add-reference-soc-genera
 a Linux image needs to be flashed to the eMMC memory in
 the Icicle board. If users have already flashed the Linux image as
 described in the [Icicle Setup
-Guide](https://microchiptech.github.io/fpga-hls-docs/icicle_setup.html),
+Guide](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-1F9BA312-87A9-43F0-A66E-B83D805E3F02.html),
 this section may be skipped, and users may move on to [this section](#extract-the-icicle-kit-reference-design-files). A
 similar procedure can be followed for the user’s own Linux image when
 integrating SmartHLS design into their own existing system.
@@ -1736,7 +1736,7 @@ from [PolarFire SoC Yocto BSP
 .
 
 ![](.//media/image3.png)Follow the instructions on [Icicle Setup
-Guide](https://microchiptech.github.io/fpga-hls-docs/icicle_setup.html)
+Guide](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-1F9BA312-87A9-43F0-A66E-B83D805E3F02.html)
 for setting the Icicle kit. As explained in the guide, when flashing the
 Icicle board (Step 5 in the Icicle Setup Guide), use
 `core-image-minimal-dev-icicle-kit-es.wic.gz` that you have downloaded in
@@ -2028,7 +2028,7 @@ the newly added Linux image.
 
 ![](.//media/image3.png) After the board has successfully booted, you
 can connect using a serial terminal. Connect in the same
-[manner](https://microchiptech.github.io/fpga-hls-docs/icicle_setup.html#step-7-accessing-linux-on-board-and-determining-the-ip-address)
+[manner](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-88244281-BA99-4B1D-9E38-43EE07745978.html)
 as the serial terminal used during the writing of the Linux image,
 except this time using channel 1 (`/dev/ttyUSB1`on Linux,
 and `Interface 1` on Windows), you should see a login screen:
@@ -2204,7 +2204,7 @@ SoC, we already have [programmed our Custom SoC bitstream to the FPGA](#programm
 `Makefile.user` defines various options related to compiling and running
 the compiled program. Figure 8‑26 is a snippet of `Makefile.user`
 containing the runtime settings. Visit the [Makefile
-Variable](https://microchiptech.github.io/fpga-hls-docs/userguide.html#makefile-variables)
+Variable](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-398C5B20-F31F-4C97-AA81-DDDC0BE0F469.html)
 section of our user guide for a full list of predefined user flags and
 their uses. Important: Ensure that `SRCS` is set to
 `main_variables/main.simple.cpp`.
@@ -2397,7 +2397,7 @@ Running with hardware module, the CPU utilization is about 11%:
 <p align="center">Figure 8‑33 CPU Usage when Running with Accelerators</p></p>
 
 SmartHLS has a TCL parameter called
-[SOC\_POLL\_DELAY](https://microchiptech.github.io/fpga-hls-docs/userguide.html?highlight=soc_poll_delay#user-defined-smartdesigns)
+[SOC\_POLL\_DELAY](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-8CD9C2D1-7FF3-4C70-8CB7-364597AFDAD7.html)
 with a value specified in microseconds. This parameter is used for
 controlling how often the hardware driver polls the module to check for
 completion. Sometimes for long running tasks, the MSS only needs to
@@ -2449,7 +2449,7 @@ different call in main.non-blocking.cpp as shown in Figure 8‑34.
 ```
 <p align="center">Figure 8‑34 Main Execution Loop of main.non-blocking.cpp</p>
 
-[HAS\_ACCELERATOR](https://microchiptech.github.io/fpga-hls-docs/userguide.html?highlight=has_accelerator#has-accelerator-macro)
+[HAS\_ACCELERATOR](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-6818975C-389F-427C-B913-65A667001A99.html#GUID-6818975C-389F-427C-B913-65A667001A99__SECTION_YMS_QTJ_NYB)
 is a SmartHLS defined macro that indicates whether the program is
 compiled with accelerators or not. The `*_write_input_and_start()`
 functions send the data to the hardware accelerator and start the
@@ -2546,7 +2546,7 @@ function is a classic example of the producer-consumer pattern. The in
 data is received from the AXI target interface and passed to each stage
 of the computation, namely `invert` and `threshold_to_zero`. We use a
 thread
-([hls::thread](https://microchiptech.github.io/fpga-hls-docs/optimizationguide.html#inferring-streaming-hardware-via-producer-consumer-pattern-with-threads))
+([hls::thread](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-D3311A34-24FB-4A0D-8A49-A0A56F71410F.html))
 for each stage as each stage can be run independently as long as there
 are data available. The two stages are connected via a fifo between
 them.

risc-v-demo/Readme-compile.md

@@ -347,7 +347,7 @@ Finally, the `common` directory has some common bitmaps and helper code.
 
 ## References:
 
-[SmartHLS User Guide](https://microchiptech.github.io/fpga-hls-docs/)
+[SmartHLS User Guide](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-995D69CF-ACC7-4CB0-9635-4434A765470E.html)
 
 [PolarFire_SoC_FPGA_H264_Video_Streaming_Over_Ethernet_Application_Note_AN4529.pdf](https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ApplicationNotes/ApplicationNotes/PolarFire_SoC_FPGA_H264_Video_Streaming_Over_Ethernet_Application_Note_AN4529.pdf)
 

risc-v-demo/Readme.md

@@ -295,7 +295,7 @@ now updated.
 
 **NOTE:** 
 As an additional reference about terminals and the image flashing process,
-you can check the [IcicleKit Setup Instructions](https://microchiptech.github.io/fpga-hls-docs/icicle_setup.html). 
+you can check the [IcicleKit Setup Instructions](https://onlinedocs.microchip.com/oxy/GUID-AFCB5DCC-964F-4BE7-AA46-C756FA87ED7B-en-US-11/GUID-1F9BA312-87A9-43F0-A66E-B83D805E3F02.html). 
 It includes instructions and additional screen captures for the PolarFire Icicle 
 kit but the the process is similar in the PolarFire SoC Video Kit, except they 
 use different image files.