z80_isa.csv

Z80 Instruction Set Overview																																																		
Regs: A, (B,C), (D,E), (H,L), PC, SP, IX, IY, F { C, N, P/V, H, Z, S }, I=Interrupt vectors, R=Memory refresh																																																		
AM: I=Immediate, IE=Immediate Extended, MPZA=Modified Page Zero, L=Relative Jump, E=Extended, EJ=Extended Jump, EP=Extended Port, X=Indexed, R=Register, M=Implied, RI=Register Indirect, B=Bit																																																		
																					M1					M2					M3					M4					M5					M6				
OP Code	ASM	OP1	OP2	AM1	AM2	Offset	Bit pattern for offset									M Cycles	T States	Flags affect	Operation	Notes	T1	T2	T3	T4	T5	T1	T2	T3	T4	T5	T1	T2	T3	T4	T5	T1	T2	T3	T4	T5	T1	T2	T3	T4	T5	T1	T2	T3	T4	T5
LD	LD r,s	{r}	{s}	R	R	0	0	1	r	r	r	s	s	s		1	4		r <- s		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{s}.OE, TMP.L	TMP.OE.DBUS, {r}.L																									
																																																		
LD	LD r,n	{r}	{n}	R	I	0	0	0	r	r	r	1	1	0		2	7 (4,3)		r <- n		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, {r}.L																						
						1	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD r,(HL)	{r}	(HL)	R	RI	0	0	1	r	r	r	1	1	0		2	7 (4,3)		r <- (HL)	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, {r}.L																						
																																																		
LD	LD r,(IX+d)	{r}	(IX+{d})	R	X	0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)		r <- (IX+d)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, {r}.L											
						1	0	1	r	r	r	1	1	0																																				
						2	d	d	d	d	d	d	d	d																																				
																																																		
LD	LD r,(IY+d)	{r}	(IY+{d})	R	X	0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)		r <- (IY+d)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, {r}.L											
						1	0	1	r	r	r	1	1	0																																				
						2	d	d	d	d	d	d	d	d																																				
																																																		
LD	LD (HL),r	(HL)	{r}	RI	R	0	0	1	1	1	0	r	r	r		2	7 (4,3)		(HL) <- r		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	{r}.OE, DBUF.L.OUT	{r}.OE																						
																																																		
LD	LD (IX+d),r	(IX+{d})	{r}	X	R	0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)		(IX+d) <- r		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L, {r}.OE	{r}.OE, DBUF.L.OUT	{r}.OE											
						1	0	1	1	1	0	r	r	r						The 110 is a reverse reg index?																														
						2	d	d	d	d	d	d	d	d																																				
																																																		
LD	LD (IY+d),r	(IY+{d})	{r}	X	R	0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)		(IY+d) <- r		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L, {r}.OE	{r}.OE, DBUF.L.OUT	{r}.OE											
						1	0	1	1	1	0	r	r	r																																				
						2	d	d	d	d	d	d	d	d																																				
																																																		
LD	LD (HL),n	(HL)	{n}	RI	I	0	0	0	1	1	0	1	1	0	36	3	10 (4,3,3)		(HL) <- n	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, HL.OE, ABUF.L	TMP.OE.DBUS, DBUF.L.OUT	TMP.OE.DBUS	-																
							n	n	n	n	n	n	n	n																																				
																																																		
LD	LD (IX+d),n	(IX+{d})	{n}	X	I	0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)		(IX+d) <- n		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, DISP.L.DBUS, DISP.L.X	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.OE, ABUF.L	TMP.OE.DBUS, DBUF.L.OUT	TMP.OE.DBUS	-	-					
						1	0	0	1	1	0	1	1	0	36																																			
						2	d	d	d	d	d	d	d	d																																				
						3	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD (IY+d),n	(IY+{d})	{n}	X	I	0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)		(IY+d) <- n		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, DISP.L.DBUS, DISP.L.Y	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.OE, ABUF.L	TMP.OE.DBUS, DBUF.L.OUT	TMP.OE.DBUS	-	-					
						1	0	0	1	1	0	1	1	0	36																																			
						2	d	d	d	d	d	d	d	d																																				
						3	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD A,(BC)	A	(BC)	R	RI	0	0	0	0	0	1	0	1	0	0A	2	7 (4,3)		A <- (BC)	(BC) or (DE) ?	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	BC.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, A.L	-	-																				
																																																		
LD	LD A,(DE)	A	(DE)	R	RI	0	0	0	0	1	1	0	1	0	1A	2	7 (4,3)		A <- (DE)	Register source or dest?	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	DE.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, A.L	-	-																				
																																																		
LD	LD A,(nn)	A	({nn})	R	E	0	0	0	1	1	1	0	1	0	3A	4	13 (4,3,3,3)		A <- (nn)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, ABUS.H.L.DBUS	-	-	TMP.OE.DBUS, ABUS.L.L.DBUS	ABUF.L	DBUF.L.IN	DBUF.L.IN, A.L	-										
						1	n	n	n	n	n	n	n	n																																				
						2	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD (BC),A	(BC)	A	RI	R	0	0	0	0	0	0	0	1	0	02	2	7 (4,3)		(BC) <- A		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	BC.OE, ABUF.L	A.OE.DBUS, DBUF.L.OUT	A.OE.DBUS	-	-																				
																																																		
LD	LD (DE),A	(DE)	A	RI	R	0	0	0	0	1	0	0	1	0	12	2	7 (4,3)		(DE) <- A		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	DE.OE, ABUF.L	A.OE.DBUS, DBUF.L.OUT	A.OE.DBUS	-	-																				
																																																		
LD	LD (nn),A	({nn})	A	E	R	0	0	0	1	1	0	0	1	0	32	4	13 (4,3,3,3)		(nn) <- A		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, ABUS.H.L.DBUS	-	-	TMP.OE.DBUS, ABUS.L.L.DBUS	ABUF.L	A.OE.DBUS, DBUF.L.OUT	A.OE.DBUS	-										
						1	n	n	n	n	n	n	n	n																																				
						2	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD A,I	A	I	R	R	0	1	1	1	0	1	1	0	1	ED	2	9 (4,5)	S,Z,H,P/V,N	A <- Interrupt vector reg		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	I.OE, A.L																				
						1	0	1	0	1	0	1	1	1	57					I or R reg?																														
																																																		
LD	LD A,R	A	R	R	R	0	1	1	1	0	1	1	0	1	ED	2	9 (4,5)	S,Z,H,P/V,N	A <- Memory refresh reg		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	R.OE, A.L																				
						1	0	1	0	1	1	1	1	1	5F																																			
																																																		
LD	LD I,A	I	A	R	R	0	1	1	1	0	1	1	0	1	ED	2	9 (4,5)		Interrupt vector reg <- A		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	A.OE.DBUS, I.L																				
						1	0	1	0	0	0	1	1	1	47																																			
																																																		
LD	LD R,A	R	A	R	R	0	1	1	1	0	1	1	0	1	ED	2	9 (4,5)		Memory refresh reg <- A		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	A.OE.DBUS, R.L																				
						1	0	1	0	0	1	1	1	1	4F																																			
																																																		
LD	LD RR,nn	{RR}	{nn}	R	IE	0	0	0	R	R	0	0	0	1		2	10 (4,3,3)		Register pair <- nn		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, {RR}.L.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, {RR}.H.L	-	-				-	-										
						1	n	n	n	n	n	n	n	n																																				
						2	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD IX,nn	IX	{nn}	R	IE	0	1	1	0	1	1	1	0	1	DD	4	14 (4,4,3,3)		IX <- nn		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, IX.L.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, IX.H.L	-	-										
						1	0	0	1	0	0	0	0	1	21																																			
						2	n	n	n	n	n	n	n	n																																				
						3	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD IY,nn	IY	{nn}	R	IE	0	1	1	1	1	1	1	0	1	FD	4	14 (4,4,3,3)		IY <- nn		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, IY.L.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, IY.H.L	-	-										
						1	0	0	1	0	0	0	0	1	21																																			
						2	n	n	n	n	n	n	n	n																																				
						3	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD HL,(nn)	HL	({nn})	R	E	0	0	0	1	0	1	0	1	0	2A	5	16 (4,3,3,3,3)		H <- (nn+1), L <- (nn)	Register source or dest?	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, ABUS.H.L.DBUS	-	-	TMP.OE.DBUS, ABUS.L.L.DBUS	ABUF.L	DBUF.L.IN	DBUF.L.IN, L.L	-	INC2.P, INC2.L	INC2.P, INC2.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, H.L						
						1	n	n	n	n	n	n	n	n																																				
						2	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD RR,(nn)	{RR}	({nn})	R	E	0	1	1	1	0	1	1	0	1	ED	6	20 (4,4,3,3,3,3)		RRh <- (nn+1), RRl <- (nn)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, ABUS.H.L.DBUS	-	-	TMP.OE.DBUS, ABUS.L.L.DBUS	ABUF.L	DBUF.L.IN	DBUF.L.IN, {RR}.L.L	-	INC2.P, INC2.L	INC2.P, INC2.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, {RR}.H.L	-
						1	0	1	R	R	1	0	1	1																																				
						2	n	n	n	n	n	n	n	n																																				
						3	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD IX,(nn)	IX	({nn})	R	E	0	1	1	0	1	1	1	0	1	DD	6	20 (4,4,3,3,3,3)		IXh <- (nn+1), IXl <- (nn)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, ABUS.H.L.DBUS	-	-	TMP.OE.DBUS, ABUS.L.L.DBUS	ABUF.L	DBUF.L.IN	DBUF.L.IN, IX.L.L	-	INC2.P, INC2.L	INC2.P, INC2.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, IX.H.L	-
						1	0	0	1	0	1	0	1	0	2A																																			
						2	n	n	n	n	n	n	n	n																																				
						3	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD IY,(nn)	IY	({nn})	R	E	0	1	1	1	1	1	1	0	1	FD	6	20 (4,4,3,3,3,3)		IYh <- (nn+1), IYl <- (nn)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, ABUS.H.L.DBUS	-	-	TMP.OE.DBUS, ABUS.L.L.DBUS	ABUF.L	DBUF.L.IN	DBUF.L.IN, IY.L.L	-	INC2.P, INC2.L	INC2.P, INC2.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, IY.H.L	-
						1	0	0	1	0	1	0	1	0	2A																																			
						2	n	n	n	n	n	n	n	n																																				
						3	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD (nn), HL	({nn})	 HL	E	R	0	0	0	1	0	0	0	1	0	22	5	16 (4,3,3,3,3)		(nn+1) <- H, (nn) <- L		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, ABUS.H.L.DBUS	-	-	TMP.OE.DBUS, ABUS.L.L.DBUS	ABUF.L	L.OE, DBUF.L.OUT	-	-	INC2.P, INC2.L	INC2.P, INC2.OE, ABUF.L	H.OE, DBUF.L.OUT	-	-					
						1	n	n	n	n	n	n	n	n																																				
						2	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD (nn), RR	({nn})	 {RR}	E	R	0	1	1	1	0	1	1	0	1	ED	6	20 (4,4,3,3,3,3)		(nn+1) <- RRh, (nn) <-RRl		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, ABUS.H.L.DBUS	-	-	TMP.OE.DBUS, ABUS.L.L.DBUS	ABUF.L	{RR}.L.OE, DBUF.L.OUT	-	-	INC2.P, INC2.L	INC2.P, INC2.OE, ABUF.L	{RR}.H.OE, DBUF.L.OUT	-	-
						1	0	1	R	R	0	0	1	1																																				
						2	n	n	n	n	n	n	n	n																																				
						3	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD (nn), IX	({nn})	 IX	E	R	0	1	1	0	1	1	1	0	1	DD	6	20 (4,4,3,3,3,3)		(nn+1) <- IXh, (nn) <-IXl	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, ABUS.H.L.DBUS	-	-	TMP.OE.DBUS, ABUS.L.L.DBUS	ABUF.L	IX.L.OE, DBUF.L.OUT	-	-	INC2.P, INC2.L	INC2.P, INC2.OE, ABUF.L	IX.H.OE, DBUF.L.OUT	-	-
						1	0	0	1	0	0	0	1	0	22																																			
						2	n	n	n	n	n	n	n	n																																				
						3	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD (nn), IY	({nn})	 IY	E	R	0	1	1	1	1	1	1	0	1	FD	6	20 (4,4,3,3,3,3)		(nn+1) <- IYh, (nn) <-IYl		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, ABUS.H.L.DBUS	-	-	TMP.OE.DBUS, ABUS.L.L.DBUS	ABUF.L	IY.L.OE, DBUF.L.OUT	-	-	INC2.P, INC2.L	INC2.P, INC2.OE, ABUF.L	IY.H.OE, DBUF.L.OUT	-	-
						1	0	0	1	0	0	0	1	0	22																																			
						2	n	n	n	n	n	n	n	n																																				
						3	n	n	n	n	n	n	n	n																																				
																																																		
LD	LD SP,HL	SP	HL	R	R	0	1	1	1	1	1	0	0	1	F9	1	6		SP <- HL		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	HL.H.OE, SP.H.L	HL.L.OE, SP.L.L																								
																																																		
LD	LD SP,IX	SP	IX	R	R	0	1	1	0	1	1	1	0	1	DD	2	10 (4,6)		SP <- IX		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	IX.H.OE, SP.H.L	IX.L.OE, SP.L.L																								
							1	1	1	1	1	0	0	1	F9																																			
																																																		
LD	LD SP,IY	SP	IY	R	R	0	1	1	1	1	1	1	0	1	FD	2	10 (4,6)		SP <- IY		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	IY.H.OE, SP.H.L	IY.L.OE, SP.L.L																								
							1	1	1	1	1	0	0	1	F9																																			
																																																		
PUSH	PUSH QQ	{QQ}		R		0	1	1	Q	Q	0	1	0	1		3	11 (5,3,3)		(SP-1) <- QQh, (SP-2) <- QQl, SP <- SP - 2		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	SP.OE, INC2.N, INC2.L	INC2.N, INC2.OE, SP.L.INC2	SP.OE, ABUF.L,{QQ}.H.OE	{QQ}.H.OE, DBUF.L.OUT, INC2.N, INC2.L	-	-	INC2.N, INC2.OE, SP.L.INC2	SP.OE, ABUF.L,{QQ}.L.OE	{QQ}.L.OE, DBUF.L.OUT	-	-															
																																																		
PUSH	PUSH IX	IX		R		0	1	1	0	1	1	1	0	1	DD	4	15 (4,5,3,3)		(SP-1) <- IXh, (SP-2) <- IXl, SP <- SP - 2	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	SP.OE, INC2.N, INC2.L	INC2.N, INC2.OE, SP.L.INC2	SP.OE, ABUF.L,IX.H.OE	IX.H.OE, DBUF.L.OUT, INC2.N, INC2.L	-	-	INC2.N, INC2.OE, SP.L.INC2	SP.OE, ABUF.L,IX.L.OE	IX.L.OE, DBUF.L.OUT	-	-										
						1	1	1	1	0	0	1	0	1	E5																																			
																																																		
PUSH	PUSH IY	IY		R		0	1	1	1	1	1	1	0	1	FD	4	15 (4,5,3,3)		(SP-1) <- IYh, (SP-2) <- IYl, SP <- SP - 2		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	SP.OE, INC2.N, INC2.L	INC2.N, INC2.OE, SP.L.INC2	SP.OE, ABUF.L,IY.H.OE	IY.H.OE, DBUF.L.OUT, INC2.N, INC2.L	-	-	INC2.N, INC2.OE, SP.L.INC2	SP.OE, ABUF.L,IY.L.OE	IY.L.OE, DBUF.L.OUT	-	-										
						1	1	1	1	0	0	1	0	1	E5																																			
																																																		
POP	POP QQ	{QQ}		R		0	1	1	Q	Q	0	0	0	1		3	10 (4,3,3)		QQl <- (SP), QQh <- (SP+1), SP <- SP + 2		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X		SP.OE, ABUF.L,DBUF.L.IN, INC2.P, INC2.L	DBUF.L.IN, {QQ}.L.L	INC2.P, INC2.OE, SP.L.INC2	-	-	SP.OE, ABUF.L,DBUF.L.IN, INC2.P, INC2.L	DBUF.L.IN, {QQ}.H.L	INC2.P, INC2.OE, SP.L.INC2	-	-															
																																																		
POP	POP IX	IX		R		0	1	1	0	1	1	1	0	1	DD	4	14 (4,4,3,3)		IXl <- (SP), IXh <- (SP+2), SP <- SP + 2		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X		SP.OE, ABUF.L,DBUF.L.IN, INC2.P, INC2.L	DBUF.L.IN, IX.L.L	INC2.P, INC2.OE, SP.L.INC2	-	-	SP.OE, ABUF.L,DBUF.L.IN, INC2.P, INC2.L	DBUF.L.IN, IX.H.L	INC2.P, INC2.OE, SP.L.INC2	-	-										
						1	1	1	1	0	0	0	0	1	E1																																			
																																																		
POP	POP IY	IY		R		0	1	1	1	1	1	1	0	1	FD	4	14 (4,4,3,3)		IHl <- (SP), IHh <- (SP+2), SP <- SP + 2		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X		SP.OE, ABUF.L,DBUF.L.IN, INC2.P, INC2.L	DBUF.L.IN, IY.L.L	INC2.P, INC2.OE, SP.L.INC2	-	-	SP.OE, ABUF.L,DBUF.L.IN, INC2.P, INC2.L	DBUF.L.IN, IY.H.L	INC2.P, INC2.OE, SP.L.INC2	-	-										
						1	1	1	1	0	0	0	0	1	E1																																			
																																																		
EX	EX DE,HL	DE	HL	R	R	0	1	1	1	0	1	0	1	1	EB	1	4		DE <-> HL		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	DE.HL.EX	-																									
																																																		
EX	EX AF,AF'	AF	AF'	R	R	0	0	0	0	0	1	0	0	0	08	1	4		AF <-> AF'		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	AF.AF.EX	-																									
																																																		
EXX	EXX					0	1	1	0	1	1	0	0	1	D9	1	4		(BC) <-> (BC'), (DE) <-> (DE'), (HL) <-> (HL')		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	BCDEHL.EX	-																									
																																																		
EX	EX (SP),HL	(SP)	HL	RI	R	0	1	1	1	0	0	0	1	1	E3	5	19 (4,3,4,3,5)		L <-> (SP), H <-> (SP+1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	SP.OE, ABUF.L,L.OE, TMP.L	-	DBUF.L.IN, L.L, INC2.P, INC2.L	-	-	TMP.OE.DBUS, DBUF.L.OUT	TMP.OE.DBUS, DBUF.L.OUT	-	-	-	INC2.OE, ABUF.L, H.OE, TMP.L	-	DBUF.L.IN, H.L	-	-	TMP.OE.DBUS, DBUF.L.OUT	TMP.OE.DBUS, DBUF.L.OUT	-	-	-					
																																																		
EX	EX (SP),IX	(SP)	IX	RI	R	0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,4,3,5)		IXl <-> (SP), IXh <-> (SP+1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	SP.OE, ABUF.L,IX.L.OE, TMP.L	-	DBUF.L.IN, IX.L.L, INC2.P, INC2.L	-	-	TMP.OE.DBUS, DBUF.L.OUT	TMP.OE.DBUS, DBUF.L.OUT	-	-	-	INC2.OE, ABUF.L, IX.H.OE, TMP.L	-	DBUF.L.IN, IX.H.L	-	-	TMP.OE.DBUS, DBUF.L.OUT	TMP.OE.DBUS, DBUF.L.OUT	-	-	-					
							1	1	1	0	0	0	1	1	E3																																			
																																																		
EX	EX (SP),IY	(SP)	IY	RI	R	0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,4,3,5)		IYl <-> (SP), IYh <-> (SP+1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	SP.OE, ABUF.L,IY.L.OE, TMP.L	-	DBUF.L.IN, IY.L.L, INC2.P, INC2.L	-	-	TMP.OE.DBUS, DBUF.L.OUT	TMP.OE.DBUS, DBUF.L.OUT	-	-	-	INC2.OE, ABUF.L, IY.H.OE, TMP.L	-	DBUF.L.IN, IY.H.L	-	-	TMP.OE.DBUS, DBUF.L.OUT	TMP.OE.DBUS, DBUF.L.OUT	-	-	-					
							1	1	1	0	0	0	1	1	E3																																			
																																																		
LDI	LDI					0	1	1	1	0	1	1	0	1	ED	4	16 (4,4,3,5)	H,P/V,N	(DE) <- (HL), DE <- DE + 1, HL <- HL + 1, BC <- BC -1																															
						1	1	0	1	0	0	0	0	0	A0																																			
																																																		
LDIR	LDIR					0	1	1	1	0	1	1	0	1	ED	5	21 (4,4,3,5,5)	H,P/V,N	(DE) <- (HL), DE <- DE + 1, HL <- HL + 1, BC F<-> BC -1																															
						1	1	0	1	1	0	0	0	0	B0																																			
																																																		
LDD	LDD					0	1	1	1	0	1	1	0	1	ED	4	16 (4,4,3,5)	H,P/V,N	(DE) <- (HL), DE <- DE -1, HL <- HL-1, BC <- BC-1																															
						1	1	0	1	0	1	0	0	0	A8																																			
																																																		
LDDR	LDDR					0	1	1	1	0	1	1	0	1	ED	5	21 (4,4,3,5,5)	H,P/V,N	(DE) <- (HL), DE <- D <- 1, HL <- HL-1, BC <- BC-1																															
						1	1	0	1	1	1	0	0	0	B8																																			
																																																		
CPI	CPI					0	1	1	1	0	1	1	0	1	ED	4	16 (4,4,3,5)	S,Z,H,P/V,N	A =?= (HL), HL <- HL +1, BC <- BC -1																															
						1	1	0	1	0	0	0	0	1	A1																																			
																																																		
CPIR	CPIR					0	1	1	1	0	1	1	0	1	ED	5	21 (4,4,3,5,5)	S,Z,H,P/V,N	A =?= (HL), HL <- HL+1, BC <- BC-1																															
						1	1	0	1	1	0	0	0	1	B1																																			
																																																		
CPD	CPD					0	1	1	1	0	1	1	0	1	ED	4	16 (4,4,3,5)	S,Z,H,P/V,N	A =?= (HL), HL <- HL -1, BC <- BC -1																															
						1	1	0	1	0	1	0	0	1	A9																																			
																																																		
CPDR	CPDR					0	1	1	1	0	1	1	0	1	ED	5	21 (4,4,3,5,5)	S,Z,H,P/V,N	A =?= (HL), HL <- HL -1, BC <- BC-1																															
						1	1	0	1	1	1	0	0	1	B9																																			
																																																		
ADD	ADD A,r	A	{r}	R	R	0	1	0	0	0	0	r	r	r		1	4	S,Z,H,P/V,N,C	A <- A + r		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{r}.OE, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.ADD, ALU.OE, A.L																									
																																																		
ADD	ADD A,n	A	{n}	R	I	0	1	1	0	0	0	1	1	0	C6	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A + n	Set for immediate??	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.ADD, ALU.OE, A.L																					
						1	n	n	n	n	n	n	n	n						No, only for ADD block like op codes																														
																																																		
ADD	ADD A,(HL)	A	(HL)	R	RI	0	1	0	0	0	0	1	1	0	86	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A + (HL)	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.ADD, ALU.OE, A.L																					
																																																		
ADD	ADD A,(IX+d)	A	(IX+{d})	R	X	0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A + (IX+d)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.ADD, ALU.OE, A.L										
						1	1	0	0	0	0	1	1	0	86																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
ADD	ADD A,(IY+d)	A	(IY+{d})	R	X	0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A + (IY+d)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.ADD, ALU.OE, A.L										
						1	1	0	0	0	0	1	1	0	86																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
ADC	ADC A,r	A	{r}	R	R	0	1	0	0	0	1	r	r	r		1	4	S,Z,H,P/V,N,C	A <- A + r + CY	Change to block ADD	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{r}.OE, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.ADC, ALU.OE, A.L																									
																																																		
ADC	ADC A,n	A	{n}	R	I	0	1	1	0	0	1	1	1	0	CE	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A + n + CY	Set for immediate??	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.ADC, ALU.OE, A.L																					
						1	n	n	n	n	n	n	n	n																																				
																																																		
ADC	ADC A,(HL)	A	(HL)	R	RI	0	1	0	0	0	1	1	1	0	8E	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A + (HL) + CY	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.ADC, ALU.OE, A.L																					
																																																		
ADC	ADC A,(IX+d)	A	(IX+{d})	R	X	0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A + (IX+d) + CY	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.ADC, ALU.OE, A.L										
						1	1	0	0	0	1	1	1	0	8E																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
ADC	ADC A,(IY+d)	A	(IY+{d})	R	X	0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A + (IY+d) + CY		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.ADC, ALU.OE, A.L										
						1	1	0	0	0	1	1	1	0	8E																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
SUB	SUB r	{r}		R		0	1	0	0	1	0	r	r	r		1	4	S,Z,H,P/V,N,C	A <- A - r	Change to block ADD	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{r}.OE, TMP.L, A.OE, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.SUB, ALU.OE, A.L																									
																																																		
SUB	SUB n	{n}		I		0	1	1	0	1	0	1	1	0	D6	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A - n	Set for immediate??	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.SUB, ALU.OE, A.L																					
						1	n	n	n	n	n	n	n	n																																				
																																																		
SUB	SUB (HL)	(HL)		RI		0	1	0	0	1	0	1	1	0	96	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A - (HL)	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.SUB, ALU.OE, A.L																					
																																																		
SUB	SUB (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A - (IX+d)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.SUB, ALU.OE, A.L										
						1	1	0	0	1	0	1	1	0	96																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
SUB	SUB (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A + (IY+d)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.SUB, ALU.OE, A.L										
						1	1	0	0	1	0	1	1	0	96																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
SBC	SBC A,r	A	{r}	R	R	0	1	0	0	1	1	r	r	r		1	4	S,Z,H,P/V,N,C	A <- A + r + CY	Change to block ADD	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{r}.OE, TMP.L, A.OE, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.SBC, ALU.OE, A.L																									
																																																		
SBC	SBC A,n	A	{n}	R	I	0	1	1	0	1	1	1	1	0	DE	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A + n + CY	Set for immediate??	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.SBC, ALU.OE, A.L																					
						1	n	n	n	n	n	n	n	n																																				
																																																		
SBC	SBC A,(HL)	A	(HL)	R	RI	0	1	0	0	1	1	1	1	0	9E	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A + (HL) + CY	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.SBC, ALU.OE, A.L																					
																																																		
SBC	SBC A,(IX+d)	A	(IX+{d})	R	X	0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A + (IX+d) + CY	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.SBC, ALU.OE, A.L										
						1	1	0	0	1	1	1	1	0	9E																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
SBC	SBC A,(IY+d)	A	(IY+{d})	R	X	0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A + (IY+d) + CY		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.SBC, ALU.OE, A.L										
						1	1	0	0	1	1	1	1	0	9E																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
AND	AND r	{r}		R		0	1	0	1	0	0	r	r	r		1	4	S,Z,H,P/V,N,C	A <- A & r	Change to block ADD	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{r}.OE, TMP.L, A.OE, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.AND, ALU.OE, A.L																									
																																																		
AND	AND n	{n}		I		0	1	1	1	0	0	1	1	0	E6	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A & n	Set for immediate??	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.AND, ALU.OE, A.L																					
						1	n	n	n	n	n	n	n	n																																				
																																																		
AND	AND (HL)	(HL)		RI		0	1	0	1	0	0	1	1	0	A6	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A & (HL)	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.AND, ALU.OE, A.L																					
																																																		
AND	AND (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A & (IX+d)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.AND, ALU.OE, A.L										
						1	1	0	1	0	0	1	1	0	A6																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
AND	AND (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A & (IY+d)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.AND, ALU.OE, A.L										
						1	1	0	1	0	0	1	1	0	A6																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
OR	OR r	{r}		R		0	1	0	1	1	0	r	r	r		1	4	S,Z,H,P/V,N,C	A <- A | r	Change to block OR	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{r}.OE, TMP.L, A.OE, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.OR, ALU.OE, A.L																									
																																																		
OR	OR n	{n}		I		0	1	1	1	1	0	1	1	0	F6	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A | n	Set for immediate??	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.OR, ALU.OE, A.L																					
						1	n	n	n	n	n	n	n	n																																				
																																																		
OR	OR (HL)	(HL)		RI		0	1	0	1	1	0	1	1	0	B6	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A | (HL)	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.OR, ALU.OE, A.L																					
																																																		
OR	OR (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A | (IX+d)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.OR, ALU.OE, A.L										
						1	1	0	1	1	0	1	1	0	B6																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
OR	OR (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A | (IY+d)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.OR, ALU.OE, A.L										
						1	1	0	1	1	0	1	1	0	B6																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
XOR	XOR r	{r}		R		0	1	0	1	0	1	r	r	r		1	4	S,Z,H,P/V,N,C	A <- A + r	Change to block OR	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{r}.OE, TMP.L, A.OE, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.XOR, ALU.OE, A.L																									
																																																		
XOR	XOR n	{n}		I		0	1	1	1	0	1	1	1	0	EE	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A + n	Set for immediate??	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.XOR, ALU.OE, A.L																					
						1	n	n	n	n	n	n	n	n																																				
																				Wrong opcodes in z80cpu_um.pdf!																														
XOR	XOR (HL)	(HL)		RI		0	1	0	1	0	1	1	1	0	AE	2	7 (4,3)	S,Z,H,P/V,N,C	A <- A + (HL)	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.XOR, ALU.OE, A.L																					
																																																		
XOR	XOR (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A + (IX+d)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.XOR, ALU.OE, A.L										
						1	1	0	1	0	1	1	1	0	AE																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
XOR	XOR (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	A <- A + (IY+d)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.XOR, ALU.OE, A.L										
						1	1	0	1	0	1	1	1	0	AE																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
CP	CP r	{r}		R		0	1	0	1	1	1	r	r	r		1	4	S,Z,H,P/V,N,C	Z <-  A = r		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{r}.OE, TMP.L, A.OE, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.CP, ALU.OE																									
																																																		
CP	CP n	{n}		I		0	1	1	1	1	1	1	1	0	FE	2	7 (4,3)	S,Z,H,P/V,N,C	Z <-  A = n	Set for immediate??	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.CP, ALU.OE																					
						1	n	n	n	n	n	n	n	n																																				
																																																		
CP	CP (HL)	(HL)		RI		0	1	0	1	1	1	1	1	0	BE	2	7 (4,3)	S,Z,H,P/V,N,C	Z <-  A = (HL)	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.CP, ALU.OE																					
																																																		
CP	CP (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	Z <-  A = (IX+d)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.CP, ALU.OE										
						1	1	0	1	1	1	1	1	0	BE																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
CP	CP (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	5	19 (4,4,3,5,3)	S,Z,H,P/V,N,C	Z <-  A = (IY+d)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.CP, ALU.OE										
						1	1	0	1	1	1	1	1	0	BE																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
INC	INC r	{r}		R		0	0	0	r	r	r	1	0	0		1	4	S,Z,H,P/V,N	r <- r + 1		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{r}.OE, TMP.L	TMP.OE.ALU, ALU.OP.INC, ALU.OE, {r}.L																									
																																																		
INC	INC (HL)	(HL)		RI		0	0	0	1	1	0	1	0	0	34	3	11 (4,4,3)	S,Z,H,P/V,N	(HL) <- (HL) + 1	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.INC, ALU.OE		HL.OE, ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE																	
																																																		
INC	INC (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,4,3,5)	S,Z,H,P/V,N	(IX+d) <- (IX+d) + 1	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.INC, ALU.OE	DISP.OE, ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE							
						1	0	0	1	1	0	1	0	0	34																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
INC	INC (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,4,3,5)	S,Z,H,P/V,N	(IY+d) <- (IY+d) + 1		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.INC, ALU.OE	DISP.OE, ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE							
						1	0	0	1	1	0	1	0	0	34																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
DEC	DEC r	{r}		R		0	0	0	r	r	r	1	0	1		1	4	S,Z,H,P/V,N	r <- r - 1	Change to block INC	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{r}.OE, TMP.L	TMP.OE.ALU, ALU.OP.DEC, ALU.OE, {r}.L																									
																																																		
DEC	DEC (HL)	(HL)		RI		0	0	0	1	1	0	1	0	1	35	3	11 (4,4,3)	S,Z,H,P/V,N	(HL) <- (HL) - 1	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.DEC, ALU.OE		HL.OE, ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE																	
																																																		
DEC	DEC (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,4,3,5)	S,Z,H,P/V,N	(IX+d) <- (IX+d) - 1	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.DEC, ALU.OE	DISP.OE, ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE							
						1	0	0	1	1	0	1	0	1	35																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
DEC	DEC (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,4,3,5)	S,Z,H,P/V,N	(IY+d) <- (IY+d) - 1		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.DEC, ALU.OE	DISP.OE, ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE							
						1	0	0	1	1	0	1	0	1	35																																			
						2	d	d	d	d	d	d	d	d																																				
																																																		
DAA	DAA					0	0	0	1	0	0	1	1	1	27	1	4	S,Z,H,P/V,C	A <- BCD adjust (A,F)																															
																																																		
CPL	CPL					0	0	0	1	0	1	1	1	1	2F	1	4	H,N	A <- /A																															
																																																		
NEG	NEG					0	1	1	1	0	1	1	0	1	ED	2	8 (4,4)	S,Z,H,P/V,N,C	A <- 0 - A																															
						1	0	1	0	0	0	1	0	0	44																																			
																																																		
CCF	CCF					0	0	0	1	1	1	1	1	1	3F	1	4	H,N,C	CY <- /CY		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	F.CY.INV	-																									
																																																		
SCF	SCF					0	0	0	1	1	0	1	1	1	37	1	4	H,N,C	CY <- 1		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	F.CY.SET	-																									
																																																		
NOP	NOP					0	0	0	0	0	0	0	0	0	00	1	4		--		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	PC.OE																										
																																																		
HALT	HALT					0	0	1	1	1	0	1	1	0	76	1	4		---																															
																																																		
DI	DI					0	1	1	1	1	0	0	1	1	F3	1	4		IFF <- 0																															
																																																		
EI	EI					0	1	1	1	1	1	0	1	1	FB	1	4		IFF <- 1																															
																																																		
IM	IM 0	0				0	1	1	1	0	1	1	0	1	ED	2	8 (4,4)		IM <- 0																															
						1	0	1	0	0	0	1	1	0	46																																			
																																																		
IM	IM 1	1				0	1	1	1	0	1	1	0	1	ED	2	8 (4,4)		IM <- 1																															
						1	0	1	0	1	0	1	1	0	56																																			
																																																		
IM	IM 2	2				0	1	1	1	0	1	1	0	1	ED	2	8 (4,4)		IM <- 2																															
						1	0	1	0	1	1	1	1	0	5E																																			
																																																		
ADD	ADD HL,RR	HL	{RR}	R	R	0	0	0	R	R	1	0	0	1		3	11 (4,4,3)	H,N,C	HL <- HL + RR																															
																																																		
ADC	ADC HL,RR	HL	{RR}	R	R	0	1	1	1	0	1	1	0	1	ED	3	11 (4,4,3)	S,Z,H,P/V,N,C	HL <- HL + RR + CY																															
						1	0	1	R	R	1	0	1	0																																				
																																																		
SBC	SBC HL,RR	HL	{RR}	R	R	0	1	1	1	0	1	1	0	1	ED	3	11 (4,4,3)	S,Z,H,P/V,N,C	HL <- HL - RR - CY																															
						1	0	1	R	R	0	0	1	0																																				
																																																		
ADD	ADD IX,PP	IX	{PP}	R	R	0	1	1	0	1	1	1	0	1	DD	4	15 (4,4,4,3)	H,N,C	IX <- IX + PP																															
						1	0	0	P	P	1	0	0	1																																				
																																																		
ADD	ADD IY,OO	IY	{OO}	R	R	0	1	1	1	1	1	1	0	1	FD	4	15 (4,4,4,3)	H,N,C	IY <- IY + OO																															
						1	0	0	O	O	1	0	0	1																																				
																																																		
INC	INC RR	{RR}		R		0	0	0	R	R	0	0	1	1		1	6		RR <- RR + 1		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{RR}.OE, INC2.P, INC2.L	INC2.P, INC2.OE, {RR}.L.INC2																									
																																																		
INC	INC IX	IX		R		0	1	1	0	1	1	1	0	1	DD	2	10 (4,6)		IX <- IX + 1	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	IX.OE, INC2.P, INC2.L	INC2.P, INC2.OE, IX.L.INC2																			
						1	0	0	1	0	0	0	1	1	23																																			
																																																		
INC	INC IY	IY		R		0	1	1	1	1	1	1	0	1	FD	2	10 (4,6)		IY <- IY + 1		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	IY.OE, INC2.P, INC2.L	INC2.P, INC2.OE, IY.L.INC2																			
						1	0	0	1	0	0	0	1	1	23																																			
																																																		
DEC	DEC RR	{RR}		R		0	0	0	R	R	1	0	1	1		1	6		RR <- RR - 1	Change to block INC	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	{RR}.OE, INC2.N, INC2.L	INC2.N, INC2.OE, {RR}.L.INC2																									
																																																		
DEC	DEC IX	IX		R		0	1	1	0	1	1	1	0	1	DD	2	10 (4,6)		IX <- IX - 1	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	IX.OE, INC2.N, INC2.L	INC2.N, INC2.OE, IX.L.INC2																			
						1	0	0	1	0	1	0	1	1	2B																																			
																																																		
DEC	DEC IY	IY		R		0	1	1	1	1	1	1	0	1	FD	2	10 (4,6)		IY <- IY - 1		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	IY.OE, INC2.N, INC2.L	INC2.N, INC2.OE, IY.L.INC2																			
						1	0	0	1	0	1	0	1	1	2B																																			
																																																		
RLCA	RLCA					0	0	0	0	0	0	1	1	1	07	1	4	H,N,C	CY <- A[7], A <- ROL(A,1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	A.OE, ACT.L.A	ACT.OE, ALU.OP.RLCA, ALU.OE, A.L																									
																																																		
RLA	RLA					0	0	0	0	1	0	1	1	1	17	1	4	H,N,C	[CY,A] <- ROL([CY,A], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	A.OE, ACT.L.A	ACT.OE, ALU.OP.RLA, ALU.OE, A.L																									
																																																		
RRCA	RRCA					0	0	0	0	0	1	1	1	1	0F	1	4	H,N,C	CY <- A[0], A <- ROR(A,1)	Change to RLCA	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	A.OE, ACT.L.A	ACT.OE, ALU.OP.RRCA, ALU.OE, A.L																									
																																																		
RRA	RRA					0	0	0	0	1	1	1	1	1	1F	1	4	H,N,C	[A,CY] <- ROR([A,CY], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	A.OE, ACT.L.A	ACT.OE, ALU.OP.RRA, ALU.OE, A.L																									
																																																		
RLC	RLC r	{r}		R		0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	S,Z,H,P/V,N,C	CY <- r[7], r <- ROL(r,1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	{r}.OE, ACT.L.DBUS	ACT.OE, ALU.OP.RLC, ALU.OE, {r}.L	-	-																					
						1	0	0	0	0	0	r	r	r																																				
																																																		
RLC	RLC (HL)	(HL)		RI		0	1	1	0	0	1	0	1	1	CB	4	15 (4,4,4,3)	S,Z,H,P/V,N,C	CY <- (HL)[7], (HL) <- ROL( (HL) ,1)	(HL) == 110 register!	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RLC, ALU.OE	-	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE																	
						1	0	0	0	0	0	1	1	0	06																																			
																																																		
RLC	RLC (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	CY <- (IX+d)[7], (IX+d) <- ROL( (IX+d) ,1)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RLC, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	0	0	0	1	1	0	06																																			
																																																		
RLC	RLC (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	CY <- (IY+d)[7], (IY+d) <- ROL( (IY+d) ,1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RLC, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	0	0	0	1	1	0	06																																			
																																																		
RL	RL r	{r}		R		0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	S,Z,H,P/V,N,C	CY <- r[0], r <- ROR(r,1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	{r}.OE, ACT.L.DBUS	ACT.OE, ALU.OP.RL, ALU.OE, {r}.L	-	-																					
						1	0	0	0	1	0	r	r	r																																				
																																																		
RL	RL (HL)	(HL)		RI		0	1	1	0	0	1	0	1	1	CB	4	15 (4,4,4,3)	S,Z,H,P/V,N,C	CY <- (HL)[0], (HL) <- ROR( (HL) ,1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RL, ALU.OE	-	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE																	
						1	0	0	0	1	0	1	1	0	16					(HL) == 110 register!																														
																																																		
RL	RL (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	CY <- (IX+d)[0], (IX+d) <- ROR( (IX+d) ,1)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RL, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	0	1	0	1	1	0	16																																			
																																																		
RL	RL (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	CY <- (IY+d)[0], (IY+d) <- ROR( (IY+d) ,1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RL, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	0	1	0	1	1	0	16																																			
																																																		
RRC	RRC r	{r}		R		0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	S,Z,H,P/V,N,C	[CY,r] <- ROL([CY,r], 1)	Change to block RL	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	{r}.OE, ACT.L.DBUS	ACT.OE, ALU.OP.RRC, ALU.OE, {r}.L	-	-																					
						1	0	0	0	0	1	r	r	r																																				
																																																		
RRC	RRC (HL)	(HL)		RI		0	1	1	0	0	1	0	1	1	CB	4	15 (4,4,4,3)	S,Z,H,P/V,N,C	[CY,(HL)] <- ROL([CY,(HL)], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RRC, ALU.OE	-	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE																	
						1	0	0	0	0	1	1	1	0	0E					(HL) == 110 register!																														
																																																		
RRC	RRC (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[CY,(IX+d)] <- ROL([CY,(IX+d)], 1)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RRC, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	0	0	1	1	1	0	0E																																			
																																																		
RRC	RRC (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[CY,(IY+d)] <- ROL([CY,(IY+d)], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RRC, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	0	0	1	1	1	0	0E																																			
																																																		
RR	RR r	{r}		R		0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	S,Z,H,P/V,N,C	[r,CY] <- ROR([r,CY], 1)	Change to block RL	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	{r}.OE, ACT.L.DBUS	ACT.OE, ALU.OP.RR, ALU.OE, {r}.L	-	-																					
						1	0	0	0	1	1	r	r	r																																				
																																																		
RR	RR (HL)	(HL)		RI		0	1	1	0	0	1	0	1	1	CB	4	15 (4,4,4,3)	S,Z,H,P/V,N,C	[(HL),CY] <- ROR([(HL),CY], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RR, ALU.OE	-	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE																	
						1	0	0	0	1	1	1	1	0	1E					(HL) == 110 register!																														
																																																		
RR	RR (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[(IX+d),CX] <- ROR([(IX+d),CY], 1)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RR, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	0	1	1	1	1	0	1E																																			
																																																		
RR	RR (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[(IY+d),CX] <- ROR([(IY+d),CY], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.RR, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	0	1	1	1	1	0	1E																																			
																																																		
SLA	SLA r	{r}		R		0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	S,Z,H,P/V,N,C	[CY,r] <- SHL([r,0], 1)	Change to block RL	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	{r}.OE, ACT.L.DBUS	ACT.OE, ALU.OP.SLA, ALU.OE, {r}.L	-	-																					
						1	0	0	1	0	0	r	r	r																																				
																																																		
SLA	SLA (HL)	(HL)		RI		0	1	1	0	0	1	0	1	1	CB	4	15 (4,4,4,3)	S,Z,H,P/V,N,C	[CY, (HL) ] <- SHL([ (HL) ,0], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.SLA, ALU.OE	-	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE																	
						1	0	0	1	0	0	1	1	0	26					(HL) == 110 register!																														
																																																		
SLA	SLA (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[CY, (IX+d) ] <- SHL([ (IX+d) ,0], 1)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.SLA, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	1	0	0	1	1	0	26																																			
																																																		
SLA	SLA (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[CY, (IY+d) ] <- SHL([ (IY+d) ,0], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.SLA, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	1	0	0	1	1	0	26																																			
																																																		
SLL	SLL r	{r}		R		0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	S,Z,H,P/V,N,C	[CY,r] <- SHL([r,0], 1)	Change to block RL																														
						1	0	0	1	1	0	r	r	r																																				
																																																		
SLL	SLL (HL)	(HL)		RI		0	1	1	0	0	1	0	1	1	CB	4	15 (4,4,4,3)	S,Z,H,P/V,N,C	[CY, (HL) ] <- SHL([ (HL) ,0], 1)	UNDOC																														
						1	0	0	1	1	0	1	1	0	36					(HL) == 110 register!																														
																																																		
SLL	SLL (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[CY, (IX+d) ] <- SHL([ (IX+d) ,0], 1)	This bit seems to indicate X/Y																														
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	1	1	0	1	1	0	36																																			
																																																		
SLL	SLL (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[CY, (IY+d) ] <- SHL([ (IY+d) ,0], 1)																															
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	1	1	0	1	1	0	36																																			
																																																		
SRA	SRA r	{r}		R		0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	S,Z,H,P/V,N,C	[r,CY] <- SHR([r[7],r], 1)	Change to block RL	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	{r}.OE, ACT.L.DBUS	ACT.OE, ALU.OP.SRA, ALU.OE, {r}.L	-	-																					
						1	0	0	1	0	1	r	r	r																																				
																																																		
SRA	SRA (HL)	(HL)		RI		0	1	1	0	0	1	0	1	1	CB	4	15 (4,4,4,3)	S,Z,H,P/V,N,C	[ (HL) ,CY] <- SHR([ (HL)[7], (HL) ], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.SRA, ALU.OE	-	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE																	
						1	0	0	1	0	1	1	1	0	2E					(HL) == 110 register!																														
																																																		
SRA	SRA (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[ (IX+d) ,CY] <- SHR([ (IX+d)[7], (IX+d) ], 1)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.SRA, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	1	0	1	1	1	0	2E																																			
																																																		
SRA	SRA (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[ (IY+d) ,CY] <- SHR([ (IY+d)[7], (IY+d) ], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.SRA, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	1	0	1	1	1	0	2E																																			
																																																		
SRL	SRL r	{r}		R		0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	S,Z,H,P/V,N,C	[r,CY] <- SHR([0,r], 1)	Change to block RL	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	{r}.OE, ACT.L.DBUS	ACT.OE, ALU.OP.SRL, ALU.OE, {r}.L	-	-																					
						1	0	0	1	1	1	r	r	r																																				
																																																		
SRL	SRL (HL)	(HL)		RI		0	1	1	0	0	1	0	1	1	CB	4	15 (4,4,4,3)	S,Z,H,P/V,N,C	[ (HL) ,CY] <- SHR([0, (HL) ], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.SRL, ALU.OE	-	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE																	
						1	0	0	1	1	1	1	1	0	3E					(HL) == 110 register!																														
																																																		
SRL	SRL (IX+d)	(IX+{d})		X		0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[ (IX+d) ,CY] <- SHR([0, (IX+d) ], 1)	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.SRL, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	1	1	1	1	1	0	3E																																			
																																																		
SRL	SRL (IY+d)	(IY+{d})		X		0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,5,4,3)	S,Z,H,P/V,N,C	[ (IY+d) ,CY] <- SHR([0, (IY+d) ], 1)		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, ACT.L.DBUS	ACT.OE, ALU.OP.SRL, ALU.OE	ABUF.L	ALU.OE, DBUF.L.OUT	ALU.OE		
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	0	1	1	1	1	1	0	3E																																			
																																																		
RLD	RLD					0	1	1	1	0	1	1	0	1	ED	5	18 (4,4,3,4,3)	S,Z,H,P/V,N	[ A, (HL) ] <- [ A[7..4], (HL)[7..4], (HL)[3..0], A[3..0] ]		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.RLD1, ALU.OE, DBUF.L.OUT	ALU.OE	TMP.OE.ALU, ACT.OE, ALU.OP.RLD2, ALU.OE, A.L	A.L																		
						1	0	1	1	0	1	1	1	1	6F																																			
																																																		
RRD	RRD					0	1	1	1	0	1	1	0	1	ED	5	18 (4,4,3,4,3)	S,Z,H,P/V,N	[ A, (HL) ] <- [ A[7..4], (HL)[3..0], A[3..0], (HL)[7.4] ]		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L, A.OE.ACT, ACT.L.A	TMP.OE.ALU, ACT.OE, ALU.OP.RRD1, ALU.OE, DBUF.L.OUT	ALU.OE	TMP.OE.ALU, ACT.OE, ALU.OP.RRD2, ALU.OE, A.L	A.L																		
						1	0	1	1	0	0	1	1	1	67																																			
																																																		
BIT	BIT b,r	{b}	{r}	B	R	0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	Z,H,N	Z <- r[b]		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L, ACT.L.DBUS	{r}.OE, TMP.L	TMP.OE.ALU, ACT.OE, ALU.OP.BIT, ALU.OE																				
						1	0	1	b	b	b	r	r	r																																				
																																																		
BIT	BIT b,(HL)	{b}	(HL)	B	RI	0	1	1	0	0	1	0	1	1	CB	3	12 (4,4,4)	Z,H,N	Z <- (HL)[b]		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L, ACT.L.DBUS			HL.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L	TMP.OE.ALU, ACT.OE, ALU.OP.BIT, ALU.OE																
						1	0	1	b	b	b	1	1	0						(HL) == 110 register!																														
																																																		
BIT	BIT b,(IX+d)	{b}	(IX+{d})	B	X	0	1	1	0	1	1	1	0	1	DD	5	20 (4,4,3,5,4)	Z,H,N	Z <- (IX+d)[b]	This bit seems to indicate X/Y	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.X, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L	TMP.OE.ALU, ACT.OE, ALU.OP.BIT, ALU.OE	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L, ACT.L.DBUS	TMP.OE.ALU, ACT.OE, ALU.OP.BIT, ALU.OE						
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	1	b	b	b	1	1	0																																				
																																																		
BIT	BIT b,(IY+d)	{b}	(IY+{d})	B	X	0	1	1	1	1	1	1	0	1	FD	5	20 (4,4,3,5,4)	Z,H,N	Z <- (IY+d)[b]		PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L	X	-	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, TMP.L	-	-	TMP.OE.DBUS, DISP.L.Y, DISP.L.DBUS	DISP.OE, ABUF.L	DBUF.L.IN	DBUF.L.IN, TMP.L	TMP.OE.ALU, ACT.OE, ALU.OP.BIT, ALU.OE	PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L, ACT.L.DBUS	TMP.OE.ALU, ACT.OE, ALU.OP.BIT, ALU.OE						
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	0	1	b	b	b	1	1	0																																				
																																																		
SET	SET b,r	{b}	{r}	B	R	0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	Z,H,N	r[b] <- 1	Change to block BIT						PC.OE, ABUF.L, INC2.P, INC2.L	INC2.P, INC2.OE, PC.L.INC2, DBUF.L.IN	DBUF.L.IN, INSTR.L, ACT.L.DBUS	{r}.OE, TMP.L	TMP.OE.ALU, ACT.OE, ALU.OP.SET, ALU.OE																				
						1	1	1	b	b	b	r	r	r																																				
																																																		
SET	SET b,(HL)	{b}	(HL)	B	RI	0	1	1	0	0	1	0	1	1	CB	4	15 (4,4,4,3)	Z,H,N	(HL)[b] <- 1																															
						1	1	1	b	b	b	1	1	0						(HL) == 110 register!																														
																																																		
SET	SET b,(IX+d)	{b}	(IX+{d})	B	X	0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,5,4,3)	Z,H,N	(IX+d)[b] <- 1	This SET seems to indicate X/Y																														
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	1	1	b	b	b	1	1	0																																				
																																																		
SET	SET b,(IY+d)	{b}	(IY+{d})	B	X	0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,5,4,3)	Z,H,N	(IY+d)[b] <- 1																															
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	1	1	b	b	b	1	1	0																																				
																																																		
RES	RES b,r	{b}	{r}	B	R	0	1	1	0	0	1	0	1	1	CB	2	8 (4,4)	Z,H,N	r[b] <- 0	Change to block BIT																														
						1	1	0	b	b	b	r	r	r																																				
																																																		
RES	RES b,(HL)	{b}	(HL)	B	RI	0	1	1	0	0	1	0	1	1	CB	4	15 (4,4,4,3)	Z,H,N	(HL)[b] <- 0																															
						1	1	0	b	b	b	1	1	0						(HL) == 110 register!																														
																																																		
RES	RES b,(IX+d)	{b}	(IX+{d})	B	X	0	1	1	0	1	1	1	0	1	DD	6	23 (4,4,3,5,4,3)	Z,H,N	(IX+d)[b] <- 0	This RES seems to indicate X/Y																														
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	1	0	b	b	b	1	1	0																																				
																																																		
RES	RES b,(IY+d)	{b}	(IY+{d})	B	X	0	1	1	1	1	1	1	0	1	FD	6	23 (4,4,3,5,4,3)	Z,H,N	(IY+d)[b] <- 0																															
						1	1	1	0	0	1	0	1	1	CB																																			
						2	d	d	d	d	d	d	d	d																																				
						3	1	0	b	b	b	1	1	0																																				
																																																		
JP	JP nn	{nn}		EJ		0	1	1	0	0	0	0	1	1	C3	3	10 (4,3,3)		PC <- nn																															
						1	n	n	n	n	n	n	n	n						low order																														
						2	n	n	n	n	n	n	n	n						high order																														
																																																		
JP	JP cc,nn	{cc}	{nn}	B	EJ	0	1	1	c	c	c	0	1	0		3	10 (4,3,3)		IF cc true, PC <- nn																															
						1	n	n	n	n	n	n	n	n																																				
						2	n	n	n	n	n	n	n	n																																				
																																																		
JR	JR ee	{ee}		L		0	0	0	0	1	1	0	0	0	18	3	12 (4,3,5)		PC <- PC + ee																															
						1	e	e	e	e	e	e	e	e						ee = ee-2 !!																														
																																																		
JR	JR C,ee	C	{ee}	B	L	0	0	0	1	1	1	0	0	0	38	3	12 (4,3,5)		IF C, PC <- PC + ee	Change to block JR																														
						1	e	e	e	e	e	e	e	e						ee = ee-2 !!																														
																																																		
JR	JR NC,ee	NC	{ee}	B	L	0	0	0	1	1	0	0	0	0	30	3	12 (4,3,5)		IF NC, PC <- PC + ee	Change to block JR																														
						1	e	e	e	e	e	e	e	e						ee = ee-2 !!																														
																																																		
JR	JR Z,ee	Z	{ee}	B	L	0	0	0	1	0	1	0	0	0	28	3	12 (4,3,5)		IF Z, PC <- PC + ee	Change to block JR																														
						1	e	e	e	e	e	e	e	e						ee = ee-2 !!																														
																																																		
JR	JR NZ,ee	NZ	{ee}	B	L	0	0	0	1	0	0	0	0	0	20	3	12 (4,3,5)		IF NZ, PC <- PC + ee	Change to block JR																														
						1	e	e	e	e	e	e	e	e						ee = ee-2 !!																														
																																																		
JP	JP (HL)	(HL)		RI		0	1	1	1	0	1	0	0	1	E9	1	4		PC <- (HL)																															
																																																		
JP	JP (IX)	(IX)		RI		0	1	1	0	1	1	1	0	1	DD	2	8 (4,4)		PC <- (IX)	This bit seems to indicate X/Y																														
						1	1	1	1	0	1	0	0	1	E9																																			
																																																		
JP	JP (IY)	(IY)		RI		0	1	1	1	1	1	1	0	1	FD	2	8 (4,4)		PC <- (IY)																															
						1	1	1	1	0	1	0	0	1	E9																																			
																																																		
DJNZ	DJNZ ee	{ee}		L		0	0	0	0	1	0	0	0	0	10	3	13 (5,3,5)		B <- B - 1, IF B != 0, PC <- PC + ee																															
						1	e	e	e	e	e	e	e	e																																				
																																																		
CALL	CALL nn	{nn}		EJ		0	1	1	0	0	1	1	0	1	CD	5	17 (4,3,4,3,3)		(SP-2) <- (PC+3)l, (SP-1) <- (PC+3)h, SP <- SP - 2, PC <- nn																															
						1	n	n	n	n	n	n	n	n																																				
						2	n	n	n	n	n	n	n	n																																				
																																																		
CALL	CALL cc,nn	{cc}	{nn}	B	EJ	0	1	1	c	c	c	1	0	0		5	17 (4,3,4,3,3)		IF cc true, (SP-2) <- (PC+3)l, (SP-1) <- (PC+3)h, SP <- SP - 2, PC <- nn																															
						1	n	n	n	n	n	n	n	n																																				
						2	n	n	n	n	n	n	n	n																																				
																																																		
RET	RET					0	1	1	0	0	1	0	0	1	C9	3	10 (4,3,3)		PCl <- (SP), PCh <- (SP), SP <- SP + 2	Change to block RET																														
																																																		
RET	RET cc	{cc}		B		0	1	1	c	c	c	0	0	0		3	11 (5,3,3)		IF cc true, PCl <- (SP), PCh <- (SP), SP <- SP + 2																															
																																																		
RETI	RETI					0	1	1	1	0	1	1	0	1	ED	4	14 (4,4,3,3)		Return from Interrupt																															
						1	0	1	0	0	1	1	0	1	4D																																			
																																																		
RETN	RETN					0	1	1	1	0	1	1	0	1	ED	4	14 (4,4,3,3)		Return from non-maskable Interrupt	Change to block RETI																														
						1	0	1	0	0	0	1	0	1	45																																			
																																																		
RST	RST tt	{tt}		MPZA		0	1	1	t	t	t	1	1	1		3	11 (5,3,3)		(SP-2) <- (PC+3)l, (SP-1) <- (PC+3)h, SP <- SP - 2, PC <- nn																															
																																																		
IN	IN A,(n)	A	({n})	R	EP	0	1	1	0	1	1	0	1	1	DB	3	11 (4,3,4)		A <- (n)																															
						1	n	n	n	n	n	n	n	n																																				
																																																		
IN	IN r,(C)   	{r}	(C)   	R	RI	0	1	1	1	0	1	1	0	1	ED	3	12 (4,4,4)	S,Z,H,P/V,N	r <- (C)  	r == 110 is Flag, TODO																														
						1	0	1	r	r	r	0	0	0																																				
																																																		
INI	INI					0	1	1	1	0	1	1	0	1	ED	4	16 (4,5,3,4)	Z,N	(HL) <- (C), B <- B - 1, HL <- HL + 1																															
						1	1	0	1	0	0	0	1	0	A2																																			
																																																		
INIR	INIR					0	1	1	1	0	1	1	0	1	ED	5	21 (4,5,3,4,5)	Z,N	(HL) <- (C), B <- B - 1, HL <- HL + 1, IF B != 0, repeat																															
						1	1	0	1	1	0	0	1	0	B2																																			
																																																		
IND	IND					0	1	1	1	0	1	1	0	1	ED	4	16 (4,5,3,4)	Z,N	(HL) <- (C), B <- B - 1, HL <- HL - 1																															
						1	1	0	1	0	1	0	1	0	AA																																			
																																																		
INDR	INDR					0	1	1	1	0	1	1	0	1	ED	5	21 (4,5,3,4,5)	Z,N	(HL) <- (C), B <- B - 1, HL <- HL - 1, IF B != 0, repeat																															
						1	1	0	1	1	1	0	1	0	BA																																			
																																																		
OUT	OUT (n),A	({n})	A	EP	R	0	1	1	0	1	0	0	1	1	D3	3	11 (4,3,4)		(n) <- A																															
						1	n	n	n	n	n	n	n	n																																				
																																																		
OUT	OUT (C), r   	(C)	{r}   	RI	R	0	1	1	1	0	1	1	0	1	ED	3	12 (4,4,4)	S,Z,H,P/V,N	(C) <- r  																															
						1	0	1	r	r	r	0	0	1																																				
																																																		
OUTI	OUTI					0	1	1	1	0	1	1	0	1	ED	4	16 (4,5,3,4)	Z,N	(C) <- (HL), B <- B - 1, HL <- HL + 1																															
						1	1	0	1	0	0	0	1	1	A3																																			
																																																		
OTIR	OTIR					0	1	1	1	0	1	1	0	1	ED	5	21 (4,5,3,4,5)	Z,N	(C) <- (HL), B <- B - 1, HL <- HL + 1, IF B != 0, repeat																															
						1	1	0	1	1	0	0	1	1	B3																																			
																																																		
OUTD	OUTD					0	1	1	1	0	1	1	0	1	ED	4	16 (4,5,3,4)	Z,N	(C) <- (HL), B <- B - 1, HL <- HL - 1																															
						1	1	0	1	0	1	0	1	1	AB																																			
																																																		
OTDR	OTDR					0	1	1	1	0	1	1	0	1	ED	5	21 (4,5,3,4,5)	Z,N	(C) <- (HL), B <- B - 1, HL <- HL - 1, IF B != 0, repeat																															
						1	1	0	1	1	1	0	1	1	BB