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neogeo.sv
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//============================================================================
// SNK NeoGeo for MiSTer
//
// Copyright (C) 2018 Sean 'Furrtek' Gonsalves
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
// Current status:
// Neo CD CD check ok but crashes when loading. No more video glitches.
// How about not using a cache at all and DMAing directly from the data fed by the HPS ?
// The "sector ready" IRQ could be triggered just when a sector is requested, and the actual transfer
// could be done when the system ROM starts up the DMA transfer ?
// Neo CD times 12/05/2019:
// SECTOR_READY goes high at SECTOR_TIMER == 430631
// So it takes 600000-430631=169369 ticks to get a sector from HPS
// 169369/120M=1.41ms (1451 kB/s)
// DMA copy: 215 ticks for 10 bytes
// So 215/120M/10=179.17ns per byte (5450 kB/s)
// Neo CD times 11/05/2019:
// DMA copy: 616 ticks for 10 bytes
// So 215/120M/10=513.3ns per byte (1902 kB/s)
module emu
(
//Master input clock
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [48:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
output [12:0] VIDEO_ARX,
output [12:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
output VGA_SCALER, // Force VGA scaler
output VGA_DISABLE, // analog out is off
input [11:0] HDMI_WIDTH,
input [11:0] HDMI_HEIGHT,
output HDMI_FREEZE,
`ifdef MISTER_FB
// Use framebuffer in DDRAM
// FB_FORMAT:
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
// [3] : 0=16bits 565 1=16bits 1555
// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
//
// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
output FB_EN,
output [4:0] FB_FORMAT,
output [11:0] FB_WIDTH,
output [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output FB_FORCE_BLANK,
`ifdef MISTER_FB_PALETTE
// Palette control for 8bit modes.
// Ignored for other video modes.
output FB_PAL_CLK,
output [7:0] FB_PAL_ADDR,
output [23:0] FB_PAL_DOUT,
input [23:0] FB_PAL_DIN,
output FB_PAL_WR,
`endif
`endif
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
// I/O board button press simulation (active high)
// b[1]: user button
// b[0]: osd button
output [1:0] BUTTONS,
input CLK_AUDIO, // 24.576 MHz
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
//ADC
inout [3:0] ADC_BUS,
//SD-SPI
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
//SDRAM interface with lower latency
output SDRAM_CLK,
output SDRAM_CKE,
output [12:0] SDRAM_A,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
`ifdef MISTER_DUAL_SDRAM
//Secondary SDRAM
//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
input SDRAM2_EN,
output SDRAM2_CLK,
output [12:0] SDRAM2_A,
output [1:0] SDRAM2_BA,
inout [15:0] SDRAM2_DQ,
output SDRAM2_nCS,
output SDRAM2_nCAS,
output SDRAM2_nRAS,
output SDRAM2_nWE,
`endif
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR,
// Open-drain User port.
// 0 - D+/RX
// 1 - D-/TX
// 2..6 - USR2..USR6
// Set USER_OUT to 1 to read from USER_IN.
input [6:0] USER_IN,
output [6:0] USER_OUT,
input OSD_STATUS
);
assign ADC_BUS = 'Z;
assign USER_OUT = '1;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign AUDIO_S = 1; // Signed
assign AUDIO_MIX = status[6:5];
assign AUDIO_L = snd_mix_l[16:1];
assign AUDIO_R = snd_mix_r[16:1];
assign LED_USER = status[0] | bk_pending;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign BUTTONS = osd_btn;
assign VGA_SCALER= 0;
assign VGA_DISABLE = 0;
assign HDMI_FREEZE = 0;
wire [1:0] ar = status[33:32];
wire vcrop_en = status[34];
wire [3:0] vcopt = status[38:35];
reg en216p;
reg [4:0] voff;
always @(posedge CLK_VIDEO) begin
en216p <= ((HDMI_WIDTH == 1920) && (HDMI_HEIGHT == 1080) && !forced_scandoubler && !scale);
voff <= (vcopt < 6) ? {vcopt,1'b0} : ({vcopt,1'b0} - 5'd24);
end
wire vga_de;
video_freak video_freak
(
.*,
.VGA_DE_IN(vga_de),
.ARX((!ar) ? 12'd10 : (ar - 1'd1)),
.ARY((!ar) ? 12'd7 : 12'd0),
.CROP_SIZE((en216p & vcrop_en) ? 10'd216 : 10'd0),
.CROP_OFF(voff),
.SCALE(status[40:39])
);
// status bit definition:
// 31 23 15 7
// --AA-PSS -------- L--CGGDD DEEMVTTR
// : status[0] System Reset, used by the HPS, keep it there
// T: status[2:1] System type, 0=Console, 1=Arcade, 2=CD, 3=CDZ
// V: status[3] Video mode
// M: status[4] Memory card presence
// E: status[6:5] Stereo mix
// D: status[9:7] DIP switches
// G: status[11:10] Neo CD region
// C: status[12] Save memory card & backup RAM
// L: status[12] CD lid state (DEBUG)
// : status[14] Manual Reset
// : status[20:15] OSD options
// 0123456789 ABCDEFGHIJKLMNO
// Conditional modification of the CONF strings chaining according to chosen system type
// Con Arc CD CDz
// 00 01 10 11
// F F + + ~SYSTEM_CDx;
// + + S S SYSTEM_CDx;
// O O + + ~SYSTEM_CDx;
// + O + + SYSTEM_MVS;
// + + O O SYSTEM_CDx;
// Status Bit Map:
// Upper Lower
// 0 1 2 3 4 5 6
// 01234567890123456789012345678901 23456789012345678901234567890123
// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
// XXXXXXXXXXXXX XXX XXXXX XXXXXXX XXXXXXXXXXX XXXXXX
`include "build_id.v"
localparam CONF_STR = {
"NEOGEO;;",
"-;",
"FS1,*,Load ROM set;",
"S1,CUECHD,Load CD Image;",
"-;",
"H3OP,FM,ON,OFF;",
"H3OQ,ADPCMA,ON,OFF;",
"H3OR,ADPCMB,ON,OFF;",
"H3OS,PSG,ON,OFF;",
"H3oP,ADPCMA CH 1,ON,OFF;",
"H3oQ,ADPCMA CH 2,ON,OFF;",
"H3oR,ADPCMA CH 3,ON,OFF;",
"H3oS,ADPCMA CH 4,ON,OFF;",
"H3oT,ADPCMA CH 5,ON,OFF;",
"H3oU,ADPCMA CH 6,ON,OFF;",
"H3-;",
"O1,System Type,Console(AES),Arcade(MVS);",
"OM,BIOS,UniBIOS,Original;",
"O3,Video Mode,NTSC,PAL;",
"-;",
"o9A,Input,Joystick or Spinner,Joystick,Spinner,Mouse(Irr.Maze);",
"-;",
"H0O4,Memory Card,Plugged,Unplugged;",
"RL,Reload Memory Card;",
"D4RC,Save Memory Card;",
"OO,Autosave,OFF,ON;",
"-;",
"O2,CD Type,CD,CDZ;",
"OTU,CD Speed,1x,2x,3x,4x;",
"OAB,CD Region,US,EU,JP,AS;",
"OF,CD lid,Closed,Opened;",
"H2-;",
"H2O7,[DIP] Settings,OFF,ON;",
"H2O8,[DIP] Freeplay,OFF,ON;",
"H2O9,[DIP] Freeze,OFF,ON;",
"-;",
"P1,Audio & Video;",
"P1-;",
"P1OG,Width,320px,304px;",
"P1o01,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
"P1OIK,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
"P1-;",
"d5P1o2,Vertical Crop,Disabled,216p(5x);",
"d5P1o36,Crop Offset,0,2,4,8,10,12,-12,-10,-8,-6,-4,-2;",
"P1o78,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
"P1-;",
"P1O56,Stereo Mix,none,25%,50%,100%;",
"P1-;",
"-;",
"RE,Reset & apply;", // decouple manual reset from system reset
"J1,A,B,C,D,Start,Select,Coin,ABC;", // ABC is a special key to press A+B+C at once, useful for keyboards that don't allow more than 2 keypresses at once
"jn,A,B,X,Y,Start,Select,L,R;", // name mapping
"jp,B,A,D,C,Start,Select,L,R;", // positional mapping consistent with NeoGeoCD controller
"V,v",`BUILD_DATE //
};
//////////////////// CLOCKS ///////////////////
wire locked;
wire CLK_48M, CLK_96M;
assign CLK_VIDEO = CLK_48M;
wire clk_sys = CLK_48M;
pll pll
(
.refclk(CLK_50M),
.rst(0),
.outclk_0(CLK_96M),
.outclk_1(CLK_48M),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
.locked(locked)
);
reg CLK_EN_24M_N, CLK_EN_24M_P;
always @(posedge CLK_48M) begin
CLK_EN_24M_N <= ~CLK_EN_24M_N;
CLK_EN_24M_P <= CLK_EN_24M_N;
end
wire [63:0] reconfig_to_pll;
wire [63:0] reconfig_from_pll;
wire cfg_waitrequest;
reg cfg_write;
reg [5:0] cfg_address;
reg [31:0] cfg_data;
pll_cfg pll_cfg
(
.mgmt_clk(CLK_50M),
.mgmt_reset(0),
.mgmt_waitrequest(cfg_waitrequest),
.mgmt_read(0),
.mgmt_readdata(),
.mgmt_write(cfg_write),
.mgmt_address(cfg_address),
.mgmt_writedata(cfg_data),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
always @(posedge CLK_50M) begin
reg sys_mvs = 0, sys_mvs2 = 0;
reg [2:0] state = 0;
reg sys_mvs_r;
sys_mvs <= SYSTEM_MVS;
sys_mvs2 <= sys_mvs;
cfg_write <= 0;
if(sys_mvs2 == sys_mvs && sys_mvs2 != sys_mvs_r) begin
state <= 1;
sys_mvs_r <= sys_mvs2;
end
if(!cfg_waitrequest) begin
if(state) state<=state+1'd1;
case(state)
1: begin
cfg_address <= 0;
cfg_data <= 0;
cfg_write <= 1;
end
5: begin
cfg_address <= 7;
cfg_data <= sys_mvs_r ? 2576980378 : 2865308404;
cfg_write <= 1;
end
7: begin
cfg_address <= 2;
cfg_data <= 0;
cfg_write <= 1;
end
endcase
end
end
// The watchdog should output nRESET but it makes video sync stop for a moment, so the
// MiSTer OSD jumps around. Provide an indication for devs that a watchdog reset happened ?
reg [14:0] TRASH_ADDR;
reg SYSTEM_TYPE, SYSTEM_CD_TYPE;
reg nRESET;
always @(posedge CLK_48M) begin
reg rst_n;
nRESET <= rst_n;
rst_n <= &TRASH_ADDR;
if(CLK_EN_24M_N && ~&TRASH_ADDR) TRASH_ADDR <= TRASH_ADDR + 1'b1;
if (status[0] | status[14] | buttons[1] | bk_loading | RESET) begin
TRASH_ADDR <= 0;
SYSTEM_TYPE <= status[1]; // Latch the system type on reset
SYSTEM_CD_TYPE <= status[2];
end
end
reg osd_btn = 0;
always @(posedge CLK_48M) begin
integer timeout = 0;
reg last_rst = 0;
if (RESET) last_rst = 0;
if (status[0]) last_rst = 1;
if (last_rst & ~status[0]) begin
osd_btn <= 0;
if(timeout < 48000000) begin
timeout <= timeout + 1;
osd_btn <= 1;
end
end
end
////////////////// HPS I/O ///////////////////
// VD 0: Save file
wire [1:0] img_mounted;
wire sd_buff_wr, img_readonly;
wire [7:0] sd_buff_addr; // Address inside 256-word sector
wire [15:0] sd_buff_dout;
wire [15:0] sd_buff_din[2];
wire [15:0] sd_req_type;
wire [63:0] img_size;
wire [31:0] sd_lba[2];
wire [1:0] sd_wr;
wire [1:0] sd_rd;
wire [1:0] sd_ack;
wire [15:0] joystick_0; // ----HNLS DCBAUDLR
wire [15:0] joystick_1;
wire [8:0] spinner_0, spinner_1;
wire [1:0] buttons;
wire [10:0] ps2_key;
wire [24:0] ps2_mouse;
wire forced_scandoubler;
wire [63:0] status;
wire [64:0] rtc;
wire ioctl_wr;
wire [26:0] ioctl_addr;
wire [15:0] ioctl_dout;
wire ioctl_download;
wire [7:0] ioctl_idx;
wire SYSTEM_MVS = SYSTEM_TYPE & ~cd_en;
wire SYSTEM_CDx = cd_en;
wire SYSTEM_CDZ = SYSTEM_CDx & SYSTEM_CD_TYPE;
wire [15:0] sdram_sz;
wire [21:0] gamma_bus;
hps_io #(.CONF_STR(CONF_STR), .WIDE(1), .VDNUM(2)) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.forced_scandoubler(forced_scandoubler),
.joystick_0(joystick_0), .joystick_1(joystick_1),
.spinner_0(spinner_0), .spinner_1(spinner_1),
.ps2_mouse(ps2_mouse),
.buttons(buttons),
.ps2_key(ps2_key),
.status(status), // status read (32 bits)
.status_menumask({status[22], 9'd0, en216p, bk_autosave | ~bk_pending, ~dbg_menu,~SYSTEM_MVS,1'b0,SYSTEM_CDx}),
.RTC(rtc),
.sdram_sz(sdram_sz),
.gamma_bus(gamma_bus),
// Loading signals
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_dout),
.ioctl_download(ioctl_download),
.ioctl_index(ioctl_idx),
.ioctl_wait((ddr_loading & ddram_wait) | memcp_wait),
.sd_lba(sd_lba),
.sd_rd(sd_rd),
.sd_wr(sd_wr),
.sd_ack(sd_ack),
.sd_buff_addr(sd_buff_addr),
.sd_buff_dout(sd_buff_dout),
.sd_buff_din(sd_buff_din),
.sd_buff_wr(sd_buff_wr),
.img_mounted(img_mounted),
.img_readonly(img_readonly),
.img_size(img_size),
.EXT_BUS(EXT_BUS)
);
reg [7:0] ioctl_index;
always @(posedge clk_sys) ioctl_index <= ioctl_idx;
reg dbg_menu = 0;
always @(posedge clk_sys) begin
reg old_stb;
reg enter = 0;
reg esc = 0;
old_stb <= ps2_key[10];
if(old_stb ^ ps2_key[10]) begin
if(ps2_key[7:0] == 'h5A) enter <= ps2_key[9];
if(ps2_key[7:0] == 'h76) esc <= ps2_key[9];
end
if(enter & esc) begin
dbg_menu <= ~dbg_menu;
enter <= 0;
esc <= 0;
end
end
////////////////// Her Majesty ///////////////////
reg [31:0] cfg = 0;
wire [15:0] snd_right;
wire [15:0] snd_left;
wire nRESETP, nSYSTEM, CARD_WE, SHADOW, nVEC, nREGEN, nSRAMWEN, PALBNK;
wire CD_nRESET_Z80;
// Clocks
wire CLK_EN_12M, CLK_EN_12M_N, CLK_68KCLK, CLK_68KCLKB, CLK_EN_6MB, CLK_EN_1HB, CLK_EN_4M_P, CLK_EN_4M_N, CLK_EN_68K_P, CLK_EN_68K_N;
// 68k stuff
wire [15:0] M68K_DATA;
wire [23:1] M68K_ADDR;
wire A22Z, A23Z;
wire M68K_RW, nAS, nLDS, nUDS, nDTACK, nHALT, nBR, nBG, nBGACK;
wire [15:0] M68K_DATA_BYTE_MASK;
wire [15:0] FX68K_DATAIN;
wire [15:0] FX68K_DATAOUT;
wire IPL0, IPL1;
wire FC0, FC1, FC2;
reg [3:0] P_BANK;
// RTC stuff
wire RTC_DOUT, RTC_DIN, RTC_CLK, RTC_STROBE, RTC_TP;
// OEs and WEs
wire nSROMOEL, nSROMOEU, nSROMOE;
wire nROMOEL, nROMOEU;
wire nPORTOEL, nPORTOEU, nPORTWEL, nPORTWEU, nPORTADRS;
wire nSRAMOEL, nSRAMOEU, nSRAMWEL, nSRAMWEU;
wire nWRL, nWRU, nWWL, nWWU;
wire nLSPOE, nLSPWE;
wire nPAL, nPAL_WE;
wire nBITW0, nBITW1, nBITWD0, nDIPRD0, nDIPRD1;
wire nSDROE, nSDPOE;
// RAM outputs
wire [7:0] WRAML_OUT;
wire [7:0] WRAMU_OUT;
wire [15:0] SRAM_OUT;
wire [7:0] CD_Z80_RAM_OUT;
wire [14:0] WRAM_ADDR;
wire [7:0] WRAML_DATA, WRAMU_DATA;
wire WRAML_WREN, WRAMU_WREN;
// Memory card stuff
wire [23:0] CDA;
wire [2:0] BNK;
wire [7:0] CDD;
wire nCD1, nCD2;
wire nCRDO, nCRDW, nCRDC;
wire nCARDWEN, CARDWENB;
// Z80 stuff
wire [7:0] SDD_IN, SDD_OUT, Z80_SDD_OUT;
wire [7:0] SDD_RD_C1;
wire [15:0] SDA, Z80_SDA;
wire nSDRD, nSDWR, nMREQ, nIORQ, nBUSAK;
wire Z80_nSDRD, Z80_nSDWR, Z80_nMREQ;
wire Z80_nINT, Z80_nNMI, nSDW, nSDZ80R, nSDZ80W, nSDZ80CLR;
wire nSDROM, nSDMRD, nSDMWR, SDRD0, SDRD1, nZRAMCS;
wire n2610CS, n2610RD, n2610WR;
// Graphics stuff
wire [23:0] PBUS;
wire [7:0] LO_ROM_DATA;
wire nPBUS_OUT_EN;
wire [19:0] C_LATCH;
reg [3:0] C_LATCH_EXT;
wire [63:0] CR_DOUBLE;
wire [26:0] CROM_ADDR;
wire [1:0] FIX_BANK;
wire [15:0] S_LATCH;
wire [7:0] FIXD;
wire [10:0] FIXMAP_ADDR;
wire CWE, BWE, BOE;
wire [14:0] SLOW_VRAM_ADDR;
reg [15:0] SLOW_VRAM_DATA_IN;
wire [15:0] SLOW_VRAM_DATA_OUT;
wire [10:0] FAST_VRAM_ADDR;
wire [15:0] FAST_VRAM_DATA_IN;
wire [15:0] FAST_VRAM_DATA_OUT;
wire [11:0] PAL_RAM_ADDR;
wire [15:0] PAL_RAM_DATA;
reg [15:0] PAL_RAM_REG;
wire PCK1, PCK2, EVEN1, EVEN2, LOAD, H;
wire PCK1_EN_P, PCK2_EN_P;
wire PCK1_EN_N, PCK2_EN_N;
wire DOTA, DOTB;
wire CA4, S1H1, S2H1;
wire CHBL, nBNKB, VCS;
wire CHG, LD1, LD2, SS1, SS2;
wire [3:0] GAD;
wire [3:0] GBD;
wire [3:0] WE;
wire [3:0] CK;
wire CD_VIDEO_EN, CD_FIX_EN, CD_SPR_EN;
// SDRAM multiplexing stuff
wire [15:0] SROM_DATA;
wire [15:0] PROM_DATA;
parameter INDEX_SPROM = 0;
parameter INDEX_LOROM = 1;
parameter INDEX_SFIXROM = 2;
parameter INDEX_P1ROM_A = 4;
parameter INDEX_P1ROM_B = 5;
parameter INDEX_P2ROM = 6;
parameter INDEX_S1ROM = 8;
parameter INDEX_M1ROM = 9;
parameter INDEX_MEMCP = 10;
parameter INDEX_CROM0 = 15;
parameter INDEX_VROMS = 16;
parameter INDEX_CROMS = 64;
wire video_mode = status[3];
wire ms5p_bank = cfg[17];
wire xram = cfg[18];
wire adpcma_ext = cfg[19];
wire [2:0] cart_pchip = cfg[22:20];
wire use_pcm = cfg[23];
wire [1:0] cart_chip = cfg[25:24]; // legacy option: 0 - none, 1 - PRO-CT0, 2 - Link MCU
wire [1:0] cmc_chip = cfg[27:26]; // type 1/2
wire rom_wait = cfg[28]; // ROMWAIT from cart. 0 - Full speed, 1 - 1 wait cycle
wire [1:0] p_wait = cfg[30:29]; // PWAIT from cart. 0 - Full speed, 1 - 1 wait cycle, 2 - 2 cycles
wire cd_en = cfg[31]; // Neo CD
// Memory card and backup ram image save/load
assign sd_rd[0] = bk_rd;
assign sd_wr[0] = bk_wr;
assign sd_lba[0] = bk_lba;
assign sd_buff_din[0] = bk_dout;
wire bk_ack = sd_ack[0];
assign sd_rd[1] = 0;
assign sd_wr[1] = 0;
assign sd_buff_din[1] = 0;
assign sd_lba[1] = 0;
wire downloading = status[0];
reg bk_rd, bk_wr;
reg bk_ena = 0;
reg bk_pending = 0;
reg [31:0] bk_lba;
wire bk_autosave = status[24];
// Memory write flag for backup memory & memory card
// (~nBWL | ~nBWU) : [AES] Unibios (set to MVS) softdip settings, [MVS] cab settings, dates, timer, high scores, saves, & bookkeeeping
// CARD_WE : [AES/MVS] game saves and high scores
wire bk_change = sram_slot_we | CARD_WE;
wire memcard_change;
reg sram_slot_we;
always @(posedge clk_sys) begin
sram_slot_we <= 0;
if(~nBWL | ~nBWU) begin
sram_slot_we <= (M68K_ADDR[15:1] >= 'h190 && M68K_ADDR[15:1] < 'h4190);
end
end
always @(posedge clk_sys) begin
reg old_downloading = 0;
old_downloading <= downloading;
if(~old_downloading & downloading) bk_ena <= 0;
// Save file always mounted in the end of downloading state.
if(downloading && img_mounted[0] && !img_readonly) bk_ena <= 1;
// Determine whether file needs to be written
if (bk_change) bk_pending <= 1;
else if (bk_state) bk_pending <= 0;
end
wire bk_load = status[21];
wire bk_save = status[12] | (bk_autosave & OSD_STATUS);
reg bk_loading = 0;
reg bk_state = 0;
always @(posedge clk_sys) begin
reg old_downloading = 0;
reg old_load = 0, old_save = 0, old_ack;
old_downloading <= downloading;
old_load <= bk_load;
old_save <= bk_save;
old_ack <= bk_ack;
if(~old_ack & bk_ack) {bk_rd, bk_wr} <= 0;
if(!bk_state) begin
if(bk_ena & ((~old_load & bk_load) | (~old_save & bk_save & bk_pending))) begin
bk_state <= 1;
bk_loading <= bk_load;
bk_lba <= 0;
bk_rd <= bk_load;
bk_wr <= ~bk_load;
end
// always load backup so it will erase the memory if doesn't exist
if(old_downloading & ~downloading & bk_ena) begin
bk_state <= 1;
bk_loading <= 1;
bk_lba <= 0;
bk_rd <= 1;
bk_wr <= 0;
end
end else begin
if(old_ack & ~bk_ack) begin
if (bk_lba >= 'h8F) begin // 64KB + 8KB regardless the selected system
bk_loading <= 0;
bk_state <= 0;
end else begin
bk_lba <= bk_lba + 1'd1;
bk_rd <= bk_loading;
bk_wr <= ~bk_loading;
end
end
end
end
wire [1:0] CD_REGION;
always @(status[11:10])
begin
// CD Region code remap:
// status[11:10] remap
// 00 10 US
// 01 01 EU
// 10 11 JP
// 11 00 ASIA
case(status[11:10])
2'b00: CD_REGION = 2'b10;
2'b01: CD_REGION = 2'b01;
2'b10: CD_REGION = 2'b11;
2'b11: CD_REGION = 2'b00;
endcase
end
wire [2:0] CD_TR_AREA; // Transfer area code
wire [15:0] CD_TR_WR_DATA;
wire [19:1] CD_TR_WR_ADDR;
wire [1:0] CD_BANK_SPR;
wire CD_TR_WR_SPR, CD_TR_WR_PCM, CD_TR_WR_Z80, CD_TR_WR_FIX;
wire CD_TR_RD_SPR, CD_TR_RD_FIX, CD_TR_RD_Z80, CD_TR_RD_PCM;
wire CD_USE_SPR, CD_USE_FIX, CD_USE_Z80, CD_USE_PCM;
wire CD_UPLOAD_EN;
wire CD_BANK_PCM;
wire CD_IRQ;
wire CD_VBLANK_IRQ_EN, CD_TIMER_IRQ_EN;
wire DMA_RUNNING, DMA_WR_OUT, DMA_RD_OUT;
wire [15:0] DMA_DATA_OUT;
wire [23:0] DMA_ADDR_IN;
wire [23:0] DMA_ADDR_OUT;
wire [15:0] DMA_DATA_IN = CD_TR_RD_PCM ? { 8'h00, ADPCMA_DOUT } : PROM_DATA;
wire DMA_SDRAM_BUSY;
wire PROM_DATA_READY;
wire [15:0] CD_AUDIO_L, CD_AUDIO_R;
//CD communication
reg [48:0] cd_in;
wire [48:0] cd_out;
wire [35:0] EXT_BUS;
wire CD_DATA_WR_READY, CDDA_WR_READY;
hps_ext hps_ext
(
.clk_sys(clk_sys),
.EXT_BUS(EXT_BUS),
.cd_data_ready(CD_DATA_WR_READY),
.cdda_ready(CDDA_WR_READY),
.cd_in(cd_in),
.cd_out(cd_out)
);
reg [39:0] CDD_STATUS;
wire [39:0] CDD_COMMAND_DATA;
wire CDD_COMMAND_SEND;
reg CDD_STATUS_LATCH;
wire [1:0] cd_speed = status[30:29];
always @(posedge clk_sys) begin
reg cd_out48_last = 1;
reg cdd_send_old = 0;
CDD_STATUS_LATCH <= 0;
if (cd_out[48] != cd_out48_last) begin
cd_out48_last <= cd_out[48];
CDD_STATUS <= cd_out[39:0];
CDD_STATUS_LATCH <= 1;
end
cdd_send_old <= CDD_COMMAND_SEND;
if (CDD_COMMAND_SEND && !cdd_send_old) begin
cd_in[47:0] <= {6'd0,cd_speed,CDD_COMMAND_DATA};
cd_in[48] <= ~cd_in[48];
end else begin
if (old_reset & ~nRESET) begin
cd_in[47:0] <= 8'hFF;
cd_in[48] <= ~cd_in[48];
end
end
end
//extend ioctl_wr for 16 cycles
reg ioctl_wr_x;
always @(posedge clk_sys) begin
reg [3:0] cnt = 0;
if (ioctl_wr) begin
cnt <= 4'd15;
ioctl_wr_x <= 1;
end
else if (cnt) begin
cnt <= cnt - 1'd1;
end
else begin
ioctl_wr_x <= 0;
end
end
localparam CD_MCLK = 48335658;
wire CDDA_CLK;
CEGen CEGEN_CDDA_CLK
(
.CLK(CLK_48M),
.RST_N(nRESET),
.IN_CLK(CD_MCLK),
.OUT_CLK(44100),
.CE(CDDA_CLK)
);
wire CD_DATA_DOWNLOAD = ioctl_download & (ioctl_index[5:0] == 6'h02);
wire CD_DATA_WR = ioctl_wr_x & CD_DATA_DOWNLOAD;
wire CDDA_DOWNLOAD = ioctl_download & (ioctl_index[5:0] == 6'h04);
wire CDDA_WR = ioctl_wr_x & CDDA_DOWNLOAD;
cd_sys #(.MCLK(CD_MCLK)) cdsystem(
.nRESET(nRESET),
.clk_sys(CLK_48M), .CLK_68KCLK_EN(CLK_EN_68K_P),
.M68K_ADDR(M68K_ADDR), .M68K_DATA(M68K_DATA), .A22Z(A22Z), .A23Z(A23Z),
.nLDS(nLDS), .nUDS(nUDS), .M68K_RW(M68K_RW), .nAS(nAS), .nDTACK(nDTACK_ADJ),
.nBR(nBR), .nBG(nBG), .nBGACK(nBGACK),
.SYSTEM_CDx(SYSTEM_CDx),
.CD_REGION(CD_REGION),
.CD_SPEED(cd_speed),
.CD_LID(~status[15] ^ SYSTEM_CDZ), // CD lid state (DEBUG)
.CD_VIDEO_EN(CD_VIDEO_EN), .CD_FIX_EN(CD_FIX_EN), .CD_SPR_EN(CD_SPR_EN),
.CD_nRESET_Z80(CD_nRESET_Z80),
.CD_TR_WR_SPR(CD_TR_WR_SPR), .CD_TR_WR_PCM(CD_TR_WR_PCM),
.CD_TR_WR_Z80(CD_TR_WR_Z80), .CD_TR_WR_FIX(CD_TR_WR_FIX),
.CD_TR_RD_FIX(CD_TR_RD_FIX), .CD_TR_RD_SPR(CD_TR_RD_SPR),
.CD_TR_RD_Z80(CD_TR_RD_Z80), .CD_TR_RD_PCM(CD_TR_RD_PCM),
.CD_USE_FIX(CD_USE_FIX), .CD_USE_SPR(CD_USE_SPR),
.CD_USE_Z80(CD_USE_Z80), .CD_USE_PCM(CD_USE_PCM),
.CD_TR_AREA(CD_TR_AREA),
.CD_BANK_SPR(CD_BANK_SPR), .CD_BANK_PCM(CD_BANK_PCM),
.CD_TR_WR_DATA(CD_TR_WR_DATA), .CD_TR_WR_ADDR(CD_TR_WR_ADDR),
.CD_UPLOAD_EN(CD_UPLOAD_EN),
.CD_IRQ(CD_IRQ), .IACK(IACK),
.CD_VBLANK_IRQ_EN(CD_VBLANK_IRQ_EN), .CD_TIMER_IRQ_EN(CD_TIMER_IRQ_EN),
.CDD_STATUS_IN(CDD_STATUS), .CDD_STATUS_LATCH(CDD_STATUS_LATCH),
.CDD_COMMAND_DATA(CDD_COMMAND_DATA), .CDD_COMMAND_SEND(CDD_COMMAND_SEND),
.CD_DATA_DOWNLOAD(CD_DATA_DOWNLOAD), .CD_DATA_WR(CD_DATA_WR),
.CD_DATA_DIN(ioctl_dout),
.CD_DATA_ADDR(ioctl_addr[11:1]),
.CD_DATA_WR_READY(CD_DATA_WR_READY),
.CDDA_RD(CDDA_CLK), .CDDA_WR(CDDA_WR),
.CD_AUDIO_L(CD_AUDIO_L), .CD_AUDIO_R(CD_AUDIO_R),
.CDDA_WR_READY(CDDA_WR_READY),
.DMA_RUNNING(DMA_RUNNING),
.DMA_DATA_IN(DMA_DATA_IN), .DMA_DATA_OUT(DMA_DATA_OUT),
.DMA_WR_OUT(DMA_WR_OUT), .DMA_RD_OUT(DMA_RD_OUT),
.DMA_ADDR_IN(DMA_ADDR_IN), // Used for reading
.DMA_ADDR_OUT(DMA_ADDR_OUT), // Used for writing
.DMA_SDRAM_BUSY(DMA_SDRAM_BUSY | ddram_wait | ADPCMA_RD_WAIT)
);
// The P1 zone is writable on the Neo CD
// Is there a write enable register for it ?
wire CD_EXT_WR = DMA_RUNNING ? (SYSTEM_CDx & (DMA_ADDR_OUT[23:21] == 3'd0) & DMA_WR_OUT) : // DMA writes to $000000~$1FFFFF
(SYSTEM_CDx & ~|{A23Z, A22Z, M68K_ADDR[21]} & ~M68K_RW & ~(nLDS & nUDS)); // CPU writes to $000000~$1FFFFF
wire nROMOE = nROMOEL & nROMOEU;
wire nPORTOE = nPORTOEL & nPORTOEU;
// CD system work ram is in SDRAM
wire CD_EXT_RD = DMA_RUNNING ? (SYSTEM_CDx & (DMA_ADDR_IN[23:21] == 3'd0) & DMA_RD_OUT) : // DMA reads from $000000~$1FFFFF
(SYSTEM_CDx & (~nWRL | ~nWRU)); // CPU reads from $100000~$1FFFFF
wire sdram_ready;
wire [26:1] sdram_addr;
wire [15:0] sdram_dout;
wire [15:0] sdram_din;
// ioctl_download is used to load the system ROM on CD systems, we need it !
reg ioctl_en;
always_ff @(posedge clk_sys) begin
ioctl_en <= SYSTEM_CDx ? (ioctl_index == INDEX_SPROM) :
(ioctl_index != INDEX_LOROM && ioctl_index != INDEX_M1ROM && ioctl_index != INDEX_MEMCP && (ioctl_index < INDEX_VROMS || ioctl_index >= INDEX_CROMS));
end
wire [26:0] CROM_LOAD_ADDR = ({ioctl_addr[25:0], 1'b0} + {ioctl_index[7:1]-INDEX_CROMS[7:1], 18'h00000, ioctl_index[0], 1'b0});
wire [26:0] VROM_LOAD_ADDR = ({1'b0, ioctl_addr[25:0]} + {ioctl_index[7:0]-INDEX_VROMS[7:0], 19'h00000});
localparam SPROM_OFFSET = 27'h0000000; // System ROM: $0000000~$007FFFF
localparam SFIXROM_OFFSET = 27'h0020000; // SFIX: $0020000~$003FFFF (in sys ROM)
localparam S1ROM_OFFSET = 27'h0080000; // S1: $0080000~$00FFFFF
localparam P1ROM_A_OFFSET = 27'h0200000; // P1+: $0200000~...
localparam P1ROM_B_OFFSET = 27'h0280000; // P1: $0280000~$02FFFFF (secondary 512KB)
localparam P2ROM_OFFSET = 27'h0300000; // P2+: $0300000~...
wire [26:0] ioctl_addr_offset =
(ioctl_index == INDEX_SPROM) ? {SPROM_OFFSET[26:19] , ioctl_addr[18:0]} : // System ROM: $0000000~$007FFFF
(ioctl_index == INDEX_SFIXROM) ? {SFIXROM_OFFSET[26:17], ioctl_addr[16:0]} : // SFIX: $0020000~$003FFFF (in sys ROM)
(ioctl_index == INDEX_S1ROM) ? {S1ROM_OFFSET[26:19] , ioctl_addr[18:0]} : // S1: $0080000~$00FFFFF
(ioctl_index == INDEX_P1ROM_A) ? P1ROM_A_OFFSET + ioctl_addr : // P1+: $0200000~...
(ioctl_index == INDEX_P1ROM_B) ? {P1ROM_B_OFFSET[26:19], ioctl_addr[18:0]} : // P1: $0280000~$02FFFFF (secondary 512KB)
(ioctl_index == INDEX_P2ROM) ? P2ROM_OFFSET + ioctl_addr : // P2+: $0300000~...
(ioctl_index == INDEX_CROM0) ? {CROM_START, 20'd0} + ioctl_addr : // C: end of P, consolidated CROM
(ioctl_index >= INDEX_CROMS) ? {CROM_START, 20'd0} + CROM_LOAD_ADDR : // C*: end of P
27'h0100000; // undefined case, use work RAM address to make sure no ROM gets overwritten
reg [6:0] CROM_START;
reg [26:0] P2ROM_MASK, CROM_MASK, V1ROM_MASK, V2ROM_MASK, MROM_MASK;
always_ff @(posedge clk_sys) begin
reg old_rst;
reg old_download;
old_rst <= status[0];