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files.qip
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files.qip
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set_global_assignment -name SYSTEMVERILOG_FILE Arcade-KickAndRun.sv
set_global_assignment -name SDC_FILE "Arcade-KickAndRun.sdc"
set_global_assignment -name VERILOG_FILE rtl/addr_decode.v
set_global_assignment -name VERILOG_FILE rtl/core.v
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VERILOG_FILE rtl/ecpu/ecpu.v
set_global_assignment -name VERILOG_FILE rtl/ecpu/ecpu_rom.v
set_global_assignment -name VERILOG_FILE rtl/fw/clk_en.v
set_global_assignment -name VERILOG_FILE rtl/fw/dpram.v
#set_global_assignment -name SYSTEMVERILOG_FILE rtl/fw/sdram.sv
#set_global_assignment -name VERILOG_FILE rtl/fw/ddram.v
set_global_assignment -name VERILOG_FILE rtl/fw/falling_edge.v
set_global_assignment -name VERILOG_FILE rtl/fw/hvgen.v
set_global_assignment -name VERILOG_FILE rtl/fw/ram.v
set_global_assignment -name VERILOG_FILE rtl/fw/rising_edge.v
set_global_assignment -name VERILOG_FILE rtl/mcpu/mcpu.v
set_global_assignment -name VERILOG_FILE rtl/mcpu/mcpu_rom.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/mcu/M6801_core.sv
set_global_assignment -name VERILOG_FILE rtl/mcu/mcu.v
set_global_assignment -name QIP_FILE rtl/pll/pll_0002_q13.qip
set_global_assignment -name VERILOG_FILE rtl/scpu/scpu.v
set_global_assignment -name VERILOG_FILE rtl/scpu/scpu_rom.v
set_global_assignment -name QIP_FILE rtl/tv80/TV80.qip
set_global_assignment -name VERILOG_FILE rtl/video/data.v
set_global_assignment -name VERILOG_FILE rtl/video/video.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt03.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt03_acc.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt10.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt10_acc.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12.v
set_global_assignment -name VHDL_FILE rtl/ym2203/jt12.vhd
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_acc.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_csr.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_div.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_dout.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_eg.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_eg_cnt.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_eg_comb.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_eg_ctrl.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_eg_final.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_eg_pure.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_eg_step.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_exprom.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_kon.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_lfo.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_logsin.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_mmr.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_mod.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_op.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_pcm.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_pcm_interpol.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_pg.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_pg_comb.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_pg_dt.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_pg_inc.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_pg_sum.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_pm.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_reg.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_rst.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_sh.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_sh24.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_sh_rst.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_single_acc.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_sumch.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_timers.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt12_top.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcm.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcma_lut.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcmb.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcmb_cnt.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcmb_gain.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcmb_interpol.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcm_acc.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcm_cnt.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcm_comb.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcm_dbrom.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcm_div.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcm_drvA.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcm_drvB.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcm_dt.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_adpcm_gain.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/adpcm/jt10_cen_burst.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/alt/eg_cnt.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/alt/eg_comb.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/alt/eg_mux.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/alt/eg_step.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/alt/eg_step_ram.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/dac/jt12_dac.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/dac/jt12_dac2.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/deprecated/jt12_amp.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/deprecated/jt12_mod24.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/deprecated/jt12_mod6.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/deprecated/jt12_opram.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/jt49.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/jt49_bus.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/jt49_cen.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/jt49_div.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/jt49_eg.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/jt49_exp.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/jt49_noise.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/filter/jt49_dcrm.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/filter/jt49_dcrm2.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/filter/jt49_dly.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/jt49/filter/jt49_mave.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/mixer/jt12_comb.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/mixer/jt12_decim.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/mixer/jt12_fm_uprate.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/mixer/jt12_genmix.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/mixer/jt12_interpol.v
set_global_assignment -name VERILOG_FILE rtl/ym2203/mixer/jt12_mixer.v