core-v-mcu-emul.core

CAPI=2:

# Copyright 2021 OpenHW Group
# Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1

name: openhwgroup.org:systems:core-v-mcu-emul
description: CORE-V MCU Emulation Top.

filesets:
  emulation-rtl:
    depend:
    - openhwgroup.org:systems:core-v-mcu
    - pulp-platform.org::tech_cells_xilinx
    files:
    - emulation/xilinx/rtl/cv32e40p_clock_gate.sv
    - emulation/xilinx/rtl/fpga_bootrom.sv
    - emulation/xilinx/rtl/fpga_clk_gen.sv
    - emulation/xilinx/rtl/fpga_interleaved_ram.sv
    - emulation/xilinx/rtl/fpga_private_ram.sv
    - emulation/xilinx/rtl/fpga_slow_clk_gen.sv
    - emulation/xilinx/rtl/pad_functional_xilinx.sv
    - emulation/xilinx/rtl/pulp_clock_gating_xilinx.sv
    - emulation/xilinx/rtl/xilinx_core_v_mcu.v
    file_type: systemVerilogSource

  genesys2-xdc:
    files:
    - constraints/genesys2.xdc
    file_type: xdc

  genesys2-cfg:
    files:
    - fpga/genesys2.tcl
    file_type: tclSource

  nexys-xdc:
    files:
    - emulation/core-v-mcu-nexys/constraints/core-v-mcu-pin-assignment.xdc
    file_type: xdc

  nexys-cfg:
    files:
    - emulation/core-v-mcu-nexys/tcl/common.tcl
    - emulation/core-v-mcu-nexys/tcl/flatten.tcl
    file_type: tclSource

  xilinx-ips:
    files:
    - emulation/xilinx/ips/xilinx_clk_mngr.tcl
    - emulation/xilinx/ips/xilinx_slow_clk_mngr.tcl
    - emulation/xilinx/ips/xilinx_interleaved_ram.tcl
    - emulation/xilinx/ips/xilinx_private_ram.tcl
    file_type: tclSource

parameters:
  PULP_FPGA_EMUL:
    datatype: bool
    paramtype: vlogdefine
    default: true

targets:
  default: &default
    filesets:
    - emulation-rtl
    - xilinx-ips
    toplevel: xilinx_core_v_mcu

  genesys2:
    default_tool: vivado
    parameters: [PULP_FPGA_EMUL=true]
    description: Digilent Genesys2 Board
    filesets:
    - files-rtl
    - genesys2-cfg
    - genesys2-xdc
    - xilinx-ips
    tools:
      vivado:
        part: xc7k325tffg900-2
    toplevel: xilinx_core_v_mcu

  nexys-a7-100t:
    <<: *default
    default_tool: vivado
    description: Digilent Nexys-A7-100T Board
    parameters:
    - PULP_FPGA_EMUL=true
    filesets_append:
    - nexys-cfg
    - nexys-xdc
    tools:
      vivado:
        part: xc7a100tcsg324-1
    toplevel: xilinx_core_v_mcu