control_path.vhd.bak

library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity control_path is
	port(
		reset, clock: in std_logic; 
		op_code: in std_logic_vector(3 downto 0);
		CZ: in std_logic_vector(1 downto 0);
		C: out std_logic_vector(26 downto 0);
		state_out: out std_logic_vector(4 downto 0);
		CY, Z, invalid_next: in std_logic);
end entity;

architecture fsm of control_path is
	type fsm_state is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16,s17,s18);
	signal Q, nQ: fsm_state := S0;
begin

		clockcycle:
		process(clock, nQ)
	begin
		if (clock'event and clock = '1') then
			Q <= nQ;
		end if;
	end process;
	control_pin:
	process(op_code,Q)
	begin
	
		C<= (others => '0');
		case Q is
			when S0 =>
							C <= (others => '0');
							state_out <= "00000";
			when S1 =>
						
			
			
		end if;
		end process;
		
		stae_next:
		process(op_code,  CY,CZ,  Z, invalid_next, reset, Q)
		begin
		nQ <= Q;
		if (reset = '1') then
			nQ <= S0;
		else
			case Q is
					 when S0 => nQ <= S1;
					 when S1 =>
									case op_code is
										when others => nQ<=S2;
										end case;
					when S2 =>
									case op_code is
										when "0001" | "0010"=>
												case CZ is
													when "00" => nQ <= S3;
													when "10" =>
																	if (CY = '1') then	nQ <= S3;
																		else	nQ <= S5;
																	end if;
													when "01" =>
																	if (Z = '1') then	nQ <= S3;
																	else nQ <= S5;
																	end if;
													when "11" =>nQ <= S3;
													when others =>	nQ <= S5;
													end case;
										when others =>	nQ <= S5;
										end case;
					when S3 => nQ <= S4;	
					when S4 => nQ <= S5;	
				end case;
				end if;
				end process;
	
end architecture;