From bf10cec2f12aa37403067e5e7ff588bafcf1d9d3 Mon Sep 17 00:00:00 2001 From: Matthias Hertel Date: Tue, 7 May 2024 10:38:13 +0200 Subject: [PATCH] Updates for 24.02 - Test Framework removed / needs update first - Added Hello World csolution for simple integration test - Signal library added to pack - devcontainer using Arm-MLOps docker environment - tasks for VSC --- .devcontainer/Dockerfile | 4 +- tensorflow-build/README.md | 79 +- tensorflow-build/build.sh | 29 - tensorflow-build/build_d.sh | 8 +- tensorflow-build/build_r.sh | 47 +- tensorflow-build/clean_file_list.py | 13 +- tensorflow-build/generate_cmsis_pack.py | 11 +- tensorflow-build/template/cmsis_pdsc.tpl | 16 +- .../App/Validation_CMSIS-NN/App.clayer.yml | 46 - .../RTE/Machine_Learning/debug_log.cpp | 43 - .../RTE/Machine_Learning/micro_time.cpp | 67 - .../RTE/Machine_Learning/system_setup.cpp | 36 - .../arm_nn_softmax_common_s8.c | 141 -- .../App/Validation_CMSIS-NN/retarget_stdio.c | 115 -- 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tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/retarget_stdio.c delete mode 100644 tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/SSE-300-MPS3.cprj delete mode 100644 tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/packlist delete mode 100644 tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/platform_setup.c delete mode 100644 tensorflow-test/vht/packs/packinstall.sh delete mode 100644 tensorflow-test/vht/vht.yml delete mode 100644 tensorflow-test/vht/vht_config.txt diff --git a/.devcontainer/Dockerfile b/.devcontainer/Dockerfile index a9a2e1a..e746060 100644 --- a/.devcontainer/Dockerfile +++ b/.devcontainer/Dockerfile @@ -6,8 +6,8 @@ WORKDIR /tensorflow-pack RUN apt-get update -y && apt-get upgrade -y -RUN apt-get install rsync wget git zip curl -y --fix-missing +RUN apt-get install rsync wget git zip curl ninja-build -y --fix-missing RUN pip3 install pillow requests six semantic_version pyyml -#RUN su -l arm_mlops_docker -c "cpackget index --force https://www.keil.com/pack/index.pidx" \ No newline at end of file + diff --git a/tensorflow-build/README.md b/tensorflow-build/README.md index e694871..43e2be9 100644 --- a/tensorflow-build/README.md +++ b/tensorflow-build/README.md @@ -1,20 +1,42 @@ + # tensorflow-build Directory contains scripts and assets to compile the CMSIS-pack containing the latest TensorFlow Lite Micro. -## build_r.sh -Entry point to run the full workflow to download, sort, generate source trees and build the pack. -### The workflow is: +## build_r.sh (build_d.sh for development releases) +The build_r.sh script serves as the entry point for running a full workflow that involves downloading, sorting, generating source trees, and building a pack. Steps involved in this workflow: + +1. **Get the latest root repository**: The script starts by retrieving the latest root repository from mlplatform.org. This repository contains a list of JSON files that index release SHAs for a specific release. This step ensures that the script is working with the most up-to-date information. + +2. **Retrieve repositories for a specified release**: The script then proceeds to retrieve the repositories associated with a specified release. The release version is passed to the script as a parameter. For example, if the release version is "20.02", the script will fetch the repositories related to that specific release. + +3. **Create source trees**: The create_tflm_tree.py script is used to generate source trees for different variants, namely "Reference", "CMSIS-NN", and "Ethos-U". These source trees serve as the foundation for building the pack. + +4. **Write source file lists**: For each source tree generated in the previous step, the script writes a list of files used in that particular source tree into a text file with a name like srcs.*.lst. These lists of source files provide a comprehensive overview of the files included in each source tree. + +5. **Merge determined sources**: The script then merges the determined sources into a build directory. This step brings together the necessary files from the different source trees to create a unified set of sources for the pack. + +6. **Apply patches**: The script applies a series of patches to the source files. These patches are necessary to ensure compatibility and correct functionality of the TensorFlow Lite Micro code within the CMSIS-Pack environment. The patches are applied using the 'patch' command, and the specific patches to be applied are determined by the script based on the release version and the specific source tree variant. + +7. **Run generate_cmsis_pack.py**: Finally, the script executes the generate_cmsis_pack.py script and passes the lists of sources as arguments. This script is responsible for generating the CMSIS pack, which is a collection of software components and device support files used in embedded systems development. + +## generate_cmsis_pack.py +This script is responsible for generating the CMSIS pack. It takes several parameters, including paths to source files, headers, and the release version. Here are the steps involved in this script: + +1. **Read Parameters**: The script starts by reading the parameters passed to it. These parameters include paths to source files, headers, and the release version. + +2. **Pull PackChk**: The script then pulls PackChk for the platform the script is executed on. PackChk is a tool used to validate the CMSIS pack. + +3. **Generate PDSC File**: Using the input parameters, the script generates a PDSC (Pack Description) file. This file describes the pack contents, including software components, device support files, and examples. -1. Get the latest root repository from mlplatform.org. It contains a list of json files with an index of release SHAs for a specific release. -2. Retrieve the repositories for a specified release (e.g. "20.02"). This release is passed to the github workflow as a parameter. -3. create_tflm_tree.py is used to create the source trees for variants "Reference", "CMSIS-NN", "Ethos-U". -4. For each source tree a list of files used it written into a srcs.*.lst text file. -5. Merge determined sources into build directory. -6. Run generate_cmsis_pack.py and pass the lists of sources. +4. **Validate PDSC File**: The generated PDSC file is then validated using PackChk. If the validation fails, the script will stop execution. -## generate_cmsis_pack.py +5. **Generate CMSIS Pack**: If the PDSC file passes validation, the script proceeds to generate the CMSIS pack. This pack is a collection of software components and device support files used in embedded systems development. + +6. **Output**: The output of this script is a tensorflow-lite-micro.*.pack file, which is only generated when the PDSC validation passes. + +## generate_cmsis_pack.py Usage ``` Parameters are: --input_template Path to template file pdsc. @@ -33,4 +55,39 @@ Parameters are: ``` Internally generate_cmsis_pack.py will pull PackChk for the platform the script is executed on. -The generated pdsc will be validated and the tensorflow-lite-micro.*.pack will only be generated when validation passes. \ No newline at end of file +The generated pdsc will be validated and the tensorflow-lite-micro.*.pack will only be generated when validation passes. + +## Additional Scripts in the Repository + +### get_releases.py + +""" +This script retrieves the latest releases from a GitHub repository. + +Usage: + python get_releases.py [repository] + +Arguments: + repository (str): The name of the GitHub repository to retrieve releases from. + +Returns: + list: A list of dictionaries, where each dictionary represents a release and contains the following keys: + - name (str): The name of the release. + - tag_name (str): The tag name of the release. + - published_at (str): The date and time when the release was published. + - assets (list): A list of dictionaries representing the assets associated with the release, where each dictionary contains the following keys: + - name (str): The name of the asset. + - download_url (str): The URL to download the asset. + +Example: + python get_releases.py myrepo +""" + +### clean_file_list.py +""" +This script provides functions to clean up a list of file names. + +The `clean_file_list` module contains functions that can be used to remove unwanted characters and formats from a list of file names. It provides a simple and efficient way to sanitize file names before further processing. + +Usage: + python clean_file_list.py \ No newline at end of file diff --git a/tensorflow-build/build.sh b/tensorflow-build/build.sh deleted file mode 100755 index f248563..0000000 --- a/tensorflow-build/build.sh +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/sh -python3 ./tensorflow-pack/tensorflow-build/generate_cmsis_pack.py --tensorflow_path=./tensorflow --input_template=./tensorflow-pack/tensorflow-build/template/cmsis_pdsc.tpl --srcs=./tensorflow-pack/tensorflow-build/srcs.lst --hdrs=./tensorflow-pack/tensorflow-build/hdrs.lst --hdrs-cmsis-nn=./tensorflow-pack/tensorflow-build/hdrs.cmsis-nn.lst --srcs-cmsis-nn=./tensorflow-pack/tensorflow-build/srcs.cmsis-nn.lst --hdrs-ethos=./tensorflow-pack/tensorflow-build/hdrs.ethos.lst --srcs-ethos=./tensorflow-pack/tensorflow-build/srcs.ethos.lst --testhdrs=./tensorflow-pack/tensorflow-build/hdrs.test.lst --testsrcs=./tensorflow-pack/tensorflow-build/srcs.test.lst --util_src=./tensorflow-pack/tensorflow-build/util_srcs.lst - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/tensorflow-build/build_d.sh b/tensorflow-build/build_d.sh index 4fa6967..1f587ab 100755 --- a/tensorflow-build/build_d.sh +++ b/tensorflow-build/build_d.sh @@ -1,6 +1,7 @@ #!/bin/sh -echo Building from latest main branch - nightly build $1 + +echo Building from latest main branch - nightly build" $1 mkdir ./tensorflow-pack/tensorflow-build/rel mkdir ./tensorflow-pack/tensorflow-build/rel/mlplatform @@ -12,8 +13,11 @@ wget -O ./tensorflow-pack/tensorflow-build/rel/master.tar.gz https://review.mlpl tar -xzf ./tensorflow-pack/tensorflow-build/rel/master.tar.gz -C ./tensorflow-pack/tensorflow-build/rel/mlplatform # Get ml-platforms srcs cd ./tensorflow-pack/tensorflow-build/rel/mlplatform/ + +echo Fetching ml-platforms sources python3 fetch_externals.py fetch + cd ./core_software/tflite_micro python3 ./tensorflow/lite/micro/tools/project_generation/create_tflm_tree.py \ @@ -23,6 +27,7 @@ python3 ./tensorflow/lite/micro/tools/project_generation/create_tflm_tree.py \ > ../../../../../tensorflow-build/srcs.raw rsync -a ../../../../../tensorflow-build/src/tensorflow ../../../../../tensorflow-build/gen/build + python3 ./tensorflow/lite/micro/tools/project_generation/create_tflm_tree.py \ --makefile_options="TARGET=cortex_m_generic OPTIMIZED_KERNEL_DIR=cmsis_nn TARGET_ARCH=cortex-m55" \ --print_src_files --rename_cc_to_cpp\ @@ -50,6 +55,7 @@ python3 ./tensorflow-pack/tensorflow-build/clean_file_list.py \ python3 ./tensorflow-pack/tensorflow-build/clean_file_list.py \ ./tensorflow-pack/tensorflow-build/srcs.ethos_u.raw > ./tensorflow-pack/tensorflow-build/srcs.ethos_u.lst + python3 ./tensorflow-pack/tensorflow-build/generate_cmsis_pack.py \ --release=1.99 \ --candidate_rev=$1 \ diff --git a/tensorflow-build/build_r.sh b/tensorflow-build/build_r.sh index 3aefd14..4f3d538 100755 --- a/tensorflow-build/build_r.sh +++ b/tensorflow-build/build_r.sh @@ -1,19 +1,45 @@ #!/bin/sh -echo $1 $2 - +echo "\033[0;32m" +echo "Building from mlplatforms release: " $1 +echo "Release tag: " $2 + +# Check if working directories exist and delete if so. Then create new. +if [ -d "./tensorflow-pack/tensorflow-build/rel" ]; then + rm -rf ./tensorflow-pack/tensorflow-build/rel +fi mkdir ./tensorflow-pack/tensorflow-build/rel + +if [ -d "./tensorflow-pack/tensorflow-build/rel/mlplatform" ]; then + rm -rf ./tensorflow-pack/tensorflow-build/rel/mlplatform +fi mkdir ./tensorflow-pack/tensorflow-build/rel/mlplatform + +if [ -d "./tensorflow-pack/tensorflow-build/gen" ]; then + rm -rf ./tensorflow-pack/tensorflow-build/gen +fi mkdir ./tensorflow-pack/tensorflow-build/gen + +if [ -d "./tensorflow-pack/tensorflow-build/gen/build" ]; then + rm -rf ./tensorflow-pack/tensorflow-build/gen/build +fi mkdir ./tensorflow-pack/tensorflow-build/gen/build + # Get ml-platforms root wget -O ./tensorflow-pack/tensorflow-build/rel/master.tar.gz https://review.mlplatform.org/plugins/gitiles/ml/ethos-u/ethos-u/+archive/refs/heads/master.tar.gz + + # Extract tar.gz tar -xzf ./tensorflow-pack/tensorflow-build/rel/master.tar.gz -C ./tensorflow-pack/tensorflow-build/rel/mlplatform # Get ml-platforms srcs cd ./tensorflow-pack/tensorflow-build/rel/mlplatform/ + +echo "\033[1;33m" + python3 fetch_externals.py -c $1.json fetch +echo "\033[0;32m" + cd ./core_software/tflite_micro python3 ./tensorflow/lite/micro/tools/project_generation/create_tflm_tree.py \ @@ -22,6 +48,7 @@ python3 ./tensorflow/lite/micro/tools/project_generation/create_tflm_tree.py \ ../../../../../tensorflow-build/src \ > ../../../../../tensorflow-build/srcs.raw rsync -a ../../../../../tensorflow-build/src/tensorflow ../../../../../tensorflow-build/gen/build +rsync -a ../../../../../tensorflow-build/src/signal ../../../../../tensorflow-build/gen/build python3 ./tensorflow/lite/micro/tools/project_generation/create_tflm_tree.py \ --makefile_options="TARGET=cortex_m_generic OPTIMIZED_KERNEL_DIR=cmsis_nn TARGET_ARCH=cortex-m55" \ @@ -29,13 +56,15 @@ python3 ./tensorflow/lite/micro/tools/project_generation/create_tflm_tree.py \ ../../../../../tensorflow-build/src \ > ../../../../../tensorflow-build/srcs.cmsis_nn.raw rsync -a ../../../../../tensorflow-build/src/tensorflow ../../../../../tensorflow-build/gen/build +rsync -a ../../../../../tensorflow-build/src/signal ../../../../../tensorflow-build/gen/build python3 ./tensorflow/lite/micro/tools/project_generation/create_tflm_tree.py \ --makefile_options="TARGET=cortex_m_generic OPTIMIZED_KERNEL_DIR=cmsis_nn CO_PROCESSOR=ethos_u ETHOSU_ARCH=u55 TARGET_ARCH=cortex-m55" \ --print_src_files \ - ../../../../../tensorflow-build/src --rename_cc_to_cpp\ + ../../../../../tensorflow-build/src --rename_cc_to_cpp \ > ../../../../../tensorflow-build/srcs.ethos_u.raw rsync -a ../../../../../tensorflow-build/src/tensorflow ../../../../../tensorflow-build/gen/build +rsync -a ../../../../../tensorflow-build/src/signal ../../../../../tensorflow-build/gen/build rsync -a ./tensorflow/lite/micro/testing/*.h ../../../../../tensorflow-build/gen/build/tensorflow/lite/micro/testing/ @@ -50,6 +79,16 @@ python3 ./tensorflow-pack/tensorflow-build/clean_file_list.py \ python3 ./tensorflow-pack/tensorflow-build/clean_file_list.py \ ./tensorflow-pack/tensorflow-build/srcs.ethos_u.raw > ./tensorflow-pack/tensorflow-build/srcs.ethos_u.lst +echo "\033[0;33m" + +# If a folder ./patches/$1 exists, call the patch.sh in this folder +if [ -d "./tensorflow-pack/tensorflow-build/patches/$1" ]; then + echo "Patching" + ./tensorflow-pack/tensorflow-build/patches/$1/patch.sh +fi + +echo "\033[1;34m" + python3 ./tensorflow-pack/tensorflow-build/generate_cmsis_pack.py \ --release=1.$1 \ --candidate_rev=$2 \ @@ -64,7 +103,7 @@ python3 ./tensorflow-pack/tensorflow-build/generate_cmsis_pack.py \ --srcs-ethos=./tensorflow-pack/tensorflow-build/srcs.ethos_u.lst \ --testhdrs=./tensorflow-pack/tensorflow-build/empty.lst \ --testsrcs=./tensorflow-pack/tensorflow-build/testsrcs.lst \ - --util_src=./tensorflow-pack/tensorflow-build/empty.lst + --util_src=./tensorflow-pack/tensorflow-build/kernelutil.lst diff --git a/tensorflow-build/clean_file_list.py b/tensorflow-build/clean_file_list.py index 77fd7bf..17d9f1f 100644 --- a/tensorflow-build/clean_file_list.py +++ b/tensorflow-build/clean_file_list.py @@ -8,7 +8,18 @@ txt_file.close() no_dupes_list = list(dict.fromkeys(content_list)) +signal_files_list = [] for filename in no_dupes_list: - if not filename.startswith("signal") and if not "downloads" in filename and not "LICENSE" in filename: + if filename.startswith("signal/"): + signal_files_list.append(filename) + no_dupes_list.remove(filename) + elif not "downloads" in filename and not "LICENSE" in filename: print(filename) + + +signal_filename = in_filename.replace("srcs.", "signal.").replace(".raw", ".lst") +with open(signal_filename, 'w') as f: + for item in signal_files_list: + f.write("%s\n" % item) + diff --git a/tensorflow-build/generate_cmsis_pack.py b/tensorflow-build/generate_cmsis_pack.py index d381dfe..5845edf 100644 --- a/tensorflow-build/generate_cmsis_pack.py +++ b/tensorflow-build/generate_cmsis_pack.py @@ -156,7 +156,6 @@ def make_component_file_list(srcs_list): and src != "tensorflow/lite/c/common.c" \ and src != "tensorflow/lite/micro/cortex_m_generic/micro_time.cpp" \ and src != "tensorflow/lite/micro/cortex_m_generic/debug_log.cpp" \ - and src != "tensorflow/lite/micro/recording_micro_allocator.cpp" \ and src.endswith("_test.cc") == False: replace_srcs += ' \n' @@ -236,6 +235,14 @@ def main(unparsed_args, flags): all_test_srcs_list = test_srcs_list + test_hdrs_list all_test_srcs_list.sort() + # get signal library if exists ("signal.lst" alongside flags.srcs) + replace_signal_srcs = "" + if os.path.exists(flags.srcs.replace("srcs.", "signal.")): + signal_srcs_list = load_list_from_file(flags.srcs.replace("srcs.", "signal.")) + replace_signal_srcs = make_component_file_list(signal_srcs_list) + + print(replace_signal_srcs) + replace_core_srcs = make_component_file_list(all_core_srcs_list) replace_util_srcs = make_component_file_list(all_util_srcs_list) replace_test_srcs = make_component_file_list(all_test_srcs_list) @@ -280,6 +287,8 @@ def main(unparsed_args, flags): r'%{KERNEL_UTIL_FILES}%', replace_util_srcs, six.ensure_str(template_file_text)) template_file_text = re.sub( r'%{TEST_FILES}%', replace_test_srcs, six.ensure_str(template_file_text)) + template_file_text = re.sub( + r'%{SIGNAL_FILES_REFERENCE}%', replace_signal_srcs, six.ensure_str(template_file_text)) template_file_text = re.sub( r'%{RELEASE_VERSION}%', pack_version, template_file_text) template_file_text = re.sub( diff --git a/tensorflow-build/template/cmsis_pdsc.tpl b/tensorflow-build/template/cmsis_pdsc.tpl index fdf0413..75c9105 100644 --- a/tensorflow-build/template/cmsis_pdsc.tpl +++ b/tensorflow-build/template/cmsis_pdsc.tpl @@ -95,7 +95,7 @@ - TensorFlow Lite Micro Library + TensorFlow Lite Micro Library - Kernel Utilities @@ -105,7 +105,7 @@ - TensorFlow Lite Micro Library + TensorFlow Lite Micro Test Utilities #define RTE_ML_TF_LITE /* TF */ @@ -115,6 +115,16 @@ - + + TensorFlow Lite Micro Signal Library + + + #define RTE_ML_TF_LITE /* TF */ + + + %{SIGNAL_FILES_REFERENCE}% + + + diff --git a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/App.clayer.yml b/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/App.clayer.yml deleted file mode 100644 index 37ad4b5..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/App.clayer.yml +++ /dev/null @@ -1,46 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: App - # name: CMSIS-RTOS2_Validation - description: Validation of TensorFlow Lite Micro CMSIS Pack in Reference implementation - # packs: - # - pack: ARM::CMSIS - # - pack: ARM::CMSIS-FreeRTOS - - defines: - - PRINT_XML_REPORT=1 - - #add-paths: - #- ./Config - #- ../../../Include - - misc: - - C*: - - -Wno-macro-redefined - - -Wno-pragma-pack - - -Wno-parentheses-equality - - -fno-unwind-tables - - -ffunction-sections - - -fdata-sections - - C: - - -std=c11 - - CPP: - - -fno-rtti - - -fno-exceptions - - -fno-threadsafe-statics - - -fno-exceptions - - -std=c++11 - - components: - # [Cvendor::]Cclass[&Cbundle]:Cgroup[:Csub][&Cvariant][@[>=]Cversion] - - component: tensorflow::Machine Learning:TensorFlow:Kernel&CMSIS-NN - - component: ARM::CMSIS:NN Lib - - component: ARM::CMSIS:DSP&Source - - groups: - - - group: Source files - files: - - file: ./retarget_stdio.c - - file: ./arm_nn_softmax_common_s8.c diff --git a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/RTE/Machine_Learning/debug_log.cpp b/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/RTE/Machine_Learning/debug_log.cpp deleted file mode 100644 index bc79d43..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/RTE/Machine_Learning/debug_log.cpp +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -// Implementation for the DebugLog() function that prints to the debug logger on -// an generic Cortex-M device. - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -#include "tensorflow/lite/micro/debug_log.h" - -#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" - -static DebugLogCallback debug_log_callback = nullptr; - -void RegisterDebugLogCallback(void (*cb)(const char* s)) { - debug_log_callback = cb; -} - -void DebugLog(const char* s) { -#ifndef TF_LITE_STRIP_ERROR_STRINGS - if (debug_log_callback != nullptr) { - debug_log_callback(s); - } -#endif -} - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus diff --git a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/RTE/Machine_Learning/micro_time.cpp b/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/RTE/Machine_Learning/micro_time.cpp deleted file mode 100644 index 023ac6d..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/RTE/Machine_Learning/micro_time.cpp +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -#include "tensorflow/lite/micro/micro_time.h" - -// DWT (Data Watchpoint and Trace) registers, only exists on ARM Cortex with a -// DWT unit. -#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) -/*!< DWT Control register */ - -// DWT Control register. -#define KIN1_DWT_CYCCNTENA_BIT (1UL << 0) - -// CYCCNTENA bit in DWT_CONTROL register. -#define KIN1_DWT_CYCCNT (*((volatile uint32_t*)0xE0001004)) - -// DWT Cycle Counter register. -#define KIN1_DEMCR (*((volatile uint32_t*)0xE000EDFC)) - -// DEMCR: Debug Exception and Monitor Control Register. -#define KIN1_TRCENA_BIT (1UL << 24) - -#define KIN1_LAR (*((volatile uint32_t*)0xE0001FB0)) - -#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) - -// Unlock access to DWT (ITM, etc.)registers. -#define KIN1_UnlockAccessToDWT() KIN1_LAR = 0xC5ACCE55; - -// TRCENA: Enable trace and debug block DEMCR (Debug Exception and Monitor -// Control Register. -#define KIN1_InitCycleCounter() KIN1_DEMCR |= KIN1_TRCENA_BIT - -#define KIN1_ResetCycleCounter() KIN1_DWT_CYCCNT = 0 -#define KIN1_EnableCycleCounter() KIN1_DWT_CONTROL |= KIN1_DWT_CYCCNTENA_BIT -#define KIN1_DisableCycleCounter() KIN1_DWT_CONTROL &= ~KIN1_DWT_CYCCNTENA_BIT -#define KIN1_GetCycleCounter() KIN1_DWT_CYCCNT - -namespace tflite { - -int32_t ticks_per_second() { return 0; } - -int32_t GetCurrentTimeTicks() { - static bool is_initialized = false; - if (!is_initialized) { - KIN1_UnlockAccessToDWT(); - KIN1_InitCycleCounter(); - KIN1_ResetCycleCounter(); - KIN1_EnableCycleCounter(); - is_initialized = true; - } - return KIN1_GetCycleCounter(); -} - -} // namespace tflite diff --git a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/RTE/Machine_Learning/system_setup.cpp b/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/RTE/Machine_Learning/system_setup.cpp deleted file mode 100644 index df6cfc6..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/RTE/Machine_Learning/system_setup.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -#include "tensorflow/lite/micro/system_setup.h" -#include "stdio.h" -#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" - -extern "C" void stdio_init (void); - -namespace tflite { - -void debug_log_printf(const char* s) { - printf("%s", s); -} - -// To add an equivalent function for your own platform, create your own -// implementation file, and place it in a subfolder named after the target. See -// tensorflow/lite/micro/debug_log.cc for a similar example. -void InitializeTarget() { - stdio_init(); - RegisterDebugLogCallback(debug_log_printf); - //debug_log_printf("Initialized UART and registered Callback.") -} -} // namespace tflite diff --git a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/arm_nn_softmax_common_s8.c b/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/arm_nn_softmax_common_s8.c deleted file mode 100644 index e697767..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/arm_nn_softmax_common_s8.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (C) 2022 Arm Limited or its affiliates. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* ---------------------------------------------------------------------- - * Project: CMSIS NN Library - * Title: arm_nn_softmax_common_s8.c - * Description: Softmax with s8 input and output of s8 or s16. - * - * $Date: 17 March 2022 - * $Revision: V.1.0.1 - * - * Target Processor: Cortex-M processors - * -------------------------------------------------------------------- */ - -#include "arm_nnsupportfunctions.h" - -#define ACCUM_BITS 12 - -/** - * @ingroup groupSupport - */ - -/** - * @addtogroup Softmax - * @{ - */ - -/* - * Softmax function with s8 input and output of s8 or s16. - * - * Refer header file for details. - * - */ -void arm_nn_softmax_common_s8(const int8_t *input, - const int32_t num_rows, - const int32_t row_size, - const int32_t mult, - const int32_t shift, - const int32_t diff_min, - const bool int16_output, - void *output) -{ - const int32_t mask = (1 << shift); - - int32_t col = 0; - int32_t row_idx; - - for (row_idx = 0; row_idx < num_rows; ++row_idx) - { - // Find the maximum value in order to ensure numerical stability - int8_t max = *input; - - for (col = 1; col < row_size; ++col) - { - max = MAX(max, input[col]); - } - - int32_t diff = 0; - int32_t sum = 0; - - for (col = 0; col < row_size; ++col) - { - diff = input[col] - max; - if (diff >= diff_min) - { - sum += DIV_POW2(EXP_ON_NEG(MUL_SAT(diff * mask, mult)), ACCUM_BITS); - } - } - - const int32_t headroom = __CLZ(sum); - const int32_t shifted_scale = ONE_OVER1((sum > 0 ? sum << headroom : 0) - (1 << 31)); - int32_t bits_over_unit; - - if (int16_output) - { - int16_t *output_s16 = (int16_t *)output + row_idx * row_size; - - bits_over_unit = ACCUM_BITS - headroom + 15; - - for (col = 0; col < row_size; ++col) - { - diff = input[col] - max; - - if (diff >= diff_min) - { - const int32_t res = - DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) + - NN_Q15_MIN; - output_s16[col] = (int16_t)CLAMP(res, (int32_t)NN_Q15_MAX, (int32_t)NN_Q15_MIN); - } - else - { - output_s16[col] = NN_Q15_MIN; - } - } - } - else - { - int8_t *output_s8 = (int8_t *)output + row_idx * row_size; - - bits_over_unit = ACCUM_BITS - headroom + 23; - - for (col = 0; col < row_size; ++col) - { - diff = input[col] - max; - if (diff >= diff_min) - { - const int32_t res = - DIV_POW2(MUL_SAT(shifted_scale, EXP_ON_NEG(MUL_SAT(diff * mask, mult))), bits_over_unit) + - NN_Q7_MIN; - output_s8[col] = (int8_t)CLAMP(res, (int32_t)NN_Q7_MAX, (int32_t)NN_Q7_MIN); - } - else - { - output_s8[col] = NN_Q7_MIN; - } - } - } - - input += row_size; - } -} - -/** - * @} end of NNBasicMath group - */ \ No newline at end of file diff --git a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/retarget_stdio.c b/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/retarget_stdio.c deleted file mode 100644 index d91159f..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_CMSIS-NN/retarget_stdio.c +++ /dev/null @@ -1,115 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Name: retarget_stdio.c - * Purpose: Retarget stdio to USART - * - *---------------------------------------------------------------------------*/ - -#include "Driver_USART.h" - -#define USART_DRV_NUM 0 -#define USART_BAUDRATE 115200 - -#define _USART_Driver_(n) Driver_USART##n -#define USART_Driver_(n) _USART_Driver_(n) - -extern ARM_DRIVER_USART USART_Driver_(USART_DRV_NUM); -#define ptrUSART (&USART_Driver_(USART_DRV_NUM)) - -/* Prototypes */ -int stdio_init (void); -int stderr_putchar (int ch); -int stdout_putchar (int ch); -int stdin_getchar (void); - -/** - Initialize stdio - - \return 0 on success, or -1 on error. -*/ -int stdio_init (void) { - int32_t status; - - status = ptrUSART->Initialize(NULL); - if (status != ARM_DRIVER_OK) return (-1); - - status = ptrUSART->PowerControl(ARM_POWER_FULL); - if (status != ARM_DRIVER_OK) return (-1); - - status = ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | - ARM_USART_DATA_BITS_8 | - ARM_USART_PARITY_NONE | - ARM_USART_STOP_BITS_1 | - ARM_USART_FLOW_CONTROL_NONE, - USART_BAUDRATE); - if (status != ARM_DRIVER_OK) return (-1); - - status = ptrUSART->Control(ARM_USART_CONTROL_RX, 1); - if (status != ARM_DRIVER_OK) return (-1); - - return (0); -} - -/** - Put a character to the stderr - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stderr_putchar (int ch) { - uint8_t buf[1]; - - buf[0] = (uint8_t)ch; - if (ptrUSART->Send(buf, 1) != ARM_DRIVER_OK) { - return (-1); - } - while (ptrUSART->GetTxCount() != 1); - return (ch); -} - -/** - Put a character to the stdout - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stdout_putchar (int ch) { - uint8_t buf[1]; - - buf[0] = (uint8_t)ch; - if (ptrUSART->Send(buf, 1) != ARM_DRIVER_OK) { - return (-1); - } - while (ptrUSART->GetTxCount() != 1); - return (ch); -} - -/** - Get a character from the stdio - - \return The next character from the input, or -1 on read error. -*/ -int stdin_getchar (void) { - uint8_t buf[1]; - - if (ptrUSART->Receive(buf, 1) != ARM_DRIVER_OK) { - return (-1); - } - while (ptrUSART->GetRxCount() != 1); - return (buf[0]); -} diff --git a/tensorflow-test-ng/Layer/App/Validation_Reference/App.clayer.yml b/tensorflow-test-ng/Layer/App/Validation_Reference/App.clayer.yml deleted file mode 100644 index 9f6ba38..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_Reference/App.clayer.yml +++ /dev/null @@ -1,44 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: App - # name: CMSIS-RTOS2_Validation - description: Validation of TensorFlow Lite Micro CMSIS Pack in Reference implementation - # packs: - # - pack: ARM::CMSIS - # - pack: ARM::CMSIS-FreeRTOS - - defines: - - PRINT_XML_REPORT=1 - - #add-paths: - # - ./Config - # - ../../../Include - - misc: - - C*: - - -Wno-macro-redefined - - -Wno-pragma-pack - - -Wno-parentheses-equality - - -fno-unwind-tables - - -ffunction-sections - - -fdata-sections - - C: - - -std=c11 - - CPP: - - -fno-rtti - - -fno-exceptions - - -fno-threadsafe-statics - - -fno-exceptions - - -std=c++11 - - components: - # [Cvendor::]Cclass[&Cbundle]:Cgroup[:Csub][&Cvariant][@[>=]Cversion] - - component: tensorflow::Machine Learning:TensorFlow:Kernel&Reference - - - groups: - - - group: Source files - files: - - file: ./retarget_stdio.c diff --git a/tensorflow-test-ng/Layer/App/Validation_Reference/RTE/Machine_Learning/micro_time.cpp b/tensorflow-test-ng/Layer/App/Validation_Reference/RTE/Machine_Learning/micro_time.cpp deleted file mode 100644 index 023ac6d..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_Reference/RTE/Machine_Learning/micro_time.cpp +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -#include "tensorflow/lite/micro/micro_time.h" - -// DWT (Data Watchpoint and Trace) registers, only exists on ARM Cortex with a -// DWT unit. -#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) -/*!< DWT Control register */ - -// DWT Control register. -#define KIN1_DWT_CYCCNTENA_BIT (1UL << 0) - -// CYCCNTENA bit in DWT_CONTROL register. -#define KIN1_DWT_CYCCNT (*((volatile uint32_t*)0xE0001004)) - -// DWT Cycle Counter register. -#define KIN1_DEMCR (*((volatile uint32_t*)0xE000EDFC)) - -// DEMCR: Debug Exception and Monitor Control Register. -#define KIN1_TRCENA_BIT (1UL << 24) - -#define KIN1_LAR (*((volatile uint32_t*)0xE0001FB0)) - -#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) - -// Unlock access to DWT (ITM, etc.)registers. -#define KIN1_UnlockAccessToDWT() KIN1_LAR = 0xC5ACCE55; - -// TRCENA: Enable trace and debug block DEMCR (Debug Exception and Monitor -// Control Register. -#define KIN1_InitCycleCounter() KIN1_DEMCR |= KIN1_TRCENA_BIT - -#define KIN1_ResetCycleCounter() KIN1_DWT_CYCCNT = 0 -#define KIN1_EnableCycleCounter() KIN1_DWT_CONTROL |= KIN1_DWT_CYCCNTENA_BIT -#define KIN1_DisableCycleCounter() KIN1_DWT_CONTROL &= ~KIN1_DWT_CYCCNTENA_BIT -#define KIN1_GetCycleCounter() KIN1_DWT_CYCCNT - -namespace tflite { - -int32_t ticks_per_second() { return 0; } - -int32_t GetCurrentTimeTicks() { - static bool is_initialized = false; - if (!is_initialized) { - KIN1_UnlockAccessToDWT(); - KIN1_InitCycleCounter(); - KIN1_ResetCycleCounter(); - KIN1_EnableCycleCounter(); - is_initialized = true; - } - return KIN1_GetCycleCounter(); -} - -} // namespace tflite diff --git a/tensorflow-test-ng/Layer/App/Validation_Reference/RTE/Machine_Learning/system_setup.cpp b/tensorflow-test-ng/Layer/App/Validation_Reference/RTE/Machine_Learning/system_setup.cpp deleted file mode 100644 index df6cfc6..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_Reference/RTE/Machine_Learning/system_setup.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -#include "tensorflow/lite/micro/system_setup.h" -#include "stdio.h" -#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" - -extern "C" void stdio_init (void); - -namespace tflite { - -void debug_log_printf(const char* s) { - printf("%s", s); -} - -// To add an equivalent function for your own platform, create your own -// implementation file, and place it in a subfolder named after the target. See -// tensorflow/lite/micro/debug_log.cc for a similar example. -void InitializeTarget() { - stdio_init(); - RegisterDebugLogCallback(debug_log_printf); - //debug_log_printf("Initialized UART and registered Callback.") -} -} // namespace tflite diff --git a/tensorflow-test-ng/Layer/App/Validation_Reference/main.c b/tensorflow-test-ng/Layer/App/Validation_Reference/main.c deleted file mode 100644 index 897d681..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_Reference/main.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2022 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include "cmsis_rv2.h" - -extern int stdio_init (void); - -int main (void) { - /* Initialize stdio */ - stdio_init(); - - /* CMSIS-RTOS2 validation entry */ - cmsis_rv2(); -} - -#if defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) -void _start (void) { - main(); - - for(;;); -} -#endif diff --git a/tensorflow-test-ng/Layer/App/Validation_Reference/retarget_stdio.c b/tensorflow-test-ng/Layer/App/Validation_Reference/retarget_stdio.c deleted file mode 100644 index d91159f..0000000 --- a/tensorflow-test-ng/Layer/App/Validation_Reference/retarget_stdio.c +++ /dev/null @@ -1,115 +0,0 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Name: retarget_stdio.c - * Purpose: Retarget stdio to USART - * - *---------------------------------------------------------------------------*/ - -#include "Driver_USART.h" - -#define USART_DRV_NUM 0 -#define USART_BAUDRATE 115200 - -#define _USART_Driver_(n) Driver_USART##n -#define USART_Driver_(n) _USART_Driver_(n) - -extern ARM_DRIVER_USART USART_Driver_(USART_DRV_NUM); -#define ptrUSART (&USART_Driver_(USART_DRV_NUM)) - -/* Prototypes */ -int stdio_init (void); -int stderr_putchar (int ch); -int stdout_putchar (int ch); -int stdin_getchar (void); - -/** - Initialize stdio - - \return 0 on success, or -1 on error. -*/ -int stdio_init (void) { - int32_t status; - - status = ptrUSART->Initialize(NULL); - if (status != ARM_DRIVER_OK) return (-1); - - status = ptrUSART->PowerControl(ARM_POWER_FULL); - if (status != ARM_DRIVER_OK) return (-1); - - status = ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | - ARM_USART_DATA_BITS_8 | - ARM_USART_PARITY_NONE | - ARM_USART_STOP_BITS_1 | - ARM_USART_FLOW_CONTROL_NONE, - USART_BAUDRATE); - if (status != ARM_DRIVER_OK) return (-1); - - status = ptrUSART->Control(ARM_USART_CONTROL_RX, 1); - if (status != ARM_DRIVER_OK) return (-1); - - return (0); -} - -/** - Put a character to the stderr - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stderr_putchar (int ch) { - uint8_t buf[1]; - - buf[0] = (uint8_t)ch; - if (ptrUSART->Send(buf, 1) != ARM_DRIVER_OK) { - return (-1); - } - while (ptrUSART->GetTxCount() != 1); - return (ch); -} - -/** - Put a character to the stdout - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stdout_putchar (int ch) { - uint8_t buf[1]; - - buf[0] = (uint8_t)ch; - if (ptrUSART->Send(buf, 1) != ARM_DRIVER_OK) { - return (-1); - } - while (ptrUSART->GetTxCount() != 1); - return (ch); -} - -/** - Get a character from the stdio - - \return The next character from the input, or -1 on read error. -*/ -int stdin_getchar (void) { - uint8_t buf[1]; - - if (ptrUSART->Receive(buf, 1) != ARM_DRIVER_OK) { - return (-1); - } - while (ptrUSART->GetRxCount() != 1); - return (buf[0]); -} diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct deleted file mode 100644 index 447f912..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/ac6_arm.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c deleted file mode 100644 index a245256..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c +++ /dev/null @@ -1,218 +0,0 @@ -/****************************************************************************** - * @file startup_CMSDK_CM0plus.c - * @brief CMSIS Startup File for CMSDK_M0plus Device - ******************************************************************************/ -/* Copyright (c) 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM0plus) || defined (CMSDK_CM0plus_VHT) - #include "CMSDK_CM0plus.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#if defined CMSDK_CM0plus_VHT /* VSI Interrupts */ -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#else -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - UART0RX_Handler, /* 0 UART 0 receive interrupt */ - UART0TX_Handler, /* 1 UART 0 transmit interrupt */ - UART1RX_Handler, /* 2 UART 1 receive interrupt */ - UART1TX_Handler, /* 3 UART 1 transmit interrupt */ - UART2RX_Handler, /* 4 UART 2 receive interrupt */ - UART2TX_Handler, /* 5 UART 2 transmit interrupt */ - GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ - GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ - TIMER0_Handler, /* 8 Timer 0 interrupt */ - TIMER1_Handler, /* 9 Timer 1 interrupt */ - DUALTIMER_Handler, /* 10 Dual Timer interrupt */ - SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ - UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ - ETHERNET_Handler, /* 13 Ethernet interrupt */ - I2S_Handler, /* 14 Audio I2S interrupt */ - TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ - GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ - GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ - UART3RX_Handler, /* 18 UART 3 receive interrupt */ - UART3TX_Handler, /* 19 UART 3 transmit interrupt */ - UART4RX_Handler, /* 20 UART 4 receive interrupt */ - UART4TX_Handler, /* 21 UART 4 transmit interrupt */ - SPI_2_Handler, /* 22 SPI 2 interrupt */ - SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ -#if defined CMSDK_CM0plus_VHT - ARM_VSI0_Handler, /* 24 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 25 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 26 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 27 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 28 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 29 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 30 VSI 6 interrupt */ - ARM_VSI7_Handler /* 31 VSI 7 interrupt */ -#else - GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ - GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ - GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ - GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ - GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ - GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ - GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ - GPIO0_7_Handler /* 31 GPIO 0 individual interrupt ( 7) */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c deleted file mode 100644 index cd31f9e..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c +++ /dev/null @@ -1,74 +0,0 @@ -/****************************************************************************** - * @file system_CMSDK_CM0plus.c - * @brief CMSIS System Source File for CMSDK_M0plus Device - ******************************************************************************/ -/* Copyright (c) 2011 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM0plus) || defined (CMSDK_CM0plus_VHT) - #include "CMSDK_CM0plus.h" -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/Target.clayer.yml deleted file mode 100644 index 8e3ec74..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_CMx_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/vht_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_AC6/vht_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld deleted file mode 100644 index 59bd7d1..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/gcc_arm.ld +++ /dev/null @@ -1,279 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ - -/* -; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00400000; - -/*--------------------- Embedded RAM Configuration ---------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* -; -------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option �--section-start� or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG ((__bss_end__ - __bss_start__) / 4) - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c deleted file mode 100644 index a245256..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/startup_CMSDK_CM0plus.c +++ /dev/null @@ -1,218 +0,0 @@ -/****************************************************************************** - * @file startup_CMSDK_CM0plus.c - * @brief CMSIS Startup File for CMSDK_M0plus Device - ******************************************************************************/ -/* Copyright (c) 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM0plus) || defined (CMSDK_CM0plus_VHT) - #include "CMSDK_CM0plus.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#if defined CMSDK_CM0plus_VHT /* VSI Interrupts */ -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#else -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - UART0RX_Handler, /* 0 UART 0 receive interrupt */ - UART0TX_Handler, /* 1 UART 0 transmit interrupt */ - UART1RX_Handler, /* 2 UART 1 receive interrupt */ - UART1TX_Handler, /* 3 UART 1 transmit interrupt */ - UART2RX_Handler, /* 4 UART 2 receive interrupt */ - UART2TX_Handler, /* 5 UART 2 transmit interrupt */ - GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ - GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ - TIMER0_Handler, /* 8 Timer 0 interrupt */ - TIMER1_Handler, /* 9 Timer 1 interrupt */ - DUALTIMER_Handler, /* 10 Dual Timer interrupt */ - SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ - UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ - ETHERNET_Handler, /* 13 Ethernet interrupt */ - I2S_Handler, /* 14 Audio I2S interrupt */ - TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ - GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ - GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ - UART3RX_Handler, /* 18 UART 3 receive interrupt */ - UART3TX_Handler, /* 19 UART 3 transmit interrupt */ - UART4RX_Handler, /* 20 UART 4 receive interrupt */ - UART4TX_Handler, /* 21 UART 4 transmit interrupt */ - SPI_2_Handler, /* 22 SPI 2 interrupt */ - SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ -#if defined CMSDK_CM0plus_VHT - ARM_VSI0_Handler, /* 24 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 25 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 26 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 27 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 28 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 29 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 30 VSI 6 interrupt */ - ARM_VSI7_Handler /* 31 VSI 7 interrupt */ -#else - GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ - GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ - GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ - GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ - GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ - GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ - GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ - GPIO0_7_Handler /* 31 GPIO 0 individual interrupt ( 7) */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c deleted file mode 100644 index cd31f9e..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/RTE/Device/CMSDK_CM0plus_VHT/system_CMSDK_CM0plus.c +++ /dev/null @@ -1,74 +0,0 @@ -/****************************************************************************** - * @file system_CMSDK_CM0plus.c - * @brief CMSIS System Source File for CMSDK_M0plus Device - ******************************************************************************/ -/* Copyright (c) 2011 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM0plus) || defined (CMSDK_CM0plus_VHT) - #include "CMSDK_CM0plus.h" -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/Target.clayer.yml deleted file mode 100644 index 8e3ec74..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_CMx_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/vht_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM0plus_VHT_GCC/vht_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h b/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h deleted file mode 100644 index 46622d3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h +++ /dev/null @@ -1,585 +0,0 @@ -/****************************************************************************** - * @file partition_IOTKit_CM23.h - * @brief CMSIS-Core Initial Setup for Secure / Non-Secure Zones for IOTKit_CM23 - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef PARTITION_IOTKit_CM23_H -#define PARTITION_IOTKit_CM23_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 0 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x10000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x101FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x28200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x283FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x403FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 0 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 0 - -/* -// Interrupts 0..31 -// Non-Secure Watchdog Reset Request <0=> Secure state <1=> Non-Secure state -// Non-Secure Watchdog interrupt <0=> Secure state <1=> Non-Secure state -// S32K Timer interrupt <0=> Secure state <1=> Non-Secure state -// Timer 0 interrupt <0=> Secure state <1=> Non-Secure state -// Timer 1 interrupt <0=> Secure state <1=> Non-Secure state -// Dual Timer interrupt <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 0 - -/* -// Interrupts 32..63 -// UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 teceive interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 0, 1, 2, 3, 4 overflow interrupt <0=> Secure state <1=> Non-Secure state -// Ethernet interrupt <0=> Secure state <1=> Non-Secure state -// Audio I2S interrupt <0=> Secure state <1=> Non-Secure state -// Touch Screen interrupt <0=> Secure state <1=> Non-Secure state -// SPI 0 (SPI Header) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 1 (CLCD) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 2 (Shield ADC) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 3 (Shield 0 SPI) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 4 (Shield 1 SPI) interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 2 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 2 terminal count interrupt <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// DMA 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// GPIO 1 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_IOTKit_CM23_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c b/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c deleted file mode 100644 index 8fecd78..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c +++ /dev/null @@ -1,506 +0,0 @@ -/****************************************************************************** - * @file startup_IOTKit_CM23.c - * @brief CMSIS Startup File for IOTKit_CM23 Device - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (IOTKit_CM23) || defined (IOTKit_CM23_VHT) - #include "IOTKit_CM23.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Core IoT Interrupts */ -void NONSEC_WATCHDOG_RESET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void NONSEC_WATCHDOG_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void S32K_TIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BRIDGE_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* External Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UARTOVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* VSI Interrupts */ -#if defined (IOTKit_CM23_VHT) -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Core IoT Interrupts */ - NONSEC_WATCHDOG_RESET_Handler, /* 0 Non-Secure Watchdog Reset Handler */ - NONSEC_WATCHDOG_Handler, /* 1 Non-Secure Watchdog Handler */ - S32K_TIMER_Handler, /* 2 S32K Timer Handler */ - TIMER0_Handler, /* 3 TIMER 0 Handler */ - TIMER1_Handler, /* 4 TIMER 1 Handler */ - DUALTIMER_Handler, /* 5 Dual Timer Handler */ - 0, /* 6 Reserved */ - 0, /* 7 Reserved */ - 0, /* 8 Reserved */ - MPC_Handler, /* 9 MPC Combined (Secure) Handler */ - PPC_Handler, /* 10 PPC Combined (Secure) Handler */ - MSC_Handler, /* 11 MSC Combined (Secure) Handler */ - BRIDGE_ERROR_Handler, /* 12 Bridge Error Combined (Secure) Handler */ - 0, /* 13 Reserved */ - 0, /* 14 Reserved */ - 0, /* 15 Reserved */ - 0, /* 16 Reserved */ - 0, /* 17 Reserved */ - 0, /* 18 Reserved */ - 0, /* 19 Reserved */ - 0, /* 20 Reserved */ - 0, /* 21 Reserved */ - 0, /* 22 Reserved */ - 0, /* 23 Reserved */ - 0, /* 24 Reserved */ - 0, /* 25 Reserved */ - 0, /* 26 Reserved */ - 0, /* 27 Reserved */ - 0, /* 28 Reserved */ - 0, /* 29 Reserved */ - 0, /* 30 Reserved */ - 0, /* 31 Reserved */ - - /* External Interrupts */ - UART0RX_Handler, /* 32 UART 0 RX Handler */ - UART0TX_Handler, /* 33 UART 0 TX Handler */ - UART1RX_Handler, /* 34 UART 1 RX Handler */ - UART1TX_Handler, /* 35 UART 1 TX Handler */ - UART2RX_Handler, /* 36 UART 2 RX Handler */ - UART2TX_Handler, /* 37 UART 2 TX Handler */ - UART3RX_Handler, /* 38 UART 2 RX Handler */ - UART3TX_Handler, /* 39 UART 2 TX Handler */ - UART4RX_Handler, /* 40 UART 2 RX Handler */ - UART4TX_Handler, /* 41 UART 2 TX Handler */ - UART0_Handler, /* 42 UART 0 combined Handler */ - UART1_Handler, /* 43 UART 1 combined Handler */ - UART2_Handler, /* 44 UART 2 combined Handler */ - UART3_Handler, /* 45 UART 3 combined Handler */ - UART4_Handler, /* 46 UART 4 combined Handler */ - UARTOVF_Handler, /* 47 UART 0,1,2,3,4 Overflow Handler */ - ETHERNET_Handler , /* 48 Ethernet Handler */ - I2S_Handler, /* 49 I2S Handler */ - TSC_Handler, /* 50 Touch Screen Handler */ - SPI0_Handler, /* 51 SPI 0 Handler */ - SPI1_Handler, /* 52 SPI 1 Handler */ - SPI2_Handler, /* 53 SPI 2 Handler */ - SPI3_Handler, /* 54 SPI 3 Handler */ - SPI4_Handler, /* 55 SPI 4 Handler */ - DMA0_ERROR_Handler, /* 56 DMA 0 Error Handler */ - DMA0_TC_Handler, /* 57 DMA 0 Terminal Count Handler */ - DMA0_Handler, /* 58 DMA 0 Combined Handler */ - DMA1_ERROR_Handler, /* 59 DMA 1 Error Handler */ - DMA1_TC_Handler, /* 60 DMA 1 Terminal Count Handler */ - DMA1_Handler, /* 61 DMA 1 Combined Handler */ - DMA2_ERROR_Handler, /* 62 DMA 2 Error Handler */ - DMA2_TC_Handler, /* 63 DMA 2 Terminal Count Handler */ - DMA2_Handler, /* 64 DMA 2 Combined Handler */ - DMA3_ERROR_Handler, /* 65 DMA 3 Error Handler */ - DMA3_TC_Handler, /* 66 DMA 3 Terminal Count Handler */ - DMA3_Handler, /* 67 DMA 3 Combined Handler */ - GPIO0_Handler, /* 68 GPIO 0 Combined Handler */ - GPIO1_Handler, /* 69 GPIO 1 Combined Handler */ - GPIO2_Handler, /* 70 GPIO 2 Combined Handler */ - GPIO3_Handler, /* 71 GPIO 3 Combined Handler */ - GPIO0_0_Handler, /* 72 */ /* All P0 I/O pins used as irq source */ - GPIO0_1_Handler, /* 73 */ /* There are 16 pins in total */ - GPIO0_2_Handler, /* 74 */ - GPIO0_3_Handler, /* 75 */ - GPIO0_4_Handler, /* 76 */ - GPIO0_5_Handler, /* 77 */ - GPIO0_6_Handler, /* 78 */ - GPIO0_7_Handler, /* 79 */ - GPIO0_8_Handler, /* 80 */ - GPIO0_9_Handler, /* 81 */ - GPIO0_10_Handler, /* 82 */ - GPIO0_11_Handler, /* 83 */ - GPIO0_12_Handler, /* 84 */ - GPIO0_13_Handler, /* 85 */ - GPIO0_14_Handler, /* 86 */ - GPIO0_15_Handler, /* 87 */ - GPIO1_0_Handler, /* 88 */ /* All P1 I/O pins used as irq source */ - GPIO1_1_Handler, /* 89 */ /* There are 16 pins in total */ - GPIO1_2_Handler, /* 90 */ - GPIO1_3_Handler, /* 91 */ - GPIO1_4_Handler, /* 92 */ - GPIO1_5_Handler, /* 93 */ - GPIO1_6_Handler, /* 94 */ - GPIO1_7_Handler, /* 95 */ - GPIO1_8_Handler, /* 96 */ - GPIO1_9_Handler, /* 97 */ - GPIO1_10_Handler, /* 98 */ - GPIO1_11_Handler, /* 99 */ - GPIO1_12_Handler, /* 100 */ - GPIO1_13_Handler, /* 101 */ - GPIO1_14_Handler, /* 102 */ - GPIO1_15_Handler, /* 103 */ - GPIO2_0_Handler, /* 104 */ /* All P2 I/O pins used as irq source */ - GPIO2_1_Handler, /* 105 */ /* There are 16 pins in total */ - GPIO2_2_Handler, /* 106 */ - GPIO2_3_Handler, /* 107 */ - GPIO2_4_Handler, /* 108 */ - GPIO2_5_Handler, /* 109 */ - GPIO2_6_Handler, /* 110 */ - GPIO2_7_Handler, /* 111 */ - GPIO2_8_Handler, /* 112 */ - GPIO2_9_Handler, /* 113 */ - GPIO2_10_Handler, /* 114 */ - GPIO2_11_Handler, /* 115 */ - GPIO2_12_Handler, /* 116 */ - GPIO2_13_Handler, /* 117 */ - GPIO2_14_Handler, /* 118 */ - GPIO2_15_Handler, /* 119 */ - GPIO3_0_Handler, /* 120 */ /* All P3 I/O pins used as irq source */ - GPIO3_1_Handler, /* 121 */ /* There are 4 pins in total */ - GPIO3_2_Handler, /* 122 */ - GPIO3_3_Handler, /* 123 */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined (IOTKit_CM23_VHT) - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c b/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c deleted file mode 100644 index b778da8..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c +++ /dev/null @@ -1,132 +0,0 @@ -/****************************************************************************** - * @file system_IOTKit_CM23.c - * @brief CMSIS Device System Source File for IOTKit_CM23 Device - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (IOTKit_CM23) || defined (IOTKit_CM23_VHT) - #include "IOTKit_CM23.h" -#else - #error device not specified! -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_IOTKit_CM23.h" -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -// uint32_t blk_cfg, blk_max, blk_size, blk_cnt; -#endif - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* start IOT Green configuration ------------------------- */ - - /* configure MPC --------------- */ - - /* configure unsecure code area MPSSSRAM1 (0x00200000 - 0x003FFFFF) */ -// blk_max = IOTKIT_MPCSSRAM1->BLK_MAX; /* = 0x1 */ -// blk_cfg = IOTKIT_MPCSSRAM1->BLK_CFG; /* = 0xC */ -// blk_size = 1UL << (blk_cfg + 5U); /* = 0x20000 */ -// blk_cnt = 0x200000U / blk_size; /* = 0x10 */ - - IOTKIT_MPCSSRAM1->CTRL &= ~(1UL << 8U); /* clear auto increment */ - IOTKIT_MPCSSRAM1->BLK_IDX = 0; /* write LUT index */ - IOTKIT_MPCSSRAM1->BLK_LUT = 0xFFFF0000UL; /* configure blocks */ - - - /* configure unsecure data area MPSSSRAM3 (0x28200000 - 0x283FFFFF) */ -// blk_max = IOTKIT_MPCSSRAM3->BLK_MAX; /* = 0x1 */ -// blk_cfg = IOTKIT_MPCSSRAM3->BLK_CFG; /* = 0xB */ -// blk_size = 1UL << (blk_cfg + 5U); /* = 0x10000 */ -// blk_cnt = 0x200000U / blk_size; /* = 0x20 */ - - IOTKIT_MPCSSRAM3->CTRL &= ~(1UL << 8U); /* clear auto increment */ - IOTKIT_MPCSSRAM3->BLK_IDX = 1; /* write LUT index */ - IOTKIT_MPCSSRAM3->BLK_LUT = 0xFFFFFFFFUL; /* configure blocks */ - - - - /* enable the Non Secure Callable Configuration for IDAU (NSCCFG register) */ - IOTKIT_SPC->NSCCFG |= 1U; - - - /* configure PPC --------------- */ -#if !defined (__USE_SECURE) - /* Allow Non-secure access for SCC/FPGAIO registers */ - IOTKIT_SPC->APBNSPPCEXP[2U] |= ((1UL << 0U) | - (1UL << 2U) ); - /* Allow Non-secure access for SPI1/UART0 registers */ - IOTKIT_SPC->APBNSPPCEXP[1U] |= ((1UL << 1U) | - (1UL << 5U) ); -#endif - -/* end IOT Green configuration --------------------------- */ - - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/Target.clayer.yml deleted file mode 100644 index 510c0a9..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_IOTKit_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2 IOT-Kit:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/vht_config.txt deleted file mode 100644 index 79f362c..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/vht_config.txt +++ /dev/null @@ -1,27 +0,0 @@ -## Parameters: -## instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -##------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -##------------------------------------------------------------------------------ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -cpu0.BE=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset -cpu0.INITVTORNS=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored -cpu0.SAU=4 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -cpu0.SYST=2 # (int , init-time) default = '0x2' : Include SysTick timer functionality (0=Absent, 1=Secure only, 2=Secure and NS) -cpu0.VTOR=1 # (bool , init-time) default = '1' : Include Vector Table Offset Register -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.platform_type=1 # (int , init-time) default = '0x0' : 0:Original MPS2 ; 1:IoT Kit (cut-down SSE-200) ; 2:Full SSE-200; 3:SVOS -idau.NUM_IDAU_REGION=0 # (int , init-time) default = '0x12' : -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld b/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld deleted file mode 100644 index 4dcf11b..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/gcc_arm.ld +++ /dev/null @@ -1,301 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ - -/* -; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x10000000; -__ROM_SIZE = 0x00400000; - -/*--------------------- Embedded RAM Configuration ---------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x38000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* -; -------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 8; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option �--section-start� or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - - LONG (__bss_start__) - LONG ((__bss_end__ - __bss_start__) / 4) - - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ - - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM - - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h b/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h deleted file mode 100644 index 46622d3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/partition_IOTKit_CM23.h +++ /dev/null @@ -1,585 +0,0 @@ -/****************************************************************************** - * @file partition_IOTKit_CM23.h - * @brief CMSIS-Core Initial Setup for Secure / Non-Secure Zones for IOTKit_CM23 - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef PARTITION_IOTKit_CM23_H -#define PARTITION_IOTKit_CM23_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 0 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x10000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x101FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x28200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x283FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x403FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 0 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 0 - -/* -// Interrupts 0..31 -// Non-Secure Watchdog Reset Request <0=> Secure state <1=> Non-Secure state -// Non-Secure Watchdog interrupt <0=> Secure state <1=> Non-Secure state -// S32K Timer interrupt <0=> Secure state <1=> Non-Secure state -// Timer 0 interrupt <0=> Secure state <1=> Non-Secure state -// Timer 1 interrupt <0=> Secure state <1=> Non-Secure state -// Dual Timer interrupt <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 0 - -/* -// Interrupts 32..63 -// UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 teceive interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 0, 1, 2, 3, 4 overflow interrupt <0=> Secure state <1=> Non-Secure state -// Ethernet interrupt <0=> Secure state <1=> Non-Secure state -// Audio I2S interrupt <0=> Secure state <1=> Non-Secure state -// Touch Screen interrupt <0=> Secure state <1=> Non-Secure state -// SPI 0 (SPI Header) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 1 (CLCD) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 2 (Shield ADC) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 3 (Shield 0 SPI) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 4 (Shield 1 SPI) interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 2 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 2 terminal count interrupt <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// DMA 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// GPIO 1 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_IOTKit_CM23_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c b/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c deleted file mode 100644 index 8fecd78..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/startup_IOTKit_CM23.c +++ /dev/null @@ -1,506 +0,0 @@ -/****************************************************************************** - * @file startup_IOTKit_CM23.c - * @brief CMSIS Startup File for IOTKit_CM23 Device - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (IOTKit_CM23) || defined (IOTKit_CM23_VHT) - #include "IOTKit_CM23.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Core IoT Interrupts */ -void NONSEC_WATCHDOG_RESET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void NONSEC_WATCHDOG_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void S32K_TIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BRIDGE_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* External Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UARTOVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* VSI Interrupts */ -#if defined (IOTKit_CM23_VHT) -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Core IoT Interrupts */ - NONSEC_WATCHDOG_RESET_Handler, /* 0 Non-Secure Watchdog Reset Handler */ - NONSEC_WATCHDOG_Handler, /* 1 Non-Secure Watchdog Handler */ - S32K_TIMER_Handler, /* 2 S32K Timer Handler */ - TIMER0_Handler, /* 3 TIMER 0 Handler */ - TIMER1_Handler, /* 4 TIMER 1 Handler */ - DUALTIMER_Handler, /* 5 Dual Timer Handler */ - 0, /* 6 Reserved */ - 0, /* 7 Reserved */ - 0, /* 8 Reserved */ - MPC_Handler, /* 9 MPC Combined (Secure) Handler */ - PPC_Handler, /* 10 PPC Combined (Secure) Handler */ - MSC_Handler, /* 11 MSC Combined (Secure) Handler */ - BRIDGE_ERROR_Handler, /* 12 Bridge Error Combined (Secure) Handler */ - 0, /* 13 Reserved */ - 0, /* 14 Reserved */ - 0, /* 15 Reserved */ - 0, /* 16 Reserved */ - 0, /* 17 Reserved */ - 0, /* 18 Reserved */ - 0, /* 19 Reserved */ - 0, /* 20 Reserved */ - 0, /* 21 Reserved */ - 0, /* 22 Reserved */ - 0, /* 23 Reserved */ - 0, /* 24 Reserved */ - 0, /* 25 Reserved */ - 0, /* 26 Reserved */ - 0, /* 27 Reserved */ - 0, /* 28 Reserved */ - 0, /* 29 Reserved */ - 0, /* 30 Reserved */ - 0, /* 31 Reserved */ - - /* External Interrupts */ - UART0RX_Handler, /* 32 UART 0 RX Handler */ - UART0TX_Handler, /* 33 UART 0 TX Handler */ - UART1RX_Handler, /* 34 UART 1 RX Handler */ - UART1TX_Handler, /* 35 UART 1 TX Handler */ - UART2RX_Handler, /* 36 UART 2 RX Handler */ - UART2TX_Handler, /* 37 UART 2 TX Handler */ - UART3RX_Handler, /* 38 UART 2 RX Handler */ - UART3TX_Handler, /* 39 UART 2 TX Handler */ - UART4RX_Handler, /* 40 UART 2 RX Handler */ - UART4TX_Handler, /* 41 UART 2 TX Handler */ - UART0_Handler, /* 42 UART 0 combined Handler */ - UART1_Handler, /* 43 UART 1 combined Handler */ - UART2_Handler, /* 44 UART 2 combined Handler */ - UART3_Handler, /* 45 UART 3 combined Handler */ - UART4_Handler, /* 46 UART 4 combined Handler */ - UARTOVF_Handler, /* 47 UART 0,1,2,3,4 Overflow Handler */ - ETHERNET_Handler , /* 48 Ethernet Handler */ - I2S_Handler, /* 49 I2S Handler */ - TSC_Handler, /* 50 Touch Screen Handler */ - SPI0_Handler, /* 51 SPI 0 Handler */ - SPI1_Handler, /* 52 SPI 1 Handler */ - SPI2_Handler, /* 53 SPI 2 Handler */ - SPI3_Handler, /* 54 SPI 3 Handler */ - SPI4_Handler, /* 55 SPI 4 Handler */ - DMA0_ERROR_Handler, /* 56 DMA 0 Error Handler */ - DMA0_TC_Handler, /* 57 DMA 0 Terminal Count Handler */ - DMA0_Handler, /* 58 DMA 0 Combined Handler */ - DMA1_ERROR_Handler, /* 59 DMA 1 Error Handler */ - DMA1_TC_Handler, /* 60 DMA 1 Terminal Count Handler */ - DMA1_Handler, /* 61 DMA 1 Combined Handler */ - DMA2_ERROR_Handler, /* 62 DMA 2 Error Handler */ - DMA2_TC_Handler, /* 63 DMA 2 Terminal Count Handler */ - DMA2_Handler, /* 64 DMA 2 Combined Handler */ - DMA3_ERROR_Handler, /* 65 DMA 3 Error Handler */ - DMA3_TC_Handler, /* 66 DMA 3 Terminal Count Handler */ - DMA3_Handler, /* 67 DMA 3 Combined Handler */ - GPIO0_Handler, /* 68 GPIO 0 Combined Handler */ - GPIO1_Handler, /* 69 GPIO 1 Combined Handler */ - GPIO2_Handler, /* 70 GPIO 2 Combined Handler */ - GPIO3_Handler, /* 71 GPIO 3 Combined Handler */ - GPIO0_0_Handler, /* 72 */ /* All P0 I/O pins used as irq source */ - GPIO0_1_Handler, /* 73 */ /* There are 16 pins in total */ - GPIO0_2_Handler, /* 74 */ - GPIO0_3_Handler, /* 75 */ - GPIO0_4_Handler, /* 76 */ - GPIO0_5_Handler, /* 77 */ - GPIO0_6_Handler, /* 78 */ - GPIO0_7_Handler, /* 79 */ - GPIO0_8_Handler, /* 80 */ - GPIO0_9_Handler, /* 81 */ - GPIO0_10_Handler, /* 82 */ - GPIO0_11_Handler, /* 83 */ - GPIO0_12_Handler, /* 84 */ - GPIO0_13_Handler, /* 85 */ - GPIO0_14_Handler, /* 86 */ - GPIO0_15_Handler, /* 87 */ - GPIO1_0_Handler, /* 88 */ /* All P1 I/O pins used as irq source */ - GPIO1_1_Handler, /* 89 */ /* There are 16 pins in total */ - GPIO1_2_Handler, /* 90 */ - GPIO1_3_Handler, /* 91 */ - GPIO1_4_Handler, /* 92 */ - GPIO1_5_Handler, /* 93 */ - GPIO1_6_Handler, /* 94 */ - GPIO1_7_Handler, /* 95 */ - GPIO1_8_Handler, /* 96 */ - GPIO1_9_Handler, /* 97 */ - GPIO1_10_Handler, /* 98 */ - GPIO1_11_Handler, /* 99 */ - GPIO1_12_Handler, /* 100 */ - GPIO1_13_Handler, /* 101 */ - GPIO1_14_Handler, /* 102 */ - GPIO1_15_Handler, /* 103 */ - GPIO2_0_Handler, /* 104 */ /* All P2 I/O pins used as irq source */ - GPIO2_1_Handler, /* 105 */ /* There are 16 pins in total */ - GPIO2_2_Handler, /* 106 */ - GPIO2_3_Handler, /* 107 */ - GPIO2_4_Handler, /* 108 */ - GPIO2_5_Handler, /* 109 */ - GPIO2_6_Handler, /* 110 */ - GPIO2_7_Handler, /* 111 */ - GPIO2_8_Handler, /* 112 */ - GPIO2_9_Handler, /* 113 */ - GPIO2_10_Handler, /* 114 */ - GPIO2_11_Handler, /* 115 */ - GPIO2_12_Handler, /* 116 */ - GPIO2_13_Handler, /* 117 */ - GPIO2_14_Handler, /* 118 */ - GPIO2_15_Handler, /* 119 */ - GPIO3_0_Handler, /* 120 */ /* All P3 I/O pins used as irq source */ - GPIO3_1_Handler, /* 121 */ /* There are 4 pins in total */ - GPIO3_2_Handler, /* 122 */ - GPIO3_3_Handler, /* 123 */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined (IOTKit_CM23_VHT) - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c b/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c deleted file mode 100644 index b778da8..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/RTE/Device/IOTKit_CM23_VHT/system_IOTKit_CM23.c +++ /dev/null @@ -1,132 +0,0 @@ -/****************************************************************************** - * @file system_IOTKit_CM23.c - * @brief CMSIS Device System Source File for IOTKit_CM23 Device - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (IOTKit_CM23) || defined (IOTKit_CM23_VHT) - #include "IOTKit_CM23.h" -#else - #error device not specified! -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_IOTKit_CM23.h" -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -// uint32_t blk_cfg, blk_max, blk_size, blk_cnt; -#endif - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* start IOT Green configuration ------------------------- */ - - /* configure MPC --------------- */ - - /* configure unsecure code area MPSSSRAM1 (0x00200000 - 0x003FFFFF) */ -// blk_max = IOTKIT_MPCSSRAM1->BLK_MAX; /* = 0x1 */ -// blk_cfg = IOTKIT_MPCSSRAM1->BLK_CFG; /* = 0xC */ -// blk_size = 1UL << (blk_cfg + 5U); /* = 0x20000 */ -// blk_cnt = 0x200000U / blk_size; /* = 0x10 */ - - IOTKIT_MPCSSRAM1->CTRL &= ~(1UL << 8U); /* clear auto increment */ - IOTKIT_MPCSSRAM1->BLK_IDX = 0; /* write LUT index */ - IOTKIT_MPCSSRAM1->BLK_LUT = 0xFFFF0000UL; /* configure blocks */ - - - /* configure unsecure data area MPSSSRAM3 (0x28200000 - 0x283FFFFF) */ -// blk_max = IOTKIT_MPCSSRAM3->BLK_MAX; /* = 0x1 */ -// blk_cfg = IOTKIT_MPCSSRAM3->BLK_CFG; /* = 0xB */ -// blk_size = 1UL << (blk_cfg + 5U); /* = 0x10000 */ -// blk_cnt = 0x200000U / blk_size; /* = 0x20 */ - - IOTKIT_MPCSSRAM3->CTRL &= ~(1UL << 8U); /* clear auto increment */ - IOTKIT_MPCSSRAM3->BLK_IDX = 1; /* write LUT index */ - IOTKIT_MPCSSRAM3->BLK_LUT = 0xFFFFFFFFUL; /* configure blocks */ - - - - /* enable the Non Secure Callable Configuration for IDAU (NSCCFG register) */ - IOTKIT_SPC->NSCCFG |= 1U; - - - /* configure PPC --------------- */ -#if !defined (__USE_SECURE) - /* Allow Non-secure access for SCC/FPGAIO registers */ - IOTKIT_SPC->APBNSPPCEXP[2U] |= ((1UL << 0U) | - (1UL << 2U) ); - /* Allow Non-secure access for SPI1/UART0 registers */ - IOTKIT_SPC->APBNSPPCEXP[1U] |= ((1UL << 1U) | - (1UL << 5U) ); -#endif - -/* end IOT Green configuration --------------------------- */ - - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/Target.clayer.yml deleted file mode 100644 index 510c0a9..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_IOTKit_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2 IOT-Kit:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/vht_config.txt deleted file mode 100644 index 79f362c..0000000 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_GCC/vht_config.txt +++ /dev/null @@ -1,27 +0,0 @@ -## Parameters: -## instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -##------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -##------------------------------------------------------------------------------ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -cpu0.BE=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.INITVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset -cpu0.INITVTORNS=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored -cpu0.SAU=4 # (int , init-time) default = '0x4' : Number of SAU regions (0 => no SAU) -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -cpu0.SYST=2 # (int , init-time) default = '0x2' : Include SysTick timer functionality (0=Absent, 1=Secure only, 2=Secure and NS) -cpu0.VTOR=1 # (bool , init-time) default = '1' : Include Vector Table Offset Register -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.platform_type=1 # (int , init-time) default = '0x0' : 0:Original MPS2 ; 1:IoT Kit (cut-down SSE-200) ; 2:Full SSE-200; 3:SVOS -idau.NUM_IDAU_REGION=0 # (int , init-time) default = '0x12' : -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h deleted file mode 100644 index 98585d3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h +++ /dev/null @@ -1,637 +0,0 @@ -/****************************************************************************** - * @file partition_IOTKit_CM33.h - * @brief CMSIS-Core Initial Setup for Secure / Non-Secure Zones for IOTKit_CM33 - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef PARTITION_IOTKit_CM33_H -#define PARTITION_IOTKit_CM33_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 0 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x10000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x101FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x28200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x283FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x403FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 0 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 0 - -/* -// Interrupts 0..31 -// Non-Secure Watchdog Reset Request <0=> Secure state <1=> Non-Secure state -// Non-Secure Watchdog interrupt <0=> Secure state <1=> Non-Secure state -// S32K Timer interrupt <0=> Secure state <1=> Non-Secure state -// Timer 0 interrupt <0=> Secure state <1=> Non-Secure state -// Timer 1 interrupt <0=> Secure state <1=> Non-Secure state -// Dual Timer interrupt <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 0 - -/* -// Interrupts 32..63 -// UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 teceive interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 0, 1, 2, 3, 4 overflow interrupt <0=> Secure state <1=> Non-Secure state -// Ethernet interrupt <0=> Secure state <1=> Non-Secure state -// Audio I2S interrupt <0=> Secure state <1=> Non-Secure state -// Touch Screen interrupt <0=> Secure state <1=> Non-Secure state -// SPI 0 (SPI Header) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 1 (CLCD) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 2 (Shield ADC) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 3 (Shield 0 SPI) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 4 (Shield 1 SPI) interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 2 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 2 terminal count interrupt <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// DMA 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// GPIO 1 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_IOTKit_CM33_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c deleted file mode 100644 index e06f735..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c +++ /dev/null @@ -1,513 +0,0 @@ -/****************************************************************************** - * @file startup_IOTKit_CM33.c - * @brief CMSIS Startup File for IOTKit_CM33 Device - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) - #include "IOTKit_CM33.h" -#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) - #include "IOTKit_CM33_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Core IoT Interrupts */ -void NONSEC_WATCHDOG_RESET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void NONSEC_WATCHDOG_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void S32K_TIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BRIDGE_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* External Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UARTOVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* VSI Interrupts */ -#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Core IoT Interrupts */ - NONSEC_WATCHDOG_RESET_Handler, /* 0 Non-Secure Watchdog Reset Handler */ - NONSEC_WATCHDOG_Handler, /* 1 Non-Secure Watchdog Handler */ - S32K_TIMER_Handler, /* 2 S32K Timer Handler */ - TIMER0_Handler, /* 3 TIMER 0 Handler */ - TIMER1_Handler, /* 4 TIMER 1 Handler */ - DUALTIMER_Handler, /* 5 Dual Timer Handler */ - 0, /* 6 Reserved */ - 0, /* 7 Reserved */ - 0, /* 8 Reserved */ - MPC_Handler, /* 9 MPC Combined (Secure) Handler */ - PPC_Handler, /* 10 PPC Combined (Secure) Handler */ - MSC_Handler, /* 11 MSC Combined (Secure) Handler */ - BRIDGE_ERROR_Handler, /* 12 Bridge Error Combined (Secure) Handler */ - 0, /* 13 Reserved */ - 0, /* 14 Reserved */ - 0, /* 15 Reserved */ - 0, /* 16 Reserved */ - 0, /* 17 Reserved */ - 0, /* 18 Reserved */ - 0, /* 19 Reserved */ - 0, /* 20 Reserved */ - 0, /* 21 Reserved */ - 0, /* 22 Reserved */ - 0, /* 23 Reserved */ - 0, /* 24 Reserved */ - 0, /* 25 Reserved */ - 0, /* 26 Reserved */ - 0, /* 27 Reserved */ - 0, /* 28 Reserved */ - 0, /* 29 Reserved */ - 0, /* 30 Reserved */ - 0, /* 31 Reserved */ - - /* External Interrupts */ - UART0RX_Handler, /* 32 UART 0 RX Handler */ - UART0TX_Handler, /* 33 UART 0 TX Handler */ - UART1RX_Handler, /* 34 UART 1 RX Handler */ - UART1TX_Handler, /* 35 UART 1 TX Handler */ - UART2RX_Handler, /* 36 UART 2 RX Handler */ - UART2TX_Handler, /* 37 UART 2 TX Handler */ - UART3RX_Handler, /* 38 UART 2 RX Handler */ - UART3TX_Handler, /* 39 UART 2 TX Handler */ - UART4RX_Handler, /* 40 UART 2 RX Handler */ - UART4TX_Handler, /* 41 UART 2 TX Handler */ - UART0_Handler, /* 42 UART 0 combined Handler */ - UART1_Handler, /* 43 UART 1 combined Handler */ - UART2_Handler, /* 44 UART 2 combined Handler */ - UART3_Handler, /* 45 UART 3 combined Handler */ - UART4_Handler, /* 46 UART 4 combined Handler */ - UARTOVF_Handler, /* 47 UART 0,1,2,3,4 Overflow Handler */ - ETHERNET_Handler , /* 48 Ethernet Handler */ - I2S_Handler, /* 49 I2S Handler */ - TSC_Handler, /* 50 Touch Screen Handler */ - SPI0_Handler, /* 51 SPI 0 Handler */ - SPI1_Handler, /* 52 SPI 1 Handler */ - SPI2_Handler, /* 53 SPI 2 Handler */ - SPI3_Handler, /* 54 SPI 3 Handler */ - SPI4_Handler, /* 55 SPI 4 Handler */ - DMA0_ERROR_Handler, /* 56 DMA 0 Error Handler */ - DMA0_TC_Handler, /* 57 DMA 0 Terminal Count Handler */ - DMA0_Handler, /* 58 DMA 0 Combined Handler */ - DMA1_ERROR_Handler, /* 59 DMA 1 Error Handler */ - DMA1_TC_Handler, /* 60 DMA 1 Terminal Count Handler */ - DMA1_Handler, /* 61 DMA 1 Combined Handler */ - DMA2_ERROR_Handler, /* 62 DMA 2 Error Handler */ - DMA2_TC_Handler, /* 63 DMA 2 Terminal Count Handler */ - DMA2_Handler, /* 64 DMA 2 Combined Handler */ - DMA3_ERROR_Handler, /* 65 DMA 3 Error Handler */ - DMA3_TC_Handler, /* 66 DMA 3 Terminal Count Handler */ - DMA3_Handler, /* 67 DMA 3 Combined Handler */ - GPIO0_Handler, /* 68 GPIO 0 Combined Handler */ - GPIO1_Handler, /* 69 GPIO 1 Combined Handler */ - GPIO2_Handler, /* 70 GPIO 2 Combined Handler */ - GPIO3_Handler, /* 71 GPIO 3 Combined Handler */ - GPIO0_0_Handler, /* 72 */ /* All P0 I/O pins used as irq source */ - GPIO0_1_Handler, /* 73 */ /* There are 16 pins in total */ - GPIO0_2_Handler, /* 74 */ - GPIO0_3_Handler, /* 75 */ - GPIO0_4_Handler, /* 76 */ - GPIO0_5_Handler, /* 77 */ - GPIO0_6_Handler, /* 78 */ - GPIO0_7_Handler, /* 79 */ - GPIO0_8_Handler, /* 80 */ - GPIO0_9_Handler, /* 81 */ - GPIO0_10_Handler, /* 82 */ - GPIO0_11_Handler, /* 83 */ - GPIO0_12_Handler, /* 84 */ - GPIO0_13_Handler, /* 85 */ - GPIO0_14_Handler, /* 86 */ - GPIO0_15_Handler, /* 87 */ - GPIO1_0_Handler, /* 88 */ /* All P1 I/O pins used as irq source */ - GPIO1_1_Handler, /* 89 */ /* There are 16 pins in total */ - GPIO1_2_Handler, /* 90 */ - GPIO1_3_Handler, /* 91 */ - GPIO1_4_Handler, /* 92 */ - GPIO1_5_Handler, /* 93 */ - GPIO1_6_Handler, /* 94 */ - GPIO1_7_Handler, /* 95 */ - GPIO1_8_Handler, /* 96 */ - GPIO1_9_Handler, /* 97 */ - GPIO1_10_Handler, /* 98 */ - GPIO1_11_Handler, /* 99 */ - GPIO1_12_Handler, /* 100 */ - GPIO1_13_Handler, /* 101 */ - GPIO1_14_Handler, /* 102 */ - GPIO1_15_Handler, /* 103 */ - GPIO2_0_Handler, /* 104 */ /* All P2 I/O pins used as irq source */ - GPIO2_1_Handler, /* 105 */ /* There are 16 pins in total */ - GPIO2_2_Handler, /* 106 */ - GPIO2_3_Handler, /* 107 */ - GPIO2_4_Handler, /* 108 */ - GPIO2_5_Handler, /* 109 */ - GPIO2_6_Handler, /* 110 */ - GPIO2_7_Handler, /* 111 */ - GPIO2_8_Handler, /* 112 */ - GPIO2_9_Handler, /* 113 */ - GPIO2_10_Handler, /* 114 */ - GPIO2_11_Handler, /* 115 */ - GPIO2_12_Handler, /* 116 */ - GPIO2_13_Handler, /* 117 */ - GPIO2_14_Handler, /* 118 */ - GPIO2_15_Handler, /* 119 */ - GPIO3_0_Handler, /* 120 */ /* All P3 I/O pins used as irq source */ - GPIO3_1_Handler, /* 121 */ /* There are 4 pins in total */ - GPIO3_2_Handler, /* 122 */ - GPIO3_3_Handler, /* 123 */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c deleted file mode 100644 index 3370379..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c +++ /dev/null @@ -1,149 +0,0 @@ -/****************************************************************************** - * @file system_IOTKit_CM33.c - * @brief CMSIS System Source File for IOTKit_CM33 Device - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) - #include "IOTKit_CM33.h" -#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) - #include "IOTKit_CM33_FP.h" -#else - #error device not specified! -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_IOTKit_CM33.h" -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -// uint32_t blk_cfg, blk_max, blk_size, blk_cnt; -#endif - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* start IOT Green configuration ------------------------- */ - - /* Enable BusFault, UsageFault, MemManageFault and SecureFault to ease diagnostic */ - SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | - SCB_SHCSR_BUSFAULTENA_Msk | - SCB_SHCSR_MEMFAULTENA_Msk | - SCB_SHCSR_SECUREFAULTENA_Msk); - - /* BFSR register setting to enable precise errors */ - SCB->CFSR |= SCB_CFSR_PRECISERR_Msk; - - - /* configure MPC --------------- */ - - /* configure unsecure code area MPSSSRAM1 (0x00200000 - 0x003FFFFF) */ -// blk_max = IOTKIT_MPCSSRAM1->BLK_MAX; /* = 0x1 */ -// blk_cfg = IOTKIT_MPCSSRAM1->BLK_CFG; /* = 0xC */ -// blk_size = 1UL << (blk_cfg + 5U); /* = 0x20000 */ -// blk_cnt = 0x200000U / blk_size; /* = 0x10 */ - - IOTKIT_MPCSSRAM1->CTRL &= ~(1UL << 8U); /* clear auto increment */ - IOTKIT_MPCSSRAM1->BLK_IDX = 0; /* write LUT index */ - IOTKIT_MPCSSRAM1->BLK_LUT = 0xFFFF0000UL; /* configure blocks */ - - - /* configure unsecure data area MPSSSRAM3 (0x28200000 - 0x283FFFFF) */ -// blk_max = IOTKIT_MPCSSRAM3->BLK_MAX; /* = 0x1 */ -// blk_cfg = IOTKIT_MPCSSRAM3->BLK_CFG; /* = 0xB */ -// blk_size = 1UL << (blk_cfg + 5U); /* = 0x10000 */ -// blk_cnt = 0x200000U / blk_size; /* = 0x20 */ - - IOTKIT_MPCSSRAM3->CTRL &= ~(1UL << 8U); /* clear auto increment */ - IOTKIT_MPCSSRAM3->BLK_IDX = 1; /* write LUT index */ - IOTKIT_MPCSSRAM3->BLK_LUT = 0xFFFFFFFFUL; /* configure blocks */ - - - - /* enable the Non Secure Callable Configuration for IDAU (NSCCFG register) */ - IOTKIT_SPC->NSCCFG |= 1U; - - - /* configure PPC --------------- */ -#if !defined (__USE_SECURE) - /* Allow Non-secure access for SCC/FPGAIO registers */ - IOTKIT_SPC->APBNSPPCEXP[2U] |= ((1UL << 0U) | - (1UL << 2U) ); - /* Allow Non-secure access for SPI1/UART0 registers */ - IOTKIT_SPC->APBNSPPCEXP[1U] |= ((1UL << 1U) | - (1UL << 5U) ); -#endif - -/* end IOT Green configuration --------------------------- */ - - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/Target.clayer.yml deleted file mode 100644 index 510c0a9..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_IOTKit_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2 IOT-Kit:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/vht_config.txt deleted file mode 100644 index 8c9da53..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/vht_config.txt +++ /dev/null @@ -1,33 +0,0 @@ -## Parameters: -## instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -##------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -##------------------------------------------------------------------------------ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset -cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored -cpu0.SAU=0x8 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.platform_type=1 # (int , init-time) default = '0x0' : 0:Original MPS2 ; 1:IoT Kit (cut-down SSE-200) ; 2:Full SSE-200; 3:SVOS -idau.NUM_IDAU_REGION=0 # (int , init-time) default = '0x12' : -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld deleted file mode 100644 index 5f3fdf2..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/gcc_arm.ld +++ /dev/null @@ -1,299 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ - -/* -; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x10000000; -__ROM_SIZE = 0x00400000; - -/*--------------------- Embedded RAM Configuration ---------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x38000000; -__RAM_SIZE = 0x00200000; - -/*--------------------- Stack / Heap Configuration ---------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* -; -------------------- <<< end of configuration section >>> ------------------- - */ - -/* ARMv8-M stack sealing: - to use ARMv8-M stack sealing set __STACKSEAL_SIZE to 8 otherwise keep 0 - */ -__STACKSEAL_SIZE = 0; - - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __StackSeal (only if ARMv8-M stack sealing is used) - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option �--section-start� or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG ((__bss_end__ - __bss_start__) / 4) - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h deleted file mode 100644 index 98585d3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/partition_IOTKit_CM33.h +++ /dev/null @@ -1,637 +0,0 @@ -/****************************************************************************** - * @file partition_IOTKit_CM33.h - * @brief CMSIS-Core Initial Setup for Secure / Non-Secure Zones for IOTKit_CM33 - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef PARTITION_IOTKit_CM33_H -#define PARTITION_IOTKit_CM33_H - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Initialize Security Attribution Unit (SAU) CTRL register -*/ -#define SAU_INIT_CTRL 0 - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x10000000 /* start address of SAU region 0 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x101FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x00200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x003FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x28200000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x283FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 0 -/* -// -*/ - -/* -// Initialize SAU Region 3 -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x40000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x403FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 0 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point Unit -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 0 - -/* -// Interrupts 0..31 -// Non-Secure Watchdog Reset Request <0=> Secure state <1=> Non-Secure state -// Non-Secure Watchdog interrupt <0=> Secure state <1=> Non-Secure state -// S32K Timer interrupt <0=> Secure state <1=> Non-Secure state -// Timer 0 interrupt <0=> Secure state <1=> Non-Secure state -// Timer 1 interrupt <0=> Secure state <1=> Non-Secure state -// Dual Timer interrupt <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 0 - -/* -// Interrupts 32..63 -// UART 0 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 0 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 teceive interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 receive interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 transmit interrupt <0=> Secure state <1=> Non-Secure state -// UART 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 4 combined interrupt <0=> Secure state <1=> Non-Secure state -// UART 0, 1, 2, 3, 4 overflow interrupt <0=> Secure state <1=> Non-Secure state -// Ethernet interrupt <0=> Secure state <1=> Non-Secure state -// Audio I2S interrupt <0=> Secure state <1=> Non-Secure state -// Touch Screen interrupt <0=> Secure state <1=> Non-Secure state -// SPI 0 (SPI Header) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 1 (CLCD) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 2 (Shield ADC) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 3 (Shield 0 SPI) interrupt <0=> Secure state <1=> Non-Secure state -// SPI 4 (Shield 1 SPI) interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 2 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 2 terminal count interrupt <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// DMA 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 error interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 terminal count interrupt <0=> Secure state <1=> Non-Secure state -// DMA 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 0 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 1 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 2 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 3 combined interrupt <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 0 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// GPIO 1 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 1 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 4) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 5) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 6) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 7) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 8) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt ( 9) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (10) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (11) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (12) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (13) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (14) <0=> Secure state <1=> Non-Secure state -// GPIO 2 individual interrupt (15) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 0) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 1) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 2) <0=> Secure state <1=> Non-Secure state -// GPIO 3 individual interrupt ( 3) <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ - defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP10_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif /* PARTITION_IOTKit_CM33_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c deleted file mode 100644 index e06f735..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/startup_IOTKit_CM33.c +++ /dev/null @@ -1,513 +0,0 @@ -/****************************************************************************** - * @file startup_IOTKit_CM33.c - * @brief CMSIS Startup File for IOTKit_CM33 Device - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) - #include "IOTKit_CM33.h" -#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) - #include "IOTKit_CM33_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -extern uint32_t __STACK_SEAL; -#endif - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Core IoT Interrupts */ -void NONSEC_WATCHDOG_RESET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void NONSEC_WATCHDOG_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void S32K_TIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PPC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void MSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BRIDGE_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* External Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UARTOVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TSC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_ERROR_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_TC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DMA3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_10_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_11_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_12_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_13_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_14_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_15_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* VSI Interrupts */ -#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - SecureFault_Handler, /* -9 Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Core IoT Interrupts */ - NONSEC_WATCHDOG_RESET_Handler, /* 0 Non-Secure Watchdog Reset Handler */ - NONSEC_WATCHDOG_Handler, /* 1 Non-Secure Watchdog Handler */ - S32K_TIMER_Handler, /* 2 S32K Timer Handler */ - TIMER0_Handler, /* 3 TIMER 0 Handler */ - TIMER1_Handler, /* 4 TIMER 1 Handler */ - DUALTIMER_Handler, /* 5 Dual Timer Handler */ - 0, /* 6 Reserved */ - 0, /* 7 Reserved */ - 0, /* 8 Reserved */ - MPC_Handler, /* 9 MPC Combined (Secure) Handler */ - PPC_Handler, /* 10 PPC Combined (Secure) Handler */ - MSC_Handler, /* 11 MSC Combined (Secure) Handler */ - BRIDGE_ERROR_Handler, /* 12 Bridge Error Combined (Secure) Handler */ - 0, /* 13 Reserved */ - 0, /* 14 Reserved */ - 0, /* 15 Reserved */ - 0, /* 16 Reserved */ - 0, /* 17 Reserved */ - 0, /* 18 Reserved */ - 0, /* 19 Reserved */ - 0, /* 20 Reserved */ - 0, /* 21 Reserved */ - 0, /* 22 Reserved */ - 0, /* 23 Reserved */ - 0, /* 24 Reserved */ - 0, /* 25 Reserved */ - 0, /* 26 Reserved */ - 0, /* 27 Reserved */ - 0, /* 28 Reserved */ - 0, /* 29 Reserved */ - 0, /* 30 Reserved */ - 0, /* 31 Reserved */ - - /* External Interrupts */ - UART0RX_Handler, /* 32 UART 0 RX Handler */ - UART0TX_Handler, /* 33 UART 0 TX Handler */ - UART1RX_Handler, /* 34 UART 1 RX Handler */ - UART1TX_Handler, /* 35 UART 1 TX Handler */ - UART2RX_Handler, /* 36 UART 2 RX Handler */ - UART2TX_Handler, /* 37 UART 2 TX Handler */ - UART3RX_Handler, /* 38 UART 2 RX Handler */ - UART3TX_Handler, /* 39 UART 2 TX Handler */ - UART4RX_Handler, /* 40 UART 2 RX Handler */ - UART4TX_Handler, /* 41 UART 2 TX Handler */ - UART0_Handler, /* 42 UART 0 combined Handler */ - UART1_Handler, /* 43 UART 1 combined Handler */ - UART2_Handler, /* 44 UART 2 combined Handler */ - UART3_Handler, /* 45 UART 3 combined Handler */ - UART4_Handler, /* 46 UART 4 combined Handler */ - UARTOVF_Handler, /* 47 UART 0,1,2,3,4 Overflow Handler */ - ETHERNET_Handler , /* 48 Ethernet Handler */ - I2S_Handler, /* 49 I2S Handler */ - TSC_Handler, /* 50 Touch Screen Handler */ - SPI0_Handler, /* 51 SPI 0 Handler */ - SPI1_Handler, /* 52 SPI 1 Handler */ - SPI2_Handler, /* 53 SPI 2 Handler */ - SPI3_Handler, /* 54 SPI 3 Handler */ - SPI4_Handler, /* 55 SPI 4 Handler */ - DMA0_ERROR_Handler, /* 56 DMA 0 Error Handler */ - DMA0_TC_Handler, /* 57 DMA 0 Terminal Count Handler */ - DMA0_Handler, /* 58 DMA 0 Combined Handler */ - DMA1_ERROR_Handler, /* 59 DMA 1 Error Handler */ - DMA1_TC_Handler, /* 60 DMA 1 Terminal Count Handler */ - DMA1_Handler, /* 61 DMA 1 Combined Handler */ - DMA2_ERROR_Handler, /* 62 DMA 2 Error Handler */ - DMA2_TC_Handler, /* 63 DMA 2 Terminal Count Handler */ - DMA2_Handler, /* 64 DMA 2 Combined Handler */ - DMA3_ERROR_Handler, /* 65 DMA 3 Error Handler */ - DMA3_TC_Handler, /* 66 DMA 3 Terminal Count Handler */ - DMA3_Handler, /* 67 DMA 3 Combined Handler */ - GPIO0_Handler, /* 68 GPIO 0 Combined Handler */ - GPIO1_Handler, /* 69 GPIO 1 Combined Handler */ - GPIO2_Handler, /* 70 GPIO 2 Combined Handler */ - GPIO3_Handler, /* 71 GPIO 3 Combined Handler */ - GPIO0_0_Handler, /* 72 */ /* All P0 I/O pins used as irq source */ - GPIO0_1_Handler, /* 73 */ /* There are 16 pins in total */ - GPIO0_2_Handler, /* 74 */ - GPIO0_3_Handler, /* 75 */ - GPIO0_4_Handler, /* 76 */ - GPIO0_5_Handler, /* 77 */ - GPIO0_6_Handler, /* 78 */ - GPIO0_7_Handler, /* 79 */ - GPIO0_8_Handler, /* 80 */ - GPIO0_9_Handler, /* 81 */ - GPIO0_10_Handler, /* 82 */ - GPIO0_11_Handler, /* 83 */ - GPIO0_12_Handler, /* 84 */ - GPIO0_13_Handler, /* 85 */ - GPIO0_14_Handler, /* 86 */ - GPIO0_15_Handler, /* 87 */ - GPIO1_0_Handler, /* 88 */ /* All P1 I/O pins used as irq source */ - GPIO1_1_Handler, /* 89 */ /* There are 16 pins in total */ - GPIO1_2_Handler, /* 90 */ - GPIO1_3_Handler, /* 91 */ - GPIO1_4_Handler, /* 92 */ - GPIO1_5_Handler, /* 93 */ - GPIO1_6_Handler, /* 94 */ - GPIO1_7_Handler, /* 95 */ - GPIO1_8_Handler, /* 96 */ - GPIO1_9_Handler, /* 97 */ - GPIO1_10_Handler, /* 98 */ - GPIO1_11_Handler, /* 99 */ - GPIO1_12_Handler, /* 100 */ - GPIO1_13_Handler, /* 101 */ - GPIO1_14_Handler, /* 102 */ - GPIO1_15_Handler, /* 103 */ - GPIO2_0_Handler, /* 104 */ /* All P2 I/O pins used as irq source */ - GPIO2_1_Handler, /* 105 */ /* There are 16 pins in total */ - GPIO2_2_Handler, /* 106 */ - GPIO2_3_Handler, /* 107 */ - GPIO2_4_Handler, /* 108 */ - GPIO2_5_Handler, /* 109 */ - GPIO2_6_Handler, /* 110 */ - GPIO2_7_Handler, /* 111 */ - GPIO2_8_Handler, /* 112 */ - GPIO2_9_Handler, /* 113 */ - GPIO2_10_Handler, /* 114 */ - GPIO2_11_Handler, /* 115 */ - GPIO2_12_Handler, /* 116 */ - GPIO2_13_Handler, /* 117 */ - GPIO2_14_Handler, /* 118 */ - GPIO2_15_Handler, /* 119 */ - GPIO3_0_Handler, /* 120 */ /* All P3 I/O pins used as irq source */ - GPIO3_1_Handler, /* 121 */ /* There are 4 pins in total */ - GPIO3_2_Handler, /* 122 */ - GPIO3_3_Handler, /* 123 */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined (IOTKit_CM33_VHT) || defined (IOTKit_CM33_FP_VHT) - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - __set_PSP((uint32_t)(&__INITIAL_SP)); - - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); -#endif - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c deleted file mode 100644 index 3370379..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/RTE/Device/IOTKit_CM33_FP_VHT/system_IOTKit_CM33.c +++ /dev/null @@ -1,149 +0,0 @@ -/****************************************************************************** - * @file system_IOTKit_CM33.c - * @brief CMSIS System Source File for IOTKit_CM33 Device - ******************************************************************************/ -/* Copyright (c) 2015 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (IOTKit_CM33) || defined (IOTKit_CM33_VHT) - #include "IOTKit_CM33.h" -#elif defined (IOTKit_CM33_FP) || defined (IOTKit_CM33_FP_VHT) - #include "IOTKit_CM33_FP.h" -#else - #error device not specified! -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #include "partition_IOTKit_CM33.h" -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -// uint32_t blk_cfg, blk_max, blk_size, blk_cnt; -#endif - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* start IOT Green configuration ------------------------- */ - - /* Enable BusFault, UsageFault, MemManageFault and SecureFault to ease diagnostic */ - SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | - SCB_SHCSR_BUSFAULTENA_Msk | - SCB_SHCSR_MEMFAULTENA_Msk | - SCB_SHCSR_SECUREFAULTENA_Msk); - - /* BFSR register setting to enable precise errors */ - SCB->CFSR |= SCB_CFSR_PRECISERR_Msk; - - - /* configure MPC --------------- */ - - /* configure unsecure code area MPSSSRAM1 (0x00200000 - 0x003FFFFF) */ -// blk_max = IOTKIT_MPCSSRAM1->BLK_MAX; /* = 0x1 */ -// blk_cfg = IOTKIT_MPCSSRAM1->BLK_CFG; /* = 0xC */ -// blk_size = 1UL << (blk_cfg + 5U); /* = 0x20000 */ -// blk_cnt = 0x200000U / blk_size; /* = 0x10 */ - - IOTKIT_MPCSSRAM1->CTRL &= ~(1UL << 8U); /* clear auto increment */ - IOTKIT_MPCSSRAM1->BLK_IDX = 0; /* write LUT index */ - IOTKIT_MPCSSRAM1->BLK_LUT = 0xFFFF0000UL; /* configure blocks */ - - - /* configure unsecure data area MPSSSRAM3 (0x28200000 - 0x283FFFFF) */ -// blk_max = IOTKIT_MPCSSRAM3->BLK_MAX; /* = 0x1 */ -// blk_cfg = IOTKIT_MPCSSRAM3->BLK_CFG; /* = 0xB */ -// blk_size = 1UL << (blk_cfg + 5U); /* = 0x10000 */ -// blk_cnt = 0x200000U / blk_size; /* = 0x20 */ - - IOTKIT_MPCSSRAM3->CTRL &= ~(1UL << 8U); /* clear auto increment */ - IOTKIT_MPCSSRAM3->BLK_IDX = 1; /* write LUT index */ - IOTKIT_MPCSSRAM3->BLK_LUT = 0xFFFFFFFFUL; /* configure blocks */ - - - - /* enable the Non Secure Callable Configuration for IDAU (NSCCFG register) */ - IOTKIT_SPC->NSCCFG |= 1U; - - - /* configure PPC --------------- */ -#if !defined (__USE_SECURE) - /* Allow Non-secure access for SCC/FPGAIO registers */ - IOTKIT_SPC->APBNSPPCEXP[2U] |= ((1UL << 0U) | - (1UL << 2U) ); - /* Allow Non-secure access for SPI1/UART0 registers */ - IOTKIT_SPC->APBNSPPCEXP[1U] |= ((1UL << 1U) | - (1UL << 5U) ); -#endif - -/* end IOT Green configuration --------------------------- */ - - TZ_SAU_Setup(); -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/Target.clayer.yml deleted file mode 100644 index 1701481..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil.:V2M-MPS2_IOTKit_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2 IOT-Kit:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/vht_config.txt deleted file mode 100644 index 8c9da53..0000000 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_GCC/vht_config.txt +++ /dev/null @@ -1,33 +0,0 @@ -## Parameters: -## instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -##------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -##------------------------------------------------------------------------------ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -cpu0.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.DSP=1 # (bool , init-time) default = '1' : Set whether the model has the DSP extension -cpu0.FPU=1 # (bool , init-time) default = '1' : Set whether the model has VFP support -cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset -cpu0.INITSVTOR=0 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset -cpu0.IRQLVL=0x3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority -cpu0.ITM=0 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.MPU_NS=0x8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions -cpu0.MPU_S=0x8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored -cpu0.SAU=0x8 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) -cpu0.SAU_CTRL.ALLNS=0 # (bool , init-time) default = '0' : At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set -cpu0.SAU_CTRL.ENABLE=0 # (bool , init-time) default = '0' : Enable SAU at reset -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -cpu0.semihosting-enable=0 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -fvp_mps2.platform_type=1 # (int , init-time) default = '0x0' : 0:Original MPS2 ; 1:IoT Kit (cut-down SSE-200) ; 2:Full SSE-200; 3:SVOS -idau.NUM_IDAU_REGION=0 # (int , init-time) default = '0x12' : -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct b/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct deleted file mode 100644 index dda75e3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/ac6_arm.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c b/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c deleted file mode 100644 index a0753d0..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c +++ /dev/null @@ -1,421 +0,0 @@ -/****************************************************************************** - * @file startup_CMSDK_CM3.c - * @brief CMSIS Startup File for CMSDK_M3 Device - ******************************************************************************/ -/* Copyright (c) 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM3) || defined (CMSDK_CM3_VHT) - #include "CMSDK_CM3.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#if defined CMSDK_CM3_VHT -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - UART0RX_Handler, /* 0 UART 0 receive interrupt */ - UART0TX_Handler, /* 1 UART 0 transmit interrupt */ - UART1RX_Handler, /* 2 UART 1 receive interrupt */ - UART1TX_Handler, /* 3 UART 1 transmit interrupt */ - UART2RX_Handler, /* 4 UART 2 receive interrupt */ - UART2TX_Handler, /* 5 UART 2 transmit interrupt */ - GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ - GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ - TIMER0_Handler, /* 8 Timer 0 interrupt */ - TIMER1_Handler, /* 9 Timer 1 interrupt */ - DUALTIMER_Handler, /* 10 Dual Timer interrupt */ - SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ - UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ - ETHERNET_Handler, /* 13 Ethernet interrupt */ - I2S_Handler, /* 14 Audio I2S interrupt */ - TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ - GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ - GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ - UART3RX_Handler, /* 18 UART 3 receive interrupt */ - UART3TX_Handler, /* 19 UART 3 transmit interrupt */ - UART4RX_Handler, /* 20 UART 4 receive interrupt */ - UART4TX_Handler, /* 21 UART 4 transmit interrupt */ - SPI_2_Handler, /* 22 SPI 2 interrupt */ - SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ - GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ - GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ - GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ - GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ - GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ - GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ - GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ - GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ - 0, /* 32 Reserved */ - 0, /* 33 Reserved */ - 0, /* 34 Reserved */ - 0, /* 35 Reserved */ - 0, /* 36 Reserved */ - 0, /* 37 Reserved */ - 0, /* 38 Reserved */ - 0, /* 39 Reserved */ - 0, /* 40 Reserved */ - 0, /* 41 Reserved */ - 0, /* 42 Reserved */ - 0, /* 43 Reserved */ - 0, /* 44 Reserved */ - 0, /* 45 Reserved */ - 0, /* 46 Reserved */ - 0, /* 47 Reserved */ - 0, /* 48 Reserved */ - 0, /* 49 Reserved */ - 0, /* 50 Reserved */ - 0, /* 51 Reserved */ - 0, /* 52 Reserved */ - 0, /* 53 Reserved */ - 0, /* 54 Reserved */ - 0, /* 55 Reserved */ - 0, /* 56 Reserved */ - 0, /* 57 Reserved */ - 0, /* 58 Reserved */ - 0, /* 59 Reserved */ - 0, /* 60 Reserved */ - 0, /* 61 Reserved */ - 0, /* 62 Reserved */ - 0, /* 63 Reserved */ - 0, /* 64 Reserved */ - 0, /* 65 Reserved */ - 0, /* 66 Reserved */ - 0, /* 67 Reserved */ - 0, /* 68 Reserved */ - 0, /* 69 Reserved */ - 0, /* 70 Reserved */ - 0, /* 71 Reserved */ - 0, /* 72 Reserved */ - 0, /* 73 Reserved */ - 0, /* 74 Reserved */ - 0, /* 75 Reserved */ - 0, /* 76 Reserved */ - 0, /* 77 Reserved */ - 0, /* 78 Reserved */ - 0, /* 79 Reserved */ - 0, /* 80 Reserved */ - 0, /* 81 Reserved */ - 0, /* 82 Reserved */ - 0, /* 83 Reserved */ - 0, /* 84 Reserved */ - 0, /* 85 Reserved */ - 0, /* 86 Reserved */ - 0, /* 87 Reserved */ - 0, /* 88 Reserved */ - 0, /* 89 Reserved */ - 0, /* 90 Reserved */ - 0, /* 91 Reserved */ - 0, /* 92 Reserved */ - 0, /* 93 Reserved */ - 0, /* 94 Reserved */ - 0, /* 95 Reserved */ - 0, /* 96 Reserved */ - 0, /* 97 Reserved */ - 0, /* 98 Reserved */ - 0, /* 99 Reserved */ - 0, /* 100 Reserved */ - 0, /* 101 Reserved */ - 0, /* 102 Reserved */ - 0, /* 103 Reserved */ - 0, /* 104 Reserved */ - 0, /* 105 Reserved */ - 0, /* 106 Reserved */ - 0, /* 107 Reserved */ - 0, /* 108 Reserved */ - 0, /* 109 Reserved */ - 0, /* 110 Reserved */ - 0, /* 111 Reserved */ - 0, /* 112 Reserved */ - 0, /* 113 Reserved */ - 0, /* 114 Reserved */ - 0, /* 115 Reserved */ - 0, /* 116 Reserved */ - 0, /* 117 Reserved */ - 0, /* 118 Reserved */ - 0, /* 119 Reserved */ - 0, /* 120 Reserved */ - 0, /* 121 Reserved */ - 0, /* 122 Reserved */ - 0, /* 123 Reserved */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined CMSDK_CM3_VHT - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c b/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c deleted file mode 100644 index d83b399..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c +++ /dev/null @@ -1,78 +0,0 @@ -/****************************************************************************** - * @file system_CMSDK_CM3.c - * @brief CMSIS System Source File for CMSDK_M3 Device - ******************************************************************************/ -/* Copyright (c) 2011 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM3) || defined (CMSDK_CM3_VHT) - #include "CMSDK_CM3.h" -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/Target.clayer.yml deleted file mode 100644 index 8e3ec74..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_CMx_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/vht_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_AC6/vht_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld b/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld deleted file mode 100644 index 59bd7d1..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/gcc_arm.ld +++ /dev/null @@ -1,279 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ - -/* -; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00400000; - -/*--------------------- Embedded RAM Configuration ---------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* -; -------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option �--section-start� or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG ((__bss_end__ - __bss_start__) / 4) - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c b/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c deleted file mode 100644 index a0753d0..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/startup_CMSDK_CM3.c +++ /dev/null @@ -1,421 +0,0 @@ -/****************************************************************************** - * @file startup_CMSDK_CM3.c - * @brief CMSIS Startup File for CMSDK_M3 Device - ******************************************************************************/ -/* Copyright (c) 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM3) || defined (CMSDK_CM3_VHT) - #include "CMSDK_CM3.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#if defined CMSDK_CM3_VHT -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - UART0RX_Handler, /* 0 UART 0 receive interrupt */ - UART0TX_Handler, /* 1 UART 0 transmit interrupt */ - UART1RX_Handler, /* 2 UART 1 receive interrupt */ - UART1TX_Handler, /* 3 UART 1 transmit interrupt */ - UART2RX_Handler, /* 4 UART 2 receive interrupt */ - UART2TX_Handler, /* 5 UART 2 transmit interrupt */ - GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ - GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ - TIMER0_Handler, /* 8 Timer 0 interrupt */ - TIMER1_Handler, /* 9 Timer 1 interrupt */ - DUALTIMER_Handler, /* 10 Dual Timer interrupt */ - SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ - UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ - ETHERNET_Handler, /* 13 Ethernet interrupt */ - I2S_Handler, /* 14 Audio I2S interrupt */ - TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ - GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ - GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ - UART3RX_Handler, /* 18 UART 3 receive interrupt */ - UART3TX_Handler, /* 19 UART 3 transmit interrupt */ - UART4RX_Handler, /* 20 UART 4 receive interrupt */ - UART4TX_Handler, /* 21 UART 4 transmit interrupt */ - SPI_2_Handler, /* 22 SPI 2 interrupt */ - SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ - GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ - GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ - GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ - GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ - GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ - GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ - GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ - GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ - 0, /* 32 Reserved */ - 0, /* 33 Reserved */ - 0, /* 34 Reserved */ - 0, /* 35 Reserved */ - 0, /* 36 Reserved */ - 0, /* 37 Reserved */ - 0, /* 38 Reserved */ - 0, /* 39 Reserved */ - 0, /* 40 Reserved */ - 0, /* 41 Reserved */ - 0, /* 42 Reserved */ - 0, /* 43 Reserved */ - 0, /* 44 Reserved */ - 0, /* 45 Reserved */ - 0, /* 46 Reserved */ - 0, /* 47 Reserved */ - 0, /* 48 Reserved */ - 0, /* 49 Reserved */ - 0, /* 50 Reserved */ - 0, /* 51 Reserved */ - 0, /* 52 Reserved */ - 0, /* 53 Reserved */ - 0, /* 54 Reserved */ - 0, /* 55 Reserved */ - 0, /* 56 Reserved */ - 0, /* 57 Reserved */ - 0, /* 58 Reserved */ - 0, /* 59 Reserved */ - 0, /* 60 Reserved */ - 0, /* 61 Reserved */ - 0, /* 62 Reserved */ - 0, /* 63 Reserved */ - 0, /* 64 Reserved */ - 0, /* 65 Reserved */ - 0, /* 66 Reserved */ - 0, /* 67 Reserved */ - 0, /* 68 Reserved */ - 0, /* 69 Reserved */ - 0, /* 70 Reserved */ - 0, /* 71 Reserved */ - 0, /* 72 Reserved */ - 0, /* 73 Reserved */ - 0, /* 74 Reserved */ - 0, /* 75 Reserved */ - 0, /* 76 Reserved */ - 0, /* 77 Reserved */ - 0, /* 78 Reserved */ - 0, /* 79 Reserved */ - 0, /* 80 Reserved */ - 0, /* 81 Reserved */ - 0, /* 82 Reserved */ - 0, /* 83 Reserved */ - 0, /* 84 Reserved */ - 0, /* 85 Reserved */ - 0, /* 86 Reserved */ - 0, /* 87 Reserved */ - 0, /* 88 Reserved */ - 0, /* 89 Reserved */ - 0, /* 90 Reserved */ - 0, /* 91 Reserved */ - 0, /* 92 Reserved */ - 0, /* 93 Reserved */ - 0, /* 94 Reserved */ - 0, /* 95 Reserved */ - 0, /* 96 Reserved */ - 0, /* 97 Reserved */ - 0, /* 98 Reserved */ - 0, /* 99 Reserved */ - 0, /* 100 Reserved */ - 0, /* 101 Reserved */ - 0, /* 102 Reserved */ - 0, /* 103 Reserved */ - 0, /* 104 Reserved */ - 0, /* 105 Reserved */ - 0, /* 106 Reserved */ - 0, /* 107 Reserved */ - 0, /* 108 Reserved */ - 0, /* 109 Reserved */ - 0, /* 110 Reserved */ - 0, /* 111 Reserved */ - 0, /* 112 Reserved */ - 0, /* 113 Reserved */ - 0, /* 114 Reserved */ - 0, /* 115 Reserved */ - 0, /* 116 Reserved */ - 0, /* 117 Reserved */ - 0, /* 118 Reserved */ - 0, /* 119 Reserved */ - 0, /* 120 Reserved */ - 0, /* 121 Reserved */ - 0, /* 122 Reserved */ - 0, /* 123 Reserved */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined CMSDK_CM3_VHT - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c b/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c deleted file mode 100644 index d83b399..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/RTE/Device/CMSDK_CM3_VHT/system_CMSDK_CM3.c +++ /dev/null @@ -1,78 +0,0 @@ -/****************************************************************************** - * @file system_CMSDK_CM3.c - * @brief CMSIS System Source File for CMSDK_M3 Device - ******************************************************************************/ -/* Copyright (c) 2011 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM3) || defined (CMSDK_CM3_VHT) - #include "CMSDK_CM3.h" -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/Target.clayer.yml deleted file mode 100644 index 8e3ec74..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_CMx_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/vht_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM3_VHT_GCC/vht_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct deleted file mode 100644 index 991e4e3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/ac6_arm.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c deleted file mode 100644 index 08b2426..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c +++ /dev/null @@ -1,423 +0,0 @@ -/****************************************************************************** - * @file startup_CMSDK_CM4.c - * @brief CMSIS Startup File for CMSDK_M4 Device - ******************************************************************************/ -/* Copyright (c) 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) - #include "CMSDK_CM4.h" -#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) - #include "CMSDK_CM4_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - UART0RX_Handler, /* 0 UART 0 receive interrupt */ - UART0TX_Handler, /* 1 UART 0 transmit interrupt */ - UART1RX_Handler, /* 2 UART 1 receive interrupt */ - UART1TX_Handler, /* 3 UART 1 transmit interrupt */ - UART2RX_Handler, /* 4 UART 2 receive interrupt */ - UART2TX_Handler, /* 5 UART 2 transmit interrupt */ - GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ - GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ - TIMER0_Handler, /* 8 Timer 0 interrupt */ - TIMER1_Handler, /* 9 Timer 1 interrupt */ - DUALTIMER_Handler, /* 10 Dual Timer interrupt */ - SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ - UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ - ETHERNET_Handler, /* 13 Ethernet interrupt */ - I2S_Handler, /* 14 Audio I2S interrupt */ - TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ - GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ - GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ - UART3RX_Handler, /* 18 UART 3 receive interrupt */ - UART3TX_Handler, /* 19 UART 3 transmit interrupt */ - UART4RX_Handler, /* 20 UART 4 receive interrupt */ - UART4TX_Handler, /* 21 UART 4 transmit interrupt */ - SPI_2_Handler, /* 22 SPI 2 interrupt */ - SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ - GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ - GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ - GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ - GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ - GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ - GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ - GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ - GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ - 0, /* 32 Reserved */ - 0, /* 33 Reserved */ - 0, /* 34 Reserved */ - 0, /* 35 Reserved */ - 0, /* 36 Reserved */ - 0, /* 37 Reserved */ - 0, /* 38 Reserved */ - 0, /* 39 Reserved */ - 0, /* 40 Reserved */ - 0, /* 41 Reserved */ - 0, /* 42 Reserved */ - 0, /* 43 Reserved */ - 0, /* 44 Reserved */ - 0, /* 45 Reserved */ - 0, /* 46 Reserved */ - 0, /* 47 Reserved */ - 0, /* 48 Reserved */ - 0, /* 49 Reserved */ - 0, /* 50 Reserved */ - 0, /* 51 Reserved */ - 0, /* 52 Reserved */ - 0, /* 53 Reserved */ - 0, /* 54 Reserved */ - 0, /* 55 Reserved */ - 0, /* 56 Reserved */ - 0, /* 57 Reserved */ - 0, /* 58 Reserved */ - 0, /* 59 Reserved */ - 0, /* 60 Reserved */ - 0, /* 61 Reserved */ - 0, /* 62 Reserved */ - 0, /* 63 Reserved */ - 0, /* 64 Reserved */ - 0, /* 65 Reserved */ - 0, /* 66 Reserved */ - 0, /* 67 Reserved */ - 0, /* 68 Reserved */ - 0, /* 69 Reserved */ - 0, /* 70 Reserved */ - 0, /* 71 Reserved */ - 0, /* 72 Reserved */ - 0, /* 73 Reserved */ - 0, /* 74 Reserved */ - 0, /* 75 Reserved */ - 0, /* 76 Reserved */ - 0, /* 77 Reserved */ - 0, /* 78 Reserved */ - 0, /* 79 Reserved */ - 0, /* 80 Reserved */ - 0, /* 81 Reserved */ - 0, /* 82 Reserved */ - 0, /* 83 Reserved */ - 0, /* 84 Reserved */ - 0, /* 85 Reserved */ - 0, /* 86 Reserved */ - 0, /* 87 Reserved */ - 0, /* 88 Reserved */ - 0, /* 89 Reserved */ - 0, /* 90 Reserved */ - 0, /* 91 Reserved */ - 0, /* 92 Reserved */ - 0, /* 93 Reserved */ - 0, /* 94 Reserved */ - 0, /* 95 Reserved */ - 0, /* 96 Reserved */ - 0, /* 97 Reserved */ - 0, /* 98 Reserved */ - 0, /* 99 Reserved */ - 0, /* 100 Reserved */ - 0, /* 101 Reserved */ - 0, /* 102 Reserved */ - 0, /* 103 Reserved */ - 0, /* 104 Reserved */ - 0, /* 105 Reserved */ - 0, /* 106 Reserved */ - 0, /* 107 Reserved */ - 0, /* 108 Reserved */ - 0, /* 109 Reserved */ - 0, /* 110 Reserved */ - 0, /* 111 Reserved */ - 0, /* 112 Reserved */ - 0, /* 113 Reserved */ - 0, /* 114 Reserved */ - 0, /* 115 Reserved */ - 0, /* 116 Reserved */ - 0, /* 117 Reserved */ - 0, /* 118 Reserved */ - 0, /* 119 Reserved */ - 0, /* 120 Reserved */ - 0, /* 121 Reserved */ - 0, /* 122 Reserved */ - 0, /* 123 Reserved */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c deleted file mode 100644 index 27aa0d7..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c +++ /dev/null @@ -1,85 +0,0 @@ -/****************************************************************************** - * @file system_CMSDK_CM4.c - * @brief CMSIS System Source File for CMSDK_M4 Device - ******************************************************************************/ -/* Copyright (c) 2011 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) - #include "CMSDK_CM4.h" -#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) - #include "CMSDK_CM4_FP.h" -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/Target.clayer.yml deleted file mode 100644 index 8e3ec74..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_CMx_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/vht_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_AC6/vht_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld deleted file mode 100644 index 59bd7d1..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/gcc_arm.ld +++ /dev/null @@ -1,279 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ - -/* -; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00400000; - -/*--------------------- Embedded RAM Configuration ---------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* -; -------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option �--section-start� or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG ((__bss_end__ - __bss_start__) / 4) - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c deleted file mode 100644 index 08b2426..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/startup_CMSDK_CM4.c +++ /dev/null @@ -1,423 +0,0 @@ -/****************************************************************************** - * @file startup_CMSDK_CM4.c - * @brief CMSIS Startup File for CMSDK_M4 Device - ******************************************************************************/ -/* Copyright (c) 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) - #include "CMSDK_CM4.h" -#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) - #include "CMSDK_CM4_FP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - UART0RX_Handler, /* 0 UART 0 receive interrupt */ - UART0TX_Handler, /* 1 UART 0 transmit interrupt */ - UART1RX_Handler, /* 2 UART 1 receive interrupt */ - UART1TX_Handler, /* 3 UART 1 transmit interrupt */ - UART2RX_Handler, /* 4 UART 2 receive interrupt */ - UART2TX_Handler, /* 5 UART 2 transmit interrupt */ - GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ - GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ - TIMER0_Handler, /* 8 Timer 0 interrupt */ - TIMER1_Handler, /* 9 Timer 1 interrupt */ - DUALTIMER_Handler, /* 10 Dual Timer interrupt */ - SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ - UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ - ETHERNET_Handler, /* 13 Ethernet interrupt */ - I2S_Handler, /* 14 Audio I2S interrupt */ - TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ - GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ - GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ - UART3RX_Handler, /* 18 UART 3 receive interrupt */ - UART3TX_Handler, /* 19 UART 3 transmit interrupt */ - UART4RX_Handler, /* 20 UART 4 receive interrupt */ - UART4TX_Handler, /* 21 UART 4 transmit interrupt */ - SPI_2_Handler, /* 22 SPI 2 interrupt */ - SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ - GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ - GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ - GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ - GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ - GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ - GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ - GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ - GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ - 0, /* 32 Reserved */ - 0, /* 33 Reserved */ - 0, /* 34 Reserved */ - 0, /* 35 Reserved */ - 0, /* 36 Reserved */ - 0, /* 37 Reserved */ - 0, /* 38 Reserved */ - 0, /* 39 Reserved */ - 0, /* 40 Reserved */ - 0, /* 41 Reserved */ - 0, /* 42 Reserved */ - 0, /* 43 Reserved */ - 0, /* 44 Reserved */ - 0, /* 45 Reserved */ - 0, /* 46 Reserved */ - 0, /* 47 Reserved */ - 0, /* 48 Reserved */ - 0, /* 49 Reserved */ - 0, /* 50 Reserved */ - 0, /* 51 Reserved */ - 0, /* 52 Reserved */ - 0, /* 53 Reserved */ - 0, /* 54 Reserved */ - 0, /* 55 Reserved */ - 0, /* 56 Reserved */ - 0, /* 57 Reserved */ - 0, /* 58 Reserved */ - 0, /* 59 Reserved */ - 0, /* 60 Reserved */ - 0, /* 61 Reserved */ - 0, /* 62 Reserved */ - 0, /* 63 Reserved */ - 0, /* 64 Reserved */ - 0, /* 65 Reserved */ - 0, /* 66 Reserved */ - 0, /* 67 Reserved */ - 0, /* 68 Reserved */ - 0, /* 69 Reserved */ - 0, /* 70 Reserved */ - 0, /* 71 Reserved */ - 0, /* 72 Reserved */ - 0, /* 73 Reserved */ - 0, /* 74 Reserved */ - 0, /* 75 Reserved */ - 0, /* 76 Reserved */ - 0, /* 77 Reserved */ - 0, /* 78 Reserved */ - 0, /* 79 Reserved */ - 0, /* 80 Reserved */ - 0, /* 81 Reserved */ - 0, /* 82 Reserved */ - 0, /* 83 Reserved */ - 0, /* 84 Reserved */ - 0, /* 85 Reserved */ - 0, /* 86 Reserved */ - 0, /* 87 Reserved */ - 0, /* 88 Reserved */ - 0, /* 89 Reserved */ - 0, /* 90 Reserved */ - 0, /* 91 Reserved */ - 0, /* 92 Reserved */ - 0, /* 93 Reserved */ - 0, /* 94 Reserved */ - 0, /* 95 Reserved */ - 0, /* 96 Reserved */ - 0, /* 97 Reserved */ - 0, /* 98 Reserved */ - 0, /* 99 Reserved */ - 0, /* 100 Reserved */ - 0, /* 101 Reserved */ - 0, /* 102 Reserved */ - 0, /* 103 Reserved */ - 0, /* 104 Reserved */ - 0, /* 105 Reserved */ - 0, /* 106 Reserved */ - 0, /* 107 Reserved */ - 0, /* 108 Reserved */ - 0, /* 109 Reserved */ - 0, /* 110 Reserved */ - 0, /* 111 Reserved */ - 0, /* 112 Reserved */ - 0, /* 113 Reserved */ - 0, /* 114 Reserved */ - 0, /* 115 Reserved */ - 0, /* 116 Reserved */ - 0, /* 117 Reserved */ - 0, /* 118 Reserved */ - 0, /* 119 Reserved */ - 0, /* 120 Reserved */ - 0, /* 121 Reserved */ - 0, /* 122 Reserved */ - 0, /* 123 Reserved */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined CMSDK_CM4_VHT || defined CMSDK_CM4_FP_VHT - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c deleted file mode 100644 index 27aa0d7..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/RTE/Device/CMSDK_CM4_FP_VHT/system_CMSDK_CM4.c +++ /dev/null @@ -1,85 +0,0 @@ -/****************************************************************************** - * @file system_CMSDK_CM4.c - * @brief CMSIS System Source File for CMSDK_M4 Device - ******************************************************************************/ -/* Copyright (c) 2011 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM4) || defined (CMSDK_CM4_VHT) - #include "CMSDK_CM4.h" -#elif defined (CMSDK_CM4_FP) || defined (CMSDK_CM4_FP_VHT) - #include "CMSDK_CM4_FP.h" -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/Target.clayer.yml deleted file mode 100644 index 8e3ec74..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_CMx_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/vht_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM4_FP_VHT_GCC/vht_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/RTE_Device.h deleted file mode 100644 index 5bf4c86..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/RTE_Device.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2019-2022 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::Drivers:USART -#define RTE_USART0 1 - -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::Drivers:USART -#define RTE_USART1 1 - -// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] -// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC -#define RTE_ISRAM0_MPC 1 - -// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] -// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC -#define RTE_ISRAM1_MPC 1 - -// MPC (Memory Protection Controller) [Driver_SRAM_MPC] -// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC -#define RTE_SRAM_MPC 1 - -// MPC (Memory Protection Controller) [Driver_QSPI_MPC] -// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC -#define RTE_QSPI_MPC 1 - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] -// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN0 1 - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] -// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN_EXP0 1 - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] -// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN_EXP1 1 - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] -// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH0 1 - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] -// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH1 1 - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP0 1 - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP1 1 - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP2 1 - -// Flash device emulated by SRAM [Driver_Flash0] -// Configuration settings for Driver_Flash0 in component ::Drivers:Flash -#define RTE_FLASH0 1 - -// I2C SBCon [Driver_I2C0] -// Configuration settings for Driver_I2C0 in component ::Drivers:I2C -#define RTE_I2C0 1 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h deleted file mode 100644 index bfc348f..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2019-2022 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_DRIVER_CONFIG_H__ -#define __CMSIS_DRIVER_CONFIG_H__ - -#include "system_SSE300MPS3.h" -#include "device_cfg.h" -#include "device_definition.h" -#include "platform_base_address.h" - -#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/device_cfg.h b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/device_cfg.h deleted file mode 100644 index 2ff3eaa..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/device_cfg.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2020-2022 Arm Limited. All rights reserved. - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __DEVICE_CFG_H__ -#define __DEVICE_CFG_H__ - -/** - * \file device_cfg.h - * \brief Configuration file native driver re-targeting - * - * \details This file can be used to add native driver specific macro - * definitions to select which peripherals are available in the build. - * - * This is a default device configuration file with all peripherals enabled. - */ - -/* Secure only peripheral configuration */ - -/* ARM MPS3 IO SCC */ -#define MPS3_IO_S -#define MPS3_IO_DEV MPS3_IO_DEV_S - -/* I2C_SBCon */ -#define I2C0_SBCON_S -#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S - -/* I2S */ -#define MPS3_I2S_S -#define MPS3_I2S_DEV MPS3_I2S_DEV_S - -/* ARM UART Controller PL011 */ -#define UART0_CMSDK_S -#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S -#define UART1_CMSDK_S -#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S - -#define DEFAULT_UART_BAUDRATE 115200U - -/* To be used as CODE and DATA sram */ -#define MPC_ISRAM0_S -#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S - -#define MPC_ISRAM1_S -#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S - -#define MPC_SRAM_S -#define MPC_SRAM_DEV MPC_SRAM_DEV_S - -#define MPC_QSPI_S -#define MPC_QSPI_DEV MPC_QSPI_DEV_S - -/** System Counter Armv8-M */ -#define SYSCOUNTER_CNTRL_ARMV8_M_S -#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S - -#define SYSCOUNTER_READ_ARMV8_M_S -#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S -/** - * Arbitrary scaling values for test purposes - */ -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u - -/* System timer */ -#define SYSTIMER0_ARMV8_M_S -#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S -#define SYSTIMER1_ARMV8_M_S -#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S -#define SYSTIMER2_ARMV8_M_S -#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S -#define SYSTIMER3_ARMV8_M_S -#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S - -#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) - -/* CMSDK GPIO driver structures */ -#define GPIO0_CMSDK_S -#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S -#define GPIO1_CMSDK_S -#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S -#define GPIO2_CMSDK_S -#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S -#define GPIO3_CMSDK_S -#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S - -/* System Watchdogs */ -#define SYSWDOG_ARMV8_M_S -#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S - -/* ARM MPC SIE 300 driver structures */ -#define MPC_VM0_S -#define MPC_VM0_DEV MPC_VM0_DEV_S -#define MPC_VM1_S -#define MPC_VM1_DEV MPC_VM1_DEV_S -#define MPC_SSRAM2_S -#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S -#define MPC_SSRAM3_S -#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S - -/* ARM PPC driver structures */ -#define PPC_SSE300_MAIN0_S -#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S -#define PPC_SSE300_MAIN_EXP0_S -#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S -#define PPC_SSE300_MAIN_EXP1_S -#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S -#define PPC_SSE300_MAIN_EXP2_S -#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S -#define PPC_SSE300_MAIN_EXP3_S -#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S -#define PPC_SSE300_PERIPH0_S -#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S -#define PPC_SSE300_PERIPH1_S -#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S -#define PPC_SSE300_PERIPH_EXP0_S -#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S -#define PPC_SSE300_PERIPH_EXP1_S -#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S -#define PPC_SSE300_PERIPH_EXP2_S -#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S -#define PPC_SSE300_PERIPH_EXP3_S -#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S - -/* ARM SPI PL022 */ -/* Invalid device stubs are not defined */ -#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ -#define SPI1_PL022_S -#define SPI1_PL022_DEV SPI1_PL022_DEV_S - - -#endif /* __DEVICE_CFG_H__ */ diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct deleted file mode 100644 index 343c63d..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct +++ /dev/null @@ -1,78 +0,0 @@ -#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc - -;/* -; * Copyright (c) 2018-2021 Arm Limited. All rights reserved. -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; */ - -#include "region_defs.h" - -LR_CODE S_CODE_START { - ER_CODE S_CODE_START { - *.o (RESET +First) - .ANY (+RO) - } - - /* - * Place the CMSE Veneers (containing the SG instruction) after the code, in - * a separate 32 bytes aligned region so that the SAU can programmed to just - * set this region as Non-Secure Callable. The maximum size of this - * executable region makes it only used the space left over by the ER_CODE - * region so that you can rely on code+veneer size combined will not exceed - * the S_CODE_SIZE value. We also substract from the available space the - * area used to align this section on 32 bytes boundary (for SAU conf). - */ - ER_CODE_CMSE_VENEER +0 ALIGN 32 { - *(Veneer$$CMSE) - } - /* - * This dummy region ensures that the next one will be aligned on a 32 bytes - * boundary, so that the following region will not be mistakenly configured - * as Non-Secure Callable by the SAU. - */ - ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {} - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - CODE_WATERMARK +0 EMPTY 0x0 { - } - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) - - ER_DATA S_DATA_START { - .ANY (+ZI +RW) - } - - #if HEAP_SIZE > 0 - ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap - } - #endif - - ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack - } - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - SRAM_WATERMARK +0 EMPTY 0x0 { - } - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) -} diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/platform_base_address.h b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/platform_base_address.h deleted file mode 100644 index b813097..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/platform_base_address.h +++ /dev/null @@ -1,271 +0,0 @@ -/* - * Copyright (c) 2019-2021 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file platform_base_address.h - * \brief This file defines all the peripheral base addresses for AN552 MPS3 SSE-300 + - * Ethos-U55 platform. - */ - -#ifndef __PLATFORM_BASE_ADDRESS_H__ -#define __PLATFORM_BASE_ADDRESS_H__ - -/* ======= Defines peripherals memory map addresses ======= */ -/* Non-secure memory map addresses */ -#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ -#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */ -#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */ -#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */ -#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */ -#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */ -#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ -#define ISRAM1_BASE_NS 0x21100000 /* Internal SRAM Area Non-Secure base address */ -#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ -#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ -#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */ -/* Non-Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */ -#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */ -#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */ -#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */ -#define FMC_CMSDK_GPIO_0_BASE_NS 0x41104000 /* FMC CMSDK GPIO 0 Non-Secure base address */ -#define FMC_CMSDK_GPIO_1_BASE_NS 0x41105000 /* FMC CMSDK GPIO 1 Non-Secure base address */ -#define FMC_CMSDK_GPIO_2_BASE_NS 0x41106000 /* FMC CMSDK GPIO 2 Non-Secure base address */ -#define FMC_CMSDK_GPIO_3_BASE_NS 0x41107000 /* FMC CMSDK GPIO 3 Non-Secure base address */ -#define EXTERNAL_MANAGER_0_BASE_NS 0x41200000 /* External manager 0 (Unused) Non-Secure base address */ -#define EXTERNAL_MANAGER_1_BASE_NS 0x41201000 /* External manager 1 (Unused) Non-Secure base address */ -#define EXTERNAL_MANAGER_2_BASE_NS 0x41202000 /* External manager 2 (Unused) Non-Secure base address */ -#define EXTERNAL_MANAGER_3_BASE_NS 0x41203000 /* External manager 3 (Unused) Non-Secure base address */ -#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */ -#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */ -#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */ -#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */ -#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */ -#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */ -#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */ -#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ -#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ -#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ -/* Non-Secure MSTEXPPIHL Peripheral region */ -#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */ -#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */ -#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ -#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */ -#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ -#define FMC_USER_APB0 0x4920C000 /* FMC User APB0 */ -#define FMC_USER_APB1 0x4920D000 /* FMC User APB1 */ -#define FMC_USER_APB2 0x4920E000 /* FMC User APB2 */ -#define FMC_USER_APB3 0x4920F000 /* FMC User APB3 */ -#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */ -#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */ -#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ -#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */ -#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */ -#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */ -#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */ -#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */ -#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */ -#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */ -#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */ -#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */ -#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */ -#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */ -#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */ - -/* Secure memory map addresses */ -#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ -#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */ -#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */ -#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */ -#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */ -#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */ -#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ -#define ISRAM1_BASE_S 0x31100000 /* Internal SRAM Area Secure base address */ -#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ -/* Secure Subsystem peripheral region */ -#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ -#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ -#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ -#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */ -#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */ -#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */ -/* Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */ -#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */ -#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */ -#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */ -#define FMC_CMSDK_GPIO_0_BASE_S 0x51104000 /* FMC CMSDK GPIO 0 Secure base address */ -#define FMC_CMSDK_GPIO_1_BASE_S 0x51105000 /* FMC CMSDK GPIO 1 Secure base address */ -#define FMC_CMSDK_GPIO_2_BASE_S 0x51106000 /* FMC CMSDK GPIO 2 Secure base address */ -#define FMC_CMSDK_GPIO_3_BASE_S 0x51107000 /* FMC CMSDK GPIO 3 Secure base address */ -#define EXTERNAL_MANAGER0_BASE_S 0x51200000 /* External Manager 0 (Unused) Secure base address */ -#define EXTERNAL_MANAGER1_BASE_S 0x51201000 /* External Manager 1 (Unused) Secure base address */ -#define EXTERNAL_MANAGER2_BASE_S 0x51202000 /* External Manager 2 (Unused) Secure base address */ -#define EXTERNAL_MANAGER3_BASE_S 0x51203000 /* External Manager 3 (Unused) Secure base address */ -#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */ -#define USB_BASE_S 0x51500000 /* USB Secure base address */ -#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */ -#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */ -#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */ -#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */ -#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */ -#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */ -#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */ -#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */ -#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */ -/* Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */ -#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */ -#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */ -#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */ -#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */ -#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */ -#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */ -#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ -#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */ -#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ -/* Secure MSTEXPPIHL Peripheral region */ -#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */ -#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */ -#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ -#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */ -#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ -#define FMC_USER_APB_0_BASE_S 0x5920C000 /* FMC User APB0 registers Secure base address */ -#define FMC_USER_APB_1_BASE_S 0x5920D000 /* FMC User APB1 registers Secure base address */ -#define FMC_USER_APB_2_BASE_S 0x5920E000 /* FMC User APB2 registers Secure base address */ -#define FMC_USER_APB_3_BASE_S 0x5920F000 /* FMC User APB3 registers Secure base address */ -#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */ -#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */ -#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ -#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */ -#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */ -#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */ -#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */ -#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */ -#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */ -#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */ -#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */ -#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */ -#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ -#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ -#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */ - -/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ -#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller - * Access from Non-secure software is only allowed - * if AIRCR.BFHFNMINS is set to 1 */ - -/* Memory size definitions */ -#define ITCM_SIZE (0x00080000) /* 512 kB */ -#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */ -#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ -#define SRAM_SIZE (0x00100000) /* 1 MB */ -#define ISRAM0_SIZE (0x00100000) /* 1 MB */ -#define ISRAM1_SIZE (0x00100000) /* 1 MB */ -#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ -#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ -#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ - -/* Defines for Driver MPC's */ -/* SRAM -- 2 MB */ -#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS) -#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_NS (0x0) -#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S) -#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_S (0x0) - -/* QSPI -- 8 MB*/ -#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS) -#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_NS (0x0) -#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S) -#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_S (0x0) - -/* ISRAM0 -- 2 MB*/ -#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS) -#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S) -#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_S (0x0) - -/* ISRAM1 -- 2 MB*/ -#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS) -#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S) -#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_S (0x0) - -/* DDR4 -- 2GB (8 * 256 MB) */ -#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0) -#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S) -#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S) -#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S) -#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S) -#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS) - -#endif /* __PLATFORM_BASE_ADDRESS_H__ */ diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/region_defs.h b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/region_defs.h deleted file mode 100644 index 32ac16b..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/region_defs.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2016-2022 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_DEFS_H__ -#define __REGION_DEFS_H__ - -#include "region_limits.h" - -/* ************************************************************** - * WARNING: this file is parsed both by the C/C++ compiler - * and the linker. As a result the syntax must be valid not only - * for C/C++ but for the linker scripts too. - * Beware of the following limitations: - * - LD (GCC linker) requires white space around operators. - * - UL postfix for macros is not suported by the linker script - ****************************************************************/ - -/* Secure regions */ -#define S_CODE_START ( S_ROM_ALIAS ) -#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) -#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) - -#define S_DATA_START ( S_RAM_ALIAS ) -#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) -#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) - -#define S_DDR4_START ( S_DDR4_ALIAS ) -#define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) -#define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) - -#endif /* __REGION_DEFS_H__ */ diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/region_limits.h b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/region_limits.h deleted file mode 100644 index e789786..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/region_limits.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2018-2022 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_LIMITS_H__ -#define __REGION_LIMITS_H__ - -/* ************************************************************** - * WARNING: this file is parsed both by the C/C++ compiler - * and the linker. As a result the syntax must be valid not only - * for C/C++ but for the linker scripts too. - * Beware of the following limitations: - * - LD (GCC linker) requires white space around operators. - * - UL postfix for macros is not suported by the linker script - ****************************************************************/ - -/* Secure Code */ -#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ -#define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ - -/* Secure Data */ -#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ -#define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ - -/* Secure DDR4 */ -#define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ -#define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ - -/* Heap and Stack sizes for secure and nonsecure applications */ -#define HEAP_SIZE (0x00000400) /* 1 KiB */ -#define STACK_SIZE (0x00000400) /* 1 KiB */ - -#endif /* __REGION_LIMITS_H__ */ diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c deleted file mode 100644 index d1e59d7..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "SSE300MPS3.h" - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler Function Prototype - *----------------------------------------------------------------------------*/ -typedef void( *pFunc )( void ); - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; - -extern void __PROGRAM_START(void) __NO_RETURN; - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Reset_Handler (void) __NO_RETURN; - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -#define DEFAULT_IRQ_HANDLER(handler_name) \ -void __WEAK __NO_RETURN handler_name(void); \ -void handler_name(void) { \ - while(1); \ -} - -/* Exceptions */ -DEFAULT_IRQ_HANDLER(NMI_Handler) -DEFAULT_IRQ_HANDLER(HardFault_Handler) -DEFAULT_IRQ_HANDLER(MemManage_Handler) -DEFAULT_IRQ_HANDLER(BusFault_Handler) -DEFAULT_IRQ_HANDLER(UsageFault_Handler) -DEFAULT_IRQ_HANDLER(SecureFault_Handler) -DEFAULT_IRQ_HANDLER(SVC_Handler) -DEFAULT_IRQ_HANDLER(DebugMon_Handler) -DEFAULT_IRQ_HANDLER(PendSV_Handler) -DEFAULT_IRQ_HANDLER(SysTick_Handler) - -DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler) -DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) -DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) -DEFAULT_IRQ_HANDLER(TIMER0_Handler) -DEFAULT_IRQ_HANDLER(TIMER1_Handler) -DEFAULT_IRQ_HANDLER(TIMER2_Handler) -DEFAULT_IRQ_HANDLER(MPC_Handler) -DEFAULT_IRQ_HANDLER(PPC_Handler) -DEFAULT_IRQ_HANDLER(MSC_Handler) -DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) -DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) -DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) -DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) -DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) -DEFAULT_IRQ_HANDLER(TIMER3_Handler) -DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler) -DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler) - -DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) -DEFAULT_IRQ_HANDLER(UARTRX0_Handler) -DEFAULT_IRQ_HANDLER(UARTTX0_Handler) -DEFAULT_IRQ_HANDLER(UARTRX1_Handler) -DEFAULT_IRQ_HANDLER(UARTTX1_Handler) -DEFAULT_IRQ_HANDLER(UARTRX2_Handler) -DEFAULT_IRQ_HANDLER(UARTTX2_Handler) -DEFAULT_IRQ_HANDLER(UARTRX3_Handler) -DEFAULT_IRQ_HANDLER(UARTTX3_Handler) -DEFAULT_IRQ_HANDLER(UARTRX4_Handler) -DEFAULT_IRQ_HANDLER(UARTTX4_Handler) -DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) -DEFAULT_IRQ_HANDLER(UARTOVF_Handler) -DEFAULT_IRQ_HANDLER(ETHERNET_Handler) -DEFAULT_IRQ_HANDLER(I2S_Handler) -DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) -DEFAULT_IRQ_HANDLER(USB_Handler) -DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) -DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) -DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) -DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) -DEFAULT_IRQ_HANDLER(UARTRX5_Handler) -DEFAULT_IRQ_HANDLER(UARTTX5_Handler) -DEFAULT_IRQ_HANDLER(UART5_Handler) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const pFunc __VECTOR_TABLE[496]; - const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14: NMI Handler */ - HardFault_Handler, /* -13: Hard Fault Handler */ - MemManage_Handler, /* -12: MPU Fault Handler */ - BusFault_Handler, /* -11: Bus Fault Handler */ - UsageFault_Handler, /* -10: Usage Fault Handler */ - SecureFault_Handler, /* -9: Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5: SVCall Handler */ - DebugMon_Handler, /* -4: Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2: PendSV Handler */ - SysTick_Handler, /* -1: SysTick Handler */ - - NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */ - NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ - SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ - TIMER0_Handler, /* 3: TIMER 0 Handler */ - TIMER1_Handler, /* 4: TIMER 1 Handler */ - TIMER2_Handler, /* 5: TIMER 2 Handler */ - 0, /* 6: Reserved */ - 0, /* 7: Reserved */ - 0, /* 8: Reserved */ - MPC_Handler, /* 9: MPC Combined (Secure) Handler */ - PPC_Handler, /* 10: PPC Combined (Secure) Handler */ - MSC_Handler, /* 11: MSC Combined (Secure) Handler */ - BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ - 0, /* 13: Reserved */ - MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ - SYS_PPU_Handler, /* 15: SYS PPU Handler */ - CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ - 0, /* 17: Reserved */ - 0, /* 18: Reserved */ - 0, /* 19: Reserved */ - 0, /* 20: Reserved */ - 0, /* 21: Reserved */ - 0, /* 22: Reserved */ - 0, /* 23: Reserved */ - 0, /* 24: Reserved */ - 0, /* 25: Reserved */ - DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ - TIMER3_Handler, /* 27: TIMER 3 Handler */ - CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */ - CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */ - 0, /* 30: Reserved */ - 0, /* 31: Reserved */ - - /* External interrupts */ - System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ - UARTRX0_Handler, /* 33: UART 0 RX Handler */ - UARTTX0_Handler, /* 34: UART 0 TX Handler */ - UARTRX1_Handler, /* 35: UART 1 RX Handler */ - UARTTX1_Handler, /* 36: UART 1 TX Handler */ - UARTRX2_Handler, /* 37: UART 2 RX Handler */ - UARTTX2_Handler, /* 38: UART 2 TX Handler */ - UARTRX3_Handler, /* 39: UART 3 RX Handler */ - UARTTX3_Handler, /* 40: UART 3 TX Handler */ - UARTRX4_Handler, /* 41: UART 4 RX Handler */ - UARTTX4_Handler, /* 42: UART 4 TX Handler */ - UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ - UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ - UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ - UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ - UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ - UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ - ETHERNET_Handler, /* 49: Ethernet Handler */ - I2S_Handler, /* 50: Audio I2S Handler */ - TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ - USB_Handler, /* 52: USB Handler */ - SPI_ADC_Handler, /* 53: SPI ADC Handler */ - SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ - SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ - ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ - 0, /* 57: Reserved */ - 0, /* 58: Reserved */ - 0, /* 59: Reserved */ - 0, /* 60: Reserved */ - 0, /* 61: Reserved */ - 0, /* 62: Reserved */ - 0, /* 63: Reserved */ - 0, /* 64: Reserved */ - 0, /* 65: Reserved */ - 0, /* 66: Reserved */ - 0, /* 67: Reserved */ - 0, /* 68: Reserved */ - GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ - GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ - GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ - GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ - GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ - GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ - GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ - GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ - GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ - GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ - GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ - GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ - GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ - GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ - GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ - GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ - GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ - GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ - GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ - GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ - GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ - GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ - GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ - GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ - GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ - GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ - GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ - GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ - GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ - GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ - GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ - GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ - GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ - GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ - GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ - GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ - GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ - GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ - GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ - GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ - GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ - GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ - GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ - GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ - GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ - GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ - GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ - GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ - GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ - GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ - GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ - GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ - GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ - GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ - GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ - GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ - UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ - UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ - UART5_Handler, /* 127: UART 5 combined Interrupt */ - 0, /* 128: Reserved */ - 0, /* 129: Reserved */ - 0, /* 130: Reserved */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h deleted file mode 100644 index feba5e9..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2009-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#ifndef __SYSTEM_CORE_INIT_H__ -#define __SYSTEM_CORE_INIT_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ - -/** - * \brief Initializes the system - */ -extern void SystemInit(void); - -/** - * \brief Restores system core clock - */ -extern void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_CORE_INIT_H__ */ diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/Target.clayer.yml deleted file mode 100644 index 3c484c1..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/Target.clayer.yml +++ /dev/null @@ -1,27 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: ARM::V2M_MPS3_SSE_300_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: ARM::CMSIS Driver:USART - - - component: ARM::Device:Startup&Baremetal - - component: ARM::Device:Definition - - - component: ARM::Native Driver:SysCounter - - component: ARM::Native Driver:SysTimer - - component: ARM::Native Driver:Timeout - - component: ARM::Native Driver:UART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/vht_config.txt deleted file mode 100644 index 1329fed..0000000 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/vht_config.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -cpu_core.core_clk.mul=100000000 # (int , init-time) default = '0x17d7840' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -cpu_core.mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected -cpu_core.mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -cpu_core.mps3_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -cpu_core.mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ \ No newline at end of file diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct deleted file mode 100644 index e1b77e5..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/ac6_arm.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c deleted file mode 100644 index 82b8c8a..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c +++ /dev/null @@ -1,425 +0,0 @@ -/****************************************************************************** - * @file startup_CMSDK_CM7.c - * @brief CMSIS Startup File for CMSDK_M7 Device - ******************************************************************************/ -/* Copyright (c) 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) - #include "CMSDK_CM7.h" -#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) - #include "CMSDK_CM7_SP.h" -#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) - #include "CMSDK_CM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - UART0RX_Handler, /* 0 UART 0 receive interrupt */ - UART0TX_Handler, /* 1 UART 0 transmit interrupt */ - UART1RX_Handler, /* 2 UART 1 receive interrupt */ - UART1TX_Handler, /* 3 UART 1 transmit interrupt */ - UART2RX_Handler, /* 4 UART 2 receive interrupt */ - UART2TX_Handler, /* 5 UART 2 transmit interrupt */ - GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ - GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ - TIMER0_Handler, /* 8 Timer 0 interrupt */ - TIMER1_Handler, /* 9 Timer 1 interrupt */ - DUALTIMER_Handler, /* 10 Dual Timer interrupt */ - SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ - UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ - ETHERNET_Handler, /* 13 Ethernet interrupt */ - I2S_Handler, /* 14 Audio I2S interrupt */ - TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ - GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ - GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ - UART3RX_Handler, /* 18 UART 3 receive interrupt */ - UART3TX_Handler, /* 19 UART 3 transmit interrupt */ - UART4RX_Handler, /* 20 UART 4 receive interrupt */ - UART4TX_Handler, /* 21 UART 4 transmit interrupt */ - SPI_2_Handler, /* 22 SPI 2 interrupt */ - SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ - GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ - GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ - GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ - GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ - GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ - GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ - GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ - GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ - 0, /* 32 Reserved */ - 0, /* 33 Reserved */ - 0, /* 34 Reserved */ - 0, /* 35 Reserved */ - 0, /* 36 Reserved */ - 0, /* 37 Reserved */ - 0, /* 38 Reserved */ - 0, /* 39 Reserved */ - 0, /* 40 Reserved */ - 0, /* 41 Reserved */ - 0, /* 42 Reserved */ - 0, /* 43 Reserved */ - 0, /* 44 Reserved */ - 0, /* 45 Reserved */ - 0, /* 46 Reserved */ - 0, /* 47 Reserved */ - 0, /* 48 Reserved */ - 0, /* 49 Reserved */ - 0, /* 50 Reserved */ - 0, /* 51 Reserved */ - 0, /* 52 Reserved */ - 0, /* 53 Reserved */ - 0, /* 54 Reserved */ - 0, /* 55 Reserved */ - 0, /* 56 Reserved */ - 0, /* 57 Reserved */ - 0, /* 58 Reserved */ - 0, /* 59 Reserved */ - 0, /* 60 Reserved */ - 0, /* 61 Reserved */ - 0, /* 62 Reserved */ - 0, /* 63 Reserved */ - 0, /* 64 Reserved */ - 0, /* 65 Reserved */ - 0, /* 66 Reserved */ - 0, /* 67 Reserved */ - 0, /* 68 Reserved */ - 0, /* 69 Reserved */ - 0, /* 70 Reserved */ - 0, /* 71 Reserved */ - 0, /* 72 Reserved */ - 0, /* 73 Reserved */ - 0, /* 74 Reserved */ - 0, /* 75 Reserved */ - 0, /* 76 Reserved */ - 0, /* 77 Reserved */ - 0, /* 78 Reserved */ - 0, /* 79 Reserved */ - 0, /* 80 Reserved */ - 0, /* 81 Reserved */ - 0, /* 82 Reserved */ - 0, /* 83 Reserved */ - 0, /* 84 Reserved */ - 0, /* 85 Reserved */ - 0, /* 86 Reserved */ - 0, /* 87 Reserved */ - 0, /* 88 Reserved */ - 0, /* 89 Reserved */ - 0, /* 90 Reserved */ - 0, /* 91 Reserved */ - 0, /* 92 Reserved */ - 0, /* 93 Reserved */ - 0, /* 94 Reserved */ - 0, /* 95 Reserved */ - 0, /* 96 Reserved */ - 0, /* 97 Reserved */ - 0, /* 98 Reserved */ - 0, /* 99 Reserved */ - 0, /* 100 Reserved */ - 0, /* 101 Reserved */ - 0, /* 102 Reserved */ - 0, /* 103 Reserved */ - 0, /* 104 Reserved */ - 0, /* 105 Reserved */ - 0, /* 106 Reserved */ - 0, /* 107 Reserved */ - 0, /* 108 Reserved */ - 0, /* 109 Reserved */ - 0, /* 110 Reserved */ - 0, /* 111 Reserved */ - 0, /* 112 Reserved */ - 0, /* 113 Reserved */ - 0, /* 114 Reserved */ - 0, /* 115 Reserved */ - 0, /* 116 Reserved */ - 0, /* 117 Reserved */ - 0, /* 118 Reserved */ - 0, /* 119 Reserved */ - 0, /* 120 Reserved */ - 0, /* 121 Reserved */ - 0, /* 122 Reserved */ - 0, /* 123 Reserved */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c deleted file mode 100644 index fdfec7a..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c +++ /dev/null @@ -1,87 +0,0 @@ -/****************************************************************************** - * @file system_CMSDK_CM7.c - * @brief CMSIS System Source File for CMSDK_CM7 Device - ******************************************************************************/ -/* Copyright (c) 2011 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) - #include "CMSDK_CM7.h" -#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) - #include "CMSDK_CM7_SP.h" -#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) - #include "CMSDK_CM7_DP.h" -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/Target.clayer.yml deleted file mode 100644 index 8e3ec74..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_CMx_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/vht_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_AC6/vht_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld deleted file mode 100644 index 59bd7d1..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/gcc_arm.ld +++ /dev/null @@ -1,279 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ - -/* -; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00400000; - -/*--------------------- Embedded RAM Configuration ---------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* -; -------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option �--section-start� or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG ((__bss_end__ - __bss_start__) / 4) - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c deleted file mode 100644 index 82b8c8a..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/startup_CMSDK_CM7.c +++ /dev/null @@ -1,425 +0,0 @@ -/****************************************************************************** - * @file startup_CMSDK_CM7.c - * @brief CMSIS Startup File for CMSDK_M7 Device - ******************************************************************************/ -/* Copyright (c) 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) - #include "CMSDK_CM7.h" -#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) - #include "CMSDK_CM7_SP.h" -#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) - #include "CMSDK_CM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - UART0RX_Handler, /* 0 UART 0 receive interrupt */ - UART0TX_Handler, /* 1 UART 0 transmit interrupt */ - UART1RX_Handler, /* 2 UART 1 receive interrupt */ - UART1TX_Handler, /* 3 UART 1 transmit interrupt */ - UART2RX_Handler, /* 4 UART 2 receive interrupt */ - UART2TX_Handler, /* 5 UART 2 transmit interrupt */ - GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ - GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ - TIMER0_Handler, /* 8 Timer 0 interrupt */ - TIMER1_Handler, /* 9 Timer 1 interrupt */ - DUALTIMER_Handler, /* 10 Dual Timer interrupt */ - SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ - UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ - ETHERNET_Handler, /* 13 Ethernet interrupt */ - I2S_Handler, /* 14 Audio I2S interrupt */ - TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ - GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ - GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ - UART3RX_Handler, /* 18 UART 3 receive interrupt */ - UART3TX_Handler, /* 19 UART 3 transmit interrupt */ - UART4RX_Handler, /* 20 UART 4 receive interrupt */ - UART4TX_Handler, /* 21 UART 4 transmit interrupt */ - SPI_2_Handler, /* 22 SPI 2 interrupt */ - SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ - GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ - GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ - GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ - GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ - GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ - GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ - GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ - GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ - 0, /* 32 Reserved */ - 0, /* 33 Reserved */ - 0, /* 34 Reserved */ - 0, /* 35 Reserved */ - 0, /* 36 Reserved */ - 0, /* 37 Reserved */ - 0, /* 38 Reserved */ - 0, /* 39 Reserved */ - 0, /* 40 Reserved */ - 0, /* 41 Reserved */ - 0, /* 42 Reserved */ - 0, /* 43 Reserved */ - 0, /* 44 Reserved */ - 0, /* 45 Reserved */ - 0, /* 46 Reserved */ - 0, /* 47 Reserved */ - 0, /* 48 Reserved */ - 0, /* 49 Reserved */ - 0, /* 50 Reserved */ - 0, /* 51 Reserved */ - 0, /* 52 Reserved */ - 0, /* 53 Reserved */ - 0, /* 54 Reserved */ - 0, /* 55 Reserved */ - 0, /* 56 Reserved */ - 0, /* 57 Reserved */ - 0, /* 58 Reserved */ - 0, /* 59 Reserved */ - 0, /* 60 Reserved */ - 0, /* 61 Reserved */ - 0, /* 62 Reserved */ - 0, /* 63 Reserved */ - 0, /* 64 Reserved */ - 0, /* 65 Reserved */ - 0, /* 66 Reserved */ - 0, /* 67 Reserved */ - 0, /* 68 Reserved */ - 0, /* 69 Reserved */ - 0, /* 70 Reserved */ - 0, /* 71 Reserved */ - 0, /* 72 Reserved */ - 0, /* 73 Reserved */ - 0, /* 74 Reserved */ - 0, /* 75 Reserved */ - 0, /* 76 Reserved */ - 0, /* 77 Reserved */ - 0, /* 78 Reserved */ - 0, /* 79 Reserved */ - 0, /* 80 Reserved */ - 0, /* 81 Reserved */ - 0, /* 82 Reserved */ - 0, /* 83 Reserved */ - 0, /* 84 Reserved */ - 0, /* 85 Reserved */ - 0, /* 86 Reserved */ - 0, /* 87 Reserved */ - 0, /* 88 Reserved */ - 0, /* 89 Reserved */ - 0, /* 90 Reserved */ - 0, /* 91 Reserved */ - 0, /* 92 Reserved */ - 0, /* 93 Reserved */ - 0, /* 94 Reserved */ - 0, /* 95 Reserved */ - 0, /* 96 Reserved */ - 0, /* 97 Reserved */ - 0, /* 98 Reserved */ - 0, /* 99 Reserved */ - 0, /* 100 Reserved */ - 0, /* 101 Reserved */ - 0, /* 102 Reserved */ - 0, /* 103 Reserved */ - 0, /* 104 Reserved */ - 0, /* 105 Reserved */ - 0, /* 106 Reserved */ - 0, /* 107 Reserved */ - 0, /* 108 Reserved */ - 0, /* 109 Reserved */ - 0, /* 110 Reserved */ - 0, /* 111 Reserved */ - 0, /* 112 Reserved */ - 0, /* 113 Reserved */ - 0, /* 114 Reserved */ - 0, /* 115 Reserved */ - 0, /* 116 Reserved */ - 0, /* 117 Reserved */ - 0, /* 118 Reserved */ - 0, /* 119 Reserved */ - 0, /* 120 Reserved */ - 0, /* 121 Reserved */ - 0, /* 122 Reserved */ - 0, /* 123 Reserved */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c deleted file mode 100644 index fdfec7a..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/RTE/Device/CMSDK_CM7_DP_VHT/system_CMSDK_CM7.c +++ /dev/null @@ -1,87 +0,0 @@ -/****************************************************************************** - * @file system_CMSDK_CM7.c - * @brief CMSIS System Source File for CMSDK_CM7 Device - ******************************************************************************/ -/* Copyright (c) 2011 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) - #include "CMSDK_CM7.h" -#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) - #include "CMSDK_CM7_SP.h" -#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) - #include "CMSDK_CM7_DP.h" -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/Target.clayer.yml deleted file mode 100644 index 8e3ec74..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_CMx_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/vht_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_DP_VHT_GCC/vht_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct deleted file mode 100644 index e1b77e5..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct +++ /dev/null @@ -1,76 +0,0 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc -; command above MUST be in first line (no comment above!) - -/* -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- -*/ - -/*--------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x00000000 -#define __ROM_SIZE 0x00080000 - -/*--------------------- Embedded RAM Configuration --------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x20000000 -#define __RAM_SIZE 0x00040000 - -/*--------------------- Stack / Heap Configuration --------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000200 -#define __HEAP_SIZE 0x00000C00 - -/* -;------------- <<< end of configuration section >>> --------------------------- -*/ - - -/*---------------------------------------------------------------------------- - User Stack & Heap boundary definition - *----------------------------------------------------------------------------*/ -#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ -#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ - - -/*---------------------------------------------------------------------------- - Scatter File Definitions definition - *----------------------------------------------------------------------------*/ -#define __RO_BASE __ROM_BASE -#define __RO_SIZE __ROM_SIZE - -#define __RW_BASE __RAM_BASE -#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) - - -LR_ROM __RO_BASE __RO_SIZE { ; load region size_region - ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - .ANY (+XO) - } - - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) - } - -#if __HEAP_SIZE > 0 - ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap - } -#endif - - ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack - } -} diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c deleted file mode 100644 index 82b8c8a..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c +++ /dev/null @@ -1,425 +0,0 @@ -/****************************************************************************** - * @file startup_CMSDK_CM7.c - * @brief CMSIS Startup File for CMSDK_M7 Device - ******************************************************************************/ -/* Copyright (c) 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) - #include "CMSDK_CM7.h" -#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) - #include "CMSDK_CM7_SP.h" -#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) - #include "CMSDK_CM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - UART0RX_Handler, /* 0 UART 0 receive interrupt */ - UART0TX_Handler, /* 1 UART 0 transmit interrupt */ - UART1RX_Handler, /* 2 UART 1 receive interrupt */ - UART1TX_Handler, /* 3 UART 1 transmit interrupt */ - UART2RX_Handler, /* 4 UART 2 receive interrupt */ - UART2TX_Handler, /* 5 UART 2 transmit interrupt */ - GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ - GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ - TIMER0_Handler, /* 8 Timer 0 interrupt */ - TIMER1_Handler, /* 9 Timer 1 interrupt */ - DUALTIMER_Handler, /* 10 Dual Timer interrupt */ - SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ - UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ - ETHERNET_Handler, /* 13 Ethernet interrupt */ - I2S_Handler, /* 14 Audio I2S interrupt */ - TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ - GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ - GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ - UART3RX_Handler, /* 18 UART 3 receive interrupt */ - UART3TX_Handler, /* 19 UART 3 transmit interrupt */ - UART4RX_Handler, /* 20 UART 4 receive interrupt */ - UART4TX_Handler, /* 21 UART 4 transmit interrupt */ - SPI_2_Handler, /* 22 SPI 2 interrupt */ - SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ - GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ - GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ - GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ - GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ - GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ - GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ - GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ - GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ - 0, /* 32 Reserved */ - 0, /* 33 Reserved */ - 0, /* 34 Reserved */ - 0, /* 35 Reserved */ - 0, /* 36 Reserved */ - 0, /* 37 Reserved */ - 0, /* 38 Reserved */ - 0, /* 39 Reserved */ - 0, /* 40 Reserved */ - 0, /* 41 Reserved */ - 0, /* 42 Reserved */ - 0, /* 43 Reserved */ - 0, /* 44 Reserved */ - 0, /* 45 Reserved */ - 0, /* 46 Reserved */ - 0, /* 47 Reserved */ - 0, /* 48 Reserved */ - 0, /* 49 Reserved */ - 0, /* 50 Reserved */ - 0, /* 51 Reserved */ - 0, /* 52 Reserved */ - 0, /* 53 Reserved */ - 0, /* 54 Reserved */ - 0, /* 55 Reserved */ - 0, /* 56 Reserved */ - 0, /* 57 Reserved */ - 0, /* 58 Reserved */ - 0, /* 59 Reserved */ - 0, /* 60 Reserved */ - 0, /* 61 Reserved */ - 0, /* 62 Reserved */ - 0, /* 63 Reserved */ - 0, /* 64 Reserved */ - 0, /* 65 Reserved */ - 0, /* 66 Reserved */ - 0, /* 67 Reserved */ - 0, /* 68 Reserved */ - 0, /* 69 Reserved */ - 0, /* 70 Reserved */ - 0, /* 71 Reserved */ - 0, /* 72 Reserved */ - 0, /* 73 Reserved */ - 0, /* 74 Reserved */ - 0, /* 75 Reserved */ - 0, /* 76 Reserved */ - 0, /* 77 Reserved */ - 0, /* 78 Reserved */ - 0, /* 79 Reserved */ - 0, /* 80 Reserved */ - 0, /* 81 Reserved */ - 0, /* 82 Reserved */ - 0, /* 83 Reserved */ - 0, /* 84 Reserved */ - 0, /* 85 Reserved */ - 0, /* 86 Reserved */ - 0, /* 87 Reserved */ - 0, /* 88 Reserved */ - 0, /* 89 Reserved */ - 0, /* 90 Reserved */ - 0, /* 91 Reserved */ - 0, /* 92 Reserved */ - 0, /* 93 Reserved */ - 0, /* 94 Reserved */ - 0, /* 95 Reserved */ - 0, /* 96 Reserved */ - 0, /* 97 Reserved */ - 0, /* 98 Reserved */ - 0, /* 99 Reserved */ - 0, /* 100 Reserved */ - 0, /* 101 Reserved */ - 0, /* 102 Reserved */ - 0, /* 103 Reserved */ - 0, /* 104 Reserved */ - 0, /* 105 Reserved */ - 0, /* 106 Reserved */ - 0, /* 107 Reserved */ - 0, /* 108 Reserved */ - 0, /* 109 Reserved */ - 0, /* 110 Reserved */ - 0, /* 111 Reserved */ - 0, /* 112 Reserved */ - 0, /* 113 Reserved */ - 0, /* 114 Reserved */ - 0, /* 115 Reserved */ - 0, /* 116 Reserved */ - 0, /* 117 Reserved */ - 0, /* 118 Reserved */ - 0, /* 119 Reserved */ - 0, /* 120 Reserved */ - 0, /* 121 Reserved */ - 0, /* 122 Reserved */ - 0, /* 123 Reserved */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c deleted file mode 100644 index fdfec7a..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c +++ /dev/null @@ -1,87 +0,0 @@ -/****************************************************************************** - * @file system_CMSDK_CM7.c - * @brief CMSIS System Source File for CMSDK_CM7 Device - ******************************************************************************/ -/* Copyright (c) 2011 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) - #include "CMSDK_CM7.h" -#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) - #include "CMSDK_CM7_SP.h" -#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) - #include "CMSDK_CM7_DP.h" -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/Target.clayer.yml deleted file mode 100644 index 8e3ec74..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_CMx_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/vht_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_AC6/vht_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h deleted file mode 100644 index 7584efd..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h +++ /dev/null @@ -1,50 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2016 ARM Ltd. - * - * This software is provided 'as-is', without any express or implied warranty. - * In no event will the authors be held liable for any damages arising from - * the use of this software. Permission is granted to anyone to use this - * software for any purpose, including commercial applications, and to alter - * it and redistribute it freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software. If you use this software in - * a product, an acknowledgment in the product documentation would be - * appreciated but is not required. - * - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software. - * - * 3. This notice may not be removed or altered from any source distribution. - * - * $Date: 25. April 2016 - * $Revision: V1.0.0 - * - * Project: RTE Device Configuration for ARM CMSDK_CM device - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART -#define RTE_USART0 1 - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART -#define RTE_USART1 0 - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] -// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART -#define RTE_UART2 0 - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] -// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART -#define RTE_UART3 0 - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld deleted file mode 100644 index 59bd7d1..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld +++ /dev/null @@ -1,279 +0,0 @@ -/****************************************************************************** - * @file gcc_arm.ld - * @brief GNU Linker Script for Cortex-M based device - ******************************************************************************/ - -/* -; -------- <<< Use Configuration Wizard in Context Menu >>> ------------------- - */ - -/*---------------------- Flash Configuration ---------------------------------- -; Flash Configuration -; Flash Base Address <0x0-0xFFFFFFFF:8> -; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__ROM_BASE = 0x00000000; -__ROM_SIZE = 0x00400000; - -/*--------------------- Embedded RAM Configuration ---------------------------- -; RAM Configuration -; RAM Base Address <0x0-0xFFFFFFFF:8> -; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__RAM_BASE = 0x20000000; -__RAM_SIZE = 0x00020000; - -/*--------------------- Stack / Heap Configuration ---------------------------- -; Stack / Heap Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; - -/* -; -------------------- <<< end of configuration section >>> ------------------- - */ - -MEMORY -{ - FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE - RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - /* - * SG veneers: - * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option �--section-start� or in a linker script, - * to indicate where to place these veneers in memory. - */ -/* - .gnu.sgstubs : - { - . = ALIGN(32); - } > FLASH -*/ - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG ((__bss_end__ - __bss_start__) / 4) - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; - } > FLASH - - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; - - } > RAM - - /* - * Secondary data section, optional - * - * Remember to add each additional data section - * to the .copy.table above to asure proper - * initialization during startup. - */ -/* - __etext2 = ALIGN (4); - - .data2 : AT (__etext2) - { - . = ALIGN(4); - __data2_start__ = .; - *(.data2) - *(.data2.*) - . = ALIGN(4); - __data2_end__ = .; - - } > RAM2 -*/ - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss) - *(.bss.*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM - - /* - * Secondary bss section, optional - * - * Remember to add each additional bss section - * to the .zero.table above to asure proper - * initialization during startup. - */ -/* - .bss2 : - { - . = ALIGN(4); - __bss2_start__ = .; - *(.bss2) - *(.bss2.*) - . = ALIGN(4); - __bss2_end__ = .; - } > RAM2 AT > RAM2 -*/ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c deleted file mode 100644 index 82b8c8a..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/startup_CMSDK_CM7.c +++ /dev/null @@ -1,425 +0,0 @@ -/****************************************************************************** - * @file startup_CMSDK_CM7.c - * @brief CMSIS Startup File for CMSDK_M7 Device - ******************************************************************************/ -/* Copyright (c) 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) - #include "CMSDK_CM7.h" -#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) - #include "CMSDK_CM7_SP.h" -#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) - #include "CMSDK_CM7_DP.h" -#else - #error device not specified! -#endif - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; - -extern __NO_RETURN void __PROGRAM_START(void); - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler (void); - void Default_Handler(void); - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -/* Exceptions */ -void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void HardFault_Handler (void) __attribute__ ((weak)); -void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); - -/* Interrupts */ -void UART0RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART0TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART1TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART2TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO1ALL_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TIMER1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void DUALTIMER_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART_0_1_2_OVF_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ETHERNET_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void I2S_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void TOUCHSCREEN_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART3TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4RX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void UART4TX_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void SPI_3_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void GPIO0_7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT -void ARM_VSI0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -void ARM_VSI7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); -#endif - - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - const VECTOR_TABLE_Type __VECTOR_TABLE[256] __VECTOR_TABLE_ATTRIBUTE = { - (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14 NMI Handler */ - HardFault_Handler, /* -13 Hard Fault Handler */ - MemManage_Handler, /* -12 MPU Fault Handler */ - BusFault_Handler, /* -11 Bus Fault Handler */ - UsageFault_Handler, /* -10 Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5 SVC Handler */ - DebugMon_Handler, /* -4 Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2 PendSV Handler */ - SysTick_Handler, /* -1 SysTick Handler */ - - /* Interrupts */ - UART0RX_Handler, /* 0 UART 0 receive interrupt */ - UART0TX_Handler, /* 1 UART 0 transmit interrupt */ - UART1RX_Handler, /* 2 UART 1 receive interrupt */ - UART1TX_Handler, /* 3 UART 1 transmit interrupt */ - UART2RX_Handler, /* 4 UART 2 receive interrupt */ - UART2TX_Handler, /* 5 UART 2 transmit interrupt */ - GPIO0ALL_Handler, /* 6 GPIO 0 combined interrupt */ - GPIO1ALL_Handler, /* 7 GPIO 1 combined interrupt */ - TIMER0_Handler, /* 8 Timer 0 interrupt */ - TIMER1_Handler, /* 9 Timer 1 interrupt */ - DUALTIMER_Handler, /* 10 Dual Timer interrupt */ - SPI_0_1_Handler, /* 11 SPI 0, SPI 1 interrupt */ - UART_0_1_2_OVF_Handler, /* 12 UART overflow (0, 1 & 2) interrupt */ - ETHERNET_Handler, /* 13 Ethernet interrupt */ - I2S_Handler, /* 14 Audio I2S interrupt */ - TOUCHSCREEN_Handler, /* 15 Touch Screen interrupt */ - GPIO2_Handler, /* 16 GPIO 2 combined interrupt */ - GPIO3_Handler, /* 17 GPIO 3 combined interrupt */ - UART3RX_Handler, /* 18 UART 3 receive interrupt */ - UART3TX_Handler, /* 19 UART 3 transmit interrupt */ - UART4RX_Handler, /* 20 UART 4 receive interrupt */ - UART4TX_Handler, /* 21 UART 4 transmit interrupt */ - SPI_2_Handler, /* 22 SPI 2 interrupt */ - SPI_3_4_Handler, /* 23 SPI 3, SPI 4 interrupt */ - GPIO0_0_Handler, /* 24 GPIO 0 individual interrupt ( 0) */ - GPIO0_1_Handler, /* 25 GPIO 0 individual interrupt ( 1) */ - GPIO0_2_Handler, /* 26 GPIO 0 individual interrupt ( 2) */ - GPIO0_3_Handler, /* 27 GPIO 0 individual interrupt ( 3) */ - GPIO0_4_Handler, /* 28 GPIO 0 individual interrupt ( 4) */ - GPIO0_5_Handler, /* 29 GPIO 0 individual interrupt ( 5) */ - GPIO0_6_Handler, /* 30 GPIO 0 individual interrupt ( 6) */ - GPIO0_7_Handler, /* 31 GPIO 0 individual interrupt ( 7) */ - 0, /* 32 Reserved */ - 0, /* 33 Reserved */ - 0, /* 34 Reserved */ - 0, /* 35 Reserved */ - 0, /* 36 Reserved */ - 0, /* 37 Reserved */ - 0, /* 38 Reserved */ - 0, /* 39 Reserved */ - 0, /* 40 Reserved */ - 0, /* 41 Reserved */ - 0, /* 42 Reserved */ - 0, /* 43 Reserved */ - 0, /* 44 Reserved */ - 0, /* 45 Reserved */ - 0, /* 46 Reserved */ - 0, /* 47 Reserved */ - 0, /* 48 Reserved */ - 0, /* 49 Reserved */ - 0, /* 50 Reserved */ - 0, /* 51 Reserved */ - 0, /* 52 Reserved */ - 0, /* 53 Reserved */ - 0, /* 54 Reserved */ - 0, /* 55 Reserved */ - 0, /* 56 Reserved */ - 0, /* 57 Reserved */ - 0, /* 58 Reserved */ - 0, /* 59 Reserved */ - 0, /* 60 Reserved */ - 0, /* 61 Reserved */ - 0, /* 62 Reserved */ - 0, /* 63 Reserved */ - 0, /* 64 Reserved */ - 0, /* 65 Reserved */ - 0, /* 66 Reserved */ - 0, /* 67 Reserved */ - 0, /* 68 Reserved */ - 0, /* 69 Reserved */ - 0, /* 70 Reserved */ - 0, /* 71 Reserved */ - 0, /* 72 Reserved */ - 0, /* 73 Reserved */ - 0, /* 74 Reserved */ - 0, /* 75 Reserved */ - 0, /* 76 Reserved */ - 0, /* 77 Reserved */ - 0, /* 78 Reserved */ - 0, /* 79 Reserved */ - 0, /* 80 Reserved */ - 0, /* 81 Reserved */ - 0, /* 82 Reserved */ - 0, /* 83 Reserved */ - 0, /* 84 Reserved */ - 0, /* 85 Reserved */ - 0, /* 86 Reserved */ - 0, /* 87 Reserved */ - 0, /* 88 Reserved */ - 0, /* 89 Reserved */ - 0, /* 90 Reserved */ - 0, /* 91 Reserved */ - 0, /* 92 Reserved */ - 0, /* 93 Reserved */ - 0, /* 94 Reserved */ - 0, /* 95 Reserved */ - 0, /* 96 Reserved */ - 0, /* 97 Reserved */ - 0, /* 98 Reserved */ - 0, /* 99 Reserved */ - 0, /* 100 Reserved */ - 0, /* 101 Reserved */ - 0, /* 102 Reserved */ - 0, /* 103 Reserved */ - 0, /* 104 Reserved */ - 0, /* 105 Reserved */ - 0, /* 106 Reserved */ - 0, /* 107 Reserved */ - 0, /* 108 Reserved */ - 0, /* 109 Reserved */ - 0, /* 110 Reserved */ - 0, /* 111 Reserved */ - 0, /* 112 Reserved */ - 0, /* 113 Reserved */ - 0, /* 114 Reserved */ - 0, /* 115 Reserved */ - 0, /* 116 Reserved */ - 0, /* 117 Reserved */ - 0, /* 118 Reserved */ - 0, /* 119 Reserved */ - 0, /* 120 Reserved */ - 0, /* 121 Reserved */ - 0, /* 122 Reserved */ - 0, /* 123 Reserved */ - 0, /* 124 Reserved */ - 0, /* 125 Reserved */ - 0, /* 126 Reserved */ - 0, /* 127 Reserved */ - 0, /* 128 Reserved */ - 0, /* 129 Reserved */ - 0, /* 130 Reserved */ - 0, /* 131 Reserved */ - 0, /* 132 Reserved */ - 0, /* 133 Reserved */ - 0, /* 134 Reserved */ - 0, /* 135 Reserved */ - 0, /* 136 Reserved */ - 0, /* 137 Reserved */ - 0, /* 138 Reserved */ - 0, /* 139 Reserved */ - 0, /* 140 Reserved */ - 0, /* 141 Reserved */ - 0, /* 142 Reserved */ - 0, /* 143 Reserved */ - 0, /* 144 Reserved */ - 0, /* 145 Reserved */ - 0, /* 146 Reserved */ - 0, /* 147 Reserved */ - 0, /* 148 Reserved */ - 0, /* 149 Reserved */ - 0, /* 150 Reserved */ - 0, /* 151 Reserved */ - 0, /* 152 Reserved */ - 0, /* 153 Reserved */ - 0, /* 154 Reserved */ - 0, /* 155 Reserved */ - 0, /* 156 Reserved */ - 0, /* 157 Reserved */ - 0, /* 158 Reserved */ - 0, /* 159 Reserved */ - 0, /* 160 Reserved */ - 0, /* 161 Reserved */ - 0, /* 162 Reserved */ - 0, /* 163 Reserved */ - 0, /* 164 Reserved */ - 0, /* 165 Reserved */ - 0, /* 166 Reserved */ - 0, /* 167 Reserved */ - 0, /* 168 Reserved */ - 0, /* 169 Reserved */ - 0, /* 170 Reserved */ - 0, /* 171 Reserved */ - 0, /* 172 Reserved */ - 0, /* 173 Reserved */ - 0, /* 174 Reserved */ - 0, /* 175 Reserved */ - 0, /* 176 Reserved */ - 0, /* 177 Reserved */ - 0, /* 178 Reserved */ - 0, /* 179 Reserved */ - 0, /* 180 Reserved */ - 0, /* 181 Reserved */ - 0, /* 182 Reserved */ - 0, /* 183 Reserved */ - 0, /* 184 Reserved */ - 0, /* 185 Reserved */ - 0, /* 186 Reserved */ - 0, /* 187 Reserved */ - 0, /* 188 Reserved */ - 0, /* 189 Reserved */ - 0, /* 190 Reserved */ - 0, /* 191 Reserved */ - 0, /* 192 Reserved */ - 0, /* 193 Reserved */ - 0, /* 194 Reserved */ - 0, /* 195 Reserved */ - 0, /* 196 Reserved */ - 0, /* 197 Reserved */ - 0, /* 198 Reserved */ - 0, /* 199 Reserved */ - 0, /* 200 Reserved */ - 0, /* 201 Reserved */ - 0, /* 202 Reserved */ - 0, /* 203 Reserved */ - 0, /* 204 Reserved */ - 0, /* 205 Reserved */ - 0, /* 206 Reserved */ - 0, /* 207 Reserved */ - 0, /* 208 Reserved */ - 0, /* 209 Reserved */ - 0, /* 210 Reserved */ - 0, /* 211 Reserved */ - 0, /* 212 Reserved */ - 0, /* 213 Reserved */ - 0, /* 214 Reserved */ - 0, /* 215 Reserved */ - 0, /* 216 Reserved */ - 0, /* 217 Reserved */ - 0, /* 218 Reserved */ - 0, /* 219 Reserved */ - 0, /* 220 Reserved */ - 0, /* 221 Reserved */ - 0, /* 222 Reserved */ - 0, /* 223 Reserved */ -#if defined CMSDK_CM7_VHT || defined CMSDK_CM7_SP_VHT || defined CMSDK_CM7_DP_VHT - ARM_VSI0_Handler, /* 224 VSI 0 interrupt */ - ARM_VSI1_Handler, /* 225 VSI 1 interrupt */ - ARM_VSI2_Handler, /* 226 VSI 2 interrupt */ - ARM_VSI3_Handler, /* 227 VSI 3 interrupt */ - ARM_VSI4_Handler, /* 228 VSI 4 interrupt */ - ARM_VSI5_Handler, /* 229 VSI 5 interrupt */ - ARM_VSI6_Handler, /* 230 VSI 6 interrupt */ - ARM_VSI7_Handler /* 231 VSI 7 interrupt */ -#else - 0, /* 224 Reserved */ - 0, /* 225 Reserved */ - 0, /* 226 Reserved */ - 0, /* 227 Reserved */ - 0, /* 228 Reserved */ - 0, /* 229 Reserved */ - 0, /* 230 Reserved */ - 0 /* 231 Reserved */ -#endif -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -__NO_RETURN void Reset_Handler(void) -{ - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wmissing-noreturn" -#endif - -/*---------------------------------------------------------------------------- - Hard Fault Handler - *----------------------------------------------------------------------------*/ -void HardFault_Handler(void) -{ - while(1); -} - -/*---------------------------------------------------------------------------- - Default Handler for Exceptions / Interrupts - *----------------------------------------------------------------------------*/ -void Default_Handler(void) -{ - while(1); -} - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#endif diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c deleted file mode 100644 index fdfec7a..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/RTE/Device/CMSDK_CM7_SP_VHT/system_CMSDK_CM7.c +++ /dev/null @@ -1,87 +0,0 @@ -/****************************************************************************** - * @file system_CMSDK_CM7.c - * @brief CMSIS System Source File for CMSDK_CM7 Device - ******************************************************************************/ -/* Copyright (c) 2011 - 2022 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#if defined (CMSDK_CM7) || defined (CMSDK_CM7_VHT) - #include "CMSDK_CM7.h" -#elif defined (CMSDK_CM7_SP) || defined (CMSDK_CM7_SP_VHT) - #include "CMSDK_CM7_SP.h" -#elif defined (CMSDK_CM7_DP) || defined (CMSDK_CM7_DP_VHT) - #include "CMSDK_CM7_DP.h" -#else - #error device not specified! -#endif - - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define XTAL (50000000UL) /* Oscillator frequency */ - -#define SYSTEM_CLOCK (XTAL / 2U) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ -extern const VECTOR_TABLE_Type __VECTOR_TABLE[256]; - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); -#endif - -#if defined (__FPU_USED) && (__FPU_USED == 1U) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - SystemCoreClock = SYSTEM_CLOCK; -} diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/Target.clayer.yml b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/Target.clayer.yml deleted file mode 100644 index 8e3ec74..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/Target.clayer.yml +++ /dev/null @@ -1,22 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Target - description: Target setup - - # packs: - # - pack: ARM::CMSIS - # - pack: Keil::V2M-MPS2_CMx_BSP - - components: - # [Cvendor::] Cclass [&Cbundle] :Cgroup [:Csub] [&Cvariant] [@[>=]Cversion] - - component: ARM::CMSIS:CORE - - component: Device:Startup&C Startup - - - component: Keil::Board Support&V2M-MPS2:Common - - component: Keil::CMSIS Driver:USART - - groups: - - group: VHT - files: - - file: ./vht_config.txt diff --git a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/vht_config.txt b/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/vht_config.txt deleted file mode 100644 index b7f12f3..0000000 --- a/tensorflow-test-ng/Layer/Target/CM7_SP_VHT_GCC/vht_config.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output -fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -#------------------------------------------------------------------------------ diff --git a/tensorflow-test-ng/Layer/Test/Test.clayer.yml b/tensorflow-test-ng/Layer/Test/Test.clayer.yml deleted file mode 100644 index be92a23..0000000 --- a/tensorflow-test-ng/Layer/Test/Test.clayer.yml +++ /dev/null @@ -1,23 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.1/tools/projmgr/schemas/clayer.schema.json - -layer: - # type: Test - # name: Tensorflow test sources - description: Validation of TensorFlow Lite Micro specific unit test - - #add-paths: - # - ../../../Include - - components: - - component: tensorflow::Machine Learning:TensorFlow:Kernel Utils - - component: tensorflow::Machine Learning:TensorFlow:Testing - - component: tensorflow::Data Exchange:Serialization:flatbuffers&tensorflow - - component: tensorflow::Data Processing:Math:gemmlowp fixed-point&tensorflow - - component: tensorflow::Data Processing:Math:kissfft&tensorflow - - component: tensorflow::Data Processing:Math:ruy&tensorflow - - groups: - - - group: Unit Test Source files - files: - <-- test_src_files --> diff --git a/tensorflow-test-ng/Project/Validation.cproject.yml b/tensorflow-test-ng/Project/Validation.cproject.yml deleted file mode 100644 index 6cdd5ef..0000000 --- a/tensorflow-test-ng/Project/Validation.cproject.yml +++ /dev/null @@ -1,91 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.2/tools/projmgr/schemas/cproject.schema.json - -project: - layers: - # App: Validation for Reference - - layer: ./Test.clayer.yml - - layer: ../../Layer/App/Validation_Reference/App.clayer.yml - for-type: - - .Reference_AC6 - - .Reference_GC - # App: CMSIS-RTOS2 Validation for FreeRTOS - - layer: ../../Layer/App/Validation_CMSIS-NN/App.clayer.yml - for-type: - - .CMSIS-NN_AC6 - - .CMSIS-NN_GCC - - #Target: CM0plus - - layer: ../../Layer/Target/CM0plus_VHT_AC6/Target.clayer.yml - for-type: - - .Reference_AC6+CM0plus - - .CMSIS-NN_AC6+CM0plus - - layer: ../../Layer/Target/CM0plus_VHT_GCC/Target.clayer.yml - for-type: - - .Reference_GC+CM0plus - - .CMSIS-NN_GCC+CM0plus - - #Target: CM3 - - layer: ../../Layer/Target/CM3_VHT_AC6/Target.clayer.yml - for-type: - - .Reference_AC6+CM3 - - .CMSIS-NN_AC6+CM3 - - layer: ../../Layer/Target/CM3_VHT_GCC/Target.clayer.yml - for-type: - - .Reference_GC+CM3 - - .CMSIS-NN_GCC+CM3 - - #Target: CM4_FP - - layer: ../../Layer/Target/CM4_FP_VHT_AC6/Target.clayer.yml - for-type: - - .Reference_AC6+CM4_FP - - .CMSIS-NN_AC6+CM4_FP - - layer: ../../Layer/Target/CM4_FP_VHT_GCC/Target.clayer.yml - for-type: - - .Reference_GC+CM4_FP - - .CMSIS-NN_GCC+CM4_FP - - #Target: CM7_DP - - layer: ../../Layer/Target/CM7_DP_VHT_AC6/Target.clayer.yml - for-type: - - .Reference_AC6+CM7_DP - - .CMSIS-NN_AC6+CM7_DP - - layer: ../../Layer/Target/CM7_DP_VHT_GCC/Target.clayer.yml - for-type: - - .Reference_GC+CM7_DP - - .CMSIS-NN_GCC+CM7_DP - - #Target: CM7_SP - - layer: ../../Layer/Target/CM7_SP_VHT_AC6/Target.clayer.yml - for-type: - - .Reference_AC6+CM7_SP - - .CMSIS-NN_AC6+CM7_SP - - layer: ../../Layer/Target/CM7_SP_VHT_GCC/Target.clayer.yml - for-type: - - .Reference_GC+CM7_SP - - .CMSIS-NN_GCC+CM7_SP - - #Target: CM23 - - layer: ../../Layer/Target/CM23_VHT_AC6/Target.clayer.yml - for-type: - - .Reference_AC6+CM23 - - .CMSIS-NN_AC6+CM23 - - layer: ../../Layer/Target/CM23_VHT_GCC/Target.clayer.yml - for-type: - - .Reference_GC+CM23 - - .CMSIS-NN_GCC+CM23 - - #Target: CM33_FP - - layer: ../../Layer/Target/CM33_FP_VHT_AC6/Target.clayer.yml - for-type: - - .Reference_AC6+CM33_FP - - .CMSIS-NN_AC6+CM33_FP - - layer: ../../Layer/Target/CM33_FP_VHT_GCC/Target.clayer.yml - for-type: - - .Reference_GC+CM33_FP - - .CMSIS-NN_GCC+CM33_FP - - #Target: CM55 - - layer: ../../Layer/Target/CM55_VHT_AC6/Target.clayer.yml - for-type: - - .Reference_AC6+CM55 - - .CMSIS-NN_AC6+CM55 diff --git a/tensorflow-test-ng/Project/Validation.csolution.yml b/tensorflow-test-ng/Project/Validation.csolution.yml deleted file mode 100644 index 7e1bb29..0000000 --- a/tensorflow-test-ng/Project/Validation.csolution.yml +++ /dev/null @@ -1,172 +0,0 @@ -# yaml-language-server: $schema=https://raw.githubusercontent.com/Open-CMSIS-Pack/devtools/schemas/projmgr/0.9.2/tools/projmgr/schemas/csolution.schema.json - -solution: - packs: - - pack: ARM::CMSIS@5.9.0 - - pack: tensorflow::tensorflow-lite-micro - - pack: tensorflow::flatbuffers - - pack: tensorflow::ruy - - pack: tensorflow::kissfft - - pack: tensorflow::gemmlowp - - pack: Keil::V2M-MPS2_CMx_BSP@1.8.0 - for-type: - - +CM0plus - - +CM3 - - +CM4_FP - - +CM7_DP - - +CM7_SP - - pack: Keil::V2M-MPS2_IOTKit_BSP@1.5.0 - for-type: - - +CM23 - - +CM33_FP - - pack: ARM::V2M_MPS3_SSE_300_BSP@1.3.0 - for-type: - - +CM55 - - target-types: -# #CM0plus -# - type: CM0plus -# device: CMSDK_CM0plus_VHT -# defines: -# - TST_IRQ_HANDLER_A=TIMER0_Handler -# - TST_IRQ_NUM_A=8 -# - TST_IRQ_HANDLER_B=TIMER1_Handler -# - TST_IRQ_NUM_B=9 -# #CM3 -# - type: CM3 -# device: CMSDK_CM3_VHT -# defines: -# - TST_IRQ_HANDLER_A=TIMER0_Handler -# - TST_IRQ_NUM_A=8 -# - TST_IRQ_HANDLER_B=TIMER1_Handler -# - TST_IRQ_NUM_B=9 -# #CM4_FP -# - type: CM4_FP -# device: CMSDK_CM4_FP_VHT -# defines: -# - TST_IRQ_HANDLER_A=TIMER0_Handler -# - TST_IRQ_NUM_A=8 -# - TST_IRQ_HANDLER_B=TIMER1_Handler -# - TST_IRQ_NUM_B=9 -# misc: -# - compiler: AC6 -# C: [-mfloat-abi=hard, -mfpu=fpv4-sp-d16] -# ASM: [-mfloat-abi=hard, -mfpu=fpv4-sp-d16] -# -# - compiler: GCC -# C: [-mfloat-abi=hard, -mfpu=auto] -# ASM: [-mfloat-abi=hard, -mfpu=auto] -# Link: [-mfloat-abi=hard] -# #CM7_DP -# - type: CM7_DP -# device: CMSDK_CM7_DP_VHT -# defines: -# - TST_IRQ_HANDLER_A=TIMER0_Handler -# - TST_IRQ_NUM_A=8 -# - TST_IRQ_HANDLER_B=TIMER1_Handler -# - TST_IRQ_NUM_B=9 -# misc: -# - compiler: AC6 -# C: [-mfloat-abi=hard, -mfpu=fpv5-d16] -# ASM: [-mfloat-abi=hard, -mfpu=fpv5-d16] -# -# - compiler: GCC -# C: [-mfloat-abi=hard, -mfpu=auto] -# ASM: [-mfloat-abi=hard, -mfpu=auto] -# Link: [-mfloat-abi=hard] -# #CM7_SP -# - type: CM7_SP -# device: CMSDK_CM7_SP_VHT -# defines: -# - TST_IRQ_HANDLER_A=TIMER0_Handler -# - TST_IRQ_NUM_A=8 -# - TST_IRQ_HANDLER_B=TIMER1_Handler -# - TST_IRQ_NUM_B=9 -# misc: -# - compiler: AC6 -# C: [-mfloat-abi=hard, -mfpu=fpv5-sp-d16] -# ASM: [-mfloat-abi=hard, -mfpu=fpv5-sp-d16] -# -# - compiler: GCC -# C: [-mfloat-abi=hard, -mfpu=auto] -# ASM: [-mfloat-abi=hard, -mfpu=auto] -# Link: [-mfloat-abi=hard] -# #CM23 -# - type: CM23 -# device: IOTKit_CM23_VHT -# defines: -# - TST_IRQ_HANDLER_A=NONSEC_WATCHDOG_RESET_Handler -# - TST_IRQ_NUM_A=0 -# - TST_IRQ_HANDLER_B=NONSEC_WATCHDOG_Handler -# - TST_IRQ_NUM_B=1 -# - configENABLE_FPU=0 -# misc: -# - compiler: AC6 -# C: [-mcmse] -# ASM: [-mcmse] -# -# - compiler: GCC -# C: [-mfloat-abi=soft, -mfpu=auto] -# ASM: [-mfloat-abi=soft, -mfpu=auto] -# Link: [-mfloat-abi=soft] -# #CM33_FP -# - type: CM33_FP -# device: IOTKit_CM33_FP_VHT -# defines: -# - TST_IRQ_HANDLER_A=NONSEC_WATCHDOG_RESET_Handler -# - TST_IRQ_NUM_A=0 -# - TST_IRQ_HANDLER_B=NONSEC_WATCHDOG_Handler -# - TST_IRQ_NUM_B=1 -# misc: -# - compiler: AC6 -# C: [-mfloat-abi=hard, -mfpu=fpv5-sp-d16, -mcmse] -# ASM: [-mfloat-abi=hard, -mfpu=fpv5-sp-d16, -mcmse] -# -# - compiler: GCC -# C: [-mfloat-abi=hard, -mfpu=auto] -# ASM: [-mfloat-abi=hard, -mfpu=auto] -# Link: [-mfloat-abi=hard] - #CM55 - - type: CM55 - device: SSE-300-MPS3 - defines: - - TST_IRQ_HANDLER_A=NONSEC_WATCHDOG_RESET_Handler - - TST_IRQ_NUM_A=0 - - TST_IRQ_HANDLER_B=NONSEC_WATCHDOG_Handler - - TST_IRQ_NUM_B=1 - misc: - - compiler: AC6 - C: [-mfloat-abi=hard, -mcmse] - ASM: [-mfloat-abi=hard, -mcmse] - - build-types: - - type: Reference_AC6 - compiler: AC6 - misc: - - compiler: AC6 - C: [-Os, -std=c99, -gdwarf-4, -ffunction-sections] - Link: [--entry=Reset_Handler] - - - type: Reference_GCC - compiler: GCC - misc: - - compiler: GCC - C: [-Os, -std=gnu99, -mapcs-frame, -mthumb-interwork] - Link: [-lm, -specs=nosys.specs, --entry=Reset_Handler] - - - type: CMSIS-NN_AC6 - compiler: AC6 - misc: - - compiler: AC6 - C: [-Os, -std=c99, -gdwarf-4, -ffunction-sections] - Link: [--entry=Reset_Handler] - - - type: CMSIS-NN_GCC - compiler: GCC - misc: - - compiler: GCC - C: [-Os, -std=gnu99, -mapcs-frame, -mthumb-interwork, -masm-syntax-unified] - Link: [-lm, -specs=nosys.specs, --entry=Reset_Handler] - - projects: - - project: ./Validation.cproject.yml diff --git a/tensorflow-test-ng/avh.yml b/tensorflow-test-ng/avh.yml deleted file mode 100644 index 5d26eca..0000000 --- a/tensorflow-test-ng/avh.yml +++ /dev/null @@ -1,49 +0,0 @@ -name: "TensorFlow Lite Micro Unit tests" -workdir: ./ -backend: - aws: - ami-version: ==1.2.3 - instance-type: c5.4xlarge -upload: - - packs/**/* - - Layer/**/* - - Project/**/* - - Source/**/* - - avh_exec_test.py - - exec_suite.sh - - record_test_results.py - -steps: - - run: | - sudo wget https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 - sudo tar -xvf gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 - sudo mv gcc-arm-none-eabi-10-2020-q4-major /opt/gcc-arm-none-eabi-10-2020-q4-major - sudo ln -s /opt/gcc-arm-none-eabi-10-2020-q4-major/bin/arm-none-eabi-gcc /usr/bin/arm-none-eabi-gcc - wget https://github.com/Open-CMSIS-Pack/devtools/releases/download/tools%2Ftoolbox%2F1.0.0/cmsis-toolbox.sh - chmod +x cmsis-toolbox.sh - sudo ./cmsis-toolbox.sh </dev/null)) - $(dirname $(which armcc 2>/dev/null)) - /opt/gcc-arm-none-eabi-10-2020-q4-major/bin - - EOI - source /opt/ctools/etc/setup - cpackget -v init --pack-root /home/ubuntu/packs https://www.keil.com/pack/index.pidx - cpackget pack add tensorflow.tensorflow-lite-micro.1.22.5-rc4 -a - cpackget pack add tensorflow.flatbuffers.1.22.5-rc4 -a - cpackget pack add tensorflow.ruy.1.22.5-rc4 -a - cpackget pack add tensorflow.gemmlowp.1.22.5-rc4 -a - cpackget pack add tensorflow.kissfft.1.22.5-rc4 -a - cpackget pack add Keil.V2M-MPS2_CMx_BSP.1.8.0 -a - cpackget pack add Keil.V2M-IOTKit_BSP.1.5.0 -a - cpackget pack add Keil.V2M-MPS2_IOTKit_BSP.1.5.0 -a - cpackget pack add ARM.V2M_MPS3_SSE_300_BSP.1.3.0 -a - - ./exec_suite.sh > test_results.log 2>&1 - -download: - - test_results.log - - diff --git a/tensorflow-test-ng/avh_exec_test.py b/tensorflow-test-ng/avh_exec_test.py deleted file mode 100644 index 4843807..0000000 --- a/tensorflow-test-ng/avh_exec_test.py +++ /dev/null @@ -1,56 +0,0 @@ - -import argparse -import os -import sys -import xml.etree.ElementTree as ET - -vhtdict = { - "CMSDK_CM0plus_VHT": "VHT_MPS2_Cortex-M0plus", - "CMSDK_CM3_VHT" : "VHT_MPS2_Cortex-M3", - "CMSDK_CM4_FP_VHT" : "VHT_MPS2_Cortex-M4", - "CMSDK_CM7_DP_VHT" : "VHT_MPS2_Cortex-M7", - "CMSDK_CM7_SP_VHT" : "VHT_MPS2_Cortex-M7", - "IOTKit_CM23_VHT" : "VHT_MPS2_Cortex-M23", - "IOTKit_CM33_FP_VHT" : "VHT_MPS2_Cortex-M33", - "SSE-300-MPS3" : "VHT_MPS3_Corstone_SSE-300" -} -def main(): -#get argument from command line - parser = argparse.ArgumentParser( - description="Execute a test package on the correct VHT.") - # add the --project option - parser.add_argument("--project", type=str, default=os.path.curdir, - help="CPRJ with test") - - # Check if path in --project exists - if not os.path.exists(parser.parse_args().project): - print("Path " + parser.parse_args().project + " does not exist") - sys.exit(1) - # print --project - print("Working on project: " + parser.parse_args().project) - basepath = "./" + os.path.dirname(parser.parse_args().project) - # Open CPRJ file as XML file - tree = ET.parse(parser.parse_args().project) - root = tree.getroot() - #retrieve output path - output_xml = root.findall('./target/output')[0] - executable_name = output_xml.get('name') - output_path = os.path.join(basepath, output_xml.get('outdir')) - compiler_xml = root.findall('./compilers/compiler')[0] - compiler = compiler_xml.get('name') - if compiler == "AC6": - executable_name += ".axf" - else: - executable_name += ".elf" - print(executable_name) - # Check if outpath exists - if not os.path.exists(output_path): - print("Path " + output_path + " does not exist") - # sys.exit(1) - target_xml = root.findall('./target')[0] - device_name = target_xml.get('Dname') - print(device_name, "executed on ", vhtdict[device_name]) - os.system(vhtdict[device_name] + " --timelimit=2 -a " + output_path + "/" + executable_name) - -if __name__ == '__main__': - main() diff --git a/tensorflow-test-ng/copy_sources.py b/tensorflow-test-ng/copy_sources.py deleted file mode 100644 index b310647..0000000 --- a/tensorflow-test-ng/copy_sources.py +++ /dev/null @@ -1,80 +0,0 @@ - -import os -import sys -import subprocess -import datetime -import argparse -import shutil -from time import perf_counter -import yaml -import re -import six - -# get the datetime, when the script got started -datetime_string = datetime.datetime.now().strftime("%Y-%m-%d_%H-%M-%S") -# get the script's directory, where template and work folders are located / created -test_on_arm_base = os.path.dirname(os.path.abspath(sys.argv[0])) - -last_stderr = "" -last_stdout = "" - - -def main(): - test_error = 0 - # create the argument parser - parser = argparse.ArgumentParser( - description="Copy test sources from tensorflow repo to sources in test package.") - # add the --tflm_path option - parser.add_argument("--tflm_path", type=str, default=os.path.curdir, - help="path, basepath for sources from inventory") - parser.add_argument("--out_path", type=str, default=os.path.curdir, - help="path, output path for sources from inventory") - parser.add_argument("--inventory", type=str, default="", - help="yml file with a list of tests and sources for complex tests") - - # Check if path in --tflm_path exists - if not os.path.exists(parser.parse_args().tflm_path): - print("Path " + parser.parse_args().tflm_path + " does not exist") - sys.exit(1) - # print --tflm_path - print("Working on tflm_path: " + parser.parse_args().tflm_path) - - # Check if path in --out_path exists - if not os.path.exists(parser.parse_args().out_path): - print("Path " + parser.parse_args().out_path + " does not exist") - sys.exit(1) - # print --out_path - print("Working on out_path: " + parser.parse_args().out_path) - - # Check if inventory file exists - if not os.path.exists(parser.parse_args().inventory): - print("File " + parser.parse_args().inventory + " does not exist") - sys.exit(1) - # print --inventory - print("Working on inventory: " + parser.parse_args().inventory) - - # Read inventory file - with open(parser.parse_args().inventory, 'r') as stream: - inventory = yaml.safe_load(stream) - - if inventory: - for key, value in inventory.items(): - print(">>>TEST Test Suite: ", value['readable']) - for test in value['tests']: - testname = [key for key in test.keys()][0] - #cproj_file_name = create_cproj(cvariant, toolchain, test_device, test['sources'], testname, tflm_path) - print(testname) - for src in test['sources']: - src_path = os.path.join(parser.parse_args().tflm_path, src) - dst_path = os.path.join(parser.parse_args().out_path, src) - if os.path.exists(src_path): - #replace extension from .cc to .cpp - if src_path.endswith(".cc"): - dst_path = dst_path.replace(".cc", ".cpp") - print(src_path, " ==> " , dst_path) - os.makedirs(os.path.dirname(dst_path), exist_ok=True) - shutil.copy(src_path, dst_path) - - -if __name__ == '__main__': - main() diff --git a/tensorflow-test-ng/create_tests.py b/tensorflow-test-ng/create_tests.py deleted file mode 100644 index 847d909..0000000 --- a/tensorflow-test-ng/create_tests.py +++ /dev/null @@ -1,98 +0,0 @@ - -import os -import sys -import subprocess -import datetime -import argparse -import shutil -from time import perf_counter -import yaml -import re -import six - -# get the datetime, when the script got started -datetime_string = datetime.datetime.now().strftime("%Y-%m-%d_%H-%M-%S") -# get the script's directory, where template and work folders are located / created -test_on_arm_base = os.path.dirname(os.path.abspath(sys.argv[0])) - -last_stderr = "" -last_stdout = "" - -def sanitize_xml(unsanitized): - """Uses a whitelist to avoid generating bad XML.""" - return re.sub(r'[^a-zA-Z0-9+_\-/\\.]', '', six.ensure_str(unsanitized)) - - -def write_file_list (file_list, file_name): - with open(file_name) as f: - s = f.read() - if "<-- test_src_files -->" not in s: - print('Error when writing Test.clayer.yml') - return - with open(file_name, 'w') as f: - print('Writing Test.clayer.yml') - s = s.replace("<-- test_src_files -->", file_list) - f.write(s) - -def make_file_list(base_path ,srcs_list): - replace_srcs = '' - srcs_list = set(srcs_list) - for src in srcs_list: - if not src: - continue - clean_src = sanitize_xml(os.path.join(base_path,src)) - #replace extension .cc with .cpp - if clean_src.endswith(".cc"): - clean_src = clean_src.replace(".cc", ".cpp") - replace_srcs += ' - file: ' + clean_src + ' \n' - return replace_srcs - -def main(): - test_error = 0 - # create the argument parser - parser = argparse.ArgumentParser( - description="Run tensorflow-lite-micro tests on Arm VFPs.") - parser.add_argument("--out_path", type=str, default=os.path.curdir, - help="path, output path for sources from inventory") - parser.add_argument("--inventory", type=str, default="", - help="yml file with a list of tests and sources for complex tests") - - - # Check if path in --out_path exists - if not os.path.exists(parser.parse_args().out_path): - print("Path " + parser.parse_args().out_path + " does not exist") - sys.exit(1) - # print --out_path - print("Working on out_path: " + parser.parse_args().out_path) - - # Check if inventory file exists - if not os.path.exists(parser.parse_args().inventory): - print("File " + parser.parse_args().inventory + " does not exist") - sys.exit(1) - # print --inventory - print("Working on inventory: " + parser.parse_args().inventory) - - # Read inventory file - with open(parser.parse_args().inventory, 'r') as stream: - inventory = yaml.safe_load(stream) - - if inventory: - for key, value in inventory.items(): - print(">>>TEST Test Suite: ", value['readable']) - for test in value['tests']: - testname = [key for key in test.keys()][0] - #cproj_file_name = create_cproj(cvariant, toolchain, test_device, test['sources'], testname, tflm_path) - print(testname) - src_yml = make_file_list("../../Source/", test['sources']) - test_dir = os.path.join(parser.parse_args().out_path, testname) - #create directory for test in out_path - os.makedirs(test_dir, exist_ok=True) - shutil.copy(os.path.dirname(__file__)+"/Project/Validation.cproject.yml", test_dir) - shutil.copy(os.path.dirname(__file__)+"/Project/Validation.csolution.yml", test_dir) - shutil.copy(os.path.dirname(__file__)+"/Layer/Test/Test.clayer.yml", test_dir) - # replace string in Test.clayer.yml - write_file_list(src_yml, os.path.join(test_dir, "Test.clayer.yml")) - - -if __name__ == '__main__': - main() diff --git a/tensorflow-test-ng/exec_suite.sh b/tensorflow-test-ng/exec_suite.sh deleted file mode 100755 index 7d323a7..0000000 --- a/tensorflow-test-ng/exec_suite.sh +++ /dev/null @@ -1,24 +0,0 @@ -#!/bin/sh - -# Iterate through all folders in ./gen -# and generate test projects -for folder in ./gen/*; do - # increment counter - echo Package $folder - # Generate test project - csolution convert -n -s $folder/Validation.csolution.yml -o $folder/ -done - -for folder in ./gen/*; do - for target in $folder/*; do - #find .cprj file in target folder - cprj_file=$(find $target -name "*.cprj") - #if cprj file exists - if [ -f "$cprj_file" ]; then - echo "Building: " $cprj_file - cbuild $cprj_file #> $target/build.log - python3 avh_exec_test.py --project=$cprj_file > $target/test_result.log - python3 record_test_results.py --results=$target/test_result.log - fi - done -done diff --git a/tensorflow-test-ng/export_test_report.py b/tensorflow-test-ng/export_test_report.py deleted file mode 100644 index fe66870..0000000 --- a/tensorflow-test-ng/export_test_report.py +++ /dev/null @@ -1,36 +0,0 @@ -import sqlite3 -import argparse -import os - -def main(): - test_error = 0 - # create the argument parser - parser = argparse.ArgumentParser( - description="Export various test report files from test results SQLite database.") - parser.add_argument("--out_path", type=str, default=os.path.curdir, - help="path, output path for reports") - parser.add_argument("--report", type=str, default="test_results.db", - help="yml file with a list of tests and sources for complex tests") - - # Check if path in --out_path exists - if not os.path.exists(parser.parse_args().out_path): - print("Path " + parser.parse_args().out_path + " does not exist") - sys.exit(1) - - # Check if report file exists - if not os.path.exists(parser.parse_args().report): - print("File " + parser.parse_args().report + " does not exist") - sys.exit(1) - - # Read report file as SQLite database - conn = sqlite3.connect(parser.parse_args().report) - c = conn.cursor() - c.execute("SELECT * FROM results WHERE testname = 'ALL_TESTS'") - test_results = c.fetchall() - conn.close() - print(test_results) - - - -if __name__ == '__main__': - main() diff --git a/tensorflow-test-ng/generic_tests.yml b/tensorflow-test-ng/generic_tests.yml deleted file mode 100644 index 8b61eea..0000000 --- a/tensorflow-test-ng/generic_tests.yml +++ /dev/null @@ -1,44 +0,0 @@ -generic_tests: - readable: "Generic Components Unit Tests" - report: generic.junit - tests: - - memory_arena_threshold_test: - sources: - - tensorflow/lite/micro/memory_arena_threshold_test.cc - - tensorflow/lite/micro/benchmarks/keyword_scrambled_model_data.cc - - tensorflow/lite/micro/testing/test_conv_model.cc - - memory_helpers_test: - sources: - - tensorflow/lite/micro/memory_helpers_test.cc - - micro_allocator_test: - sources: - - tensorflow/lite/micro/micro_allocator_test.cc - - tensorflow/lite/micro/testing/test_conv_model.cc - - micro_error_reporter_test: - sources: - - tensorflow/lite/micro/micro_error_reporter_test.cc - - micro_interpreter_test: - sources: - - tensorflow/lite/micro/micro_interpreter_test.cc - - micro_mutable_op_resolver_test: - sources: - - tensorflow/lite/micro/micro_mutable_op_resolver_test.cc - - micro_string_test: - sources: - - tensorflow/lite/micro/micro_string_test.cc - - micro_time_test: - sources: - - tensorflow/lite/micro/micro_time_test.cc - - micro_utils_test: - sources: - - tensorflow/lite/micro/micro_utils_test.cc - - recording_micro_allocator_test: - sources: - - tensorflow/lite/micro/recording_micro_allocator_test.cc - - tensorflow/lite/micro/testing/test_conv_model.cc - - recording_simple_memory_allocator_test: - sources: - - tensorflow/lite/micro/recording_simple_memory_allocator_test.cc - - simple_memory_allocator_test: - sources: - - tensorflow/lite/micro/simple_memory_allocator_test.cc diff --git a/tensorflow-test-ng/kernel_tests_cmsis.yml b/tensorflow-test-ng/kernel_tests_cmsis.yml deleted file mode 100644 index 00f5354..0000000 --- a/tensorflow-test-ng/kernel_tests_cmsis.yml +++ /dev/null @@ -1,203 +0,0 @@ -kernel_unit_tests: - readable: "Kernel Unit Tests - CMSIS-NN" - report: kernel.cmsisnn.junit - tests: - - activations_test: - sources: - - tensorflow/lite/micro/kernels/activations_test.cc - - add_test: - sources: - - tensorflow/lite/micro/kernels/add_test.cc - - add_n_test: - sources: - - tensorflow/lite/micro/kernels/add_n_test.cc - - arg_min_max_test: - sources: - - tensorflow/lite/micro/kernels/arg_min_max_test.cc - - batch_to_space_nd_test: - sources: - - tensorflow/lite/micro/kernels/batch_to_space_nd_test.cc - - cast_test: - sources: - - tensorflow/lite/micro/kernels/cast_test.cc - - ceil_test: - sources: - - tensorflow/lite/micro/kernels/ceil_test.cc - - circular_buffer_test: - sources: - - tensorflow/lite/micro/kernels/circular_buffer_test.cc - - tensorflow/lite/micro/kernels/circular_buffer_flexbuffers_generated_data.cc - - comparisons_test: - sources: - - tensorflow/lite/micro/kernels/comparisons_test.cc - - concatenation_test: - sources: - - tensorflow/lite/micro/kernels/concatenation_test.cc - - conv_test: - sources: - - tensorflow/lite/micro/kernels/conv_test.cc - - tensorflow/lite/micro/kernels/conv_test_common.cc - - cumsum_test: - sources: - - tensorflow/lite/micro/kernels/cumsum_test.cc - - depth_to_space_test: - sources: - - tensorflow/lite/micro/kernels/depth_to_space_test.cc - - depthwise_conv_test: - sources: - - tensorflow/lite/micro/kernels/depthwise_conv_test.cc - - dequantize_test: - sources: - - tensorflow/lite/micro/kernels/dequantize_test.cc - - detection_postprocess_test: - sources: - - tensorflow/lite/micro/kernels/detection_postprocess_test.cc - - tensorflow/lite/micro/kernels/detection_postprocess_flexbuffers_generated_data.cc - - elementwise_test: - sources: - - tensorflow/lite/micro/kernels/elementwise_test.cc - - elu_test: - sources: - - tensorflow/lite/micro/kernels/elu_test.cc - - exp_test: - sources: - - tensorflow/lite/micro/kernels/exp_test.cc - - expand_dims_test: - sources: - - tensorflow/lite/micro/kernels/expand_dims_test.cc - - fill_test: - sources: - - tensorflow/lite/micro/kernels/fill_test.cc - - floor_test: - sources: - - tensorflow/lite/micro/kernels/floor_test.cc - - floor_div_test: - sources: - - tensorflow/lite/micro/kernels/floor_div_test.cc - - floor_mod_test: - sources: - - tensorflow/lite/micro/kernels/floor_mod_test.cc - - fully_connected_test: - sources: - - tensorflow/lite/micro/kernels/fully_connected_test.cc - - gather_test: - sources: - - tensorflow/lite/micro/kernels/gather_test.cc - - gather_nd_test: - sources: - - tensorflow/lite/micro/kernels/gather_nd_test.cc - - hard_swish_test: - sources: - - tensorflow/lite/micro/kernels/hard_swish_test.cc - - l2norm_test: - sources: - - tensorflow/lite/micro/kernels/l2norm_test.cc - - l2_pool_2d_test: - sources: - - tensorflow/lite/micro/kernels/l2_pool_2d_test.cc - - leaky_relu_test: - sources: - - tensorflow/lite/micro/kernels/leaky_relu_test.cc - - logical_test: - sources: - - tensorflow/lite/micro/kernels/logical_test.cc - - logistic_test: - sources: - - tensorflow/lite/micro/kernels/logistic_test.cc - - log_softmax_test: - sources: - - tensorflow/lite/micro/kernels/log_softmax_test.cc - - maximum_minimum_test: - sources: - - tensorflow/lite/micro/kernels/maximum_minimum_test.cc - - mul_test: - sources: - - tensorflow/lite/micro/kernels/mul_test.cc - - neg_test: - sources: - - tensorflow/lite/micro/kernels/neg_test.cc - - pack_test: - sources: - - tensorflow/lite/micro/kernels/pack_test.cc - - pad_test: - sources: - - tensorflow/lite/micro/kernels/pad_test.cc - - pooling_test: - sources: - - tensorflow/lite/micro/kernels/pooling_test.cc - - prelu_test: - sources: - - tensorflow/lite/micro/kernels/prelu_test.cc - - quantization_util_test: - sources: - - tensorflow/lite/micro/kernels/quantization_util_test.cc - - quantize_test: - sources: - - tensorflow/lite/micro/kernels/quantize_test.cc - - reduce_test: - sources: - - tensorflow/lite/micro/kernels/reduce_test.cc - - reshape_test: - sources: - - tensorflow/lite/micro/kernels/reshape_test.cc - - resize_bilinear_test: - sources: - - tensorflow/lite/micro/kernels/resize_bilinear_test.cc - - resize_nearest_neighbor_test: - sources: - - tensorflow/lite/micro/kernels/resize_nearest_neighbor_test.cc - - round_test: - sources: - - tensorflow/lite/micro/kernels/round_test.cc - - shape_test: - sources: - - tensorflow/lite/micro/kernels/shape_test.cc - - softmax_test: - sources: - - tensorflow/lite/micro/kernels/softmax_test.cc - - space_to_batch_nd_test: - sources: - - tensorflow/lite/micro/kernels/space_to_batch_nd_test.cc - - space_to_depth_test: - sources: - - tensorflow/lite/micro/kernels/space_to_depth_test.cc - - split_test: - sources: - - tensorflow/lite/micro/kernels/split_test.cc - - split_v_test: - sources: - - tensorflow/lite/micro/kernels/split_v_test.cc - - squeeze_test: - sources: - - tensorflow/lite/micro/kernels/squeeze_test.cc - - strided_slice_test: - sources: - - tensorflow/lite/micro/kernels/strided_slice_test.cc - - sub_test: - sources: - - tensorflow/lite/micro/kernels/sub_test.cc - - svdf_test: - sources: - - tensorflow/lite/micro/kernels/svdf_test.cc - - tanh_test: - sources: - - tensorflow/lite/micro/kernels/tanh_test.cc - - transpose_test: - sources: - - tensorflow/lite/micro/kernels/transpose_test.cc - - transpose_conv_test: - sources: - - tensorflow/lite/micro/kernels/transpose_conv_test.cc - - tensorflow/lite/micro/kernels/conv_test_common.cc - - unpack_test: - sources: - - tensorflow/lite/micro/kernels/unpack_test.cc - - zeros_like_test: - sources: - - tensorflow/lite/micro/kernels/zeros_like_test.cc - - greedy_memory_planner_test: - sources: - - tensorflow/lite/micro/memory_planner/greedy_memory_planner_test.cc - - linear_memory_planner_test: - sources: - - tensorflow/lite/micro/memory_planner/linear_memory_planner_test.c diff --git a/tensorflow-test-ng/kernel_tests_ethos.yml b/tensorflow-test-ng/kernel_tests_ethos.yml deleted file mode 100644 index 161e423..0000000 --- a/tensorflow-test-ng/kernel_tests_ethos.yml +++ /dev/null @@ -1,203 +0,0 @@ -kernel_unit_tests: - readable: "Kernel Unit Tests - Ethos-U" - report: kernel.ethos.junit - tests: - - activations_test: - sources: - - tensorflow/lite/micro/kernels/activations_test.cc - - add_test: - sources: - - tensorflow/lite/micro/kernels/add_test.cc - - add_n_test: - sources: - - tensorflow/lite/micro/kernels/add_n_test.cc - - arg_min_max_test: - sources: - - tensorflow/lite/micro/kernels/arg_min_max_test.cc - - batch_to_space_nd_test: - sources: - - tensorflow/lite/micro/kernels/batch_to_space_nd_test.cc - - cast_test: - sources: - - tensorflow/lite/micro/kernels/cast_test.cc - - ceil_test: - sources: - - tensorflow/lite/micro/kernels/ceil_test.cc - - circular_buffer_test: - sources: - - tensorflow/lite/micro/kernels/circular_buffer_test.cc - - tensorflow/lite/micro/kernels/circular_buffer_flexbuffers_generated_data.cc - - comparisons_test: - sources: - - tensorflow/lite/micro/kernels/comparisons_test.cc - - concatenation_test: - sources: - - tensorflow/lite/micro/kernels/concatenation_test.cc - - conv_test: - sources: - - tensorflow/lite/micro/kernels/conv_test.cc - - tensorflow/lite/micro/kernels/conv_test_common.cc - - cumsum_test: - sources: - - tensorflow/lite/micro/kernels/cumsum_test.cc - - depth_to_space_test: - sources: - - tensorflow/lite/micro/kernels/depth_to_space_test.cc - - depthwise_conv_test: - sources: - - tensorflow/lite/micro/kernels/depthwise_conv_test.cc - - dequantize_test: - sources: - - tensorflow/lite/micro/kernels/dequantize_test.cc - - detection_postprocess_test: - sources: - - tensorflow/lite/micro/kernels/detection_postprocess_test.cc - - tensorflow/lite/micro/kernels/detection_postprocess_flexbuffers_generated_data.cc - - elementwise_test: - sources: - - tensorflow/lite/micro/kernels/elementwise_test.cc - - elu_test: - sources: - - tensorflow/lite/micro/kernels/elu_test.cc - - exp_test: - sources: - - tensorflow/lite/micro/kernels/exp_test.cc - - expand_dims_test: - sources: - - tensorflow/lite/micro/kernels/expand_dims_test.cc - - fill_test: - sources: - - tensorflow/lite/micro/kernels/fill_test.cc - - floor_test: - sources: - - tensorflow/lite/micro/kernels/floor_test.cc - - floor_div_test: - sources: - - tensorflow/lite/micro/kernels/floor_div_test.cc - - floor_mod_test: - sources: - - tensorflow/lite/micro/kernels/floor_mod_test.cc - - fully_connected_test: - sources: - - tensorflow/lite/micro/kernels/fully_connected_test.cc - - gather_test: - sources: - - tensorflow/lite/micro/kernels/gather_test.cc - - gather_nd_test: - sources: - - tensorflow/lite/micro/kernels/gather_nd_test.cc - - hard_swish_test: - sources: - - tensorflow/lite/micro/kernels/hard_swish_test.cc - - l2norm_test: - sources: - - tensorflow/lite/micro/kernels/l2norm_test.cc - - l2_pool_2d_test: - sources: - - tensorflow/lite/micro/kernels/l2_pool_2d_test.cc - - leaky_relu_test: - sources: - - tensorflow/lite/micro/kernels/leaky_relu_test.cc - - logical_test: - sources: - - tensorflow/lite/micro/kernels/logical_test.cc - - logistic_test: - sources: - - tensorflow/lite/micro/kernels/logistic_test.cc - - log_softmax_test: - sources: - - tensorflow/lite/micro/kernels/log_softmax_test.cc - - maximum_minimum_test: - sources: - - tensorflow/lite/micro/kernels/maximum_minimum_test.cc - - mul_test: - sources: - - tensorflow/lite/micro/kernels/mul_test.cc - - neg_test: - sources: - - tensorflow/lite/micro/kernels/neg_test.cc - - pack_test: - sources: - - tensorflow/lite/micro/kernels/pack_test.cc - - pad_test: - sources: - - tensorflow/lite/micro/kernels/pad_test.cc - - pooling_test: - sources: - - tensorflow/lite/micro/kernels/pooling_test.cc - - prelu_test: - sources: - - tensorflow/lite/micro/kernels/prelu_test.cc - - quantization_util_test: - sources: - - tensorflow/lite/micro/kernels/quantization_util_test.cc - - quantize_test: - sources: - - tensorflow/lite/micro/kernels/quantize_test.cc - - reduce_test: - sources: - - tensorflow/lite/micro/kernels/reduce_test.cc - - reshape_test: - sources: - - tensorflow/lite/micro/kernels/reshape_test.cc - - resize_bilinear_test: - sources: - - tensorflow/lite/micro/kernels/resize_bilinear_test.cc - - resize_nearest_neighbor_test: - sources: - - tensorflow/lite/micro/kernels/resize_nearest_neighbor_test.cc - - round_test: - sources: - - tensorflow/lite/micro/kernels/round_test.cc - - shape_test: - sources: - - tensorflow/lite/micro/kernels/shape_test.cc - - softmax_test: - sources: - - tensorflow/lite/micro/kernels/softmax_test.cc - - space_to_batch_nd_test: - sources: - - tensorflow/lite/micro/kernels/space_to_batch_nd_test.cc - - space_to_depth_test: - sources: - - tensorflow/lite/micro/kernels/space_to_depth_test.cc - - split_test: - sources: - - tensorflow/lite/micro/kernels/split_test.cc - - split_v_test: - sources: - - tensorflow/lite/micro/kernels/split_v_test.cc - - squeeze_test: - sources: - - tensorflow/lite/micro/kernels/squeeze_test.cc - - strided_slice_test: - sources: - - tensorflow/lite/micro/kernels/strided_slice_test.cc - - sub_test: - sources: - - tensorflow/lite/micro/kernels/sub_test.cc - - svdf_test: - sources: - - tensorflow/lite/micro/kernels/svdf_test.cc - - tanh_test: - sources: - - tensorflow/lite/micro/kernels/tanh_test.cc - - transpose_test: - sources: - - tensorflow/lite/micro/kernels/transpose_test.cc - - transpose_conv_test: - sources: - - tensorflow/lite/micro/kernels/transpose_conv_test.cc - - tensorflow/lite/micro/kernels/conv_test_common.cc - - unpack_test: - sources: - - tensorflow/lite/micro/kernels/unpack_test.cc - - zeros_like_test: - sources: - - tensorflow/lite/micro/kernels/zeros_like_test.cc - - lanner/greedy_memory_planner_test: - sources: - - tensorflow/lite/micro/memory_planner/greedy_memory_planner_test.cc - - lanner/linear_memory_planner_te: - sources: - - tensorflow/lite/micro/memory_planner/linear_memory_planner_test.c \ No newline at end of file diff --git a/tensorflow-test-ng/kernel_tests_reference.yml b/tensorflow-test-ng/kernel_tests_reference.yml deleted file mode 100644 index 11a9aab..0000000 --- a/tensorflow-test-ng/kernel_tests_reference.yml +++ /dev/null @@ -1,203 +0,0 @@ -kernel_unit_tests: - readable: "Kernel Unit Tests Reference" - report: kernel.reference.junit - tests: - - activations_test: - sources: - - tensorflow/lite/micro/kernels/activations_test.cc - - add_test: - sources: - - tensorflow/lite/micro/kernels/add_test.cc - - add_n_test: - sources: - - tensorflow/lite/micro/kernels/add_n_test.cc - - arg_min_max_test: - sources: - - tensorflow/lite/micro/kernels/arg_min_max_test.cc - - batch_to_space_nd_test: - sources: - - tensorflow/lite/micro/kernels/batch_to_space_nd_test.cc - - cast_test: - sources: - - tensorflow/lite/micro/kernels/cast_test.cc - - ceil_test: - sources: - - tensorflow/lite/micro/kernels/ceil_test.cc - - circular_buffer_test: - sources: - - tensorflow/lite/micro/kernels/circular_buffer_test.cc - - tensorflow/lite/micro/kernels/circular_buffer_flexbuffers_generated_data.cc - - comparisons_test: - sources: - - tensorflow/lite/micro/kernels/comparisons_test.cc - - concatenation_test: - sources: - - tensorflow/lite/micro/kernels/concatenation_test.cc - - conv_test: - sources: - - tensorflow/lite/micro/kernels/conv_test.cc - - tensorflow/lite/micro/kernels/conv_test_common.cc - - cumsum_test: - sources: - - tensorflow/lite/micro/kernels/cumsum_test.cc - - depth_to_space_test: - sources: - - tensorflow/lite/micro/kernels/depth_to_space_test.cc - - depthwise_conv_test: - sources: - - tensorflow/lite/micro/kernels/depthwise_conv_test.cc - - dequantize_test: - sources: - - tensorflow/lite/micro/kernels/dequantize_test.cc - - detection_postprocess_test: - sources: - - tensorflow/lite/micro/kernels/detection_postprocess_test.cc - - tensorflow/lite/micro/kernels/detection_postprocess_flexbuffers_generated_data.cc - - elementwise_test: - sources: - - tensorflow/lite/micro/kernels/elementwise_test.cc - - elu_test: - sources: - - tensorflow/lite/micro/kernels/elu_test.cc - - exp_test: - sources: - - tensorflow/lite/micro/kernels/exp_test.cc - - expand_dims_test: - sources: - - tensorflow/lite/micro/kernels/expand_dims_test.cc - - fill_test: - sources: - - tensorflow/lite/micro/kernels/fill_test.cc - - floor_test: - sources: - - tensorflow/lite/micro/kernels/floor_test.cc - - floor_div_test: - sources: - - tensorflow/lite/micro/kernels/floor_div_test.cc - - floor_mod_test: - sources: - - tensorflow/lite/micro/kernels/floor_mod_test.cc - - fully_connected_test: - sources: - - tensorflow/lite/micro/kernels/fully_connected_test.cc - - gather_test: - sources: - - tensorflow/lite/micro/kernels/gather_test.cc - - gather_nd_test: - sources: - - tensorflow/lite/micro/kernels/gather_nd_test.cc - - hard_swish_test: - sources: - - tensorflow/lite/micro/kernels/hard_swish_test.cc - - l2norm_test: - sources: - - tensorflow/lite/micro/kernels/l2norm_test.cc - - l2_pool_2d_test: - sources: - - tensorflow/lite/micro/kernels/l2_pool_2d_test.cc - - leaky_relu_test: - sources: - - tensorflow/lite/micro/kernels/leaky_relu_test.cc - - logical_test: - sources: - - tensorflow/lite/micro/kernels/logical_test.cc - - logistic_test: - sources: - - tensorflow/lite/micro/kernels/logistic_test.cc - - log_softmax_test: - sources: - - tensorflow/lite/micro/kernels/log_softmax_test.cc - - maximum_minimum_test: - sources: - - tensorflow/lite/micro/kernels/maximum_minimum_test.cc - - mul_test: - sources: - - tensorflow/lite/micro/kernels/mul_test.cc - - neg_test: - sources: - - tensorflow/lite/micro/kernels/neg_test.cc - - pack_test: - sources: - - tensorflow/lite/micro/kernels/pack_test.cc - - pad_test: - sources: - - tensorflow/lite/micro/kernels/pad_test.cc - - pooling_test: - sources: - - tensorflow/lite/micro/kernels/pooling_test.cc - - prelu_test: - sources: - - tensorflow/lite/micro/kernels/prelu_test.cc - - quantization_util_test: - sources: - - tensorflow/lite/micro/kernels/quantization_util_test.cc - - quantize_test: - sources: - - tensorflow/lite/micro/kernels/quantize_test.cc - - reduce_test: - sources: - - tensorflow/lite/micro/kernels/reduce_test.cc - - reshape_test: - sources: - - tensorflow/lite/micro/kernels/reshape_test.cc - - resize_bilinear_test: - sources: - - tensorflow/lite/micro/kernels/resize_bilinear_test.cc - - resize_nearest_neighbor_test: - sources: - - tensorflow/lite/micro/kernels/resize_nearest_neighbor_test.cc - - round_test: - sources: - - tensorflow/lite/micro/kernels/round_test.cc - - shape_test: - sources: - - tensorflow/lite/micro/kernels/shape_test.cc - - softmax_test: - sources: - - tensorflow/lite/micro/kernels/softmax_test.cc - - space_to_batch_nd_test: - sources: - - tensorflow/lite/micro/kernels/space_to_batch_nd_test.cc - - space_to_depth_test: - sources: - - tensorflow/lite/micro/kernels/space_to_depth_test.cc - - split_test: - sources: - - tensorflow/lite/micro/kernels/split_test.cc - - split_v_test: - sources: - - tensorflow/lite/micro/kernels/split_v_test.cc - - squeeze_test: - sources: - - tensorflow/lite/micro/kernels/squeeze_test.cc - - strided_slice_test: - sources: - - tensorflow/lite/micro/kernels/strided_slice_test.cc - - sub_test: - sources: - - tensorflow/lite/micro/kernels/sub_test.cc - - svdf_test: - sources: - - tensorflow/lite/micro/kernels/svdf_test.cc - - tanh_test: - sources: - - tensorflow/lite/micro/kernels/tanh_test.cc - - transpose_test: - sources: - - tensorflow/lite/micro/kernels/transpose_test.cc - - transpose_conv_test: - sources: - - tensorflow/lite/micro/kernels/transpose_conv_test.cc - - tensorflow/lite/micro/kernels/conv_test_common.cc - - unpack_test: - sources: - - tensorflow/lite/micro/kernels/unpack_test.cc - - zeros_like_test: - sources: - - tensorflow/lite/micro/kernels/zeros_like_test.cc - - greedy_memory_planner_test: - sources: - - tensorflow/lite/micro/memory_planner/greedy_memory_planner_test.cc - - linear_memory_planner_test: - sources: - - tensorflow/lite/micro/memory_planner/linear_memory_planner_test.cc \ No newline at end of file diff --git a/tensorflow-test-ng/record_test_results.py b/tensorflow-test-ng/record_test_results.py deleted file mode 100644 index 8565b3a..0000000 --- a/tensorflow-test-ng/record_test_results.py +++ /dev/null @@ -1,82 +0,0 @@ -import sqlite3 -import argparse -import os -import sys - -#python main -def main(): -#get argument from command line - parser = argparse.ArgumentParser( - description="Copy test sources from tensorflow repo to sources in test package.") - # add the --results option - parser.add_argument("--results", type=str, default=os.path.curdir, - help="stdio log of testrun") - # Check if path in --results exists - if not os.path.exists(parser.parse_args().results): - print("File " + parser.parse_args().results + " does not exist") - sys.exit(1) - #connect to database - conn = sqlite3.connect('test_results.db') - db = conn.cursor() - #create table - db.execute('''CREATE TABLE IF NOT EXISTS results - (package text, testname text, compiler text, cvariant text, targetcpu text, testok boolean)''') - #insert a row of data - # print --results - print("Working on results: " + parser.parse_args().results) - # Read results file - with open(parser.parse_args().results, 'r') as stream: - results = stream.read() - # Walk trough results file line by line - for line in results.splitlines(): - # Check if line contains "Working on project: " - if "Working on project: " in line: - # Get project name - project_file = line.split("Working on project: ")[1] - splitstring = project_file.split("/") - package = splitstring[2] - project = splitstring[4] - print("Project: " + project_file) - print("Package: " + package) - # Extract string between two strings "+" and ".axf" - cpu = project.split("+")[1] - cpu = cpu.split(".cprj")[0] - print("Target CPU: " + cpu) - # Extract string between two strings "_" and "+" - compiler = project.split("_")[1] - compiler = compiler.split("+")[0] - print("Compiler: " + compiler) - # Extract string between two strings "Validation." and "_" - cvariant = project.split("Validation.")[1] - cvariant = cvariant.split("_")[0] - print("Cvariant: " + cvariant) - testcount = 0 - # Walk trough results file line by line - for line in results.splitlines(): - # Check if line contains "Testing " - if "Testing " in line: - testcount+=1 - test_name = line.split("Testing ")[1] - print("Register: " + test_name) - test_ok = "False" - # Check if next line contains "Testing" or "passed" or "xterm" - if "Testing" in results.splitlines()[results.splitlines().index(line)+1]: - test_ok = "True" - elif "xterm" in results.splitlines()[results.splitlines().index(line)+1]: - test_ok = "True" - elif "passed" in results.splitlines()[results.splitlines().index(line)+1]: - test_ok = "True" - db.execute("INSERT INTO results VALUES ('"+package+"','"+test_name+"', '"+compiler+"','"+cvariant+"', '"+cpu+"', '"+test_ok+"')") - if testcount == 0: - print("No tests found - package failed") - db.execute("INSERT INTO results VALUES ('"+package+"','ALL_TESTS', '"+compiler+"','"+cvariant+"', '"+cpu+"', 'False')") - #commit changes - conn.commit() - #close connection - conn.close() - return 0 - - -#python application entry point -if __name__ == "__main__": - main() \ No newline at end of file diff --git a/tensorflow-test-ng/test_r.sh b/tensorflow-test-ng/test_r.sh deleted file mode 100755 index 36865a2..0000000 --- a/tensorflow-test-ng/test_r.sh +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/sh -# Create string with list of yml inventorys to run -#inventory_list="generic_tests.yml kernel_tests_cmsis.yml test_tests.yml" -inventory_list="test_tests.yml" - -rm -R ./tensorflow-pack/tensorflow-test-ng/Source -mkdir ./tensorflow-pack/tensorflow-test-ng/Source - -for inventory in $inventory_list; do - python3 ./tensorflow-pack/tensorflow-test-ng/copy_sources.py \ - --tflm_path=./tensorflow-pack/tensorflow-build/rel/mlplatform/core_software/tflite_micro \ - --inventory=./tensorflow-pack/tensorflow-test-ng/$inventory \ - --out_path=./tensorflow-pack/tensorflow-test-ng/Source -done - -rm -R ./tensorflow-pack/tensorflow-test-ng/gen -mkdir ./tensorflow-pack/tensorflow-test-ng/gen - -for inventory in $inventory_list; do - python3 ./tensorflow-pack/tensorflow-test-ng/create_tests.py \ - --inventory=./tensorflow-pack/tensorflow-test-ng/$inventory \ - --out_path=./tensorflow-pack/tensorflow-test-ng/gen -done diff --git a/tensorflow-test-ng/test_tests.yml b/tensorflow-test-ng/test_tests.yml deleted file mode 100644 index 88fd98e..0000000 --- a/tensorflow-test-ng/test_tests.yml +++ /dev/null @@ -1,12 +0,0 @@ -test_tests: - readable: "Test Tests" - report: test_test.junit - tests: - - testing_helpers_test: - sources: - - tensorflow/lite/micro/testing_helpers_test.cc - - - - - diff --git a/tensorflow-test/HelloWorld/HelloWorld.cbuild-idx.yml b/tensorflow-test/HelloWorld/HelloWorld.cbuild-idx.yml new file mode 100644 index 0000000..cd7121d --- /dev/null +++ b/tensorflow-test/HelloWorld/HelloWorld.cbuild-idx.yml @@ -0,0 +1,12 @@ +build-idx: + generated-by: csolution version 2.1.0 + cdefault: ${CMSIS_COMPILER_ROOT}/cdefault.yml + csolution: HelloWorld.csolution.yml + cprojects: + - cproject: HelloWorld.cproject.yml + clayers: + - clayer: $Target-Layer$ + cbuilds: + - cbuild: HelloWorld.size+CM55.cbuild.yml + project: HelloWorld + configuration: .size+CM55 diff --git a/tensorflow-test/HelloWorld/HelloWorld.cproject.yml b/tensorflow-test/HelloWorld/HelloWorld.cproject.yml new file mode 100644 index 0000000..4e7d47d --- /dev/null +++ b/tensorflow-test/HelloWorld/HelloWorld.cproject.yml @@ -0,0 +1,47 @@ +project: + + debug: on + + packs: + - pack: ARM::CMSIS + - pack: ARM::CMSIS-DSP + - pack: ARM::CMSIS-NN + # path: ../ + - pack: ARM::Cortex_DFP + # path: ../ + - pack: tensorflow::tensorflow-lite-micro + - pack: tensorflow::flatbuffers + - pack: tensorflow::gemmlowp + - pack: tensorflow::kissfft + - pack: tensorflow::ruy + + add-path: + - ./hello_world + + define: + - PROJECT_GENERATION: 1 + + components: + - component: ARM::CMSIS:DSP&Source + - component: ARM::CMSIS:NN Lib + - component: tensorflow::Data Exchange:Serialization:flatbuffers + - component: tensorflow::Data Processing:Math:gemmlowp fixed-point&tensorflow + - component: tensorflow::Data Processing:Math:kissfft&tensorflow + - component: tensorflow::Data Processing:Math:ruy&tensorflow + - component: tensorflow::Machine Learning:TensorFlow:Kernel&Reference + - component: tensorflow::Machine Learning:TensorFlow:Kernel Utils + - component: tensorflow::Machine Learning:TensorFlow:Testing + - component: ARM::CMSIS:CORE@6.0.0 + - component: ARM::Device:Startup&C Startup + + groups: + - group: TFL_main + files: + - file: ./hello_world/hello_world_test.cpp + - group: TFL_models + files: + - file: ./hello_world/models/hello_world_int8_model_data.cpp + - file: ./hello_world/models/hello_world_float_model_data.cpp + + layers: + - layer: $Target-Layer$ diff --git a/tensorflow-test/HelloWorld/HelloWorld.csolution.yml b/tensorflow-test/HelloWorld/HelloWorld.csolution.yml new file mode 100644 index 0000000..cdc33fb --- /dev/null +++ b/tensorflow-test/HelloWorld/HelloWorld.csolution.yml @@ -0,0 +1,95 @@ +solution: + created-for: cmsis-toobox@2.0.0 + + cdefault: + misc: + - for-compiler: GCC + C-CPP: + - -ffunction-sections + - -fdata-sections + Link: + - -Wl,--gc-sections + - for-compiler: CLANG + C-CPP: + - -ffunction-sections + - -fdata-sections + Link: + - -Wl,--gc-sections + + packs: + - pack: ARM::Cortex_DFP + + target-types: + - type: CM0 + device: ARMCM0 + variables: + - Target-Layer: ../Target/CM0/Target.clayer.yml + - type: CM0plus + device: ARMCM0P + variables: + - Target-Layer: ../Target/CM0plus/Target.clayer.yml + - type: CM3 + device: ARMCM3 + variables: + - Target-Layer: ../Target/CM3/Target.clayer.yml + - type: CM4 + device: ARMCM4 + processor: + fpu: off + variables: + - Target-Layer: ../Target/CM4/Target.clayer.yml + - type: CM4_FP + device: ARMCM4 + variables: + - Target-Layer: ../Target/CM4/Target.clayer.yml + - type: CM7 + device: ARMCM7 + variables: + - Target-Layer: ../Target/CM7/Target.clayer.yml + - type: CM23 + device: ARMCM23 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM23/Target.clayer.yml + - type: CM33 + device: ARMCM33 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM33/Target.clayer.yml + - type: CM55 + device: ARMCM55 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM55/Target.clayer.yml + - type: CM55_Ethos + device: ARMCM55 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM55_Ethos/Target.clayer.yml + - type: CM85 + device: ARMCM85 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM85/Target.clayer.yml + - type: CM85_Ethos + device: ARMCM85 + processor: + trustzone: off + variables: + - Target-Layer: ../Target/CM85_Ethos/Target.clayer.yml + + build-types: + - type: balanced + optimize: balanced + - type: size + optimize: size + - type: speed + optimize: speed + + projects: + - project: ./HelloWorld.cproject.yml diff --git a/tensorflow-test/HelloWorld/HelloWorld.size+CM55.cbuild.yml b/tensorflow-test/HelloWorld/HelloWorld.size+CM55.cbuild.yml new file mode 100644 index 0000000..5d7cdbd --- /dev/null +++ b/tensorflow-test/HelloWorld/HelloWorld.size+CM55.cbuild.yml @@ -0,0 +1,736 @@ +build: + generated-by: csolution version 2.1.0 + solution: HelloWorld.csolution.yml + project: HelloWorld.cproject.yml + context: HelloWorld.size+CM55 + compiler: AC6 + device: ARMCM55 + processor: + fpu: on + trustzone: off + packs: + - pack: ARM::CMSIS-DSP@1.15.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0 + - pack: ARM::CMSIS-NN@4.1.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0 + - pack: ARM::CMSIS@6.0.0 + path: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0 + - pack: ARM::Cortex_DFP@1.0.0 + path: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0 + - pack: tensorflow::flatbuffers@1.24.2 + path: ${CMSIS_PACK_ROOT}/tensorflow/flatbuffers/1.24.2 + - pack: tensorflow::gemmlowp@1.24.2 + path: ${CMSIS_PACK_ROOT}/tensorflow/gemmlowp/1.24.2 + - pack: tensorflow::kissfft@1.24.2 + path: ${CMSIS_PACK_ROOT}/tensorflow/kissfft/1.24.2 + - pack: tensorflow::ruy@1.24.2 + path: ${CMSIS_PACK_ROOT}/tensorflow/ruy/1.24.2 + - pack: tensorflow::tensorflow-lite-micro@1.24.2 + path: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2 + optimize: size + debug: on + misc: + ASM: + - -masm=auto + C: + - -std=gnu11 + - -ffunction-sections + - -Wno-macro-redefined + - -Wno-pragma-pack + - -Wno-parentheses-equality + - -Wno-license-management + CPP: + - -ffunction-sections + - -Wno-macro-redefined + - -Wno-pragma-pack + - -Wno-parentheses-equality + - -Wno-license-management + Link: + - --entry=Reset_Handler + - --map + - --info summarysizes + - --summary_stderr + - --diag_suppress=L6314W + define: + - PROJECT_GENERATION: 1 + - ARMCM55 + - _RTE_ + add-path: + - hello_world + - RTE/_size_CM55 + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/PrivateInclude + - ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Include + - ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/CMSIS/Core/Include + - ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/Device/ARMCM55/Include + - ${CMSIS_PACK_ROOT}/tensorflow/flatbuffers/1.24.2/src/include + - ${CMSIS_PACK_ROOT}/tensorflow/gemmlowp/1.24.2/src + - ${CMSIS_PACK_ROOT}/tensorflow/kissfft/1.24.2/src + - ${CMSIS_PACK_ROOT}/tensorflow/kissfft/1.24.2/src/tools + - ${CMSIS_PACK_ROOT}/tensorflow/ruy/1.24.2/src + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2 + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/c + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/core + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/core/api + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/core/c + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/kernels + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/kernels/internal + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/kernels/internal/optimized + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/kernels/internal/reference + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/kernels/internal/reference/integer_ops + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/arena_allocator + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/cortex_m_generic + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/kernels + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/memory_planner + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/testing + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/tflite_bridge + - ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/schema + output-dirs: + intdir: tmp/HelloWorld/CM55/size + outdir: out/HelloWorld/CM55/size + rtedir: RTE + output: + - type: elf + file: HelloWorld.axf + components: + - component: ARM::CMSIS:CORE@6.0.0 + condition: ARMv6_7_8-M Device + from-pack: ARM::CMSIS@6.0.0 + selected-by: ARM::CMSIS:CORE@6.0.0 + - component: ARM::CMSIS:DSP&Source@1.15.0 + condition: CMSISCORE + from-pack: ARM::CMSIS-DSP@1.15.0 + selected-by: ARM::CMSIS:DSP&Source + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/BasicMathFunctions/BasicMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/BasicMathFunctions/BasicMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/BayesFunctions/BayesFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/BayesFunctions/BayesFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/CommonTables/CommonTables.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/CommonTables/CommonTablesF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/ComplexMathFunctions/ComplexMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/ComplexMathFunctions/ComplexMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/ControllerFunctions/ControllerFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/DistanceFunctions/DistanceFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/DistanceFunctions/DistanceFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/FastMathFunctions/FastMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/FastMathFunctions/FastMathFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/FilteringFunctions/FilteringFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/FilteringFunctions/FilteringFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/InterpolationFunctions/InterpolationFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/InterpolationFunctions/InterpolationFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/MatrixFunctions/MatrixFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/MatrixFunctions/MatrixFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/QuaternionMathFunctions/QuaternionMathFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/SVMFunctions/SVMFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/SVMFunctions/SVMFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/StatisticsFunctions/StatisticsFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/StatisticsFunctions/StatisticsFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/SupportFunctions/SupportFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/SupportFunctions/SupportFunctionsF16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/TransformFunctions/TransformFunctions.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/Source/TransformFunctions/TransformFunctionsF16.c + category: source + - component: ARM::CMSIS:NN Lib@4.1.0 + condition: CMSIS-NN + from-pack: ARM::CMSIS-NN@4.1.0 + selected-by: ARM::CMSIS:NN Lib + files: + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_nn_activation_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu6_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q15.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/ActivationFunctions/arm_relu_q7.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s16.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_add_s8.c + category: source + - file: ${CMSIS_PACK_ROOT}/ARM/CMSIS-NN/4.1.0/Source/BasicMathFunctions/arm_elementwise_mul_s16.c + category: source + - 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file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/kernels/squeeze.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/kernels/strided_slice.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/kernels/strided_slice_common.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/kernels/sub.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/kernels/sub_common.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/kernels/svdf.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/kernels/svdf_common.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/kernels/tanh.cpp + category: sourceCpp + - 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file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/memory_planner/greedy_memory_planner.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/memory_planner/linear_memory_planner.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/memory_planner/non_persistent_buffer_planner_shim.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_allocation_info.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_allocator.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_context.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_interpreter.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_interpreter_context.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_interpreter_graph.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_log.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_op_resolver.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_profiler.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_resource_variable.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/micro_utils.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/mock_micro_graph.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/recording_micro_allocator.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/test_helper_custom_ops.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/test_helpers.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/tflite_bridge/flatbuffer_conversions_bridge.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/micro/tflite_bridge/micro_error_reporter.cpp + category: sourceCpp + - file: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/tensorflow/lite/schema/schema_utils.cpp + category: sourceCpp + - component: tensorflow::Machine Learning:TensorFlow:Testing@1.24.2 + from-pack: tensorflow::tensorflow-lite-micro@1.24.2 + selected-by: tensorflow::Machine Learning:TensorFlow:Testing + linker: + script: ${CMSIS_COMPILER_ROOT}/ac6_linker_script.sct + regions: ../Target/CM55/RTE/Device/ARMCM55/regions_ARMCM55.h + groups: + - group: TFL_main + files: + - file: ./hello_world/hello_world_test.cpp + category: sourceCpp + - group: TFL_models + files: + - file: ./hello_world/models/hello_world_int8_model_data.cpp + category: sourceCpp + - file: ./hello_world/models/hello_world_float_model_data.cpp + category: sourceCpp + - group: FVP + files: + - file: ../Target/CM55/fvp_config.txt + category: doc + constructed-files: + - file: RTE/_size_CM55/Pre_Include_Global.h + category: preIncludeGlobal + - file: RTE/_size_CM55/RTE_Components.h + category: header + licenses: + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/CMSIS-DSP/1.15.0/LICENSE + packs: + - pack: ARM::CMSIS-DSP@1.15.0 + components: + - component: ARM::CMSIS:DSP&Source@1.15.0 + - license: + packs: + - pack: ARM::CMSIS-NN@4.1.0 + components: + - component: ARM::CMSIS:NN Lib@4.1.0 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/CMSIS/6.0.0/LICENSE + packs: + - pack: ARM::CMSIS@6.0.0 + components: + - component: ARM::CMSIS:CORE@6.0.0 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/ARM/Cortex_DFP/1.0.0/LICENSE + packs: + - pack: ARM::Cortex_DFP@1.0.0 + components: + - component: ARM::Device:Startup&C Startup@2.2.0 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/tensorflow/flatbuffers/1.24.2/LICENSE.txt + packs: + - pack: tensorflow::flatbuffers@1.24.2 + components: + - component: tensorflow::Data Exchange:Serialization:flatbuffers&tensorflow@1.24.2 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/tensorflow/gemmlowp/1.24.2/LICENSE.txt + packs: + - pack: tensorflow::gemmlowp@1.24.2 + components: + - component: tensorflow::Data Processing:Math:gemmlowp fixed-point&tensorflow@1.24.2 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/tensorflow/kissfft/1.24.2/LICENSE.txt + packs: + - pack: tensorflow::kissfft@1.24.2 + components: + - component: tensorflow::Data Processing:Math:kissfft&tensorflow@1.24.2 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/tensorflow/ruy/1.24.2/LICENSE.txt + packs: + - pack: tensorflow::ruy@1.24.2 + components: + - component: tensorflow::Data Processing:Math:ruy&tensorflow@1.24.2 + - license: + license-agreement: ${CMSIS_PACK_ROOT}/tensorflow/tensorflow-lite-micro/1.24.2/LICENSE + packs: + - pack: tensorflow::tensorflow-lite-micro@1.24.2 + components: + - component: tensorflow::Machine Learning:TensorFlow:Kernel Utils@1.24.2 + - component: tensorflow::Machine Learning:TensorFlow:Kernel&Reference@1.24.2 + - component: tensorflow::Machine Learning:TensorFlow:Testing@1.24.2 diff --git a/tensorflow-test/HelloWorld/HelloWorld.size+CM55.cprj b/tensorflow-test/HelloWorld/HelloWorld.size+CM55.cprj new file mode 100644 index 0000000..647167c --- /dev/null +++ b/tensorflow-test/HelloWorld/HelloWorld.size+CM55.cprj @@ -0,0 +1,71 @@ + + + + + + Automatically generated project + + + + + + + + + + + + + + + + + + + + + + + + + + PROJECT_GENERATION=1 + ./hello_world + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/ARMCM55_ac6.sct similarity index 83% rename from tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct rename to tensorflow-test/HelloWorld/RTE/Device/ARMCM55/ARMCM55_ac6.sct index c182aa8..6f84bd3 100644 --- a/tensorflow-test-ng/Layer/Target/CM33_FP_VHT_AC6/RTE/Device/IOTKit_CM33_FP_VHT/ac6_arm.sct +++ b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/ARMCM55_ac6.sct @@ -1,8 +1,8 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc -mcmse +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse /* @@ -15,8 +15,8 @@ ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x10000000 -#define __ROM_SIZE 0x00200000 +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration @@ -24,8 +24,8 @@ ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x38000000 -#define __RAM_SIZE 0x00200000 +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration @@ -33,12 +33,12 @@ ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 +#define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 -/*--------------------- CMSE Venner Configuration --------------------------- -; CMSE Venner Configuration -; CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32> +/*--------------------- CMSE Veneer Configuration --------------------------- +; CMSE Veneer Configuration +; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 @@ -78,7 +78,7 @@ #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- @@ -92,8 +92,12 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region .ANY (+XO) } - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) } #if __HEAP_SIZE > 0 @@ -111,7 +115,7 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Venners +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } diff --git a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 similarity index 83% rename from tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct rename to tensorflow-test/HelloWorld/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 index 6fa1f5b..6f84bd3 100644 --- a/tensorflow-test-ng/Layer/Target/CM23_VHT_AC6/RTE/Device/IOTKit_CM23_VHT/ac6_arm.sct +++ b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 @@ -1,8 +1,8 @@ -#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc ; command above MUST be in first line (no comment above!) ;Note: Add '-mcmse' to first line if your software model is "Secure Mode". -; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m23 -xc -mcmse +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse /* @@ -15,8 +15,8 @@ ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ -#define __ROM_BASE 0x10000000 -#define __ROM_SIZE 0x00200000 +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 /*--------------------- Embedded RAM Configuration --------------------------- ; RAM Configuration @@ -24,8 +24,8 @@ ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ -#define __RAM_BASE 0x38000000 -#define __RAM_SIZE 0x00200000 +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 /*--------------------- Stack / Heap Configuration --------------------------- ; Stack / Heap Configuration @@ -33,12 +33,12 @@ ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; *----------------------------------------------------------------------------*/ -#define __STACK_SIZE 0x00000400 +#define __STACK_SIZE 0x00000200 #define __HEAP_SIZE 0x00000C00 -/*--------------------- CMSE Venner Configuration --------------------------- -; CMSE Venner Configuration -; CMSE Venner Size (in Bytes) <0x0-0xFFFFFFFF:32> +/*--------------------- CMSE Veneer Configuration --------------------------- +; CMSE Veneer Configuration +; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> ; *----------------------------------------------------------------------------*/ #define __CMSEVENEER_SIZE 0x200 @@ -78,7 +78,7 @@ #define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) #define __RW_BASE ( __RAM_BASE ) -#define __RW_SIZE ( __RAM_SIZE - __STACK_SIZE - __HEAP_SIZE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) /*---------------------------------------------------------------------------- @@ -92,8 +92,12 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region .ANY (+XO) } - RW_RAM __RW_BASE __RW_SIZE { ; RW data - .ANY (+RW +ZI) + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) } #if __HEAP_SIZE > 0 @@ -111,7 +115,7 @@ LR_ROM __RO_BASE __RO_SIZE { ; load region size_region } #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Venners +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers ER_CMSE_VENEER __CV_BASE __CV_SIZE { *(Veneer$$CMSE) } diff --git a/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/startup_ARMCM55.c b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..0557c5f --- /dev/null +++ b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,164 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS-Core Device Startup File for Cortex-M55 Device + * @version V1.1.0 + * @date 16. December 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 new file mode 100644 index 0000000..0557c5f --- /dev/null +++ b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 @@ -0,0 +1,164 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS-Core Device Startup File for Cortex-M55 Device + * @version V1.1.0 + * @date 16. December 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/system_ARMCM55.c b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..dc329c7 --- /dev/null +++ b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,107 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.1.0 + * @date 28. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 new file mode 100644 index 0000000..dc329c7 --- /dev/null +++ b/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 @@ -0,0 +1,107 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.1.0 + * @date 28. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test-ng/Layer/App/Validation_Reference/RTE/Machine_Learning/debug_log.cpp b/tensorflow-test/HelloWorld/RTE/Machine_Learning/debug_log.cpp similarity index 63% rename from tensorflow-test-ng/Layer/App/Validation_Reference/RTE/Machine_Learning/debug_log.cpp rename to tensorflow-test/HelloWorld/RTE/Machine_Learning/debug_log.cpp index bc79d43..8d159c2 100644 --- a/tensorflow-test-ng/Layer/App/Validation_Reference/RTE/Machine_Learning/debug_log.cpp +++ b/tensorflow-test/HelloWorld/RTE/Machine_Learning/debug_log.cpp @@ -1,4 +1,4 @@ -/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,28 +16,54 @@ limitations under the License. // Implementation for the DebugLog() function that prints to the debug logger on // an generic Cortex-M device. +#include "tensorflow/lite/micro/debug_log.h" + #ifdef __cplusplus extern "C" { #endif // __cplusplus -#include "tensorflow/lite/micro/debug_log.h" - #include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" +#ifndef TF_LITE_STRIP_ERROR_STRINGS +#include +#endif + static DebugLogCallback debug_log_callback = nullptr; +namespace { + +void InvokeDebugLogCallback(const char* s) { + if (debug_log_callback != nullptr) { + debug_log_callback(s); + } +} + +} // namespace + void RegisterDebugLogCallback(void (*cb)(const char* s)) { debug_log_callback = cb; } -void DebugLog(const char* s) { +#include + +void DebugLog(const char* format, va_list args) { #ifndef TF_LITE_STRIP_ERROR_STRINGS - if (debug_log_callback != nullptr) { - debug_log_callback(s); - } + constexpr int kMaxLogLen = 256; + char log_buffer[kMaxLogLen]; + + vsnprintf(log_buffer, kMaxLogLen, format, args); + InvokeDebugLogCallback(log_buffer); #endif } +#ifndef TF_LITE_STRIP_ERROR_STRINGS +// Only called from MicroVsnprintf (micro_log.h) +int DebugVsnprintf(char* buffer, size_t buf_size, const char* format, + va_list vlist) { + return vsnprintf(buffer, buf_size, format, vlist); +} +#endif + #ifdef __cplusplus } // extern "C" #endif // __cplusplus diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/debug_log.cc b/tensorflow-test/HelloWorld/RTE/Machine_Learning/debug_log.cpp.base@1.24.2 similarity index 64% rename from tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/debug_log.cc rename to tensorflow-test/HelloWorld/RTE/Machine_Learning/debug_log.cpp.base@1.24.2 index bc79d43..b7182a5 100644 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/debug_log.cc +++ b/tensorflow-test/HelloWorld/RTE/Machine_Learning/debug_log.cpp.base@1.24.2 @@ -1,4 +1,4 @@ -/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -16,28 +16,52 @@ limitations under the License. // Implementation for the DebugLog() function that prints to the debug logger on // an generic Cortex-M device. +#include "tensorflow/lite/micro/debug_log.h" + #ifdef __cplusplus extern "C" { #endif // __cplusplus -#include "tensorflow/lite/micro/debug_log.h" - #include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" +#ifndef TF_LITE_STRIP_ERROR_STRINGS +#include +#endif + static DebugLogCallback debug_log_callback = nullptr; +namespace { + +void InvokeDebugLogCallback(const char* s) { + if (debug_log_callback != nullptr) { + debug_log_callback(s); + } +} + +} // namespace + void RegisterDebugLogCallback(void (*cb)(const char* s)) { debug_log_callback = cb; } -void DebugLog(const char* s) { +void DebugLog(const char* format, va_list args) { #ifndef TF_LITE_STRIP_ERROR_STRINGS - if (debug_log_callback != nullptr) { - debug_log_callback(s); - } + constexpr int kMaxLogLen = 256; + char log_buffer[kMaxLogLen]; + + vsnprintf(log_buffer, kMaxLogLen, format, args); + InvokeDebugLogCallback(log_buffer); #endif } +#ifndef TF_LITE_STRIP_ERROR_STRINGS +// Only called from MicroVsnprintf (micro_log.h) +int DebugVsnprintf(char* buffer, size_t buf_size, const char* format, + va_list vlist) { + return vsnprintf(buffer, buf_size, format, vlist); +} +#endif + #ifdef __cplusplus } // extern "C" #endif // __cplusplus diff --git a/tensorflow-test/HelloWorld/RTE/Machine_Learning/micro_time.cpp b/tensorflow-test/HelloWorld/RTE/Machine_Learning/micro_time.cpp new file mode 100644 index 0000000..17614af --- /dev/null +++ b/tensorflow-test/HelloWorld/RTE/Machine_Learning/micro_time.cpp @@ -0,0 +1,80 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "tensorflow/lite/micro/micro_time.h" + +// Set in micro/tools/make/targets/cortex_m_generic_makefile.inc. +// Needed for the DWT and PMU counters. +#include "RTE_Components.h" +#include CMSIS_device_header + +namespace tflite { + +#if 1 + +// Stub functions for the project_generation target since these will be replaced +// by the target-specific implementation in the overall infrastructure that the +// TFLM project generation will be a part of. +//int32_t ticks_per_second() { return 0; } +//uint32_t GetCurrentTimeTicks() { return 0; } + +#else + +uint32_t ticks_per_second() { return 0; } + +uint32_t GetCurrentTimeTicks() { + static bool is_initialized = false; + + if (!is_initialized) { +#if (!defined(TF_LITE_STRIP_ERROR_STRINGS) && !defined(ARMCM0) && \ + !defined(ARMCM0plus)) +#ifdef ARM_MODEL_USE_PMU_COUNTERS + ARM_PMU_Enable(); + DCB->DEMCR |= DCB_DEMCR_TRCENA_Msk; + + ARM_PMU_CYCCNT_Reset(); + ARM_PMU_CNTR_Enable(PMU_CNTENSET_CCNTR_ENABLE_Msk); + +#else +#ifdef ARMCM7 + DWT->LAR = 0xC5ACCE55; +#endif + DCB->DEMCR |= DCB_DEMCR_TRCENA_Msk; + + // Reset and DWT cycle counter. + DWT->CYCCNT = 0; + DWT->CTRL |= 1UL; + +#endif +#endif + + is_initialized = true; + } + +#if (!defined(TF_LITE_STRIP_ERROR_STRINGS) && !defined(ARMCM0) && \ + !defined(ARMCM0plus)) +#ifdef ARM_MODEL_USE_PMU_COUNTERS + return ARM_PMU_Get_CCNTR(); +#else + return DWT->CYCCNT; +#endif +#else + return 0; +#endif +} + +#endif // defined(PROJECT_GENERATION) + +} // namespace tflite diff --git a/tensorflow-test/HelloWorld/RTE/Machine_Learning/micro_time.cpp.base@1.24.2 b/tensorflow-test/HelloWorld/RTE/Machine_Learning/micro_time.cpp.base@1.24.2 new file mode 100644 index 0000000..49dcbf6 --- /dev/null +++ b/tensorflow-test/HelloWorld/RTE/Machine_Learning/micro_time.cpp.base@1.24.2 @@ -0,0 +1,80 @@ +/* Copyright 2022 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include "tensorflow/lite/micro/micro_time.h" + +// Set in micro/tools/make/targets/cortex_m_generic_makefile.inc. +// Needed for the DWT and PMU counters. +#include "RTE_Components.h" +#include CMSIS_device_header + +namespace tflite { + +#if defined(PROJECT_GENERATION) + +// Stub functions for the project_generation target since these will be replaced +// by the target-specific implementation in the overall infrastructure that the +// TFLM project generation will be a part of. +uint32_t ticks_per_second() { return 0; } +uint32_t GetCurrentTimeTicks() { return 0; } + +#else + +uint32_t ticks_per_second() { return 0; } + +uint32_t GetCurrentTimeTicks() { + static bool is_initialized = false; + + if (!is_initialized) { +#if (!defined(TF_LITE_STRIP_ERROR_STRINGS) && !defined(ARMCM0) && \ + !defined(ARMCM0plus)) +#ifdef ARM_MODEL_USE_PMU_COUNTERS + ARM_PMU_Enable(); + DCB->DEMCR |= DCB_DEMCR_TRCENA_Msk; + + ARM_PMU_CYCCNT_Reset(); + ARM_PMU_CNTR_Enable(PMU_CNTENSET_CCNTR_ENABLE_Msk); + +#else +#ifdef ARMCM7 + DWT->LAR = 0xC5ACCE55; +#endif + DCB->DEMCR |= DCB_DEMCR_TRCENA_Msk; + + // Reset and DWT cycle counter. + DWT->CYCCNT = 0; + DWT->CTRL |= 1UL; + +#endif +#endif + + is_initialized = true; + } + +#if (!defined(TF_LITE_STRIP_ERROR_STRINGS) && !defined(ARMCM0) && \ + !defined(ARMCM0plus)) +#ifdef ARM_MODEL_USE_PMU_COUNTERS + return ARM_PMU_Get_CCNTR(); +#else + return DWT->CYCCNT; +#endif +#else + return 0; +#endif +} + +#endif // defined(PROJECT_GENERATION) + +} // namespace tflite diff --git a/tensorflow-test/HelloWorld/RTE/Machine_Learning/system_setup.cpp b/tensorflow-test/HelloWorld/RTE/Machine_Learning/system_setup.cpp new file mode 100644 index 0000000..d6b0237 --- /dev/null +++ b/tensorflow-test/HelloWorld/RTE/Machine_Learning/system_setup.cpp @@ -0,0 +1,164 @@ +/* Copyright 2024 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#ifdef ETHOS_U +#include + +#include + +#include "ethosu_driver.h" +#include "pmu_ethosu.h" +#endif + +// This is set in micro/tools/make/targets/cortex_m_corstone_300_makefile.inc. +// It is needed for the calls to NVIC_SetVector()/NVIC_EnableIR(), +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "tensorflow/lite/micro/micro_log.h" +#include "tensorflow/lite/micro/micro_time.h" +#include "tensorflow/lite/micro/system_setup.h" + +#ifdef ETHOS_U + +bool npuPmuCycleCounterIsSet; +uint64_t npuPmuCycleCounter; + +extern "C" { +void ethosu_inference_begin(struct ethosu_driver* drv, void* userArg) { + // Enable PMU + ETHOSU_PMU_Enable(drv); + + // Enable cycle counter + ETHOSU_PMU_PMCCNTR_CFG_Set_Stop_Event(drv, ETHOSU_PMU_NPU_IDLE); + ETHOSU_PMU_PMCCNTR_CFG_Set_Start_Event(drv, ETHOSU_PMU_NPU_ACTIVE); + ETHOSU_PMU_CNTR_Enable(drv, ETHOSU_PMU_CCNT_Msk); + ETHOSU_PMU_CYCCNT_Reset(drv); + + // Reset all counters + ETHOSU_PMU_EVCNTR_ALL_Reset(drv); +} + +void ethosu_inference_end(struct ethosu_driver* drv, void* userArg) { + // Save cycle counter + npuPmuCycleCounter += ETHOSU_PMU_Get_CCNTR(drv); + npuPmuCycleCounterIsSet = true; + + // Disable PMU + ETHOSU_PMU_Disable(drv); +} +} +#endif + +namespace tflite { + +namespace { +#ifdef ETHOS_U +constexpr uint32_t kClocksPerSecond = 200e6; +#else +constexpr uint32_t kClocksPerSecond = 25e6; +#endif +} // namespace + +uint32_t ticks_per_second() { return kClocksPerSecond; } + +uint32_t GetCurrentTimeTicks() { +#if (!defined(TF_LITE_STRIP_ERROR_STRINGS)) +#ifdef ETHOS_U + uint32_t ticks = static_cast(npuPmuCycleCounter); + + // Note cycle counter will be reset here for next iteration + if (npuPmuCycleCounterIsSet) { + npuPmuCycleCounter = 0; + npuPmuCycleCounterIsSet = false; + } + + return ticks; +#else + +#if defined(ARMCM0) + return 0; +#else +#ifdef ARMCM55 + return ARM_PMU_Get_CCNTR(); +#else + return DWT->CYCCNT; +#endif +#endif + +#endif +#else + return 0; +#endif +} + +#ifdef ETHOS_U +#if defined(ETHOSU_FAST_MEMORY_SIZE) && ETHOSU_FAST_MEMORY_SIZE > 0 +__attribute__((aligned(16), section(".bss.ethosu_scratch"))) +uint8_t ethosu0_scratch[ETHOSU_FAST_MEMORY_SIZE]; +#else +#define ethosu0_scratch 0 +#define ETHOSU_FAST_MEMORY_SIZE 0 +#endif + +struct ethosu_driver ethosu0_driver; + +void ethosuIrqHandler0() { ethosu_irq_handler(ðosu0_driver); } +#endif + +extern "C" { +void uart_init(void); +} + +void InitializeTarget() { + uart_init(); + +#if (!defined(TF_LITE_STRIP_ERROR_STRINGS) && !defined(ARMCM0)) +#ifdef ARMCM55 + ARM_PMU_Enable(); + DCB->DEMCR |= DCB_DEMCR_TRCENA_Msk; + + ARM_PMU_CYCCNT_Reset(); + ARM_PMU_CNTR_Enable(PMU_CNTENSET_CCNTR_ENABLE_Msk); + +#else + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + + // Reset and enable DWT cycle counter. + DWT->CYCCNT = 0; + DWT->CTRL |= 1UL; + +#endif +#endif + +#ifdef ETHOS_U + constexpr int ethosu_base_address = 0x48102000; + constexpr int ethosu_irq = 56; + constexpr int ethosu_irq_priority = 5; + + // Initialize Ethos-U NPU driver. + if (ethosu_init(ðosu0_driver, reinterpret_cast(ethosu_base_address), + ethosu0_scratch, ETHOSU_FAST_MEMORY_SIZE, 1, 1)) { + MicroPrintf("Failed to initialize Ethos-U driver"); + return; + } + NVIC_SetVector(static_cast(ethosu_irq), + (uint32_t)ðosuIrqHandler0); + NVIC_SetPriority(static_cast(ethosu_irq), ethosu_irq_priority); + NVIC_EnableIRQ(static_cast(ethosu_irq)); +#endif +} + +} // namespace tflite \ No newline at end of file diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/system_setup.cc b/tensorflow-test/HelloWorld/RTE/Machine_Learning/system_setup.cpp.base@1.24.2 similarity index 74% rename from tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/system_setup.cc rename to tensorflow-test/HelloWorld/RTE/Machine_Learning/system_setup.cpp.base@1.24.2 index e803dc2..db4a100 100644 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/system_setup.cc +++ b/tensorflow-test/HelloWorld/RTE/Machine_Learning/system_setup.cpp.base@1.24.2 @@ -14,23 +14,12 @@ limitations under the License. ==============================================================================*/ #include "tensorflow/lite/micro/system_setup.h" -#include "stdio.h" -#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" - -extern "C" void serial_init (void); namespace tflite { -void debug_log_printf(const char* s) { - printf(s); -} - // To add an equivalent function for your own platform, create your own // implementation file, and place it in a subfolder named after the target. See // tensorflow/lite/micro/debug_log.cc for a similar example. -void InitializeTarget() { - serial_init(); - RegisterDebugLogCallback(debug_log_printf); - //debug_log_printf("Initialized UART and registered Callback.") -} +void InitializeTarget() {} + } // namespace tflite diff --git a/tensorflow-test/HelloWorld/RTE/_size_CM55/Pre_Include_Global.h b/tensorflow-test/HelloWorld/RTE/_size_CM55/Pre_Include_Global.h new file mode 100644 index 0000000..94d5edb --- /dev/null +++ b/tensorflow-test/HelloWorld/RTE/_size_CM55/Pre_Include_Global.h @@ -0,0 +1,17 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.1.0 + * + * Project: 'HelloWorld.size+CM55' + * Target: 'size+CM55' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* tensorflow::Machine Learning:TensorFlow:Kernel&Reference@1.24.2 */ +// enabling global pre includes + #define TF_LITE_STATIC_MEMORY 1 + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/tensorflow-test/HelloWorld/RTE/_size_CM55/RTE_Components.h b/tensorflow-test/HelloWorld/RTE/_size_CM55/RTE_Components.h new file mode 100644 index 0000000..f739c48 --- /dev/null +++ b/tensorflow-test/HelloWorld/RTE/_size_CM55/RTE_Components.h @@ -0,0 +1,32 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.1.0 + * + * Project: 'HelloWorld.size+CM55' + * Target: 'size+CM55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM55.h" + +/* tensorflow::Data Exchange:Serialization:flatbuffers&tensorflow@1.24.2 */ +#define RTE_DataExchange_Serialization_flatbuffers /* flatbuffers */ +/* tensorflow::Data Processing:Math:gemmlowp fixed-point&tensorflow@1.24.2 */ +#define RTE_DataExchange_Math_gemmlowp /* gemmlowp */ +/* tensorflow::Data Processing:Math:kissfft&tensorflow@1.24.2 */ +#define RTE_DataExchange_Math_kissfft /* kissfft */ +/* tensorflow::Data Processing:Math:ruy&tensorflow@1.24.2 */ +#define RTE_DataProcessing_Math_ruy /* ruy */ +/* tensorflow::Machine Learning:TensorFlow:Kernel&Reference@1.24.2 */ +#define RTE_ML_TF_LITE /* TF */ +/* tensorflow::Machine Learning:TensorFlow:Testing@1.24.2 */ +#define RTE_ML_TF_LITE /* TF */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/tensorflow-test/HelloWorld/hello_world/BUILD b/tensorflow-test/HelloWorld/hello_world/BUILD new file mode 100644 index 0000000..03c9484 --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/BUILD @@ -0,0 +1,84 @@ +# Description: +# TensorFlow Lite for Microcontrollers "hello world" example. +load("@rules_python//python:defs.bzl", "py_binary") +load("@tflm_pip_deps//:requirements.bzl", "requirement") +load( + "//tensorflow/lite/micro:build_def.bzl", + "micro_copts", +) + +package( + # Disabling layering_check because of http://b/177257332 + features = ["-layering_check"], + licenses = ["notice"], +) + +cc_library( + name = "model", + srcs = [ + "//tensorflow/lite/micro/examples/hello_world/models:generated_hello_world_float_model_cc", + "//tensorflow/lite/micro/examples/hello_world/models:generated_hello_world_int8_model_cc", + ], + hdrs = [ + "//tensorflow/lite/micro/examples/hello_world/models:generated_hello_world_float_model_hdr", + "//tensorflow/lite/micro/examples/hello_world/models:generated_hello_world_int8_model_hdr", + ], + copts = micro_copts(), +) + +cc_test( + name = "hello_world_test", + srcs = [ + "hello_world_test.cc", + ], + deps = [ + ":model", + "//tensorflow/lite/micro:micro_framework", + "//tensorflow/lite/micro:micro_log", + "//tensorflow/lite/micro:micro_profiler", + "//tensorflow/lite/micro:op_resolvers", + "//tensorflow/lite/micro:recording_allocators", + "//tensorflow/lite/micro/testing:micro_test", + "//tensorflow/lite/schema:schema_fbs", + ], +) + +py_binary( + name = "evaluate", + srcs = ["evaluate.py"], + data = ["//tensorflow/lite/micro/examples/hello_world/models:hello_world_float.tflite"], + python_version = "PY3", + srcs_version = "PY3", + deps = [ + "@absl_py//absl:app", + "@absl_py//absl/flags", + "@absl_py//absl/logging", + requirement("numpy"), + requirement("tensorflow-cpu"), + "//python/tflite_micro:runtime", + ], +) + +py_binary( + name = "evaluate_test", + srcs = ["evaluate_test.py"], + data = [ + "//tensorflow/lite/micro/examples/hello_world/models:hello_world_float.tflite", + "//tensorflow/lite/micro/examples/hello_world/models:hello_world_int8.tflite", + ], + python_version = "PY3", + srcs_version = "PY3", + deps = [ + ":evaluate", + ], +) + +py_binary( + name = "train", + srcs = ["train.py"], + srcs_version = "PY3", + deps = [ + requirement("numpy"), + requirement("tensorflow-cpu"), + ], +) diff --git a/tensorflow-test/HelloWorld/hello_world/Makefile.inc b/tensorflow-test/HelloWorld/hello_world/Makefile.inc new file mode 100644 index 0000000..bfcd52e --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/Makefile.inc @@ -0,0 +1,37 @@ +HELLO_WORLD_TEST_SRCS := \ +$(TENSORFLOW_ROOT)tensorflow/lite/micro/examples/hello_world/hello_world_test.cc + +HELLO_WORLD_SRCS := \ +$(TENSORFLOW_ROOT)tensorflow/lite/micro/examples/hello_world/hello_world_test.cc + +HELLO_WORLD_HDRS := + +HELLO_WORLD_GENERATOR_INPUTS := \ +$(TENSORFLOW_ROOT)tensorflow/lite/micro/examples/hello_world/models/hello_world_float.tflite \ +$(TENSORFLOW_ROOT)tensorflow/lite/micro/examples/hello_world/models/hello_world_int8.tflite + +HELLO_WORLD_GENERATED_SRCS := \ +$(GENERATED_SRCS_DIR)$(TENSORFLOW_ROOT)tensorflow/lite/micro/examples/hello_world/models/hello_world_float_model_data.cc \ +$(GENERATED_SRCS_DIR)$(TENSORFLOW_ROOT)tensorflow/lite/micro/examples/hello_world/models/hello_world_int8_model_data.cc + +HELLO_WORLD_GENERATED_HDRS := \ +$(GENERATED_SRCS_DIR)$(TENSORFLOW_ROOT)tensorflow/lite/micro/examples/hello_world/models/hello_world_float_model_data.h \ +$(GENERATED_SRCS_DIR)$(TENSORFLOW_ROOT)tensorflow/lite/micro/examples/hello_world/models/hello_world_int8_model_data.h + +# Tests loading and running the sine model. +$(eval $(call microlite_test,hello_world_test,\ +$(HELLO_WORLD_TEST_SRCS),,$(HELLO_WORLD_GENERATOR_INPUTS))) + +# Builds a standalone binary. +$(eval $(call microlite_test,hello_world,\ +$(HELLO_WORLD_SRCS),,$(HELLO_WORLD_GENERATOR_INPUTS))) + +# Add sources and headers generated from $(HELLO_WORLD_GENERATOR_INPUTS). +HELLO_WORLD_SRCS += $(HELLO_WORLD_GENERATED_SRCS) +HELLO_WORLD_HDRS += $(HELLO_WORLD_GENERATED_HDRS) + +list_hello_world_example_sources: + @echo $(HELLO_WORLD_SRCS) + +list_hello_world_example_headers: + @echo $(HELLO_WORLD_HDRS) diff --git a/tensorflow-test/HelloWorld/hello_world/README.md b/tensorflow-test/HelloWorld/hello_world/README.md new file mode 100644 index 0000000..8277750 --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/README.md @@ -0,0 +1,94 @@ + + +# Hello World Example + +This example is designed to demonstrate the absolute basics of using [TensorFlow +Lite for Microcontrollers](https://www.tensorflow.org/lite/microcontrollers). +It includes the full end-to-end workflow of training a model, converting it for +use with TensorFlow Lite for Microcontrollers for running inference on a +microcontroller. + +## Table of contents + +- [Run the evaluate.py script on a development machine](#run-the-evaluate-script-on-a-development-machine) +- [Run the tests on a development machine](#run-the-tests-on-a-development-machine) +- [Train your own model](#train-your-own-model) + +## Run the evaluate.py script on a development machine +The evaluate.py script runs the hello_world.tflite model with x_values in the +range of [0, 2*PI]. The script plots a diagram of the predicted value of sinwave +using TFLM interpreter and compare that prediction with the actual value +generated by the numpy lib. +```bash +bazel build tensorflow/lite/micro/examples/hello_world:evaluate +bazel run tensorflow/lite/micro/examples/hello_world:evaluate +bazel run tensorflow/lite/micro/examples/hello_world:evaluate -- --use_tflite +``` +![TFLM hello_world sinwave prediction VS actual values](images/hello_world_tflm.png) ![TFLM hello_world sinwave prediction VS actual values](images/hello_world_tflite.png) + +## Run the evaluate_test.py script on a development machine +These tests verify the input/output as well as the prediction of the +hello_world.tflite model. There is a test to also verify the correctness of +the model by running both TFLM and TFlite interpreter and then comparing the +prediction from both interpreters. +```bash +bazel build tensorflow/lite/micro/examples/hello_world:evaluate_test +bazel run tensorflow/lite/micro/examples/hello_world:evaluate_test +``` + +## Run the tests on a development machine + +Run the cc test using bazel +```bash +bazel run tensorflow/lite/micro/examples/hello_world:hello_world_test +``` +And to run it using make +```bash +make -f tensorflow/lite/micro/tools/make/Makefile test_hello_world_test +``` + +The source for the test is [hello_world_test.cc](hello_world_test.cc). +It's a fairly small amount of code that creates an interpreter, gets a handle to +a model that's been compiled into the program, and then invokes the interpreter +with the model and sample inputs. + +## Train your own model + +So far you have used an existing trained model to run inference on +microcontrollers. If you wish to train your own model, here are the scripts +that can help you to achieve that. + +```bash +bazel build tensorflow/lite/micro/examples/hello_world:train +``` +And to run it +```bash +bazel-bin/tensorflow/lite/micro/examples/hello_world/train --save_tf_model +--save_dir=/tmp/model_created/ +``` +The above script will create a TF model and TFlite model inside the +`/tmp/model_created` directory. + +Now the above model is a `float` model. Means it can take floating point input +and can produce floating point output. + +If we want a fully quantized model we can use the `ptq.py` script inside the +quantization directory. The `ptq.py` script can take a floating point TF model +and can produce a quantized model. + +Build the `ptq.py` script like +```bash +bazel build tensorflow/lite/micro/examples/hello_world/quantization:ptq +``` + +Then we can run the `ptq` script to convert the float model to quant model as +follows. Note that we are using the directory (`/tmp/model_created`) of the +TF model as the source_model_dir here. The quant model +(named `hello_world_int8.tflite`) will be created inside the target_dir. +The `ptq.py` script will convert the `TF model` found inside the +`/tmp/model_created` folder and convert it to a `int8` TFlite model. +```bash +bazel-bin/tensorflow/lite/micro/examples/hello_world/quantization/ptq +--source_model_dir=/tmp/model_created --target_dir=/tmp/quant_model/ +``` + diff --git a/tensorflow-test/HelloWorld/hello_world/evaluate.py b/tensorflow-test/HelloWorld/hello_world/evaluate.py new file mode 100644 index 0000000..8b6f948 --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/evaluate.py @@ -0,0 +1,140 @@ +# Copyright 2023 The TensorFlow Authors. All Rights Reserved. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +import tensorflow as tf +from absl import app +from absl import flags +import numpy as np +import matplotlib.pyplot as plt +from tensorflow.python.platform import resource_loader +from tflite_micro.python.tflite_micro import runtime + +_USE_TFLITE_INTERPRETER = flags.DEFINE_bool( + 'use_tflite', + False, + 'Inference with the TF Lite interpreter instead of the TFLM interpreter', +) + +_PREFIX_PATH = resource_loader.get_path_to_datafile('') + + +def invoke_tflm_interpreter(input_shape, interpreter, x_value, input_index, + output_index): + input_data = np.reshape(x_value, input_shape) + interpreter.set_input(input_data, input_index) + interpreter.invoke() + y_quantized = np.reshape(interpreter.get_output(output_index), -1)[0] + return y_quantized + + +def invoke_tflite_interpreter(input_shape, interpreter, x_value, input_index, + output_index): + input_data = np.reshape(x_value, input_shape) + interpreter.set_tensor(input_index, input_data) + interpreter.invoke() + tflite_output = interpreter.get_tensor(output_index) + y_quantized = np.reshape(tflite_output, -1)[0] + return y_quantized + + +# Generate a list of 1000 random floats in the range of 0 to 2*pi. +def generate_random_int8_input(sample_count=1000): + # Generate a uniformly distributed set of random numbers in the range from + # 0 to 2Ï€, which covers a complete sine wave oscillation + np.random.seed(42) + x_values = np.random.uniform(low=0, high=2 * np.pi, + size=sample_count).astype(np.int8) + return x_values + + +# Generate a list of 1000 random floats in the range of 0 to 2*pi. +def generate_random_float_input(sample_count=1000): + # Generate a uniformly distributed set of random numbers in the range from + # 0 to 2Ï€, which covers a complete sine wave oscillation + np.random.seed(42) + x_values = np.random.uniform(low=0, high=2 * np.pi, + size=sample_count).astype(np.float32) + return x_values + + +# Invoke the tflm interpreter with x_values in the range of [0, 2*PI] and +# returns the prediction of the interpreter. +def get_tflm_prediction(model_path, x_values): + # Create the tflm interpreter + tflm_interpreter = runtime.Interpreter.from_file(model_path) + + input_shape = np.array(tflm_interpreter.get_input_details(0).get('shape')) + + y_predictions = np.empty(x_values.size, dtype=np.float32) + + for i, x_value in enumerate(x_values): + y_predictions[i] = invoke_tflm_interpreter(input_shape, + tflm_interpreter, + x_value, + input_index=0, + output_index=0) + return y_predictions + + +# Invoke the tflite interpreter with x_values in the range of [0, 2*PI] and +# returns the prediction of the interpreter. +def get_tflite_prediction(model_path, x_values): + # TFLite interpreter + tflite_interpreter = tf.lite.Interpreter( + model_path=model_path, + experimental_op_resolver_type=tf.lite.experimental.OpResolverType. + BUILTIN_REF, + ) + tflite_interpreter.allocate_tensors() + + input_details = tflite_interpreter.get_input_details()[0] + output_details = tflite_interpreter.get_output_details()[0] + input_shape = np.array(input_details.get('shape')) + + y_predictions = np.empty(x_values.size, dtype=np.float32) + + for i, x_value in enumerate(x_values): + y_predictions[i] = invoke_tflite_interpreter( + input_shape, + tflite_interpreter, + x_value, + input_details['index'], + output_details['index'], + ) + return y_predictions + + +def main(_): + model_path = os.path.join(_PREFIX_PATH, 'models/hello_world_float.tflite') + + x_values = generate_random_float_input() + + # Calculate the corresponding sine values + y_true_values = np.sin(x_values).astype(np.float32) + + if _USE_TFLITE_INTERPRETER.value: + y_predictions = get_tflite_prediction(model_path, x_values) + plt.plot(x_values, y_predictions, 'b.', label='TFLite Prediction') + else: + y_predictions = get_tflm_prediction(model_path, x_values) + plt.plot(x_values, y_predictions, 'b.', label='TFLM Prediction') + + plt.plot(x_values, y_true_values, 'r.', label='Actual values') + plt.legend() + plt.show() + + +if __name__ == '__main__': + app.run(main) diff --git a/tensorflow-test/HelloWorld/hello_world/evaluate_test.py b/tensorflow-test/HelloWorld/hello_world/evaluate_test.py new file mode 100644 index 0000000..6de8490 --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/evaluate_test.py @@ -0,0 +1,64 @@ +# Copyright 2023 The TensorFlow Authors. All Rights Reserved. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +import numpy as np + +from tensorflow.python.framework import test_util +from tensorflow.python.platform import resource_loader +from tensorflow.python.platform import test +from tflite_micro.python.tflite_micro import runtime +from tflite_micro.tensorflow.lite.micro.examples.hello_world import evaluate + +PREFIX_PATH = resource_loader.get_path_to_datafile('') + + +class HelloWorldFloatModelTest(test_util.TensorFlowTestCase): + model_path = os.path.join(PREFIX_PATH, 'models/hello_world_float.tflite') + input_shape = (1, 1) + output_shape = (1, 1) + tflm_interpreter = runtime.Interpreter.from_file(model_path) + + def test_compare_with_tflite(self): + x_values = evaluate.generate_random_float_input() + + tflm_y_predictions = evaluate.get_tflm_prediction(self.model_path, + x_values) + + tflite_y_predictions = evaluate.get_tflite_prediction( + self.model_path, x_values) + + self.assertAllEqual(tflm_y_predictions, tflite_y_predictions) + + +class HelloWorldQuantModelTest(test_util.TensorFlowTestCase): + model_path = os.path.join(PREFIX_PATH, 'models/hello_world_int8.tflite') + input_shape = (1, 1) + output_shape = (1, 1) + tflm_interpreter = runtime.Interpreter.from_file(model_path) + + def test_compare_with_tflite(self): + x_values = evaluate.generate_random_int8_input() + + tflm_y_predictions = evaluate.get_tflm_prediction(self.model_path, + x_values) + + tflite_y_predictions = evaluate.get_tflite_prediction( + self.model_path, x_values) + + self.assertAllEqual(tflm_y_predictions, tflite_y_predictions) + + +if __name__ == '__main__': + test.main() diff --git a/tensorflow-test/HelloWorld/hello_world/hello_world_test.cpp b/tensorflow-test/HelloWorld/hello_world/hello_world_test.cpp new file mode 100644 index 0000000..5665ecf --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/hello_world_test.cpp @@ -0,0 +1,159 @@ +/* Copyright 2023 The TensorFlow Authors. All Rights Reserved. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +==============================================================================*/ + +#include + +#include "tensorflow/lite/core/c/common.h" +#include "./models/hello_world_float_model_data.h" +#include "./models/hello_world_int8_model_data.h" +#include "tensorflow/lite/micro/micro_interpreter.h" +#include "tensorflow/lite/micro/micro_log.h" +#include "tensorflow/lite/micro/micro_mutable_op_resolver.h" +#include "tensorflow/lite/micro/micro_profiler.h" +#include "tensorflow/lite/micro/recording_micro_interpreter.h" +#include "tensorflow/lite/micro/system_setup.h" +#include "tensorflow/lite/schema/schema_generated.h" + +namespace { +using HelloWorldOpResolver = tflite::MicroMutableOpResolver<1>; + +TfLiteStatus RegisterOps(HelloWorldOpResolver& op_resolver) { + TF_LITE_ENSURE_STATUS(op_resolver.AddFullyConnected()); + return kTfLiteOk; +} +} // namespace + +TfLiteStatus ProfileMemoryAndLatency() { + tflite::MicroProfiler profiler; + HelloWorldOpResolver op_resolver; + TF_LITE_ENSURE_STATUS(RegisterOps(op_resolver)); + + // Arena size just a round number. The exact arena usage can be determined + // using the RecordingMicroInterpreter. + constexpr int kTensorArenaSize = 3000; + uint8_t tensor_arena[kTensorArenaSize]; + constexpr int kNumResourceVariables = 24; + + tflite::RecordingMicroAllocator* allocator( + tflite::RecordingMicroAllocator::Create(tensor_arena, kTensorArenaSize)); + tflite::RecordingMicroInterpreter interpreter( + tflite::GetModel(g_hello_world_float_model_data), op_resolver, allocator, + tflite::MicroResourceVariables::Create(allocator, kNumResourceVariables), + &profiler); + + TF_LITE_ENSURE_STATUS(interpreter.AllocateTensors()); + TFLITE_CHECK_EQ(interpreter.inputs_size(), 1); + interpreter.input(0)->data.f[0] = 1.f; + TF_LITE_ENSURE_STATUS(interpreter.Invoke()); + + MicroPrintf(""); // Print an empty new line + profiler.LogTicksPerTagCsv(); + + MicroPrintf(""); // Print an empty new line + interpreter.GetMicroAllocator().PrintAllocations(); + return kTfLiteOk; +} + +TfLiteStatus LoadFloatModelAndPerformInference() { + const tflite::Model* model = + ::tflite::GetModel(g_hello_world_float_model_data); + TFLITE_CHECK_EQ(model->version(), TFLITE_SCHEMA_VERSION); + + HelloWorldOpResolver op_resolver; + TF_LITE_ENSURE_STATUS(RegisterOps(op_resolver)); + + // Arena size just a round number. The exact arena usage can be determined + // using the RecordingMicroInterpreter. + constexpr int kTensorArenaSize = 3000; + uint8_t tensor_arena[kTensorArenaSize]; + + tflite::MicroInterpreter interpreter(model, op_resolver, tensor_arena, + kTensorArenaSize); + TF_LITE_ENSURE_STATUS(interpreter.AllocateTensors()); + + // Check if the predicted output is within a small range of the + // expected output + float epsilon = 0.05f; + constexpr int kNumTestValues = 4; + float golden_inputs[kNumTestValues] = {0.f, 1.f, 3.f, 5.f}; + + for (int i = 0; i < kNumTestValues; ++i) { + interpreter.input(0)->data.f[0] = golden_inputs[i]; + TF_LITE_ENSURE_STATUS(interpreter.Invoke()); + float y_pred = interpreter.output(0)->data.f[0]; + TFLITE_CHECK_LE(abs(sin(golden_inputs[i]) - y_pred), epsilon); + } + + return kTfLiteOk; +} + +TfLiteStatus LoadQuantModelAndPerformInference() { + // Map the model into a usable data structure. This doesn't involve any + // copying or parsing, it's a very lightweight operation. + const tflite::Model* model = + ::tflite::GetModel(g_hello_world_int8_model_data); + TFLITE_CHECK_EQ(model->version(), TFLITE_SCHEMA_VERSION); + + HelloWorldOpResolver op_resolver; + TF_LITE_ENSURE_STATUS(RegisterOps(op_resolver)); + + // Arena size just a round number. The exact arena usage can be determined + // using the RecordingMicroInterpreter. + constexpr int kTensorArenaSize = 3000; + uint8_t tensor_arena[kTensorArenaSize]; + + tflite::MicroInterpreter interpreter(model, op_resolver, tensor_arena, + kTensorArenaSize); + + TF_LITE_ENSURE_STATUS(interpreter.AllocateTensors()); + + TfLiteTensor* input = interpreter.input(0); + TFLITE_CHECK_NE(input, nullptr); + + TfLiteTensor* output = interpreter.output(0); + TFLITE_CHECK_NE(output, nullptr); + + float output_scale = output->params.scale; + int output_zero_point = output->params.zero_point; + + // Check if the predicted output is within a small range of the + // expected output + float epsilon = 0.05; + + constexpr int kNumTestValues = 4; + float golden_inputs_float[kNumTestValues] = {0.77, 1.57, 2.3, 3.14}; + + // The int8 values are calculated using the following formula + // (golden_inputs_float[i] / input->params.scale + input->params.scale) + int8_t golden_inputs_int8[kNumTestValues] = {-96, -63, -34, 0}; + + for (int i = 0; i < kNumTestValues; ++i) { + input->data.int8[0] = golden_inputs_int8[i]; + TF_LITE_ENSURE_STATUS(interpreter.Invoke()); + float y_pred = (output->data.int8[0] - output_zero_point) * output_scale; + TFLITE_CHECK_LE(abs(sin(golden_inputs_float[i]) - y_pred), epsilon); + } + + return kTfLiteOk; +} + +int main(int argc, char* argv[]) { + tflite::InitializeTarget(); + TF_LITE_ENSURE_STATUS(ProfileMemoryAndLatency()); + TF_LITE_ENSURE_STATUS(LoadFloatModelAndPerformInference()); + TF_LITE_ENSURE_STATUS(LoadQuantModelAndPerformInference()); + MicroPrintf("~~~ALL TESTS PASSED~~~\n"); + return kTfLiteOk; +} diff --git a/tensorflow-test/HelloWorld/hello_world/images/hello_world_tflite.png b/tensorflow-test/HelloWorld/hello_world/images/hello_world_tflite.png new file mode 100644 index 0000000000000000000000000000000000000000..56b222169864b2bbec16a3882dd63c96132b9d2c GIT binary patch literal 27649 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0000000..4c9441b --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/models/BUILD @@ -0,0 +1,40 @@ +load("//tensorflow/lite/micro:build_def.bzl", "generate_cc_arrays") + +package( + default_visibility = ["//visibility:public"], +) + +exports_files( + srcs = [ + "hello_world_float.tflite", + "hello_world_int8.tflite", + ], + visibility = [ + "//codegen/examples/hello_world:__subpackages__", + "//tensorflow/lite/micro/examples/hello_world:__subpackages__", + ], +) + +generate_cc_arrays( + name = "generated_hello_world_float_model_cc", + src = "hello_world_float.tflite", + out = "hello_world_float_model_data.cc", +) + +generate_cc_arrays( + name = "generated_hello_world_float_model_hdr", + src = "hello_world_float.tflite", + out = "hello_world_float_model_data.h", +) + +generate_cc_arrays( + name = "generated_hello_world_int8_model_cc", + src = "hello_world_int8.tflite", + out = "hello_world_int8_model_data.cc", +) + +generate_cc_arrays( + name = "generated_hello_world_int8_model_hdr", + src = "hello_world_int8.tflite", + out = "hello_world_int8_model_data.h", +) diff --git a/tensorflow-test/HelloWorld/hello_world/models/hello_world_float.tflite b/tensorflow-test/HelloWorld/hello_world/models/hello_world_float.tflite new file mode 100644 index 0000000000000000000000000000000000000000..f741b3a7b6b63a476832b4f95c3199b7b8b7e17e GIT binary patch literal 3164 zcmaJ@2~?9;7XAen6pE-38D%Ug~4T~F81OYv+g%wwOI1cxM(L6KHzHaE1?jP48RQIF>rpCITI0Kr%ttM7U27dI*9O!HyJcY1oC}#B!mRWfiaK zMI&C%>wE~k35lA7@hxa%~9qJ+o$Zitq6p5KZp-jrlU*z5om~0Df6IPGMo_| ziBn68@VcE3%pUsyY`28M+@LGiG}r`&+TD0<=YE)zD&pGsY)C(tiH^G#;>(rZ*xhLv ze%0b6?Vh|@%usB>?~Ko+5WNX9Vr`{W^*8a$x)O-}F;$$H{4ddv*;3qnl?+a}4-s7| zdy3~r7UGQ)cIdjW6b;!Q`sP>P6FvJLPz<&CS)B6pP;u(9Y7knw6dx|j1jB+IQq+B4 zoEURnvfG|4)l?@y?$az-Qtd4bmkogYb7iRfS^X;yS7FWH)dKekx9Q90s|kMq#p6 z1{1eF7u^@zkDo} zt2Uya`#nYJ<1`o{SHk=KYcM+RaB+*EQTEs_!T7CdkTJH1!?__aQNkZIIdWM!jGSz{e=|lH|+yu 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diff --git a/tensorflow-test/HelloWorld/hello_world/models/hello_world_float_model_data.h b/tensorflow-test/HelloWorld/hello_world/models/hello_world_float_model_data.h new file mode 100644 index 0000000..63e0abb --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/models/hello_world_float_model_data.h @@ -0,0 +1,4 @@ +#include + +extern const unsigned int g_hello_world_float_model_data_size; +extern const unsigned char g_hello_world_float_model_data[]; diff --git a/tensorflow-test/HelloWorld/hello_world/models/hello_world_int8.tflite b/tensorflow-test/HelloWorld/hello_world/models/hello_world_int8.tflite new file mode 100644 index 0000000000000000000000000000000000000000..9a379ea9d93ed1662117d4ebc659e3cc8667f192 GIT binary patch literal 2704 zcmai0YfMvT82(BtZK2AoK&i;MbX*bxf+W+?EHKf{gv&%m+?J)Q>p`28>Yyb{wgi6| zXBK}hi$7epnEfz|TlUkKZCT7N22EUMf*`G7P(Tsv2pFz%_B`kGbgTmVnkV1oeZTki zz3dh;(7asZHc7vmR?_iV%NeF$j!ce+DoBIv^boA_cR0 z8?2%p$Op)i2J}eXyv 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g_hello_world_int8_model_data_size = 2704; +alignas(16) const unsigned char g_hello_world_int8_model_data[] = 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diff --git a/tensorflow-test/HelloWorld/hello_world/models/hello_world_int8_model_data.h b/tensorflow-test/HelloWorld/hello_world/models/hello_world_int8_model_data.h new file mode 100644 index 0000000..c0c87a5 --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/models/hello_world_int8_model_data.h @@ -0,0 +1,4 @@ +#include + +extern const unsigned int g_hello_world_int8_model_data_size; +extern const unsigned char g_hello_world_int8_model_data[]; diff --git a/tensorflow-test/HelloWorld/hello_world/quantization/BUILD b/tensorflow-test/HelloWorld/hello_world/quantization/BUILD new file mode 100644 index 0000000..db9df23 --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/quantization/BUILD @@ -0,0 +1,18 @@ +load("@rules_python//python:defs.bzl", "py_binary") +load("@tflm_pip_deps//:requirements.bzl", "requirement") + +py_binary( + name = "ptq", + srcs = ["ptq.py"], + data = ["//tensorflow/lite/micro/examples/hello_world/models:hello_world_float.tflite"], + python_version = "PY3", + srcs_version = "PY3", + deps = [ + "@absl_py//absl:app", + "@absl_py//absl/flags", + "@absl_py//absl/logging", + requirement("numpy"), + requirement("tensorflow-cpu"), + "//python/tflite_micro:runtime", + ], +) diff --git a/tensorflow-test/HelloWorld/hello_world/quantization/ptq.py b/tensorflow-test/HelloWorld/hello_world/quantization/ptq.py new file mode 100644 index 0000000..bfab0d0 --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/quantization/ptq.py @@ -0,0 +1,116 @@ +# Copyright 2023 The TensorFlow Authors. All Rights Reserved. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= +"""This script can create a quant(int8) model from the saved TF model. + +Run: +Build the train.py script +`bazel build tensorflow/lite/micro/examples/hello_world/quantization:train` + +The following command first creates the trained TF float model that we will quantize later +`bazel-bin/tensorflow/lite/micro/examples/hello_world/train --save_tf_model --save_dir=/tmp/float_model/` + +Build the ptq.py script +`bazel build tensorflow/lite/micro/examples/hello_world/quantization:ptq` + +Then we can run the ptq script to convert the float model to quant model as follows. +Note that we are using the directory of the TF model as the source_model_dir here. +The quant model (named hello_world_int8.tflite) will be created inside the target_dir. +`bazel-bin/tensorflow/lite/micro/examples/hello_world/quantization/ptq --source_model_dir=/tmp/float_model --target_dir=/tmp/quant_model/` +""" +import math +import os + +from absl import app +from absl import flags +from absl import logging +import numpy as np +import tensorflow as tf + +FLAGS = flags.FLAGS + +flags.DEFINE_string("source_model_dir", "/tmp/float_model/", + "the directory where the trained model can be found.") +flags.DEFINE_string("target_dir", "/tmp/quant_model", + "the directory to save the quant model.") + + +def get_data(): + """ + The code will generate a set of random `x` values + """ + # Generate a uniformly distributed set of random numbers in the range from + # 0 to 2Ï€, which covers a complete sine wave oscillation + x_values = np.random.uniform(low=0, high=2 * math.pi, + size=1000).astype(np.float32) + + # Shuffle the values to guarantee they're not in order + np.random.shuffle(x_values) + + return x_values + + +def save_tflite_model(tflite_model, target_dir, model_name): + """save the converted tflite model + Args: + tflite_model (binary): the converted model in serialized format. + save_dir (str): the save directory + model_name (str): model name to be saved + """ + if not os.path.exists(target_dir): + os.makedirs(target_dir) + save_path = os.path.join(target_dir, model_name) + with open(save_path, "wb") as f: + f.write(tflite_model) + logging.info("Tflite model saved to %s", target_dir) + + +def convert_quantized_tflite_model(source_model_dir, x_values): + """Convert the save TF model to tflite model, then save it as .tflite + flatbuffer format + + Args: + source_model_dir (tf.keras.Model): the trained hello_world flaot Model dir + x_train (numpy.array): list of the training data + + Returns: + The converted model in serialized format. + """ + + # Convert the model to the TensorFlow Lite format with quantization + def representative_dataset(num_samples=500): + for i in range(num_samples): + yield [x_values[i].reshape(1, 1)] + + converter = tf.lite.TFLiteConverter.from_saved_model(source_model_dir) + converter.optimizations = [tf.lite.Optimize.DEFAULT] + converter.target_spec.supported_ops = [tf.lite.OpsSet.TFLITE_BUILTINS_INT8] + converter.inference_input_type = tf.int8 + converter.inference_output_type = tf.int8 + converter.representative_dataset = representative_dataset + tflite_model = converter.convert() + return tflite_model + + +def main(_): + x_values = get_data() + quantized_tflite_model = convert_quantized_tflite_model( + FLAGS.source_model_dir, x_values) + save_tflite_model(quantized_tflite_model, + FLAGS.target_dir, + model_name="hello_world_int8.tflite") + + +if __name__ == "__main__": + app.run(main) \ No newline at end of file diff --git a/tensorflow-test/HelloWorld/hello_world/train.py b/tensorflow-test/HelloWorld/hello_world/train.py new file mode 100644 index 0000000..3a2322c --- /dev/null +++ b/tensorflow-test/HelloWorld/hello_world/train.py @@ -0,0 +1,141 @@ +# Copyright 2023 The TensorFlow Authors. All Rights Reserved. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# ============================================================================= +"""hellow_world model training for sinwave recognition + +Run: +`bazel build tensorflow/lite/micro/examples/hello_world:train` +`bazel-bin/tensorflow/lite/micro/examples/hello_world/train --save_tf_model --save_dir=/tmp/model_created/` +""" +import math +import os + +from absl import app +from absl import flags +from absl import logging +import numpy as np +import tensorflow as tf + +FLAGS = flags.FLAGS + +flags.DEFINE_integer("epochs", 500, "number of epochs to train the model.") +flags.DEFINE_string("save_dir", "/tmp/hello_world_models", + "the directory to save the trained model.") +flags.DEFINE_boolean("save_tf_model", False, + "store the original unconverted tf model.") + + +def get_data(): + """ + The code will generate a set of random `x` values,calculate their sine + values. + """ + # Generate a uniformly distributed set of random numbers in the range from + # 0 to 2Ï€, which covers a complete sine wave oscillation + x_values = np.random.uniform(low=0, high=2 * math.pi, + size=1000).astype(np.float32) + + # Shuffle the values to guarantee they're not in order + np.random.shuffle(x_values) + + # Calculate the corresponding sine values + y_values = np.sin(x_values).astype(np.float32) + + return (x_values, y_values) + + +def create_model() -> tf.keras.Model: + model = tf.keras.Sequential() + + # First layer takes a scalar input and feeds it through 16 "neurons". The + # neurons decide whether to activate based on the 'relu' activation function. + model.add(tf.keras.layers.Dense(16, activation='relu', input_shape=(1, ))) + + # The new second and third layer will help the network learn more complex + # representations + model.add(tf.keras.layers.Dense(16, activation='relu')) + + # Final layer is a single neuron, since we want to output a single value + model.add(tf.keras.layers.Dense(1)) + + # Compile the model using the standard 'adam' optimizer and the mean squared + # error or 'mse' loss function for regression. + model.compile(optimizer='adam', loss='mse', metrics=['mae']) + + return model + + +def convert_tflite_model(model): + """Convert the save TF model to tflite model, then save it as .tflite flatbuffer format + Args: + model (tf.keras.Model): the trained hello_world Model + Returns: + The converted model in serialized format. + """ + converter = tf.lite.TFLiteConverter.from_keras_model(model) + tflite_model = converter.convert() + return tflite_model + + +def save_tflite_model(tflite_model, save_dir, model_name): + """save the converted tflite model + Args: + tflite_model (binary): the converted model in serialized format. + save_dir (str): the save directory + model_name (str): model name to be saved + """ + if not os.path.exists(save_dir): + os.makedirs(save_dir) + save_path = os.path.join(save_dir, model_name) + with open(save_path, "wb") as f: + f.write(tflite_model) + logging.info("Tflite model saved to %s", save_dir) + + +def train_model(epochs, x_values, y_values): + """Train keras hello_world model + Args: epochs (int) : number of epochs to train the model + x_train (numpy.array): list of the training data + y_train (numpy.array): list of the corresponding array + Returns: + tf.keras.Model: A trained keras hello_world model + """ + model = create_model() + model.fit(x_values, + y_values, + epochs=epochs, + validation_split=0.2, + batch_size=64, + verbose=2) + + if FLAGS.save_tf_model: + model.save(FLAGS.save_dir, save_format="tf") + logging.info("TF model saved to %s", FLAGS.save_dir) + + return model + + +def main(_): + x_values, y_values = get_data() + trained_model = train_model(FLAGS.epochs, x_values, y_values) + + # Convert and save the model to .tflite + tflite_model = convert_tflite_model(trained_model) + save_tflite_model(tflite_model, + FLAGS.save_dir, + model_name="hello_world_float.tflite") + + +if __name__ == "__main__": + app.run(main) \ No newline at end of file diff --git a/tensorflow-test/HelloWorld/out/HelloWorld/CM55/size/HelloWorld.axf b/tensorflow-test/HelloWorld/out/HelloWorld/CM55/size/HelloWorld.axf new file mode 100644 index 0000000000000000000000000000000000000000..3295ab71a06f0d583f5517227723953d952dd882 GIT binary patch literal 2078464 zcmeFZd3+Ps)i-|c%xJZ+WtL#Tn30V^HcMnyLpE8q$2Lu3Lr6l>q{x8Dh=5U8QkvyK zhAeJ)(wMAg*Q8Erd8SEosuEJe62lVjxl4w8C~sM=a6UmZjhKjtr%J-@d=? z-`bzquI}9B+;h)8=X=hb&E+>rlu~l(k0W-%o|LOJ0a{hDw9}4`30{@}Fe<<)D3jBux|34|9 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zi%}Ri>3(+n_2@hQa1i7AK|uGPn^&VBK^|>>hVGMq?qYd0`r*I7Y{+a}zXZf9{wPXb zk8VGUBIe{LXh>{JtjAyDPuDG6Xj^}OJ$m!^;*@_T-rvIassl%(pT7}pdVccb?^FDl gF!cWzbieopUFv6We}LDI_svh=i2iJd@HKS*1JK(2P5=M^ literal 0 HcmV?d00001 diff --git a/tensorflow-test/HelloWorld/out/HelloWorld/CM55/size/HelloWorld.size+CM55.clog b/tensorflow-test/HelloWorld/out/HelloWorld/CM55/size/HelloWorld.size+CM55.clog new file mode 100644 index 0000000..c83daac --- /dev/null +++ b/tensorflow-test/HelloWorld/out/HelloWorld/CM55/size/HelloWorld.size+CM55.clog @@ -0,0 +1,60 @@ +# CMSIS Build Audit File generated on 2024-05-06T14:39:18 + +# Project Description File: /workspaces/tensorflow-pack/tensorflow-test/HelloWorld/HelloWorld.size+CM55.cprj + +# Toolchain Configuration File: /home/arm_mlops_docker/cmsis-toolbox-linux-amd64/etc/AC6.6.18.0.cmake + +# Package: ARM::CMSIS@6.0.0 + Location: /home/arm_mlops_docker/packs/ARM/CMSIS/6.0.0/ + + * Component: ARM::CMSIS:CORE@6.0.0 + +# Package: ARM::CMSIS-DSP@1.15.0 + Location: /home/arm_mlops_docker/packs/ARM/CMSIS-DSP/1.15.0/ + + * Component: ARM::CMSIS:DSP&Source@1.15.0 + +# Package: ARM::CMSIS-NN@4.1.0 + Location: /home/arm_mlops_docker/packs/ARM/CMSIS-NN/4.1.0/ + + * Component: ARM::CMSIS:NN Lib@4.1.0 + +# Package: ARM::Cortex_DFP@1.0.0 + Location: /home/arm_mlops_docker/packs/ARM/Cortex_DFP/1.0.0/ + + * Component: ARM::Device:Startup&C Startup@2.2.0 + - ConfigFile: /workspaces/tensorflow-pack/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/ARMCM55_ac6.sct:1.1.0 + - ConfigFile: /workspaces/tensorflow-pack/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/startup_ARMCM55.c:1.1.0 + - ConfigFile: /workspaces/tensorflow-pack/tensorflow-test/HelloWorld/RTE/Device/ARMCM55/system_ARMCM55.c:1.1.0 + +# Package: tensorflow::flatbuffers@1.24.2 + Location: /home/arm_mlops_docker/packs/tensorflow/flatbuffers/1.24.2/ + + * Component: tensorflow::Data Exchange:Serialization:flatbuffers&tensorflow@1.24.2 + +# Package: tensorflow::gemmlowp@1.24.2 + Location: /home/arm_mlops_docker/packs/tensorflow/gemmlowp/1.24.2/ + + * Component: tensorflow::Data Processing:Math:gemmlowp fixed-point&tensorflow@1.24.2 + +# Package: tensorflow::kissfft@1.24.2 + Location: /home/arm_mlops_docker/packs/tensorflow/kissfft/1.24.2/ + + * Component: tensorflow::Data Processing:Math:kissfft&tensorflow@1.24.2 + +# Package: tensorflow::ruy@1.24.2 + Location: /home/arm_mlops_docker/packs/tensorflow/ruy/1.24.2/ + + * Component: tensorflow::Data Processing:Math:ruy&tensorflow@1.24.2 + +# Package: tensorflow::tensorflow-lite-micro@1.24.2 + Location: /home/arm_mlops_docker/packs/tensorflow/tensorflow-lite-micro/1.24.2/ + + * Component: tensorflow::Machine Learning:TensorFlow:Kernel Utils@1.24.2 + - ConfigFile: /workspaces/tensorflow-pack/tensorflow-test/HelloWorld/RTE/Machine_Learning/debug_log.cpp:1.24.2 + - ConfigFile: /workspaces/tensorflow-pack/tensorflow-test/HelloWorld/RTE/Machine_Learning/micro_time.cpp:1.24.2 + - ConfigFile: /workspaces/tensorflow-pack/tensorflow-test/HelloWorld/RTE/Machine_Learning/system_setup.cpp:1.24.2 + + * Component: tensorflow::Machine Learning:TensorFlow:Kernel&Reference@1.24.2 + + * Component: tensorflow::Machine Learning:TensorFlow:Testing@1.24.2 diff --git a/tensorflow-test/Target/CM0/RTE/Device/ARMCM0/regions_ARMCM0.h b/tensorflow-test/Target/CM0/RTE/Device/ARMCM0/regions_ARMCM0.h new file mode 100644 index 0000000..0d11343 --- /dev/null +++ b/tensorflow-test/Target/CM0/RTE/Device/ARMCM0/regions_ARMCM0.h @@ -0,0 +1,60 @@ +#ifndef REGIONS_ARMCM0_H +#define REGIONS_ARMCM0_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00040000 +#define __ROM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// + +// RAM Configuration +// ======================= +// RAM=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM0_H */ diff --git a/tensorflow-test/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c b/tensorflow-test/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..0b44834 --- /dev/null +++ b/tensorflow-test/Target/CM0/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,146 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM0) + #include "ARMCM0.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/Target/CM0/RTE/Device/ARMCM0/system_ARMCM0.c b/tensorflow-test/Target/CM0/RTE/Device/ARMCM0/system_ARMCM0.c new file mode 100644 index 0000000..3eb38aa --- /dev/null +++ b/tensorflow-test/Target/CM0/RTE/Device/ARMCM0/system_ARMCM0.c @@ -0,0 +1,56 @@ +/**************************************************************************//** + * @file system_ARMCM0.c + * @brief CMSIS Device System Source File for + * ARMCM0 Device + * @version V1.0.0 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM0.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM0/Target.clayer.yml b/tensorflow-test/Target/CM0/Target.clayer.yml new file mode 100644 index 0000000..bd24c67 --- /dev/null +++ b/tensorflow-test/Target/CM0/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M0 target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM0/regions_ARMCM0.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM0/fvp_config.txt b/tensorflow-test/Target/CM0/fvp_config.txt new file mode 100644 index 0000000..96e7c90 --- /dev/null +++ b/tensorflow-test/Target/CM0/fvp_config.txt @@ -0,0 +1,6 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM0plus/RTE/Device/ARMCM0P/regions_ARMCM0P.h b/tensorflow-test/Target/CM0plus/RTE/Device/ARMCM0P/regions_ARMCM0P.h new file mode 100644 index 0000000..797cbd2 --- /dev/null +++ b/tensorflow-test/Target/CM0plus/RTE/Device/ARMCM0P/regions_ARMCM0P.h @@ -0,0 +1,60 @@ +#ifndef REGIONS_ARMCM0P_H +#define REGIONS_ARMCM0P_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00040000 +#define __ROM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// + +// RAM Configuration +// ======================= +// RAM=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM0P_H */ diff --git a/tensorflow-test/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c b/tensorflow-test/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c new file mode 100644 index 0000000..ee32c09 --- /dev/null +++ b/tensorflow-test/Target/CM0plus/RTE/Device/ARMCM0P/startup_ARMCM0plus.c @@ -0,0 +1,146 @@ +/****************************************************************************** + * @file startup_ARMCM0plus.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0+ Device + * @version V3.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM0P) + #include "ARMCM0plus.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_core_init.c b/tensorflow-test/Target/CM0plus/RTE/Device/ARMCM0P/system_ARMCM0plus.c similarity index 62% rename from tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_core_init.c rename to tensorflow-test/Target/CM0plus/RTE/Device/ARMCM0P/system_ARMCM0plus.c index 3f46da1..5f81ef7 100644 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_core_init.c +++ b/tensorflow-test/Target/CM0plus/RTE/Device/ARMCM0P/system_ARMCM0plus.c @@ -1,75 +1,69 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "cmsis.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ - #define XTAL (32000000UL) - #define SYSTEM_CLOCK (XTAL) - #define PERIPHERAL_CLOCK (25000000UL) - -/*---------------------------------------------------------------------------- - Externals - *----------------------------------------------------------------------------*/ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - extern uint32_t __VECTOR_TABLE; -#endif - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; -uint32_t PeripheralClock = PERIPHERAL_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; - PeripheralClock = PERIPHERAL_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); -#endif - -/* CMSIS System Initialization */ -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__MVE_USED) && (__MVE_USED == 1U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif -} +/**************************************************************************//** + * @file system_ARMCM0plus.c + * @brief CMSIS Device System Source File for + * ARMCM0plus Device + * @version V2.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM0P) + #include "ARMCM0plus.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM0plus/Target.clayer.yml b/tensorflow-test/Target/CM0plus/Target.clayer.yml new file mode 100644 index 0000000..7637f53 --- /dev/null +++ b/tensorflow-test/Target/CM0plus/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M0+ target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM0P/regions_ARMCM0P.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM0plus/fvp_config.txt b/tensorflow-test/Target/CM0plus/fvp_config.txt new file mode 100644 index 0000000..96e7c90 --- /dev/null +++ b/tensorflow-test/Target/CM0plus/fvp_config.txt @@ -0,0 +1,6 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM23/RTE/Device/ARMCM23/regions_ARMCM23.h b/tensorflow-test/Target/CM23/RTE/Device/ARMCM23/regions_ARMCM23.h new file mode 100644 index 0000000..4007534 --- /dev/null +++ b/tensorflow-test/Target/CM23/RTE/Device/ARMCM23/regions_ARMCM23.h @@ -0,0 +1,94 @@ +#ifndef REGIONS_ARMCM23_H +#define REGIONS_ARMCM23_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM_S=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x10000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM0_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// ROM_NS=<__ROM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00200000 +#define __ROM1_BASE 0x00200000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM1_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __ROM1_DEFAULT 0 +// Startup +// Selects region to be used for startup code. +#define __ROM1_STARTUP 0 +// + +// + +// RAM Configuration +// ======================= +// RAM_S=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x30000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// RAM_NS=<__RAM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20200000 +#define __RAM1_BASE 0x20200000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM1_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM1_DEFAULT 0 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM1_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM23_H */ diff --git a/tensorflow-test/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c b/tensorflow-test/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c new file mode 100644 index 0000000..3a58aab --- /dev/null +++ b/tensorflow-test/Target/CM23/RTE/Device/ARMCM23/startup_ARMCM23.c @@ -0,0 +1,159 @@ +/****************************************************************************** + * @file startup_ARMCM23.c + * @brief CMSIS-Core Device Startup File for a Cortex-M23 Device + * @version V3.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_core_init.c b/tensorflow-test/Target/CM23/RTE/Device/ARMCM23/system_ARMCM23.c similarity index 59% rename from tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_core_init.c rename to tensorflow-test/Target/CM23/RTE/Device/ARMCM23/system_ARMCM23.c index 3f46da1..6db5585 100644 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_core_init.c +++ b/tensorflow-test/Target/CM23/RTE/Device/ARMCM23/system_ARMCM23.c @@ -1,75 +1,77 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "cmsis.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ - #define XTAL (32000000UL) - #define SYSTEM_CLOCK (XTAL) - #define PERIPHERAL_CLOCK (25000000UL) - -/*---------------------------------------------------------------------------- - Externals - *----------------------------------------------------------------------------*/ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - extern uint32_t __VECTOR_TABLE; -#endif - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; -uint32_t PeripheralClock = PERIPHERAL_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; - PeripheralClock = PERIPHERAL_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); -#endif - -/* CMSIS System Initialization */ -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__MVE_USED) && (__MVE_USED == 1U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif -} +/**************************************************************************//** + * @file system_ARMCM23.c + * @brief CMSIS Device System Source File for + * ARMCM23 Device + * @version V2.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM23) + #include "ARMCM23.h" + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM23.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM23/Target.clayer.yml b/tensorflow-test/Target/CM23/Target.clayer.yml new file mode 100644 index 0000000..cbdfa80 --- /dev/null +++ b/tensorflow-test/Target/CM23/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M23 target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM23/regions_ARMCM23.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM23/fvp_config.txt b/tensorflow-test/Target/CM23/fvp_config.txt new file mode 100644 index 0000000..076d14d --- /dev/null +++ b/tensorflow-test/Target/CM23/fvp_config.txt @@ -0,0 +1,7 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM3/RTE/Device/ARMCM3/regions_ARMCM3.h b/tensorflow-test/Target/CM3/RTE/Device/ARMCM3/regions_ARMCM3.h new file mode 100644 index 0000000..0a40c16 --- /dev/null +++ b/tensorflow-test/Target/CM3/RTE/Device/ARMCM3/regions_ARMCM3.h @@ -0,0 +1,60 @@ +#ifndef REGIONS_ARMCM3_H +#define REGIONS_ARMCM3_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00040000 +#define __ROM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// + +// RAM Configuration +// ======================= +// RAM=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM3_H */ diff --git a/tensorflow-test/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c b/tensorflow-test/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c new file mode 100644 index 0000000..e0b7524 --- /dev/null +++ b/tensorflow-test/Target/CM3/RTE/Device/ARMCM3/startup_ARMCM3.c @@ -0,0 +1,150 @@ +/****************************************************************************** + * @file startup_ARMCM3.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M3 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM3) + #include "ARMCM3.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_core_init.c b/tensorflow-test/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c similarity index 61% rename from tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_core_init.c rename to tensorflow-test/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c index 3f46da1..1948453 100644 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_core_init.c +++ b/tensorflow-test/Target/CM3/RTE/Device/ARMCM3/system_ARMCM3.c @@ -1,75 +1,65 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "cmsis.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ - #define XTAL (32000000UL) - #define SYSTEM_CLOCK (XTAL) - #define PERIPHERAL_CLOCK (25000000UL) - -/*---------------------------------------------------------------------------- - Externals - *----------------------------------------------------------------------------*/ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - extern uint32_t __VECTOR_TABLE; -#endif - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; -uint32_t PeripheralClock = PERIPHERAL_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; - PeripheralClock = PERIPHERAL_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); -#endif - -/* CMSIS System Initialization */ -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__MVE_USED) && (__MVE_USED == 1U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif -} +/**************************************************************************//** + * @file system_ARMCM3.c + * @brief CMSIS Device System Source File for + * ARMCM3 Device + * @version V1.0.1 + * @date 15. November 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ARMCM3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM3/Target.clayer.yml b/tensorflow-test/Target/CM3/Target.clayer.yml new file mode 100644 index 0000000..7dec29a --- /dev/null +++ b/tensorflow-test/Target/CM3/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M3 target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM3/regions_ARMCM3.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM3/fvp_config.txt b/tensorflow-test/Target/CM3/fvp_config.txt new file mode 100644 index 0000000..96e7c90 --- /dev/null +++ b/tensorflow-test/Target/CM3/fvp_config.txt @@ -0,0 +1,6 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM33/RTE/Device/ARMCM33/regions_ARMCM33.h b/tensorflow-test/Target/CM33/RTE/Device/ARMCM33/regions_ARMCM33.h new file mode 100644 index 0000000..347e13e --- /dev/null +++ b/tensorflow-test/Target/CM33/RTE/Device/ARMCM33/regions_ARMCM33.h @@ -0,0 +1,94 @@ +#ifndef REGIONS_ARMCM33_H +#define REGIONS_ARMCM33_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM_S=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x10000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM0_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// ROM_NS=<__ROM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00200000 +#define __ROM1_BASE 0x00200000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM1_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __ROM1_DEFAULT 0 +// Startup +// Selects region to be used for startup code. +#define __ROM1_STARTUP 0 +// + +// + +// RAM Configuration +// ======================= +// RAM_S=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x30000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// RAM_NS=<__RAM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20200000 +#define __RAM1_BASE 0x20200000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM1_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM1_DEFAULT 0 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM1_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM33_H */ diff --git a/tensorflow-test/Target/CM33/RTE/Device/ARMCM33/startup_ARMCM33.c b/tensorflow-test/Target/CM33/RTE/Device/ARMCM33/startup_ARMCM33.c new file mode 100644 index 0000000..9f498ef --- /dev/null +++ b/tensorflow-test/Target/CM33/RTE/Device/ARMCM33/startup_ARMCM33.c @@ -0,0 +1,164 @@ +/****************************************************************************** + * @file startup_ARMCM33.c + * @brief CMSIS-Core Device Startup File for Cortex-M33 Device + * @version V3.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/tensorflow-test/Target/CM33/RTE/Device/ARMCM33/system_ARMCM33.c similarity index 55% rename from tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c rename to tensorflow-test/Target/CM33/RTE/Device/ARMCM33/system_ARMCM33.c index 1d8c3b6..faebac6 100644 --- a/tensorflow-test-ng/Layer/Target/CM55_VHT_AC6/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c +++ b/tensorflow-test/Target/CM33/RTE/Device/ARMCM33/system_ARMCM33.c @@ -1,86 +1,86 @@ -/* - * Copyright (c) 2009-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "SSE300MPS3.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ - #define XTAL (32000000UL) - #define SYSTEM_CLOCK (XTAL) - #define PERIPHERAL_CLOCK (25000000UL) - -/*---------------------------------------------------------------------------- - Externals - *----------------------------------------------------------------------------*/ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - extern uint32_t __VECTOR_TABLE; -#endif - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; -uint32_t PeripheralClock = PERIPHERAL_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; - PeripheralClock = PERIPHERAL_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); -#endif - -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ - - /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set - * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU - * into retention state - */ - PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL; -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - - /* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __DSB(); - __ISB(); - -} +/**************************************************************************//** + * @file system_ARMCM33.c + * @brief CMSIS Device System Source File for + * ARMCM33 Device + * @version V2.0.0 + * @date 06. Aril 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM33) + #include "ARMCM33.h" + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM33.h" + #endif +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM33/Target.clayer.yml b/tensorflow-test/Target/CM33/Target.clayer.yml new file mode 100644 index 0000000..cbc6ac3 --- /dev/null +++ b/tensorflow-test/Target/CM33/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M33 target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM33/regions_ARMCM33.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM33/fvp_config.txt b/tensorflow-test/Target/CM33/fvp_config.txt new file mode 100644 index 0000000..076d14d --- /dev/null +++ b/tensorflow-test/Target/CM33/fvp_config.txt @@ -0,0 +1,7 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +fvp_mps2.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic +fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM4/RTE/Device/ARMCM4/regions_ARMCM4.h b/tensorflow-test/Target/CM4/RTE/Device/ARMCM4/regions_ARMCM4.h new file mode 100644 index 0000000..bade8a3 --- /dev/null +++ b/tensorflow-test/Target/CM4/RTE/Device/ARMCM4/regions_ARMCM4.h @@ -0,0 +1,60 @@ +#ifndef REGIONS_ARMCM4_H +#define REGIONS_ARMCM4_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00040000 +#define __ROM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// + +// RAM Configuration +// ======================= +// RAM=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM4_H */ diff --git a/tensorflow-test/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c b/tensorflow-test/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c new file mode 100644 index 0000000..26f22d1 --- /dev/null +++ b/tensorflow-test/Target/CM4/RTE/Device/ARMCM4/startup_ARMCM4.c @@ -0,0 +1,150 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V3.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/tensorflow-test/Target/CM4/RTE/Device/ARMCM4/system_ARMCM4.c similarity index 66% rename from tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c rename to tensorflow-test/Target/CM4/RTE/Device/ARMCM4/system_ARMCM4.c index a0a2fb0..612bd5c 100644 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c +++ b/tensorflow-test/Target/CM4/RTE/Device/ARMCM4/system_ARMCM4.c @@ -1,79 +1,79 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "SSE300MPS3.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ - #define XTAL (32000000UL) - #define SYSTEM_CLOCK (XTAL) - #define PERIPHERAL_CLOCK (25000000UL) - -/*---------------------------------------------------------------------------- - Externals - *----------------------------------------------------------------------------*/ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - extern uint32_t __VECTOR_TABLE; -#endif - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; -uint32_t PeripheralClock = PERIPHERAL_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; - PeripheralClock = PERIPHERAL_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); -#endif - -/* CMSIS System Initialization */ -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 1U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -/* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __ISB(); -} +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V2.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM4/Target.clayer.yml b/tensorflow-test/Target/CM4/Target.clayer.yml new file mode 100644 index 0000000..7c6ca41 --- /dev/null +++ b/tensorflow-test/Target/CM4/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M4 target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM4/regions_ARMCM4.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM4/fvp_config.txt b/tensorflow-test/Target/CM4/fvp_config.txt new file mode 100644 index 0000000..7dc428d --- /dev/null +++ b/tensorflow-test/Target/CM4/fvp_config.txt @@ -0,0 +1,7 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=0 # (bool , init-time) default = '1' : Set whether the model has VFP support +fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM4_FP/RTE/Device/ARMCM4/regions_ARMCM4.h b/tensorflow-test/Target/CM4_FP/RTE/Device/ARMCM4/regions_ARMCM4.h new file mode 100644 index 0000000..bade8a3 --- /dev/null +++ b/tensorflow-test/Target/CM4_FP/RTE/Device/ARMCM4/regions_ARMCM4.h @@ -0,0 +1,60 @@ +#ifndef REGIONS_ARMCM4_H +#define REGIONS_ARMCM4_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00040000 +#define __ROM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// + +// RAM Configuration +// ======================= +// RAM=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM4_H */ diff --git a/tensorflow-test/Target/CM4_FP/RTE/Device/ARMCM4/startup_ARMCM4.c b/tensorflow-test/Target/CM4_FP/RTE/Device/ARMCM4/startup_ARMCM4.c new file mode 100644 index 0000000..26f22d1 --- /dev/null +++ b/tensorflow-test/Target/CM4_FP/RTE/Device/ARMCM4/startup_ARMCM4.c @@ -0,0 +1,150 @@ +/****************************************************************************** + * @file startup_ARMCM4.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M4 Device + * @version V3.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/tensorflow-test/Target/CM4_FP/RTE/Device/ARMCM4/system_ARMCM4.c similarity index 66% rename from tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c rename to tensorflow-test/Target/CM4_FP/RTE/Device/ARMCM4/system_ARMCM4.c index a0a2fb0..612bd5c 100644 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c +++ b/tensorflow-test/Target/CM4_FP/RTE/Device/ARMCM4/system_ARMCM4.c @@ -1,79 +1,79 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "SSE300MPS3.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ - #define XTAL (32000000UL) - #define SYSTEM_CLOCK (XTAL) - #define PERIPHERAL_CLOCK (25000000UL) - -/*---------------------------------------------------------------------------- - Externals - *----------------------------------------------------------------------------*/ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - extern uint32_t __VECTOR_TABLE; -#endif - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; -uint32_t PeripheralClock = PERIPHERAL_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; - PeripheralClock = PERIPHERAL_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); -#endif - -/* CMSIS System Initialization */ -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 1U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -/* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __ISB(); -} +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V2.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) + #include "ARMCM4.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM4_FP/Target.clayer.yml b/tensorflow-test/Target/CM4_FP/Target.clayer.yml new file mode 100644 index 0000000..2c62414 --- /dev/null +++ b/tensorflow-test/Target/CM4_FP/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M4 with FPU target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM4/regions_ARMCM4.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM4_FP/fvp_config.txt b/tensorflow-test/Target/CM4_FP/fvp_config.txt new file mode 100644 index 0000000..fac1a65 --- /dev/null +++ b/tensorflow-test/Target/CM4_FP/fvp_config.txt @@ -0,0 +1,7 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +armcortexm4ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support +fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/ARMCM55_ac6.sct b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/ARMCM55_ac6.sct new file mode 100644 index 0000000..6f84bd3 --- /dev/null +++ b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/ARMCM55_ac6.sct @@ -0,0 +1,123 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Veneer Configuration --------------------------- +; CMSE Veneer Configuration +; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 new file mode 100644 index 0000000..6f84bd3 --- /dev/null +++ b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/ARMCM55_ac6.sct.base@1.1.0 @@ -0,0 +1,123 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +;Note: Add '-mcmse' to first line if your software model is "Secure Mode". +; #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc -mcmse + + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/*--------------------- CMSE Veneer Configuration --------------------------- +; CMSE Veneer Configuration +; CMSE Veneer Size (in Bytes) <0x0-0xFFFFFFFF:32> +; + *----------------------------------------------------------------------------*/ +#define __CMSEVENEER_SIZE 0x200 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE - __STACKSEAL_SIZE) /* starts at end of RAM - 8 byte stack seal */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + + +/*---------------------------------------------------------------------------- + Region base & size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __CV_BASE ( __ROM_BASE + __ROM_SIZE - __CMSEVENEER_SIZE ) +#define __CV_SIZE ( __CMSEVENEER_SIZE ) +#else +#define __CV_SIZE ( 0 ) +#endif + +#define __RO_BASE ( __ROM_BASE ) +#define __RO_SIZE ( __ROM_SIZE - __CV_SIZE ) + +#define __RW_BASE ( __RAM_BASE ) +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __STACKSEAL_SIZE ) + + +/*---------------------------------------------------------------------------- + Scatter Region definition + *----------------------------------------------------------------------------*/ +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +LR_CMSE_VENEER __CV_BASE ALIGN 32 __CV_SIZE { ; own load/execution region for CMSE Veneers + ER_CMSE_VENEER __CV_BASE __CV_SIZE { + *(Veneer$$CMSE) + } +} +#endif diff --git a/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/regions_ARMCM55.h b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/regions_ARMCM55.h new file mode 100644 index 0000000..2074e04 --- /dev/null +++ b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/regions_ARMCM55.h @@ -0,0 +1,94 @@ +#ifndef REGIONS_ARMCM55_H +#define REGIONS_ARMCM55_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM_S=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x10000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM0_SIZE 0x00070000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// ROM_NS=<__ROM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00200000 +#define __ROM1_BASE 0x00070000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM1_SIZE 0x00010000 +// Default region +// Enables memory region globally for the application. +#define __ROM1_DEFAULT 0 +// Startup +// Selects region to be used for startup code. +#define __ROM1_STARTUP 0 +// + +// + +// RAM Configuration +// ======================= +// RAM_S=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x30000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00040000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// RAM_NS=<__RAM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20200000 +#define __RAM1_BASE 0x30040000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM1_SIZE 0x00040000 +// Default region +// Enables memory region globally for the application. +#define __RAM1_DEFAULT 0 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM1_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM55_H */ diff --git a/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/startup_ARMCM55.c b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..c5eee5e --- /dev/null +++ b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,164 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS-Core Device Startup File for Cortex-M55 Device + * @version V1.1.0 + * @date 16. December 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 new file mode 100644 index 0000000..0557c5f --- /dev/null +++ b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/startup_ARMCM55.c.base@1.1.0 @@ -0,0 +1,164 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS-Core Device Startup File for Cortex-M55 Device + * @version V1.1.0 + * @date 16. December 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/system_ARMCM55.c b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..283dad3 --- /dev/null +++ b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,107 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.1.0 + * @date 28. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 new file mode 100644 index 0000000..dc329c7 --- /dev/null +++ b/tensorflow-test/Target/CM55/RTE/Device/ARMCM55/system_ARMCM55.c.base@1.1.0 @@ -0,0 +1,107 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.1.0 + * @date 28. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM55/Target.clayer.yml b/tensorflow-test/Target/CM55/Target.clayer.yml new file mode 100644 index 0000000..f35490e --- /dev/null +++ b/tensorflow-test/Target/CM55/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M55 target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM55/regions_ARMCM55.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM55/fvp_config.txt b/tensorflow-test/Target/CM55/fvp_config.txt new file mode 100644 index 0000000..65a861c --- /dev/null +++ b/tensorflow-test/Target/CM55/fvp_config.txt @@ -0,0 +1,11 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=1 # (bool , init-time) default = '0' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.semihosting-heap_base=0x3002fc00 # (int , init-time) default = '0x0' : Virtual address of heap base +cpu0.semihosting-heap_limit=0x3003fc00 # (int , init-time) default = '0x20700000' : Virtual address of top of heap +cpu0.semihosting-stack_base=0x30040000 # (int , init-time) default = '0x20800000' : Virtual address of base of descending stack +cpu0.semihosting-stack_limit=0x3003fc00 # (int , init-time) default = '0x20700000' : Virtual address of stack limit +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM55_Ethos/RTE/Device/ARMCM55/regions_ARMCM55.h b/tensorflow-test/Target/CM55_Ethos/RTE/Device/ARMCM55/regions_ARMCM55.h new file mode 100644 index 0000000..2074e04 --- /dev/null +++ b/tensorflow-test/Target/CM55_Ethos/RTE/Device/ARMCM55/regions_ARMCM55.h @@ -0,0 +1,94 @@ +#ifndef REGIONS_ARMCM55_H +#define REGIONS_ARMCM55_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM_S=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x10000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM0_SIZE 0x00070000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// ROM_NS=<__ROM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00200000 +#define __ROM1_BASE 0x00070000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM1_SIZE 0x00010000 +// Default region +// Enables memory region globally for the application. +#define __ROM1_DEFAULT 0 +// Startup +// Selects region to be used for startup code. +#define __ROM1_STARTUP 0 +// + +// + +// RAM Configuration +// ======================= +// RAM_S=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x30000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00040000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// RAM_NS=<__RAM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20200000 +#define __RAM1_BASE 0x30040000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM1_SIZE 0x00040000 +// Default region +// Enables memory region globally for the application. +#define __RAM1_DEFAULT 0 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM1_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM55_H */ diff --git a/tensorflow-test/Target/CM55_Ethos/RTE/Device/ARMCM55/startup_ARMCM55.c b/tensorflow-test/Target/CM55_Ethos/RTE/Device/ARMCM55/startup_ARMCM55.c new file mode 100644 index 0000000..c5eee5e --- /dev/null +++ b/tensorflow-test/Target/CM55_Ethos/RTE/Device/ARMCM55/startup_ARMCM55.c @@ -0,0 +1,164 @@ +/****************************************************************************** + * @file startup_ARMCM55.c + * @brief CMSIS-Core Device Startup File for Cortex-M55 Device + * @version V1.1.0 + * @date 16. December 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/Target/CM55_Ethos/RTE/Device/ARMCM55/system_ARMCM55.c b/tensorflow-test/Target/CM55_Ethos/RTE/Device/ARMCM55/system_ARMCM55.c new file mode 100644 index 0000000..283dad3 --- /dev/null +++ b/tensorflow-test/Target/CM55_Ethos/RTE/Device/ARMCM55/system_ARMCM55.c @@ -0,0 +1,107 @@ +/**************************************************************************//** + * @file system_ARMCM55.c + * @brief CMSIS Device System Source File for + * ARMCM55 Device + * @version V1.1.0 + * @date 28. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM55) + #include "ARMCM55.h" +#else + #error device not specified! +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM55.h" +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL ( 5000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (5U * XTAL) + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM55_Ethos/Target.clayer.yml b/tensorflow-test/Target/CM55_Ethos/Target.clayer.yml new file mode 100644 index 0000000..b42f4be --- /dev/null +++ b/tensorflow-test/Target/CM55_Ethos/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M55 with Ethos-U target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM55/regions_ARMCM55.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM55_Ethos/fvp_config.txt b/tensorflow-test/Target/CM55_Ethos/fvp_config.txt new file mode 100644 index 0000000..65a861c --- /dev/null +++ b/tensorflow-test/Target/CM55_Ethos/fvp_config.txt @@ -0,0 +1,11 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=1 # (bool , init-time) default = '0' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.semihosting-heap_base=0x3002fc00 # (int , init-time) default = '0x0' : Virtual address of heap base +cpu0.semihosting-heap_limit=0x3003fc00 # (int , init-time) default = '0x20700000' : Virtual address of top of heap +cpu0.semihosting-stack_base=0x30040000 # (int , init-time) default = '0x20800000' : Virtual address of base of descending stack +cpu0.semihosting-stack_limit=0x3003fc00 # (int , init-time) default = '0x20700000' : Virtual address of stack limit +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM7/RTE/Device/ARMCM7/regions_ARMCM7.h b/tensorflow-test/Target/CM7/RTE/Device/ARMCM7/regions_ARMCM7.h new file mode 100644 index 0000000..8b2c07e --- /dev/null +++ b/tensorflow-test/Target/CM7/RTE/Device/ARMCM7/regions_ARMCM7.h @@ -0,0 +1,60 @@ +#ifndef REGIONS_ARMCM7_H +#define REGIONS_ARMCM7_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x00000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00040000 +#define __ROM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// + +// RAM Configuration +// ======================= +// RAM=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x20000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00400000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM7_H */ diff --git a/tensorflow-test/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c b/tensorflow-test/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c new file mode 100644 index 0000000..8d1c645 --- /dev/null +++ b/tensorflow-test/Target/CM7/RTE/Device/ARMCM7/startup_ARMCM7.c @@ -0,0 +1,150 @@ +/****************************************************************************** + * @file startup_ARMCM7.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M7 Device + * @version V3.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + const VECTOR_TABLE_Type __VECTOR_TABLE[240] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 223 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/tensorflow-test/Target/CM7/RTE/Device/ARMCM7/system_ARMCM7.c similarity index 66% rename from tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c rename to tensorflow-test/Target/CM7/RTE/Device/ARMCM7/system_ARMCM7.c index a0a2fb0..4642b88 100644 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c +++ b/tensorflow-test/Target/CM7/RTE/Device/ARMCM7/system_ARMCM7.c @@ -1,79 +1,79 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "SSE300MPS3.h" - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ - #define XTAL (32000000UL) - #define SYSTEM_CLOCK (XTAL) - #define PERIPHERAL_CLOCK (25000000UL) - -/*---------------------------------------------------------------------------- - Externals - *----------------------------------------------------------------------------*/ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - extern uint32_t __VECTOR_TABLE; -#endif - -/*---------------------------------------------------------------------------- - System Core Clock Variable - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = SYSTEM_CLOCK; -uint32_t PeripheralClock = PERIPHERAL_CLOCK; - -/*---------------------------------------------------------------------------- - System Core Clock update function - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ - SystemCoreClock = SYSTEM_CLOCK; - PeripheralClock = PERIPHERAL_CLOCK; -} - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ -void SystemInit (void) -{ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); -#endif - -/* CMSIS System Initialization */ -#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 1U)) - SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ - (3U << 11U*2U) ); /* enable CP11 Full Access */ -#endif - -#ifdef UNALIGNED_SUPPORT_DISABLE - SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; -#endif - -/* Enable Loop and branch info cache */ - SCB->CCR |= SCB_CCR_LOB_Msk; - __ISB(); -} +/**************************************************************************//** + * @file system_ARMCM7.c + * @brief CMSIS Device System Source File for + * ARMCM7 Device + * @version V2.0.0 + * @date 06. April 2023 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM7) + #include "ARMCM7.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM7/Target.clayer.yml b/tensorflow-test/Target/CM7/Target.clayer.yml new file mode 100644 index 0000000..6882154 --- /dev/null +++ b/tensorflow-test/Target/CM7/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M7 target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM7/regions_ARMCM7.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM7/fvp_config.txt b/tensorflow-test/Target/CM7/fvp_config.txt new file mode 100644 index 0000000..96e7c90 --- /dev/null +++ b/tensorflow-test/Target/CM7/fvp_config.txt @@ -0,0 +1,6 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +fvp_mps2.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM85/RTE/Device/ARMCM85/regions_ARMCM85.h b/tensorflow-test/Target/CM85/RTE/Device/ARMCM85/regions_ARMCM85.h new file mode 100644 index 0000000..41d8ed5 --- /dev/null +++ b/tensorflow-test/Target/CM85/RTE/Device/ARMCM85/regions_ARMCM85.h @@ -0,0 +1,94 @@ +#ifndef REGIONS_ARMCM85_H +#define REGIONS_ARMCM85_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM_S=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x11000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM0_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// ROM_NS=<__ROM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00200000 +#define __ROM1_BASE 0x01100000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM1_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __ROM1_DEFAULT 0 +// Startup +// Selects region to be used for startup code. +#define __ROM1_STARTUP 0 +// + +// + +// RAM Configuration +// ======================= +// RAM_S=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x31000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// RAM_NS=<__RAM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20200000 +#define __RAM1_BASE 0x21200000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM1_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM1_DEFAULT 0 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM1_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM85_H */ diff --git a/tensorflow-test/Target/CM85/RTE/Device/ARMCM85/startup_ARMCM85.c b/tensorflow-test/Target/CM85/RTE/Device/ARMCM85/startup_ARMCM85.c new file mode 100644 index 0000000..9ac2cef --- /dev/null +++ b/tensorflow-test/Target/CM85/RTE/Device/ARMCM85/startup_ARMCM85.c @@ -0,0 +1,164 @@ +/****************************************************************************** + * @file startup_ARMCM85.c + * @brief CMSIS Device Startup File for ARMCM85 Device + * @version V1.0.0 + * @date 07. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM85) + #include "ARMCM85.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/Target/CM85/RTE/Device/ARMCM85/system_ARMCM85.c b/tensorflow-test/Target/CM85/RTE/Device/ARMCM85/system_ARMCM85.c new file mode 100644 index 0000000..ba13355 --- /dev/null +++ b/tensorflow-test/Target/CM85/RTE/Device/ARMCM85/system_ARMCM85.c @@ -0,0 +1,106 @@ +/**************************************************************************//** + * @file system_ARMCM85.c + * @brief CMSIS Device System Source File for ARMCM85 Device + * @version V1.0.0 + * @date 30. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM85) + #include "ARMCM85.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM85.h" + #endif +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM85/Target.clayer.yml b/tensorflow-test/Target/CM85/Target.clayer.yml new file mode 100644 index 0000000..d52433c --- /dev/null +++ b/tensorflow-test/Target/CM85/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M85 target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM85/regions_ARMCM85.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM85/fvp_config.txt b/tensorflow-test/Target/CM85/fvp_config.txt new file mode 100644 index 0000000..350672a --- /dev/null +++ b/tensorflow-test/Target/CM85/fvp_config.txt @@ -0,0 +1,11 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=1 # (bool , init-time) default = '0' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.semihosting-heap_base=0x311efc00 # (int , init-time) default = '0x0' : Virtual address of heap base +cpu0.semihosting-heap_limit=0x311ffc00 # (int , init-time) default = '0x20700000' : Virtual address of top of heap +cpu0.semihosting-stack_base=0x31200000 # (int , init-time) default = '0x20800000' : Virtual address of base of descending stack +cpu0.semihosting-stack_limit=0x311ffc00 # (int , init-time) default = '0x20700000' : Virtual address of stack limit +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/Target/CM85_Ethos/RTE/Device/ARMCM85/regions_ARMCM85.h b/tensorflow-test/Target/CM85_Ethos/RTE/Device/ARMCM85/regions_ARMCM85.h new file mode 100644 index 0000000..41d8ed5 --- /dev/null +++ b/tensorflow-test/Target/CM85_Ethos/RTE/Device/ARMCM85/regions_ARMCM85.h @@ -0,0 +1,94 @@ +#ifndef REGIONS_ARMCM85_H +#define REGIONS_ARMCM85_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Device pack: ARM.CMSIS_DFP.0.0.0 +// Device pack used to generate this file + +// ROM Configuration +// ======================= +// ROM_S=<__ROM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00000000 +#define __ROM0_BASE 0x11000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM0_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __ROM0_DEFAULT 1 +// Startup +// Selects region to be used for startup code. +#define __ROM0_STARTUP 1 +// + +// ROM_NS=<__ROM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x00200000 +#define __ROM1_BASE 0x01100000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00200000 +#define __ROM1_SIZE 0x00100000 +// Default region +// Enables memory region globally for the application. +#define __ROM1_DEFAULT 0 +// Startup +// Selects region to be used for startup code. +#define __ROM1_STARTUP 0 +// + +// + +// RAM Configuration +// ======================= +// RAM_S=<__RAM0> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20000000 +#define __RAM0_BASE 0x31000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM0_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM0_DEFAULT 1 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM0_NOINIT 0 +// + +// RAM_NS=<__RAM1> +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Default: 0x20200000 +#define __RAM1_BASE 0x21200000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +// Default: 0x00020000 +#define __RAM1_SIZE 0x00200000 +// Default region +// Enables memory region globally for the application. +#define __RAM1_DEFAULT 0 +// No zero initialize +// Excludes region from zero initialization. +#define __RAM1_NOINIT 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000400 +#define __HEAP_SIZE 0x00010000 +// + + +#endif /* REGIONS_ARMCM85_H */ diff --git a/tensorflow-test/Target/CM85_Ethos/RTE/Device/ARMCM85/startup_ARMCM85.c b/tensorflow-test/Target/CM85_Ethos/RTE/Device/ARMCM85/startup_ARMCM85.c new file mode 100644 index 0000000..9ac2cef --- /dev/null +++ b/tensorflow-test/Target/CM85_Ethos/RTE/Device/ARMCM85/startup_ARMCM85.c @@ -0,0 +1,164 @@ +/****************************************************************************** + * @file startup_ARMCM85.c + * @brief CMSIS Device Startup File for ARMCM85 Device + * @version V1.0.0 + * @date 07. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM85) + #include "ARMCM85.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint32_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void BusFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void UsageFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SecureFault_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + const VECTOR_TABLE_Type __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + MemManage_Handler, /* -12 MPU Fault Handler */ + BusFault_Handler, /* -11 Bus Fault Handler */ + UsageFault_Handler, /* -10 Usage Fault Handler */ + SecureFault_Handler, /* -9 Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVC Handler */ + DebugMon_Handler, /* -4 Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10 .. 480 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/tensorflow-test/Target/CM85_Ethos/RTE/Device/ARMCM85/system_ARMCM85.c b/tensorflow-test/Target/CM85_Ethos/RTE/Device/ARMCM85/system_ARMCM85.c new file mode 100644 index 0000000..ba13355 --- /dev/null +++ b/tensorflow-test/Target/CM85_Ethos/RTE/Device/ARMCM85/system_ARMCM85.c @@ -0,0 +1,106 @@ +/**************************************************************************//** + * @file system_ARMCM85.c + * @brief CMSIS Device System Source File for ARMCM85 Device + * @version V1.0.0 + * @date 30. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM85) + #include "ARMCM85.h" + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #include "partition_ARMCM85.h" + #endif +#else + #error device not specified! +#endif + + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + + /* Set CPDLPSTATE.RLPSTATE to 0 + Set CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU into retention state. + Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk | + PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk ); + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + + /* Enable Branch Prediction */ + SCB->CCR |= SCB_CCR_BP_Msk; + + __DSB(); + __ISB(); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + TZ_SAU_Setup(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/tensorflow-test/Target/CM85_Ethos/Target.clayer.yml b/tensorflow-test/Target/CM85_Ethos/Target.clayer.yml new file mode 100644 index 0000000..d805f9d --- /dev/null +++ b/tensorflow-test/Target/CM85_Ethos/Target.clayer.yml @@ -0,0 +1,15 @@ +layer: + type: Target + description: Cortex-M85 with Ethos-U target components and files + + components: + - component: ARM::CMSIS:CORE + - component: Device:Startup&C Startup + + linker: + - regions: ./RTE/Device/ARMCM85/regions_ARMCM85.h + + groups: + - group: FVP + files: + - file: ./fvp_config.txt diff --git a/tensorflow-test/Target/CM85_Ethos/fvp_config.txt b/tensorflow-test/Target/CM85_Ethos/fvp_config.txt new file mode 100644 index 0000000..350672a --- /dev/null +++ b/tensorflow-test/Target/CM85_Ethos/fvp_config.txt @@ -0,0 +1,11 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#---------------------------------------------------------------------------------------------- +cpu0.semihosting-enable=1 # (bool , init-time) default = '0' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. +cpu0.semihosting-heap_base=0x311efc00 # (int , init-time) default = '0x0' : Virtual address of heap base +cpu0.semihosting-heap_limit=0x311ffc00 # (int , init-time) default = '0x20700000' : Virtual address of top of heap +cpu0.semihosting-stack_base=0x31200000 # (int , init-time) default = '0x20800000' : Virtual address of base of descending stack +cpu0.semihosting-stack_limit=0x311ffc00 # (int , init-time) default = '0x20700000' : Virtual address of stack limit +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#---------------------------------------------------------------------------------------------- diff --git a/tensorflow-test/all_tests_reference.yml b/tensorflow-test/all_tests_reference.yml deleted file mode 100644 index 375c84f..0000000 --- a/tensorflow-test/all_tests_reference.yml +++ /dev/null @@ -1,256 +0,0 @@ -test_tests: - readable: "Test Tests" - report: test_test.junit - tests: - - testing_helpers_test: - sources: - - tensorflow/lite/micro/testing_helpers_test.cc - -generic_tests: - readable: "Generic Unit Tests - Reference Kernel" - report: generic.junit - tests: - - memory_arena_threshold_test: - sources: - - tensorflow/lite/micro/memory_arena_threshold_test.cc - - tensorflow/lite/micro/benchmarks/keyword_scrambled_model_data.cc - - tensorflow/lite/micro/testing/test_conv_model.cc - - memory_helpers_test: - sources: - - tensorflow/lite/micro/memory_helpers_test.cc - - micro_allocator_test: - sources: - - tensorflow/lite/micro/micro_allocator_test.cc - - tensorflow/lite/micro/testing/test_conv_model.cc - - micro_error_reporter_test: - sources: - - tensorflow/lite/micro/micro_error_reporter_test.cc - - micro_interpreter_test: - sources: - - tensorflow/lite/micro/micro_interpreter_test.cc - - micro_mutable_op_resolver_test: - sources: - - tensorflow/lite/micro/micro_mutable_op_resolver_test.cc - - micro_string_test: - sources: - - tensorflow/lite/micro/micro_string_test.cc - - micro_time_test: - sources: - - tensorflow/lite/micro/micro_time_test.cc - - micro_utils_test: - sources: - - tensorflow/lite/micro/micro_utils_test.cc - - recording_micro_allocator_test: - sources: - - tensorflow/lite/micro/recording_micro_allocator_test.cc - - tensorflow/lite/micro/testing/test_conv_model.cc - - recording_simple_memory_allocator_test: - sources: - - tensorflow/lite/micro/recording_simple_memory_allocator_test.cc - - simple_memory_allocator_test: - sources: - - tensorflow/lite/micro/simple_memory_allocator_test.cc - -kernel_unit_tests: - readable: "Kernel Unit Tests" - report: kernel.junit - tests: - - activations_test: - sources: - - tensorflow/lite/micro/kernels/activations_test.cc - - add_test: - sources: - - tensorflow/lite/micro/kernels/add_test.cc - - add_n_test: - sources: - - tensorflow/lite/micro/kernels/add_n_test.cc - - arg_min_max_test: - sources: - - tensorflow/lite/micro/kernels/arg_min_max_test.cc - - batch_to_space_nd_test: - sources: - - tensorflow/lite/micro/kernels/batch_to_space_nd_test.cc - - cast_test: - sources: - - tensorflow/lite/micro/kernels/cast_test.cc - - ceil_test: - sources: - - tensorflow/lite/micro/kernels/ceil_test.cc - - circular_buffer_test: - sources: - - tensorflow/lite/micro/kernels/circular_buffer_test.cc - - tensorflow/lite/micro/kernels/circular_buffer_flexbuffers_generated_data.cc - - comparisons_test: - sources: - - tensorflow/lite/micro/kernels/comparisons_test.cc - - concatenation_test: - sources: - - tensorflow/lite/micro/kernels/concatenation_test.cc -# - conv_test: -# sources: -# - tensorflow/lite/micro/kernels/conv_test.cc -# - tensorflow/lite/micro/kernels/conv_test_common.cc - - cumsum_test: - sources: - - tensorflow/lite/micro/kernels/cumsum_test.cc - - depth_to_space_test: - sources: - - tensorflow/lite/micro/kernels/depth_to_space_test.cc - - depthwise_conv_test: - sources: - - tensorflow/lite/micro/kernels/depthwise_conv_test.cc - - dequantize_test: - sources: - - tensorflow/lite/micro/kernels/dequantize_test.cc - - detection_postprocess_test: - sources: - - tensorflow/lite/micro/kernels/detection_postprocess_test.cc - - tensorflow/lite/micro/kernels/detection_postprocess_flexbuffers_generated_data.cc - - elementwise_test: - sources: - - tensorflow/lite/micro/kernels/elementwise_test.cc - - elu_test: - sources: - - tensorflow/lite/micro/kernels/elu_test.cc - - exp_test: - sources: - - tensorflow/lite/micro/kernels/exp_test.cc - - expand_dims_test: - sources: - - tensorflow/lite/micro/kernels/expand_dims_test.cc - - fill_test: - sources: - - tensorflow/lite/micro/kernels/fill_test.cc - - floor_test: - sources: - - tensorflow/lite/micro/kernels/floor_test.cc - - floor_div_test: - sources: - - tensorflow/lite/micro/kernels/floor_div_test.cc - - floor_mod_test: - sources: - - tensorflow/lite/micro/kernels/floor_mod_test.cc - - fully_connected_test: - sources: - - tensorflow/lite/micro/kernels/fully_connected_test.cc - - gather_test: - sources: - - tensorflow/lite/micro/kernels/gather_test.cc - - gather_nd_test: - sources: - - tensorflow/lite/micro/kernels/gather_nd_test.cc - - hard_swish_test: - sources: - - tensorflow/lite/micro/kernels/hard_swish_test.cc - - l2norm_test: - sources: - - tensorflow/lite/micro/kernels/l2norm_test.cc - - l2_pool_2d_test: - sources: - - tensorflow/lite/micro/kernels/l2_pool_2d_test.cc - - leaky_relu_test: - sources: - - tensorflow/lite/micro/kernels/leaky_relu_test.cc - - logical_test: - sources: - - tensorflow/lite/micro/kernels/logical_test.cc - - logistic_test: - sources: - - tensorflow/lite/micro/kernels/logistic_test.cc - - log_softmax_test: - sources: - - tensorflow/lite/micro/kernels/log_softmax_test.cc - - maximum_minimum_test: - sources: - - tensorflow/lite/micro/kernels/maximum_minimum_test.cc - - mul_test: - sources: - - tensorflow/lite/micro/kernels/mul_test.cc - - neg_test: - sources: - - tensorflow/lite/micro/kernels/neg_test.cc - - pack_test: - sources: - - tensorflow/lite/micro/kernels/pack_test.cc - - pad_test: - sources: - - tensorflow/lite/micro/kernels/pad_test.cc - - pooling_test: - sources: - - tensorflow/lite/micro/kernels/pooling_test.cc - - prelu_test: - sources: - - tensorflow/lite/micro/kernels/prelu_test.cc - - quantization_util_test: - sources: - - tensorflow/lite/micro/kernels/quantization_util_test.cc - - quantize_test: - sources: - - tensorflow/lite/micro/kernels/quantize_test.cc - - reduce_test: - sources: - - tensorflow/lite/micro/kernels/reduce_test.cc - - reshape_test: - sources: - - tensorflow/lite/micro/kernels/reshape_test.cc - - resize_bilinear_test: - sources: - - tensorflow/lite/micro/kernels/resize_bilinear_test.cc - - resize_nearest_neighbor_test: - sources: - - tensorflow/lite/micro/kernels/resize_nearest_neighbor_test.cc - - round_test: - sources: - - tensorflow/lite/micro/kernels/round_test.cc - - shape_test: - sources: - - tensorflow/lite/micro/kernels/shape_test.cc - - softmax_test: - sources: - - tensorflow/lite/micro/kernels/softmax_test.cc - - space_to_batch_nd_test: - sources: - - tensorflow/lite/micro/kernels/space_to_batch_nd_test.cc - - space_to_depth_test: - sources: - - tensorflow/lite/micro/kernels/space_to_depth_test.cc - - split_test: - sources: - - tensorflow/lite/micro/kernels/split_test.cc - - split_v_test: - sources: - - tensorflow/lite/micro/kernels/split_v_test.cc - - squeeze_test: - sources: - - tensorflow/lite/micro/kernels/squeeze_test.cc - - strided_slice_test: - sources: - - tensorflow/lite/micro/kernels/strided_slice_test.cc - - sub_test: - sources: - - tensorflow/lite/micro/kernels/sub_test.cc - - svdf_test: - sources: - - tensorflow/lite/micro/kernels/svdf_test.cc - - tanh_test: - sources: - - tensorflow/lite/micro/kernels/tanh_test.cc - - transpose_test: - sources: - - tensorflow/lite/micro/kernels/transpose_test.cc - - transpose_conv_test: - sources: - - tensorflow/lite/micro/kernels/transpose_conv_test.cc - - tensorflow/lite/micro/kernels/conv_test_common.cc - - unpack_test: - sources: - - tensorflow/lite/micro/kernels/unpack_test.cc - - zeros_like_test: - sources: - - tensorflow/lite/micro/kernels/zeros_like_test.cc - - lanner/greedy_memory_planner_test: - sources: - - tensorflow/lite/micro/memory_planner/greedy_memory_planner_test.cc - - lanner/linear_memory_planner_te: - sources: - - tensorflow/lite/micro/memory_planner/linear_memory_planner_test.c \ No newline at end of file diff --git a/tensorflow-test/cmsis-toolbox.options b/tensorflow-test/cmsis-toolbox.options deleted file mode 100644 index 82e5eb7..0000000 --- a/tensorflow-test/cmsis-toolbox.options +++ /dev/null @@ -1,6 +0,0 @@ -/opt/cbuild -/home/ubuntu/packs -/opt/armcompiler/bin - -/opt/gcc-arm-none-eabi-10-2020-q4-major/bin - diff --git a/tensorflow-test/generic_tests.yml b/tensorflow-test/generic_tests.yml deleted file mode 100644 index 3afa548..0000000 --- a/tensorflow-test/generic_tests.yml +++ /dev/null @@ -1,248 +0,0 @@ -generic_tests: - readable: "Generic Components Unit Tests" - report: generic.junit - tests: - - memory_arena_threshold_test: - sources: - - tensorflow/lite/micro/memory_arena_threshold_test.cc - - tensorflow/lite/micro/benchmarks/keyword_scrambled_model_data.cc - - tensorflow/lite/micro/testing/test_conv_model.cc - - memory_helpers_test: - sources: - - tensorflow/lite/micro/memory_helpers_test.cc - - micro_allocator_test: - sources: - - tensorflow/lite/micro/micro_allocator_test.cc - - tensorflow/lite/micro/testing/test_conv_model.cc - - micro_error_reporter_test: - sources: - - tensorflow/lite/micro/micro_error_reporter_test.cc - - micro_interpreter_test: - sources: - - tensorflow/lite/micro/micro_interpreter_test.cc - - micro_mutable_op_resolver_test: - sources: - - tensorflow/lite/micro/micro_mutable_op_resolver_test.cc - - micro_string_test: - sources: - - tensorflow/lite/micro/micro_string_test.cc - - micro_time_test: - sources: - - tensorflow/lite/micro/micro_time_test.cc - - micro_utils_test: - sources: - - tensorflow/lite/micro/micro_utils_test.cc - - recording_micro_allocator_test: - sources: - - tensorflow/lite/micro/recording_micro_allocator_test.cc - - tensorflow/lite/micro/testing/test_conv_model.cc - - recording_simple_memory_allocator_test: - sources: - - tensorflow/lite/micro/recording_simple_memory_allocator_test.cc - - simple_memory_allocator_test: - sources: - - tensorflow/lite/micro/simple_memory_allocator_test.cc - -kernel_unit_tests: - readable: "Kernel Unit Tests" - report: kernel.junit - tests: - - activations_test: - sources: - - tensorflow/lite/micro/kernels/activations_test.cc - - add_test: - sources: - - tensorflow/lite/micro/kernels/add_test.cc - - add_n_test: - sources: - - tensorflow/lite/micro/kernels/add_n_test.cc - - arg_min_max_test: - sources: - - tensorflow/lite/micro/kernels/arg_min_max_test.cc - - batch_to_space_nd_test: - sources: - - tensorflow/lite/micro/kernels/batch_to_space_nd_test.cc - - cast_test: - sources: - - tensorflow/lite/micro/kernels/cast_test.cc - - ceil_test: - sources: - - tensorflow/lite/micro/kernels/ceil_test.cc - - circular_buffer_test: - sources: - - tensorflow/lite/micro/kernels/circular_buffer_test.cc - - tensorflow/lite/micro/kernels/circular_buffer_flexbuffers_generated_data.cc - - comparisons_test: - sources: - - tensorflow/lite/micro/kernels/comparisons_test.cc - - concatenation_test: - sources: - - tensorflow/lite/micro/kernels/concatenation_test.cc - - conv_test: - sources: - - tensorflow/lite/micro/kernels/conv_test.cc - - tensorflow/lite/micro/kernels/conv_test_common.cc - - cumsum_test: - sources: - - tensorflow/lite/micro/kernels/cumsum_test.cc - - depth_to_space_test: - sources: - - tensorflow/lite/micro/kernels/depth_to_space_test.cc - - depthwise_conv_test: - sources: - - tensorflow/lite/micro/kernels/depthwise_conv_test.cc - - dequantize_test: - sources: - - tensorflow/lite/micro/kernels/dequantize_test.cc - - detection_postprocess_test: - sources: - - tensorflow/lite/micro/kernels/detection_postprocess_test.cc - - tensorflow/lite/micro/kernels/detection_postprocess_flexbuffers_generated_data.cc - - elementwise_test: - sources: - - tensorflow/lite/micro/kernels/elementwise_test.cc - - elu_test: - sources: - - tensorflow/lite/micro/kernels/elu_test.cc - - exp_test: - sources: - - tensorflow/lite/micro/kernels/exp_test.cc - - expand_dims_test: - sources: - - tensorflow/lite/micro/kernels/expand_dims_test.cc - - fill_test: - sources: - - tensorflow/lite/micro/kernels/fill_test.cc - - floor_test: - sources: - - tensorflow/lite/micro/kernels/floor_test.cc - - floor_div_test: - sources: - - tensorflow/lite/micro/kernels/floor_div_test.cc - - floor_mod_test: - sources: - - tensorflow/lite/micro/kernels/floor_mod_test.cc - - fully_connected_test: - sources: - - tensorflow/lite/micro/kernels/fully_connected_test.cc - - gather_test: - sources: - - tensorflow/lite/micro/kernels/gather_test.cc - - gather_nd_test: - sources: - - tensorflow/lite/micro/kernels/gather_nd_test.cc - - hard_swish_test: - sources: - - tensorflow/lite/micro/kernels/hard_swish_test.cc - - l2norm_test: - sources: - - tensorflow/lite/micro/kernels/l2norm_test.cc - - l2_pool_2d_test: - sources: - - tensorflow/lite/micro/kernels/l2_pool_2d_test.cc - - leaky_relu_test: - sources: - - tensorflow/lite/micro/kernels/leaky_relu_test.cc - - logical_test: - sources: - - tensorflow/lite/micro/kernels/logical_test.cc - - logistic_test: - sources: - - tensorflow/lite/micro/kernels/logistic_test.cc - - log_softmax_test: - sources: - - tensorflow/lite/micro/kernels/log_softmax_test.cc - - maximum_minimum_test: - sources: - - tensorflow/lite/micro/kernels/maximum_minimum_test.cc - - mul_test: - sources: - - tensorflow/lite/micro/kernels/mul_test.cc - - neg_test: - sources: - - tensorflow/lite/micro/kernels/neg_test.cc - - pack_test: - sources: - - tensorflow/lite/micro/kernels/pack_test.cc - - pad_test: - sources: - - tensorflow/lite/micro/kernels/pad_test.cc - - pooling_test: - sources: - - tensorflow/lite/micro/kernels/pooling_test.cc - - prelu_test: - sources: - - tensorflow/lite/micro/kernels/prelu_test.cc - - quantization_util_test: - sources: - - tensorflow/lite/micro/kernels/quantization_util_test.cc - - quantize_test: - sources: - - tensorflow/lite/micro/kernels/quantize_test.cc - - reduce_test: - sources: - - tensorflow/lite/micro/kernels/reduce_test.cc - - reshape_test: - sources: - - tensorflow/lite/micro/kernels/reshape_test.cc - - resize_bilinear_test: - sources: - - tensorflow/lite/micro/kernels/resize_bilinear_test.cc - - resize_nearest_neighbor_test: - sources: - - tensorflow/lite/micro/kernels/resize_nearest_neighbor_test.cc - - round_test: - sources: - - tensorflow/lite/micro/kernels/round_test.cc - - shape_test: - sources: - - tensorflow/lite/micro/kernels/shape_test.cc - - softmax_test: - sources: - - tensorflow/lite/micro/kernels/softmax_test.cc - - space_to_batch_nd_test: - sources: - - tensorflow/lite/micro/kernels/space_to_batch_nd_test.cc - - space_to_depth_test: - sources: - - tensorflow/lite/micro/kernels/space_to_depth_test.cc - - split_test: - sources: - - tensorflow/lite/micro/kernels/split_test.cc - - split_v_test: - sources: - - tensorflow/lite/micro/kernels/split_v_test.cc - - squeeze_test: - sources: - - tensorflow/lite/micro/kernels/squeeze_test.cc - - strided_slice_test: - sources: - - tensorflow/lite/micro/kernels/strided_slice_test.cc - - sub_test: - sources: - - tensorflow/lite/micro/kernels/sub_test.cc - - svdf_test: - sources: - - tensorflow/lite/micro/kernels/svdf_test.cc - - tanh_test: - sources: - - tensorflow/lite/micro/kernels/tanh_test.cc - - transpose_test: - sources: - - tensorflow/lite/micro/kernels/transpose_test.cc - - transpose_conv_test: - sources: - - tensorflow/lite/micro/kernels/transpose_conv_test.cc - - tensorflow/lite/micro/kernels/conv_test_common.cc - - unpack_test: - sources: - - tensorflow/lite/micro/kernels/unpack_test.cc - - zeros_like_test: - sources: - - tensorflow/lite/micro/kernels/zeros_like_test.cc - - lanner/greedy_memory_planner_test: - sources: - - tensorflow/lite/micro/memory_planner/greedy_memory_planner_test.cc - - lanner/linear_memory_planner_te: - sources: - - tensorflow/lite/micro/memory_planner/linear_memory_planner_test.c \ No newline at end of file diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Include/led_port.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Include/led_port.h deleted file mode 100644 index e9e6e28..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Include/led_port.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2017 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __LED_PORT_H__ -#define __LED_PORT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* The goal of this file is to create a common LED API for different targets in order - * create common example applications. - */ - -/* Note: Currently this API doesn't handle the case when a peripheral is - * mapped to secure and non-secure region as well, but could be extended - * to select secure or non-secure one. - */ - -/** - * \brief Get the number of bits of LED port, - * in the current platform, that can be - * read and written in one chunk. - * - * \return Available number of bits of LED port. - */ -unsigned int get_led_port_bit_length(void); - -/** - * \brief Initializes LED device if needed - */ -void led_port_init(void); - -/** - * \brief Set the value of the LED port. - * - * \param[in] led Value of the LED port will be set. - * Every bit represents one physical LED. - * - * \return 0 if succeeded, 1 otherwise - */ -unsigned int set_led_port(unsigned int led_mask); - -/** - * \brief Get the value of the LED port. - * - * \return Value of the LED port - * Every bit represents one physical LED. - */ -unsigned int get_led_port(void); - - -#ifdef __cplusplus -} -#endif -#endif /* __LED_PORT_H__ */ diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Include/serial.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Include/serial.h deleted file mode 100644 index 77f15a4..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Include/serial.h +++ /dev/null @@ -1,33 +0,0 @@ -/* -* Copyright (c) 2017 Arm Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - - -#include - -/** - * \brief Initializes default UART device - */ -void serial_init(void); - -/** - * \brief Prints a string through the default UART device - */ -void serial_print(char *str); - -#endif /* __SERIAL_H__ */ diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Include/timeout.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Include/timeout.h deleted file mode 100644 index a9931ae..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Include/timeout.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2017-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __TIMEOUT_H__ -#define __TIMEOUT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "device_definition.h" - -/* Structure to maintain elapsed time */ -struct timeout_t { - void *dev_ptr; - bool is_initialized; -}; - -/** - * \brief Initializes timout structure - * - * \param[in] timeout Pointer to the timeout structure - * \param[in] delay Delay in ms to check timeout against - * - * \return Returns true if the delay value was set, - * false otherwise - */ -bool timeout_init(struct timeout_t *timeout, uint32_t delay); - -/** - * \brief Checks if the given time has passed or not - * - * \param[in] timer Pointer to the timer structure - * - * \details This function compares the timestamp stored in the timeout structure - * and the current time. If the difference is more than the given delay, - * the current time is stored and will be used for the next comparison - * - * \return 1 if the given time has passed, 0 if not - */ -bool timeout_delay_is_elapsed(struct timeout_t *timeout); - -/** - * \brief Uninitializes timout structure and stops timer operation. - * - * \param[in] timeout Pointer to the timeout structure - */ -void timeout_uninit(struct timeout_t *timeout); - -/** - * \brief Waits the specified time in milliseconds. - * - * \param[in] ms Time to wait in milliseconds - */ -void wait_ms(uint32_t ms); - -#ifdef __cplusplus -} -#endif -#endif /* __TIMEOUT_H__ */ diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Source/led_port.c b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Source/led_port.c deleted file mode 100644 index 109495a..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Source/led_port.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "led_port.h" -#include "arm_mps3_io_drv.h" -#include "device_cfg.h" -#include "device_definition.h" - -#define MAX_PIN_FPGAIO_LED 10UL -#define MAX_LED_MASK ((1U << MAX_PIN_FPGAIO_LED) - 1) -#define BIT_VALUE(v, bit) (((v) >> (bit) & 1UL)) - -static unsigned int led_status; - -unsigned int get_led_port_bit_length(void) -{ - return MAX_PIN_FPGAIO_LED; -} - -void led_port_init(void) -{ - /* Turn off all LEDs at init */ - arm_mps3_io_write_leds(&MPS3_IO_DEV, ARM_MPS3_IO_ACCESS_PORT, 0, 0); - led_status = 0x0; -} - -unsigned int set_led_port(unsigned int led_mask) -{ - uint8_t i; - uint32_t value; - - if (led_mask > MAX_LED_MASK) { - return 1; - } - - /* Set the LEDs to new value one by one */ - for (i = 0; i < MAX_PIN_FPGAIO_LED; i++) { - if (BIT_VALUE((led_mask ^ led_status), i)) { - /* led pin i has new value */ - value = BIT_VALUE(led_mask, i); - arm_mps3_io_write_leds(&MPS3_IO_DEV, - ARM_MPS3_IO_ACCESS_PIN, - i, value); - } - } - led_status = led_mask; - - return 0; -} - -/** - * \brief Get the value of the LED port. - * - * \return Value of the LED port - * Every bit represents one physical LED. - */ -unsigned int get_led_port(void) -{ - return arm_mps3_io_read_leds(&MPS3_IO_DEV, - ARM_MPS3_IO_ACCESS_PORT, - 0); -} diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Source/serial.c b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Source/serial.c deleted file mode 100644 index 475f4e3..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Source/serial.c +++ /dev/null @@ -1,55 +0,0 @@ -/* -* Copyright (c) 2017-2020 Arm Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#include -#include -#include "device_cfg.h" -#include "Driver_USART.h" -#include "serial.h" - -extern ARM_DRIVER_USART Driver_USART0; - -void serial_init(void) -{ - Driver_USART0.Initialize(NULL); - Driver_USART0.Control(ARM_USART_MODE_ASYNCHRONOUS, DEFAULT_UART_BAUDRATE); -} - -void serial_print(char *str) -{ - (void)Driver_USART0.Send(str, strlen(str)); -} - -/* Struct FILE is implemented in stdio.h. Used to redirect printf to UART0 */ -//FILE __stdout; -/* Redirects armclang printf to UART */ -int stdout_putchar(int ch) -{ - if (Driver_USART0.Send(&ch, 1) == ARM_DRIVER_OK) { - return ch; - } - return EOF; -} - -/* Redirects gcc printf to UART0 */ -int _write(int fd, char *str, int len) -{ - if (Driver_USART0.Send(str, len) == ARM_DRIVER_OK) { - return len; - } - return 0; -} - diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Source/systimer_armv8-m_timeout.c b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Source/systimer_armv8-m_timeout.c deleted file mode 100644 index dc79876..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/API/Source/systimer_armv8-m_timeout.c +++ /dev/null @@ -1,73 +0,0 @@ -/* -* Copyright (c) 2019-2020 Arm Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#include "timeout.h" -#include "device_cfg.h" -#include "systimer_armv8-m_drv.h" -#include "syscounter_armv8-m_cntrl_drv.h" -#include "platform_description.h" - -#define MS_TO_TICK(ms) ((ms) * (SystemCoreClock / 1000)) - -/* Systimer is configured over the 32-bit down-counting Timer view, so maximum - * delay is defined by its bit width. */ -#define MAX_DELAY_MS (UINT32_MAX / \ - (SystemCoreClock / 1000)) - -static uint32_t delay_in_tick; - -bool timeout_init(struct timeout_t *timeout, uint32_t delay) -{ - struct systimer_armv8_m_dev_t *dev; - - if (!timeout || delay > MAX_DELAY_MS) { - return false; - } - - if (timeout->is_initialized) { - return false; - } - - syscounter_armv8_m_cntrl_init(&SYSCOUNTER_CNTRL_ARMV8_M_DEV); - - dev = &SYSTIMER0_ARMV8_M_DEV; - systimer_armv8_m_init(dev); - - delay_in_tick = MS_TO_TICK(delay); - systimer_armv8_m_set_timer_value(dev, delay_in_tick); - - timeout->dev_ptr = (void *)dev; - timeout->is_initialized = true; - - return true; -} - -bool timeout_delay_is_elapsed(struct timeout_t *timeout) -{ - struct systimer_armv8_m_dev_t* dev; - - if (!timeout || !timeout->is_initialized) { - return false; - } - - dev = (struct systimer_armv8_m_dev_t*)timeout->dev_ptr; - if (systimer_armv8_m_is_interrupt_asserted(dev)) { - systimer_armv8_m_set_timer_value(dev, delay_in_tick); - return true; - } - - return false; -} diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/RTE_Device.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/RTE_Device.h deleted file mode 100644 index 8de4d3a..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/RTE_Device.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::Drivers:USART -#define RTE_USART0 1 -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] - -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::Drivers:USART -#define RTE_USART1 1 -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] - -// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] -// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC -#define RTE_ISRAM0_MPC 1 -// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] - -// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] -// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC -#define RTE_ISRAM1_MPC 1 -// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] - -// MPC (Memory Protection Controller) [Driver_SRAM_MPC] -// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC -#define RTE_SRAM_MPC 1 -// MPC (Memory Protection Controller) [Driver_SRAM_MPC] - -// MPC (Memory Protection Controller) [Driver_QSPI_MPC] -// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC -#define RTE_QSPI_MPC 1 -// MPC (Memory Protection Controller) [Driver_QSPI_MPC] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] -// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] -// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN_EXP0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] -// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN_EXP1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP1] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] -// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] -// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH1] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP1] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP2 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP2] - -// Flash device emulated by SRAM [Driver_Flash0] -// Configuration settings for Driver_Flash0 in component ::Drivers:Flash -#define RTE_FLASH0 1 -// Flash device emulated by SRAM [Driver_Flash0] - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h deleted file mode 100644 index 5ad6fb6..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_DRIVER_CONFIG_H__ -#define __CMSIS_DRIVER_CONFIG_H__ - -#include "system_core_init.h" -#include "device_cfg.h" -#include "device_definition.h" -#include "platform_base_address.h" - -#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/device_cfg.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/device_cfg.h deleted file mode 100644 index d3591f2..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/device_cfg.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __DEVICE_CFG_H__ -#define __DEVICE_CFG_H__ - -/** - * \file device_cfg.h - * \brief Configuration file native driver re-targeting - * - * \details This file can be used to add native driver specific macro - * definitions to select which peripherals are available in the build. - * - * This is a default device configuration file with all peripherals enabled. - */ - -/* Secure only peripheral configuration */ - -/* ARM MPS3 IO SCC */ -#define MPS3_IO_S -#define MPS3_IO_DEV MPS3_IO_DEV_S - -/* ARM UART Controller PL011 */ -#define UART0_CMSDK_S -#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S -#define UART1_CMSDK_S -#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S - -#define DEFAULT_UART_BAUDRATE 115200U - -/* To be used as CODE and DATA sram */ -#define MPC_ISRAM0_S -#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S - -#define MPC_ISRAM1_S -#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S - -#define MPC_SRAM_S -#define MPC_SRAM_DEV MPC_SRAM_DEV_S - -#define MPC_QSPI_S -#define MPC_QSPI_DEV MPC_QSPI_DEV_S - -/** System Counter Armv8-M */ -#define SYSCOUNTER_CNTRL_ARMV8_M_S -#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S - -#define SYSCOUNTER_READ_ARMV8_M_S -#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S -/** - * Arbitrary scaling values for test purposes - */ -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u - -/* System timer */ -#define SYSTIMER0_ARMV8_M_S -#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S -#define SYSTIMER1_ARMV8_M_S -#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S -#define SYSTIMER2_ARMV8_M_S -#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S -#define SYSTIMER3_ARMV8_M_S -#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S - -#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) - -/* CMSDK GPIO driver structures */ -#define GPIO0_CMSDK_S -#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S -#define GPIO1_CMSDK_S -#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S -#define GPIO2_CMSDK_S -#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S -#define GPIO3_CMSDK_S -#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S - -/* ARM MPS3 IO FPGAIO driver structures */ -#define ARM_MPS3_IO_FPGAIO_S -#define ARM_MPS3_IO_FPGAIO_DEV ARM_MPS3_IO_FPGAIO_DEV_S - -/* System Watchdogs */ -#define SYSWDOG_ARMV8_M_S -#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S - -/* ARM MPC SIE 300 driver structures */ -#define MPC_VM0_S -#define MPC_VM0_DEV MPC_VM0_DEV_S -#define MPC_VM1_S -#define MPC_VM1_DEV MPC_VM1_DEV_S -#define MPC_SSRAM2_S -#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S -#define MPC_SSRAM3_S -#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S - -/* ARM PPC driver structures */ -#define PPC_SSE300_MAIN0_S -#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S -#define PPC_SSE300_MAIN_EXP0_S -#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S -#define PPC_SSE300_MAIN_EXP1_S -#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S -#define PPC_SSE300_MAIN_EXP2_S -#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S -#define PPC_SSE300_MAIN_EXP3_S -#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S -#define PPC_SSE300_PERIPH0_S -#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S -#define PPC_SSE300_PERIPH1_S -#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S -#define PPC_SSE300_PERIPH_EXP0_S -#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S -#define PPC_SSE300_PERIPH_EXP1_S -#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S -#define PPC_SSE300_PERIPH_EXP2_S -#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S -#define PPC_SSE300_PERIPH_EXP3_S -#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S - -/* ARM SPI PL022 */ -/* Invalid device stubs are not defined */ -#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ -#define SPI1_PL022_S -#define SPI1_PL022_DEV SPI1_PL022_DEV_S - - -#endif /* __DEVICE_CFG_H__ */ \ No newline at end of file diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct deleted file mode 100644 index f289ee3..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct +++ /dev/null @@ -1,78 +0,0 @@ -#! armclang --target=arm-arm-none-eabi -mcpu=cortex-m55 -E -xc - -;/* -; * Copyright (c) 2018-2021 Arm Limited. All rights reserved. -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; */ - -#include "region_defs.h" - -LR_CODE S_CODE_START { - ER_CODE S_CODE_START { - *.o (RESET +First) - .ANY (+RO) - } - - /* - * Place the CMSE Veneers (containing the SG instruction) after the code, in - * a separate 32 bytes aligned region so that the SAU can programmed to just - * set this region as Non-Secure Callable. The maximum size of this - * executable region makes it only used the space left over by the ER_CODE - * region so that you can rely on code+veneer size combined will not exceed - * the S_CODE_SIZE value. We also substract from the available space the - * area used to align this section on 32 bytes boundary (for SAU conf). - */ - ER_CODE_CMSE_VENEER +0 ALIGN 32 { - *(Veneer$$CMSE) - } - /* - * This dummy region ensures that the next one will be aligned on a 32 bytes - * boundary, so that the following region will not be mistakenly configured - * as Non-Secure Callable by the SAU. - */ - ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {} - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - CODE_WATERMARK +0 EMPTY 0x0 { - } - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) - - ER_DATA S_DATA_START { - .ANY (+ZI +RW) - } - - #if HEAP_SIZE > 0 - ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap - } - #endif - - ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack - } - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - SRAM_WATERMARK +0 EMPTY 0x0 { - } - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) -} diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/platform_base_address.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/platform_base_address.h deleted file mode 100644 index c5c3ee7..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/platform_base_address.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 2019-2021 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file platform_base_address.h - * \brief This file defines all the peripheral base addresses for MPS3 SSE-300 + - * Ethos-U55 AN547 platform. - */ - -#ifndef __PLATFORM_BASE_ADDRESS_H__ -#define __PLATFORM_BASE_ADDRESS_H__ - -/* ======= Defines peripherals memory map addresses ======= */ -/* Non-secure memory map addresses */ -#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ -#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */ -#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */ -#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */ -#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */ -#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */ -#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ -#define ISRAM1_BASE_NS 0x21200000 /* Internal SRAM Area Non-Secure base address */ -#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ -#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ -#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */ -/* Non-Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */ -#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */ -#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */ -#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */ -#define AHB_USER_0_BASE_NS 0x41104000 /* AHB USER 0 Non-Secure base address */ -#define AHB_USER_1_BASE_NS 0x41105000 /* AHB USER 1 Non-Secure base address */ -#define AHB_USER_2_BASE_NS 0x41106000 /* AHB USER 2 Non-Secure base address */ -#define AHB_USER_3_BASE_NS 0x41107000 /* AHB USER 3 Non-Secure base address */ -#define DMA_0_BASE_NS 0x41200000 /* DMA 0 Non-Secure base address */ -#define DMA_1_BASE_NS 0x41201000 /* DMA 1 Non-Secure base address */ -#define DMA_2_BASE_NS 0x41202000 /* DMA 2 Non-Secure base address */ -#define DMA_3_BASE_NS 0x41203000 /* DMA 3 Non-Secure base address */ -#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */ -#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */ -#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */ -#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */ -#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */ -#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */ -#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */ -#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ -#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ -#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ -/* Non-Secure MSTEXPPIHL Peripheral region */ -#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */ -#define U55_TIMING_ADAPTER_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter registers Non-Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ -#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */ -#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ -#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */ -#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */ -#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ -#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */ -#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */ -#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */ -#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */ -#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */ -#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */ -#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */ -#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */ -#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */ -#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */ -#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */ -#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */ - -/* Secure memory map addresses */ -#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ -#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */ -#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */ -#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */ -#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */ -#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */ -#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ -#define ISRAM1_BASE_S 0x31200000 /* Internal SRAM Area Secure base address */ -#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ -/* Secure Subsystem peripheral region */ -#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ -#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ -#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ -#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */ -#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */ -#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */ -/* Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */ -#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */ -#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */ -#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */ -#define AHB_USER_0_BASE_S 0x51104000 /* AHB USER 0 Secure base address */ -#define AHB_USER_1_BASE_S 0x51105000 /* AHB USER 1 Secure base address */ -#define AHB_USER_2_BASE_S 0x51106000 /* AHB USER 2 Secure base address */ -#define AHB_USER_3_BASE_S 0x51107000 /* AHB USER 3 Secure base address */ -#define DMA_0_BASE_S 0x51200000 /* DMA 0 Secure base address */ -#define DMA_1_BASE_S 0x51201000 /* DMA 1 Secure base address */ -#define DMA_2_BASE_S 0x51202000 /* DMA 2 Secure base address */ -#define DMA_3_BASE_S 0x51203000 /* DMA 3 Secure base address */ -#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */ -#define USB_BASE_S 0x51500000 /* USB Secure base address */ -#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */ -#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */ -#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */ -#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */ -#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */ -#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */ -#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */ -#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */ -#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */ -/* Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */ -#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */ -#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */ -#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */ -#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */ -#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */ -#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */ -#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ -#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */ -#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ -/* Secure MSTEXPPIHL Peripheral region */ -#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */ -#define U55_TIMING_ADAPTER_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter registers Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ -#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */ -#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ -#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */ -#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */ -#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ -#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */ -#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */ -#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */ -#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */ -#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */ -#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */ -#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */ -#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */ -#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */ -#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ -#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ -#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */ - -/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ -#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller - * Access from Non-secure software is only allowed - * if AIRCR.BFHFNMINS is set to 1 */ - -/* Memory size definitions */ -#define ITCM_SIZE (0x00080000) /* 512 kB */ -#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */ -#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ -#define SRAM_SIZE (0x00200000) /* 2 MB */ -#define ISRAM0_SIZE (0x00200000) /* 2 MB */ -#define ISRAM1_SIZE (0x00200000) /* 2 MB */ -#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ -#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ -#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ - -/* Defines for Driver MPC's */ -/* SRAM -- 2 MB */ -#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS) -#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_NS (0x0) -#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S) -#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_S (0x0) - -/* QSPI -- 8 MB*/ -#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS) -#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_NS (0x0) -#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S) -#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_S (0x0) - -/* ISRAM0 -- 2 MB*/ -#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS) -#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S) -#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_S (0x0) - -/* ISRAM1 -- 2 MB*/ -#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS) -#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S) -#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_S (0x0) - -/* DDR4 -- 2GB (8 * 256 MB) */ -#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0) -#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S) -#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S) -#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S) -#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S) -#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS) - -#endif /* __PLATFORM_BASE_ADDRESS_H__ */ diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_defs.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_defs.h deleted file mode 100644 index c8cd919..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_defs.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2016-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_DEFS_H__ -#define __REGION_DEFS_H__ - -#include "region_limits.h" - -/* ************************************************************** - * WARNING: this file is parsed both by the C/C++ compiler - * and the linker. As a result the syntax must be valid not only - * for C/C++ but for the linker scripts too. - * Beware of the following limitations: - * - LD (GCC linker) requires white space around operators. - * - UL postfix for macros is not suported by the linker script - ****************************************************************/ - -/* Secure regions */ -#define S_CODE_START ( S_ROM_ALIAS ) -#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) -#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) - -#define S_DATA_START ( S_RAM_ALIAS ) -#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) -#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) - -/* Non-Secure regions */ -#define NS_CODE_START ( NS_ROM_ALIAS ) -#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) -#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) - -#define NS_DATA_START ( NS_RAM_ALIAS ) -#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) -#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) - -#endif /* __REGION_DEFS_H__ */ diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_limits.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_limits.h deleted file mode 100644 index 58a76c7..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_limits.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2018-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_LIMITS_H__ -#define __REGION_LIMITS_H__ - -/* ************************************************************** - * WARNING: this file is parsed both by the C/C++ compiler - * and the linker. As a result the syntax must be valid not only - * for C/C++ but for the linker scripts too. - * Beware of the following limitations: - * - LD (GCC linker) requires white space around operators. - * - UL postfix for macros is not suported by the linker script - ****************************************************************/ - -/* Secure Code */ -#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ -#define TOTAL_S_ROM_SIZE (0x00080000) /* 256 kB */ - -/* Secure Data */ -#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ -#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ - - -/* Non-Secure Code */ -#define NS_ROM_ALIAS (0x01000000) /* SRAM_BASE_NS */ -#define TOTAL_NS_ROM_SIZE (0x00080000) /* 256 kB */ - -/* Non-Secure Data */ -#define NS_RAM_ALIAS (0x21000000) /* ISRAM0_BASE_NS */ -#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ - - -/* Heap and Stack sizes for secure and nonsecure applications */ -#define HEAP_SIZE (0x0000C000) /* 1 KiB */ -#define STACK_SIZE (0x00008000) /* 1 KiB */ - -#endif /* __REGION_LIMITS_H__ */ diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c deleted file mode 100644 index 53e367c..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "cmsis.h" - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler Function Prototype - *----------------------------------------------------------------------------*/ -typedef void( *pFunc )( void ); - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; - -extern void __PROGRAM_START(void) __NO_RETURN; - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Reset_Handler (void) __NO_RETURN; - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -#define DEFAULT_IRQ_HANDLER(handler_name) \ -void __WEAK handler_name(void); \ -void handler_name(void) { \ - while(1); \ -} - -/* Exceptions */ -DEFAULT_IRQ_HANDLER(NMI_Handler) -DEFAULT_IRQ_HANDLER(HardFault_Handler) -DEFAULT_IRQ_HANDLER(MemManage_Handler) -DEFAULT_IRQ_HANDLER(BusFault_Handler) -DEFAULT_IRQ_HANDLER(UsageFault_Handler) -DEFAULT_IRQ_HANDLER(SecureFault_Handler) -DEFAULT_IRQ_HANDLER(SVC_Handler) -DEFAULT_IRQ_HANDLER(DebugMon_Handler) -DEFAULT_IRQ_HANDLER(PendSV_Handler) -DEFAULT_IRQ_HANDLER(SysTick_Handler) - -DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler) -DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) -DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) -DEFAULT_IRQ_HANDLER(TIMER0_Handler) -DEFAULT_IRQ_HANDLER(TIMER1_Handler) -DEFAULT_IRQ_HANDLER(TIMER2_Handler) -DEFAULT_IRQ_HANDLER(MPC_Handler) -DEFAULT_IRQ_HANDLER(PPC_Handler) -DEFAULT_IRQ_HANDLER(MSC_Handler) -DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) -DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) -DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) -DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) -DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) -DEFAULT_IRQ_HANDLER(TIMER3_Handler) -DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler) -DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler) - -DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) -DEFAULT_IRQ_HANDLER(UARTRX0_Handler) -DEFAULT_IRQ_HANDLER(UARTTX0_Handler) -DEFAULT_IRQ_HANDLER(UARTRX1_Handler) -DEFAULT_IRQ_HANDLER(UARTTX1_Handler) -DEFAULT_IRQ_HANDLER(UARTRX2_Handler) -DEFAULT_IRQ_HANDLER(UARTTX2_Handler) -DEFAULT_IRQ_HANDLER(UARTRX3_Handler) -DEFAULT_IRQ_HANDLER(UARTTX3_Handler) -DEFAULT_IRQ_HANDLER(UARTRX4_Handler) -DEFAULT_IRQ_HANDLER(UARTTX4_Handler) -DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) -DEFAULT_IRQ_HANDLER(UARTOVF_Handler) -DEFAULT_IRQ_HANDLER(ETHERNET_Handler) -DEFAULT_IRQ_HANDLER(I2S_Handler) -DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) -DEFAULT_IRQ_HANDLER(USB_Handler) -DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) -DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) -DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) -DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) -DEFAULT_IRQ_HANDLER(UARTRX5_Handler) -DEFAULT_IRQ_HANDLER(UARTTX5_Handler) -DEFAULT_IRQ_HANDLER(UART5_Handler) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const pFunc __VECTOR_TABLE[496]; - const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14: NMI Handler */ - HardFault_Handler, /* -13: Hard Fault Handler */ - MemManage_Handler, /* -12: MPU Fault Handler */ - BusFault_Handler, /* -11: Bus Fault Handler */ - UsageFault_Handler, /* -10: Usage Fault Handler */ - SecureFault_Handler, /* -9: Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5: SVCall Handler */ - DebugMon_Handler, /* -4: Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2: PendSV Handler */ - SysTick_Handler, /* -1: SysTick Handler */ - - NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */ - NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ - SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ - TIMER0_Handler, /* 3: TIMER 0 Handler */ - TIMER1_Handler, /* 4: TIMER 1 Handler */ - TIMER2_Handler, /* 5: TIMER 2 Handler */ - 0, /* 6: Reserved */ - 0, /* 7: Reserved */ - 0, /* 8: Reserved */ - MPC_Handler, /* 9: MPC Combined (Secure) Handler */ - PPC_Handler, /* 10: PPC Combined (Secure) Handler */ - MSC_Handler, /* 11: MSC Combined (Secure) Handler */ - BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ - 0, /* 13: Reserved */ - MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ - SYS_PPU_Handler, /* 15: SYS PPU Handler */ - CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ - 0, /* 17: Reserved */ - 0, /* 18: Reserved */ - 0, /* 19: Reserved */ - 0, /* 20: Reserved */ - 0, /* 21: Reserved */ - 0, /* 22: Reserved */ - 0, /* 23: Reserved */ - 0, /* 24: Reserved */ - 0, /* 25: Reserved */ - DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ - TIMER3_Handler, /* 27: TIMER 3 Handler */ - CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */ - CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */ - 0, /* 30: Reserved */ - 0, /* 31: Reserved */ - - /* External interrupts */ - System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ - UARTRX0_Handler, /* 33: UART 0 RX Handler */ - UARTTX0_Handler, /* 34: UART 0 TX Handler */ - UARTRX1_Handler, /* 35: UART 1 RX Handler */ - UARTTX1_Handler, /* 36: UART 1 TX Handler */ - UARTRX2_Handler, /* 37: UART 2 RX Handler */ - UARTTX2_Handler, /* 38: UART 2 TX Handler */ - UARTRX3_Handler, /* 39: UART 3 RX Handler */ - UARTTX3_Handler, /* 40: UART 3 TX Handler */ - UARTRX4_Handler, /* 41: UART 4 RX Handler */ - UARTTX4_Handler, /* 42: UART 4 TX Handler */ - UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ - UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ - UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ - UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ - UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ - UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ - ETHERNET_Handler, /* 49: Ethernet Handler */ - I2S_Handler, /* 50: Audio I2S Handler */ - TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ - USB_Handler, /* 52: USB Handler */ - SPI_ADC_Handler, /* 53: SPI ADC Handler */ - SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ - SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ - ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ - 0, /* 57: Reserved */ - 0, /* 58: Reserved */ - 0, /* 59: Reserved */ - 0, /* 60: Reserved */ - 0, /* 61: Reserved */ - 0, /* 62: Reserved */ - 0, /* 63: Reserved */ - 0, /* 64: Reserved */ - 0, /* 65: Reserved */ - 0, /* 66: Reserved */ - 0, /* 67: Reserved */ - 0, /* 68: Reserved */ - GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ - GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ - GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ - GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ - GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ - GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ - GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ - GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ - GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ - GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ - GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ - GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ - GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ - GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ - GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ - GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ - GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ - GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ - GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ - GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ - GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ - GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ - GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ - GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ - GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ - GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ - GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ - GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ - GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ - GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ - GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ - GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ - GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ - GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ - GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ - GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ - GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ - GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ - GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ - GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ - GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ - GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ - GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ - GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ - GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ - GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ - GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ - GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ - GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ - GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ - GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ - GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ - GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ - GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ - GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ - GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ - UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ - UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ - UART5_Handler, /* 127: UART 5 combined Interrupt */ - 0, /* 128: Reserved */ - 0, /* 129: Reserved */ - 0, /* 130: Reserved */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/micro_time.cc b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/micro_time.cc deleted file mode 100644 index 023ac6d..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/micro_time.cc +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -#include "tensorflow/lite/micro/micro_time.h" - -// DWT (Data Watchpoint and Trace) registers, only exists on ARM Cortex with a -// DWT unit. -#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) -/*!< DWT Control register */ - -// DWT Control register. -#define KIN1_DWT_CYCCNTENA_BIT (1UL << 0) - -// CYCCNTENA bit in DWT_CONTROL register. -#define KIN1_DWT_CYCCNT (*((volatile uint32_t*)0xE0001004)) - -// DWT Cycle Counter register. -#define KIN1_DEMCR (*((volatile uint32_t*)0xE000EDFC)) - -// DEMCR: Debug Exception and Monitor Control Register. -#define KIN1_TRCENA_BIT (1UL << 24) - -#define KIN1_LAR (*((volatile uint32_t*)0xE0001FB0)) - -#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) - -// Unlock access to DWT (ITM, etc.)registers. -#define KIN1_UnlockAccessToDWT() KIN1_LAR = 0xC5ACCE55; - -// TRCENA: Enable trace and debug block DEMCR (Debug Exception and Monitor -// Control Register. -#define KIN1_InitCycleCounter() KIN1_DEMCR |= KIN1_TRCENA_BIT - -#define KIN1_ResetCycleCounter() KIN1_DWT_CYCCNT = 0 -#define KIN1_EnableCycleCounter() KIN1_DWT_CONTROL |= KIN1_DWT_CYCCNTENA_BIT -#define KIN1_DisableCycleCounter() KIN1_DWT_CONTROL &= ~KIN1_DWT_CYCCNTENA_BIT -#define KIN1_GetCycleCounter() KIN1_DWT_CYCCNT - -namespace tflite { - -int32_t ticks_per_second() { return 0; } - -int32_t GetCurrentTimeTicks() { - static bool is_initialized = false; - if (!is_initialized) { - KIN1_UnlockAccessToDWT(); - KIN1_InitCycleCounter(); - KIN1_ResetCycleCounter(); - KIN1_EnableCycleCounter(); - is_initialized = true; - } - return KIN1_GetCycleCounter(); -} - -} // namespace tflite diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/Pre_Include_Global.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/Pre_Include_Global.h deleted file mode 100644 index 6234fa2..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/Pre_Include_Global.h +++ /dev/null @@ -1,18 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'template_Corstone300' - * Target: 'template_Corstone300' - */ - -#ifndef PRE_INCLUDE_GLOBAL_H -#define PRE_INCLUDE_GLOBAL_H - -/* tensorflow::Machine Learning:TensorFlow:Kernel:CMSIS-NN:0.1.20210416 */ -// enabling global pre includes - #define TF_LITE_STATIC_MEMORY 1 - - -#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/RTE_Components.h b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/RTE_Components.h deleted file mode 100644 index 452f25e..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/RTE_Components.h +++ /dev/null @@ -1,35 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'template_Corstone300' - * Target: 'template_Corstone300' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "SSE300MPS3.h" - -/* ARM::CMSIS Driver:USART:1.0.0 */ -#define RTE_Drivers_USART -/* tensorflow::Data Exchange:Serialization:flatbuffers:tensorflow:1.12.0 */ -#define RTE_DataExchange_Serialization_flatbuffers /* flatbuffers */ -/* tensorflow::Data Processing:Math:gemmlowp fixed-point:tensorflow:1.0.0 */ -#define RTE_DataExchange_Math_gemmlowp /* gemmlowp */ -/* tensorflow::Data Processing:Math:kissfft:tensorflow:1.4.5 */ -#define RTE_DataExchange_Math_kissfft /* kissfft */ -/* tensorflow::Data Processing:Math:ruy:tensorflow:1.12.0 */ -#define RTE_DataProcessing_Math_ruy /* ruy */ -/* tensorflow::Machine Learning:TensorFlow:Kernel:CMSIS-NN:0.1.20210416 */ -#define RTE_ML_TF_LITE /* TF */ -/* tensorflow::Machine Learning:TensorFlow:Testing:0.1.20210416 */ -#define RTE_ML_TF_LITE /* TF */ - - -#endif /* RTE_COMPONENTS_H */ diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/SSE-300-MPS3.cprj b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/SSE-300-MPS3.cprj deleted file mode 100644 index 7e3dd75..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/SSE-300-MPS3.cprj +++ /dev/null @@ -1,85 +0,0 @@ - - - - - UnitTestTemplate - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _file_block_xml_ - - - - - diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/packlist b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/packlist deleted file mode 100644 index c9c5636..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/packlist +++ /dev/null @@ -1 +0,0 @@ -https://keilpack.azureedge.net/pack/ARM.V2M_MPS3_SSE_300_BSP.1.1.0.pack diff --git a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/platform_setup.c b/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/platform_setup.c deleted file mode 100644 index 279de43..0000000 --- a/tensorflow-test/templates/CMSIS-NN/ARMCLANG/SSE-300-MPS3/platform_setup.c +++ /dev/null @@ -1,10 +0,0 @@ - - -int platform_setup (void) -{ - serial_init(); - - -} - - diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Include/led_port.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Include/led_port.h deleted file mode 100644 index e9e6e28..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Include/led_port.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2017 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __LED_PORT_H__ -#define __LED_PORT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* The goal of this file is to create a common LED API for different targets in order - * create common example applications. - */ - -/* Note: Currently this API doesn't handle the case when a peripheral is - * mapped to secure and non-secure region as well, but could be extended - * to select secure or non-secure one. - */ - -/** - * \brief Get the number of bits of LED port, - * in the current platform, that can be - * read and written in one chunk. - * - * \return Available number of bits of LED port. - */ -unsigned int get_led_port_bit_length(void); - -/** - * \brief Initializes LED device if needed - */ -void led_port_init(void); - -/** - * \brief Set the value of the LED port. - * - * \param[in] led Value of the LED port will be set. - * Every bit represents one physical LED. - * - * \return 0 if succeeded, 1 otherwise - */ -unsigned int set_led_port(unsigned int led_mask); - -/** - * \brief Get the value of the LED port. - * - * \return Value of the LED port - * Every bit represents one physical LED. - */ -unsigned int get_led_port(void); - - -#ifdef __cplusplus -} -#endif -#endif /* __LED_PORT_H__ */ diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Include/serial.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Include/serial.h deleted file mode 100644 index 77f15a4..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Include/serial.h +++ /dev/null @@ -1,33 +0,0 @@ -/* -* Copyright (c) 2017 Arm Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - - -#include - -/** - * \brief Initializes default UART device - */ -void serial_init(void); - -/** - * \brief Prints a string through the default UART device - */ -void serial_print(char *str); - -#endif /* __SERIAL_H__ */ diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Include/timeout.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Include/timeout.h deleted file mode 100644 index a9931ae..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Include/timeout.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2017-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __TIMEOUT_H__ -#define __TIMEOUT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "device_definition.h" - -/* Structure to maintain elapsed time */ -struct timeout_t { - void *dev_ptr; - bool is_initialized; -}; - -/** - * \brief Initializes timout structure - * - * \param[in] timeout Pointer to the timeout structure - * \param[in] delay Delay in ms to check timeout against - * - * \return Returns true if the delay value was set, - * false otherwise - */ -bool timeout_init(struct timeout_t *timeout, uint32_t delay); - -/** - * \brief Checks if the given time has passed or not - * - * \param[in] timer Pointer to the timer structure - * - * \details This function compares the timestamp stored in the timeout structure - * and the current time. If the difference is more than the given delay, - * the current time is stored and will be used for the next comparison - * - * \return 1 if the given time has passed, 0 if not - */ -bool timeout_delay_is_elapsed(struct timeout_t *timeout); - -/** - * \brief Uninitializes timout structure and stops timer operation. - * - * \param[in] timeout Pointer to the timeout structure - */ -void timeout_uninit(struct timeout_t *timeout); - -/** - * \brief Waits the specified time in milliseconds. - * - * \param[in] ms Time to wait in milliseconds - */ -void wait_ms(uint32_t ms); - -#ifdef __cplusplus -} -#endif -#endif /* __TIMEOUT_H__ */ diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Source/led_port.c b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Source/led_port.c deleted file mode 100644 index 109495a..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Source/led_port.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "led_port.h" -#include "arm_mps3_io_drv.h" -#include "device_cfg.h" -#include "device_definition.h" - -#define MAX_PIN_FPGAIO_LED 10UL -#define MAX_LED_MASK ((1U << MAX_PIN_FPGAIO_LED) - 1) -#define BIT_VALUE(v, bit) (((v) >> (bit) & 1UL)) - -static unsigned int led_status; - -unsigned int get_led_port_bit_length(void) -{ - return MAX_PIN_FPGAIO_LED; -} - -void led_port_init(void) -{ - /* Turn off all LEDs at init */ - arm_mps3_io_write_leds(&MPS3_IO_DEV, ARM_MPS3_IO_ACCESS_PORT, 0, 0); - led_status = 0x0; -} - -unsigned int set_led_port(unsigned int led_mask) -{ - uint8_t i; - uint32_t value; - - if (led_mask > MAX_LED_MASK) { - return 1; - } - - /* Set the LEDs to new value one by one */ - for (i = 0; i < MAX_PIN_FPGAIO_LED; i++) { - if (BIT_VALUE((led_mask ^ led_status), i)) { - /* led pin i has new value */ - value = BIT_VALUE(led_mask, i); - arm_mps3_io_write_leds(&MPS3_IO_DEV, - ARM_MPS3_IO_ACCESS_PIN, - i, value); - } - } - led_status = led_mask; - - return 0; -} - -/** - * \brief Get the value of the LED port. - * - * \return Value of the LED port - * Every bit represents one physical LED. - */ -unsigned int get_led_port(void) -{ - return arm_mps3_io_read_leds(&MPS3_IO_DEV, - ARM_MPS3_IO_ACCESS_PORT, - 0); -} diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Source/serial.c b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Source/serial.c deleted file mode 100644 index 475f4e3..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Source/serial.c +++ /dev/null @@ -1,55 +0,0 @@ -/* -* Copyright (c) 2017-2020 Arm Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#include -#include -#include "device_cfg.h" -#include "Driver_USART.h" -#include "serial.h" - -extern ARM_DRIVER_USART Driver_USART0; - -void serial_init(void) -{ - Driver_USART0.Initialize(NULL); - Driver_USART0.Control(ARM_USART_MODE_ASYNCHRONOUS, DEFAULT_UART_BAUDRATE); -} - -void serial_print(char *str) -{ - (void)Driver_USART0.Send(str, strlen(str)); -} - -/* Struct FILE is implemented in stdio.h. Used to redirect printf to UART0 */ -//FILE __stdout; -/* Redirects armclang printf to UART */ -int stdout_putchar(int ch) -{ - if (Driver_USART0.Send(&ch, 1) == ARM_DRIVER_OK) { - return ch; - } - return EOF; -} - -/* Redirects gcc printf to UART0 */ -int _write(int fd, char *str, int len) -{ - if (Driver_USART0.Send(str, len) == ARM_DRIVER_OK) { - return len; - } - return 0; -} - diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Source/systimer_armv8-m_timeout.c b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Source/systimer_armv8-m_timeout.c deleted file mode 100644 index dc79876..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/API/Source/systimer_armv8-m_timeout.c +++ /dev/null @@ -1,73 +0,0 @@ -/* -* Copyright (c) 2019-2020 Arm Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#include "timeout.h" -#include "device_cfg.h" -#include "systimer_armv8-m_drv.h" -#include "syscounter_armv8-m_cntrl_drv.h" -#include "platform_description.h" - -#define MS_TO_TICK(ms) ((ms) * (SystemCoreClock / 1000)) - -/* Systimer is configured over the 32-bit down-counting Timer view, so maximum - * delay is defined by its bit width. */ -#define MAX_DELAY_MS (UINT32_MAX / \ - (SystemCoreClock / 1000)) - -static uint32_t delay_in_tick; - -bool timeout_init(struct timeout_t *timeout, uint32_t delay) -{ - struct systimer_armv8_m_dev_t *dev; - - if (!timeout || delay > MAX_DELAY_MS) { - return false; - } - - if (timeout->is_initialized) { - return false; - } - - syscounter_armv8_m_cntrl_init(&SYSCOUNTER_CNTRL_ARMV8_M_DEV); - - dev = &SYSTIMER0_ARMV8_M_DEV; - systimer_armv8_m_init(dev); - - delay_in_tick = MS_TO_TICK(delay); - systimer_armv8_m_set_timer_value(dev, delay_in_tick); - - timeout->dev_ptr = (void *)dev; - timeout->is_initialized = true; - - return true; -} - -bool timeout_delay_is_elapsed(struct timeout_t *timeout) -{ - struct systimer_armv8_m_dev_t* dev; - - if (!timeout || !timeout->is_initialized) { - return false; - } - - dev = (struct systimer_armv8_m_dev_t*)timeout->dev_ptr; - if (systimer_armv8_m_is_interrupt_asserted(dev)) { - systimer_armv8_m_set_timer_value(dev, delay_in_tick); - return true; - } - - return false; -} diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/RTE_Device.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/RTE_Device.h deleted file mode 100644 index 8de4d3a..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/RTE_Device.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::Drivers:USART -#define RTE_USART0 1 -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] - -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::Drivers:USART -#define RTE_USART1 1 -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] - -// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] -// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC -#define RTE_ISRAM0_MPC 1 -// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] - -// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] -// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC -#define RTE_ISRAM1_MPC 1 -// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] - -// MPC (Memory Protection Controller) [Driver_SRAM_MPC] -// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC -#define RTE_SRAM_MPC 1 -// MPC (Memory Protection Controller) [Driver_SRAM_MPC] - -// MPC (Memory Protection Controller) [Driver_QSPI_MPC] -// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC -#define RTE_QSPI_MPC 1 -// MPC (Memory Protection Controller) [Driver_QSPI_MPC] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] -// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] -// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN_EXP0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] -// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN_EXP1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP1] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] -// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] -// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH1] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP1] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP2 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP2] - -// Flash device emulated by SRAM [Driver_Flash0] -// Configuration settings for Driver_Flash0 in component ::Drivers:Flash -#define RTE_FLASH0 1 -// Flash device emulated by SRAM [Driver_Flash0] - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h deleted file mode 100644 index 5ad6fb6..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_DRIVER_CONFIG_H__ -#define __CMSIS_DRIVER_CONFIG_H__ - -#include "system_core_init.h" -#include "device_cfg.h" -#include "device_definition.h" -#include "platform_base_address.h" - -#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/device_cfg.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/device_cfg.h deleted file mode 100644 index d3591f2..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/device_cfg.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __DEVICE_CFG_H__ -#define __DEVICE_CFG_H__ - -/** - * \file device_cfg.h - * \brief Configuration file native driver re-targeting - * - * \details This file can be used to add native driver specific macro - * definitions to select which peripherals are available in the build. - * - * This is a default device configuration file with all peripherals enabled. - */ - -/* Secure only peripheral configuration */ - -/* ARM MPS3 IO SCC */ -#define MPS3_IO_S -#define MPS3_IO_DEV MPS3_IO_DEV_S - -/* ARM UART Controller PL011 */ -#define UART0_CMSDK_S -#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S -#define UART1_CMSDK_S -#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S - -#define DEFAULT_UART_BAUDRATE 115200U - -/* To be used as CODE and DATA sram */ -#define MPC_ISRAM0_S -#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S - -#define MPC_ISRAM1_S -#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S - -#define MPC_SRAM_S -#define MPC_SRAM_DEV MPC_SRAM_DEV_S - -#define MPC_QSPI_S -#define MPC_QSPI_DEV MPC_QSPI_DEV_S - -/** System Counter Armv8-M */ -#define SYSCOUNTER_CNTRL_ARMV8_M_S -#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S - -#define SYSCOUNTER_READ_ARMV8_M_S -#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S -/** - * Arbitrary scaling values for test purposes - */ -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u - -/* System timer */ -#define SYSTIMER0_ARMV8_M_S -#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S -#define SYSTIMER1_ARMV8_M_S -#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S -#define SYSTIMER2_ARMV8_M_S -#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S -#define SYSTIMER3_ARMV8_M_S -#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S - -#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) - -/* CMSDK GPIO driver structures */ -#define GPIO0_CMSDK_S -#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S -#define GPIO1_CMSDK_S -#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S -#define GPIO2_CMSDK_S -#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S -#define GPIO3_CMSDK_S -#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S - -/* ARM MPS3 IO FPGAIO driver structures */ -#define ARM_MPS3_IO_FPGAIO_S -#define ARM_MPS3_IO_FPGAIO_DEV ARM_MPS3_IO_FPGAIO_DEV_S - -/* System Watchdogs */ -#define SYSWDOG_ARMV8_M_S -#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S - -/* ARM MPC SIE 300 driver structures */ -#define MPC_VM0_S -#define MPC_VM0_DEV MPC_VM0_DEV_S -#define MPC_VM1_S -#define MPC_VM1_DEV MPC_VM1_DEV_S -#define MPC_SSRAM2_S -#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S -#define MPC_SSRAM3_S -#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S - -/* ARM PPC driver structures */ -#define PPC_SSE300_MAIN0_S -#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S -#define PPC_SSE300_MAIN_EXP0_S -#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S -#define PPC_SSE300_MAIN_EXP1_S -#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S -#define PPC_SSE300_MAIN_EXP2_S -#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S -#define PPC_SSE300_MAIN_EXP3_S -#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S -#define PPC_SSE300_PERIPH0_S -#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S -#define PPC_SSE300_PERIPH1_S -#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S -#define PPC_SSE300_PERIPH_EXP0_S -#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S -#define PPC_SSE300_PERIPH_EXP1_S -#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S -#define PPC_SSE300_PERIPH_EXP2_S -#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S -#define PPC_SSE300_PERIPH_EXP3_S -#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S - -/* ARM SPI PL022 */ -/* Invalid device stubs are not defined */ -#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ -#define SPI1_PL022_S -#define SPI1_PL022_DEV SPI1_PL022_DEV_S - - -#endif /* __DEVICE_CFG_H__ */ \ No newline at end of file diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct deleted file mode 100644 index f289ee3..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct +++ /dev/null @@ -1,78 +0,0 @@ -#! armclang --target=arm-arm-none-eabi -mcpu=cortex-m55 -E -xc - -;/* -; * Copyright (c) 2018-2021 Arm Limited. All rights reserved. -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; */ - -#include "region_defs.h" - -LR_CODE S_CODE_START { - ER_CODE S_CODE_START { - *.o (RESET +First) - .ANY (+RO) - } - - /* - * Place the CMSE Veneers (containing the SG instruction) after the code, in - * a separate 32 bytes aligned region so that the SAU can programmed to just - * set this region as Non-Secure Callable. The maximum size of this - * executable region makes it only used the space left over by the ER_CODE - * region so that you can rely on code+veneer size combined will not exceed - * the S_CODE_SIZE value. We also substract from the available space the - * area used to align this section on 32 bytes boundary (for SAU conf). - */ - ER_CODE_CMSE_VENEER +0 ALIGN 32 { - *(Veneer$$CMSE) - } - /* - * This dummy region ensures that the next one will be aligned on a 32 bytes - * boundary, so that the following region will not be mistakenly configured - * as Non-Secure Callable by the SAU. - */ - ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {} - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - CODE_WATERMARK +0 EMPTY 0x0 { - } - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) - - ER_DATA S_DATA_START { - .ANY (+ZI +RW) - } - - #if HEAP_SIZE > 0 - ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap - } - #endif - - ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack - } - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - SRAM_WATERMARK +0 EMPTY 0x0 { - } - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) -} diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/platform_base_address.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/platform_base_address.h deleted file mode 100644 index c5c3ee7..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/platform_base_address.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 2019-2021 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file platform_base_address.h - * \brief This file defines all the peripheral base addresses for MPS3 SSE-300 + - * Ethos-U55 AN547 platform. - */ - -#ifndef __PLATFORM_BASE_ADDRESS_H__ -#define __PLATFORM_BASE_ADDRESS_H__ - -/* ======= Defines peripherals memory map addresses ======= */ -/* Non-secure memory map addresses */ -#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ -#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */ -#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */ -#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */ -#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */ -#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */ -#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ -#define ISRAM1_BASE_NS 0x21200000 /* Internal SRAM Area Non-Secure base address */ -#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ -#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ -#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */ -/* Non-Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */ -#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */ -#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */ -#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */ -#define AHB_USER_0_BASE_NS 0x41104000 /* AHB USER 0 Non-Secure base address */ -#define AHB_USER_1_BASE_NS 0x41105000 /* AHB USER 1 Non-Secure base address */ -#define AHB_USER_2_BASE_NS 0x41106000 /* AHB USER 2 Non-Secure base address */ -#define AHB_USER_3_BASE_NS 0x41107000 /* AHB USER 3 Non-Secure base address */ -#define DMA_0_BASE_NS 0x41200000 /* DMA 0 Non-Secure base address */ -#define DMA_1_BASE_NS 0x41201000 /* DMA 1 Non-Secure base address */ -#define DMA_2_BASE_NS 0x41202000 /* DMA 2 Non-Secure base address */ -#define DMA_3_BASE_NS 0x41203000 /* DMA 3 Non-Secure base address */ -#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */ -#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */ -#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */ -#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */ -#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */ -#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */ -#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */ -#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ -#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ -#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ -/* Non-Secure MSTEXPPIHL Peripheral region */ -#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */ -#define U55_TIMING_ADAPTER_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter registers Non-Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ -#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */ -#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ -#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */ -#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */ -#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ -#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */ -#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */ -#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */ -#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */ -#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */ -#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */ -#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */ -#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */ -#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */ -#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */ -#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */ -#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */ - -/* Secure memory map addresses */ -#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ -#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */ -#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */ -#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */ -#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */ -#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */ -#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ -#define ISRAM1_BASE_S 0x31200000 /* Internal SRAM Area Secure base address */ -#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ -/* Secure Subsystem peripheral region */ -#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ -#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ -#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ -#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */ -#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */ -#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */ -/* Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */ -#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */ -#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */ -#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */ -#define AHB_USER_0_BASE_S 0x51104000 /* AHB USER 0 Secure base address */ -#define AHB_USER_1_BASE_S 0x51105000 /* AHB USER 1 Secure base address */ -#define AHB_USER_2_BASE_S 0x51106000 /* AHB USER 2 Secure base address */ -#define AHB_USER_3_BASE_S 0x51107000 /* AHB USER 3 Secure base address */ -#define DMA_0_BASE_S 0x51200000 /* DMA 0 Secure base address */ -#define DMA_1_BASE_S 0x51201000 /* DMA 1 Secure base address */ -#define DMA_2_BASE_S 0x51202000 /* DMA 2 Secure base address */ -#define DMA_3_BASE_S 0x51203000 /* DMA 3 Secure base address */ -#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */ -#define USB_BASE_S 0x51500000 /* USB Secure base address */ -#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */ -#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */ -#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */ -#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */ -#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */ -#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */ -#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */ -#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */ -#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */ -/* Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */ -#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */ -#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */ -#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */ -#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */ -#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */ -#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */ -#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ -#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */ -#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ -/* Secure MSTEXPPIHL Peripheral region */ -#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */ -#define U55_TIMING_ADAPTER_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter registers Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ -#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */ -#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ -#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */ -#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */ -#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ -#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */ -#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */ -#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */ -#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */ -#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */ -#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */ -#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */ -#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */ -#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */ -#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ -#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ -#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */ - -/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ -#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller - * Access from Non-secure software is only allowed - * if AIRCR.BFHFNMINS is set to 1 */ - -/* Memory size definitions */ -#define ITCM_SIZE (0x00080000) /* 512 kB */ -#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */ -#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ -#define SRAM_SIZE (0x00200000) /* 2 MB */ -#define ISRAM0_SIZE (0x00200000) /* 2 MB */ -#define ISRAM1_SIZE (0x00200000) /* 2 MB */ -#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ -#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ -#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ - -/* Defines for Driver MPC's */ -/* SRAM -- 2 MB */ -#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS) -#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_NS (0x0) -#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S) -#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_S (0x0) - -/* QSPI -- 8 MB*/ -#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS) -#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_NS (0x0) -#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S) -#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_S (0x0) - -/* ISRAM0 -- 2 MB*/ -#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS) -#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S) -#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_S (0x0) - -/* ISRAM1 -- 2 MB*/ -#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS) -#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S) -#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_S (0x0) - -/* DDR4 -- 2GB (8 * 256 MB) */ -#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0) -#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S) -#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S) -#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S) -#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S) -#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS) - -#endif /* __PLATFORM_BASE_ADDRESS_H__ */ diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_defs.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_defs.h deleted file mode 100644 index c8cd919..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_defs.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2016-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_DEFS_H__ -#define __REGION_DEFS_H__ - -#include "region_limits.h" - -/* ************************************************************** - * WARNING: this file is parsed both by the C/C++ compiler - * and the linker. As a result the syntax must be valid not only - * for C/C++ but for the linker scripts too. - * Beware of the following limitations: - * - LD (GCC linker) requires white space around operators. - * - UL postfix for macros is not suported by the linker script - ****************************************************************/ - -/* Secure regions */ -#define S_CODE_START ( S_ROM_ALIAS ) -#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) -#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) - -#define S_DATA_START ( S_RAM_ALIAS ) -#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) -#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) - -/* Non-Secure regions */ -#define NS_CODE_START ( NS_ROM_ALIAS ) -#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) -#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) - -#define NS_DATA_START ( NS_RAM_ALIAS ) -#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) -#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) - -#endif /* __REGION_DEFS_H__ */ diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_limits.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_limits.h deleted file mode 100644 index 58a76c7..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_limits.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2018-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_LIMITS_H__ -#define __REGION_LIMITS_H__ - -/* ************************************************************** - * WARNING: this file is parsed both by the C/C++ compiler - * and the linker. As a result the syntax must be valid not only - * for C/C++ but for the linker scripts too. - * Beware of the following limitations: - * - LD (GCC linker) requires white space around operators. - * - UL postfix for macros is not suported by the linker script - ****************************************************************/ - -/* Secure Code */ -#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ -#define TOTAL_S_ROM_SIZE (0x00080000) /* 256 kB */ - -/* Secure Data */ -#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ -#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ - - -/* Non-Secure Code */ -#define NS_ROM_ALIAS (0x01000000) /* SRAM_BASE_NS */ -#define TOTAL_NS_ROM_SIZE (0x00080000) /* 256 kB */ - -/* Non-Secure Data */ -#define NS_RAM_ALIAS (0x21000000) /* ISRAM0_BASE_NS */ -#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ - - -/* Heap and Stack sizes for secure and nonsecure applications */ -#define HEAP_SIZE (0x0000C000) /* 1 KiB */ -#define STACK_SIZE (0x00008000) /* 1 KiB */ - -#endif /* __REGION_LIMITS_H__ */ diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c deleted file mode 100644 index 53e367c..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "cmsis.h" - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler Function Prototype - *----------------------------------------------------------------------------*/ -typedef void( *pFunc )( void ); - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; - -extern void __PROGRAM_START(void) __NO_RETURN; - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Reset_Handler (void) __NO_RETURN; - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -#define DEFAULT_IRQ_HANDLER(handler_name) \ -void __WEAK handler_name(void); \ -void handler_name(void) { \ - while(1); \ -} - -/* Exceptions */ -DEFAULT_IRQ_HANDLER(NMI_Handler) -DEFAULT_IRQ_HANDLER(HardFault_Handler) -DEFAULT_IRQ_HANDLER(MemManage_Handler) -DEFAULT_IRQ_HANDLER(BusFault_Handler) -DEFAULT_IRQ_HANDLER(UsageFault_Handler) -DEFAULT_IRQ_HANDLER(SecureFault_Handler) -DEFAULT_IRQ_HANDLER(SVC_Handler) -DEFAULT_IRQ_HANDLER(DebugMon_Handler) -DEFAULT_IRQ_HANDLER(PendSV_Handler) -DEFAULT_IRQ_HANDLER(SysTick_Handler) - -DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler) -DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) -DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) -DEFAULT_IRQ_HANDLER(TIMER0_Handler) -DEFAULT_IRQ_HANDLER(TIMER1_Handler) -DEFAULT_IRQ_HANDLER(TIMER2_Handler) -DEFAULT_IRQ_HANDLER(MPC_Handler) -DEFAULT_IRQ_HANDLER(PPC_Handler) -DEFAULT_IRQ_HANDLER(MSC_Handler) -DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) -DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) -DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) -DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) -DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) -DEFAULT_IRQ_HANDLER(TIMER3_Handler) -DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler) -DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler) - -DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) -DEFAULT_IRQ_HANDLER(UARTRX0_Handler) -DEFAULT_IRQ_HANDLER(UARTTX0_Handler) -DEFAULT_IRQ_HANDLER(UARTRX1_Handler) -DEFAULT_IRQ_HANDLER(UARTTX1_Handler) -DEFAULT_IRQ_HANDLER(UARTRX2_Handler) -DEFAULT_IRQ_HANDLER(UARTTX2_Handler) -DEFAULT_IRQ_HANDLER(UARTRX3_Handler) -DEFAULT_IRQ_HANDLER(UARTTX3_Handler) -DEFAULT_IRQ_HANDLER(UARTRX4_Handler) -DEFAULT_IRQ_HANDLER(UARTTX4_Handler) -DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) -DEFAULT_IRQ_HANDLER(UARTOVF_Handler) -DEFAULT_IRQ_HANDLER(ETHERNET_Handler) -DEFAULT_IRQ_HANDLER(I2S_Handler) -DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) -DEFAULT_IRQ_HANDLER(USB_Handler) -DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) -DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) -DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) -DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) -DEFAULT_IRQ_HANDLER(UARTRX5_Handler) -DEFAULT_IRQ_HANDLER(UARTTX5_Handler) -DEFAULT_IRQ_HANDLER(UART5_Handler) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const pFunc __VECTOR_TABLE[496]; - const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14: NMI Handler */ - HardFault_Handler, /* -13: Hard Fault Handler */ - MemManage_Handler, /* -12: MPU Fault Handler */ - BusFault_Handler, /* -11: Bus Fault Handler */ - UsageFault_Handler, /* -10: Usage Fault Handler */ - SecureFault_Handler, /* -9: Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5: SVCall Handler */ - DebugMon_Handler, /* -4: Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2: PendSV Handler */ - SysTick_Handler, /* -1: SysTick Handler */ - - NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */ - NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ - SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ - TIMER0_Handler, /* 3: TIMER 0 Handler */ - TIMER1_Handler, /* 4: TIMER 1 Handler */ - TIMER2_Handler, /* 5: TIMER 2 Handler */ - 0, /* 6: Reserved */ - 0, /* 7: Reserved */ - 0, /* 8: Reserved */ - MPC_Handler, /* 9: MPC Combined (Secure) Handler */ - PPC_Handler, /* 10: PPC Combined (Secure) Handler */ - MSC_Handler, /* 11: MSC Combined (Secure) Handler */ - BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ - 0, /* 13: Reserved */ - MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ - SYS_PPU_Handler, /* 15: SYS PPU Handler */ - CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ - 0, /* 17: Reserved */ - 0, /* 18: Reserved */ - 0, /* 19: Reserved */ - 0, /* 20: Reserved */ - 0, /* 21: Reserved */ - 0, /* 22: Reserved */ - 0, /* 23: Reserved */ - 0, /* 24: Reserved */ - 0, /* 25: Reserved */ - DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ - TIMER3_Handler, /* 27: TIMER 3 Handler */ - CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */ - CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */ - 0, /* 30: Reserved */ - 0, /* 31: Reserved */ - - /* External interrupts */ - System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ - UARTRX0_Handler, /* 33: UART 0 RX Handler */ - UARTTX0_Handler, /* 34: UART 0 TX Handler */ - UARTRX1_Handler, /* 35: UART 1 RX Handler */ - UARTTX1_Handler, /* 36: UART 1 TX Handler */ - UARTRX2_Handler, /* 37: UART 2 RX Handler */ - UARTTX2_Handler, /* 38: UART 2 TX Handler */ - UARTRX3_Handler, /* 39: UART 3 RX Handler */ - UARTTX3_Handler, /* 40: UART 3 TX Handler */ - UARTRX4_Handler, /* 41: UART 4 RX Handler */ - UARTTX4_Handler, /* 42: UART 4 TX Handler */ - UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ - UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ - UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ - UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ - UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ - UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ - ETHERNET_Handler, /* 49: Ethernet Handler */ - I2S_Handler, /* 50: Audio I2S Handler */ - TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ - USB_Handler, /* 52: USB Handler */ - SPI_ADC_Handler, /* 53: SPI ADC Handler */ - SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ - SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ - ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ - 0, /* 57: Reserved */ - 0, /* 58: Reserved */ - 0, /* 59: Reserved */ - 0, /* 60: Reserved */ - 0, /* 61: Reserved */ - 0, /* 62: Reserved */ - 0, /* 63: Reserved */ - 0, /* 64: Reserved */ - 0, /* 65: Reserved */ - 0, /* 66: Reserved */ - 0, /* 67: Reserved */ - 0, /* 68: Reserved */ - GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ - GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ - GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ - GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ - GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ - GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ - GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ - GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ - GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ - GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ - GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ - GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ - GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ - GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ - GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ - GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ - GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ - GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ - GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ - GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ - GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ - GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ - GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ - GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ - GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ - GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ - GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ - GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ - GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ - GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ - GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ - GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ - GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ - GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ - GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ - GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ - GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ - GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ - GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ - GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ - GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ - GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ - GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ - GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ - GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ - GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ - GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ - GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ - GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ - GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ - GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ - GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ - GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ - GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ - GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ - GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ - UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ - UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ - UART5_Handler, /* 127: UART 5 combined Interrupt */ - 0, /* 128: Reserved */ - 0, /* 129: Reserved */ - 0, /* 130: Reserved */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/debug_log.cc b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/debug_log.cc deleted file mode 100644 index bc79d43..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/debug_log.cc +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -// Implementation for the DebugLog() function that prints to the debug logger on -// an generic Cortex-M device. - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -#include "tensorflow/lite/micro/debug_log.h" - -#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" - -static DebugLogCallback debug_log_callback = nullptr; - -void RegisterDebugLogCallback(void (*cb)(const char* s)) { - debug_log_callback = cb; -} - -void DebugLog(const char* s) { -#ifndef TF_LITE_STRIP_ERROR_STRINGS - if (debug_log_callback != nullptr) { - debug_log_callback(s); - } -#endif -} - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/micro_time.cc b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/micro_time.cc deleted file mode 100644 index 023ac6d..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/micro_time.cc +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -#include "tensorflow/lite/micro/micro_time.h" - -// DWT (Data Watchpoint and Trace) registers, only exists on ARM Cortex with a -// DWT unit. -#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) -/*!< DWT Control register */ - -// DWT Control register. -#define KIN1_DWT_CYCCNTENA_BIT (1UL << 0) - -// CYCCNTENA bit in DWT_CONTROL register. -#define KIN1_DWT_CYCCNT (*((volatile uint32_t*)0xE0001004)) - -// DWT Cycle Counter register. -#define KIN1_DEMCR (*((volatile uint32_t*)0xE000EDFC)) - -// DEMCR: Debug Exception and Monitor Control Register. -#define KIN1_TRCENA_BIT (1UL << 24) - -#define KIN1_LAR (*((volatile uint32_t*)0xE0001FB0)) - -#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) - -// Unlock access to DWT (ITM, etc.)registers. -#define KIN1_UnlockAccessToDWT() KIN1_LAR = 0xC5ACCE55; - -// TRCENA: Enable trace and debug block DEMCR (Debug Exception and Monitor -// Control Register. -#define KIN1_InitCycleCounter() KIN1_DEMCR |= KIN1_TRCENA_BIT - -#define KIN1_ResetCycleCounter() KIN1_DWT_CYCCNT = 0 -#define KIN1_EnableCycleCounter() KIN1_DWT_CONTROL |= KIN1_DWT_CYCCNTENA_BIT -#define KIN1_DisableCycleCounter() KIN1_DWT_CONTROL &= ~KIN1_DWT_CYCCNTENA_BIT -#define KIN1_GetCycleCounter() KIN1_DWT_CYCCNT - -namespace tflite { - -int32_t ticks_per_second() { return 0; } - -int32_t GetCurrentTimeTicks() { - static bool is_initialized = false; - if (!is_initialized) { - KIN1_UnlockAccessToDWT(); - KIN1_InitCycleCounter(); - KIN1_ResetCycleCounter(); - KIN1_EnableCycleCounter(); - is_initialized = true; - } - return KIN1_GetCycleCounter(); -} - -} // namespace tflite diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/system_setup.cc b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/system_setup.cc deleted file mode 100644 index e803dc2..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/system_setup.cc +++ /dev/null @@ -1,36 +0,0 @@ -/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -#include "tensorflow/lite/micro/system_setup.h" -#include "stdio.h" -#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" - -extern "C" void serial_init (void); - -namespace tflite { - -void debug_log_printf(const char* s) { - printf(s); -} - -// To add an equivalent function for your own platform, create your own -// implementation file, and place it in a subfolder named after the target. See -// tensorflow/lite/micro/debug_log.cc for a similar example. -void InitializeTarget() { - serial_init(); - RegisterDebugLogCallback(debug_log_printf); - //debug_log_printf("Initialized UART and registered Callback.") -} -} // namespace tflite diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/Pre_Include_Global.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/Pre_Include_Global.h deleted file mode 100644 index 6234fa2..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/Pre_Include_Global.h +++ /dev/null @@ -1,18 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'template_Corstone300' - * Target: 'template_Corstone300' - */ - -#ifndef PRE_INCLUDE_GLOBAL_H -#define PRE_INCLUDE_GLOBAL_H - -/* tensorflow::Machine Learning:TensorFlow:Kernel:CMSIS-NN:0.1.20210416 */ -// enabling global pre includes - #define TF_LITE_STATIC_MEMORY 1 - - -#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/RTE_Components.h b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/RTE_Components.h deleted file mode 100644 index 452f25e..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/RTE_Components.h +++ /dev/null @@ -1,35 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'template_Corstone300' - * Target: 'template_Corstone300' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "SSE300MPS3.h" - -/* ARM::CMSIS Driver:USART:1.0.0 */ -#define RTE_Drivers_USART -/* tensorflow::Data Exchange:Serialization:flatbuffers:tensorflow:1.12.0 */ -#define RTE_DataExchange_Serialization_flatbuffers /* flatbuffers */ -/* tensorflow::Data Processing:Math:gemmlowp fixed-point:tensorflow:1.0.0 */ -#define RTE_DataExchange_Math_gemmlowp /* gemmlowp */ -/* tensorflow::Data Processing:Math:kissfft:tensorflow:1.4.5 */ -#define RTE_DataExchange_Math_kissfft /* kissfft */ -/* tensorflow::Data Processing:Math:ruy:tensorflow:1.12.0 */ -#define RTE_DataProcessing_Math_ruy /* ruy */ -/* tensorflow::Machine Learning:TensorFlow:Kernel:CMSIS-NN:0.1.20210416 */ -#define RTE_ML_TF_LITE /* TF */ -/* tensorflow::Machine Learning:TensorFlow:Testing:0.1.20210416 */ -#define RTE_ML_TF_LITE /* TF */ - - -#endif /* RTE_COMPONENTS_H */ diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/SSE-300-MPS3.cprj b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/SSE-300-MPS3.cprj deleted file mode 100644 index a1a6a8d..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/SSE-300-MPS3.cprj +++ /dev/null @@ -1,85 +0,0 @@ - - - - - UnitTestTemplate - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _file_block_xml_ - - - - - diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/packlist b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/packlist deleted file mode 100644 index c9c5636..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/packlist +++ /dev/null @@ -1 +0,0 @@ -https://keilpack.azureedge.net/pack/ARM.V2M_MPS3_SSE_300_BSP.1.1.0.pack diff --git a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/platform_setup.c b/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/platform_setup.c deleted file mode 100644 index 279de43..0000000 --- a/tensorflow-test/templates/Ethos-U/ARMCLANG/SSE-300-MPS3/platform_setup.c +++ /dev/null @@ -1,10 +0,0 @@ - - -int platform_setup (void) -{ - serial_init(); - - -} - - diff --git a/tensorflow-test/templates/FVP_Corstone_SSE-300_Ethos-U55.config b/tensorflow-test/templates/FVP_Corstone_SSE-300_Ethos-U55.config deleted file mode 100644 index d9b93ee..0000000 --- a/tensorflow-test/templates/FVP_Corstone_SSE-300_Ethos-U55.config +++ /dev/null @@ -1,1656 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -NSC_CFG_0=0 # (bool , init-time) default = '0' : Whether 0x10000000..0x1FFFFFFF is non-secure-callable -NSC_CFG_1=0 # (bool , init-time) default = '0' : Whether 0x30000000..0x3FFFFFFF is non-secure-callable -REMOTE_CONNECTION.CADIServer.enable_remote_cadi=0 # (bool , init-time) default = '0' : Allow connections from remote hosts -REMOTE_CONNECTION.CADIServer.listen_address=127.0.0.1 # (string, init-time) default = '127.0.0.1' : Network address the server should listen on if enable_remote_cadi is set ("127.0.0.1" by default) -REMOTE_CONNECTION.CADIServer.port=31627 # (int , init-time) default = '0x7b8b' : TCP port the server should listen on if enable_remote_cadi is set (31627 by default) -REMOTE_CONNECTION.CADIServer.range=0 # (int , init-time) default = '0x0' : If requested port is not avaliable, search for next avaliable port in range: [port:port+range] (0 by default, only try specified port) -core_clk.mul=25000000 # (int , init-time) default = '0x17d7840' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -cpu0.BEATS_PER_TICK=2 # (int , init-time) default = '0x2' : Number of beats from each in-flight vector instruction executed in 1 tick (1,2 or 4). -cpu0.BF_is_nop=0 # (bool , init-time) default = '0' : BF instruction executes as NOP, even if we have LO_BRANCH_INFO. -cpu0.CDEMAPPEDONCP=1 # (bool , init-time) default = '1' : Specifies whether the instruction for a given Coprocessor is redirected to the CDE module -cpu0.CFGBIGEND=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode -cpu0.CFGDTCMSZ=13 # (int , init-time) default = '0xd' : Size of the data TCM. 0=No DTCM implemented. Otherwise=Size of DTCM=pow(2, CFGDTCMSZ - 1) KB. Minimum size is 4KB -cpu0.CFGITCMSZ=11 # (int , init-time) default = '0xb' : Size of the instruction TCM. 0=No ITCM implemented. Otherwise=Size of ITCM=pow(2, CFGITCMSZ - 1) KB. Minimum size is 4KB -cpu0.CFGNOCDECP=0 # (int , init-time) default = '0x0' : Bit N means external coprocessor N (CP7:CP0) disable for CDE coprocessor -cpu0.CFGPAHBSZ=0 # (int , init-time) default = '0x0' : Size of the P-AHB peripheral port memory region. 0=P-AHB disabled, 1=64MB, 2=128MB, 3=256MB, 4=512MB -cpu0.CPIF=1 # (bool , init-time) default = '1' : Specifies whether the external coprocessor interface is included -cpu0.CPNSPRESENT=255 # (int , init-time) default = '0xff' : Bit N means external coprocessor N (CP7:CP0) is accessible in Non-Secure state -cpu0.CPSPRESENT=255 # (int , init-time) default = '0xff' : Bit N means external coprocessor N (CP7:CP0) is accessible in Secure state -cpu0.DBGLVL=2 # (int , init-time) default = '0x2' : 0: Minimal debug; 1: 2 Watchpoints, 4 Breakpoint comparators; 2: 4 Watchpoints, 8 Breakpoint comparators; 3: 8 Watchpoints, 8 Breakpoint comparators -cpu0.DCACHESZ=15 # (int , init-time) default = '0xf' : Whether the D-cache is included and, if included, the size of it. Bit 0: 0=No D-cache included, 1=D-cache included. Bits [4:1]: 0x0=4KB D-cache, 0x1=8KB D-cache, 0x3=16KB D-cache, 0x7=32KB D-cache, 0x15=64KB D-cache -cpu0.ECOREVNUM=0 # (int , init-time) default = '0x0' : ECO Revision number -cpu0.ERRDEVID.NUM=56 # (int , init-time) default = '0x38' : RAS: Number of implemented error record indexes, 0 to 56. -cpu0.ETM=1 # (bool , init-time) default = '1' : Support for ETM trace. false : No ETM trace included, true: ETM trace included -cpu0.ICACHESZ=15 # (int , init-time) default = '0xf' : Whether the I-cache is included and, if included, the size of it. Bit 0: 0=No I-cache included, 1=I-cache included. Bits [4:1]: 0x0=4KB I-cache, 0x1=8KB I-cache, 0x3=16KB I-cache, 0x7=32KB I-cache, 0x15=64KB I-cache -cpu0.ID_ISAR0.CmpBranch=3 # (int , init-time) default = '0x3' : Support for Compare and Branch instructions. 1 = Supports CBNZ and CBZ instructions; 3 = Supports non-predicated low overhead looping (WLS, DLS, LE, and LC) and branch future (BF, BFX, BFL, BFLX, and BFCSEL) instructions. -cpu0.INITNSVTOR=0 # (int , init-time) default = '0x0' : Non-Secure vector-table offset at reset -cpu0.INITPAHBEN=0 # (bool , init-time) default = '0' : The P-AHB enable state at reset -cpu0.INITSVTOR=268435456 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset -cpu0.IRQDIS0=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+0] -cpu0.IRQDIS1=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+32] -cpu0.IRQDIS10=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+320] -cpu0.IRQDIS11=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+352] -cpu0.IRQDIS12=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+384] -cpu0.IRQDIS13=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+416] -cpu0.IRQDIS14=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+448] -cpu0.IRQDIS2=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+64] -cpu0.IRQDIS3=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+96] -cpu0.IRQDIS4=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+128] -cpu0.IRQDIS5=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+160] -cpu0.IRQDIS6=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+192] -cpu0.IRQDIS7=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+224] -cpu0.IRQDIS8=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+256] -cpu0.IRQDIS9=0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+288] -cpu0.IRQLVL=3 # (int , init-time) default = '0x3' : Number of bits of interrupt priority -cpu0.ITM=1 # (bool , init-time) default = '1' : Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included -cpu0.LOCKDTGU=0 # (bool , init-time) default = '0' : Lock down of Data TGU registers write -cpu0.LOCKITGU=0 # (bool , init-time) default = '0' : Lock down of Instruction TGU registers write -cpu0.LOCKTCM=0 # (bool , init-time) default = '0' : Lock down of TCM registers write -cpu0.LOCK_NS_MPU=0 # (bool , init-time) default = '0' : Lock down of Non-Secure MPU registers write -cpu0.LOCK_SAU=0 # (bool , init-time) default = '0' : Lock down of SAU registers write -cpu0.LOCK_S_MPU=0 # (bool , init-time) default = '0' : Lock down of Secure MPU registers write -cpu0.MPU_NS=8 # (int , init-time) default = '0x8' : Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions -cpu0.MPU_S=8 # (int , init-time) default = '0x8' : Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored -cpu0.SAU=8 # (int , init-time) default = '0x8' : Number of SAU regions (0 => no SAU) -cpu0.SECEXT=1 # (bool , init-time) default = '1' : Whether the ARMv8-M Security Extensions are included -cpu0.WICLINES=35 # (int , init-time) default = '0x23' : Number of lines supported by the WIC interface -cpu0.aircr_iesb_is_writable=1 # (bool , init-time) default = '1' : IS the AIRCR.IESB bit [5] writable? -cpu0.aircr_iesb_reset=0 # (bool , init-time) default = '0' : Set the AIRCR.IESB bit [5] after reset -cpu0.cde_impl_name= # (string, init-time) default = '' : Name of the CDE implementation for this core (implementation contributed by MTI plugin). -cpu0.cpi_div=1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) -cpu0.cpi_mul=1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) -cpu0.dcache-state_modelled=0 # (bool , run-time ) default = '0' : Set whether D-cache has stateful implementation -cpu0.dcache-ways=4 # (int , init-time) default = '0x4' : L1 D-cache ways (sets are implicit from size) -cpu0.delay_faultmask_update=0 # (bool , init-time) default = '0' : Delay FAULTMASK update to context sync -cpu0.delay_sysreg_update=0 # (bool , init-time) default = '0' : Delay some system register updates (e.g. SHCSR) to context sync -cpu0.duplicate_CADI_TCM_writes=0 # (bool , init-time) default = '0' : CADI writes to TCMs are also sent to downstream memory at same addresses (for validation platforms) -cpu0.ecc_on=0 # (bool , init-time) default = '0' : Enable Error Correcting Code -cpu0.execute_via_archex=1 # (bool , init-time) default = '1' : Use ArchEx-generated code from V8_1_PACBTI_BETA_1_0_INTERNAL for execution -cpu0.has_cde=0 # (bool , init-time) default = '0' : Enables Custom Datapath Extensions -cpu0.has_pmu=0 # (bool , init-time) default = '0' : Availability of optional PMU. -cpu0.has_unpriviledged_debug=1 # (bool , init-time) default = '1' : Unpriviledged Debug Extension supported for Mainline Extension -cpu0.icache-state_modelled=0 # (bool , run-time ) default = '0' : Set whether I-cache has stateful implementation -cpu0.icache-ways=2 # (int , init-time) default = '0x2' : L1 I-cache ways (sets are implicit from size) -cpu0.min_sync_level=0 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) -cpu0.mve_unpred_config_json='[["CLEAR_IT","VPNOT_T1","InITBlock"],["OK","VMINNMV_f_T2","Rda==11x1"],["OK","VDDUP","curOffset MOD imm32 != 0"],["OK","VDDUP","bufSize MOD imm32 != 0"],["OK","VDDUP","curOffset >= bufSize "]]' # (string, init-time) default = ''[["CLEAR_IT","VPNOT_T1","InITBlock"],["OK","VMINNMV_f_T2","Rda==11x1"],["OK","VDDUP","curOffset MOD imm32 != 0"],["OK","VDDUP","bufSize MOD imm32 != 0"],["OK","VDDUP","curOffset >= bufSize "]]'' : A JSON array of arrays of the form [unpred_result, instr, cond] forunpredictable configruation for MVE. Either instr or cond may be omitted. The first match wins. Use 'list' to show the available options -cpu0.num_pmu_counters=31 # (int , init-time) default = '0x1f' : Number of available PMU counters. -cpu0.ras_ERRFR0='{"ED":0x1,"UE":0x1}' # (string, init-time) default = ''{"ED":0x1,"UE":0x1}'' : A JSON object or array of objects for each field of ERRFR. Records not described default to RAZ e.g. '{"ED":0x1,"UE":0x1}'. -cpu0.ras_cei_pin=2 # (int , init-time) default = '0x2' : RAS: Critical error interrupt pin. -cpu0.ras_cei_support=1 # (bool , init-time) default = '1' : RAS: Whether Critical Error Interrupt is supported -cpu0.ras_eri_pin=1 # (int , init-time) default = '0x1' : RAS: Error recovery interrupt pin. -cpu0.ras_eri_support=1 # (bool , init-time) default = '1' : RAS: Whether Error Recovery Interrupt is supported -cpu0.ras_error_record=72057594037927935 # (int , init-time) default = '0xffffffffffffff' : 56 bit value that specifies which nodes out of 0-55 are implemented (ERRDEVID is derived from this parameter) -cpu0.ras_fhi_pin=0 # (int , init-time) default = '0x0' : RAS: Fault handling interrupt pin. -cpu0.ras_fhi_support=1 # (bool , init-time) default = '1' : RAS: Whether Fault Handling Interrupt is supported -cpu0.scheduler_mode=0 # (int , init-time) default = '0x0' : Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare) -cpu0.semihosting-Thumb_SVC=171 # (int , init-time) default = '0xab' : T32 SVC number for semihosting -cpu0.semihosting-cmd_line= # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu0.semihosting-cwd= # (string, init-time) default = '' : Base directory for semihosting file access. -cpu0.semihosting-enable=1 # (bool , init-time) default = '0' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu0.semihosting-heap_base=0 # (int , init-time) default = '0x0' : Virtual address of heap base -cpu0.semihosting-heap_limit=275775488 # (int , init-time) default = '0x10700000' : Virtual address of top of heap -cpu0.semihosting-prefix=0 # (bool , init-time) default = '0' : Prefix semihosting output with target instance name -cpu0.semihosting-stack_base=275775488 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack -cpu0.semihosting-stack_limit=276824064 # (int , init-time) default = '0x10800000' : Virtual address of stack limit -cpu0.tcm_fill_pattern_1=3755990991 # (int , init-time) default = '0xdfdfdfcf' : TCM Fill pattern 1 -cpu0.tcm_fill_pattern_2=3487555551 # (int , init-time) default = '0xcfdfdfdf' : TCM Fill pattern 2 -cpu0.trace_style=0 # (int , init-time) default = '0x0' : MVE instruction trace style: 0=Tarmac-like from instDB.json, 1=execute function+params (for debug), 2 = Rosetta. Add 16 for [**--] beat trace. Add 32 for tracing IMPLIED LOB instructions. Add 64 to change opcode of implied BF to 0xBF00 -cpu0.unpred_config_json_file= # (string, init-time) default = '' : Path to the unpredictable configuration file in JSON format -cpu0.vfp-enable_at_reset=0 # (bool , init-time) default = '0' : Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: Arm recommends going through the implementation's suggested VFP power-up sequence! -ethosu.cli= # (string, init-time) default = '' : -ethosu.config=H256 # (string, init-time) default = 'H256' : -ethosu.libpath=libethosu.so # (string, init-time) default = 'libethosu.so' : -idau.IDAU_REGION0.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region0 as exempt -idau.IDAU_REGION1.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region1 as exempt -idau.IDAU_REGION10.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region10 as exempt -idau.IDAU_REGION100.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region100 -idau.IDAU_REGION100.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region100 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION100.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region100 as exempt -idau.IDAU_REGION100.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region100 -idau.IDAU_REGION100.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region100 -idau.IDAU_REGION101.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region101 -idau.IDAU_REGION101.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region101 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION101.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region101 as exempt -idau.IDAU_REGION101.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region101 -idau.IDAU_REGION101.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region101 -idau.IDAU_REGION102.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region102 -idau.IDAU_REGION102.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region102 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION102.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region102 as exempt -idau.IDAU_REGION102.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region102 -idau.IDAU_REGION102.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region102 -idau.IDAU_REGION103.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region103 -idau.IDAU_REGION103.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region103 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION103.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region103 as exempt -idau.IDAU_REGION103.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region103 -idau.IDAU_REGION103.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region103 -idau.IDAU_REGION104.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region104 -idau.IDAU_REGION104.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region104 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION104.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region104 as exempt -idau.IDAU_REGION104.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region104 -idau.IDAU_REGION104.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region104 -idau.IDAU_REGION105.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region105 -idau.IDAU_REGION105.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region105 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION105.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region105 as exempt -idau.IDAU_REGION105.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region105 -idau.IDAU_REGION105.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region105 -idau.IDAU_REGION106.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region106 -idau.IDAU_REGION106.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region106 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION106.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region106 as exempt -idau.IDAU_REGION106.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region106 -idau.IDAU_REGION106.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region106 -idau.IDAU_REGION107.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region107 -idau.IDAU_REGION107.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region107 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION107.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region107 as exempt -idau.IDAU_REGION107.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region107 -idau.IDAU_REGION107.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region107 -idau.IDAU_REGION108.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region108 -idau.IDAU_REGION108.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region108 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION108.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region108 as exempt -idau.IDAU_REGION108.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region108 -idau.IDAU_REGION108.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region108 -idau.IDAU_REGION109.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region109 -idau.IDAU_REGION109.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region109 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION109.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region109 as exempt -idau.IDAU_REGION109.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region109 -idau.IDAU_REGION109.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region109 -idau.IDAU_REGION11.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region11 as exempt -idau.IDAU_REGION110.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region110 -idau.IDAU_REGION110.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region110 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION110.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region110 as exempt -idau.IDAU_REGION110.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region110 -idau.IDAU_REGION110.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region110 -idau.IDAU_REGION111.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region111 -idau.IDAU_REGION111.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region111 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION111.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region111 as exempt -idau.IDAU_REGION111.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region111 -idau.IDAU_REGION111.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region111 -idau.IDAU_REGION112.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region112 -idau.IDAU_REGION112.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region112 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION112.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region112 as exempt -idau.IDAU_REGION112.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region112 -idau.IDAU_REGION112.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region112 -idau.IDAU_REGION113.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region113 -idau.IDAU_REGION113.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region113 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION113.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region113 as exempt -idau.IDAU_REGION113.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region113 -idau.IDAU_REGION113.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region113 -idau.IDAU_REGION114.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region114 -idau.IDAU_REGION114.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region114 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION114.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region114 as exempt -idau.IDAU_REGION114.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region114 -idau.IDAU_REGION114.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region114 -idau.IDAU_REGION115.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region115 -idau.IDAU_REGION115.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region115 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION115.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region115 as exempt -idau.IDAU_REGION115.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region115 -idau.IDAU_REGION115.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region115 -idau.IDAU_REGION116.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region116 -idau.IDAU_REGION116.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region116 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION116.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region116 as exempt -idau.IDAU_REGION116.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region116 -idau.IDAU_REGION116.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region116 -idau.IDAU_REGION117.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region117 -idau.IDAU_REGION117.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region117 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION117.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region117 as exempt -idau.IDAU_REGION117.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region117 -idau.IDAU_REGION117.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region117 -idau.IDAU_REGION118.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region118 -idau.IDAU_REGION118.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region118 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION118.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region118 as exempt -idau.IDAU_REGION118.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region118 -idau.IDAU_REGION118.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region118 -idau.IDAU_REGION119.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region119 -idau.IDAU_REGION119.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region119 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION119.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region119 as exempt -idau.IDAU_REGION119.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region119 -idau.IDAU_REGION119.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region119 -idau.IDAU_REGION12.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region12 as exempt -idau.IDAU_REGION120.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region120 -idau.IDAU_REGION120.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region120 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION120.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region120 as exempt -idau.IDAU_REGION120.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region120 -idau.IDAU_REGION120.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region120 -idau.IDAU_REGION121.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region121 -idau.IDAU_REGION121.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region121 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION121.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region121 as exempt -idau.IDAU_REGION121.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region121 -idau.IDAU_REGION121.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region121 -idau.IDAU_REGION122.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region122 -idau.IDAU_REGION122.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region122 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION122.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region122 as exempt -idau.IDAU_REGION122.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region122 -idau.IDAU_REGION122.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region122 -idau.IDAU_REGION123.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region123 -idau.IDAU_REGION123.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region123 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION123.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region123 as exempt -idau.IDAU_REGION123.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region123 -idau.IDAU_REGION123.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region123 -idau.IDAU_REGION124.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region124 -idau.IDAU_REGION124.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region124 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION124.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region124 as exempt -idau.IDAU_REGION124.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region124 -idau.IDAU_REGION124.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region124 -idau.IDAU_REGION125.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region125 -idau.IDAU_REGION125.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region125 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION125.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region125 as exempt -idau.IDAU_REGION125.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region125 -idau.IDAU_REGION125.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region125 -idau.IDAU_REGION126.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region126 -idau.IDAU_REGION126.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region126 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION126.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region126 as exempt -idau.IDAU_REGION126.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region126 -idau.IDAU_REGION126.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region126 -idau.IDAU_REGION127.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region127 -idau.IDAU_REGION127.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region127 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION127.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region127 as exempt -idau.IDAU_REGION127.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region127 -idau.IDAU_REGION127.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region127 -idau.IDAU_REGION128.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region128 -idau.IDAU_REGION128.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region128 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION128.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region128 as exempt -idau.IDAU_REGION128.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region128 -idau.IDAU_REGION128.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region128 -idau.IDAU_REGION129.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region129 -idau.IDAU_REGION129.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region129 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION129.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region129 as exempt -idau.IDAU_REGION129.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region129 -idau.IDAU_REGION129.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region129 -idau.IDAU_REGION13.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region13 as exempt -idau.IDAU_REGION130.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region130 -idau.IDAU_REGION130.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region130 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION130.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region130 as exempt -idau.IDAU_REGION130.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region130 -idau.IDAU_REGION130.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region130 -idau.IDAU_REGION131.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region131 -idau.IDAU_REGION131.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region131 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION131.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region131 as exempt -idau.IDAU_REGION131.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region131 -idau.IDAU_REGION131.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region131 -idau.IDAU_REGION132.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region132 -idau.IDAU_REGION132.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region132 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION132.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region132 as exempt -idau.IDAU_REGION132.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region132 -idau.IDAU_REGION132.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region132 -idau.IDAU_REGION133.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region133 -idau.IDAU_REGION133.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region133 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION133.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region133 as exempt -idau.IDAU_REGION133.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region133 -idau.IDAU_REGION133.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region133 -idau.IDAU_REGION134.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region134 -idau.IDAU_REGION134.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region134 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION134.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region134 as exempt -idau.IDAU_REGION134.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region134 -idau.IDAU_REGION134.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region134 -idau.IDAU_REGION135.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region135 -idau.IDAU_REGION135.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region135 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION135.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region135 as exempt -idau.IDAU_REGION135.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region135 -idau.IDAU_REGION135.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region135 -idau.IDAU_REGION136.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region136 -idau.IDAU_REGION136.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region136 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION136.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region136 as exempt -idau.IDAU_REGION136.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region136 -idau.IDAU_REGION136.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region136 -idau.IDAU_REGION137.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region137 -idau.IDAU_REGION137.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region137 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION137.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region137 as exempt -idau.IDAU_REGION137.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region137 -idau.IDAU_REGION137.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region137 -idau.IDAU_REGION138.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region138 -idau.IDAU_REGION138.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region138 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION138.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region138 as exempt -idau.IDAU_REGION138.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region138 -idau.IDAU_REGION138.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region138 -idau.IDAU_REGION139.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region139 -idau.IDAU_REGION139.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region139 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION139.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region139 as exempt -idau.IDAU_REGION139.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region139 -idau.IDAU_REGION139.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region139 -idau.IDAU_REGION140.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region140 -idau.IDAU_REGION140.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region140 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION140.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region140 as exempt -idau.IDAU_REGION140.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region140 -idau.IDAU_REGION140.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region140 -idau.IDAU_REGION141.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region141 -idau.IDAU_REGION141.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region141 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION141.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region141 as exempt -idau.IDAU_REGION141.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region141 -idau.IDAU_REGION141.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region141 -idau.IDAU_REGION142.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region142 -idau.IDAU_REGION142.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region142 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION142.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region142 as exempt -idau.IDAU_REGION142.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region142 -idau.IDAU_REGION142.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region142 -idau.IDAU_REGION143.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region143 -idau.IDAU_REGION143.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region143 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION143.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region143 as exempt -idau.IDAU_REGION143.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region143 -idau.IDAU_REGION143.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region143 -idau.IDAU_REGION144.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region144 -idau.IDAU_REGION144.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region144 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION144.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region144 as exempt -idau.IDAU_REGION144.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region144 -idau.IDAU_REGION144.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region144 -idau.IDAU_REGION145.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region145 -idau.IDAU_REGION145.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region145 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION145.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region145 as exempt -idau.IDAU_REGION145.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region145 -idau.IDAU_REGION145.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region145 -idau.IDAU_REGION146.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region146 -idau.IDAU_REGION146.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region146 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION146.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region146 as exempt -idau.IDAU_REGION146.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region146 -idau.IDAU_REGION146.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region146 -idau.IDAU_REGION147.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region147 -idau.IDAU_REGION147.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region147 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION147.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region147 as exempt -idau.IDAU_REGION147.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region147 -idau.IDAU_REGION147.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region147 -idau.IDAU_REGION148.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region148 -idau.IDAU_REGION148.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region148 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION148.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region148 as exempt -idau.IDAU_REGION148.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region148 -idau.IDAU_REGION148.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region148 -idau.IDAU_REGION149.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region149 -idau.IDAU_REGION149.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region149 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION149.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region149 as exempt -idau.IDAU_REGION149.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region149 -idau.IDAU_REGION149.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region149 -idau.IDAU_REGION15.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region15 as exempt -idau.IDAU_REGION150.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region150 -idau.IDAU_REGION150.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region150 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION150.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region150 as exempt -idau.IDAU_REGION150.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region150 -idau.IDAU_REGION150.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region150 -idau.IDAU_REGION151.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region151 -idau.IDAU_REGION151.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region151 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION151.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region151 as exempt -idau.IDAU_REGION151.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region151 -idau.IDAU_REGION151.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region151 -idau.IDAU_REGION152.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region152 -idau.IDAU_REGION152.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region152 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION152.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region152 as exempt -idau.IDAU_REGION152.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region152 -idau.IDAU_REGION152.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region152 -idau.IDAU_REGION153.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region153 -idau.IDAU_REGION153.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region153 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION153.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region153 as exempt -idau.IDAU_REGION153.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region153 -idau.IDAU_REGION153.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region153 -idau.IDAU_REGION154.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region154 -idau.IDAU_REGION154.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region154 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION154.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region154 as exempt -idau.IDAU_REGION154.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region154 -idau.IDAU_REGION154.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region154 -idau.IDAU_REGION155.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region155 -idau.IDAU_REGION155.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region155 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION155.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region155 as exempt -idau.IDAU_REGION155.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region155 -idau.IDAU_REGION155.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region155 -idau.IDAU_REGION156.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region156 -idau.IDAU_REGION156.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region156 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION156.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region156 as exempt -idau.IDAU_REGION156.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region156 -idau.IDAU_REGION156.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region156 -idau.IDAU_REGION157.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region157 -idau.IDAU_REGION157.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region157 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION157.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region157 as exempt -idau.IDAU_REGION157.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region157 -idau.IDAU_REGION157.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region157 -idau.IDAU_REGION158.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region158 -idau.IDAU_REGION158.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region158 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION158.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region158 as exempt -idau.IDAU_REGION158.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region158 -idau.IDAU_REGION158.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region158 -idau.IDAU_REGION159.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region159 -idau.IDAU_REGION159.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region159 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION159.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region159 as exempt -idau.IDAU_REGION159.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region159 -idau.IDAU_REGION159.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region159 -idau.IDAU_REGION160.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region160 -idau.IDAU_REGION160.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region160 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION160.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region160 as exempt -idau.IDAU_REGION160.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region160 -idau.IDAU_REGION160.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region160 -idau.IDAU_REGION161.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region161 -idau.IDAU_REGION161.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region161 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION161.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region161 as exempt -idau.IDAU_REGION161.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region161 -idau.IDAU_REGION161.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region161 -idau.IDAU_REGION162.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region162 -idau.IDAU_REGION162.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region162 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION162.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region162 as exempt -idau.IDAU_REGION162.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region162 -idau.IDAU_REGION162.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region162 -idau.IDAU_REGION163.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region163 -idau.IDAU_REGION163.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region163 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION163.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region163 as exempt -idau.IDAU_REGION163.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region163 -idau.IDAU_REGION163.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region163 -idau.IDAU_REGION164.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region164 -idau.IDAU_REGION164.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region164 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION164.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region164 as exempt -idau.IDAU_REGION164.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region164 -idau.IDAU_REGION164.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region164 -idau.IDAU_REGION165.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region165 -idau.IDAU_REGION165.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region165 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION165.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region165 as exempt -idau.IDAU_REGION165.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region165 -idau.IDAU_REGION165.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region165 -idau.IDAU_REGION166.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region166 -idau.IDAU_REGION166.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region166 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION166.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region166 as exempt -idau.IDAU_REGION166.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region166 -idau.IDAU_REGION166.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region166 -idau.IDAU_REGION167.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region167 -idau.IDAU_REGION167.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region167 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION167.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region167 as exempt -idau.IDAU_REGION167.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region167 -idau.IDAU_REGION167.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region167 -idau.IDAU_REGION168.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region168 -idau.IDAU_REGION168.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region168 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION168.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region168 as exempt -idau.IDAU_REGION168.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region168 -idau.IDAU_REGION168.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region168 -idau.IDAU_REGION169.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region169 -idau.IDAU_REGION169.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region169 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION169.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region169 as exempt -idau.IDAU_REGION169.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region169 -idau.IDAU_REGION169.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region169 -idau.IDAU_REGION17.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region17 as exempt -idau.IDAU_REGION170.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region170 -idau.IDAU_REGION170.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region170 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION170.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region170 as exempt -idau.IDAU_REGION170.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region170 -idau.IDAU_REGION170.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region170 -idau.IDAU_REGION171.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region171 -idau.IDAU_REGION171.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region171 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION171.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region171 as exempt -idau.IDAU_REGION171.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region171 -idau.IDAU_REGION171.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region171 -idau.IDAU_REGION172.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region172 -idau.IDAU_REGION172.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region172 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION172.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region172 as exempt -idau.IDAU_REGION172.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region172 -idau.IDAU_REGION172.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region172 -idau.IDAU_REGION173.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region173 -idau.IDAU_REGION173.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region173 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION173.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region173 as exempt -idau.IDAU_REGION173.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region173 -idau.IDAU_REGION173.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region173 -idau.IDAU_REGION174.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region174 -idau.IDAU_REGION174.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region174 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION174.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region174 as exempt -idau.IDAU_REGION174.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region174 -idau.IDAU_REGION174.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region174 -idau.IDAU_REGION175.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region175 -idau.IDAU_REGION175.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region175 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION175.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region175 as exempt -idau.IDAU_REGION175.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region175 -idau.IDAU_REGION175.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region175 -idau.IDAU_REGION176.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region176 -idau.IDAU_REGION176.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region176 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION176.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region176 as exempt -idau.IDAU_REGION176.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region176 -idau.IDAU_REGION176.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region176 -idau.IDAU_REGION177.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region177 -idau.IDAU_REGION177.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region177 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION177.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region177 as exempt -idau.IDAU_REGION177.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region177 -idau.IDAU_REGION177.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region177 -idau.IDAU_REGION178.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region178 -idau.IDAU_REGION178.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region178 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION178.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region178 as exempt -idau.IDAU_REGION178.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region178 -idau.IDAU_REGION178.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region178 -idau.IDAU_REGION179.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region179 -idau.IDAU_REGION179.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region179 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION179.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region179 as exempt -idau.IDAU_REGION179.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region179 -idau.IDAU_REGION179.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region179 -idau.IDAU_REGION18.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region18 -idau.IDAU_REGION18.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region18 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION18.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region18 as exempt -idau.IDAU_REGION18.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region18 -idau.IDAU_REGION18.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region18 -idau.IDAU_REGION180.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region180 -idau.IDAU_REGION180.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region180 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION180.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region180 as exempt -idau.IDAU_REGION180.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region180 -idau.IDAU_REGION180.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region180 -idau.IDAU_REGION181.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region181 -idau.IDAU_REGION181.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region181 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION181.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region181 as exempt -idau.IDAU_REGION181.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region181 -idau.IDAU_REGION181.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region181 -idau.IDAU_REGION182.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region182 -idau.IDAU_REGION182.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region182 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION182.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region182 as exempt -idau.IDAU_REGION182.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region182 -idau.IDAU_REGION182.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region182 -idau.IDAU_REGION183.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region183 -idau.IDAU_REGION183.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region183 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION183.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region183 as exempt -idau.IDAU_REGION183.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region183 -idau.IDAU_REGION183.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region183 -idau.IDAU_REGION184.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region184 -idau.IDAU_REGION184.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region184 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION184.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region184 as exempt -idau.IDAU_REGION184.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region184 -idau.IDAU_REGION184.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region184 -idau.IDAU_REGION185.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region185 -idau.IDAU_REGION185.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region185 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION185.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region185 as exempt -idau.IDAU_REGION185.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region185 -idau.IDAU_REGION185.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region185 -idau.IDAU_REGION186.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region186 -idau.IDAU_REGION186.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region186 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION186.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region186 as exempt -idau.IDAU_REGION186.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region186 -idau.IDAU_REGION186.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region186 -idau.IDAU_REGION187.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region187 -idau.IDAU_REGION187.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region187 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION187.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region187 as exempt -idau.IDAU_REGION187.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region187 -idau.IDAU_REGION187.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region187 -idau.IDAU_REGION188.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region188 -idau.IDAU_REGION188.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region188 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION188.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region188 as exempt -idau.IDAU_REGION188.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region188 -idau.IDAU_REGION188.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region188 -idau.IDAU_REGION189.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region189 -idau.IDAU_REGION189.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region189 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION189.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region189 as exempt -idau.IDAU_REGION189.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region189 -idau.IDAU_REGION189.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region189 -idau.IDAU_REGION19.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region19 -idau.IDAU_REGION19.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region19 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION19.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region19 as exempt -idau.IDAU_REGION19.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region19 -idau.IDAU_REGION19.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region19 -idau.IDAU_REGION190.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region190 -idau.IDAU_REGION190.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region190 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION190.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region190 as exempt -idau.IDAU_REGION190.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region190 -idau.IDAU_REGION190.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region190 -idau.IDAU_REGION191.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region191 -idau.IDAU_REGION191.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region191 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION191.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region191 as exempt -idau.IDAU_REGION191.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region191 -idau.IDAU_REGION191.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region191 -idau.IDAU_REGION192.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region192 -idau.IDAU_REGION192.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region192 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION192.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region192 as exempt -idau.IDAU_REGION192.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region192 -idau.IDAU_REGION192.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region192 -idau.IDAU_REGION193.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region193 -idau.IDAU_REGION193.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region193 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION193.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region193 as exempt -idau.IDAU_REGION193.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region193 -idau.IDAU_REGION193.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region193 -idau.IDAU_REGION194.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region194 -idau.IDAU_REGION194.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region194 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION194.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region194 as exempt -idau.IDAU_REGION194.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region194 -idau.IDAU_REGION194.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region194 -idau.IDAU_REGION195.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region195 -idau.IDAU_REGION195.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region195 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION195.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region195 as exempt -idau.IDAU_REGION195.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region195 -idau.IDAU_REGION195.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region195 -idau.IDAU_REGION196.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region196 -idau.IDAU_REGION196.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region196 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION196.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region196 as exempt -idau.IDAU_REGION196.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region196 -idau.IDAU_REGION196.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region196 -idau.IDAU_REGION197.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region197 -idau.IDAU_REGION197.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region197 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION197.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region197 as exempt -idau.IDAU_REGION197.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region197 -idau.IDAU_REGION197.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region197 -idau.IDAU_REGION198.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region198 -idau.IDAU_REGION198.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region198 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION198.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region198 as exempt -idau.IDAU_REGION198.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region198 -idau.IDAU_REGION198.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region198 -idau.IDAU_REGION199.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region199 -idau.IDAU_REGION199.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region199 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION199.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region199 as exempt -idau.IDAU_REGION199.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region199 -idau.IDAU_REGION199.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region199 -idau.IDAU_REGION2.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region2 as exempt -idau.IDAU_REGION20.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region20 -idau.IDAU_REGION20.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region20 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION20.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region20 as exempt -idau.IDAU_REGION20.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region20 -idau.IDAU_REGION20.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region20 -idau.IDAU_REGION200.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region200 -idau.IDAU_REGION200.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region200 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION200.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region200 as exempt -idau.IDAU_REGION200.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region200 -idau.IDAU_REGION200.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region200 -idau.IDAU_REGION201.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region201 -idau.IDAU_REGION201.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region201 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION201.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region201 as exempt -idau.IDAU_REGION201.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region201 -idau.IDAU_REGION201.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region201 -idau.IDAU_REGION202.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region202 -idau.IDAU_REGION202.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region202 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION202.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region202 as exempt -idau.IDAU_REGION202.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region202 -idau.IDAU_REGION202.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region202 -idau.IDAU_REGION203.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region203 -idau.IDAU_REGION203.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region203 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION203.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region203 as exempt -idau.IDAU_REGION203.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region203 -idau.IDAU_REGION203.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region203 -idau.IDAU_REGION204.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region204 -idau.IDAU_REGION204.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region204 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION204.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region204 as exempt -idau.IDAU_REGION204.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region204 -idau.IDAU_REGION204.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region204 -idau.IDAU_REGION205.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region205 -idau.IDAU_REGION205.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region205 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION205.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region205 as exempt -idau.IDAU_REGION205.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region205 -idau.IDAU_REGION205.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region205 -idau.IDAU_REGION206.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region206 -idau.IDAU_REGION206.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region206 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION206.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region206 as exempt -idau.IDAU_REGION206.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region206 -idau.IDAU_REGION206.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region206 -idau.IDAU_REGION207.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region207 -idau.IDAU_REGION207.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region207 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION207.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region207 as exempt -idau.IDAU_REGION207.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region207 -idau.IDAU_REGION207.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region207 -idau.IDAU_REGION208.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region208 -idau.IDAU_REGION208.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region208 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION208.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region208 as exempt -idau.IDAU_REGION208.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region208 -idau.IDAU_REGION208.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region208 -idau.IDAU_REGION209.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region209 -idau.IDAU_REGION209.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region209 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION209.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region209 as exempt -idau.IDAU_REGION209.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region209 -idau.IDAU_REGION209.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region209 -idau.IDAU_REGION21.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region21 -idau.IDAU_REGION21.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region21 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION21.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region21 as exempt -idau.IDAU_REGION21.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region21 -idau.IDAU_REGION21.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region21 -idau.IDAU_REGION210.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region210 -idau.IDAU_REGION210.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region210 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION210.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region210 as exempt -idau.IDAU_REGION210.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region210 -idau.IDAU_REGION210.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region210 -idau.IDAU_REGION211.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region211 -idau.IDAU_REGION211.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region211 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION211.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region211 as exempt -idau.IDAU_REGION211.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region211 -idau.IDAU_REGION211.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region211 -idau.IDAU_REGION212.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region212 -idau.IDAU_REGION212.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region212 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION212.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region212 as exempt -idau.IDAU_REGION212.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region212 -idau.IDAU_REGION212.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region212 -idau.IDAU_REGION213.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region213 -idau.IDAU_REGION213.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region213 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION213.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region213 as exempt -idau.IDAU_REGION213.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region213 -idau.IDAU_REGION213.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region213 -idau.IDAU_REGION214.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region214 -idau.IDAU_REGION214.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region214 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION214.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region214 as exempt -idau.IDAU_REGION214.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region214 -idau.IDAU_REGION214.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region214 -idau.IDAU_REGION215.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region215 -idau.IDAU_REGION215.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region215 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION215.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region215 as exempt -idau.IDAU_REGION215.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region215 -idau.IDAU_REGION215.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region215 -idau.IDAU_REGION216.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region216 -idau.IDAU_REGION216.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region216 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION216.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region216 as exempt -idau.IDAU_REGION216.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region216 -idau.IDAU_REGION216.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region216 -idau.IDAU_REGION217.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region217 -idau.IDAU_REGION217.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region217 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION217.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region217 as exempt -idau.IDAU_REGION217.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region217 -idau.IDAU_REGION217.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region217 -idau.IDAU_REGION218.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region218 -idau.IDAU_REGION218.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region218 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION218.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region218 as exempt -idau.IDAU_REGION218.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region218 -idau.IDAU_REGION218.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region218 -idau.IDAU_REGION219.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region219 -idau.IDAU_REGION219.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region219 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION219.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region219 as exempt -idau.IDAU_REGION219.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region219 -idau.IDAU_REGION219.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region219 -idau.IDAU_REGION22.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region22 -idau.IDAU_REGION22.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region22 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION22.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region22 as exempt -idau.IDAU_REGION22.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region22 -idau.IDAU_REGION22.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region22 -idau.IDAU_REGION220.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region220 -idau.IDAU_REGION220.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region220 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION220.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region220 as exempt -idau.IDAU_REGION220.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region220 -idau.IDAU_REGION220.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region220 -idau.IDAU_REGION221.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region221 -idau.IDAU_REGION221.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region221 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION221.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region221 as exempt -idau.IDAU_REGION221.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region221 -idau.IDAU_REGION221.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region221 -idau.IDAU_REGION222.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region222 -idau.IDAU_REGION222.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region222 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION222.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region222 as exempt -idau.IDAU_REGION222.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region222 -idau.IDAU_REGION222.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region222 -idau.IDAU_REGION223.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region223 -idau.IDAU_REGION223.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region223 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION223.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region223 as exempt -idau.IDAU_REGION223.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region223 -idau.IDAU_REGION223.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region223 -idau.IDAU_REGION224.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region224 -idau.IDAU_REGION224.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region224 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION224.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region224 as exempt -idau.IDAU_REGION224.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region224 -idau.IDAU_REGION224.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region224 -idau.IDAU_REGION225.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region225 -idau.IDAU_REGION225.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region225 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION225.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region225 as exempt -idau.IDAU_REGION225.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region225 -idau.IDAU_REGION225.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region225 -idau.IDAU_REGION226.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region226 -idau.IDAU_REGION226.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region226 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION226.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region226 as exempt -idau.IDAU_REGION226.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region226 -idau.IDAU_REGION226.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region226 -idau.IDAU_REGION227.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region227 -idau.IDAU_REGION227.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region227 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION227.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region227 as exempt -idau.IDAU_REGION227.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region227 -idau.IDAU_REGION227.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region227 -idau.IDAU_REGION228.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region228 -idau.IDAU_REGION228.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region228 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION228.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region228 as exempt -idau.IDAU_REGION228.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region228 -idau.IDAU_REGION228.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region228 -idau.IDAU_REGION229.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region229 -idau.IDAU_REGION229.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region229 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION229.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region229 as exempt -idau.IDAU_REGION229.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region229 -idau.IDAU_REGION229.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region229 -idau.IDAU_REGION23.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region23 -idau.IDAU_REGION23.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region23 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION23.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region23 as exempt -idau.IDAU_REGION23.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region23 -idau.IDAU_REGION23.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region23 -idau.IDAU_REGION230.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region230 -idau.IDAU_REGION230.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region230 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION230.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region230 as exempt -idau.IDAU_REGION230.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region230 -idau.IDAU_REGION230.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region230 -idau.IDAU_REGION231.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region231 -idau.IDAU_REGION231.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region231 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION231.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region231 as exempt -idau.IDAU_REGION231.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region231 -idau.IDAU_REGION231.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region231 -idau.IDAU_REGION232.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region232 -idau.IDAU_REGION232.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region232 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION232.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region232 as exempt -idau.IDAU_REGION232.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region232 -idau.IDAU_REGION232.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region232 -idau.IDAU_REGION233.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region233 -idau.IDAU_REGION233.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region233 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION233.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region233 as exempt -idau.IDAU_REGION233.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region233 -idau.IDAU_REGION233.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region233 -idau.IDAU_REGION234.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region234 -idau.IDAU_REGION234.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region234 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION234.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region234 as exempt -idau.IDAU_REGION234.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region234 -idau.IDAU_REGION234.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region234 -idau.IDAU_REGION235.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region235 -idau.IDAU_REGION235.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region235 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION235.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region235 as exempt -idau.IDAU_REGION235.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region235 -idau.IDAU_REGION235.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region235 -idau.IDAU_REGION236.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region236 -idau.IDAU_REGION236.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region236 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION236.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region236 as exempt -idau.IDAU_REGION236.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region236 -idau.IDAU_REGION236.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region236 -idau.IDAU_REGION237.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region237 -idau.IDAU_REGION237.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region237 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION237.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region237 as exempt -idau.IDAU_REGION237.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region237 -idau.IDAU_REGION237.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region237 -idau.IDAU_REGION238.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region238 -idau.IDAU_REGION238.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region238 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION238.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region238 as exempt -idau.IDAU_REGION238.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region238 -idau.IDAU_REGION238.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region238 -idau.IDAU_REGION239.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region239 -idau.IDAU_REGION239.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region239 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION239.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region239 as exempt -idau.IDAU_REGION239.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region239 -idau.IDAU_REGION239.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region239 -idau.IDAU_REGION24.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region24 -idau.IDAU_REGION24.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region24 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION24.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region24 as exempt -idau.IDAU_REGION24.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region24 -idau.IDAU_REGION24.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region24 -idau.IDAU_REGION240.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region240 -idau.IDAU_REGION240.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region240 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION240.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region240 as exempt -idau.IDAU_REGION240.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region240 -idau.IDAU_REGION240.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region240 -idau.IDAU_REGION241.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region241 -idau.IDAU_REGION241.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region241 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION241.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region241 as exempt -idau.IDAU_REGION241.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region241 -idau.IDAU_REGION241.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region241 -idau.IDAU_REGION242.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region242 -idau.IDAU_REGION242.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region242 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION242.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region242 as exempt -idau.IDAU_REGION242.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region242 -idau.IDAU_REGION242.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region242 -idau.IDAU_REGION243.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region243 -idau.IDAU_REGION243.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region243 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION243.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region243 as exempt -idau.IDAU_REGION243.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region243 -idau.IDAU_REGION243.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region243 -idau.IDAU_REGION244.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region244 -idau.IDAU_REGION244.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region244 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION244.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region244 as exempt -idau.IDAU_REGION244.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region244 -idau.IDAU_REGION244.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region244 -idau.IDAU_REGION245.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region245 -idau.IDAU_REGION245.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region245 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION245.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region245 as exempt -idau.IDAU_REGION245.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region245 -idau.IDAU_REGION245.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region245 -idau.IDAU_REGION246.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region246 -idau.IDAU_REGION246.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region246 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION246.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region246 as exempt -idau.IDAU_REGION246.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region246 -idau.IDAU_REGION246.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region246 -idau.IDAU_REGION247.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region247 -idau.IDAU_REGION247.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region247 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION247.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region247 as exempt -idau.IDAU_REGION247.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region247 -idau.IDAU_REGION247.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region247 -idau.IDAU_REGION248.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region248 -idau.IDAU_REGION248.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region248 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION248.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region248 as exempt -idau.IDAU_REGION248.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region248 -idau.IDAU_REGION248.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region248 -idau.IDAU_REGION249.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region249 -idau.IDAU_REGION249.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region249 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION249.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region249 as exempt -idau.IDAU_REGION249.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region249 -idau.IDAU_REGION249.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region249 -idau.IDAU_REGION25.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region25 -idau.IDAU_REGION25.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region25 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION25.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region25 as exempt -idau.IDAU_REGION25.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region25 -idau.IDAU_REGION25.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region25 -idau.IDAU_REGION250.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region250 -idau.IDAU_REGION250.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region250 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION250.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region250 as exempt -idau.IDAU_REGION250.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region250 -idau.IDAU_REGION250.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region250 -idau.IDAU_REGION251.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region251 -idau.IDAU_REGION251.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region251 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION251.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region251 as exempt -idau.IDAU_REGION251.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region251 -idau.IDAU_REGION251.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region251 -idau.IDAU_REGION252.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region252 -idau.IDAU_REGION252.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region252 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION252.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region252 as exempt -idau.IDAU_REGION252.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region252 -idau.IDAU_REGION252.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region252 -idau.IDAU_REGION253.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region253 -idau.IDAU_REGION253.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region253 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION253.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region253 as exempt -idau.IDAU_REGION253.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region253 -idau.IDAU_REGION253.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region253 -idau.IDAU_REGION254.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region254 -idau.IDAU_REGION254.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region254 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION254.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region254 as exempt -idau.IDAU_REGION254.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region254 -idau.IDAU_REGION254.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region254 -idau.IDAU_REGION255.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region255 -idau.IDAU_REGION255.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region255 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION255.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region255 as exempt -idau.IDAU_REGION255.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region255 -idau.IDAU_REGION255.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region255 -idau.IDAU_REGION26.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region26 -idau.IDAU_REGION26.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region26 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION26.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region26 as exempt -idau.IDAU_REGION26.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region26 -idau.IDAU_REGION26.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region26 -idau.IDAU_REGION27.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region27 -idau.IDAU_REGION27.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region27 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION27.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region27 as exempt -idau.IDAU_REGION27.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region27 -idau.IDAU_REGION27.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region27 -idau.IDAU_REGION28.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region28 -idau.IDAU_REGION28.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region28 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION28.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region28 as exempt -idau.IDAU_REGION28.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region28 -idau.IDAU_REGION28.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region28 -idau.IDAU_REGION29.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region29 -idau.IDAU_REGION29.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region29 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION29.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region29 as exempt -idau.IDAU_REGION29.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region29 -idau.IDAU_REGION29.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region29 -idau.IDAU_REGION3.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region3 as exempt -idau.IDAU_REGION30.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region30 -idau.IDAU_REGION30.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region30 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION30.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region30 as exempt -idau.IDAU_REGION30.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region30 -idau.IDAU_REGION30.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region30 -idau.IDAU_REGION31.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region31 -idau.IDAU_REGION31.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region31 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION31.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region31 as exempt -idau.IDAU_REGION31.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region31 -idau.IDAU_REGION31.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region31 -idau.IDAU_REGION32.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region32 -idau.IDAU_REGION32.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region32 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION32.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region32 as exempt -idau.IDAU_REGION32.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region32 -idau.IDAU_REGION32.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region32 -idau.IDAU_REGION33.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region33 -idau.IDAU_REGION33.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region33 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION33.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region33 as exempt -idau.IDAU_REGION33.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region33 -idau.IDAU_REGION33.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region33 -idau.IDAU_REGION34.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region34 -idau.IDAU_REGION34.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region34 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION34.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region34 as exempt -idau.IDAU_REGION34.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region34 -idau.IDAU_REGION34.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region34 -idau.IDAU_REGION35.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region35 -idau.IDAU_REGION35.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region35 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION35.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region35 as exempt -idau.IDAU_REGION35.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region35 -idau.IDAU_REGION35.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region35 -idau.IDAU_REGION36.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region36 -idau.IDAU_REGION36.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region36 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION36.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region36 as exempt -idau.IDAU_REGION36.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region36 -idau.IDAU_REGION36.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region36 -idau.IDAU_REGION37.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region37 -idau.IDAU_REGION37.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region37 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION37.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region37 as exempt -idau.IDAU_REGION37.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region37 -idau.IDAU_REGION37.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region37 -idau.IDAU_REGION38.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region38 -idau.IDAU_REGION38.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region38 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION38.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region38 as exempt -idau.IDAU_REGION38.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region38 -idau.IDAU_REGION38.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region38 -idau.IDAU_REGION39.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region39 -idau.IDAU_REGION39.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region39 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION39.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region39 as exempt -idau.IDAU_REGION39.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region39 -idau.IDAU_REGION39.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region39 -idau.IDAU_REGION4.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region4 as exempt -idau.IDAU_REGION40.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region40 -idau.IDAU_REGION40.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region40 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION40.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region40 as exempt -idau.IDAU_REGION40.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region40 -idau.IDAU_REGION40.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region40 -idau.IDAU_REGION41.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region41 -idau.IDAU_REGION41.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region41 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION41.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region41 as exempt -idau.IDAU_REGION41.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region41 -idau.IDAU_REGION41.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region41 -idau.IDAU_REGION42.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region42 -idau.IDAU_REGION42.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region42 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION42.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region42 as exempt -idau.IDAU_REGION42.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region42 -idau.IDAU_REGION42.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region42 -idau.IDAU_REGION43.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region43 -idau.IDAU_REGION43.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region43 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION43.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region43 as exempt -idau.IDAU_REGION43.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region43 -idau.IDAU_REGION43.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region43 -idau.IDAU_REGION44.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region44 -idau.IDAU_REGION44.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region44 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION44.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region44 as exempt -idau.IDAU_REGION44.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region44 -idau.IDAU_REGION44.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region44 -idau.IDAU_REGION45.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region45 -idau.IDAU_REGION45.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region45 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION45.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region45 as exempt -idau.IDAU_REGION45.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region45 -idau.IDAU_REGION45.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region45 -idau.IDAU_REGION46.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region46 -idau.IDAU_REGION46.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region46 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION46.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region46 as exempt -idau.IDAU_REGION46.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region46 -idau.IDAU_REGION46.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region46 -idau.IDAU_REGION47.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region47 -idau.IDAU_REGION47.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region47 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION47.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region47 as exempt -idau.IDAU_REGION47.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region47 -idau.IDAU_REGION47.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region47 -idau.IDAU_REGION48.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region48 -idau.IDAU_REGION48.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region48 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION48.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region48 as exempt -idau.IDAU_REGION48.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region48 -idau.IDAU_REGION48.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region48 -idau.IDAU_REGION49.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region49 -idau.IDAU_REGION49.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region49 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION49.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region49 as exempt -idau.IDAU_REGION49.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region49 -idau.IDAU_REGION49.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region49 -idau.IDAU_REGION5.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region5 as exempt -idau.IDAU_REGION50.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region50 -idau.IDAU_REGION50.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region50 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION50.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region50 as exempt -idau.IDAU_REGION50.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region50 -idau.IDAU_REGION50.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region50 -idau.IDAU_REGION51.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region51 -idau.IDAU_REGION51.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region51 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION51.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region51 as exempt -idau.IDAU_REGION51.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region51 -idau.IDAU_REGION51.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region51 -idau.IDAU_REGION52.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region52 -idau.IDAU_REGION52.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region52 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION52.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region52 as exempt -idau.IDAU_REGION52.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region52 -idau.IDAU_REGION52.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region52 -idau.IDAU_REGION53.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region53 -idau.IDAU_REGION53.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region53 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION53.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region53 as exempt -idau.IDAU_REGION53.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region53 -idau.IDAU_REGION53.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region53 -idau.IDAU_REGION54.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region54 -idau.IDAU_REGION54.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region54 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION54.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region54 as exempt -idau.IDAU_REGION54.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region54 -idau.IDAU_REGION54.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region54 -idau.IDAU_REGION55.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region55 -idau.IDAU_REGION55.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region55 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION55.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region55 as exempt -idau.IDAU_REGION55.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region55 -idau.IDAU_REGION55.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region55 -idau.IDAU_REGION56.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region56 -idau.IDAU_REGION56.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region56 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION56.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region56 as exempt -idau.IDAU_REGION56.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region56 -idau.IDAU_REGION56.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region56 -idau.IDAU_REGION57.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region57 -idau.IDAU_REGION57.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region57 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION57.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region57 as exempt -idau.IDAU_REGION57.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region57 -idau.IDAU_REGION57.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region57 -idau.IDAU_REGION58.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region58 -idau.IDAU_REGION58.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region58 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION58.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region58 as exempt -idau.IDAU_REGION58.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region58 -idau.IDAU_REGION58.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region58 -idau.IDAU_REGION59.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region59 -idau.IDAU_REGION59.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region59 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION59.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region59 as exempt -idau.IDAU_REGION59.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region59 -idau.IDAU_REGION59.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region59 -idau.IDAU_REGION6.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region6 as exempt -idau.IDAU_REGION60.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region60 -idau.IDAU_REGION60.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region60 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION60.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region60 as exempt -idau.IDAU_REGION60.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region60 -idau.IDAU_REGION60.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region60 -idau.IDAU_REGION61.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region61 -idau.IDAU_REGION61.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region61 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION61.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region61 as exempt -idau.IDAU_REGION61.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region61 -idau.IDAU_REGION61.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region61 -idau.IDAU_REGION62.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region62 -idau.IDAU_REGION62.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region62 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION62.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region62 as exempt -idau.IDAU_REGION62.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region62 -idau.IDAU_REGION62.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region62 -idau.IDAU_REGION63.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region63 -idau.IDAU_REGION63.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region63 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION63.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region63 as exempt -idau.IDAU_REGION63.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region63 -idau.IDAU_REGION63.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region63 -idau.IDAU_REGION64.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region64 -idau.IDAU_REGION64.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region64 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION64.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region64 as exempt -idau.IDAU_REGION64.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region64 -idau.IDAU_REGION64.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region64 -idau.IDAU_REGION65.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region65 -idau.IDAU_REGION65.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region65 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION65.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region65 as exempt -idau.IDAU_REGION65.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region65 -idau.IDAU_REGION65.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region65 -idau.IDAU_REGION66.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region66 -idau.IDAU_REGION66.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region66 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION66.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region66 as exempt -idau.IDAU_REGION66.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region66 -idau.IDAU_REGION66.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region66 -idau.IDAU_REGION67.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region67 -idau.IDAU_REGION67.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region67 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION67.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region67 as exempt -idau.IDAU_REGION67.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region67 -idau.IDAU_REGION67.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region67 -idau.IDAU_REGION68.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region68 -idau.IDAU_REGION68.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region68 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION68.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region68 as exempt -idau.IDAU_REGION68.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region68 -idau.IDAU_REGION68.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region68 -idau.IDAU_REGION69.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region69 -idau.IDAU_REGION69.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region69 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION69.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region69 as exempt -idau.IDAU_REGION69.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region69 -idau.IDAU_REGION69.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region69 -idau.IDAU_REGION7.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region7 as exempt -idau.IDAU_REGION70.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region70 -idau.IDAU_REGION70.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region70 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION70.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region70 as exempt -idau.IDAU_REGION70.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region70 -idau.IDAU_REGION70.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region70 -idau.IDAU_REGION71.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region71 -idau.IDAU_REGION71.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region71 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION71.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region71 as exempt -idau.IDAU_REGION71.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region71 -idau.IDAU_REGION71.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region71 -idau.IDAU_REGION72.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region72 -idau.IDAU_REGION72.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region72 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION72.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region72 as exempt -idau.IDAU_REGION72.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region72 -idau.IDAU_REGION72.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region72 -idau.IDAU_REGION73.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region73 -idau.IDAU_REGION73.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region73 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION73.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region73 as exempt -idau.IDAU_REGION73.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region73 -idau.IDAU_REGION73.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region73 -idau.IDAU_REGION74.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region74 -idau.IDAU_REGION74.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region74 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION74.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region74 as exempt -idau.IDAU_REGION74.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region74 -idau.IDAU_REGION74.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region74 -idau.IDAU_REGION75.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region75 -idau.IDAU_REGION75.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region75 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION75.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region75 as exempt -idau.IDAU_REGION75.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region75 -idau.IDAU_REGION75.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region75 -idau.IDAU_REGION76.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region76 -idau.IDAU_REGION76.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region76 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION76.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region76 as exempt -idau.IDAU_REGION76.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region76 -idau.IDAU_REGION76.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region76 -idau.IDAU_REGION77.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region77 -idau.IDAU_REGION77.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region77 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION77.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region77 as exempt -idau.IDAU_REGION77.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region77 -idau.IDAU_REGION77.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region77 -idau.IDAU_REGION78.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region78 -idau.IDAU_REGION78.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region78 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION78.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region78 as exempt -idau.IDAU_REGION78.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region78 -idau.IDAU_REGION78.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region78 -idau.IDAU_REGION79.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region79 -idau.IDAU_REGION79.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region79 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION79.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region79 as exempt -idau.IDAU_REGION79.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region79 -idau.IDAU_REGION79.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region79 -idau.IDAU_REGION8.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region8 as exempt -idau.IDAU_REGION80.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region80 -idau.IDAU_REGION80.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region80 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION80.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region80 as exempt -idau.IDAU_REGION80.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region80 -idau.IDAU_REGION80.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region80 -idau.IDAU_REGION81.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region81 -idau.IDAU_REGION81.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region81 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION81.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region81 as exempt -idau.IDAU_REGION81.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region81 -idau.IDAU_REGION81.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region81 -idau.IDAU_REGION82.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region82 -idau.IDAU_REGION82.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region82 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION82.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region82 as exempt -idau.IDAU_REGION82.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region82 -idau.IDAU_REGION82.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region82 -idau.IDAU_REGION83.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region83 -idau.IDAU_REGION83.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region83 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION83.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region83 as exempt -idau.IDAU_REGION83.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region83 -idau.IDAU_REGION83.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region83 -idau.IDAU_REGION84.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region84 -idau.IDAU_REGION84.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region84 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION84.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region84 as exempt -idau.IDAU_REGION84.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region84 -idau.IDAU_REGION84.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region84 -idau.IDAU_REGION85.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region85 -idau.IDAU_REGION85.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region85 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION85.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region85 as exempt -idau.IDAU_REGION85.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region85 -idau.IDAU_REGION85.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region85 -idau.IDAU_REGION86.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region86 -idau.IDAU_REGION86.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region86 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION86.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region86 as exempt -idau.IDAU_REGION86.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region86 -idau.IDAU_REGION86.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region86 -idau.IDAU_REGION87.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region87 -idau.IDAU_REGION87.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region87 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION87.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region87 as exempt -idau.IDAU_REGION87.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region87 -idau.IDAU_REGION87.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region87 -idau.IDAU_REGION88.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region88 -idau.IDAU_REGION88.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region88 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION88.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region88 as exempt -idau.IDAU_REGION88.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region88 -idau.IDAU_REGION88.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region88 -idau.IDAU_REGION89.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region89 -idau.IDAU_REGION89.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region89 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION89.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region89 as exempt -idau.IDAU_REGION89.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region89 -idau.IDAU_REGION89.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region89 -idau.IDAU_REGION9.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region9 as exempt -idau.IDAU_REGION90.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region90 -idau.IDAU_REGION90.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region90 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION90.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region90 as exempt -idau.IDAU_REGION90.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region90 -idau.IDAU_REGION90.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region90 -idau.IDAU_REGION91.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region91 -idau.IDAU_REGION91.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region91 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION91.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region91 as exempt -idau.IDAU_REGION91.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region91 -idau.IDAU_REGION91.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region91 -idau.IDAU_REGION92.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region92 -idau.IDAU_REGION92.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region92 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION92.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region92 as exempt -idau.IDAU_REGION92.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region92 -idau.IDAU_REGION92.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region92 -idau.IDAU_REGION93.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region93 -idau.IDAU_REGION93.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region93 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION93.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region93 as exempt -idau.IDAU_REGION93.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region93 -idau.IDAU_REGION93.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region93 -idau.IDAU_REGION94.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region94 -idau.IDAU_REGION94.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region94 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION94.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region94 as exempt -idau.IDAU_REGION94.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region94 -idau.IDAU_REGION94.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region94 -idau.IDAU_REGION95.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region95 -idau.IDAU_REGION95.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region95 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION95.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region95 as exempt -idau.IDAU_REGION95.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region95 -idau.IDAU_REGION95.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region95 -idau.IDAU_REGION96.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region96 -idau.IDAU_REGION96.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region96 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION96.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region96 as exempt -idau.IDAU_REGION96.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region96 -idau.IDAU_REGION96.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region96 -idau.IDAU_REGION97.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region97 -idau.IDAU_REGION97.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region97 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION97.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region97 as exempt -idau.IDAU_REGION97.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region97 -idau.IDAU_REGION97.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region97 -idau.IDAU_REGION98.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region98 -idau.IDAU_REGION98.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region98 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION98.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region98 as exempt -idau.IDAU_REGION98.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region98 -idau.IDAU_REGION98.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region98 -idau.IDAU_REGION99.BADDR=0 # (int , init-time) default = '0x0' : Base address of IDAU region99 -idau.IDAU_REGION99.ENABLE=0 # (bool , init-time) default = '0' : 0 => IDAU region99 is S (absent if LADDR=0), 1 => NS or NSC or exempt. -idau.IDAU_REGION99.EXEMPT=0 # (bool , init-time) default = '0' : Mark IDAU region99 as exempt -idau.IDAU_REGION99.LADDR=0 # (int , init-time) default = '0x0' : Limit address of IDAU region99 -idau.IDAU_REGION99.NSC=0 # (bool , init-time) default = '0' : Set NSC for IDAU region99 -idau.NUM_IDAU_REGION=18 # (int , init-time) default = '0x12' : -mps3_board.AHBPPCEXP_DIS0=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP0 and AHBPPPCEXP0 buses -mps3_board.AHBPPCEXP_DIS1=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP1 and AHBPPPCEXP1 buses -mps3_board.AHBPPCEXP_DIS2=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP2 and AHBPPPCEXP2 buses -mps3_board.AHBPPCEXP_DIS3=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP3 and AHBPPPCEXP3 buses -mps3_board.APBPPCEXP_DIS0=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP0 and APBPPPCEXP0 buses -mps3_board.APBPPCEXP_DIS1=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP1 and APBPPPCEXP1 buses -mps3_board.APBPPCEXP_DIS2=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP2 and APBPPPCEXP2 buses -mps3_board.APBPPCEXP_DIS3=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP3 and APBPPPCEXP3 buses -mps3_board.DISABLE_GATING=0 # (bool , init-time) default = '0' : Disable Memory gating logic -mps3_board.HAS_CRYPTO=0 # (bool , init-time) default = '0' : CryptoCell Included. 0:No, 1: Yes -mps3_board.HAS_CSS=0 # (bool , init-time) default = '0' : CoreSight SoC-600 based Debug infrastructure Included. 0:No, 1: Yes -mps3_board.PSRAM.fill1=3755990991 # (int , init-time) default = '0xdfdfdfcf' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.PSRAM.fill2=3487555551 # (int , init-time) default = '0xcfdfdfdf' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.PSRAM.size=4294967296 # (int , init-time) default = '0x100000000' : Memory Size -mps3_board.PSRAM_M7.fill1=3755990991 # (int , init-time) default = '0xdfdfdfcf' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.PSRAM_M7.fill2=3487555551 # (int , init-time) default = '0xcfdfdfdf' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.PSRAM_M7.size=4294967296 # (int , init-time) default = '0x100000000' : Memory Size -mps3_board.ahb_ppc_iotss_expansion0.NONSEC_MASK=0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask -mps3_board.ahb_ppc_iotss_expansion1.NONSEC_MASK=0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask -mps3_board.apb_ppc_iotss_expansion0.NONSEC_MASK=0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask -mps3_board.apb_ppc_iotss_expansion1.NONSEC_MASK=0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask -mps3_board.apb_ppc_iotss_expansion2.NONSEC_MASK=0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask -mps3_board.clock50Hz.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.cmsdk_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -mps3_board.ddr.fill1=3755990991 # (int , init-time) default = '0xdfdfdfcf' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.ddr.fill2=3487555551 # (int , init-time) default = '0xcfdfdfdf' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.ddr.size=1073741824 # (int , init-time) default = '0x40000000' : Memory Size -mps3_board.dma0.activate_delay=0 # (int , init-time) default = '0x0' : request delay -mps3_board.dma0.fifo_size=16 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -mps3_board.dma0.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -mps3_board.dma0.max_transfer=256 # (int , init-time) default = '0x100' : Largest atomic transfer -mps3_board.dma0_securitymodifier.behaviour_ns_to_s=0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -mps3_board.dma1.activate_delay=0 # (int , init-time) default = '0x0' : request delay -mps3_board.dma1.fifo_size=16 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -mps3_board.dma1.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -mps3_board.dma1.max_transfer=256 # (int , init-time) default = '0x100' : Largest atomic transfer -mps3_board.dma1_securitymodifier.behaviour_ns_to_s=0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -mps3_board.dma2.activate_delay=0 # (int , init-time) default = '0x0' : request delay -mps3_board.dma2.fifo_size=16 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -mps3_board.dma2.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -mps3_board.dma2.max_transfer=256 # (int , init-time) default = '0x100' : Largest atomic transfer -mps3_board.dma2_securitymodifier.behaviour_ns_to_s=0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -mps3_board.dma3.activate_delay=0 # (int , init-time) default = '0x0' : request delay -mps3_board.dma3.fifo_size=16 # (int , init-time) default = '0x10' : Channel FIFO size in bytes -mps3_board.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response -mps3_board.dma3.max_transfer=256 # (int , init-time) default = '0x100' : Largest atomic transfer -mps3_board.dma3_securitymodifier.behaviour_ns_to_s=0 # (int , init-time) default = '0x0' : Behaviour for NS transactions to S space : 0:block 1:transmit 2:convert to S -mps3_board.exclusive_monitor_ddr.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -mps3_board.exclusive_monitor_ddr.clear_on_strex_address_mismatch=1 # (bool , init-time) default = '1' : Whether monitor is cleared when strex fails due to address mismatch -mps3_board.exclusive_monitor_ddr.enable_component=1 # (bool , init-time) default = '1' : Enable component -mps3_board.exclusive_monitor_ddr.log2_granule_size=0 # (int , init-time) default = '0x0' : log2 of address granule size -mps3_board.exclusive_monitor_ddr.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -mps3_board.exclusive_monitor_ddr.monitor_access_level=0 # (int , init-time) default = '0x0' : 0: Monitor all accesses, 1: Monitor all accesses except WriteBack, 2: Only monitor accesses with memory type NonCacheable or Device -mps3_board.exclusive_monitor_ddr.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -mps3_board.exclusive_monitor_ddr.number_of_monitors=8 # (int , init-time) default = '0x8' : Number of monitors -mps3_board.exclusive_monitor_ddr.shareability_domain=3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) -mps3_board.exclusive_monitor_psram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -mps3_board.exclusive_monitor_psram.clear_on_strex_address_mismatch=1 # (bool , init-time) default = '1' : Whether monitor is cleared when strex fails due to address mismatch -mps3_board.exclusive_monitor_psram.enable_component=1 # (bool , init-time) default = '1' : Enable component -mps3_board.exclusive_monitor_psram.log2_granule_size=0 # (int , init-time) default = '0x0' : log2 of address granule size -mps3_board.exclusive_monitor_psram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -mps3_board.exclusive_monitor_psram.monitor_access_level=0 # (int , init-time) default = '0x0' : 0: Monitor all accesses, 1: Monitor all accesses except WriteBack, 2: Only monitor accesses with memory type NonCacheable or Device -mps3_board.exclusive_monitor_psram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -mps3_board.exclusive_monitor_psram.number_of_monitors=8 # (int , init-time) default = '0x8' : Number of monitors -mps3_board.exclusive_monitor_psram.shareability_domain=3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) -mps3_board.exclusive_monitor_qspi_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -mps3_board.exclusive_monitor_qspi_sram.clear_on_strex_address_mismatch=1 # (bool , init-time) default = '1' : Whether monitor is cleared when strex fails due to address mismatch -mps3_board.exclusive_monitor_qspi_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -mps3_board.exclusive_monitor_qspi_sram.log2_granule_size=0 # (int , init-time) default = '0x0' : log2 of address granule size -mps3_board.exclusive_monitor_qspi_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -mps3_board.exclusive_monitor_qspi_sram.monitor_access_level=0 # (int , init-time) default = '0x0' : 0: Monitor all accesses, 1: Monitor all accesses except WriteBack, 2: Only monitor accesses with memory type NonCacheable or Device -mps3_board.exclusive_monitor_qspi_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -mps3_board.exclusive_monitor_qspi_sram.number_of_monitors=8 # (int , init-time) default = '0x8' : Number of monitors -mps3_board.exclusive_monitor_qspi_sram.shareability_domain=3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) -mps3_board.exclusive_monitor_sram.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -mps3_board.exclusive_monitor_sram.clear_on_strex_address_mismatch=1 # (bool , init-time) default = '1' : Whether monitor is cleared when strex fails due to address mismatch -mps3_board.exclusive_monitor_sram.enable_component=1 # (bool , init-time) default = '1' : Enable component -mps3_board.exclusive_monitor_sram.log2_granule_size=0 # (int , init-time) default = '0x0' : log2 of address granule size -mps3_board.exclusive_monitor_sram.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -mps3_board.exclusive_monitor_sram.monitor_access_level=0 # (int , init-time) default = '0x0' : 0: Monitor all accesses, 1: Monitor all accesses except WriteBack, 2: Only monitor accesses with memory type NonCacheable or Device -mps3_board.exclusive_monitor_sram.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -mps3_board.exclusive_monitor_sram.number_of_monitors=8 # (int , init-time) default = '0x8' : Number of monitors -mps3_board.exclusive_monitor_sram.shareability_domain=3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) -mps3_board.expansion_warning_memory.abort_on_reads=0 # (bool , init-time) default = '0' : Abort on reads (read 0 if false) -mps3_board.expansion_warning_memory.abort_on_writes=0 # (bool , init-time) default = '0' : Abort on writes (ignore if false) -mps3_board.expansion_warning_memory.read_data=0 # (int , init-time) default = '0x0' : Data to return on reads, if not aborting -mps3_board.extra_psram_size=33554432 # (int , init-time) default = '0x2000000' : Size of extra PSRAM RAM -mps3_board.gpio_test_enable=0 # (bool , init-time) default = '0' : Enable GPIO connection test -mps3_board.hostbridge.interfaceName= # (string, init-time) default = '' : Host Interface -mps3_board.hostbridge.userNetOptions= # (string, init-time) default = '' : Control options for UserNet TCP/IP (for internal use only, please do not use) -mps3_board.hostbridge.userNetPorts= # (string, init-time) default = '' : Listening ports to expose in user-mode networking -mps3_board.hostbridge.userNetSubnet=172.20.51.0/24 # (string, init-time) default = '172.20.51.0/24' : Virtual subnet for user-mode networking -mps3_board.hostbridge.userNetworking=0 # (bool , init-time) default = '0' : Enable user-mode networking -mps3_board.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu0 in reset at boot -mps3_board.iotss_systemcontrol.cpu1wait=0 # (bool , init-time) default = '0' : Whether to hold cpu1 in reset at boot -mps3_board.mps3_cmsdk_dualtimer.clk_div0.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.mps3_cmsdk_dualtimer.clk_div0.mul=1 # (int , init-time) default = '0x1' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.mps3_cmsdk_dualtimer.clk_div1.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.mps3_cmsdk_dualtimer.clk_div1.mul=1 # (int , init-time) default = '0x1' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.mps3_exclusive_monitor_zbtsram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -mps3_board.mps3_exclusive_monitor_zbtsram1.clear_on_strex_address_mismatch=1 # (bool , init-time) default = '1' : Whether monitor is cleared when strex fails due to address mismatch -mps3_board.mps3_exclusive_monitor_zbtsram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -mps3_board.mps3_exclusive_monitor_zbtsram1.log2_granule_size=0 # (int , init-time) default = '0x0' : log2 of address granule size -mps3_board.mps3_exclusive_monitor_zbtsram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -mps3_board.mps3_exclusive_monitor_zbtsram1.monitor_access_level=0 # (int , init-time) default = '0x0' : 0: Monitor all accesses, 1: Monitor all accesses except WriteBack, 2: Only monitor accesses with memory type NonCacheable or Device -mps3_board.mps3_exclusive_monitor_zbtsram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -mps3_board.mps3_exclusive_monitor_zbtsram1.number_of_monitors=8 # (int , init-time) default = '0x8' : Number of monitors -mps3_board.mps3_exclusive_monitor_zbtsram1.shareability_domain=3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) -mps3_board.mps3_exclusive_monitor_zbtsram2.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -mps3_board.mps3_exclusive_monitor_zbtsram2.clear_on_strex_address_mismatch=1 # (bool , init-time) default = '1' : Whether monitor is cleared when strex fails due to address mismatch -mps3_board.mps3_exclusive_monitor_zbtsram2.enable_component=1 # (bool , init-time) default = '1' : Enable component -mps3_board.mps3_exclusive_monitor_zbtsram2.log2_granule_size=0 # (int , init-time) default = '0x0' : log2 of address granule size -mps3_board.mps3_exclusive_monitor_zbtsram2.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -mps3_board.mps3_exclusive_monitor_zbtsram2.monitor_access_level=0 # (int , init-time) default = '0x0' : 0: Monitor all accesses, 1: Monitor all accesses except WriteBack, 2: Only monitor accesses with memory type NonCacheable or Device -mps3_board.mps3_exclusive_monitor_zbtsram2.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -mps3_board.mps3_exclusive_monitor_zbtsram2.number_of_monitors=8 # (int , init-time) default = '0x8' : Number of monitors -mps3_board.mps3_exclusive_monitor_zbtsram2.shareability_domain=3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) -mps3_board.mps3_secure_control_register_block.AHBPPCEXP_DIS0=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP0 and AHBPPPCEXP0 buses -mps3_board.mps3_secure_control_register_block.AHBPPCEXP_DIS1=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP1 and AHBPPPCEXP1 buses -mps3_board.mps3_secure_control_register_block.AHBPPCEXP_DIS2=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP2 and AHBPPPCEXP2 buses -mps3_board.mps3_secure_control_register_block.AHBPPCEXP_DIS3=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the AHBNSPPCEXP3 and AHBPPPCEXP3 buses -mps3_board.mps3_secure_control_register_block.APBPPCEXP_DIS0=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP0 and APBPPPCEXP0 buses -mps3_board.mps3_secure_control_register_block.APBPPCEXP_DIS1=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP1 and APBPPPCEXP1 buses -mps3_board.mps3_secure_control_register_block.APBPPCEXP_DIS2=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP2 and APBPPPCEXP2 buses -mps3_board.mps3_secure_control_register_block.APBPPCEXP_DIS3=0 # (int , init-time) default = '0x0' : Disables support for individual bits on the APBNSPPCEXP3 and APBPPPCEXP3 buses -mps3_board.mps3_secure_control_register_block.FLASH_BLOCK_CFG=3 # (int , init-time) default = '0x3' : Flash Block size configuration -mps3_board.mps3_secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -mps3_board.mps3_secure_control_register_block.SRAM_BLOCK_CFG=3 # (int , init-time) default = '0x3' : SRAM Block size configuration -mps3_board.mps3_secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -mps3_board.mps3_timer0.clk_div.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.mps3_timer0.clk_div.mul=1 # (int , init-time) default = '0x1' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.mps3_timer1.clk_div.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.mps3_timer1.clk_div.mul=1 # (int , init-time) default = '0x1' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.periph_clk.mul=25000000 # (int , init-time) default = '0x17d7840' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.platform_type=1 # (int , init-time) default = '0x1' : 0:Original MPS3; 1:SSE-300 -mps3_board.qspi_sram.fill1=3755990991 # (int , init-time) default = '0xdfdfdfcf' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.qspi_sram.fill2=3487555551 # (int , init-time) default = '0xcfdfdfdf' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.qspi_sram.size=8388608 # (int , init-time) default = '0x800000' : Memory Size -mps3_board.rtc.RTCDR_reset_value=0 # (int , init-time) default = '0x0' : Reset value for RTCDR -mps3_board.rtc.RTCDR_use_current_time=1 # (bool , init-time) default = '1' : Use current Unix/POSIX time for reset value for RTCDR. If true RTCDR_reset_value is ignored -mps3_board.smsc_91c111.cache_size=65536 # (int , init-time) default = '0x10000' : Size of cache memory in SMSC MMU -mps3_board.smsc_91c111.enabled=0 # (bool , init-time) default = '0' : Host interface connection enabled -mps3_board.smsc_91c111.mac_address=00:02:f7:ef:00:02 # (string, init-time) default = '00:02:f7:ef:00:02' : Host/model MAC address -mps3_board.smsc_91c111.not_lan911x=0 # (bool , init-time) default = '0' : Gracefully fail SMSC LAN911x driver probe -mps3_board.smsc_91c111.promiscuous=1 # (bool , init-time) default = '1' : Put host into promiscuous mode -mps3_board.sram.fill1=3755990991 # (int , init-time) default = '0xdfdfdfcf' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.sram.fill2=3487555551 # (int , init-time) default = '0xcfdfdfdf' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.sram.size=2097152 # (int , init-time) default = '0x200000' : Memory Size -mps3_board.sse300.NUMCPU=1 # (int , init-time) default = '0x1' : Number of Cortex-M CPU cores in the subsystem -mps3_board.sse300.NUMVMBANK=2 # (int , init-time) default = '0x2' : Number of Volatile Memory Banks -mps3_board.sse300.VM_BANK_SIZE=256 # (int , init-time) default = '0x100' : Volatile Memory Bank Size in KiloBytes, where the size of each bank is equal to 2^VM_ADDR_WIDTH -mps3_board.sse300.apb_ppc_iotss3_subsystem0.NONSEC_MASK=0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask -mps3_board.sse300.apb_ppc_iotss3_subsystem0.PORTx_ENABLE=65535 # (int , init-time) default = '0xffff' : Enable (1) or disable (0) port x (where x is between 0-15): enable = 1, disable = 0 -mps3_board.sse300.apb_ppc_iotss3_subsystem1.NONSEC_MASK=0 # (int , init-time) default = '0x0' : 16-bit wide mask for security checking of ports: 0 = check, 1 = mask -mps3_board.sse300.apb_ppc_iotss3_subsystem1.PORTx_ENABLE=65535 # (int , init-time) default = '0xffff' : Enable (1) or disable (0) port x (where x is between 0-15): enable = 1, disable = 0 -mps3_board.sse300.bus_error_warning_memory.read_data=0 # (int , init-time) default = '0x0' : Data to return on reads, if not aborting -mps3_board.sse300.clock32kHz.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.sse300.clockdivider.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.sse300.cpu0core_ppu.RevD_support=0 # (bool , init-time) default = '0' : Whether to support Rev D locked IRQ -mps3_board.sse300.cpu0core_ppu.default_op_dyn_en=0 # (bool , init-time) default = '0' : Whether to enable operating mode dynamic transition by default -mps3_board.sse300.cpu0core_ppu.default_op_policy=0 # (int , init-time) default = '0x0' : Default operating policy -mps3_board.sse300.cpu0core_ppu.lock_support=1 # (bool , init-time) default = '1' : Whether to support OFF lock feature -mps3_board.sse300.cpu0core_ppu.revision=r1p1 # (string, init-time) default = 'r1p1' : Revision -mps3_board.sse300.crypto_ppu.RevD_support=0 # (bool , init-time) default = '0' : Whether to support Rev D locked IRQ -mps3_board.sse300.crypto_ppu.default_op_dyn_en=0 # (bool , init-time) default = '0' : Whether to enable operating mode dynamic transition by default -mps3_board.sse300.crypto_ppu.default_op_policy=0 # (int , init-time) default = '0x0' : Default operating policy -mps3_board.sse300.crypto_ppu.default_pwr_dyn_en=0 # (bool , init-time) default = '0' : Whether to enable dynamic power mode transition by default -mps3_board.sse300.crypto_ppu.is_core_ppu=0 # (bool , init-time) default = '0' : PPU is core_ppu type which means wake_request would wait till PPU is OFF/OFF_EMU -mps3_board.sse300.crypto_ppu.lock_support=1 # (bool , init-time) default = '1' : Whether to support OFF lock feature -mps3_board.sse300.crypto_ppu.num_opmode_cfg=0 # (int , init-time) default = '0x0' : Number of operating modes -mps3_board.sse300.crypto_ppu.op_active_cfg=0 # (int , init-time) default = '0x0' : Operating mode active configuration (0: Ladder use model, 1: Independent user model) -mps3_board.sse300.crypto_ppu.revision=r1p1 # (string, init-time) default = 'r1p1' : Revision -mps3_board.sse300.crypto_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -mps3_board.sse300.dbg_ppu.RevD_support=0 # (bool , init-time) default = '0' : Whether to support Rev D locked IRQ -mps3_board.sse300.dbg_ppu.default_op_dyn_en=0 # (bool , init-time) default = '0' : Whether to enable operating mode dynamic transition by default -mps3_board.sse300.dbg_ppu.default_op_policy=0 # (int , init-time) default = '0x0' : Default operating policy -mps3_board.sse300.dbg_ppu.is_core_ppu=0 # (bool , init-time) default = '0' : PPU is core_ppu type which means wake_request would wait till PPU is OFF/OFF_EMU -mps3_board.sse300.dbg_ppu.lock_support=1 # (bool , init-time) default = '1' : Whether to support OFF lock feature -mps3_board.sse300.dbg_ppu.num_opmode_cfg=0 # (int , init-time) default = '0x0' : Number of operating modes -mps3_board.sse300.dbg_ppu.op_active_cfg=0 # (int , init-time) default = '0x0' : Operating mode active configuration (0: Ladder use model, 1: Independent user model) -mps3_board.sse300.dbg_ppu.revision=r1p1 # (string, init-time) default = 'r1p1' : Revision -mps3_board.sse300.dbg_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram0.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram0.clear_on_strex_address_mismatch=1 # (bool , init-time) default = '1' : Whether monitor is cleared when strex fails due to address mismatch -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram0.enable_component=1 # (bool , init-time) default = '1' : Enable component -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram0.log2_granule_size=0 # (int , init-time) default = '0x0' : log2 of address granule size -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram0.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram0.monitor_access_level=0 # (int , init-time) default = '0x0' : 0: Monitor all accesses, 1: Monitor all accesses except WriteBack, 2: Only monitor accesses with memory type NonCacheable or Device -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram0.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram0.number_of_monitors=8 # (int , init-time) default = '0x8' : Number of monitors -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram0.shareability_domain=3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram1.apply_access_width_criteria_to_non_excl_stores=1 # (bool , init-time) default = '1' : Apply the given exclusive store width matching criteria to non-exclusive stores -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram1.clear_on_strex_address_mismatch=1 # (bool , init-time) default = '1' : Whether monitor is cleared when strex fails due to address mismatch -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram1.enable_component=1 # (bool , init-time) default = '1' : Enable component -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram1.log2_granule_size=0 # (int , init-time) default = '0x0' : log2 of address granule size -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram1.match_secure_state=1 # (bool , init-time) default = '1' : Treat the secure state like an address bit -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram1.monitor_access_level=0 # (int , init-time) default = '0x0' : 0: Monitor all accesses, 1: Monitor all accesses except WriteBack, 2: Only monitor accesses with memory type NonCacheable or Device -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram1.monitor_non_excl_stores=0 # (bool , init-time) default = '0' : Monitor non-exclusive stores from the same master -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram1.number_of_monitors=8 # (int , init-time) default = '0x8' : Number of monitors -mps3_board.sse300.exclusive_monitor_iotss3_internal_sram1.shareability_domain=3 # (int , init-time) default = '0x3' : Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system) -mps3_board.sse300.iotss3_cpuidentity.debugger_master_id=4294967295 # (int , init-time) default = '0xffffffff' : -mps3_board.sse300.iotss3_internal_sram0.fill1=3755990991 # (int , init-time) default = '0xdfdfdfcf' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.sse300.iotss3_internal_sram0.fill2=3487555551 # (int , init-time) default = '0xcfdfdfdf' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.sse300.iotss3_internal_sram0.size=4294967296 # (int , init-time) default = '0x100000000' : Memory Size -mps3_board.sse300.iotss3_internal_sram1.fill1=3755990991 # (int , init-time) default = '0xdfdfdfcf' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.sse300.iotss3_internal_sram1.fill2=3487555551 # (int , init-time) default = '0xcfdfdfdf' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.sse300.iotss3_internal_sram1.size=4294967296 # (int , init-time) default = '0x100000000' : Memory Size -mps3_board.sse300.iotss3_systemcontrol.cpu1wait=1 # (bool , init-time) default = '1' : Whether to hold cpu1 in reset at boot -mps3_board.sse300.iotss3_systemcontrol.cpu2wait=1 # (bool , init-time) default = '1' : Whether to hold cpu2 in reset at boot -mps3_board.sse300.iotss3_systemcontrol.cpu3wait=1 # (bool , init-time) default = '1' : Whether to hold cpu3 in reset at boot -mps3_board.sse300.iotss3_systeminfo.CPU0_HAS_TCM=0 # (bool , init-time) default = '0' : CPU 0 has System TCM. 0:No, 1: Yes -mps3_board.sse300.iotss3_systeminfo.CPU0_TCM_BANK_NUM=0 # (int , init-time) default = '0x0' : The VM Bank that is the TCM memory for CPU 0 -mps3_board.sse300.iotss3_systeminfo.CPU1_HAS_TCM=0 # (bool , init-time) default = '0' : CPU 1 has System TCM. 0:No, 1: Yes -mps3_board.sse300.iotss3_systeminfo.CPU1_TCM_BANK_NUM=0 # (int , init-time) default = '0x0' : The VM Bank that is the TCM memory for CPU 1 -mps3_board.sse300.iotss3_systeminfo.CPU2_HAS_TCM=0 # (bool , init-time) default = '0' : CPU 2 has System TCM. 0:No, 1: Yes -mps3_board.sse300.iotss3_systeminfo.CPU2_TCM_BANK_NUM=0 # (int , init-time) default = '0x0' : The VM Bank that is the TCM memory for CPU 2 -mps3_board.sse300.iotss3_systeminfo.CPU3_HAS_TCM=0 # (bool , init-time) default = '0' : CPU 3 has System TCM. 0:No, 1: Yes -mps3_board.sse300.iotss3_systeminfo.CPU3_TCM_BANK_NUM=0 # (int , init-time) default = '0x0' : The VM Bank that is the TCM memory for CPU 3 -mps3_board.sse300.mgmt_ppu.RevD_support=0 # (bool , init-time) default = '0' : Whether to support Rev D locked IRQ -mps3_board.sse300.mgmt_ppu.default_op_dyn_en=0 # (bool , init-time) default = '0' : Whether to enable operating mode dynamic transition by default -mps3_board.sse300.mgmt_ppu.default_op_policy=0 # (int , init-time) default = '0x0' : Default operating policy -mps3_board.sse300.mgmt_ppu.default_pwr_dyn_en=0 # (bool , init-time) default = '0' : Whether to enable dynamic power mode transition by default -mps3_board.sse300.mgmt_ppu.is_core_ppu=0 # (bool , init-time) default = '0' : PPU is core_ppu type which means wake_request would wait till PPU is OFF/OFF_EMU -mps3_board.sse300.mgmt_ppu.lock_support=1 # (bool , init-time) default = '1' : Whether to support OFF lock feature -mps3_board.sse300.mgmt_ppu.num_opmode_cfg=0 # (int , init-time) default = '0x0' : Number of operating modes -mps3_board.sse300.mgmt_ppu.op_active_cfg=0 # (int , init-time) default = '0x0' : Operating mode active configuration (0: Ladder use model, 1: Independent user model) -mps3_board.sse300.mgmt_ppu.revision=r1p1 # (string, init-time) default = 'r1p1' : Revision -mps3_board.sse300.mgmt_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -mps3_board.sse300.nonsecure_watchdog.diagnostics=0 # (int , init-time) default = '0x0' : Diagnostics -mps3_board.sse300.nonsecure_watchdog.product_id=0 # (int , init-time) default = '0x0' : Product Identifier -mps3_board.sse300.refcounter.base_frequency=100000000 # (int , init-time) default = '0x5f5e100' : Reset value for CNTFID0, base frequency in Hz -mps3_board.sse300.refcounter.cntcidr0123_C=0 # (int , init-time) default = '0x0' : Values to be returned for control-frame CIDR registers -mps3_board.sse300.refcounter.cntcidr0123_R=0 # (int , init-time) default = '0x0' : Values to be returned for read-frame CIDR registers -mps3_board.sse300.refcounter.cntpidr0123_C=0 # (int , init-time) default = '0x0' : Values to be returned for control-frame PIDR registers 0-3 -mps3_board.sse300.refcounter.cntpidr0123_R=0 # (int , init-time) default = '0x0' : Values to be returned for read-frame PIDR registers 0-3 -mps3_board.sse300.refcounter.cntpidr4567_C=0 # (int , init-time) default = '0x0' : Values to be returned for control-frame PIDR registers 4-7 -mps3_board.sse300.refcounter.cntpidr4567_R=0 # (int , init-time) default = '0x0' : Values to be returned for read-frame PIDR registers 4-7 -mps3_board.sse300.refcounter.diagnostics=0 # (int , init-time) default = '0x0' : Diagnostics -mps3_board.sse300.refcounter.has_counter_scaling=0 # (bool , init-time) default = '0' : Implements ARMv8.4 generic counter scaling -mps3_board.sse300.refcounter.non_arch_fixed_frequency=0 # (int , init-time) default = '0x0' : If set, ignore CNTFID0 and instead use this frequency in Hz -mps3_board.sse300.refcounter.non_arch_start_at_default=1 # (bool , init-time) default = '1' : Firmware is expected to enable the timer at boot time. However, turning this parameter on is a model-specific way of enabling the counter module out of reset. -mps3_board.sse300.refcounter.readonly_is_WI=0 # (bool , init-time) default = '0' : Ignore (rather than failing) on writes to read-frame -mps3_board.sse300.refcounter.use_real_time=0 # (bool , init-time) default = '0' : Update the Generic Timer counter at a real-time base frequency instead of simulator time -mps3_board.sse300.s32k_timer.clk_div.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.sse300.s32k_timer.clk_div.mul=1 # (int , init-time) default = '0x1' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.sse300.s32k_watchdog.simhalt=0 # (bool , run-time ) default = '0' : Halt on reset. -mps3_board.sse300.secure_control_register_block.FLASH_BLOCK_CFG=3 # (int , init-time) default = '0x3' : Flash Block size configuration -mps3_board.sse300.secure_control_register_block.FLASH_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : Flash Watermark supported -mps3_board.sse300.secure_control_register_block.SRAM_BLOCK_CFG=3 # (int , init-time) default = '0x3' : SRAM Block size configuration -mps3_board.sse300.secure_control_register_block.SRAM_WATERMARK_SUPPORTED=1 # (bool , init-time) default = '1' : SRAM Watermark supported -mps3_board.sse300.secure_watchdog.diagnostics=0 # (int , init-time) default = '0x0' : Diagnostics -mps3_board.sse300.secure_watchdog.product_id=0 # (int , init-time) default = '0x0' : Product Identifier -mps3_board.sse300.sys_ppu.RevD_support=0 # (bool , init-time) default = '0' : Whether to support Rev D locked IRQ -mps3_board.sse300.sys_ppu.default_op_dyn_en=0 # (bool , init-time) default = '0' : Whether to enable operating mode dynamic transition by default -mps3_board.sse300.sys_ppu.default_op_policy=0 # (int , init-time) default = '0x0' : Default operating policy -mps3_board.sse300.sys_ppu.is_core_ppu=0 # (bool , init-time) default = '0' : PPU is core_ppu type which means wake_request would wait till PPU is OFF/OFF_EMU -mps3_board.sse300.sys_ppu.lock_support=1 # (bool , init-time) default = '1' : Whether to support OFF lock feature -mps3_board.sse300.sys_ppu.revision=r1p1 # (string, init-time) default = 'r1p1' : Revision -mps3_board.sse300.sys_ppu.use_active_signal=0 # (bool , init-time) default = '0' : Use device-active signal -mps3_board.sse300.timer0.bypass_ctlbase=1 # (bool , init-time) default = '1' : Bypass CNTBase Access Control. Enable if only timer frame feature is required without CNTBase access control -mps3_board.sse300.timer0.cntel0acr_implemented=0 # (int , init-time) default = '0x0' : A bit-field of 8 bits, where bit {n} enables CNTEL0ACR for timer frame {n} -mps3_board.sse300.timer0.diagnostics=0 # (int , init-time) default = '0x0' : Diagnostics -mps3_board.sse300.timer0.frame_security= # (string, init-time) default = '' : Hard-wired/configurable security for frames (N/S/X, one character per timer frame) -mps3_board.sse300.timer0.num_timers=1 # (int , init-time) default = '0x1' : Number of timer frames -mps3_board.sse300.timer1.bypass_ctlbase=1 # (bool , init-time) default = '1' : Bypass CNTBase Access Control. Enable if only timer frame feature is required without CNTBase access control -mps3_board.sse300.timer1.cntel0acr_implemented=0 # (int , init-time) default = '0x0' : A bit-field of 8 bits, where bit {n} enables CNTEL0ACR for timer frame {n} -mps3_board.sse300.timer1.diagnostics=0 # (int , init-time) default = '0x0' : Diagnostics -mps3_board.sse300.timer1.frame_security= # (string, init-time) default = '' : Hard-wired/configurable security for frames (N/S/X, one character per timer frame) -mps3_board.sse300.timer1.num_timers=1 # (int , init-time) default = '0x1' : Number of timer frames -mps3_board.sse300.timer2.bypass_ctlbase=1 # (bool , init-time) default = '1' : Bypass CNTBase Access Control. Enable if only timer frame feature is required without CNTBase access control -mps3_board.sse300.timer2.cntel0acr_implemented=0 # (int , init-time) default = '0x0' : A bit-field of 8 bits, where bit {n} enables CNTEL0ACR for timer frame {n} -mps3_board.sse300.timer2.diagnostics=0 # (int , init-time) default = '0x0' : Diagnostics -mps3_board.sse300.timer2.frame_security= # (string, init-time) default = '' : Hard-wired/configurable security for frames (N/S/X, one character per timer frame) -mps3_board.sse300.timer2.num_timers=1 # (int , init-time) default = '0x1' : Number of timer frames -mps3_board.sse300.timer3.bypass_ctlbase=1 # (bool , init-time) default = '1' : Bypass CNTBase Access Control. Enable if only timer frame feature is required without CNTBase access control -mps3_board.sse300.timer3.cntel0acr_implemented=0 # (int , init-time) default = '0x0' : A bit-field of 8 bits, where bit {n} enables CNTEL0ACR for timer frame {n} -mps3_board.sse300.timer3.diagnostics=0 # (int , init-time) default = '0x0' : Diagnostics -mps3_board.sse300.timer3.num_timers=1 # (int , init-time) default = '0x1' : Number of timer frames -mps3_board.ssram1.fill1=3755990991 # (int , init-time) default = '0xdfdfdfcf' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.ssram1.fill2=3487555551 # (int , init-time) default = '0xcfdfdfdf' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.ssram1.size=4294967296 # (int , init-time) default = '0x100000000' : Memory Size -mps3_board.ssram2.fill1=3755990991 # (int , init-time) default = '0xdfdfdfcf' : Fill pattern 1, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.ssram2.fill2=3487555551 # (int , init-time) default = '0xcfdfdfdf' : Fill pattern 2, initialise memory at start of simulation with alternating fill1, fill2 pattern -mps3_board.ssram2.size=4294967296 # (int , init-time) default = '0x100000000' : Memory Size -mps3_board.stub_i2c_spi.size=4294967296 # (int , init-time) default = '0x100000000' : Memory Size -mps3_board.telnetterminal0.mode=telnet # (string, init-time) default = 'telnet' : Terminal initialisation mode -mps3_board.telnetterminal0.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -mps3_board.telnetterminal0.start_port=5000 # (int , init-time) default = '0x1388' : Telnet TCP Port Number -mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected -mps3_board.telnetterminal0.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -mps3_board.telnetterminal1.mode=telnet # (string, init-time) default = 'telnet' : Terminal initialisation mode -mps3_board.telnetterminal1.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -mps3_board.telnetterminal1.start_port=5000 # (int , init-time) default = '0x1388' : Telnet TCP Port Number -mps3_board.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected -mps3_board.telnetterminal1.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -mps3_board.telnetterminal2.mode=telnet # (string, init-time) default = 'telnet' : Terminal initialisation mode -mps3_board.telnetterminal2.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -mps3_board.telnetterminal2.start_port=5000 # (int , init-time) default = '0x1388' : Telnet TCP Port Number -mps3_board.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected -mps3_board.telnetterminal2.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -mps3_board.telnetterminal5.mode=telnet # (string, init-time) default = 'telnet' : Terminal initialisation mode -mps3_board.telnetterminal5.quiet=0 # (bool , init-time) default = '0' : Avoid output on stdout/stderr -mps3_board.telnetterminal5.start_port=5000 # (int , init-time) default = '0x1388' : Telnet TCP Port Number -mps3_board.telnetterminal5.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected -mps3_board.telnetterminal5.terminal_command="" # (string, init-time) default = '' : Commandline to launch a terminal application and connect to the opened TCP port. Keywords %port and %title will be replaced with the opened port number and component name respectively. An empty string (default behaviour) will launch xterm (Linux) or telnet.exe (Windows) -mps3_board.uart0.clk_divider.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.uart0.clk_divider.mul=1 # (int , init-time) default = '0x1' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.uart0.in_file= # (string, init-time) default = '' : Input file for data to be read by the UART -mps3_board.uart0.in_file_escape_sequence=## # (string, init-time) default = '##' : Input file escape sequence -mps3_board.uart0.out_file='-' # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -mps3_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -mps3_board.uart0.shutdown_tag= # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -mps3_board.uart0.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -mps3_board.uart1.clk_divider.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.uart1.clk_divider.mul=1 # (int , init-time) default = '0x1' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.uart1.in_file= # (string, init-time) default = '' : Input file for data to be read by the UART -mps3_board.uart1.in_file_escape_sequence=## # (string, init-time) default = '##' : Input file escape sequence -mps3_board.uart1.out_file='-' # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -mps3_board.uart1.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -mps3_board.uart1.shutdown_tag= # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -mps3_board.uart1.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -mps3_board.uart2.clk_divider.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.uart2.clk_divider.mul=1 # (int , init-time) default = '0x1' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.uart2.in_file= # (string, init-time) default = '' : Input file for data to be read by the UART -mps3_board.uart2.in_file_escape_sequence=## # (string, init-time) default = '##' : Input file escape sequence -mps3_board.uart2.out_file= # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -mps3_board.uart2.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -mps3_board.uart2.shutdown_tag= # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -mps3_board.uart2.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -mps3_board.uart3_stub.size=4294967296 # (int , init-time) default = '0x100000000' : Memory Size -mps3_board.uart4_stub.size=4294967296 # (int , init-time) default = '0x100000000' : Memory Size -mps3_board.uart5.clk_divider.div=1 # (int , init-time) default = '0x1' : Clock Rate Divider. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.uart5.clk_divider.mul=1 # (int , init-time) default = '0x1' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -mps3_board.uart5.in_file= # (string, init-time) default = '' : Input file for data to be read by the UART -mps3_board.uart5.in_file_escape_sequence=## # (string, init-time) default = '##' : Input file escape sequence -mps3_board.uart5.out_file='-' # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) -mps3_board.uart5.shutdown_on_eot=0 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) -mps3_board.uart5.shutdown_tag= # (string, run-time ) default = '' : Shutdown simulation when a string is transmitted -mps3_board.uart5.unbuffered_output=0 # (bool , init-time) default = '0' : Unbuffered output -mps3_board.usb_stub.size=4294967296 # (int , init-time) default = '0x100000000' : Memory Size -mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -mps3_board.visualisation.idler.delay_ms=50 # (int , init-time) default = '0x32' : Determines the period, in milliseconds of real time, between gui_callback() calls. -mps3_board.visualisation.rate_limit-enable=0 # (bool , init-time) default = '1' : Rate limit simulation. -mps3_board.visualisation.window_title=CLCD %cpu% # (string, init-time) default = 'CLCD %cpu%' : Window title (%cpu% is replaced by cpu_name) diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Include/led_port.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Include/led_port.h deleted file mode 100644 index e9e6e28..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Include/led_port.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2017 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __LED_PORT_H__ -#define __LED_PORT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* The goal of this file is to create a common LED API for different targets in order - * create common example applications. - */ - -/* Note: Currently this API doesn't handle the case when a peripheral is - * mapped to secure and non-secure region as well, but could be extended - * to select secure or non-secure one. - */ - -/** - * \brief Get the number of bits of LED port, - * in the current platform, that can be - * read and written in one chunk. - * - * \return Available number of bits of LED port. - */ -unsigned int get_led_port_bit_length(void); - -/** - * \brief Initializes LED device if needed - */ -void led_port_init(void); - -/** - * \brief Set the value of the LED port. - * - * \param[in] led Value of the LED port will be set. - * Every bit represents one physical LED. - * - * \return 0 if succeeded, 1 otherwise - */ -unsigned int set_led_port(unsigned int led_mask); - -/** - * \brief Get the value of the LED port. - * - * \return Value of the LED port - * Every bit represents one physical LED. - */ -unsigned int get_led_port(void); - - -#ifdef __cplusplus -} -#endif -#endif /* __LED_PORT_H__ */ diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Include/serial.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Include/serial.h deleted file mode 100644 index 77f15a4..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Include/serial.h +++ /dev/null @@ -1,33 +0,0 @@ -/* -* Copyright (c) 2017 Arm Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#ifndef __SERIAL_H__ -#define __SERIAL_H__ - - -#include - -/** - * \brief Initializes default UART device - */ -void serial_init(void); - -/** - * \brief Prints a string through the default UART device - */ -void serial_print(char *str); - -#endif /* __SERIAL_H__ */ diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Include/timeout.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Include/timeout.h deleted file mode 100644 index a9931ae..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Include/timeout.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2017-2019 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __TIMEOUT_H__ -#define __TIMEOUT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include "device_definition.h" - -/* Structure to maintain elapsed time */ -struct timeout_t { - void *dev_ptr; - bool is_initialized; -}; - -/** - * \brief Initializes timout structure - * - * \param[in] timeout Pointer to the timeout structure - * \param[in] delay Delay in ms to check timeout against - * - * \return Returns true if the delay value was set, - * false otherwise - */ -bool timeout_init(struct timeout_t *timeout, uint32_t delay); - -/** - * \brief Checks if the given time has passed or not - * - * \param[in] timer Pointer to the timer structure - * - * \details This function compares the timestamp stored in the timeout structure - * and the current time. If the difference is more than the given delay, - * the current time is stored and will be used for the next comparison - * - * \return 1 if the given time has passed, 0 if not - */ -bool timeout_delay_is_elapsed(struct timeout_t *timeout); - -/** - * \brief Uninitializes timout structure and stops timer operation. - * - * \param[in] timeout Pointer to the timeout structure - */ -void timeout_uninit(struct timeout_t *timeout); - -/** - * \brief Waits the specified time in milliseconds. - * - * \param[in] ms Time to wait in milliseconds - */ -void wait_ms(uint32_t ms); - -#ifdef __cplusplus -} -#endif -#endif /* __TIMEOUT_H__ */ diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Source/led_port.c b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Source/led_port.c deleted file mode 100644 index 109495a..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Source/led_port.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "led_port.h" -#include "arm_mps3_io_drv.h" -#include "device_cfg.h" -#include "device_definition.h" - -#define MAX_PIN_FPGAIO_LED 10UL -#define MAX_LED_MASK ((1U << MAX_PIN_FPGAIO_LED) - 1) -#define BIT_VALUE(v, bit) (((v) >> (bit) & 1UL)) - -static unsigned int led_status; - -unsigned int get_led_port_bit_length(void) -{ - return MAX_PIN_FPGAIO_LED; -} - -void led_port_init(void) -{ - /* Turn off all LEDs at init */ - arm_mps3_io_write_leds(&MPS3_IO_DEV, ARM_MPS3_IO_ACCESS_PORT, 0, 0); - led_status = 0x0; -} - -unsigned int set_led_port(unsigned int led_mask) -{ - uint8_t i; - uint32_t value; - - if (led_mask > MAX_LED_MASK) { - return 1; - } - - /* Set the LEDs to new value one by one */ - for (i = 0; i < MAX_PIN_FPGAIO_LED; i++) { - if (BIT_VALUE((led_mask ^ led_status), i)) { - /* led pin i has new value */ - value = BIT_VALUE(led_mask, i); - arm_mps3_io_write_leds(&MPS3_IO_DEV, - ARM_MPS3_IO_ACCESS_PIN, - i, value); - } - } - led_status = led_mask; - - return 0; -} - -/** - * \brief Get the value of the LED port. - * - * \return Value of the LED port - * Every bit represents one physical LED. - */ -unsigned int get_led_port(void) -{ - return arm_mps3_io_read_leds(&MPS3_IO_DEV, - ARM_MPS3_IO_ACCESS_PORT, - 0); -} diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Source/serial.c b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Source/serial.c deleted file mode 100644 index 475f4e3..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Source/serial.c +++ /dev/null @@ -1,55 +0,0 @@ -/* -* Copyright (c) 2017-2020 Arm Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#include -#include -#include "device_cfg.h" -#include "Driver_USART.h" -#include "serial.h" - -extern ARM_DRIVER_USART Driver_USART0; - -void serial_init(void) -{ - Driver_USART0.Initialize(NULL); - Driver_USART0.Control(ARM_USART_MODE_ASYNCHRONOUS, DEFAULT_UART_BAUDRATE); -} - -void serial_print(char *str) -{ - (void)Driver_USART0.Send(str, strlen(str)); -} - -/* Struct FILE is implemented in stdio.h. Used to redirect printf to UART0 */ -//FILE __stdout; -/* Redirects armclang printf to UART */ -int stdout_putchar(int ch) -{ - if (Driver_USART0.Send(&ch, 1) == ARM_DRIVER_OK) { - return ch; - } - return EOF; -} - -/* Redirects gcc printf to UART0 */ -int _write(int fd, char *str, int len) -{ - if (Driver_USART0.Send(str, len) == ARM_DRIVER_OK) { - return len; - } - return 0; -} - diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Source/systimer_armv8-m_timeout.c b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Source/systimer_armv8-m_timeout.c deleted file mode 100644 index dc79876..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/API/Source/systimer_armv8-m_timeout.c +++ /dev/null @@ -1,73 +0,0 @@ -/* -* Copyright (c) 2019-2020 Arm Limited -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*/ - -#include "timeout.h" -#include "device_cfg.h" -#include "systimer_armv8-m_drv.h" -#include "syscounter_armv8-m_cntrl_drv.h" -#include "platform_description.h" - -#define MS_TO_TICK(ms) ((ms) * (SystemCoreClock / 1000)) - -/* Systimer is configured over the 32-bit down-counting Timer view, so maximum - * delay is defined by its bit width. */ -#define MAX_DELAY_MS (UINT32_MAX / \ - (SystemCoreClock / 1000)) - -static uint32_t delay_in_tick; - -bool timeout_init(struct timeout_t *timeout, uint32_t delay) -{ - struct systimer_armv8_m_dev_t *dev; - - if (!timeout || delay > MAX_DELAY_MS) { - return false; - } - - if (timeout->is_initialized) { - return false; - } - - syscounter_armv8_m_cntrl_init(&SYSCOUNTER_CNTRL_ARMV8_M_DEV); - - dev = &SYSTIMER0_ARMV8_M_DEV; - systimer_armv8_m_init(dev); - - delay_in_tick = MS_TO_TICK(delay); - systimer_armv8_m_set_timer_value(dev, delay_in_tick); - - timeout->dev_ptr = (void *)dev; - timeout->is_initialized = true; - - return true; -} - -bool timeout_delay_is_elapsed(struct timeout_t *timeout) -{ - struct systimer_armv8_m_dev_t* dev; - - if (!timeout || !timeout->is_initialized) { - return false; - } - - dev = (struct systimer_armv8_m_dev_t*)timeout->dev_ptr; - if (systimer_armv8_m_is_interrupt_asserted(dev)) { - systimer_armv8_m_set_timer_value(dev, delay_in_tick); - return true; - } - - return false; -} diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/RTE_Device.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/RTE_Device.h deleted file mode 100644 index 8de4d3a..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/RTE_Device.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] -// Configuration settings for Driver_USART0 in component ::Drivers:USART -#define RTE_USART0 1 -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0] - -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] -// Configuration settings for Driver_USART1 in component ::Drivers:USART -#define RTE_USART1 1 -// USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1] - -// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] -// Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC -#define RTE_ISRAM0_MPC 1 -// MPC (Memory Protection Controller) [Driver_ISRAM0_MPC] - -// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] -// Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC -#define RTE_ISRAM1_MPC 1 -// MPC (Memory Protection Controller) [Driver_ISRAM1_MPC] - -// MPC (Memory Protection Controller) [Driver_SRAM_MPC] -// Configuration settings for Driver_SRAM_MPC in component ::Drivers:MPC -#define RTE_SRAM_MPC 1 -// MPC (Memory Protection Controller) [Driver_SRAM_MPC] - -// MPC (Memory Protection Controller) [Driver_QSPI_MPC] -// Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC -#define RTE_QSPI_MPC 1 -// MPC (Memory Protection Controller) [Driver_QSPI_MPC] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN0] -// Configuration settings for Driver_PPC_SSE300_MAIN0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP0] -// Configuration settings for Driver_PPC_SSE300_MAIN_EXP0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN_EXP0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP1] -// Configuration settings for Driver_PPC_SSE300_MAIN_EXP1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_MAIN_EXP1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP1] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0] -// Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH1] -// Configuration settings for Driver_PPC_SSE300_PERIPH1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH1] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP0] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP0 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP0 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP0] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP1] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP1 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP1 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP1] - -// PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP2] -// Configuration settings for Driver_PPC_SSE300_PERIPH_EXP2 in component ::Drivers:PPC -#define RTE_PPC_SSE300_PERIPH_EXP2 1 -// PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP2] - -// Flash device emulated by SRAM [Driver_Flash0] -// Configuration settings for Driver_Flash0 in component ::Drivers:Flash -#define RTE_FLASH0 1 -// Flash device emulated by SRAM [Driver_Flash0] - -#endif /* __RTE_DEVICE_H */ diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h deleted file mode 100644 index 5ad6fb6..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2019-2020 Arm Limited. All rights reserved. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_DRIVER_CONFIG_H__ -#define __CMSIS_DRIVER_CONFIG_H__ - -#include "system_core_init.h" -#include "device_cfg.h" -#include "device_definition.h" -#include "platform_base_address.h" - -#endif /* __CMSIS_DRIVER_CONFIG_H__ */ diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/device_cfg.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/device_cfg.h deleted file mode 100644 index d3591f2..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/device_cfg.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __DEVICE_CFG_H__ -#define __DEVICE_CFG_H__ - -/** - * \file device_cfg.h - * \brief Configuration file native driver re-targeting - * - * \details This file can be used to add native driver specific macro - * definitions to select which peripherals are available in the build. - * - * This is a default device configuration file with all peripherals enabled. - */ - -/* Secure only peripheral configuration */ - -/* ARM MPS3 IO SCC */ -#define MPS3_IO_S -#define MPS3_IO_DEV MPS3_IO_DEV_S - -/* ARM UART Controller PL011 */ -#define UART0_CMSDK_S -#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S -#define UART1_CMSDK_S -#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S - -#define DEFAULT_UART_BAUDRATE 115200U - -/* To be used as CODE and DATA sram */ -#define MPC_ISRAM0_S -#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S - -#define MPC_ISRAM1_S -#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S - -#define MPC_SRAM_S -#define MPC_SRAM_DEV MPC_SRAM_DEV_S - -#define MPC_QSPI_S -#define MPC_QSPI_DEV MPC_QSPI_DEV_S - -/** System Counter Armv8-M */ -#define SYSCOUNTER_CNTRL_ARMV8_M_S -#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S - -#define SYSCOUNTER_READ_ARMV8_M_S -#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S -/** - * Arbitrary scaling values for test purposes - */ -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u -#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u - -/* System timer */ -#define SYSTIMER0_ARMV8_M_S -#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S -#define SYSTIMER1_ARMV8_M_S -#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S -#define SYSTIMER2_ARMV8_M_S -#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S -#define SYSTIMER3_ARMV8_M_S -#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S - -#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) -#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) - -/* CMSDK GPIO driver structures */ -#define GPIO0_CMSDK_S -#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S -#define GPIO1_CMSDK_S -#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S -#define GPIO2_CMSDK_S -#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S -#define GPIO3_CMSDK_S -#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S - -/* ARM MPS3 IO FPGAIO driver structures */ -#define ARM_MPS3_IO_FPGAIO_S -#define ARM_MPS3_IO_FPGAIO_DEV ARM_MPS3_IO_FPGAIO_DEV_S - -/* System Watchdogs */ -#define SYSWDOG_ARMV8_M_S -#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S - -/* ARM MPC SIE 300 driver structures */ -#define MPC_VM0_S -#define MPC_VM0_DEV MPC_VM0_DEV_S -#define MPC_VM1_S -#define MPC_VM1_DEV MPC_VM1_DEV_S -#define MPC_SSRAM2_S -#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S -#define MPC_SSRAM3_S -#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S - -/* ARM PPC driver structures */ -#define PPC_SSE300_MAIN0_S -#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S -#define PPC_SSE300_MAIN_EXP0_S -#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S -#define PPC_SSE300_MAIN_EXP1_S -#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S -#define PPC_SSE300_MAIN_EXP2_S -#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S -#define PPC_SSE300_MAIN_EXP3_S -#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S -#define PPC_SSE300_PERIPH0_S -#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S -#define PPC_SSE300_PERIPH1_S -#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S -#define PPC_SSE300_PERIPH_EXP0_S -#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S -#define PPC_SSE300_PERIPH_EXP1_S -#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S -#define PPC_SSE300_PERIPH_EXP2_S -#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S -#define PPC_SSE300_PERIPH_EXP3_S -#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S - -/* ARM SPI PL022 */ -/* Invalid device stubs are not defined */ -#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ -#define SPI1_PL022_S -#define SPI1_PL022_DEV SPI1_PL022_DEV_S - - -#endif /* __DEVICE_CFG_H__ */ \ No newline at end of file diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct deleted file mode 100644 index f289ee3..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct +++ /dev/null @@ -1,78 +0,0 @@ -#! armclang --target=arm-arm-none-eabi -mcpu=cortex-m55 -E -xc - -;/* -; * Copyright (c) 2018-2021 Arm Limited. All rights reserved. -; * -; * Licensed under the Apache License, Version 2.0 (the "License"); -; * you may not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an "AS IS" BASIS, -; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; * -; */ - -#include "region_defs.h" - -LR_CODE S_CODE_START { - ER_CODE S_CODE_START { - *.o (RESET +First) - .ANY (+RO) - } - - /* - * Place the CMSE Veneers (containing the SG instruction) after the code, in - * a separate 32 bytes aligned region so that the SAU can programmed to just - * set this region as Non-Secure Callable. The maximum size of this - * executable region makes it only used the space left over by the ER_CODE - * region so that you can rely on code+veneer size combined will not exceed - * the S_CODE_SIZE value. We also substract from the available space the - * area used to align this section on 32 bytes boundary (for SAU conf). - */ - ER_CODE_CMSE_VENEER +0 ALIGN 32 { - *(Veneer$$CMSE) - } - /* - * This dummy region ensures that the next one will be aligned on a 32 bytes - * boundary, so that the following region will not be mistakenly configured - * as Non-Secure Callable by the SAU. - */ - ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {} - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - CODE_WATERMARK +0 EMPTY 0x0 { - } - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) - - ER_DATA S_DATA_START { - .ANY (+ZI +RW) - } - - #if HEAP_SIZE > 0 - ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap - } - #endif - - ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack - } - - /* This empty, zero long execution region is here to mark the limit address - * of the last execution region that is allocated in SRAM. - */ - SRAM_WATERMARK +0 EMPTY 0x0 { - } - /* Make sure that the sections allocated in the SRAM does not exceed the - * size of the SRAM available. - */ - ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) -} diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/platform_base_address.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/platform_base_address.h deleted file mode 100644 index c5c3ee7..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/platform_base_address.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 2019-2021 Arm Limited - * - * Licensed under the Apache License Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing software - * distributed under the License is distributed on an "AS IS" BASIS - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - * \file platform_base_address.h - * \brief This file defines all the peripheral base addresses for MPS3 SSE-300 + - * Ethos-U55 AN547 platform. - */ - -#ifndef __PLATFORM_BASE_ADDRESS_H__ -#define __PLATFORM_BASE_ADDRESS_H__ - -/* ======= Defines peripherals memory map addresses ======= */ -/* Non-secure memory map addresses */ -#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ -#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */ -#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */ -#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */ -#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */ -#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */ -#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */ -#define ISRAM1_BASE_NS 0x21200000 /* Internal SRAM Area Non-Secure base address */ -#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ -#define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ -#define SSE300_NSACFG_BASE_NS 0x40080000 /* SSE-300 Non-Secure Access Configuration Register Block Non-Secure base address */ -/* Non-Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_NS 0x41100000 /* GPIO 0 Non-Secure base address */ -#define GPIO1_CMSDK_BASE_NS 0x41101000 /* GPIO 1 Non-Secure base address */ -#define GPIO2_CMSDK_BASE_NS 0x41102000 /* GPIO 2 Non-Secure base address */ -#define GPIO3_CMSDK_BASE_NS 0x41103000 /* GPIO 3 Non-Secure base address */ -#define AHB_USER_0_BASE_NS 0x41104000 /* AHB USER 0 Non-Secure base address */ -#define AHB_USER_1_BASE_NS 0x41105000 /* AHB USER 1 Non-Secure base address */ -#define AHB_USER_2_BASE_NS 0x41106000 /* AHB USER 2 Non-Secure base address */ -#define AHB_USER_3_BASE_NS 0x41107000 /* AHB USER 3 Non-Secure base address */ -#define DMA_0_BASE_NS 0x41200000 /* DMA 0 Non-Secure base address */ -#define DMA_1_BASE_NS 0x41201000 /* DMA 1 Non-Secure base address */ -#define DMA_2_BASE_NS 0x41202000 /* DMA 2 Non-Secure base address */ -#define DMA_3_BASE_NS 0x41203000 /* DMA 3 Non-Secure base address */ -#define ETHERNET_BASE_NS 0x41400000 /* Ethernet Non-Secure base address */ -#define USB_BASE_NS 0x41500000 /* USB Non-Secure base address */ -#define USER_APB0_BASE_NS 0x41700000 /* User APB 0 Non-Secure base address */ -#define USER_APB1_BASE_NS 0x41701000 /* User APB 1 Non-Secure base address */ -#define USER_APB2_BASE_NS 0x41702000 /* User APB 2 Non-Secure base address */ -#define USER_APB3_BASE_NS 0x41703000 /* User APB 3 Non-Secure base address */ -#define QSPI_CONFIG_BASE_NS 0x41800000 /* QSPI Config Non-Secure base address */ -#define QSPI_WRITE_BASE_NS 0x41801000 /* QSPI Write Non-Secure base address */ -/* Non-Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ -#define SSE300_SYSINFO_BASE_NS 0x48020000 /* SSE-300 System info Block Non-Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ -#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */ -/* Non-Secure MSTEXPPIHL Peripheral region */ -#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */ -#define U55_TIMING_ADAPTER_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter registers Non-Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */ -#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_NS 0x49203000 /* FPGA - PL022 (SPI Shield0) Non-Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_NS 0x49204000 /* FPGA - PL022 (SPI Shield1) Non-Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_NS 0x49205000 /* SBCon (I2C - Shield0) Non-Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_NS 0x49206000 /* SBCon (I2C – Shield1) Non-Secure base address */ -#define USER_APB_BASE_NS 0x49207000 /* USER APB Non-Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_NS 0x49208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Non-Secure base address */ -#define FPGA_SCC_BASE_NS 0x49300000 /* FPGA - SCC registers Non-Secure base address */ -#define FPGA_I2S_BASE_NS 0x49301000 /* FPGA - I2S (Audio) Non-Secure base address */ -#define FPGA_IO_BASE_NS 0x49302000 /* FPGA - IO (System Ctrl + I/O) Non-Secure base address */ -#define UART0_BASE_NS 0x49303000 /* UART 0 Non-Secure base address */ -#define UART1_BASE_NS 0x49304000 /* UART 1 Non-Secure base address */ -#define UART2_BASE_NS 0x49305000 /* UART 2 Non-Secure base address */ -#define UART3_BASE_NS 0x49306000 /* UART 3 Non-Secure base address */ -#define UART4_BASE_NS 0x49307000 /* UART 4 Non-Secure base address */ -#define UART5_BASE_NS 0x49308000 /* UART 5 Non-Secure base address */ -#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */ -#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */ -#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */ -#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */ -#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */ -#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */ - -/* Secure memory map addresses */ -#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ -#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */ -#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */ -#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */ -#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */ -#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */ -#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */ -#define ISRAM1_BASE_S 0x31200000 /* Internal SRAM Area Secure base address */ -#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */ -/* Secure Subsystem peripheral region */ -#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ -#define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ -#define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ -#define SSE300_SACFG_BASE_S 0x50080000 /* SSE-300 Secure Access Configuration Register Secure base address */ -#define MPC_ISRAM0_BASE_S 0x50083000 /* Internal SRAM0 Memory Protection Controller Secure base address */ -#define MPC_ISRAM1_BASE_S 0x50084000 /* Internal SRAM1 Memory Protection Controller Secure base address */ -/* Secure MSTEXPPILL Peripheral region */ -#define GPIO0_CMSDK_BASE_S 0x51100000 /* GPIO 0 Secure base address */ -#define GPIO1_CMSDK_BASE_S 0x51101000 /* GPIO 1 Secure base address */ -#define GPIO2_CMSDK_BASE_S 0x51102000 /* GPIO 2 Secure base address */ -#define GPIO3_CMSDK_BASE_S 0x51103000 /* GPIO 3 Secure base address */ -#define AHB_USER_0_BASE_S 0x51104000 /* AHB USER 0 Secure base address */ -#define AHB_USER_1_BASE_S 0x51105000 /* AHB USER 1 Secure base address */ -#define AHB_USER_2_BASE_S 0x51106000 /* AHB USER 2 Secure base address */ -#define AHB_USER_3_BASE_S 0x51107000 /* AHB USER 3 Secure base address */ -#define DMA_0_BASE_S 0x51200000 /* DMA 0 Secure base address */ -#define DMA_1_BASE_S 0x51201000 /* DMA 1 Secure base address */ -#define DMA_2_BASE_S 0x51202000 /* DMA 2 Secure base address */ -#define DMA_3_BASE_S 0x51203000 /* DMA 3 Secure base address */ -#define ETHERNET_BASE_S 0x51400000 /* Ethernet Secure base address */ -#define USB_BASE_S 0x51500000 /* USB Secure base address */ -#define USER_APB0_BASE_S 0x51700000 /* User APB 0 Secure base address */ -#define USER_APB1_BASE_S 0x51701000 /* User APB 1 Secure base address */ -#define USER_APB2_BASE_S 0x51702000 /* User APB 2 Secure base address */ -#define USER_APB3_BASE_S 0x51703000 /* User APB 3 Secure base address */ -#define QSPI_CONFIG_BASE_S 0x51800000 /* QSPI Config Secure base address */ -#define QSPI_WRITE_BASE_S 0x51801000 /* QSPI Write Secure base address */ -#define MPC_SRAM_BASE_S 0x57000000 /* SRAM Memory Protection Controller Secure base address */ -#define MPC_QSPI_BASE_S 0x57001000 /* QSPI Memory Protection Controller Secure base address */ -#define MPC_DDR4_BASE_S 0x57002000 /* DDR4 Memory Protection Controller Secure base address */ -/* Secure Subsystem peripheral region */ -#define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ -#define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ -#define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 0 Secure base address */ -#define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 1 Secure base address */ -#define SSE300_SYSINFO_BASE_S 0x58020000 /* SSE-300 System info Block Secure base address */ -#define SSE300_SYSCTRL_BASE_S 0x58021000 /* SSE-300 System control Block Secure base address */ -#define SSE300_SYSPPU_BASE_S 0x58022000 /* SSE-300 System Power Policy Unit Secure base address */ -#define SSE300_CPU0PPU_BASE_S 0x58023000 /* SSE-300 CPU 0 Power Policy Unit Secure base address */ -#define SSE300_MGMTPPU_BASE_S 0x58028000 /* SSE-300 Management Power Policy Unit Secure base address */ -#define SSE300_DBGPPU_BASE_S 0x58029000 /* SSE-300 Debug Power Policy Unit Secure base address */ -#define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ -#define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ -#define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ -#define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ -#define SYSCNTR_CNTRL_BASE_S 0x58100000 /* System Counter Control Secure base address */ -#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */ -/* Secure MSTEXPPIHL Peripheral region */ -#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */ -#define U55_TIMING_ADAPTER_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter registers Secure base address */ -#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */ -#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */ -#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */ -#define FPGA_SPI_SHIELD0_BASE_S 0x59203000 /* FPGA - PL022 (SPI Shield0) Secure base address */ -#define FPGA_SPI_SHIELD1_BASE_S 0x59204000 /* FPGA - PL022 (SPI Shield1) Secure base address */ -#define SBCon_I2C_SHIELD0_BASE_S 0x59205000 /* SBCon (I2C - Shield0) Secure base address */ -#define SBCon_I2C_SHIELD1_BASE_S 0x59206000 /* SBCon (I2C – Shield1) Secure base address */ -#define USER_APB_BASE_S 0x59207000 /* USER APB Secure base address */ -#define FPGA_DDR4_EEPROM_BASE_S 0x59208000 /* FPGA - SBCon I2C (DDR4 EEPROM) Secure base address */ -#define FPGA_SCC_BASE_S 0x59300000 /* FPGA - SCC registers Secure base address */ -#define FPGA_I2S_BASE_S 0x59301000 /* FPGA - I2S (Audio) Secure base address */ -#define FPGA_IO_BASE_S 0x59302000 /* FPGA - IO (System Ctrl + I/O) Secure base address */ -#define UART0_BASE_S 0x59303000 /* UART 0 Secure base address */ -#define UART1_BASE_S 0x59304000 /* UART 1 Secure base address */ -#define UART2_BASE_S 0x59305000 /* UART 2 Secure base address */ -#define UART3_BASE_S 0x59306000 /* UART 3 Secure base address */ -#define UART4_BASE_S 0x59307000 /* UART 4 Secure base address */ -#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */ -#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */ -#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */ -#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */ -#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */ -#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */ -#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */ - -/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ -#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller - * Access from Non-secure software is only allowed - * if AIRCR.BFHFNMINS is set to 1 */ - -/* Memory size definitions */ -#define ITCM_SIZE (0x00080000) /* 512 kB */ -#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */ -#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */ -#define SRAM_SIZE (0x00200000) /* 2 MB */ -#define ISRAM0_SIZE (0x00200000) /* 2 MB */ -#define ISRAM1_SIZE (0x00200000) /* 2 MB */ -#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */ -#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */ -#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */ - -/* Defines for Driver MPC's */ -/* SRAM -- 2 MB */ -#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS) -#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_NS (0x0) -#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S) -#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1) -#define MPC_SRAM_RANGE_OFFSET_S (0x0) - -/* QSPI -- 8 MB*/ -#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS) -#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_NS (0x0) -#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S) -#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1) -#define MPC_QSPI_RANGE_OFFSET_S (0x0) - -/* ISRAM0 -- 2 MB*/ -#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS) -#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S) -#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1) -#define MPC_ISRAM0_RANGE_OFFSET_S (0x0) - -/* ISRAM1 -- 2 MB*/ -#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS) -#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0) -#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S) -#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1) -#define MPC_ISRAM1_RANGE_OFFSET_S (0x0) - -/* DDR4 -- 2GB (8 * 256 MB) */ -#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0) -#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S) -#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS) -#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S) -#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS) -#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S) -#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS) -#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS) -#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S) -#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1)) -#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS) - -#endif /* __PLATFORM_BASE_ADDRESS_H__ */ diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_defs.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_defs.h deleted file mode 100644 index c8cd919..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_defs.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2016-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_DEFS_H__ -#define __REGION_DEFS_H__ - -#include "region_limits.h" - -/* ************************************************************** - * WARNING: this file is parsed both by the C/C++ compiler - * and the linker. As a result the syntax must be valid not only - * for C/C++ but for the linker scripts too. - * Beware of the following limitations: - * - LD (GCC linker) requires white space around operators. - * - UL postfix for macros is not suported by the linker script - ****************************************************************/ - -/* Secure regions */ -#define S_CODE_START ( S_ROM_ALIAS ) -#define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) -#define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) - -#define S_DATA_START ( S_RAM_ALIAS ) -#define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) -#define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) - -/* Non-Secure regions */ -#define NS_CODE_START ( NS_ROM_ALIAS ) -#define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE ) -#define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE ) - -#define NS_DATA_START ( NS_RAM_ALIAS ) -#define NS_DATA_SIZE ( TOTAL_NS_RAM_SIZE ) -#define NS_DATA_LIMIT ( NS_DATA_START + NS_DATA_SIZE ) - -#endif /* __REGION_DEFS_H__ */ diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_limits.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_limits.h deleted file mode 100644 index 58a76c7..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/region_limits.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2018-2020 Arm Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __REGION_LIMITS_H__ -#define __REGION_LIMITS_H__ - -/* ************************************************************** - * WARNING: this file is parsed both by the C/C++ compiler - * and the linker. As a result the syntax must be valid not only - * for C/C++ but for the linker scripts too. - * Beware of the following limitations: - * - LD (GCC linker) requires white space around operators. - * - UL postfix for macros is not suported by the linker script - ****************************************************************/ - -/* Secure Code */ -#define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ -#define TOTAL_S_ROM_SIZE (0x00080000) /* 256 kB */ - -/* Secure Data */ -#define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ -#define TOTAL_S_RAM_SIZE (0x00040000) /* 256 kB */ - - -/* Non-Secure Code */ -#define NS_ROM_ALIAS (0x01000000) /* SRAM_BASE_NS */ -#define TOTAL_NS_ROM_SIZE (0x00080000) /* 256 kB */ - -/* Non-Secure Data */ -#define NS_RAM_ALIAS (0x21000000) /* ISRAM0_BASE_NS */ -#define TOTAL_NS_RAM_SIZE (0x00040000) /* 256 kB */ - - -/* Heap and Stack sizes for secure and nonsecure applications */ -#define HEAP_SIZE (0x0000C000) /* 1 KiB */ -#define STACK_SIZE (0x00008000) /* 1 KiB */ - -#endif /* __REGION_LIMITS_H__ */ diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c deleted file mode 100644 index 53e367c..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Device/SSE-300-MPS3/startup_fvp_sse300_mps3.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c - * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b - */ - -#include "cmsis.h" - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler Function Prototype - *----------------------------------------------------------------------------*/ -typedef void( *pFunc )( void ); - -/*---------------------------------------------------------------------------- - External References - *----------------------------------------------------------------------------*/ -extern uint32_t __INITIAL_SP; -extern uint32_t __STACK_LIMIT; - -extern void __PROGRAM_START(void) __NO_RETURN; - -/*---------------------------------------------------------------------------- - Internal References - *----------------------------------------------------------------------------*/ -void Reset_Handler (void) __NO_RETURN; - -/*---------------------------------------------------------------------------- - Exception / Interrupt Handler - *----------------------------------------------------------------------------*/ -#define DEFAULT_IRQ_HANDLER(handler_name) \ -void __WEAK handler_name(void); \ -void handler_name(void) { \ - while(1); \ -} - -/* Exceptions */ -DEFAULT_IRQ_HANDLER(NMI_Handler) -DEFAULT_IRQ_HANDLER(HardFault_Handler) -DEFAULT_IRQ_HANDLER(MemManage_Handler) -DEFAULT_IRQ_HANDLER(BusFault_Handler) -DEFAULT_IRQ_HANDLER(UsageFault_Handler) -DEFAULT_IRQ_HANDLER(SecureFault_Handler) -DEFAULT_IRQ_HANDLER(SVC_Handler) -DEFAULT_IRQ_HANDLER(DebugMon_Handler) -DEFAULT_IRQ_HANDLER(PendSV_Handler) -DEFAULT_IRQ_HANDLER(SysTick_Handler) - -DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler) -DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) -DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) -DEFAULT_IRQ_HANDLER(TIMER0_Handler) -DEFAULT_IRQ_HANDLER(TIMER1_Handler) -DEFAULT_IRQ_HANDLER(TIMER2_Handler) -DEFAULT_IRQ_HANDLER(MPC_Handler) -DEFAULT_IRQ_HANDLER(PPC_Handler) -DEFAULT_IRQ_HANDLER(MSC_Handler) -DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) -DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) -DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) -DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) -DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) -DEFAULT_IRQ_HANDLER(TIMER3_Handler) -DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler) -DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler) - -DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) -DEFAULT_IRQ_HANDLER(UARTRX0_Handler) -DEFAULT_IRQ_HANDLER(UARTTX0_Handler) -DEFAULT_IRQ_HANDLER(UARTRX1_Handler) -DEFAULT_IRQ_HANDLER(UARTTX1_Handler) -DEFAULT_IRQ_HANDLER(UARTRX2_Handler) -DEFAULT_IRQ_HANDLER(UARTTX2_Handler) -DEFAULT_IRQ_HANDLER(UARTRX3_Handler) -DEFAULT_IRQ_HANDLER(UARTTX3_Handler) -DEFAULT_IRQ_HANDLER(UARTRX4_Handler) -DEFAULT_IRQ_HANDLER(UARTTX4_Handler) -DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) -DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) -DEFAULT_IRQ_HANDLER(UARTOVF_Handler) -DEFAULT_IRQ_HANDLER(ETHERNET_Handler) -DEFAULT_IRQ_HANDLER(I2S_Handler) -DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) -DEFAULT_IRQ_HANDLER(USB_Handler) -DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) -DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) -DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) -DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) -DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) -DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) -DEFAULT_IRQ_HANDLER(UARTRX5_Handler) -DEFAULT_IRQ_HANDLER(UARTTX5_Handler) -DEFAULT_IRQ_HANDLER(UART5_Handler) - -/*---------------------------------------------------------------------------- - Exception / Interrupt Vector table - *----------------------------------------------------------------------------*/ - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wpedantic" -#endif - -extern const pFunc __VECTOR_TABLE[496]; - const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = { - (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* -14: NMI Handler */ - HardFault_Handler, /* -13: Hard Fault Handler */ - MemManage_Handler, /* -12: MPU Fault Handler */ - BusFault_Handler, /* -11: Bus Fault Handler */ - UsageFault_Handler, /* -10: Usage Fault Handler */ - SecureFault_Handler, /* -9: Secure Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* -5: SVCall Handler */ - DebugMon_Handler, /* -4: Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* -2: PendSV Handler */ - SysTick_Handler, /* -1: SysTick Handler */ - - NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */ - NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ - SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ - TIMER0_Handler, /* 3: TIMER 0 Handler */ - TIMER1_Handler, /* 4: TIMER 1 Handler */ - TIMER2_Handler, /* 5: TIMER 2 Handler */ - 0, /* 6: Reserved */ - 0, /* 7: Reserved */ - 0, /* 8: Reserved */ - MPC_Handler, /* 9: MPC Combined (Secure) Handler */ - PPC_Handler, /* 10: PPC Combined (Secure) Handler */ - MSC_Handler, /* 11: MSC Combined (Secure) Handler */ - BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ - 0, /* 13: Reserved */ - MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ - SYS_PPU_Handler, /* 15: SYS PPU Handler */ - CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ - 0, /* 17: Reserved */ - 0, /* 18: Reserved */ - 0, /* 19: Reserved */ - 0, /* 20: Reserved */ - 0, /* 21: Reserved */ - 0, /* 22: Reserved */ - 0, /* 23: Reserved */ - 0, /* 24: Reserved */ - 0, /* 25: Reserved */ - DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ - TIMER3_Handler, /* 27: TIMER 3 Handler */ - CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */ - CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */ - 0, /* 30: Reserved */ - 0, /* 31: Reserved */ - - /* External interrupts */ - System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ - UARTRX0_Handler, /* 33: UART 0 RX Handler */ - UARTTX0_Handler, /* 34: UART 0 TX Handler */ - UARTRX1_Handler, /* 35: UART 1 RX Handler */ - UARTTX1_Handler, /* 36: UART 1 TX Handler */ - UARTRX2_Handler, /* 37: UART 2 RX Handler */ - UARTTX2_Handler, /* 38: UART 2 TX Handler */ - UARTRX3_Handler, /* 39: UART 3 RX Handler */ - UARTTX3_Handler, /* 40: UART 3 TX Handler */ - UARTRX4_Handler, /* 41: UART 4 RX Handler */ - UARTTX4_Handler, /* 42: UART 4 TX Handler */ - UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ - UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ - UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ - UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ - UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ - UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ - ETHERNET_Handler, /* 49: Ethernet Handler */ - I2S_Handler, /* 50: Audio I2S Handler */ - TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ - USB_Handler, /* 52: USB Handler */ - SPI_ADC_Handler, /* 53: SPI ADC Handler */ - SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ - SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ - ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ - 0, /* 57: Reserved */ - 0, /* 58: Reserved */ - 0, /* 59: Reserved */ - 0, /* 60: Reserved */ - 0, /* 61: Reserved */ - 0, /* 62: Reserved */ - 0, /* 63: Reserved */ - 0, /* 64: Reserved */ - 0, /* 65: Reserved */ - 0, /* 66: Reserved */ - 0, /* 67: Reserved */ - 0, /* 68: Reserved */ - GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ - GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ - GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ - GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ - GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ - GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ - GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ - GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ - GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ - GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ - GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ - GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ - GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ - GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ - GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ - GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ - GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ - GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ - GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ - GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ - GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ - GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ - GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ - GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ - GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ - GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ - GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ - GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ - GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ - GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ - GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ - GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ - GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ - GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ - GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ - GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ - GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ - GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ - GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ - GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ - GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ - GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ - GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ - GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ - GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ - GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ - GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ - GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ - GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ - GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ - GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ - GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ - GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ - GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ - GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ - GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ - UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ - UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ - UART5_Handler, /* 127: UART 5 combined Interrupt */ - 0, /* 128: Reserved */ - 0, /* 129: Reserved */ - 0, /* 130: Reserved */ -}; - -#if defined ( __GNUC__ ) -#pragma GCC diagnostic pop -#endif - -/*---------------------------------------------------------------------------- - Reset Handler called on controller reset - *----------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); - - SystemInit(); /* CMSIS System Initialization */ - __PROGRAM_START(); /* Enter PreMain (C library entry point) */ -} diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/debug_log.cc b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/debug_log.cc deleted file mode 100644 index bc79d43..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/debug_log.cc +++ /dev/null @@ -1,43 +0,0 @@ -/* Copyright 2020 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -// Implementation for the DebugLog() function that prints to the debug logger on -// an generic Cortex-M device. - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -#include "tensorflow/lite/micro/debug_log.h" - -#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" - -static DebugLogCallback debug_log_callback = nullptr; - -void RegisterDebugLogCallback(void (*cb)(const char* s)) { - debug_log_callback = cb; -} - -void DebugLog(const char* s) { -#ifndef TF_LITE_STRIP_ERROR_STRINGS - if (debug_log_callback != nullptr) { - debug_log_callback(s); - } -#endif -} - -#ifdef __cplusplus -} // extern "C" -#endif // __cplusplus diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/micro_time.cc b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/micro_time.cc deleted file mode 100644 index 023ac6d..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/micro_time.cc +++ /dev/null @@ -1,67 +0,0 @@ -/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -#include "tensorflow/lite/micro/micro_time.h" - -// DWT (Data Watchpoint and Trace) registers, only exists on ARM Cortex with a -// DWT unit. -#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) -/*!< DWT Control register */ - -// DWT Control register. -#define KIN1_DWT_CYCCNTENA_BIT (1UL << 0) - -// CYCCNTENA bit in DWT_CONTROL register. -#define KIN1_DWT_CYCCNT (*((volatile uint32_t*)0xE0001004)) - -// DWT Cycle Counter register. -#define KIN1_DEMCR (*((volatile uint32_t*)0xE000EDFC)) - -// DEMCR: Debug Exception and Monitor Control Register. -#define KIN1_TRCENA_BIT (1UL << 24) - -#define KIN1_LAR (*((volatile uint32_t*)0xE0001FB0)) - -#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000)) - -// Unlock access to DWT (ITM, etc.)registers. -#define KIN1_UnlockAccessToDWT() KIN1_LAR = 0xC5ACCE55; - -// TRCENA: Enable trace and debug block DEMCR (Debug Exception and Monitor -// Control Register. -#define KIN1_InitCycleCounter() KIN1_DEMCR |= KIN1_TRCENA_BIT - -#define KIN1_ResetCycleCounter() KIN1_DWT_CYCCNT = 0 -#define KIN1_EnableCycleCounter() KIN1_DWT_CONTROL |= KIN1_DWT_CYCCNTENA_BIT -#define KIN1_DisableCycleCounter() KIN1_DWT_CONTROL &= ~KIN1_DWT_CYCCNTENA_BIT -#define KIN1_GetCycleCounter() KIN1_DWT_CYCCNT - -namespace tflite { - -int32_t ticks_per_second() { return 0; } - -int32_t GetCurrentTimeTicks() { - static bool is_initialized = false; - if (!is_initialized) { - KIN1_UnlockAccessToDWT(); - KIN1_InitCycleCounter(); - KIN1_ResetCycleCounter(); - KIN1_EnableCycleCounter(); - is_initialized = true; - } - return KIN1_GetCycleCounter(); -} - -} // namespace tflite diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/system_setup.cc b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/system_setup.cc deleted file mode 100644 index df6cfc6..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/Machine_Learning/system_setup.cc +++ /dev/null @@ -1,36 +0,0 @@ -/* Copyright 2021 The TensorFlow Authors. All Rights Reserved. - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -==============================================================================*/ - -#include "tensorflow/lite/micro/system_setup.h" -#include "stdio.h" -#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h" - -extern "C" void stdio_init (void); - -namespace tflite { - -void debug_log_printf(const char* s) { - printf("%s", s); -} - -// To add an equivalent function for your own platform, create your own -// implementation file, and place it in a subfolder named after the target. See -// tensorflow/lite/micro/debug_log.cc for a similar example. -void InitializeTarget() { - stdio_init(); - RegisterDebugLogCallback(debug_log_printf); - //debug_log_printf("Initialized UART and registered Callback.") -} -} // namespace tflite diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/Pre_Include_Global.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/Pre_Include_Global.h deleted file mode 100644 index 6234fa2..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/Pre_Include_Global.h +++ /dev/null @@ -1,18 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'template_Corstone300' - * Target: 'template_Corstone300' - */ - -#ifndef PRE_INCLUDE_GLOBAL_H -#define PRE_INCLUDE_GLOBAL_H - -/* tensorflow::Machine Learning:TensorFlow:Kernel:CMSIS-NN:0.1.20210416 */ -// enabling global pre includes - #define TF_LITE_STATIC_MEMORY 1 - - -#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/RTE_Components.h b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/RTE_Components.h deleted file mode 100644 index 452f25e..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/_template_Corstone300/RTE_Components.h +++ /dev/null @@ -1,35 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Configuration File - * *** Do not modify ! *** - * - * Project: 'template_Corstone300' - * Target: 'template_Corstone300' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - - -/* - * Define the Device Header File: - */ -#define CMSIS_device_header "SSE300MPS3.h" - -/* ARM::CMSIS Driver:USART:1.0.0 */ -#define RTE_Drivers_USART -/* tensorflow::Data Exchange:Serialization:flatbuffers:tensorflow:1.12.0 */ -#define RTE_DataExchange_Serialization_flatbuffers /* flatbuffers */ -/* tensorflow::Data Processing:Math:gemmlowp fixed-point:tensorflow:1.0.0 */ -#define RTE_DataExchange_Math_gemmlowp /* gemmlowp */ -/* tensorflow::Data Processing:Math:kissfft:tensorflow:1.4.5 */ -#define RTE_DataExchange_Math_kissfft /* kissfft */ -/* tensorflow::Data Processing:Math:ruy:tensorflow:1.12.0 */ -#define RTE_DataProcessing_Math_ruy /* ruy */ -/* tensorflow::Machine Learning:TensorFlow:Kernel:CMSIS-NN:0.1.20210416 */ -#define RTE_ML_TF_LITE /* TF */ -/* tensorflow::Machine Learning:TensorFlow:Testing:0.1.20210416 */ -#define RTE_ML_TF_LITE /* TF */ - - -#endif /* RTE_COMPONENTS_H */ diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/retarget_stdio.c b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/retarget_stdio.c deleted file mode 100644 index a5a59c0..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/RTE/retarget_stdio.c +++ /dev/null @@ -1,53 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (c) 2020 Arm Limited (or its affiliates). All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * -------------------------------------------------------------------------- */ - -#include -#include -#include "device_cfg.h" -#include "Driver_USART.h" - -extern ARM_DRIVER_USART Driver_USART0; - -void stdio_init (void) { - Driver_USART0.Initialize(NULL); - Driver_USART0.Control(ARM_USART_MODE_ASYNCHRONOUS, 115200U); -} - -/** - Put a character to the stdout - - \param[in] ch Character to output - \return The character written, or -1 on write error. -*/ -int stdout_putchar (int ch) { - int32_t ret; - -#ifdef __UVISION_VERSION - // Windows Telnet expects CR-LF line endings - // add carriage return before each line feed - if (ch=='\n') { - int cr = '\r'; - Driver_USART0.Send(&cr, 1U); - } -#endif - - if (Driver_USART0.Send(&ch, 1U) == ARM_DRIVER_OK) { - return ch; - } - return EOF; -} diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/SSE-300-MPS3.cprj b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/SSE-300-MPS3.cprj deleted file mode 100644 index 4fbf9f6..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/SSE-300-MPS3.cprj +++ /dev/null @@ -1,80 +0,0 @@ - - - - - UnitTestTemplate - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _file_block_xml_ - - - - diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/packlist b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/packlist deleted file mode 100644 index c9c5636..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/packlist +++ /dev/null @@ -1 +0,0 @@ -https://keilpack.azureedge.net/pack/ARM.V2M_MPS3_SSE_300_BSP.1.1.0.pack diff --git a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/platform_setup.c b/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/platform_setup.c deleted file mode 100644 index 279de43..0000000 --- a/tensorflow-test/templates/Reference/ARMCLANG/SSE-300-MPS3/platform_setup.c +++ /dev/null @@ -1,10 +0,0 @@ - - -int platform_setup (void) -{ - serial_init(); - - -} - - diff --git a/tensorflow-test/vht/packs/packinstall.sh b/tensorflow-test/vht/packs/packinstall.sh deleted file mode 100644 index 5d4905f..0000000 --- a/tensorflow-test/vht/packs/packinstall.sh +++ /dev/null @@ -1,11 +0,0 @@ - #!/bin/sh - -find $(pwd) -type f -name "*.pack" > packlist -cat packlist -#sed -i 's/^/file:\/\//' packlist -#cat packlist -cpackget pack add -f packlist -a -cpackget pack add https://www.keil.com/pack/ARM.CMSIS.5.8.0.pack -a -cpackget pack add https://keilpack.azureedge.net/pack/ARM.V2M_MPS3_SSE_300_BSP.1.2.0.pack -a - - diff --git a/tensorflow-test/vht/vht.yml b/tensorflow-test/vht/vht.yml deleted file mode 100644 index 7287c19..0000000 --- a/tensorflow-test/vht/vht.yml +++ /dev/null @@ -1,662 +0,0 @@ -suite: - name: "tensorflow-kernel-tests-reference" - model: "VHT-Corstone-300" - configuration: "" - working_dir: "/home/ubuntu/vhtwork" - pre: "git clone https://github.com/tensorflow/tflite-micro.git && mv ./tflite-micro/tensorflow/ . && chmod +x install_cmsis_toolbox.sh && ./install_cmsis_toolbox.sh && chmod +x ./packs/packinstall.sh && cd ./packs && ./packinstall.sh" - post: "" - - builds: - - "testing_helpers_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/testing_helpers_test.cprj" - pre: "" - post: "" - - "add_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/add_test.cprj" - pre: "" - post: "" - - "add_n_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/add_n_test.cprj" - pre: "" - post: "" - - "arg_min_max_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/arg_min_max_test.cprj" - pre: "" - post: "" - - "batch_to_space_nd_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/batch_to_space_nd_test.cprj" - pre: "" - post: "" - - "cast_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/cast_test.cprj" - pre: "" - post: "" - - "ceil_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/ceil_test.cprj" - pre: "" - post: "" - - "circular_buffer_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/circular_buffer_test.cprj" - pre: "" - post: "" - - "comparisons_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/comparisons_test.cprj" - pre: "" - post: "" - - "concatenation_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/concatenation_test.cprj" - pre: "" - post: "" -# - "conv_test": -# shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/conv_test.cprj" -# pre: "" -# post: "" - - "cumsum_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/cumsum_test.cprj" - pre: "" - post: "" - - "depth_to_space_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/depth_to_space_test.cprj" - pre: "" - post: "" - - "depthwise_conv_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/depthwise_conv_test.cprj" - pre: "" - post: "" - - "dequantize_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/dequantize_test.cprj" - pre: "" - post: "" - - "detection_postprocess_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/detection_postprocess_test.cprj" - pre: "" - post: "" - - "elementwise_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/elementwise_test.cprj" - pre: "" - post: "" - - "elu_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/elu_test.cprj" - pre: "" - post: "" - - "exp_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/exp_test.cprj" - pre: "" - post: "" - - "expand_dims_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/expand_dims_test.cprj" - pre: "" - post: "" - - "fill_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/fill_test.cprj" - pre: "" - post: "" - - "floor_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/floor_test.cprj" - pre: "" - post: "" - - "floor_div_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/floor_div_test.cprj" - pre: "" - post: "" - - "floor_mod_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/floor_mod_test.cprj" - pre: "" - post: "" - - "fully_connected_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/fully_connected_test.cprj" - pre: "" - post: "" - - "gather_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/gather_test.cprj" - pre: "" - post: "" - - "gather_nd_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/gather_nd_test.cprj" - pre: "" - post: "" - - "hard_swish_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/hard_swish_test.cprj" - pre: "" - post: "" - - "l2norm_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/l2norm_test.cprj" - pre: "" - post: "" - - "l2_pool_2d_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/l2_pool_2d_test.cprj" - pre: "" - post: "" - - "leaky_relu_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/leaky_relu_test.cprj" - pre: "" - post: "" - - "logical_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/logical_test.cprj" - pre: "" - post: "" - - "logistic_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/logistic_test.cprj" - pre: "" - post: "" - - "log_softmax_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/log_softmax_test.cprj" - pre: "" - post: "" - - "maximum_minimum_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/maximum_minimum_test.cprj" - pre: "" - post: "" - - "mul_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/mul_test.cprj" - pre: "" - post: "" - - "neg_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/neg_test.cprj" - pre: "" - post: "" - - "pack_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/pack_test.cprj" - pre: "" - post: "" - - "pad_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/pad_test.cprj" - pre: "" - post: "" - - "pooling_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/pooling_test.cprj" - pre: "" - post: "" - - "prelu_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/prelu_test.cprj" - pre: "" - post: "" - - "quantization_util_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/quantization_util_test.cprj" - pre: "" - post: "" - - "quantize_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/quantize_test.cprj" - pre: "" - post: "" - - "reduce_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/reduce_test.cprj" - pre: "" - post: "" - - "reshape_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/reshape_test.cprj" - pre: "" - post: "" - - "resize_bilinear_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/resize_bilinear_test.cprj" - pre: "" - post: "" - - "resize_nearest_neighbor_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/resize_nearest_neighbor_test.cprj" - pre: "" - post: "" - - "round_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/round_test.cprj" - pre: "" - post: "" - - "shape_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/shape_test.cprj" - pre: "" - post: "" - - "softmax_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/softmax_test.cprj" - pre: "" - post: "" - - "space_to_batch_nd_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/space_to_batch_nd_test.cprj" - pre: "" - post: "" - - "space_to_depth_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/space_to_depth_test.cprj" - pre: "" - post: "" - - "split_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/split_test.cprj" - pre: "" - post: "" - - "split_v_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/split_v_test.cprj" - pre: "" - post: "" - - "squeeze_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/squeeze_test.cprj" - pre: "" - post: "" - - "strided_slice_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/strided_slice_test.cprj" - pre: "" - post: "" - - "sub_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/sub_test.cprj" - pre: "" - post: "" - - "svdf_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/svdf_test.cprj" - pre: "" - post: "" - - "tanh_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/tanh_test.cprj" - pre: "" - post: "" - - "transpose_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/transpose_test.cprj" - pre: "" - post: "" - - "transpose_conv_test": - shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/transpose_conv_test.cprj" - pre: "" - post: "" - #- "unpack_test": - # shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/unpack_test.cprj" - # pre: "" - # post: "" - #- "zeros_like_test": - # shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/zeros_like_test.cprj" - # pre: "" - # post: "" - #- "greedy_memory_planner_test": - # shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/greedy_memory_planner_test.cprj" - # pre: "" - # post: "" - #- "linear_memory_planner_te": - # shell: "cbuild.sh ./Reference/ARMCLANG/SSE-300-MPS3/linear_memory_planner_te.cprj" - # pre: "" - # post: "" - - - tests: - - "testing_helpers_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/testing_helpers_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "add_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/add_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "add_n_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/add_n_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "arg_min_max_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/arg_min_max_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "batch_to_space_nd_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/batch_to_space_nd_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "cast_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/cast_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "ceil_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/ceil_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "circular_buffer_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/circular_buffer_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "comparisons_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/comparisons_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "concatenation_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/concatenation_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - # - "conv_test": - # executable: "./Reference/ARMCLANG/SSE-300-MPS3/conv_test.axf" - # arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - # pre: "" - # post: "" - # timeout: "" - - "cumsum_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/cumsum_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "depth_to_space_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/depth_to_space_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "depthwise_conv_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/depthwise_conv_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "dequantize_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/dequantize_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "detection_postprocess_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/detection_postprocess_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "elementwise_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/elementwise_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "elu_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/elu_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "exp_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/exp_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "expand_dims_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/expand_dims_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "fill_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/fill_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "floor_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/floor_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "floor_div_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/floor_div_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "floor_mod_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/floor_mod_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "fully_connected_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/fully_connected_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "gather_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/gather_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "gather_nd_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/gather_nd_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "hard_swish_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/hard_swish_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "l2norm_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/l2norm_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "l2_pool_2d_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/l2_pool_2d_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "leaky_relu_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/leaky_relu_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "logical_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/logical_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "logistic_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/logistic_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "log_softmax_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/log_softmax_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "maximum_minimum_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/maximum_minimum_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "mul_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/mul_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "neg_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/neg_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "pack_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/pack_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "pad_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/pad_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "pooling_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/pooling_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "prelu_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/prelu_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "quantization_util_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/quantization_util_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "quantize_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/quantize_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "reduce_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/reduce_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "reshape_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/reshape_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "resize_bilinear_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/resize_bilinear_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "resize_nearest_neighbor_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/resize_nearest_neighbor_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "round_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/round_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "shape_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/shape_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "softmax_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/softmax_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "space_to_batch_nd_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/space_to_batch_nd_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "space_to_depth_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/space_to_depth_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "split_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/split_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "split_v_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/split_v_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "squeeze_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/squeeze_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "strided_slice_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/strided_slice_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "sub_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/sub_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "svdf_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/svdf_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "tanh_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/tanh_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "transpose_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/transpose_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "transpose_conv_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/transpose_conv_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "unpack_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/unpack_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - - "zeros_like_test": - executable: "./Reference/ARMCLANG/SSE-300-MPS3/zeros_like_test.axf" - arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - pre: "" - post: "" - timeout: "" - # - "greedy_memory_planner_test": - # executable: "./Reference/ARMCLANG/SSE-300-MPS3/greedy_memory_planner_test.axf" - # arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - # pre: "" - # post: "" - # timeout: "" - # - "linear_memory_planner_te": - # executable: "./Reference/ARMCLANG/SSE-300-MPS3/linear_memory_planner_te.axf" - # arguments: "-f ./vht_config.txt --stat --cyclelimit 768000000" - # pre: "" - # post: "" - # timout: "" diff --git a/tensorflow-test/vht/vht_config.txt b/tensorflow-test/vht/vht_config.txt deleted file mode 100644 index 8470fc1..0000000 --- a/tensorflow-test/vht/vht_config.txt +++ /dev/null @@ -1,18 +0,0 @@ -# Parameters: -# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] -#------------------------------------------------------------------------------ -cpu_core.core_clk.mul=100000000 # (int , init-time) default = '0x17d7840' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA -cpu_core.mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation -cpu_core.mps3_board.DISABLE_GATING=1 # (bool , init-time) default = '0' : Disable Memory gating logic -cpu_core.mps3_board.telnetterminal0.start_port=5000 # (int , init-time) default = '0x1388' : Telnet TCP Port Number -cpu_core.mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected -cpu_core.mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) - -cpu_core.cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. -cpu_core.cpu0.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF] -cpu_core.cpu0.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls -cpu_core.cpu0.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF] -cpu_core.cpu0.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF] -cpu_core.cpu0.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF] -cpu_core.cpu0.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF] -cpu_core.cpu0.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.

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