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parse_opcodes
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#!/usr/bin/env python3
from __future__ import print_function
from builtins import hex
from builtins import range
import math
import sys
import tokenize
from collections import OrderedDict
namelist = []
match = OrderedDict()
mask = OrderedDict()
pseudos = {}
arguments = {}
arglut = {}
arglut['rd'] = (11,7)
arglut['rs1'] = (19,15)
arglut['rs2'] = (24,20)
arglut['rs3'] = (31,27)
arglut['aqrl'] = (26,25)
arglut['fm'] = (31,28)
arglut['pred'] = (27,24)
arglut['succ'] = (23,20)
arglut['rm'] = (14,12)
arglut['funct3'] = (14,12)
arglut['imm20'] = (31,12)
arglut['jimm20'] = (31,12)
arglut['imm12'] = (31,20)
arglut['imm12hi'] = (31,25)
arglut['bimm12hi'] = (31,25)
arglut['imm12lo'] = (11,7)
arglut['bimm12lo'] = (11,7)
arglut['zimm'] = (19,15)
arglut['shamt'] = (25,20)
arglut['shamtw'] = (24,20)
arglut['imm5'] = (24,20)
arglut['imm6'] = (25,20)
# for vectors
arglut['vd'] = (11,7)
arglut['vs3'] = (11,7)
arglut['vs1'] = (19,15)
arglut['vs2'] = (24,20)
arglut['vm'] = (25,25)
arglut['wd'] = (26,26)
arglut['amoop'] = (31,27)
arglut['nf'] = (31,29)
arglut['simm5'] = (19,15)
arglut['zimm11'] = (30,20)
# for custom extensions
arglut['prs3'] = (11,7)
arglut['L'] = (7,7)
arglut['uimms'] = (19,15)
arglut['Luimm5'] = (29,25)
arglut['vseglen'] = (31,29)
arglut['stagger_max'] = (14,12)
arglut['stagger_mask'] = (11,8)
bits_imm12 = [
("imm12lo", 4, 0, 0), # imm12lo[4:0] -> imm[4:0]
("imm12hi", 6, 0, 5), # imm12hi[6:0] -> imm[11:5]
]
bits_bimm12 = [
("bimm12lo", 0, 0, 11), # bimm12lo[0] -> imm[11]
("bimm12lo", 4, 1, 1), # bimm12lo[4:1] -> imm[4:1]
("bimm12hi", 5, 0, 5), # bimm12hi[5:0] -> imm[10:5]
("bimm12hi", 6, 6, 12), # bimm12hi[6] -> imm[12]
]
bits_jimm20 = [
("jimm20", 7, 0, 12), # jimm20[7:0] -> imm[19:12]
("jimm20", 8, 8, 11), # jimm20[8] -> imm[11]
("jimm20", 18, 9, 1), # jimm20[18:9] -> imm[10:1]
("jimm20", 19, 19, 20), # jimm20[19] -> imm[20]
]
bits_imm6 = [
("imm6", 4, 0, 1), # imm6[4:0] -> imm[5:1]
("imm6", 5, 5, 0), # imm6[5] -> imm[0]
]
causes = [
(0x00, 'misaligned fetch'),
(0x01, 'fetch access'),
(0x02, 'illegal instruction'),
(0x03, 'breakpoint'),
(0x04, 'misaligned load'),
(0x05, 'load access'),
(0x06, 'misaligned store'),
(0x07, 'store access'),
(0x08, 'user_ecall'),
(0x09, 'supervisor_ecall'),
(0x0A, 'virtual_supervisor_ecall'),
(0x0B, 'machine_ecall'),
(0x0C, 'fetch page fault'),
(0x0D, 'load page fault'),
(0x0F, 'store page fault'),
(0x14, 'fetch guest page fault'),
(0x15, 'load guest page fault'),
(0x16, 'virtual instruction'),
(0x17, 'store guest page fault'),
]
csrs = [
# Standard User R/W
(0x001, 'fflags'),
(0x002, 'frm'),
(0x003, 'fcsr'),
(0x000, 'ustatus'),
(0x004, 'uie'),
(0x005, 'utvec'),
(0x008, 'vstart'),
(0x009, 'vxsat'),
(0x00A, 'vxrm'),
(0x00F, 'vcsr'),
(0x040, 'uscratch'),
(0x041, 'uepc'),
(0x042, 'ucause'),
(0x043, 'utval'),
(0x044, 'uip'),
# Custom User R/W
(0x800, 'fmode'),
# Standard User RO
(0xC00, 'cycle'),
(0xC01, 'time'),
(0xC02, 'instret'),
(0xC03, 'hpmcounter3'),
(0xC04, 'hpmcounter4'),
(0xC05, 'hpmcounter5'),
(0xC06, 'hpmcounter6'),
(0xC07, 'hpmcounter7'),
(0xC08, 'hpmcounter8'),
(0xC09, 'hpmcounter9'),
(0xC0A, 'hpmcounter10'),
(0xC0B, 'hpmcounter11'),
(0xC0C, 'hpmcounter12'),
(0xC0D, 'hpmcounter13'),
(0xC0E, 'hpmcounter14'),
(0xC0F, 'hpmcounter15'),
(0xC10, 'hpmcounter16'),
(0xC11, 'hpmcounter17'),
(0xC12, 'hpmcounter18'),
(0xC13, 'hpmcounter19'),
(0xC14, 'hpmcounter20'),
(0xC15, 'hpmcounter21'),
(0xC16, 'hpmcounter22'),
(0xC17, 'hpmcounter23'),
(0xC18, 'hpmcounter24'),
(0xC19, 'hpmcounter25'),
(0xC1A, 'hpmcounter26'),
(0xC1B, 'hpmcounter27'),
(0xC1C, 'hpmcounter28'),
(0xC1D, 'hpmcounter29'),
(0xC1E, 'hpmcounter30'),
(0xC1F, 'hpmcounter31'),
(0xC20, 'vl'),
(0xC21, 'vtype'),
(0xC22, 'vlenb'),
# Standard Supervisor R/W
(0x100, 'sstatus'),
(0x102, 'sedeleg'),
(0x103, 'sideleg'),
(0x104, 'sie'),
(0x105, 'stvec'),
(0x106, 'scounteren'),
(0x140, 'sscratch'),
(0x141, 'sepc'),
(0x142, 'scause'),
(0x143, 'stval'),
(0x144, 'sip'),
(0x180, 'satp'),
# Standard Hypervisor R/w
(0x200, 'vsstatus'),
(0x204, 'vsie'),
(0x205, 'vstvec'),
(0x240, 'vsscratch'),
(0x241, 'vsepc'),
(0x242, 'vscause'),
(0x243, 'vstval'),
(0x244, 'vsip'),
(0x280, 'vsatp'),
(0x600, 'hstatus'),
(0x602, 'hedeleg'),
(0x603, 'hideleg'),
(0x604, 'hie'),
(0x605, 'htimedelta'),
(0x606, 'hcounteren'),
(0x607, 'hgeie'),
(0x643, 'htval'),
(0x644, 'hip'),
(0x645, 'hvip'),
(0x64A, 'htinst'),
(0x680, 'hgatp'),
(0xE12, 'hgeip'),
# Tentative CSR assignment for CLIC
(0x007, 'utvt'),
(0x045, 'unxti'),
(0x046, 'uintstatus'),
(0x048, 'uscratchcsw'),
(0x049, 'uscratchcswl'),
(0x107, 'stvt'),
(0x145, 'snxti'),
(0x146, 'sintstatus'),
(0x148, 'sscratchcsw'),
(0x149, 'sscratchcswl'),
(0x307, 'mtvt'),
(0x345, 'mnxti'),
(0x346, 'mintstatus'),
(0x348, 'mscratchcsw'),
(0x349, 'mscratchcswl'),
# Standard Machine R/W
(0x300, 'mstatus'),
(0x301, 'misa'),
(0x302, 'medeleg'),
(0x303, 'mideleg'),
(0x304, 'mie'),
(0x305, 'mtvec'),
(0x306, 'mcounteren'),
(0x320, 'mcountinhibit'),
(0x340, 'mscratch'),
(0x341, 'mepc'),
(0x342, 'mcause'),
(0x343, 'mtval'),
(0x344, 'mip'),
(0x34a, 'mtinst'),
(0x34b, 'mtval2'),
(0x3a0, 'pmpcfg0'),
(0x3a1, 'pmpcfg1'),
(0x3a2, 'pmpcfg2'),
(0x3a3, 'pmpcfg3'),
(0x3b0, 'pmpaddr0'),
(0x3b1, 'pmpaddr1'),
(0x3b2, 'pmpaddr2'),
(0x3b3, 'pmpaddr3'),
(0x3b4, 'pmpaddr4'),
(0x3b5, 'pmpaddr5'),
(0x3b6, 'pmpaddr6'),
(0x3b7, 'pmpaddr7'),
(0x3b8, 'pmpaddr8'),
(0x3b9, 'pmpaddr9'),
(0x3ba, 'pmpaddr10'),
(0x3bb, 'pmpaddr11'),
(0x3bc, 'pmpaddr12'),
(0x3bd, 'pmpaddr13'),
(0x3be, 'pmpaddr14'),
(0x3bf, 'pmpaddr15'),
(0x7a0, 'tselect'),
(0x7a1, 'tdata1'),
(0x7a2, 'tdata2'),
(0x7a3, 'tdata3'),
(0x7b0, 'dcsr'),
(0x7b1, 'dpc'),
(0x7b2, 'dscratch0'),
(0x7b3, 'dscratch1'),
(0xB00, 'mcycle'),
(0xB02, 'minstret'),
(0xB03, 'mhpmcounter3'),
(0xB04, 'mhpmcounter4'),
(0xB05, 'mhpmcounter5'),
(0xB06, 'mhpmcounter6'),
(0xB07, 'mhpmcounter7'),
(0xB08, 'mhpmcounter8'),
(0xB09, 'mhpmcounter9'),
(0xB0A, 'mhpmcounter10'),
(0xB0B, 'mhpmcounter11'),
(0xB0C, 'mhpmcounter12'),
(0xB0D, 'mhpmcounter13'),
(0xB0E, 'mhpmcounter14'),
(0xB0F, 'mhpmcounter15'),
(0xB10, 'mhpmcounter16'),
(0xB11, 'mhpmcounter17'),
(0xB12, 'mhpmcounter18'),
(0xB13, 'mhpmcounter19'),
(0xB14, 'mhpmcounter20'),
(0xB15, 'mhpmcounter21'),
(0xB16, 'mhpmcounter22'),
(0xB17, 'mhpmcounter23'),
(0xB18, 'mhpmcounter24'),
(0xB19, 'mhpmcounter25'),
(0xB1A, 'mhpmcounter26'),
(0xB1B, 'mhpmcounter27'),
(0xB1C, 'mhpmcounter28'),
(0xB1D, 'mhpmcounter29'),
(0xB1E, 'mhpmcounter30'),
(0xB1F, 'mhpmcounter31'),
(0x323, 'mhpmevent3'),
(0x324, 'mhpmevent4'),
(0x325, 'mhpmevent5'),
(0x326, 'mhpmevent6'),
(0x327, 'mhpmevent7'),
(0x328, 'mhpmevent8'),
(0x329, 'mhpmevent9'),
(0x32A, 'mhpmevent10'),
(0x32B, 'mhpmevent11'),
(0x32C, 'mhpmevent12'),
(0x32D, 'mhpmevent13'),
(0x32E, 'mhpmevent14'),
(0x32F, 'mhpmevent15'),
(0x330, 'mhpmevent16'),
(0x331, 'mhpmevent17'),
(0x332, 'mhpmevent18'),
(0x333, 'mhpmevent19'),
(0x334, 'mhpmevent20'),
(0x335, 'mhpmevent21'),
(0x336, 'mhpmevent22'),
(0x337, 'mhpmevent23'),
(0x338, 'mhpmevent24'),
(0x339, 'mhpmevent25'),
(0x33A, 'mhpmevent26'),
(0x33B, 'mhpmevent27'),
(0x33C, 'mhpmevent28'),
(0x33D, 'mhpmevent29'),
(0x33E, 'mhpmevent30'),
(0x33F, 'mhpmevent31'),
# Custom Machine R/W
(0x7d0, 'trace'),
(0x7d1, 'stacklimit'),
# Standard Machine RO
(0xF11, 'mvendorid'),
(0xF12, 'marchid'),
(0xF13, 'mimpid'),
(0xF14, 'mhartid'),
# Custom CSR
(0x7C0, 'ssr'),
(0x7C1, 'fpmode'),
]
csrs32 = [
# Standard Hypervisor R/w
(0x615, 'htimedeltah'),
# Standard User RO
(0xC80, 'cycleh'),
(0xC81, 'timeh'),
(0xC82, 'instreth'),
(0xC83, 'hpmcounter3h'),
(0xC84, 'hpmcounter4h'),
(0xC85, 'hpmcounter5h'),
(0xC86, 'hpmcounter6h'),
(0xC87, 'hpmcounter7h'),
(0xC88, 'hpmcounter8h'),
(0xC89, 'hpmcounter9h'),
(0xC8A, 'hpmcounter10h'),
(0xC8B, 'hpmcounter11h'),
(0xC8C, 'hpmcounter12h'),
(0xC8D, 'hpmcounter13h'),
(0xC8E, 'hpmcounter14h'),
(0xC8F, 'hpmcounter15h'),
(0xC90, 'hpmcounter16h'),
(0xC91, 'hpmcounter17h'),
(0xC92, 'hpmcounter18h'),
(0xC93, 'hpmcounter19h'),
(0xC94, 'hpmcounter20h'),
(0xC95, 'hpmcounter21h'),
(0xC96, 'hpmcounter22h'),
(0xC97, 'hpmcounter23h'),
(0xC98, 'hpmcounter24h'),
(0xC99, 'hpmcounter25h'),
(0xC9A, 'hpmcounter26h'),
(0xC9B, 'hpmcounter27h'),
(0xC9C, 'hpmcounter28h'),
(0xC9D, 'hpmcounter29h'),
(0xC9E, 'hpmcounter30h'),
(0xC9F, 'hpmcounter31h'),
# Standard Machine RW
(0x310, 'mstatush'),
(0xB80, 'mcycleh'),
(0xB82, 'minstreth'),
(0xB83, 'mhpmcounter3h'),
(0xB84, 'mhpmcounter4h'),
(0xB85, 'mhpmcounter5h'),
(0xB86, 'mhpmcounter6h'),
(0xB87, 'mhpmcounter7h'),
(0xB88, 'mhpmcounter8h'),
(0xB89, 'mhpmcounter9h'),
(0xB8A, 'mhpmcounter10h'),
(0xB8B, 'mhpmcounter11h'),
(0xB8C, 'mhpmcounter12h'),
(0xB8D, 'mhpmcounter13h'),
(0xB8E, 'mhpmcounter14h'),
(0xB8F, 'mhpmcounter15h'),
(0xB90, 'mhpmcounter16h'),
(0xB91, 'mhpmcounter17h'),
(0xB92, 'mhpmcounter18h'),
(0xB93, 'mhpmcounter19h'),
(0xB94, 'mhpmcounter20h'),
(0xB95, 'mhpmcounter21h'),
(0xB96, 'mhpmcounter22h'),
(0xB97, 'mhpmcounter23h'),
(0xB98, 'mhpmcounter24h'),
(0xB99, 'mhpmcounter25h'),
(0xB9A, 'mhpmcounter26h'),
(0xB9B, 'mhpmcounter27h'),
(0xB9C, 'mhpmcounter28h'),
(0xB9D, 'mhpmcounter29h'),
(0xB9E, 'mhpmcounter30h'),
(0xB9F, 'mhpmcounter31h'),
]
opcode_base = 0
opcode_size = 7
funct_base = 12
funct_size = 3
def binary(n, digits=0):
rep = bin(n)[2:]
return rep if digits == 0 else ('0' * (digits - len(rep))) + rep
def make_c(match,mask):
print('/* Automatically generated by parse_opcodes. */')
print('#ifndef RISCV_ENCODING_H')
print('#define RISCV_ENCODING_H')
for name in namelist:
name2 = name.upper().replace('.','_')
print('#define MATCH_%s %s' % (name2, hex(match[name])))
print('#define MASK_%s %s' % (name2, hex(mask[name])))
for num, name in csrs+csrs32:
print('#define CSR_%s %s' % (name.upper(), hex(num)))
for num, name in causes:
print('#define CAUSE_%s %s' % (name.upper().replace(' ', '_'), hex(num)))
print('#endif')
print('#ifdef DECLARE_INSN')
for name in namelist:
name2 = name.replace('.','_')
print('DECLARE_INSN(%s, MATCH_%s, MASK_%s)' % (name2, name2.upper(), name2.upper()))
print('#endif')
print('#ifdef DECLARE_CSR')
for num, name in csrs+csrs32:
print('DECLARE_CSR(%s, CSR_%s)' % (name, name.upper()))
print('#endif')
print('#ifdef DECLARE_CAUSE')
for num, name in causes:
print('DECLARE_CAUSE("%s", CAUSE_%s)' % (name, name.upper().replace(' ', '_')))
print('#endif')
def make_sv(match,mask):
print('// Automatically generated by parse-opcodes (pulp-fork).')
print('package riscv_defines;')
for name in namelist:
sv_insn_mask = ""
for i in range(32):
if (mask[name] & (1 << i)) != 0:
match_bit = (match[name] >> i) & 1;
sv_insn_mask = str(match_bit) + sv_insn_mask
else:
sv_insn_mask = '?' + sv_insn_mask
name2 = name.upper().replace('.','_')
print('parameter MATCH_%s = 32\'h%x;' % (name2, (match[name])))
print('parameter MASK_%s = 32\'h%x;' % (name2, (mask[name])))
print('parameter SV_%s = 32\'b%s;' % (name2, sv_insn_mask))
for num, name in csrs+csrs32:
print('parameter CSR_%s = 32\'h%x;' % (name.upper(), (num)))
for num, name in causes:
print('parameter CAUSE_%s = 5\'h%x;' % (name.upper().replace(' ', '_'), (num)))
print('endpackage')
def make_camel_case(name):
return "".join([name.capitalize() for name in name.split('.')])
def make_camel_case_arg(arg):
return make_camel_case(".".join(".".join(arg).split('_')) or "Unit")
def make_func_case_arg(arg):
return "_".join((a.lower() for a in arg)) or "unit"
def make_rust_field_shuffle(recipe, sign_extend_to=None):
ops = list()
for (field, hi, lo, dst) in recipe:
ops.append("((self.{} >> {}) & 0x{:x}) << {}".format(
field,
lo,
(1 << (hi-lo+1)) - 1,
dst
))
ops = " | ".join(ops)
if sign_extend_to is not None:
ops = "((({0}) << {1}) as i32) >> {1}".format(ops, 32 - sign_extend_to)
return ops
def make_rust():
print("// Automatically generated by parse-opcodes.")
print()
# Group instructions based on their mask.
insts_by_mask = dict()
for name, m in mask.items():
if not pseudos.get(name):
insts_by_mask.setdefault(m, []).append(name)
distinct_masks = list(sorted(insts_by_mask.keys()))
# Group instructions based on their arguments.
insts_by_args = dict()
for name, arg in arguments.items():
if not pseudos.get(name):
insts_by_args.setdefault(tuple(sorted(arg)), []).append(name)
distinct_args = list(sorted(insts_by_args.keys()))
# Emit the argument formats.
print("/// The different instruction formats.")
print("#[derive(Debug, Copy, Clone)]")
print("pub enum Format {")
print(" Illegal(u32),")
for a in distinct_args:
print(" {0}(Format{0}),".format(make_camel_case_arg(a)))
print("}")
print()
print("impl Format {")
print(" pub fn raw(&self) -> u32 {")
print(" match self {")
print(" Self::Illegal(x) => *x,")
for a in distinct_args:
print(" Self::{}(x) => x.raw,".format(make_camel_case_arg(a)))
print(" }")
print(" }")
print("}")
print()
print("impl std::fmt::Display for Format {")
print(" fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {")
print(" match self {")
print(" Self::Illegal(x) => write!(f, \"<illegal 0x{:x}>\", x),")
for a in distinct_args:
print(" Self::{}(x) => write!(f, \"{{}}\", x),".format(make_camel_case_arg(a)))
print(" }")
print(" }")
print("}")
print()
# Emit the per-format opcodes.
for a in distinct_args:
name = make_camel_case_arg(a)
print("/// The `{}` instruction format.".format(name))
print("#[derive(Debug, Copy, Clone)]")
print("pub struct Format{} {{".format(name))
args = ["pub op: Opcode{}".format(name), "pub raw: u32"] + ["pub {}: u32".format(n.lower()) for n in a]
args = "\n ".join(("{},".format(n) for n in args))
print(" {}".format(args))
print("}")
print()
print("impl Format{} {{".format(name))
if "imm12" in a:
print(" pub fn imm(&self) -> i32 {")
print(" ((self.imm12 << 20) as i32) >> 20");
print(" }")
if "imm12hi" in a and "imm12lo" in a:
print(" pub fn imm(&self) -> i32 {")
print(" {}".format(make_rust_field_shuffle(bits_imm12, 12)));
print(" }")
if "bimm12hi" in a and "bimm12lo" in a:
print(" pub fn bimm(&self) -> i32 {")
print(" {}".format(make_rust_field_shuffle(bits_bimm12, 13)));
print(" }")
if "jimm20" in a:
print(" pub fn jimm(&self) -> i32 {")
print(" {}".format(make_rust_field_shuffle(bits_jimm20, 21)));
print(" }")
if "imm6" in a:
print(" pub fn imm(&self) -> i32 {")
print(" {}".format(make_rust_field_shuffle(bits_imm6, 6)));
print(" }")
print("}")
print()
print("/// Opcodes with the `{}` instruction format.".format(name))
print("#[derive(Debug, Copy, Clone)]")
print("pub enum Opcode{} {{".format(name))
for op in insts_by_args[a]:
print(" {},".format(make_camel_case(op)))
print("}")
print()
print("impl std::fmt::Display for Format{} {{".format(name))
print(" fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {")
print(" write!(f, \"{}\", self.op)?;")
for arg in a:
print(" write!(f, \" {}={{:x}}\", self.{})?;".format(arg, arg.lower()))
print(" Ok(())")
print(" }")
print("}")
print()
print("impl std::fmt::Display for Opcode{} {{".format(name))
print(" fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result {")
print(" match self {")
for n in insts_by_args[a]:
print(" Self::{} => write!(f, \"{}\"),".format(make_camel_case(n), n))
print(" }")
print(" }")
print("}")
print("")
# Emit the parse function.
print("/// Parse a `u32` into an instruction.")
print("pub fn parse_u32(raw: u32) -> Format {")
for m in distinct_masks:
print(" match raw & 0x{:x} {{".format(m))
for n in insts_by_mask[m]:
a = tuple(sorted(arguments[n]))
print(" 0x{:x} => return parse_{}(Opcode{}::{}, raw),".format(
match[n],
make_func_case_arg(a),
make_camel_case_arg(a),
make_camel_case(n)
))
print(" _ => (),")
print(" }")
print(" Format::Illegal(raw)")
print("}")
print()
print("/// Parse the first bytes of a `&[u8]` slice into an instruction.")
print("pub fn parse(mut raw: &[u8]) -> Format {")
print(" use byteorder::{LittleEndian, ReadBytesExt};")
print(" raw.read_u32::<LittleEndian>().map(parse_u32).unwrap_or(Format::Illegal(0))")
print("}")
print()
for a in distinct_args:
name = make_camel_case_arg(a)
func_name = make_func_case_arg(a)
print("/// Parse an instruction with the `{}` format.".format(name))
print("pub fn parse_{}(op: Opcode{}, raw: u32) -> Format {{".format(func_name, name))
print(" Format::{}(Format{} {{".format(name, name))
print(" op,")
print(" raw,")
for arg in a:
lo = arglut[arg][1]
hi = arglut[arg][0]
print(" {}: (raw >> {}) & 0x{:x},".format(arg.lower(), lo, (1<<(hi-lo+1))-1))
print(" })")
print("}")
print()
# Emit function to get instruction string.
print("/// Decode instruction into string.")
print("pub fn inst_to_string(raw: Format) -> String {")
print(" match raw {")
for a in distinct_args:
print(" Format::{0}(x) => x.op.to_string(),".format(make_camel_case_arg(a)))
print(" _ => \"Unsupported instruction format\".to_string(),")
print(" }")
print("}")
# Emit configuration.
print("/// Struct to store the latency of each instruction.")
print("#[derive(Debug, serde::Serialize, serde::Deserialize)]")
print("pub struct Latency {")
for a in distinct_args:
print(" // Format::{0}".format(make_camel_case_arg(a)))
for n in insts_by_args[a]:
n = n.lower()
print(" {}: u8,".format("_".join(n.split('.'))))
print("}")
print()
# Create a default configuration.
print("/// Struct to store the latency of each instruction.")
print("impl Default for Latency {")
print(" fn default() -> Latency {")
print(" Latency {")
for a in distinct_args:
for n in insts_by_args[a]:
n = n.lower()
print(" {}: 1,".format("_".join(n.split('.'))))
print(" }")
print(" }")
print("}")
# Emit CSR enum
print("/// CSR")
print("#[derive(Debug, Copy, Clone)]")
print("#[repr(C)]")
print("pub enum Csr {")
for csr in csrs+csrs32:
print(" {} = 0x{:03x},".format(make_camel_case(csr[1]), csr[0]))
print("}")
def make_py(match,mask):
print('# Automatically generated by parse-opcodes.')
for name in namelist:
name2 = name.upper().replace('.', '_')
print('MATCH_%s = %s' % (name2, hex(match[name])))
print('MASK_%s = %s' % (name2, hex(mask[name])))
for num, name in csrs+csrs32:
print('CSR_%s = %s' % (name.upper(), hex(num)))
for num, name in causes:
print('CAUSE_%s = %s' % (name.upper().replace(' ', '_'), hex(num)))
def yank(num,start,len):
return (num >> start) & ((1 << len) - 1)
def str_arg(arg0,name,match,arguments):
if arg0 in arguments:
return name or arg0
else:
start = arglut[arg0][1]
len = arglut[arg0][0] - arglut[arg0][1] + 1
return binary(yank(match,start,len),len)
def str_inst(name,arguments):
return name.replace('.rv32','').upper()
def print_unimp_type(name,match,arguments):
print("""
&
\\multicolumn{10}{|c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
'0'*32, \
'UNIMP' \
))
def print_u_type(name,match,arguments):
print("""
&
\\multicolumn{8}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
str_arg('imm20','imm[31:12]',match,arguments), \
str_arg('rd','',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_uj_type(name,match,arguments):
print("""
&
\\multicolumn{8}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
str_arg('jimm20','imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]',match,arguments), \
str_arg('rd','',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_s_type(name,match,arguments):
print("""
&
\\multicolumn{4}{|c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
str_arg('imm12hi','imm[11:5]',match,arguments), \
str_arg('rs2','',match,arguments), \
str_arg('rs1','',match,arguments), \
binary(yank(match,funct_base,funct_size),funct_size), \
str_arg('imm12lo','imm[4:0]',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_sb_type(name,match,arguments):
print("""
&
\\multicolumn{4}{|c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
str_arg('bimm12hi','imm[12$\\vert$10:5]',match,arguments), \
str_arg('rs2','',match,arguments), \
str_arg('rs1','',match,arguments), \
binary(yank(match,funct_base,funct_size),funct_size), \
str_arg('bimm12lo','imm[4:1$\\vert$11]',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_i_type(name,match,arguments):
print("""
&
\\multicolumn{6}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
str_arg('imm12','imm[11:0]',match,arguments), \
str_arg('rs1','',match,arguments), \
binary(yank(match,funct_base,funct_size),funct_size), \
str_arg('rd','',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_csr_type(name,match,arguments):
print("""
&
\\multicolumn{6}{|c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
str_arg('imm12','csr',match,arguments), \
('uimm' if name[-1] == 'i' else 'rs1'), \
binary(yank(match,funct_base,funct_size),funct_size), \
str_arg('rd','',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_ish_type(name,match,arguments):
print("""
&
\\multicolumn{3}{|c|}{%s} &
\\multicolumn{3}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
binary(yank(match,26,6),6), \
str_arg('shamt','shamt',match,arguments), \
str_arg('rs1','',match,arguments), \
binary(yank(match,funct_base,funct_size),funct_size), \
str_arg('rd','',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_ishw_type(name,match,arguments):
print("""
&
\\multicolumn{4}{|c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
binary(yank(match,25,7),7), \
str_arg('shamtw','shamt',match,arguments), \
str_arg('rs1','',match,arguments), \
binary(yank(match,funct_base,funct_size),funct_size), \
str_arg('rd','',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_r_type(name,match,arguments):
print("""
&
\\multicolumn{4}{|c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
binary(yank(match,25,7),7), \
str_arg('rs2','',match,arguments), \
'zimm' in arguments and str_arg('zimm','imm[4:0]',match,arguments) or str_arg('rs1','',match,arguments), \
str_arg('rm','',match,arguments), \
str_arg('rd','',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_r4_type(name,match,arguments):
print("""
&
\\multicolumn{2}{|c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
str_arg('rs3','',match,arguments), \
binary(yank(match,25,2),2), \
str_arg('rs2','',match,arguments), \
str_arg('rs1','',match,arguments), \
str_arg('rm','',match,arguments), \
str_arg('rd','',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_amo_type(name,match,arguments):
print("""
&
\\multicolumn{2}{|c|}{%s} &
\\multicolumn{1}{c|}{aq} &
\\multicolumn{1}{c|}{rl} &
\\multicolumn{2}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
binary(yank(match,27,5),5), \
str_arg('rs2','',match,arguments), \
str_arg('rs1','',match,arguments), \
binary(yank(match,funct_base,funct_size),funct_size), \
str_arg('rd','',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_fence_type(name,match,arguments):
print("""
&
\\multicolumn{2}{|c|}{%s} &
\\multicolumn{3}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} &
\\multicolumn{1}{c|}{%s} & %s \\\\
\\cline{2-11}
""" % \
( \
str_arg('fm','fm',match,arguments), \
str_arg('pred','pred',match,arguments), \
str_arg('succ','',match,arguments), \
str_arg('rs1','',match,arguments), \
binary(yank(match,funct_base,funct_size),funct_size), \
str_arg('rd','',match,arguments), \
binary(yank(match,opcode_base,opcode_size),opcode_size), \
str_inst(name,arguments) \
))
def print_header(*types):
print("""
\\newpage
\\begin{table}[p]
\\begin{small}
\\begin{center}
\\begin{tabular}{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
& & & & & & & & & & \\\\
&
\\multicolumn{1}{l}{\\instbit{31}} &
\\multicolumn{1}{r}{\\instbit{27}} &
\\instbit{26} &
\\instbit{25} &
\\multicolumn{1}{l}{\\instbit{24}} &
\\multicolumn{1}{r}{\\instbit{20}} &
\\instbitrange{19}{15} &
\\instbitrange{14}{12} &
\\instbitrange{11}{7} &
\\instbitrange{6}{0} \\\\
\\cline{2-11}
""")
if 'r' in types:
print("""
&
\\multicolumn{4}{|c|}{funct7} &
\\multicolumn{2}{c|}{rs2} &
\\multicolumn{1}{c|}{rs1} &
\\multicolumn{1}{c|}{funct3} &
\\multicolumn{1}{c|}{rd} &