diff --git a/common/read_batch.py b/common/read_batch.py index 89ed00e..1058a41 100755 --- a/common/read_batch.py +++ b/common/read_batch.py @@ -212,7 +212,7 @@ def run( # create the Sources.list with open(l, "w+") as fp: path = batch.get(rule, "__path__") - dedent = ''.join(["../"] * (2 + path.count('/'))) + dedent = "".join(["../"] * (2 + path.count("/"))) fp.write("%s\n" % os.path.join(dedent, path)) for option in batch.options(rule): if not option.startswith("__"): diff --git a/common/read_sources.py b/common/read_sources.py index fc02224..c720285 100755 --- a/common/read_sources.py +++ b/common/read_sources.py @@ -374,7 +374,9 @@ def read_from(sources_list: str, no_logger: bool = False, no_stdout: bool = True else: print(node.name, _t, sep=";") # list the parameters - for node in graph: + # from graph on reverse orders to apply the latest + # value of the parameter in the hierarchy + for node in graph[::-1]: if no_stdout and isinstance(node, Node): parameters.update(node.params) elif no_stdout: diff --git a/tests/analog/.tmp_report/report.html b/tests/analog/.tmp_report/report.html new file mode 100644 index 0000000..9d78c5b --- /dev/null +++ b/tests/analog/.tmp_report/report.html @@ -0,0 +1,195 @@ + + + + + + + + + + + +

analog

+

Friday, 22. May 2020 15:57

+

+ Errors:0 +
+ Warnings:0 +
+ Elapsed Time:39.392s +

+ + + + + + + + + + + + + + + + + + + + + + + + + + +
namelintsimulationcoveragetotal time
+ + ltspice + + -4/4-28.632s
+ + others + + ----
+ +
+ + ltspice + +

Lint

+
No lints
+ +

Simulation

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
idwarningserrorstotal time
ota006.24s
filter009.529s
schmitt008.54s
xor005.25s
+ +

Code coverage

+
No coverage simulations
+
+
+ + others + +

Lint

+
No lints
+ +

Simulation

+
No simulations
+ +

Code coverage

+
No coverage simulations
+
+ + + \ No newline at end of file diff --git a/tests/digital/.tmp_report/report.html b/tests/digital/.tmp_report/report.html new file mode 100644 index 0000000..0d723d8 --- /dev/null +++ b/tests/digital/.tmp_report/report.html @@ -0,0 +1,246 @@ + + + + + + + + + + + +

digital

+

Friday, 22. May 2020 15:53

+

+ Errors:0 +
+ Warnings:4 +
+ Elapsed Time:43.38s +

+ + + + + + + + + + + + + + + + + + + + + + + + + + +
namelintsimulationcoveragetotal time
+ + batch + + -8/8-0.440s
+ + others + + -3/3-13.872s
+ +
+ + batch + +

Lint

+
No lints
+ +

Simulation

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
idwarningserrorstotal time
s000.48s
fast_clock000.57s
s2000.64s
n000.53s
n2000.48s
tb000.51s
UFC000.68s
youpi000.51s
+ +

Code coverage

+
No coverage simulations
+
+
+ + others + +

Lint

+
No lints
+ +

Simulation

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
idwarningserrorstotal time
mako207.196s
generic_sar206.617s
simple000.59s
+ +

Code coverage

+
No coverage simulations
+
+ + + \ No newline at end of file diff --git a/tests/platform/design/adder/Sources.list b/tests/platform/design/adder/Sources.list new file mode 100644 index 0000000..50cb1eb --- /dev/null +++ b/tests/platform/design/adder/Sources.list @@ -0,0 +1,2 @@ +cla +rca \ No newline at end of file diff --git a/tests/platform/design/adder/cla/Sources.list b/tests/platform/design/adder/cla/Sources.list new file mode 100644 index 0000000..2ae481f --- /dev/null +++ b/tests/platform/design/adder/cla/Sources.list @@ -0,0 +1,3 @@ +cla.v +cla_4.v +/library/generic \ No newline at end of file diff --git a/tests/platform/design/adder/cla/cla.v b/tests/platform/design/adder/cla/cla.v new file mode 100644 index 0000000..dd3c179 --- /dev/null +++ b/tests/platform/design/adder/cla/cla.v @@ -0,0 +1,39 @@ +// Carry LookAhead Adder +`timescale 1ns/100ps + +module cla #( + parameter WIDTH = 8 +) ( + input wire [WIDTH*4-1:0] a, + input wire [WIDTH*4-1:0] b, + output wire [WIDTH*4-1:0] s, + output wire c +); + +wire [WIDTH-1:0] p; +wire [WIDTH-1:0] g; +wire [WIDTH:0] ci; + +assign ci[0] = 1'b0; + +generate + genvar gi; + + for(gi = 0; gi < WIDTH; gi = gi + 1) + begin: adder + cla_4 fa4 ( + .a(a[4*gi +: 4]), + .b(b[4*gi +: 4]), + .ci(ci[gi]), + .s(s[4*gi +: 4]), + .pg(p[gi]), + .gg(g[gi]), + .cg(ci[gi+1]) + ); + end +endgenerate + +assign c = ci[WIDTH]; + + +endmodule \ No newline at end of file diff --git a/tests/platform/design/adder/cla/cla_4.v b/tests/platform/design/adder/cla/cla_4.v new file mode 100644 index 0000000..02c63ab --- /dev/null +++ b/tests/platform/design/adder/cla/cla_4.v @@ -0,0 +1,64 @@ +// Carry LookAhead Adder +`timescale 1ns/100ps + +module cla_4 ( + input wire [3:0] a, + input wire [3:0] b, + input wire ci, + output wire [3:0] s, + output wire pg, + output wire gg, + output wire cg +); + +wire [3:0] pi; +wire [3:0] gi; +wire [4:0] c; +wire [3:0] pp; +wire [5:0] gp; +wire [1:0] cit; +wire ggt; + +assign c[0] = ci; + +full_adder_cla fa[3:0] ( + .a(a), + .b(b), + .ci(c[3:0]), + .s(s), + .p(pi), + .g(gi) +); + +// maximum and3 +and #(700ps) pp_3 (pp[3], pi[3], pi[2], pp[0]); +and #(700ps) pp_2 (pp[2], pi[2], pi[1], pp[0]); +and #(700ps) pp_1 (pp[1], pi[1], pi[0], c[0]); +and #(700ps) pp_0 (pp[0], pi[0], c[0]); + +and #(700ps) gp_2 (gp[2], gp[1], pi[2], pi[3]); +and #(700ps) gp_1 (gp[1], gi[0], pi[1], pi[2]); +and #(700ps) gp_0 (gp[0], gi[0], pi[1]); + +and #(700ps) gp_5 (gp[5], gi[2], pi[3]); +and #(700ps) gp_4 (gp[4], gi[1], pi[2], pi[3]); +and #(700ps) gp_3 (gp[3], gi[1], pi[2]); + +or #(600ps) cio_1 (c[1], gi[0], pp[0]); +or #(600ps) cio_2 (c[2], gi[1], gp[0], pp[1]); +or #(600ps) cio_3 (cit[0], gi[2], gp[1], pp[2]); +or #(600ps) cio_3b (c[3], cit[0], gp[3]); +or #(600ps) cio_4 (cit[1], gi[3], gp[2], pp[3]); +or #(600ps) cio_4b (c[4], cit[1], gp[4], gp[5]); + +and #(800ps) pg_a (pg, pi[3], pi[2], pi[1], pi[0]); +or #(600ps) gg_o1 (ggt, gi[3], gp[5], gp[4]); +or #(600ps) gg_o2 (gg, ggt, gp[2]); + +assign #(800ps) cg = gg | (pg & ci); + +specify + (ci => cg) = (1.0, 1.2); +endspecify + +endmodule \ No newline at end of file diff --git a/tests/platform/design/adder/rca/Sources.list b/tests/platform/design/adder/rca/Sources.list index faaf9f5..0614e83 100644 --- a/tests/platform/design/adder/rca/Sources.list +++ b/tests/platform/design/adder/rca/Sources.list @@ -1,2 +1,2 @@ rca.v -/library/generic +/library/generic \ No newline at end of file diff --git a/tests/platform/design/adder/rca/rca.v b/tests/platform/design/adder/rca/rca.v index bca6de6..e7c08e5 100644 --- a/tests/platform/design/adder/rca/rca.v +++ b/tests/platform/design/adder/rca/rca.v @@ -1,5 +1,7 @@ // Ripple-Carry-Adder // traditionnal one +`timescale 1ns/100ps + module rca #( parameter WIDTH = 32 ) ( diff --git a/tests/platform/library/generic/Sources.list b/tests/platform/library/generic/Sources.list index 2653f51..6393f18 100644 --- a/tests/platform/library/generic/Sources.list +++ b/tests/platform/library/generic/Sources.list @@ -1 +1 @@ -lib.v +lib.v \ No newline at end of file diff --git a/tests/platform/library/generic/lib.v b/tests/platform/library/generic/lib.v index 549ce07..e1c5bc3 100644 --- a/tests/platform/library/generic/lib.v +++ b/tests/platform/library/generic/lib.v @@ -49,4 +49,32 @@ module full_adder ( (ci => co) = (1.4, 1.6); endspecify +endmodule + +module full_adder_cla ( + input wire a, + input wire b, + input wire ci, + output wire s, + output wire p, + output wire g +); + + wire partial_sum; + + xor sum_0 (partial_sum, a, b); + xor sum_1 (s, partial_sum, ci); + or pro_c (p, a, b); + and gen_c (g, a, b); + + specify + (a => s) = (2, 2.4); + (b => s) = (2, 2.4); + (ci => s) = (1, 1.2); + (a => p) = (0.6, 0.7); + (b => p) = (0.6, 0.7); + (a => g) = (0.7, 0.8); + (b => g) = (0.7, 0.8); + endspecify + endmodule \ No newline at end of file diff --git a/tests/platform/testcases/.tmp_report/report.html b/tests/platform/testcases/.tmp_report/report.html new file mode 100644 index 0000000..0831331 --- /dev/null +++ b/tests/platform/testcases/.tmp_report/report.html @@ -0,0 +1,171 @@ + + + + + + + + + + + +

testcases

+

Sunday, 31. May 2020 13:08

+

+ Errors:154 +
+ Warnings:0 +
+ Elapsed Time:2.903s +

+ + + + + + + + + + + + + + + + + + + +
namelintsimulationcoveragetotal time
+ + others + + -1/4-0.893s
+ +
+ + others + +

Lint

+
No lints
+ +

Simulation

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
idwarningserrorstotal time
60meg040.227s
50meg020.220s
32meg000.221s
100meg01480.225s
+ +

Code coverage

+
No coverage simulations
+
+ + + \ No newline at end of file diff --git a/tests/platform/testcases/Batch.list b/tests/platform/testcases/Batch.list new file mode 100644 index 0000000..3f7a5dc --- /dev/null +++ b/tests/platform/testcases/Batch.list @@ -0,0 +1,11 @@ +do sim on adder as 32meg: + SIM_FLAGS = -gspecify -PARAM tb.TCLK=31.25 + +do sim on adder as 50meg: + SIM_FLAGS = -gspecify -PARAM tb.TCLK=20 + +do sim on adder as 60meg: + SIM_FLAGS = -gspecify -PARAM tb.TCLK=16.667 + +do sim on adder as 100meg: + SIM_FLAGS = -gspecify -PARAM tb.TCLK=10 \ No newline at end of file diff --git a/tests/platform/testcases/adder/Sources.list b/tests/platform/testcases/adder/Sources.list index 38a5de2..012bc7d 100644 --- a/tests/platform/testcases/adder/Sources.list +++ b/tests/platform/testcases/adder/Sources.list @@ -1,2 +1,4 @@ tb.sv -/design/adder/rca +/design/adder + +SIM_FLAGS=-gspecify -PARAM tb.TCLK=25 \ No newline at end of file diff --git a/tests/platform/testcases/adder/tb.sv b/tests/platform/testcases/adder/tb.sv index e19263e..1ddd1f7 100644 --- a/tests/platform/testcases/adder/tb.sv +++ b/tests/platform/testcases/adder/tb.sv @@ -2,6 +2,7 @@ module tb; +parameter TCLK = 32; parameter WIDTH = 32; reg [WIDTH-1:0] a; @@ -23,14 +24,14 @@ begin: test run_check = 1'b0; a = $urandom();//_range(0, 2**32); b = $urandom();//_range(0, 2**32); - #(15ns); + #((TCLK-1) * 1ns); run_check = 1'b1; #(1ns); end end //======== DUTS ======== -// traditionnal one +// traditional one rca #( .WIDTH(WIDTH) ) rca ( @@ -40,12 +41,22 @@ rca #( .c() ); +cla #( + .WIDTH(WIDTH/4) +) cla ( + .a(a), + .b(b), + .s(s_cla), + .c() +); + //======== Checker ======== assign s_ref = a + b; always @(posedge run_check) begin: sum_check - if (s_rca != s_ref) `log_Error("Wrong sum result"); + if (s_rca != s_ref) `log_Error("Wrong ripple-carry-adder sum result"); + if (s_cla != s_ref) `log_Error("Wrong carry-lookahead-adder sum result"); end diff --git a/tests/platform/testcases/adder/waveform.gtkw b/tests/platform/testcases/adder/waveform.gtkw index e6a80ba..f426711 100644 --- a/tests/platform/testcases/adder/waveform.gtkw +++ b/tests/platform/testcases/adder/waveform.gtkw @@ -1,15 +1,19 @@ [*] [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI -[*] Fri May 29 23:42:59 2020 +[*] Sat May 30 20:07:32 2020 [*] -[dumpfile] "/home/ludwigcron/Projects/tc_adder/.tmp_sim/run.vcd" -[dumpfile_mtime] "Fri May 29 23:42:09 2020" -[dumpfile_size] 457549 -[savefile] "/home/ludwigcron/Projects/tc_adder/waveform.gtkw" +[dumpfile] "/home/ludwigcron/Projects/reflow/tests/platform/testcases/adder/.tmp_sim/run.vcd" +[dumpfile_mtime] "Sat May 30 20:06:16 2020" +[dumpfile_size] 1872241 +[savefile] "/home/ludwigcron/Projects/reflow/tests/platform/testcases/adder/waveform.gtkw" [timestart] 0 [size] 1811 967 [pos] -1 -1 -*-14.418499 15000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-21.313917 77000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] tb. +[treeopen] tb.cla. +[treeopen] tb.cla.adder[0]. +[treeopen] tb.cla.adder[0].fa4. [sst_width] 379 [signals_width] 395 [sst_expanded] 1 @@ -22,5 +26,42 @@ tb.run_check @420 tb.s_ref[31:0] tb.s_rca[31:0] +@c00420 +tb.s_cla[31:0] +@28 +(0)tb.s_cla[31:0] +(1)tb.s_cla[31:0] +(2)tb.s_cla[31:0] +(3)tb.s_cla[31:0] +(4)tb.s_cla[31:0] +(5)tb.s_cla[31:0] +(6)tb.s_cla[31:0] +(7)tb.s_cla[31:0] +(8)tb.s_cla[31:0] +(9)tb.s_cla[31:0] +(10)tb.s_cla[31:0] +(11)tb.s_cla[31:0] +(12)tb.s_cla[31:0] +(13)tb.s_cla[31:0] +(14)tb.s_cla[31:0] +(15)tb.s_cla[31:0] +(16)tb.s_cla[31:0] +(17)tb.s_cla[31:0] +(18)tb.s_cla[31:0] +(19)tb.s_cla[31:0] +(20)tb.s_cla[31:0] +(21)tb.s_cla[31:0] +(22)tb.s_cla[31:0] +(23)tb.s_cla[31:0] +(24)tb.s_cla[31:0] +(25)tb.s_cla[31:0] +(26)tb.s_cla[31:0] +(27)tb.s_cla[31:0] +(28)tb.s_cla[31:0] +(29)tb.s_cla[31:0] +(30)tb.s_cla[31:0] +(31)tb.s_cla[31:0] +@1401600 +-group_end [pattern_trace] 1 [pattern_trace] 0