From d9abf5e08c79af03170eebbe32b5a9afb5f9551f Mon Sep 17 00:00:00 2001 From: Mythri Alle Date: Fri, 11 Nov 2022 11:07:11 +0000 Subject: [PATCH] Fix ArtDisassemblerTest.LoadLiteralVisit to read initialized values ArtDisassemblerTest.LoadLiteralVisit tests the disassembly output of ldr by reading from pc + 0. It was using 64-bit gpr and fpr registers but we only know the contents of 32-bits (the encoding of the instruction). The other 32-bits could be uninitialized or maybe even unaccessible. So use 32-bit registers so we can expect a known value always. Bug: 258391316 Test: art_disassembler_tests in asan config Change-Id: Iaaf2bbe3912772593af64a54e49519ae40e18f14 --- disassembler/disassembler_arm64_test.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/disassembler/disassembler_arm64_test.cc b/disassembler/disassembler_arm64_test.cc index c1917cc52b..81c067ab56 100644 --- a/disassembler/disassembler_arm64_test.cc +++ b/disassembler/disassembler_arm64_test.cc @@ -138,10 +138,12 @@ TEST_F(ArtDisassemblerTest, LoadLiteralVisit) { COMPARE(ldr(x0, MemOperand(x18, 0)), "ldr x0, \\[x18\\]$"); // Check we do append some extra info in the right text format for valid literal load instruction. - COMPARE(ldr(x0, vixl::aarch64::Assembler::ImmLLiteral(0)), - "ldr x0, pc\\+0 \\(addr -?0x[0-9a-f]+\\) \\(0x[0-9a-fA-F]+ / -?[0-9]+\\)"); - COMPARE(ldr(d0, vixl::aarch64::Assembler::ImmLLiteral(0)), - "ldr d0, pc\\+0 \\(addr -?0x[0-9a-f]+\\) \\([0-9]+.[0-9]+e(\\+|-)[0-9]+\\)"); + COMPARE(ldr(w0, vixl::aarch64::Assembler::ImmLLiteral(0)), + "ldr w0, pc\\+0 \\(addr -?0x[0-9a-f]+\\) \\(0x18000000 / 402653184\\)"); + // We don't compare with exact value even though it's a known literal (the encoding of the + // instruction itself) since the precision of printed floating point values could change. + COMPARE(ldr(s0, vixl::aarch64::Assembler::ImmLLiteral(0)), + "ldr s0, pc\\+0 \\(addr -?0x[0-9a-f]+\\) \\([0-9]+.[0-9]+e(\\+|-)[0-9]+\\)"); } TEST_F(ArtDisassemblerTest, LoadStoreUnsignedOffsetVisit) {