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disassembler_x86.cc
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/*
* Copyright (C) 2012 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "disassembler_x86.h"
#include <inttypes.h>
#include <ostream>
#include <sstream>
#include "android-base/logging.h"
#include "android-base/stringprintf.h"
#define TWO_BYTE_VEX 0xC5
#define THREE_BYTE_VEX 0xC4
#define VEX_M_0F 0x01
#define VEX_M_0F_38 0x02
#define VEX_M_0F_3A 0x03
#define VEX_PP_NONE 0x00
#define VEX_PP_66 0x01
#define VEX_PP_F3 0x02
#define VEX_PP_F2 0x03
using android::base::StringPrintf;
namespace art {
namespace x86 {
size_t DisassemblerX86::Dump(std::ostream& os, const uint8_t* begin) {
return DumpInstruction(os, begin);
}
void DisassemblerX86::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
size_t length = 0;
for (const uint8_t* cur = begin; cur < end; cur += length) {
length = DumpInstruction(os, cur);
}
}
static const char* gReg8Names[] = {
"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
};
static const char* gExtReg8Names[] = {
"al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
"r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l"
};
static const char* gReg16Names[] = {
"ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
"r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
};
static const char* gReg32Names[] = {
"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
"r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
};
static const char* gReg64Names[] = {
"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
};
// 64-bit opcode REX modifier.
constexpr uint8_t REX_W = 8U /* 0b1000 */;
constexpr uint8_t REX_R = 4U /* 0b0100 */;
constexpr uint8_t REX_X = 2U /* 0b0010 */;
constexpr uint8_t REX_B = 1U /* 0b0001 */;
static void DumpReg0(std::ostream& os, uint8_t rex, size_t reg,
bool byte_operand, uint8_t size_override) {
DCHECK_LT(reg, (rex == 0) ? 8u : 16u);
bool rex_w = (rex & REX_W) != 0;
if (byte_operand) {
os << ((rex == 0) ? gReg8Names[reg] : gExtReg8Names[reg]);
} else if (rex_w) {
os << gReg64Names[reg];
} else if (size_override == 0x66) {
os << gReg16Names[reg];
} else {
os << gReg32Names[reg];
}
}
static void DumpAnyReg(std::ostream& os, uint8_t rex, size_t reg,
bool byte_operand, uint8_t size_override, RegFile reg_file) {
if (reg_file == GPR) {
DumpReg0(os, rex, reg, byte_operand, size_override);
} else if (reg_file == SSE) {
os << "xmm" << reg;
} else {
os << "mm" << reg;
}
}
static void DumpReg(std::ostream& os, uint8_t rex, uint8_t reg,
bool byte_operand, uint8_t size_override, RegFile reg_file) {
bool rex_r = (rex & REX_R) != 0;
size_t reg_num = rex_r ? (reg + 8) : reg;
DumpAnyReg(os, rex, reg_num, byte_operand, size_override, reg_file);
}
static void DumpRmReg(std::ostream& os, uint8_t rex, uint8_t reg,
bool byte_operand, uint8_t size_override, RegFile reg_file) {
bool rex_b = (rex & REX_B) != 0;
size_t reg_num = rex_b ? (reg + 8) : reg;
DumpAnyReg(os, rex, reg_num, byte_operand, size_override, reg_file);
}
static void DumpAddrReg(std::ostream& os, uint8_t rex, uint8_t reg) {
if (rex != 0) {
os << gReg64Names[reg];
} else {
os << gReg32Names[reg];
}
}
static void DumpBaseReg(std::ostream& os, uint8_t rex, uint8_t reg) {
bool rex_b = (rex & REX_B) != 0;
size_t reg_num = rex_b ? (reg + 8) : reg;
DumpAddrReg(os, rex, reg_num);
}
static void DumpOpcodeReg(std::ostream& os, uint8_t rex, uint8_t reg,
bool byte_operand, uint8_t size_override) {
bool rex_b = (rex & REX_B) != 0;
size_t reg_num = rex_b ? (reg + 8) : reg;
DumpReg0(os, rex, reg_num, byte_operand, size_override);
}
enum SegmentPrefix {
kCs = 0x2e,
kSs = 0x36,
kDs = 0x3e,
kEs = 0x26,
kFs = 0x64,
kGs = 0x65,
};
static void DumpSegmentOverride(std::ostream& os, uint8_t segment_prefix) {
switch (segment_prefix) {
case kCs: os << "cs:"; break;
case kSs: os << "ss:"; break;
case kDs: os << "ds:"; break;
case kEs: os << "es:"; break;
case kFs: os << "fs:"; break;
case kGs: os << "gs:"; break;
default: break;
}
}
// Do not inline to avoid Clang stack frame problems. b/18733806
NO_INLINE
static std::string DumpCodeHex(const uint8_t* begin, const uint8_t* end) {
std::stringstream hex;
for (size_t i = 0; begin + i < end; ++i) {
hex << StringPrintf("%02X", begin[i]);
}
return hex.str();
}
std::string DisassemblerX86::DumpAddress(uint8_t mod, uint8_t rm, uint8_t rex64, uint8_t rex_w,
bool no_ops, bool byte_operand, bool byte_second_operand,
uint8_t* prefix, bool load, RegFile src_reg_file,
RegFile dst_reg_file, const uint8_t** instr,
uint32_t* address_bits) {
std::ostringstream address;
if (mod == 0 && rm == 5) {
if (!supports_rex_) { // Absolute address.
*address_bits = *reinterpret_cast<const uint32_t*>(*instr);
address << StringPrintf("[0x%x]", *address_bits);
} else { // 64-bit RIP relative addressing.
address << StringPrintf("[RIP + 0x%x]", *reinterpret_cast<const uint32_t*>(*instr));
}
(*instr) += 4;
} else if (rm == 4 && mod != 3) { // SIB
uint8_t sib = **instr;
(*instr)++;
uint8_t scale = (sib >> 6) & 3;
uint8_t index = (sib >> 3) & 7;
uint8_t base = sib & 7;
address << "[";
// REX.x is bit 3 of index.
if ((rex64 & REX_X) != 0) {
index += 8;
}
// Mod = 0 && base = 5 (ebp): no base (ignores REX.b).
bool has_base = false;
if (base != 5 || mod != 0) {
has_base = true;
DumpBaseReg(address, rex64, base);
}
// Index = 4 (esp/rsp) is disallowed.
if (index != 4) {
if (has_base) {
address << " + ";
}
DumpAddrReg(address, rex64, index);
if (scale != 0) {
address << StringPrintf(" * %d", 1 << scale);
}
}
if (mod == 0) {
if (base == 5) {
if (index != 4) {
address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(*instr));
} else {
// 64-bit low 32-bit absolute address, redundant absolute address encoding on 32-bit.
*address_bits = *reinterpret_cast<const uint32_t*>(*instr);
address << StringPrintf("%d", *address_bits);
}
(*instr) += 4;
}
} else if (mod == 1) {
address << StringPrintf(" + %d", *reinterpret_cast<const int8_t*>(*instr));
(*instr)++;
} else if (mod == 2) {
address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(*instr));
(*instr) += 4;
}
address << "]";
} else {
if (mod == 3) {
if (!no_ops) {
DumpRmReg(address, rex_w, rm, byte_operand || byte_second_operand,
prefix[2], load ? src_reg_file : dst_reg_file);
}
} else {
address << "[";
DumpBaseReg(address, rex64, rm);
if (mod == 1) {
address << StringPrintf(" + %d", *reinterpret_cast<const int8_t*>(*instr));
(*instr)++;
} else if (mod == 2) {
address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(*instr));
(*instr) += 4;
}
address << "]";
}
}
return address.str();
}
size_t DisassemblerX86::DumpNops(std::ostream& os, const uint8_t* instr) {
static constexpr uint8_t kNops[][10] = {
{ },
{ 0x90 },
{ 0x66, 0x90 },
{ 0x0f, 0x1f, 0x00 },
{ 0x0f, 0x1f, 0x40, 0x00 },
{ 0x0f, 0x1f, 0x44, 0x00, 0x00 },
{ 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00 },
{ 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00 },
{ 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 }
};
for (size_t i = 1; i < arraysize(kNops); ++i) {
if (memcmp(instr, kNops[i], i) == 0) {
os << FormatInstructionPointer(instr)
<< StringPrintf(": %22s \t nop \n", DumpCodeHex(instr, instr + i).c_str());
return i;
}
}
return 0;
}
size_t DisassemblerX86::DumpInstruction(std::ostream& os, const uint8_t* instr) {
size_t nop_size = DumpNops(os, instr);
if (nop_size != 0u) {
return nop_size;
}
const uint8_t* begin_instr = instr;
bool have_prefixes = true;
uint8_t prefix[4] = {0, 0, 0, 0};
do {
switch (*instr) {
// Group 1 - lock and repeat prefixes:
case 0xF0:
case 0xF2:
case 0xF3:
prefix[0] = *instr;
break;
// Group 2 - segment override prefixes:
case kCs:
case kSs:
case kDs:
case kEs:
case kFs:
case kGs:
prefix[1] = *instr;
break;
// Group 3 - operand size override:
case 0x66:
prefix[2] = *instr;
break;
// Group 4 - address size override:
case 0x67:
prefix[3] = *instr;
break;
default:
have_prefixes = false;
break;
}
if (have_prefixes) {
instr++;
}
} while (have_prefixes);
uint8_t rex = (supports_rex_ && (*instr >= 0x40) && (*instr <= 0x4F)) ? *instr : 0;
if (rex != 0) {
instr++;
}
const char** modrm_opcodes = nullptr;
bool has_modrm = false;
bool reg_is_opcode = false;
size_t immediate_bytes = 0;
size_t branch_bytes = 0;
std::string opcode_tmp; // Storage to keep StringPrintf result alive.
const char* opcode0 = ""; // Prefix part.
const char* opcode1 = ""; // Main opcode.
const char* opcode2 = ""; // Sub-opcode. E.g., jump type.
const char* opcode3 = ""; // Mod-rm part.
const char* opcode4 = ""; // Suffix part.
bool store = false; // stores to memory (ie rm is on the left)
bool load = false; // loads from memory (ie rm is on the right)
bool byte_operand = false; // true when the opcode is dealing with byte operands
// true when the source operand is a byte register but the target register isn't
// (ie movsxb/movzxb).
bool byte_second_operand = false;
bool target_specific = false; // register name depends on target (64 vs 32 bits).
bool ax = false; // implicit use of ax
bool cx = false; // implicit use of cx
bool reg_in_opcode = false; // low 3-bits of opcode encode register parameter
bool no_ops = false;
RegFile src_reg_file = GPR;
RegFile dst_reg_file = GPR;
switch (*instr) {
#define DISASSEMBLER_ENTRY(opname, \
rm8_r8, rm32_r32, \
r8_rm8, r32_rm32, \
ax8_i8, ax32_i32) \
case rm8_r8: opcode1 = #opname; store = true; has_modrm = true; byte_operand = true; break; \
case rm32_r32: opcode1 = #opname; store = true; has_modrm = true; break; \
case r8_rm8: opcode1 = #opname; load = true; has_modrm = true; byte_operand = true; break; \
case r32_rm32: opcode1 = #opname; load = true; has_modrm = true; break; \
case ax8_i8: opcode1 = #opname; ax = true; immediate_bytes = 1; byte_operand = true; break; \
case ax32_i32: opcode1 = #opname; ax = true; immediate_bytes = 4; break;
DISASSEMBLER_ENTRY(add,
0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,
0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,
0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */)
DISASSEMBLER_ENTRY(or,
0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,
0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,
0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */)
DISASSEMBLER_ENTRY(adc,
0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,
0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,
0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */)
DISASSEMBLER_ENTRY(sbb,
0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,
0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,
0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */)
DISASSEMBLER_ENTRY(and,
0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,
0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,
0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */)
DISASSEMBLER_ENTRY(sub,
0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,
0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,
0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */)
DISASSEMBLER_ENTRY(xor,
0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,
0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,
0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */)
DISASSEMBLER_ENTRY(cmp,
0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem/Reg32 */,
0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,
0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */)
#undef DISASSEMBLER_ENTRY
case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
opcode1 = "push";
reg_in_opcode = true;
target_specific = true;
break;
case 0x58: case 0x59: case 0x5A: case 0x5B: case 0x5C: case 0x5D: case 0x5E: case 0x5F:
opcode1 = "pop";
reg_in_opcode = true;
target_specific = true;
break;
case 0x63:
if ((rex & REX_W) != 0) {
opcode1 = "movsxd";
has_modrm = true;
load = true;
} else {
// In 32-bit mode (!supports_rex_) this is ARPL, with no REX prefix the functionality is the
// same as 'mov' but the use of the instruction is discouraged.
opcode_tmp = StringPrintf("unknown opcode '%02X'", *instr);
opcode1 = opcode_tmp.c_str();
}
break;
case 0x68: opcode1 = "push"; immediate_bytes = 4; break;
case 0x69: opcode1 = "imul"; load = true; has_modrm = true; immediate_bytes = 4; break;
case 0x6A: opcode1 = "push"; immediate_bytes = 1; break;
case 0x6B: opcode1 = "imul"; load = true; has_modrm = true; immediate_bytes = 1; break;
case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77:
case 0x78: case 0x79: case 0x7A: case 0x7B: case 0x7C: case 0x7D: case 0x7E: case 0x7F:
static const char* condition_codes[] =
{"o", "no", "b/nae/c", "nb/ae/nc", "z/eq", "nz/ne", "be/na", "nbe/a",
"s", "ns", "p/pe", "np/po", "l/nge", "nl/ge", "le/ng", "nle/g"
};
opcode1 = "j";
opcode2 = condition_codes[*instr & 0xF];
branch_bytes = 1;
break;
case 0x86: case 0x87:
opcode1 = "xchg";
store = true;
has_modrm = true;
byte_operand = (*instr == 0x86);
break;
case 0x88: opcode1 = "mov"; store = true; has_modrm = true; byte_operand = true; break;
case 0x89: opcode1 = "mov"; store = true; has_modrm = true; break;
case 0x8A: opcode1 = "mov"; load = true; has_modrm = true; byte_operand = true; break;
case 0x8B: opcode1 = "mov"; load = true; has_modrm = true; break;
case 0x9D: opcode1 = "popf"; break;
case 0x0F: // 2 byte extended opcode
instr++;
switch (*instr) {
case 0x10: case 0x11:
if (prefix[0] == 0xF2) {
opcode1 = "movsd";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF3) {
opcode1 = "movss";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[2] == 0x66) {
opcode1 = "movupd";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
opcode1 = "movups";
}
has_modrm = true;
src_reg_file = dst_reg_file = SSE;
load = *instr == 0x10;
store = !load;
break;
case 0x12: case 0x13:
if (prefix[2] == 0x66) {
opcode1 = "movlpd";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0) {
opcode1 = "movlps";
}
has_modrm = true;
src_reg_file = dst_reg_file = SSE;
load = *instr == 0x12;
store = !load;
break;
case 0x16: case 0x17:
if (prefix[2] == 0x66) {
opcode1 = "movhpd";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0) {
opcode1 = "movhps";
}
has_modrm = true;
src_reg_file = dst_reg_file = SSE;
load = *instr == 0x16;
store = !load;
break;
case 0x28: case 0x29:
if (prefix[2] == 0x66) {
opcode1 = "movapd";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0) {
opcode1 = "movaps";
}
has_modrm = true;
src_reg_file = dst_reg_file = SSE;
load = *instr == 0x28;
store = !load;
break;
case 0x2A:
if (prefix[2] == 0x66) {
opcode1 = "cvtpi2pd";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF2) {
opcode1 = "cvtsi2sd";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF3) {
opcode1 = "cvtsi2ss";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
opcode1 = "cvtpi2ps";
}
load = true;
has_modrm = true;
dst_reg_file = SSE;
break;
case 0x2C:
if (prefix[2] == 0x66) {
opcode1 = "cvttpd2pi";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF2) {
opcode1 = "cvttsd2si";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF3) {
opcode1 = "cvttss2si";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
opcode1 = "cvttps2pi";
}
load = true;
has_modrm = true;
src_reg_file = SSE;
break;
case 0x2D:
if (prefix[2] == 0x66) {
opcode1 = "cvtpd2pi";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF2) {
opcode1 = "cvtsd2si";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF3) {
opcode1 = "cvtss2si";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
opcode1 = "cvtps2pi";
}
load = true;
has_modrm = true;
src_reg_file = SSE;
break;
case 0x2E:
opcode0 = "u";
FALLTHROUGH_INTENDED;
case 0x2F:
if (prefix[2] == 0x66) {
opcode1 = "comisd";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
opcode1 = "comiss";
}
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x38: // 3 byte extended opcode
instr++;
if (prefix[2] == 0x66) {
switch (*instr) {
case 0x01:
opcode1 = "phaddw";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x02:
opcode1 = "phaddd";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x29:
opcode1 = "pcmpeqq";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x37:
opcode1 = "pcmpgtq";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x38:
opcode1 = "pminsb";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x39:
opcode1 = "pminsd";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x3A:
opcode1 = "pminuw";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x3B:
opcode1 = "pminud";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x3C:
opcode1 = "pmaxsb";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x3D:
opcode1 = "pmaxsd";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x3E:
opcode1 = "pmaxuw";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x3F:
opcode1 = "pmaxud";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x40:
opcode1 = "pmulld";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = dst_reg_file = SSE;
break;
default:
opcode_tmp = StringPrintf("unknown opcode '0F 38 %02X'", *instr);
opcode1 = opcode_tmp.c_str();
}
} else {
opcode_tmp = StringPrintf("unknown opcode '0F 38 %02X'", *instr);
opcode1 = opcode_tmp.c_str();
}
break;
case 0x3A: // 3 byte extended opcode
instr++;
if (prefix[2] == 0x66) {
switch (*instr) {
case 0x0A:
opcode1 = "roundss";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = SSE;
dst_reg_file = SSE;
immediate_bytes = 1;
break;
case 0x0B:
opcode1 = "roundsd";
prefix[2] = 0;
has_modrm = true;
load = true;
src_reg_file = SSE;
dst_reg_file = SSE;
immediate_bytes = 1;
break;
case 0x14:
opcode1 = "pextrb";
prefix[2] = 0;
has_modrm = true;
store = true;
src_reg_file = SSE;
immediate_bytes = 1;
break;
case 0x15:
opcode1 = "pextrw";
prefix[2] = 0;
has_modrm = true;
store = true;
src_reg_file = SSE;
immediate_bytes = 1;
break;
case 0x16:
opcode1 = "pextrd";
prefix[2] = 0;
has_modrm = true;
store = true;
src_reg_file = SSE;
immediate_bytes = 1;
break;
default:
opcode_tmp = StringPrintf("unknown opcode '0F 3A %02X'", *instr);
opcode1 = opcode_tmp.c_str();
}
} else {
opcode_tmp = StringPrintf("unknown opcode '0F 3A %02X'", *instr);
opcode1 = opcode_tmp.c_str();
}
break;
case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
case 0x48: case 0x49: case 0x4A: case 0x4B: case 0x4C: case 0x4D: case 0x4E: case 0x4F:
opcode1 = "cmov";
opcode2 = condition_codes[*instr & 0xF];
has_modrm = true;
load = true;
break;
case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
case 0x58: case 0x59: case 0x5C: case 0x5D: case 0x5E: case 0x5F: {
switch (*instr) {
case 0x50: opcode1 = "movmsk"; break;
case 0x51: opcode1 = "sqrt"; break;
case 0x52: opcode1 = "rsqrt"; break;
case 0x53: opcode1 = "rcp"; break;
case 0x54: opcode1 = "and"; break;
case 0x55: opcode1 = "andn"; break;
case 0x56: opcode1 = "or"; break;
case 0x57: opcode1 = "xor"; break;
case 0x58: opcode1 = "add"; break;
case 0x59: opcode1 = "mul"; break;
case 0x5C: opcode1 = "sub"; break;
case 0x5D: opcode1 = "min"; break;
case 0x5E: opcode1 = "div"; break;
case 0x5F: opcode1 = "max"; break;
default: LOG(FATAL) << "Unreachable"; UNREACHABLE();
}
if (prefix[2] == 0x66) {
opcode2 = "pd";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF2) {
opcode2 = "sd";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF3) {
opcode2 = "ss";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
opcode2 = "ps";
}
load = true;
has_modrm = true;
src_reg_file = dst_reg_file = SSE;
break;
}
case 0x5A:
if (prefix[2] == 0x66) {
opcode1 = "cvtpd2ps";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF2) {
opcode1 = "cvtsd2ss";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF3) {
opcode1 = "cvtss2sd";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
opcode1 = "cvtps2pd";
}
load = true;
has_modrm = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x5B:
if (prefix[2] == 0x66) {
opcode1 = "cvtps2dq";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF2) {
opcode1 = "bad opcode F2 0F 5B";
} else if (prefix[0] == 0xF3) {
opcode1 = "cvttps2dq";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
opcode1 = "cvtdq2ps";
}
load = true;
has_modrm = true;
src_reg_file = dst_reg_file = SSE;
break;
case 0x60: case 0x61: case 0x62: case 0x6C:
case 0x68: case 0x69: case 0x6A: case 0x6D:
if (prefix[2] == 0x66) {
src_reg_file = dst_reg_file = SSE;
prefix[2] = 0; // Clear prefix now. It has served its purpose as part of the opcode.
} else {
src_reg_file = dst_reg_file = MMX;
}
switch (*instr) {
case 0x60: opcode1 = "punpcklbw"; break;
case 0x61: opcode1 = "punpcklwd"; break;
case 0x62: opcode1 = "punpckldq"; break;
case 0x6c: opcode1 = "punpcklqdq"; break;
case 0x68: opcode1 = "punpckhbw"; break;
case 0x69: opcode1 = "punpckhwd"; break;
case 0x6A: opcode1 = "punpckhdq"; break;
case 0x6D: opcode1 = "punpckhqdq"; break;
}
load = true;
has_modrm = true;
break;
case 0x64:
case 0x65:
case 0x66:
if (prefix[2] == 0x66) {
src_reg_file = dst_reg_file = SSE;
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
src_reg_file = dst_reg_file = MMX;
}
switch (*instr) {
case 0x64: opcode1 = "pcmpgtb"; break;
case 0x65: opcode1 = "pcmpgtw"; break;
case 0x66: opcode1 = "pcmpgtd"; break;
}
prefix[2] = 0;
has_modrm = true;
load = true;
break;
case 0x6E:
if (prefix[2] == 0x66) {
dst_reg_file = SSE;
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
dst_reg_file = MMX;
}
opcode1 = "movd";
load = true;
has_modrm = true;
break;
case 0x6F:
if (prefix[2] == 0x66) {
src_reg_file = dst_reg_file = SSE;
opcode1 = "movdqa";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF3) {
src_reg_file = dst_reg_file = SSE;
opcode1 = "movdqu";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
dst_reg_file = MMX;
opcode1 = "movq";
}
load = true;
has_modrm = true;
break;
case 0x70:
if (prefix[2] == 0x66) {
opcode1 = "pshufd";
prefix[2] = 0;
has_modrm = true;
store = true;
src_reg_file = dst_reg_file = SSE;
immediate_bytes = 1;
} else if (prefix[0] == 0xF2) {
opcode1 = "pshuflw";
prefix[0] = 0;
has_modrm = true;
store = true;
src_reg_file = dst_reg_file = SSE;
immediate_bytes = 1;
} else {
opcode_tmp = StringPrintf("unknown opcode '0F %02X'", *instr);
opcode1 = opcode_tmp.c_str();
}
break;
case 0x71:
if (prefix[2] == 0x66) {
dst_reg_file = SSE;
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
dst_reg_file = MMX;
}
static const char* x71_opcodes[] = {
"unknown-71", "unknown-71", "psrlw", "unknown-71",
"psraw", "unknown-71", "psllw", "unknown-71"};
modrm_opcodes = x71_opcodes;
reg_is_opcode = true;
has_modrm = true;
store = true;
immediate_bytes = 1;
break;
case 0x72:
if (prefix[2] == 0x66) {
dst_reg_file = SSE;
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
dst_reg_file = MMX;
}
static const char* x72_opcodes[] = {
"unknown-72", "unknown-72", "psrld", "unknown-72",
"psrad", "unknown-72", "pslld", "unknown-72"};
modrm_opcodes = x72_opcodes;
reg_is_opcode = true;
has_modrm = true;
store = true;
immediate_bytes = 1;
break;
case 0x73:
if (prefix[2] == 0x66) {
dst_reg_file = SSE;
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
dst_reg_file = MMX;
}
static const char* x73_opcodes[] = {
"unknown-73", "unknown-73", "psrlq", "psrldq",
"unknown-73", "unknown-73", "psllq", "unknown-73"};
modrm_opcodes = x73_opcodes;
reg_is_opcode = true;
has_modrm = true;
store = true;
immediate_bytes = 1;
break;
case 0x74:
case 0x75:
case 0x76:
if (prefix[2] == 0x66) {
src_reg_file = dst_reg_file = SSE;
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
src_reg_file = dst_reg_file = MMX;
}
switch (*instr) {
case 0x74: opcode1 = "pcmpeqb"; break;
case 0x75: opcode1 = "pcmpeqw"; break;
case 0x76: opcode1 = "pcmpeqd"; break;
}
prefix[2] = 0;
has_modrm = true;
load = true;
break;
case 0x7C:
if (prefix[0] == 0xF2) {
opcode1 = "haddps";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[2] == 0x66) {
opcode1 = "haddpd";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
opcode_tmp = StringPrintf("unknown opcode '0F %02X'", *instr);
opcode1 = opcode_tmp.c_str();
break;
}
src_reg_file = dst_reg_file = SSE;
has_modrm = true;
load = true;
break;
case 0x7E:
if (prefix[2] == 0x66) {
src_reg_file = SSE;
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
src_reg_file = MMX;
}
opcode1 = "movd";
has_modrm = true;
store = true;
break;
case 0x7F:
if (prefix[2] == 0x66) {
src_reg_file = dst_reg_file = SSE;
opcode1 = "movdqa";
prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode
} else if (prefix[0] == 0xF3) {
src_reg_file = dst_reg_file = SSE;
opcode1 = "movdqu";
prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode
} else {
dst_reg_file = MMX;
opcode1 = "movq";
}