From 32b7bd2dce112e74add07f5f2b2278724c91ffa5 Mon Sep 17 00:00:00 2001 From: Kevin Qin <36599815+Kevin99214@users.noreply.github.com> Date: Tue, 8 Jan 2019 22:00:30 -0500 Subject: [PATCH] Add files via upload --- DE1_SoC_Audio_Example.qpf | 30 ++ DE1_SoC_Audio_Example.qsf | 324 +++++++++++++++ DE1_SoC_Audio_Example.qsf.bak | 62 +++ DE1_SoC_Audio_Example.qws | Bin 0 -> 868 bytes Display.qpf | 30 ++ Display.qsf | 341 +++++++++++++++ Display.qsf.bak | 83 ++++ Display.qws | Bin 0 -> 1275 bytes Display.v | 242 +++++++++++ Display.v.bak | 3 + FinalProject.qpf | 30 ++ FinalProject.qsf | 751 ++++++++++++++++++++++++++++++++++ FinalProject.qsf.bak | 751 ++++++++++++++++++++++++++++++++++ FinalProject.qws | Bin 0 -> 2839 bytes black.mif | 127 ++++++ c5_pin_model_dump.txt | 118 ++++++ displaytest.txt | 273 ++++++++++++ mario.qip | 5 + mario.v | 174 ++++++++ marioT.qip | 5 + marioT.v | 174 ++++++++ pokemon.qip | 5 + pokemon.v | 174 ++++++++ pokemonMIf.v | 174 ++++++++ pokemonMif.qip | 5 + pokemonT.qip | 5 + pokemonT.v | 174 ++++++++ rocky.qip | 5 + rocky.v | 174 ++++++++ rockyT.qip | 5 + rockyT.v | 174 ++++++++ zelda.qip | 5 + zelda.v | 174 ++++++++ zeldaT.qip | 5 + zeldaT.v | 174 ++++++++ 35 files changed, 4776 insertions(+) create mode 100644 DE1_SoC_Audio_Example.qpf create mode 100644 DE1_SoC_Audio_Example.qsf create mode 100644 DE1_SoC_Audio_Example.qsf.bak create mode 100644 DE1_SoC_Audio_Example.qws create mode 100644 Display.qpf create mode 100644 Display.qsf create mode 100644 Display.qsf.bak create mode 100644 Display.qws create mode 100644 Display.v create mode 100644 Display.v.bak create mode 100644 FinalProject.qpf create mode 100644 FinalProject.qsf create mode 100644 FinalProject.qsf.bak create mode 100644 FinalProject.qws create mode 100644 black.mif create mode 100644 c5_pin_model_dump.txt create mode 100644 displaytest.txt create mode 100644 mario.qip create mode 100644 mario.v create mode 100644 marioT.qip create mode 100644 marioT.v create mode 100644 pokemon.qip create mode 100644 pokemon.v create mode 100644 pokemonMIf.v create mode 100644 pokemonMif.qip create mode 100644 pokemonT.qip create mode 100644 pokemonT.v create mode 100644 rocky.qip create mode 100644 rocky.v create mode 100644 rockyT.qip create mode 100644 rockyT.v create mode 100644 zelda.qip create mode 100644 zelda.v create mode 100644 zeldaT.qip create mode 100644 zeldaT.v diff --git a/DE1_SoC_Audio_Example.qpf b/DE1_SoC_Audio_Example.qpf new file mode 100644 index 0000000..883e8bc --- /dev/null +++ b/DE1_SoC_Audio_Example.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition +# Date created = 21:45:46 November 15, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.0" +DATE = "21:45:46 November 15, 2018" + +# Revisions + +PROJECT_REVISION = "DE1_SoC_Audio_Example" diff --git a/DE1_SoC_Audio_Example.qsf b/DE1_SoC_Audio_Example.qsf new file mode 100644 index 0000000..9e94410 --- /dev/null +++ b/DE1_SoC_Audio_Example.qsf @@ -0,0 +1,324 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition +# Date created = 21:45:46 November 15, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# DE1_SoC_Audio_Example_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA5F31C6 +set_global_assignment -name TOP_LEVEL_ENTITY finalProjectMif +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:45:46 NOVEMBER 15, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/avconf/I2C_Controller.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/avconf/avconf.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Audio_Controller.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Audio_Clock.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_SYNC_FIFO.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Clock_Edge.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Audio_Out_Serializer.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Audio_In_Deserializer.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Audio_Bit_Counter.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/DE1_SoC_Audio_Example.v" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_location_assignment PIN_AJ4 -to ADC_CS_N +set_location_assignment PIN_AK4 -to ADC_DIN +set_location_assignment PIN_AK3 -to ADC_DOUT +set_location_assignment PIN_AK2 -to ADC_SCLK +set_location_assignment PIN_K7 -to AUD_ADCDAT +set_location_assignment PIN_K8 -to AUD_ADCLRCK +set_location_assignment PIN_H7 -to AUD_BCLK +set_location_assignment PIN_J7 -to AUD_DACDAT +set_location_assignment PIN_H8 -to AUD_DACLRCK +set_location_assignment PIN_G7 -to AUD_XCK +set_location_assignment PIN_AF14 -to CLOCK_50 +set_location_assignment PIN_AA16 -to CLOCK2_50 +set_location_assignment PIN_Y26 -to CLOCK3_50 +set_location_assignment PIN_K14 -to CLOCK4_50 +set_location_assignment PIN_AK14 -to DRAM_ADDR[0] +set_location_assignment PIN_AH14 -to DRAM_ADDR[1] +set_location_assignment PIN_AG15 -to DRAM_ADDR[2] +set_location_assignment PIN_AE14 -to DRAM_ADDR[3] +set_location_assignment PIN_AB15 -to DRAM_ADDR[4] +set_location_assignment PIN_AC14 -to DRAM_ADDR[5] +set_location_assignment PIN_AD14 -to DRAM_ADDR[6] +set_location_assignment PIN_AF15 -to DRAM_ADDR[7] +set_location_assignment PIN_AH15 -to DRAM_ADDR[8] +set_location_assignment PIN_AG13 -to DRAM_ADDR[9] +set_location_assignment PIN_AG12 -to DRAM_ADDR[10] +set_location_assignment PIN_AH13 -to DRAM_ADDR[11] +set_location_assignment PIN_AJ14 -to DRAM_ADDR[12] +set_location_assignment PIN_AF13 -to DRAM_BA[0] +set_location_assignment PIN_AJ12 -to DRAM_BA[1] +set_location_assignment PIN_AF11 -to DRAM_CAS_N +set_location_assignment PIN_AK13 -to DRAM_CKE +set_location_assignment PIN_AH12 -to DRAM_CLK +set_location_assignment PIN_AG11 -to DRAM_CS_N +set_location_assignment PIN_AK6 -to DRAM_DQ[0] +set_location_assignment PIN_AJ7 -to DRAM_DQ[1] +set_location_assignment PIN_AK7 -to DRAM_DQ[2] +set_location_assignment PIN_AK8 -to DRAM_DQ[3] +set_location_assignment PIN_AK9 -to DRAM_DQ[4] +set_location_assignment PIN_AG10 -to DRAM_DQ[5] +set_location_assignment PIN_AK11 -to DRAM_DQ[6] +set_location_assignment PIN_AJ11 -to DRAM_DQ[7] +set_location_assignment PIN_AH10 -to DRAM_DQ[8] +set_location_assignment PIN_AJ10 -to DRAM_DQ[9] +set_location_assignment PIN_AJ9 -to DRAM_DQ[10] +set_location_assignment PIN_AH9 -to DRAM_DQ[11] +set_location_assignment PIN_AH8 -to DRAM_DQ[12] +set_location_assignment PIN_AH7 -to DRAM_DQ[13] +set_location_assignment PIN_AJ6 -to DRAM_DQ[14] +set_location_assignment PIN_AJ5 -to DRAM_DQ[15] +set_location_assignment PIN_AB13 -to DRAM_LDQM +set_location_assignment PIN_AE13 -to DRAM_RAS_N +set_location_assignment PIN_AK12 -to DRAM_UDQM +set_location_assignment PIN_AA13 -to DRAM_WE_N +set_location_assignment PIN_AA12 -to FAN_CTRL +set_location_assignment PIN_J12 -to FPGA_I2C_SCLK +set_location_assignment PIN_K12 -to FPGA_I2C_SDAT +set_location_assignment PIN_AC18 -to GPIO_0[0] +set_location_assignment PIN_AH18 -to GPIO_0[10] +set_location_assignment PIN_AH17 -to GPIO_0[11] +set_location_assignment PIN_AG16 -to GPIO_0[12] +set_location_assignment PIN_AE16 -to GPIO_0[13] +set_location_assignment PIN_AF16 -to GPIO_0[14] +set_location_assignment PIN_AG17 -to GPIO_0[15] +set_location_assignment PIN_AA18 -to GPIO_0[16] +set_location_assignment PIN_AA19 -to GPIO_0[17] +set_location_assignment PIN_AE17 -to GPIO_0[18] +set_location_assignment PIN_AC20 -to GPIO_0[19] +set_location_assignment PIN_Y17 -to GPIO_0[1] +set_location_assignment PIN_AH19 -to GPIO_0[20] +set_location_assignment PIN_AJ20 -to GPIO_0[21] +set_location_assignment PIN_AH20 -to GPIO_0[22] +set_location_assignment PIN_AK21 -to GPIO_0[23] +set_location_assignment PIN_AD19 -to GPIO_0[24] +set_location_assignment PIN_AD20 -to GPIO_0[25] +set_location_assignment PIN_AE18 -to GPIO_0[26] +set_location_assignment PIN_AE19 -to GPIO_0[27] +set_location_assignment PIN_AF20 -to GPIO_0[28] +set_location_assignment PIN_AF21 -to GPIO_0[29] +set_location_assignment PIN_AD17 -to GPIO_0[2] +set_location_assignment PIN_AF19 -to GPIO_0[30] +set_location_assignment PIN_AG21 -to GPIO_0[31] +set_location_assignment PIN_AF18 -to GPIO_0[32] +set_location_assignment PIN_AG20 -to GPIO_0[33] +set_location_assignment PIN_AG18 -to GPIO_0[34] +set_location_assignment PIN_AJ21 -to GPIO_0[35] +set_location_assignment PIN_Y18 -to GPIO_0[3] +set_location_assignment PIN_AK16 -to GPIO_0[4] +set_location_assignment PIN_AK18 -to GPIO_0[5] +set_location_assignment PIN_AK19 -to GPIO_0[6] +set_location_assignment PIN_AJ19 -to GPIO_0[7] +set_location_assignment PIN_AJ17 -to GPIO_0[8] +set_location_assignment PIN_AJ16 -to GPIO_0[9] +set_location_assignment PIN_AB17 -to GPIO_1[0] +set_location_assignment PIN_AG26 -to GPIO_1[10] +set_location_assignment PIN_AH24 -to GPIO_1[11] +set_location_assignment PIN_AH27 -to GPIO_1[12] +set_location_assignment PIN_AJ27 -to GPIO_1[13] +set_location_assignment PIN_AK29 -to GPIO_1[14] +set_location_assignment PIN_AK28 -to GPIO_1[15] +set_location_assignment PIN_AK27 -to GPIO_1[16] +set_location_assignment PIN_AJ26 -to GPIO_1[17] +set_location_assignment PIN_AK26 -to GPIO_1[18] +set_location_assignment PIN_AH25 -to GPIO_1[19] +set_location_assignment PIN_AA21 -to GPIO_1[1] +set_location_assignment PIN_AJ25 -to GPIO_1[20] +set_location_assignment PIN_AJ24 -to GPIO_1[21] +set_location_assignment PIN_AK24 -to GPIO_1[22] +set_location_assignment PIN_AG23 -to GPIO_1[23] +set_location_assignment PIN_AK23 -to GPIO_1[24] +set_location_assignment PIN_AH23 -to GPIO_1[25] +set_location_assignment PIN_AK22 -to GPIO_1[26] +set_location_assignment PIN_AJ22 -to GPIO_1[27] +set_location_assignment PIN_AH22 -to GPIO_1[28] +set_location_assignment PIN_AG22 -to GPIO_1[29] +set_location_assignment PIN_AB21 -to GPIO_1[2] +set_location_assignment PIN_AF24 -to GPIO_1[30] +set_location_assignment PIN_AF23 -to GPIO_1[31] +set_location_assignment PIN_AE22 -to GPIO_1[32] +set_location_assignment PIN_AD21 -to GPIO_1[33] +set_location_assignment PIN_AA20 -to GPIO_1[34] +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AC23 -to GPIO_1[3] +set_location_assignment PIN_AD24 -to GPIO_1[4] +set_location_assignment PIN_AE23 -to GPIO_1[5] +set_location_assignment PIN_AE24 -to GPIO_1[6] +set_location_assignment PIN_AF25 -to GPIO_1[7] +set_location_assignment PIN_AF26 -to GPIO_1[8] +set_location_assignment PIN_AG25 -to GPIO_1[9] +set_location_assignment PIN_AE26 -to HEX0[0] +set_location_assignment PIN_AE27 -to HEX0[1] +set_location_assignment PIN_AE28 -to HEX0[2] +set_location_assignment PIN_AG27 -to HEX0[3] +set_location_assignment PIN_AF28 -to HEX0[4] +set_location_assignment PIN_AG28 -to HEX0[5] +set_location_assignment PIN_AH28 -to HEX0[6] +set_location_assignment PIN_AJ29 -to HEX1[0] +set_location_assignment PIN_AH29 -to HEX1[1] +set_location_assignment PIN_AH30 -to HEX1[2] +set_location_assignment PIN_AG30 -to HEX1[3] +set_location_assignment PIN_AF29 -to HEX1[4] +set_location_assignment PIN_AF30 -to HEX1[5] +set_location_assignment PIN_AD27 -to HEX1[6] +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_AE29 -to HEX2[1] +set_location_assignment PIN_AD29 -to HEX2[2] +set_location_assignment PIN_AC28 -to HEX2[3] +set_location_assignment PIN_AD30 -to HEX2[4] +set_location_assignment PIN_AC29 -to HEX2[5] +set_location_assignment PIN_AC30 -to HEX2[6] +set_location_assignment PIN_AD26 -to HEX3[0] +set_location_assignment PIN_AC27 -to HEX3[1] +set_location_assignment PIN_AD25 -to HEX3[2] +set_location_assignment PIN_AC25 -to HEX3[3] +set_location_assignment PIN_AB28 -to HEX3[4] +set_location_assignment PIN_AB25 -to HEX3[5] +set_location_assignment PIN_AB22 -to HEX3[6] +set_location_assignment PIN_AA24 -to HEX4[0] +set_location_assignment PIN_Y23 -to HEX4[1] +set_location_assignment PIN_Y24 -to HEX4[2] +set_location_assignment PIN_W22 -to HEX4[3] +set_location_assignment PIN_W24 -to HEX4[4] +set_location_assignment PIN_V23 -to HEX4[5] +set_location_assignment PIN_W25 -to HEX4[6] +set_location_assignment PIN_V25 -to HEX5[0] +set_location_assignment PIN_AA28 -to HEX5[1] +set_location_assignment PIN_Y27 -to HEX5[2] +set_location_assignment PIN_AB27 -to HEX5[3] +set_location_assignment PIN_AB26 -to HEX5[4] +set_location_assignment PIN_AA26 -to HEX5[5] +set_location_assignment PIN_AA25 -to HEX5[6] +set_location_assignment PIN_AA30 -to IRDA_RXD +set_location_assignment PIN_AB30 -to IRDA_TXD +set_location_assignment PIN_AA14 -to KEY[0] +set_location_assignment PIN_AA15 -to KEY[1] +set_location_assignment PIN_W15 -to KEY[2] +set_location_assignment PIN_Y16 -to KEY[3] +set_location_assignment PIN_V16 -to LEDR[0] +set_location_assignment PIN_W16 -to LEDR[1] +set_location_assignment PIN_V17 -to LEDR[2] +set_location_assignment PIN_V18 -to LEDR[3] +set_location_assignment PIN_W17 -to LEDR[4] +set_location_assignment PIN_W19 -to LEDR[5] +set_location_assignment PIN_Y19 -to LEDR[6] +set_location_assignment PIN_W20 -to LEDR[7] +set_location_assignment PIN_W21 -to LEDR[8] +set_location_assignment PIN_Y21 -to LEDR[9] +set_location_assignment PIN_AD7 -to PS2_CLK +set_location_assignment PIN_AE7 -to PS2_DAT +set_location_assignment PIN_AD9 -to PS2_CLK2 +set_location_assignment PIN_AE9 -to PS2_DAT2 +set_location_assignment PIN_AB12 -to SW[0] +set_location_assignment PIN_AC12 -to SW[1] +set_location_assignment PIN_AF9 -to SW[2] +set_location_assignment PIN_AF10 -to SW[3] +set_location_assignment PIN_AD11 -to SW[4] +set_location_assignment PIN_AD12 -to SW[5] +set_location_assignment PIN_AE11 -to SW[6] +set_location_assignment PIN_AC9 -to SW[7] +set_location_assignment PIN_AD10 -to SW[8] +set_location_assignment PIN_AE12 -to SW[9] +set_location_assignment PIN_H15 -to TD_CLK27 +set_location_assignment PIN_D2 -to TD_DATA[0] +set_location_assignment PIN_B1 -to TD_DATA[1] +set_location_assignment PIN_E2 -to TD_DATA[2] +set_location_assignment PIN_B2 -to TD_DATA[3] +set_location_assignment PIN_D1 -to TD_DATA[4] +set_location_assignment PIN_E1 -to TD_DATA[5] +set_location_assignment PIN_C2 -to TD_DATA[6] +set_location_assignment PIN_B3 -to TD_DATA[7] +set_location_assignment PIN_A5 -to TD_HS +set_location_assignment PIN_F6 -to TD_RESET_N +set_location_assignment PIN_A3 -to TD_VS +set_location_assignment PIN_AF4 -to USB_B2_CLK +set_location_assignment PIN_AH4 -to USB_B2_DATA[0] +set_location_assignment PIN_AH3 -to USB_B2_DATA[1] +set_location_assignment PIN_AJ2 -to USB_B2_DATA[2] +set_location_assignment PIN_AJ1 -to USB_B2_DATA[3] +set_location_assignment PIN_AH2 -to USB_B2_DATA[4] +set_location_assignment PIN_AG3 -to USB_B2_DATA[5] +set_location_assignment PIN_AG2 -to USB_B2_DATA[6] +set_location_assignment PIN_AG1 -to USB_B2_DATA[7] +set_location_assignment PIN_AF5 -to USB_EMPTY +set_location_assignment PIN_AG5 -to USB_FULL +set_location_assignment PIN_AF6 -to USB_OE_N +set_location_assignment PIN_AG6 -to USB_RD_N +set_location_assignment PIN_AG7 -to USB_RESET_N +set_location_assignment PIN_AG8 -to USB_SCL +set_location_assignment PIN_AF8 -to USB_SDA +set_location_assignment PIN_AH5 -to USB_WR_N +set_location_assignment PIN_B13 -to VGA_B[0] +set_location_assignment PIN_G13 -to VGA_B[1] +set_location_assignment PIN_H13 -to VGA_B[2] +set_location_assignment PIN_F14 -to VGA_B[3] +set_location_assignment PIN_H14 -to VGA_B[4] +set_location_assignment PIN_F15 -to VGA_B[5] +set_location_assignment PIN_G15 -to VGA_B[6] +set_location_assignment PIN_J14 -to VGA_B[7] +set_location_assignment PIN_F10 -to VGA_BLANK_N +set_location_assignment PIN_A11 -to VGA_CLK +set_location_assignment PIN_J9 -to VGA_G[0] +set_location_assignment PIN_J10 -to VGA_G[1] +set_location_assignment PIN_H12 -to VGA_G[2] +set_location_assignment PIN_G10 -to VGA_G[3] +set_location_assignment PIN_G11 -to VGA_G[4] +set_location_assignment PIN_G12 -to VGA_G[5] +set_location_assignment PIN_F11 -to VGA_G[6] +set_location_assignment PIN_E11 -to VGA_G[7] +set_location_assignment PIN_B11 -to VGA_HS +set_location_assignment PIN_A13 -to VGA_R[0] +set_location_assignment PIN_C13 -to VGA_R[1] +set_location_assignment PIN_E13 -to VGA_R[2] +set_location_assignment PIN_B12 -to VGA_R[3] +set_location_assignment PIN_C12 -to VGA_R[4] +set_location_assignment PIN_D12 -to VGA_R[5] +set_location_assignment PIN_E12 -to VGA_R[6] +set_location_assignment PIN_F13 -to VGA_R[7] +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_D11 -to VGA_VS +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name QIP_FILE "../Final Project (mif export)/Audio_Demo/pokemonMif.qip" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/finalProjectMif.v" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/DE1_SoC_Audio_Example.qsf.bak b/DE1_SoC_Audio_Example.qsf.bak new file mode 100644 index 0000000..2731587 --- /dev/null +++ b/DE1_SoC_Audio_Example.qsf.bak @@ -0,0 +1,62 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition +# Date created = 21:45:46 November 15, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# DE1_SoC_Audio_Example_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA5F31C6 +set_global_assignment -name TOP_LEVEL_ENTITY DE1_SoC_Audio_Example +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:45:46 NOVEMBER 15, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/avconf/I2C_Controller.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/avconf/avconf.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Audio_Controller.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Audio_Clock.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_SYNC_FIFO.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Clock_Edge.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Audio_Out_Serializer.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Audio_In_Deserializer.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/Audio_Controller/Altera_UP_Audio_Bit_Counter.v" +set_global_assignment -name VERILOG_FILE "../Final Project (mif export)/Audio_Demo/DE1_SoC_Audio_Example.v" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/DE1_SoC_Audio_Example.qws b/DE1_SoC_Audio_Example.qws new file mode 100644 index 0000000000000000000000000000000000000000..8d45c45d1de2b97d04a042a1218e02ae1bc10a5d GIT binary patch literal 868 zcmc(dOD_Xa6vzKlnlx5cRu)}|l*F`zmK}msB_j6H&P=JcrWxarh&7+VXR))ivGrNh z<9CmCp+v&Qy*aNr|MR%#%xXb{GpV*}I#H^9ohw$N7FL&Ufg(U2l*;E8wWX$x@wAoK z4#-$XU;_Mk71Y7oK#O!iyvvkohNv~2D#RC4VFPamtq5|E>vN`U%i`;-U%RSHEo)I_ zRgj@p;B&|TyNou^4OK#`!9(+w&=#N?RT}Um)$v5S`meXRA$oVPH%Kqef<~lFf~@q+ z|BO1u{63}}Vu9zFVk~<@#4YM*pK{1tuWulffu>dEtqt4CIsP5K|%TH9K%l}P*{ zK7TV>NfAP<+?Tm?&wcamoSA#xY)Z}1t8L}9ud3E{q_Sd_Ko$1#iUQtW=;knCcHl7*2VEXR;>uHHBq3sPz;*$>zfb)8Xs5pXk zm0WW=z*p(nE@%Z`rk5L36kBUr@&mgd7x9E1l2_@oAS=c!rDZB9XzMqb>|nD&Csp~H zDsdmE_V8h(W6!++;i6X=8?pCQaSu*-n0Ay2vv%zKJmW}kbA9OtSq>i^{Zz5mMBL?* znPG37DKA7jS 26'd50000000) begin +// change <= change + 1'b1; +// counter <= 26'b0; +// end +// else +// counter <= counter + 1'b1; +// +// case(change) +// 5'd0: delay2 <= 16'd23889; +// 5'd1: delay2 <= 16'd22548; +// 5'd2: delay2 <= 16'd21283; +// 5'd3: delay2 <= 16'd20088; +// 5'd4: delay2 <= 16'd18961; +// 5'd5: delay2 <= 16'd17897; +// 5'd6: delay2 <= 16'd16892; +// 5'd7: delay2 <= 16'd15944; +// 5'd8: delay2 <= 16'd15049; +// 5'd9: delay2 <= 16'd14205; +// 5'd10: delay2 <= 16'd13407; +// 5'd11: delay2 <= 16'd12655; +// 5'd12: delay2 <= 16'd47778; +// 5'd13: delay2 <= 16'd45096; +// 5'd14: delay2 <= 16'd42566; +// 5'd15: delay2 <= 16'd40176; +// 5'd16: delay2 <= 16'd37922; +// 5'd17: delay2 <= 16'd35794; +// 5'd18: delay2 <= 16'd33784; +// 5'd19: delay2 <= 16'd31888; +// 5'd20: delay2 <= 16'd30098; +// 5'd21: delay2 <= 16'd28410; +// 5'd22: delay2 <= 16'd26814; +// 5'd23: delay2 <= 16'd25310; +// 5'd31: delay2 <= 16'd12345; +// endcase +// end + + draw d1(.clk(CLOCK_50), .reset(~KEY[0]), .delay(delay), + .x(x), .y(y), .c(colour), .enable_plot(enable_plot)); + +endmodule + +module draw(input clk, reset, input [15:0] delay, + output reg [7:0] x, output reg [6:0] y, output reg c, enable_plot); + + //internal wires for memory extract + wire c2, c3, c5, c7, c8, cC, cD, cE, cG, cGreat, cI, cJ, + cK, cLess, cM, cO, cQ, cR, cS, cU, cV, cW, cX, cZ; + + //internal count registers + reg [15:0] counter; + reg [7:0] countX; + reg [6:0] countY; + reg [15:0] letterToPrint; + reg printedFlag; + + //local parameters + localparam C = 16'd23889, + Cs = 16'd22548, + D = 16'd21283, + Ds = 16'd20088, + E = 16'd18961, + F = 16'd17897, + Fs = 16'd16892, + G = 16'd15944, + Gs = 16'd15049, + A = 16'd14205, + As = 16'd13407, + B = 16'd12655, + + Co = 16'd47778, + Cso = 16'd45096, + Do = 16'd42566, + Dso = 16'd40176, + Eo = 16'd37922, + Fo = 16'd35794, + Fso = 16'd33784, + Go = 16'd31888, + Gso = 16'd30098, + Ao = 16'd28410, + Aso = 16'd26814, + Bo = 16'd25310; + + //make sure letter is only printing once + always @(posedge clk) begin + if(reset) begin + printedFlag <= 1'b0; + letterToPrint <= 16'd0; + enable_plot <= 1'b0; + end + else begin + if((letterToPrint != delay)) begin + printedFlag <= 1'b0; + letterToPrint <= delay; + end + if((countX == 8'd63) && (countY==7'd63))begin + printedFlag <= 1'b1; + end + enable_plot <= ~printedFlag; + end + end + + //count though all the pixels that need to be drawn + always @(posedge clk) begin + if(reset) begin + countX <= 8'd0; + countY <= 7'd0; + counter <= 16'd1; + end + else if(!printedFlag) begin + countX <= countX + 1'b1; + counter <= counter + 1'b1; + //move to next row + if(countX == 8'd63) begin + countY <= countY + 1'b1; + countX <= 8'd0; + end + + //counted through the entire picture + if((countX == 8'd63) && (countY==7'd63))begin + countX <= 8'd0; + countY <= 7'd0; + counter <= 16'd1; + end + end + end + + //output to screen + always @(posedge clk) begin + if(reset) begin + x <= 8'd0; + y <= 7'd0; + end + else begin + x <= countX; + y <= countY; + end + end + + //extract from image mif note to play from image mif + two display2(.address(counter), .clock(clk), .q(c2)); + three display3(.address(counter), .clock(clk), .q(c3)); + five display5(.address(counter), .clock(clk), .q(c5)); + seven display7(.address(counter), .clock(clk), .q(c7)); + eight display8(.address(counter), .clock(clk), .q(c8)); + C displayC(.address(counter), .clock(clk), .q(cC)); + D displayD(.address(counter), .clock(clk), .q(cD)); + E displayE(.address(counter), .clock(clk), .q(cE)); + G displayG(.address(counter), .clock(clk), .q(cG)); + greater displayGrt(.address(counter), .clock(clk), .q(cGreat)); + I displayI(.address(counter), .clock(clk), .q(cI)); + J displayJ(.address(counter), .clock(clk), .q(cJ)); + K displayK(.address(counter), .clock(clk), .q(cK)); + less displayL(.address(counter), .clock(clk), .q(cLess)); + M displayM(.address(counter), .clock(clk), .q(cM)); + O displayO(.address(counter), .clock(clk), .q(cO)); + Q displayQ(.address(counter), .clock(clk), .q(cQ)); + R displayR(.address(counter), .clock(clk), .q(cR)); + S displayS(.address(counter), .clock(clk), .q(cS)); + U displayU(.address(counter), .clock(clk), .q(cU)); + V displayV(.address(counter), .clock(clk), .q(cV)); + W displayW(.address(counter), .clock(clk), .q(cW)); + X displayX(.address(counter), .clock(clk), .q(cX)); + Z displayZ(.address(counter), .clock(clk), .q(cZ)); + + //determine which mif to draw onto the screen + always@(posedge clk) begin + case(letterToPrint) + C: c = cZ; + Cs: c = cS; + D: c = cX; + Ds: c = cD; + E: c = cC; + F: c = cV; + Fs: c = cG; + G: c = cM; + Gs: c = cJ; + A: c = cLess; + As: c = cK; + B: c = cGreat; + + Co: c = cQ; + Cso: c = c2; + Do: c = cW; + Dso: c = c3; + Eo: c = cE; + Fo: c = cR; + Fso: c = c5; + Go: c = cU; + Gso: c = c7; + Ao: c = cI; + Aso: c = c8; + Bo: c = cO; + + default: c = 1'b0; + endcase + end +endmodule \ No newline at end of file diff --git a/Display.v.bak b/Display.v.bak new file mode 100644 index 0000000..cb403ac --- /dev/null +++ b/Display.v.bak @@ -0,0 +1,3 @@ +module display(); + +endmodule \ No newline at end of file diff --git a/FinalProject.qpf b/FinalProject.qpf new file mode 100644 index 0000000..21638e3 --- /dev/null +++ b/FinalProject.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition +# Date created = 01:30:17 November 11, 2018 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.0" +DATE = "01:30:17 November 11, 2018" + +# Revisions + +PROJECT_REVISION = "FinalProject" diff --git a/FinalProject.qsf b/FinalProject.qsf new file mode 100644 index 0000000..b9d2476 --- /dev/null +++ b/FinalProject.qsf @@ -0,0 +1,751 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition +# Date created = 01:30:17 November 11, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# FinalProject_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA5F31C6 +set_global_assignment -name TOP_LEVEL_ENTITY FinalProject +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:30:17 NOVEMBER 11, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_AJ4 -to ADC_CS_N +set_location_assignment PIN_AK4 -to ADC_DIN +set_location_assignment PIN_AK3 -to ADC_DOUT +set_location_assignment PIN_AK2 -to ADC_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DIN -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DOUT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK -entity DE1_SoC +set_location_assignment PIN_K7 -to AUD_ADCDAT +set_location_assignment PIN_K8 -to AUD_ADCLRCK +set_location_assignment PIN_H7 -to AUD_BCLK +set_location_assignment PIN_J7 -to AUD_DACDAT +set_location_assignment PIN_H8 -to AUD_DACLRCK +set_location_assignment PIN_G7 -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK -entity DE1_SoC +set_location_assignment PIN_AF14 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 -entity DE1_SoC +set_location_assignment PIN_AA16 -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 -entity DE1_SoC +set_location_assignment PIN_Y26 -to CLOCK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 -entity DE1_SoC +set_location_assignment PIN_K14 -to CLOCK4_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK4_50 -entity DE1_SoC +set_location_assignment PIN_AK14 -to DRAM_ADDR[0] +set_location_assignment PIN_AH14 -to DRAM_ADDR[1] +set_location_assignment PIN_AG15 -to DRAM_ADDR[2] +set_location_assignment PIN_AE14 -to DRAM_ADDR[3] +set_location_assignment PIN_AB15 -to DRAM_ADDR[4] +set_location_assignment PIN_AC14 -to DRAM_ADDR[5] +set_location_assignment PIN_AD14 -to DRAM_ADDR[6] +set_location_assignment PIN_AF15 -to DRAM_ADDR[7] +set_location_assignment PIN_AH15 -to DRAM_ADDR[8] +set_location_assignment PIN_AG13 -to DRAM_ADDR[9] +set_location_assignment PIN_AG12 -to DRAM_ADDR[10] +set_location_assignment PIN_AH13 -to DRAM_ADDR[11] +set_location_assignment PIN_AJ14 -to DRAM_ADDR[12] +set_location_assignment PIN_AF13 -to DRAM_BA[0] +set_location_assignment PIN_AJ12 -to DRAM_BA[1] +set_location_assignment PIN_AF11 -to DRAM_CAS_N +set_location_assignment PIN_AK13 -to DRAM_CKE +set_location_assignment PIN_AH12 -to DRAM_CLK +set_location_assignment PIN_AG11 -to DRAM_CS_N +set_location_assignment PIN_AK6 -to DRAM_DQ[0] +set_location_assignment PIN_AJ7 -to DRAM_DQ[1] +set_location_assignment PIN_AK7 -to DRAM_DQ[2] +set_location_assignment PIN_AK8 -to DRAM_DQ[3] +set_location_assignment PIN_AK9 -to DRAM_DQ[4] +set_location_assignment PIN_AG10 -to DRAM_DQ[5] +set_location_assignment PIN_AK11 -to DRAM_DQ[6] +set_location_assignment PIN_AJ11 -to DRAM_DQ[7] +set_location_assignment PIN_AH10 -to DRAM_DQ[8] +set_location_assignment PIN_AJ10 -to DRAM_DQ[9] +set_location_assignment PIN_AJ9 -to DRAM_DQ[10] +set_location_assignment PIN_AH9 -to DRAM_DQ[11] +set_location_assignment PIN_AH8 -to DRAM_DQ[12] +set_location_assignment PIN_AH7 -to DRAM_DQ[13] +set_location_assignment PIN_AJ6 -to DRAM_DQ[14] +set_location_assignment PIN_AJ5 -to DRAM_DQ[15] +set_location_assignment PIN_AB13 -to DRAM_LDQM +set_location_assignment PIN_AE13 -to DRAM_RAS_N +set_location_assignment PIN_AK12 -to DRAM_UDQM +set_location_assignment PIN_AA13 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N -entity DE1_SoC +set_location_assignment PIN_AA12 -to FAN_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL -entity DE1_SoC +set_location_assignment PIN_J12 -to FPGA_I2C_SCLK +set_location_assignment PIN_K12 -to FPGA_I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SCLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SDAT -entity DE1_SoC +set_location_assignment PIN_AC18 -to GPIO_0[0] +set_location_assignment PIN_AH18 -to GPIO_0[10] +set_location_assignment PIN_AH17 -to GPIO_0[11] +set_location_assignment PIN_AG16 -to GPIO_0[12] +set_location_assignment PIN_AE16 -to GPIO_0[13] +set_location_assignment PIN_AF16 -to GPIO_0[14] +set_location_assignment PIN_AG17 -to GPIO_0[15] +set_location_assignment PIN_AA18 -to GPIO_0[16] +set_location_assignment PIN_AA19 -to GPIO_0[17] +set_location_assignment PIN_AE17 -to GPIO_0[18] +set_location_assignment PIN_AC20 -to GPIO_0[19] +set_location_assignment PIN_Y17 -to GPIO_0[1] +set_location_assignment PIN_AH19 -to GPIO_0[20] +set_location_assignment PIN_AJ20 -to GPIO_0[21] +set_location_assignment PIN_AH20 -to GPIO_0[22] +set_location_assignment PIN_AK21 -to GPIO_0[23] +set_location_assignment PIN_AD19 -to GPIO_0[24] +set_location_assignment PIN_AD20 -to GPIO_0[25] +set_location_assignment PIN_AE18 -to GPIO_0[26] +set_location_assignment PIN_AE19 -to GPIO_0[27] +set_location_assignment PIN_AF20 -to GPIO_0[28] +set_location_assignment PIN_AF21 -to GPIO_0[29] +set_location_assignment PIN_AD17 -to GPIO_0[2] +set_location_assignment PIN_AF19 -to GPIO_0[30] +set_location_assignment PIN_AG21 -to GPIO_0[31] +set_location_assignment PIN_AF18 -to GPIO_0[32] +set_location_assignment PIN_AG20 -to GPIO_0[33] +set_location_assignment PIN_AG18 -to GPIO_0[34] +set_location_assignment PIN_AJ21 -to GPIO_0[35] +set_location_assignment PIN_Y18 -to GPIO_0[3] +set_location_assignment PIN_AK16 -to GPIO_0[4] +set_location_assignment PIN_AK18 -to GPIO_0[5] +set_location_assignment PIN_AK19 -to GPIO_0[6] +set_location_assignment PIN_AJ19 -to GPIO_0[7] +set_location_assignment PIN_AJ17 -to GPIO_0[8] +set_location_assignment PIN_AJ16 -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] -entity DE1_SoC +set_location_assignment PIN_AB17 -to GPIO_1[0] +set_location_assignment PIN_AG26 -to GPIO_1[10] +set_location_assignment PIN_AH24 -to GPIO_1[11] +set_location_assignment PIN_AH27 -to GPIO_1[12] +set_location_assignment PIN_AJ27 -to GPIO_1[13] +set_location_assignment PIN_AK29 -to GPIO_1[14] +set_location_assignment PIN_AK28 -to GPIO_1[15] +set_location_assignment PIN_AK27 -to GPIO_1[16] +set_location_assignment PIN_AJ26 -to GPIO_1[17] +set_location_assignment PIN_AK26 -to GPIO_1[18] +set_location_assignment PIN_AH25 -to GPIO_1[19] +set_location_assignment PIN_AA21 -to GPIO_1[1] +set_location_assignment PIN_AJ25 -to GPIO_1[20] +set_location_assignment PIN_AJ24 -to GPIO_1[21] +set_location_assignment PIN_AK24 -to GPIO_1[22] +set_location_assignment PIN_AG23 -to GPIO_1[23] +set_location_assignment PIN_AK23 -to GPIO_1[24] +set_location_assignment PIN_AH23 -to GPIO_1[25] +set_location_assignment PIN_AK22 -to GPIO_1[26] +set_location_assignment PIN_AJ22 -to GPIO_1[27] +set_location_assignment PIN_AH22 -to GPIO_1[28] +set_location_assignment PIN_AG22 -to GPIO_1[29] +set_location_assignment PIN_AB21 -to GPIO_1[2] +set_location_assignment PIN_AF24 -to GPIO_1[30] +set_location_assignment PIN_AF23 -to GPIO_1[31] +set_location_assignment PIN_AE22 -to GPIO_1[32] +set_location_assignment PIN_AD21 -to GPIO_1[33] +set_location_assignment PIN_AA20 -to GPIO_1[34] +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AC23 -to GPIO_1[3] +set_location_assignment PIN_AD24 -to GPIO_1[4] +set_location_assignment PIN_AE23 -to GPIO_1[5] +set_location_assignment PIN_AE24 -to GPIO_1[6] +set_location_assignment PIN_AF25 -to GPIO_1[7] +set_location_assignment PIN_AF26 -to GPIO_1[8] +set_location_assignment PIN_AG25 -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] -entity DE1_SoC +set_location_assignment PIN_AE26 -to HEX0[0] +set_location_assignment PIN_AE27 -to HEX0[1] +set_location_assignment PIN_AE28 -to HEX0[2] +set_location_assignment PIN_AG27 -to HEX0[3] +set_location_assignment PIN_AF28 -to HEX0[4] +set_location_assignment PIN_AG28 -to HEX0[5] +set_location_assignment PIN_AH28 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] -entity DE1_SoC +set_location_assignment PIN_AJ29 -to HEX1[0] +set_location_assignment PIN_AH29 -to HEX1[1] +set_location_assignment PIN_AH30 -to HEX1[2] +set_location_assignment PIN_AG30 -to HEX1[3] +set_location_assignment PIN_AF29 -to HEX1[4] +set_location_assignment PIN_AF30 -to HEX1[5] +set_location_assignment PIN_AD27 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] -entity DE1_SoC +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_AE29 -to HEX2[1] +set_location_assignment PIN_AD29 -to HEX2[2] +set_location_assignment PIN_AC28 -to HEX2[3] +set_location_assignment PIN_AD30 -to HEX2[4] +set_location_assignment PIN_AC29 -to HEX2[5] +set_location_assignment PIN_AC30 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] -entity DE1_SoC +set_location_assignment PIN_AD26 -to HEX3[0] +set_location_assignment PIN_AC27 -to HEX3[1] +set_location_assignment PIN_AD25 -to HEX3[2] +set_location_assignment PIN_AC25 -to HEX3[3] +set_location_assignment PIN_AB28 -to HEX3[4] +set_location_assignment PIN_AB25 -to HEX3[5] +set_location_assignment PIN_AB22 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] -entity DE1_SoC +set_location_assignment PIN_AA24 -to HEX4[0] +set_location_assignment PIN_Y23 -to HEX4[1] +set_location_assignment PIN_Y24 -to HEX4[2] +set_location_assignment PIN_W22 -to HEX4[3] +set_location_assignment PIN_W24 -to HEX4[4] +set_location_assignment PIN_V23 -to HEX4[5] +set_location_assignment PIN_W25 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] -entity DE1_SoC +set_location_assignment PIN_V25 -to HEX5[0] +set_location_assignment PIN_AA28 -to HEX5[1] +set_location_assignment PIN_Y27 -to HEX5[2] +set_location_assignment PIN_AB27 -to HEX5[3] +set_location_assignment PIN_AB26 -to HEX5[4] +set_location_assignment PIN_AA26 -to HEX5[5] +set_location_assignment PIN_AA25 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] -entity DE1_SoC +set_location_assignment PIN_AA30 -to IRDA_RXD +set_location_assignment PIN_AB30 -to IRDA_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_TXD -entity DE1_SoC +set_location_assignment PIN_AA14 -to KEY[0] +set_location_assignment PIN_AA15 -to KEY[1] +set_location_assignment PIN_W15 -to KEY[2] +set_location_assignment PIN_Y16 -to KEY[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] -entity DE1_SoC +set_location_assignment PIN_V16 -to LEDR[0] +set_location_assignment PIN_W16 -to LEDR[1] +set_location_assignment PIN_V17 -to LEDR[2] +set_location_assignment PIN_V18 -to LEDR[3] +set_location_assignment PIN_W17 -to LEDR[4] +set_location_assignment PIN_W19 -to LEDR[5] +set_location_assignment PIN_Y19 -to LEDR[6] +set_location_assignment PIN_W20 -to LEDR[7] +set_location_assignment PIN_W21 -to LEDR[8] +set_location_assignment PIN_Y21 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] -entity DE1_SoC +set_location_assignment PIN_AD7 -to PS2_CLK +set_location_assignment PIN_AE7 -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT -entity DE1_SoC +set_location_assignment PIN_AD9 -to PS2_CLK2 +set_location_assignment PIN_AE9 -to PS2_DAT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 -entity DE1_SoC +set_location_assignment PIN_AB12 -to SW[0] +set_location_assignment PIN_AC12 -to SW[1] +set_location_assignment PIN_AF9 -to SW[2] +set_location_assignment PIN_AF10 -to SW[3] +set_location_assignment PIN_AD11 -to SW[4] +set_location_assignment PIN_AD12 -to SW[5] +set_location_assignment PIN_AE11 -to SW[6] +set_location_assignment PIN_AC9 -to SW[7] +set_location_assignment PIN_AD10 -to SW[8] +set_location_assignment PIN_AE12 -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] -entity DE1_SoC +set_location_assignment PIN_H15 -to TD_CLK27 +set_location_assignment PIN_D2 -to TD_DATA[0] +set_location_assignment PIN_B1 -to TD_DATA[1] +set_location_assignment PIN_E2 -to TD_DATA[2] +set_location_assignment PIN_B2 -to TD_DATA[3] +set_location_assignment PIN_D1 -to TD_DATA[4] +set_location_assignment PIN_E1 -to TD_DATA[5] +set_location_assignment PIN_C2 -to TD_DATA[6] +set_location_assignment PIN_B3 -to TD_DATA[7] +set_location_assignment PIN_A5 -to TD_HS +set_location_assignment PIN_F6 -to TD_RESET_N +set_location_assignment PIN_A3 -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS -entity DE1_SoC +set_location_assignment PIN_AF4 -to USB_B2_CLK +set_location_assignment PIN_AH4 -to USB_B2_DATA[0] +set_location_assignment PIN_AH3 -to USB_B2_DATA[1] +set_location_assignment PIN_AJ2 -to USB_B2_DATA[2] +set_location_assignment PIN_AJ1 -to USB_B2_DATA[3] +set_location_assignment PIN_AH2 -to USB_B2_DATA[4] +set_location_assignment PIN_AG3 -to USB_B2_DATA[5] +set_location_assignment PIN_AG2 -to USB_B2_DATA[6] +set_location_assignment PIN_AG1 -to USB_B2_DATA[7] +set_location_assignment PIN_AF5 -to USB_EMPTY +set_location_assignment PIN_AG5 -to USB_FULL +set_location_assignment PIN_AF6 -to USB_OE_N +set_location_assignment PIN_AG6 -to USB_RD_N +set_location_assignment PIN_AG7 -to USB_RESET_N +set_location_assignment PIN_AG8 -to USB_SCL +set_location_assignment PIN_AF8 -to USB_SDA +set_location_assignment PIN_AH5 -to USB_WR_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_EMPTY -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FULL -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_OE_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RD_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RESET_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SCL -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SDA -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_WR_N -entity DE1_SoC +set_location_assignment PIN_B13 -to VGA_B[0] +set_location_assignment PIN_G13 -to VGA_B[1] +set_location_assignment PIN_H13 -to VGA_B[2] +set_location_assignment PIN_F14 -to VGA_B[3] +set_location_assignment PIN_H14 -to VGA_B[4] +set_location_assignment PIN_F15 -to VGA_B[5] +set_location_assignment PIN_G15 -to VGA_B[6] +set_location_assignment PIN_J14 -to VGA_B[7] +set_location_assignment PIN_F10 -to VGA_BLANK_N +set_location_assignment PIN_A11 -to VGA_CLK +set_location_assignment PIN_J9 -to VGA_G[0] +set_location_assignment PIN_J10 -to VGA_G[1] +set_location_assignment PIN_H12 -to VGA_G[2] +set_location_assignment PIN_G10 -to VGA_G[3] +set_location_assignment PIN_G11 -to VGA_G[4] +set_location_assignment PIN_G12 -to VGA_G[5] +set_location_assignment PIN_F11 -to VGA_G[6] +set_location_assignment PIN_E11 -to VGA_G[7] +set_location_assignment PIN_B11 -to VGA_HS +set_location_assignment PIN_A13 -to VGA_R[0] +set_location_assignment PIN_C13 -to VGA_R[1] +set_location_assignment PIN_E13 -to VGA_R[2] +set_location_assignment PIN_B12 -to VGA_R[3] +set_location_assignment PIN_C12 -to VGA_R[4] +set_location_assignment PIN_D12 -to VGA_R[5] +set_location_assignment PIN_E12 -to VGA_R[6] +set_location_assignment PIN_F13 -to VGA_R[7] +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_D11 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SCLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SDAT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CONTROL -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP -entity DE1_SoC +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_FILE ../../Display/vga_adapter/vga_pll.v +set_global_assignment -name QIP_FILE ../../Display/vga_adapter/vga_pll.qip +set_global_assignment -name VERILOG_FILE ../../Display/vga_adapter/vga_controller.v +set_global_assignment -name VERILOG_FILE ../../Display/vga_adapter/vga_address_translator.v +set_global_assignment -name VERILOG_FILE ../../Display/vga_adapter/vga_adapter.v +set_global_assignment -name VERILOG_FILE ../../Display/Display.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/Z.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/X.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/W.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/V.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/U.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/two.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/three.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/seven.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/S.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/R.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/Q.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/O.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/M.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/less.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/K.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/J.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/I.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/greater.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/G.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/five.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/eight.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/E.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/D.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/C.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/DE1_SoC_Audio_Example.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/avconf/I2C_Controller.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/avconf/avconf.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Audio_Controller.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Audio_Clock.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Altera_UP_SYNC_FIFO.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Altera_UP_Clock_Edge.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Altera_UP_Audio_Out_Serializer.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Altera_UP_Audio_In_Deserializer.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Altera_UP_Audio_Bit_Counter.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/FinalProject.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Altera_UP_PS2_Command_Out.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Altera_UP_PS2_Data_In.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Hexadecimal_To_Seven_Segment.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/PS2_Controller.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/PS2_Demo.v +set_global_assignment -name QIP_FILE pokemonT.qip +set_global_assignment -name QIP_FILE rocky.qip +set_global_assignment -name QIP_FILE rockyT.qip +set_global_assignment -name QIP_FILE pokemon.qip +set_global_assignment -name QIP_FILE zelda.qip +set_global_assignment -name QIP_FILE zeldaT.qip +set_global_assignment -name QIP_FILE mario.qip +set_global_assignment -name QIP_FILE marioT.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FinalProject.qsf.bak b/FinalProject.qsf.bak new file mode 100644 index 0000000..b9d2476 --- /dev/null +++ b/FinalProject.qsf.bak @@ -0,0 +1,751 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition +# Date created = 01:30:17 November 11, 2018 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# FinalProject_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEMA5F31C6 +set_global_assignment -name TOP_LEVEL_ENTITY FinalProject +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:30:17 NOVEMBER 11, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_AJ4 -to ADC_CS_N +set_location_assignment PIN_AK4 -to ADC_DIN +set_location_assignment PIN_AK3 -to ADC_DOUT +set_location_assignment PIN_AK2 -to ADC_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DIN -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DOUT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK -entity DE1_SoC +set_location_assignment PIN_K7 -to AUD_ADCDAT +set_location_assignment PIN_K8 -to AUD_ADCLRCK +set_location_assignment PIN_H7 -to AUD_BCLK +set_location_assignment PIN_J7 -to AUD_DACDAT +set_location_assignment PIN_H8 -to AUD_DACLRCK +set_location_assignment PIN_G7 -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK -entity DE1_SoC +set_location_assignment PIN_AF14 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 -entity DE1_SoC +set_location_assignment PIN_AA16 -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 -entity DE1_SoC +set_location_assignment PIN_Y26 -to CLOCK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 -entity DE1_SoC +set_location_assignment PIN_K14 -to CLOCK4_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK4_50 -entity DE1_SoC +set_location_assignment PIN_AK14 -to DRAM_ADDR[0] +set_location_assignment PIN_AH14 -to DRAM_ADDR[1] +set_location_assignment PIN_AG15 -to DRAM_ADDR[2] +set_location_assignment PIN_AE14 -to DRAM_ADDR[3] +set_location_assignment PIN_AB15 -to DRAM_ADDR[4] +set_location_assignment PIN_AC14 -to DRAM_ADDR[5] +set_location_assignment PIN_AD14 -to DRAM_ADDR[6] +set_location_assignment PIN_AF15 -to DRAM_ADDR[7] +set_location_assignment PIN_AH15 -to DRAM_ADDR[8] +set_location_assignment PIN_AG13 -to DRAM_ADDR[9] +set_location_assignment PIN_AG12 -to DRAM_ADDR[10] +set_location_assignment PIN_AH13 -to DRAM_ADDR[11] +set_location_assignment PIN_AJ14 -to DRAM_ADDR[12] +set_location_assignment PIN_AF13 -to DRAM_BA[0] +set_location_assignment PIN_AJ12 -to DRAM_BA[1] +set_location_assignment PIN_AF11 -to DRAM_CAS_N +set_location_assignment PIN_AK13 -to DRAM_CKE +set_location_assignment PIN_AH12 -to DRAM_CLK +set_location_assignment PIN_AG11 -to DRAM_CS_N +set_location_assignment PIN_AK6 -to DRAM_DQ[0] +set_location_assignment PIN_AJ7 -to DRAM_DQ[1] +set_location_assignment PIN_AK7 -to DRAM_DQ[2] +set_location_assignment PIN_AK8 -to DRAM_DQ[3] +set_location_assignment PIN_AK9 -to DRAM_DQ[4] +set_location_assignment PIN_AG10 -to DRAM_DQ[5] +set_location_assignment PIN_AK11 -to DRAM_DQ[6] +set_location_assignment PIN_AJ11 -to DRAM_DQ[7] +set_location_assignment PIN_AH10 -to DRAM_DQ[8] +set_location_assignment PIN_AJ10 -to DRAM_DQ[9] +set_location_assignment PIN_AJ9 -to DRAM_DQ[10] +set_location_assignment PIN_AH9 -to DRAM_DQ[11] +set_location_assignment PIN_AH8 -to DRAM_DQ[12] +set_location_assignment PIN_AH7 -to DRAM_DQ[13] +set_location_assignment PIN_AJ6 -to DRAM_DQ[14] +set_location_assignment PIN_AJ5 -to DRAM_DQ[15] +set_location_assignment PIN_AB13 -to DRAM_LDQM +set_location_assignment PIN_AE13 -to DRAM_RAS_N +set_location_assignment PIN_AK12 -to DRAM_UDQM +set_location_assignment PIN_AA13 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N -entity DE1_SoC +set_location_assignment PIN_AA12 -to FAN_CTRL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL -entity DE1_SoC +set_location_assignment PIN_J12 -to FPGA_I2C_SCLK +set_location_assignment PIN_K12 -to FPGA_I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SCLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SDAT -entity DE1_SoC +set_location_assignment PIN_AC18 -to GPIO_0[0] +set_location_assignment PIN_AH18 -to GPIO_0[10] +set_location_assignment PIN_AH17 -to GPIO_0[11] +set_location_assignment PIN_AG16 -to GPIO_0[12] +set_location_assignment PIN_AE16 -to GPIO_0[13] +set_location_assignment PIN_AF16 -to GPIO_0[14] +set_location_assignment PIN_AG17 -to GPIO_0[15] +set_location_assignment PIN_AA18 -to GPIO_0[16] +set_location_assignment PIN_AA19 -to GPIO_0[17] +set_location_assignment PIN_AE17 -to GPIO_0[18] +set_location_assignment PIN_AC20 -to GPIO_0[19] +set_location_assignment PIN_Y17 -to GPIO_0[1] +set_location_assignment PIN_AH19 -to GPIO_0[20] +set_location_assignment PIN_AJ20 -to GPIO_0[21] +set_location_assignment PIN_AH20 -to GPIO_0[22] +set_location_assignment PIN_AK21 -to GPIO_0[23] +set_location_assignment PIN_AD19 -to GPIO_0[24] +set_location_assignment PIN_AD20 -to GPIO_0[25] +set_location_assignment PIN_AE18 -to GPIO_0[26] +set_location_assignment PIN_AE19 -to GPIO_0[27] +set_location_assignment PIN_AF20 -to GPIO_0[28] +set_location_assignment PIN_AF21 -to GPIO_0[29] +set_location_assignment PIN_AD17 -to GPIO_0[2] +set_location_assignment PIN_AF19 -to GPIO_0[30] +set_location_assignment PIN_AG21 -to GPIO_0[31] +set_location_assignment PIN_AF18 -to GPIO_0[32] +set_location_assignment PIN_AG20 -to GPIO_0[33] +set_location_assignment PIN_AG18 -to GPIO_0[34] +set_location_assignment PIN_AJ21 -to GPIO_0[35] +set_location_assignment PIN_Y18 -to GPIO_0[3] +set_location_assignment PIN_AK16 -to GPIO_0[4] +set_location_assignment PIN_AK18 -to GPIO_0[5] +set_location_assignment PIN_AK19 -to GPIO_0[6] +set_location_assignment PIN_AJ19 -to GPIO_0[7] +set_location_assignment PIN_AJ17 -to GPIO_0[8] +set_location_assignment PIN_AJ16 -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[9] -entity DE1_SoC +set_location_assignment PIN_AB17 -to GPIO_1[0] +set_location_assignment PIN_AG26 -to GPIO_1[10] +set_location_assignment PIN_AH24 -to GPIO_1[11] +set_location_assignment PIN_AH27 -to GPIO_1[12] +set_location_assignment PIN_AJ27 -to GPIO_1[13] +set_location_assignment PIN_AK29 -to GPIO_1[14] +set_location_assignment PIN_AK28 -to GPIO_1[15] +set_location_assignment PIN_AK27 -to GPIO_1[16] +set_location_assignment PIN_AJ26 -to GPIO_1[17] +set_location_assignment PIN_AK26 -to GPIO_1[18] +set_location_assignment PIN_AH25 -to GPIO_1[19] +set_location_assignment PIN_AA21 -to GPIO_1[1] +set_location_assignment PIN_AJ25 -to GPIO_1[20] +set_location_assignment PIN_AJ24 -to GPIO_1[21] +set_location_assignment PIN_AK24 -to GPIO_1[22] +set_location_assignment PIN_AG23 -to GPIO_1[23] +set_location_assignment PIN_AK23 -to GPIO_1[24] +set_location_assignment PIN_AH23 -to GPIO_1[25] +set_location_assignment PIN_AK22 -to GPIO_1[26] +set_location_assignment PIN_AJ22 -to GPIO_1[27] +set_location_assignment PIN_AH22 -to GPIO_1[28] +set_location_assignment PIN_AG22 -to GPIO_1[29] +set_location_assignment PIN_AB21 -to GPIO_1[2] +set_location_assignment PIN_AF24 -to GPIO_1[30] +set_location_assignment PIN_AF23 -to GPIO_1[31] +set_location_assignment PIN_AE22 -to GPIO_1[32] +set_location_assignment PIN_AD21 -to GPIO_1[33] +set_location_assignment PIN_AA20 -to GPIO_1[34] +set_location_assignment PIN_AC22 -to GPIO_1[35] +set_location_assignment PIN_AC23 -to GPIO_1[3] +set_location_assignment PIN_AD24 -to GPIO_1[4] +set_location_assignment PIN_AE23 -to GPIO_1[5] +set_location_assignment PIN_AE24 -to GPIO_1[6] +set_location_assignment PIN_AF25 -to GPIO_1[7] +set_location_assignment PIN_AF26 -to GPIO_1[8] +set_location_assignment PIN_AG25 -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[13] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[14] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[15] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[16] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[17] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[18] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[19] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[20] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[21] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[22] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[23] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[24] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[25] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[26] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[27] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[28] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[29] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[30] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[31] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[32] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[33] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[34] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[35] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_1[9] -entity DE1_SoC +set_location_assignment PIN_AE26 -to HEX0[0] +set_location_assignment PIN_AE27 -to HEX0[1] +set_location_assignment PIN_AE28 -to HEX0[2] +set_location_assignment PIN_AG27 -to HEX0[3] +set_location_assignment PIN_AF28 -to HEX0[4] +set_location_assignment PIN_AG28 -to HEX0[5] +set_location_assignment PIN_AH28 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] -entity DE1_SoC +set_location_assignment PIN_AJ29 -to HEX1[0] +set_location_assignment PIN_AH29 -to HEX1[1] +set_location_assignment PIN_AH30 -to HEX1[2] +set_location_assignment PIN_AG30 -to HEX1[3] +set_location_assignment PIN_AF29 -to HEX1[4] +set_location_assignment PIN_AF30 -to HEX1[5] +set_location_assignment PIN_AD27 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] -entity DE1_SoC +set_location_assignment PIN_AB23 -to HEX2[0] +set_location_assignment PIN_AE29 -to HEX2[1] +set_location_assignment PIN_AD29 -to HEX2[2] +set_location_assignment PIN_AC28 -to HEX2[3] +set_location_assignment PIN_AD30 -to HEX2[4] +set_location_assignment PIN_AC29 -to HEX2[5] +set_location_assignment PIN_AC30 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] -entity DE1_SoC +set_location_assignment PIN_AD26 -to HEX3[0] +set_location_assignment PIN_AC27 -to HEX3[1] +set_location_assignment PIN_AD25 -to HEX3[2] +set_location_assignment PIN_AC25 -to HEX3[3] +set_location_assignment PIN_AB28 -to HEX3[4] +set_location_assignment PIN_AB25 -to HEX3[5] +set_location_assignment PIN_AB22 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] -entity DE1_SoC +set_location_assignment PIN_AA24 -to HEX4[0] +set_location_assignment PIN_Y23 -to HEX4[1] +set_location_assignment PIN_Y24 -to HEX4[2] +set_location_assignment PIN_W22 -to HEX4[3] +set_location_assignment PIN_W24 -to HEX4[4] +set_location_assignment PIN_V23 -to HEX4[5] +set_location_assignment PIN_W25 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] -entity DE1_SoC +set_location_assignment PIN_V25 -to HEX5[0] +set_location_assignment PIN_AA28 -to HEX5[1] +set_location_assignment PIN_Y27 -to HEX5[2] +set_location_assignment PIN_AB27 -to HEX5[3] +set_location_assignment PIN_AB26 -to HEX5[4] +set_location_assignment PIN_AA26 -to HEX5[5] +set_location_assignment PIN_AA25 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] -entity DE1_SoC +set_location_assignment PIN_AA30 -to IRDA_RXD +set_location_assignment PIN_AB30 -to IRDA_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_TXD -entity DE1_SoC +set_location_assignment PIN_AA14 -to KEY[0] +set_location_assignment PIN_AA15 -to KEY[1] +set_location_assignment PIN_W15 -to KEY[2] +set_location_assignment PIN_Y16 -to KEY[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] -entity DE1_SoC +set_location_assignment PIN_V16 -to LEDR[0] +set_location_assignment PIN_W16 -to LEDR[1] +set_location_assignment PIN_V17 -to LEDR[2] +set_location_assignment PIN_V18 -to LEDR[3] +set_location_assignment PIN_W17 -to LEDR[4] +set_location_assignment PIN_W19 -to LEDR[5] +set_location_assignment PIN_Y19 -to LEDR[6] +set_location_assignment PIN_W20 -to LEDR[7] +set_location_assignment PIN_W21 -to LEDR[8] +set_location_assignment PIN_Y21 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] -entity DE1_SoC +set_location_assignment PIN_AD7 -to PS2_CLK +set_location_assignment PIN_AE7 -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT -entity DE1_SoC +set_location_assignment PIN_AD9 -to PS2_CLK2 +set_location_assignment PIN_AE9 -to PS2_DAT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 -entity DE1_SoC +set_location_assignment PIN_AB12 -to SW[0] +set_location_assignment PIN_AC12 -to SW[1] +set_location_assignment PIN_AF9 -to SW[2] +set_location_assignment PIN_AF10 -to SW[3] +set_location_assignment PIN_AD11 -to SW[4] +set_location_assignment PIN_AD12 -to SW[5] +set_location_assignment PIN_AE11 -to SW[6] +set_location_assignment PIN_AC9 -to SW[7] +set_location_assignment PIN_AD10 -to SW[8] +set_location_assignment PIN_AE12 -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] -entity DE1_SoC +set_location_assignment PIN_H15 -to TD_CLK27 +set_location_assignment PIN_D2 -to TD_DATA[0] +set_location_assignment PIN_B1 -to TD_DATA[1] +set_location_assignment PIN_E2 -to TD_DATA[2] +set_location_assignment PIN_B2 -to TD_DATA[3] +set_location_assignment PIN_D1 -to TD_DATA[4] +set_location_assignment PIN_E1 -to TD_DATA[5] +set_location_assignment PIN_C2 -to TD_DATA[6] +set_location_assignment PIN_B3 -to TD_DATA[7] +set_location_assignment PIN_A5 -to TD_HS +set_location_assignment PIN_F6 -to TD_RESET_N +set_location_assignment PIN_A3 -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS -entity DE1_SoC +set_location_assignment PIN_AF4 -to USB_B2_CLK +set_location_assignment PIN_AH4 -to USB_B2_DATA[0] +set_location_assignment PIN_AH3 -to USB_B2_DATA[1] +set_location_assignment PIN_AJ2 -to USB_B2_DATA[2] +set_location_assignment PIN_AJ1 -to USB_B2_DATA[3] +set_location_assignment PIN_AH2 -to USB_B2_DATA[4] +set_location_assignment PIN_AG3 -to USB_B2_DATA[5] +set_location_assignment PIN_AG2 -to USB_B2_DATA[6] +set_location_assignment PIN_AG1 -to USB_B2_DATA[7] +set_location_assignment PIN_AF5 -to USB_EMPTY +set_location_assignment PIN_AG5 -to USB_FULL +set_location_assignment PIN_AF6 -to USB_OE_N +set_location_assignment PIN_AG6 -to USB_RD_N +set_location_assignment PIN_AG7 -to USB_RESET_N +set_location_assignment PIN_AG8 -to USB_SCL +set_location_assignment PIN_AF8 -to USB_SDA +set_location_assignment PIN_AH5 -to USB_WR_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_B2_DATA[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_EMPTY -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_FULL -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_OE_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RD_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_RESET_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SCL -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_SDA -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_WR_N -entity DE1_SoC +set_location_assignment PIN_B13 -to VGA_B[0] +set_location_assignment PIN_G13 -to VGA_B[1] +set_location_assignment PIN_H13 -to VGA_B[2] +set_location_assignment PIN_F14 -to VGA_B[3] +set_location_assignment PIN_H14 -to VGA_B[4] +set_location_assignment PIN_F15 -to VGA_B[5] +set_location_assignment PIN_G15 -to VGA_B[6] +set_location_assignment PIN_J14 -to VGA_B[7] +set_location_assignment PIN_F10 -to VGA_BLANK_N +set_location_assignment PIN_A11 -to VGA_CLK +set_location_assignment PIN_J9 -to VGA_G[0] +set_location_assignment PIN_J10 -to VGA_G[1] +set_location_assignment PIN_H12 -to VGA_G[2] +set_location_assignment PIN_G10 -to VGA_G[3] +set_location_assignment PIN_G11 -to VGA_G[4] +set_location_assignment PIN_G12 -to VGA_G[5] +set_location_assignment PIN_F11 -to VGA_G[6] +set_location_assignment PIN_E11 -to VGA_G[7] +set_location_assignment PIN_B11 -to VGA_HS +set_location_assignment PIN_A13 -to VGA_R[0] +set_location_assignment PIN_C13 -to VGA_R[1] +set_location_assignment PIN_E13 -to VGA_R[2] +set_location_assignment PIN_B12 -to VGA_R[3] +set_location_assignment PIN_C12 -to VGA_R[4] +set_location_assignment PIN_D12 -to VGA_R[5] +set_location_assignment PIN_E12 -to VGA_R[6] +set_location_assignment PIN_F13 -to VGA_R[7] +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_location_assignment PIN_D11 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_CONV_USB_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[9] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[13] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ADDR[14] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_BA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CAS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CKE -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_CK_P -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_CS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DM[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[8] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[9] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[10] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[11] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[12] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[13] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[14] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[15] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[16] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[17] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[18] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[19] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[20] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[21] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[22] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[23] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[24] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[25] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[26] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[27] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[28] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[29] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[30] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_DQ[31] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_N[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to HPS_DDR3_DQS_P[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_ODT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RAS_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_RESET_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "1.5 V" -to HPS_DDR3_RZQ -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to HPS_DDR3_WE_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_GTX_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_INT_N -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDC -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_MDIO -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_RX_DV -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_ENET_TX_EN -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_DCLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_FLASH_NCSO -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_GSENSOR_INT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SCLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C1_SDAT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SCLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C2_SDAT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_I2C_CONTROL -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_KEY -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LED -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_LTC_GPIO -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_CMD -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SD_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_CLK -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MISO -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_MOSI -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_SPIM_SS -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_CLKOUT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[0] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[1] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[2] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[3] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[4] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[5] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[6] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7] -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT -entity DE1_SoC +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP -entity DE1_SoC +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_FILE ../../Display/vga_adapter/vga_pll.v +set_global_assignment -name QIP_FILE ../../Display/vga_adapter/vga_pll.qip +set_global_assignment -name VERILOG_FILE ../../Display/vga_adapter/vga_controller.v +set_global_assignment -name VERILOG_FILE ../../Display/vga_adapter/vga_address_translator.v +set_global_assignment -name VERILOG_FILE ../../Display/vga_adapter/vga_adapter.v +set_global_assignment -name VERILOG_FILE ../../Display/Display.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/Z.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/X.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/W.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/V.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/U.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/two.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/three.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/seven.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/S.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/R.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/Q.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/O.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/M.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/less.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/K.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/J.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/I.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/greater.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/G.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/five.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/eight.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/E.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/D.v +set_global_assignment -name VERILOG_FILE ../../Display/Letters/C.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/DE1_SoC_Audio_Example.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/avconf/I2C_Controller.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/avconf/avconf.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Audio_Controller.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Audio_Clock.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Altera_UP_SYNC_FIFO.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Altera_UP_Clock_Edge.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Altera_UP_Audio_Out_Serializer.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Altera_UP_Audio_In_Deserializer.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Audio_Controller/Altera_UP_Audio_Bit_Counter.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/FinalProject.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Altera_UP_PS2_Command_Out.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Altera_UP_PS2_Data_In.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/Hexadecimal_To_Seven_Segment.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/PS2_Controller.v +set_global_assignment -name VERILOG_FILE Audio_Demo/Audio_Demo/PS2_Demo.v +set_global_assignment -name QIP_FILE pokemonT.qip +set_global_assignment -name QIP_FILE rocky.qip +set_global_assignment -name QIP_FILE rockyT.qip +set_global_assignment -name QIP_FILE pokemon.qip +set_global_assignment -name QIP_FILE zelda.qip +set_global_assignment -name QIP_FILE zeldaT.qip +set_global_assignment -name QIP_FILE mario.qip +set_global_assignment -name QIP_FILE marioT.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FinalProject.qws b/FinalProject.qws new file mode 100644 index 0000000000000000000000000000000000000000..1d824e668580edf631db74c39d5a42fac0c6e2f9 GIT binary patch literal 2839 zcmeH}&rTFU5XQe52r-^KdGfFtV>Tqavg-=yNdb)q4#s#RhAh(qt_#jOtcnn#Pv8r9 z^98(m_R0aTCMG_JApELl=CJF(ux=nR^rX7Fx~r?JtG=n3TV)mPf>zbky1H7_OC?Ix zM(QvZDMo1ox~JQEE~ggji<)D8jnUQL%-%)sDf?G-A8U!8pdVqssu$S039qs@>*vt5 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111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111; + 49C0: 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111; + 4A60: 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 000 000 000 000 000 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111 111; +END; \ No newline at end of file diff --git a/c5_pin_model_dump.txt b/c5_pin_model_dump.txt new file mode 100644 index 0000000..a895a64 --- /dev/null +++ b/c5_pin_model_dump.txt @@ -0,0 +1,118 @@ +io_4iomodule_c5_index: 55gpio_index: 2 +io_4iomodule_c5_index: 54gpio_index: 465 +io_4iomodule_c5_index: 33gpio_index: 6 +io_4iomodule_c5_index: 51gpio_index: 461 +io_4iomodule_c5_index: 27gpio_index: 10 +io_4iomodule_c5_index: 57gpio_index: 457 +io_4iomodule_c5_index: 34gpio_index: 14 +io_4iomodule_c5_index: 28gpio_index: 453 +io_4iomodule_c5_index: 26gpio_index: 19 +io_4iomodule_c5_index: 47gpio_index: 449 +io_4iomodule_c5_index: 29gpio_index: 22 +io_4iomodule_c5_index: 3gpio_index: 445 +io_4iomodule_c5_index: 16gpio_index: 27 +io_4iomodule_c5_index: 6gpio_index: 441 +io_4iomodule_c5_index: 50gpio_index: 30 +io_4iomodule_c5_index: 35gpio_index: 437 +io_4iomodule_c5_index: 7gpio_index: 35 +io_4iomodule_c5_index: 53gpio_index: 433 +io_4iomodule_c5_index: 12gpio_index: 38 +io_4iomodule_c5_index: 1gpio_index: 429 +io_4iomodule_c5_index: 22gpio_index: 43 +io_4iomodule_c5_index: 8gpio_index: 425 +io_4iomodule_c5_index: 20gpio_index: 46 +io_4iomodule_c5_index: 30gpio_index: 421 +io_4iomodule_c5_index: 2gpio_index: 51 +io_4iomodule_c5_index: 31gpio_index: 417 +io_4iomodule_c5_index: 39gpio_index: 54 +io_4iomodule_c5_index: 18gpio_index: 413 +io_4iomodule_c5_index: 10gpio_index: 59 +io_4iomodule_c5_index: 42gpio_index: 409 +io_4iomodule_c5_index: 5gpio_index: 62 +io_4iomodule_c5_index: 24gpio_index: 405 +io_4iomodule_c5_index: 37gpio_index: 67 +io_4iomodule_c5_index: 13gpio_index: 401 +io_4iomodule_c5_index: 0gpio_index: 70 +io_4iomodule_c5_index: 44gpio_index: 397 +io_4iomodule_c5_index: 38gpio_index: 75 +io_4iomodule_c5_index: 52gpio_index: 393 +io_4iomodule_c5_index: 32gpio_index: 78 +io_4iomodule_c5_index: 56gpio_index: 389 +io_4iomodule_a_index: 13gpio_index: 385 +io_4iomodule_c5_index: 4gpio_index: 83 +io_4iomodule_c5_index: 23gpio_index: 86 +io_4iomodule_a_index: 15gpio_index: 381 +io_4iomodule_a_index: 8gpio_index: 377 +io_4iomodule_c5_index: 46gpio_index: 91 +io_4iomodule_a_index: 5gpio_index: 373 +io_4iomodule_a_index: 11gpio_index: 369 +io_4iomodule_c5_index: 41gpio_index: 94 +io_4iomodule_a_index: 3gpio_index: 365 +io_4iomodule_c5_index: 25gpio_index: 99 +io_4iomodule_a_index: 7gpio_index: 361 +io_4iomodule_c5_index: 9gpio_index: 102 +io_4iomodule_a_index: 0gpio_index: 357 +io_4iomodule_c5_index: 14gpio_index: 107 +io_4iomodule_a_index: 12gpio_index: 353 +io_4iomodule_c5_index: 45gpio_index: 110 +io_4iomodule_c5_index: 17gpio_index: 115 +io_4iomodule_a_index: 4gpio_index: 349 +io_4iomodule_c5_index: 36gpio_index: 118 +io_4iomodule_a_index: 10gpio_index: 345 +io_4iomodule_a_index: 16gpio_index: 341 +io_4iomodule_c5_index: 15gpio_index: 123 +io_4iomodule_a_index: 14gpio_index: 337 +io_4iomodule_c5_index: 43gpio_index: 126 +io_4iomodule_c5_index: 19gpio_index: 131 +io_4iomodule_a_index: 1gpio_index: 333 +io_4iomodule_c5_index: 59gpio_index: 134 +io_4iomodule_a_index: 2gpio_index: 329 +io_4iomodule_a_index: 9gpio_index: 325 +io_4iomodule_c5_index: 48gpio_index: 139 +io_4iomodule_a_index: 6gpio_index: 321 +io_4iomodule_a_index: 17gpio_index: 317 +io_4iomodule_c5_index: 40gpio_index: 142 +io_4iomodule_c5_index: 11gpio_index: 147 +io_4iomodule_c5_index: 58gpio_index: 150 +io_4iomodule_c5_index: 21gpio_index: 155 +io_4iomodule_c5_index: 49gpio_index: 158 +io_4iomodule_h_c5_index: 0gpio_index: 161 +io_4iomodule_h_c5_index: 6gpio_index: 165 +io_4iomodule_h_c5_index: 10gpio_index: 169 +io_4iomodule_h_c5_index: 3gpio_index: 173 +io_4iomodule_h_c5_index: 8gpio_index: 176 +io_4iomodule_h_c5_index: 11gpio_index: 180 +io_4iomodule_h_c5_index: 7gpio_index: 184 +io_4iomodule_h_c5_index: 5gpio_index: 188 +io_4iomodule_h_c5_index: 1gpio_index: 192 +io_4iomodule_h_c5_index: 2gpio_index: 196 +io_4iomodule_h_c5_index: 9gpio_index: 200 +io_4iomodule_h_c5_index: 4gpio_index: 204 +io_4iomodule_h_index: 15gpio_index: 208 +io_4iomodule_h_index: 1gpio_index: 212 +io_4iomodule_h_index: 3gpio_index: 216 +io_4iomodule_h_index: 2gpio_index: 220 +io_4iomodule_h_index: 11gpio_index: 224 +io_4iomodule_vref_h_index: 1gpio_index: 228 +io_4iomodule_h_index: 20gpio_index: 231 +io_4iomodule_h_index: 8gpio_index: 235 +io_4iomodule_h_index: 6gpio_index: 239 +io_4iomodule_h_index: 10gpio_index: 243 +io_4iomodule_h_index: 23gpio_index: 247 +io_4iomodule_h_index: 7gpio_index: 251 +io_4iomodule_h_index: 22gpio_index: 255 +io_4iomodule_h_index: 5gpio_index: 259 +io_4iomodule_h_index: 24gpio_index: 263 +io_4iomodule_h_index: 0gpio_index: 267 +io_4iomodule_h_index: 13gpio_index: 271 +io_4iomodule_h_index: 21gpio_index: 275 +io_4iomodule_h_index: 16gpio_index: 279 +io_4iomodule_vref_h_index: 0gpio_index: 283 +io_4iomodule_h_index: 12gpio_index: 286 +io_4iomodule_h_index: 4gpio_index: 290 +io_4iomodule_h_index: 19gpio_index: 294 +io_4iomodule_h_index: 18gpio_index: 298 +io_4iomodule_h_index: 17gpio_index: 302 +io_4iomodule_h_index: 25gpio_index: 306 +io_4iomodule_h_index: 14gpio_index: 310 +io_4iomodule_h_index: 9gpio_index: 314 diff --git a/displaytest.txt b/displaytest.txt new file mode 100644 index 0000000..f46cb94 --- /dev/null +++ b/displaytest.txt @@ -0,0 +1,273 @@ +// Part 2 + +module fill + ( + SW, + CLOCK_50, // On Board 50 MHz + // Your inputs and outputs here + KEY, // On Board Keys + // The ports below are for the VGA output. Do not change. + VGA_CLK, // VGA Clock + VGA_HS, // VGA H_SYNC + VGA_VS, // VGA V_SYNC + VGA_BLANK_N, // VGA BLANK + VGA_SYNC_N, // VGA SYNC + VGA_R, // VGA Red[9:0] + VGA_G, // VGA Green[9:0] + VGA_B // VGA Blue[9:0] + ); + + input [9:0] SW; + input CLOCK_50; // 50 MHz + input [3:0] KEY; + // Declare your inputs and outputs here + // Do not change the following outputs + output VGA_CLK; // VGA Clock + output VGA_HS; // VGA H_SYNC + output VGA_VS; // VGA V_SYNC + output VGA_BLANK_N; // VGA BLANK + output VGA_SYNC_N; // VGA SYNC + output [7:0] VGA_R; // VGA Red[7:0] Changed from 10 to 8-bit DAC + output [7:0] VGA_G; // VGA Green[7:0] + output [7:0] VGA_B; // VGA Blue[7:0] + + wire resetn; + assign resetn = KEY[0]; + + // Create the colour, x, y and writeEn wires that are inputs to the controller. + + wire [2:0] colour; + wire [7:0] x; + wire [6:0] y; + wire writeEn; + + //wires to connect the control signals + wire loadX, loadY, count, loadColour, clear, reset_r; + + // Create an Instance of a VGA controller - there can be only one! + // Define the number of colours as well as the initial background + // image file (.MIF) for the controller. + vga_adapter VGA( + .resetn(resetn), + .clock(CLOCK_50), + .colour(colour), + .x(x), + .y(y), + .plot(writeEn), + /* Signals for the DAC to drive the monitor. */ + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .VGA_HS(VGA_HS), + .VGA_VS(VGA_VS), + .VGA_BLANK(VGA_BLANK_N), + .VGA_SYNC(VGA_SYNC_N), + .VGA_CLK(VGA_CLK)); + defparam VGA.RESOLUTION = "160x120"; + defparam VGA.MONOCHROME = "FALSE"; + defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; + defparam VGA.BACKGROUND_IMAGE = "black.mif"; + + // Put your code here. Your code should produce signals x,y,colour and writeEn + // for the VGA controller, in addition to any other functionality your design may require. + control c0(.clk(CLOCK_50), .resetn(resetn), .go(~KEY[3]), .draw(~KEY[1]), .clear(~KEY[2]), .loadX(loadX), + .loadY(loadY), .count(count), .loadColour(loadColour), + .loadOut(writeEn), .clearOut(clear), .reset_r(reset_r)); + datapath d0(.clk(CLOCK_50), .resetn(resetn), .dataIn(SW[6:0]), .colourIn(SW[9:7]), .loadX(loadX), + .loadY(loadY), .count(count), .loadColour(loadColour), .loadout(writeEn), + .clear(clear), .Xout(x), .Yout(y), .colourOut(colour), .reset_r(reset_r)); +endmodule + +module control( + input clk, + input resetn, + input go, + input draw, + input clear, + + output reg loadX, loadY, count, loadColour, loadOut, clearOut, reset_r + ); + + reg [3:0] current_state, next_state; + + reg [4:0] counter; + + reg [13:0] clearCount; + + localparam LOAD_X = 3'd0, + LOAD_X_WAIT = 3'd1, + LOAD_Y_C = 3'd2, + LOAD_Y_C_WAIT = 3'd3, + DRAW_WAIT = 3'd4, + DRAW = 3'd5, + CLEAR_STATE = 3'd6, + REGCLEAR = 3'd7; + + // Next state logic aka our state table + always@(*) + begin: state_table + case (current_state) + LOAD_X: next_state = clear ? CLEAR_STATE : (go ? LOAD_X_WAIT : LOAD_X); // Loop in current state until value is input + LOAD_X_WAIT: next_state = go ? LOAD_X_WAIT : LOAD_Y_C; // Loop in current state until go signal goes low + LOAD_Y_C: next_state = clear ? CLEAR_STATE : (go ? LOAD_Y_C_WAIT : LOAD_Y_C); // Loop in current state until value is input + LOAD_Y_C_WAIT: next_state = go ? LOAD_Y_C_WAIT : DRAW_WAIT; // Loop in current state until go signal goes low + DRAW_WAIT: next_state = clear ? CLEAR_STATE : (draw ? DRAW : DRAW_WAIT); + DRAW: if(counter <= 5'b10000) next_state = DRAW; //Draw onto screen until all 16 pixels are drawn + else next_state = REGCLEAR; + REGCLEAR: next_state = LOAD_X; + CLEAR_STATE: if(clearCount < 14'b11110000000001) next_state = CLEAR_STATE; + else next_state = LOAD_X; + default: next_state = LOAD_X; + endcase + end // state_table + + + // Output logic aka all of our datapath control signals + always @(*) + begin: enable_signals + // By default make all our signals 0 to avoid latches. + // This is a different style from using a default statement. + // It makes the code easier to read. If you add other out + // signals be sure to assign a default value for them here. + loadX = 1'b0; + loadY = 1'b0; + count = 1'b0; + loadColour = 1'b0; + loadOut = 1'b0; + clearOut = 1'b0; + reset_r = 1'b0; + + case (current_state) + LOAD_X: begin + loadX = 1'b1; + end + LOAD_Y_C: begin + loadY = 1'b1; + loadColour = 1'b1; + end + DRAW: begin + count = 1'b1; + loadOut = 1'b1; + end + //REGCLEAR: begin + //reset_r = 1'b1; + //end + CLEAR_STATE: begin + clearOut = 1'b1; + loadOut = 1'b1; + end + // default: // don't need default since we already made sure all of our outputs were assigned a value at the start of the always block + endcase + end // enable_signals + + // current_state registers + always@(posedge clk) + begin: state_FFs + if(!resetn) begin + current_state <= LOAD_X; + counter = 5'b0; + clearCount = 14'b0; + end + else begin + current_state <= next_state; + if(current_state == DRAW) + if(counter < 5'b10000) + counter <= counter + 1'b1; + else + counter <= 5'b0; + if(current_state == CLEAR_STATE) //look through entire screen and clears + if(clearCount < 14'b11110000000001) + clearCount <= clearCount + 1'b1; + else + clearCount <= 14'b0; + + end + end // state_FFS +endmodule + +module datapath( + input clk, + input resetn, + input [6:0] dataIn, + input [2:0] colourIn, + input loadX, loadY, count, loadColour, + input loadout, clear, reset_r, + output reg [7:0] Xout, + output reg [6:0] Yout, + output reg [2:0] colourOut + ); + + // input registers + reg [7:0] x; + reg [6:0] y; + + //counter for drawing square + reg [3:0] counter; + //counter for clearing screen + reg [7:0] clearCountX; + reg [6:0] clearCountY; + // output of counter + reg [7:0] countXout; + reg [6:0] countYout; + + // Registers x, y with respective input logic + always@(posedge clk) + if(!resetn) begin //active low reset + x <= 8'b0; + y <= 7'b0; + colourOut <= 3'b0; + end + else begin + if(loadX) + x <= {1'b0, dataIn}; + if(loadY) + y <= dataIn; + if(loadColour) + colourOut <= colourIn; + if(clear) + colourOut <= 3'b0; + end + + // Output result register + always@(posedge clk) + if(!resetn || reset_r) begin //active low + Xout <= 8'b0; + Yout <= 7'b0; + end + else + if(loadout) begin + Xout <= countXout; + Yout <= countYout; + end + + //4 bit counter + always@(posedge clk) + if(!resetn || reset_r) begin + counter <= 4'b0; + clearCountX <= 8'b0; + clearCountY <= 8'b0; + countXout <= 8'b0; + countYout <= 7'b0; + end + else begin + if(count) begin //draws 4 x 4 box at location + counter <= counter + 1'b1; + countXout <= x + counter[1:0]; + countYout <= y + counter[3:2]; + end + else counter <= 4'b0; + if(clear) begin //counts through entire grid and clears screen + clearCountX <= clearCountX + 1'b1; + if(clearCountX == 8'd127) begin + clearCountY <= clearCountY + 1'b1; + clearCountX <= 8'b0; + end + countXout <= clearCountX; + countYout <= clearCountY; + end + else begin + clearCountX <= 8'b0; + clearCountY <= 7'b0; + end + end +endmodule diff --git a/mario.qip b/mario.qip new file mode 100644 index 0000000..5487f2b --- /dev/null +++ b/mario.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mario.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mario_bb.v"] diff --git a/mario.v b/mario.v new file mode 100644 index 0000000..98015c6 --- /dev/null +++ b/mario.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: mario.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module mario ( + address, + clock, + data, + wren, + q); + + input [9:0] address; + input clock; + input [17:0] data; + input wren; + output [17:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [17:0] sub_wire0; + wire [17:0] q = sub_wire0[17:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "./Audio_Demo/Audio_Demo/marioThemeV2.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 18, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./Audio_Demo/Audio_Demo/marioThemeV2.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "18" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "./Audio_Demo/Audio_Demo/marioThemeV2.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL "data[17..0]" +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL mario.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL mario.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mario.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mario.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mario_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL mario_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/marioT.qip b/marioT.qip new file mode 100644 index 0000000..453ffa6 --- /dev/null +++ b/marioT.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "marioT.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "marioT_bb.v"] diff --git a/marioT.v b/marioT.v new file mode 100644 index 0000000..a866af8 --- /dev/null +++ b/marioT.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: marioT.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module marioT ( + address, + clock, + data, + wren, + q); + + input [7:0] address; + input clock; + input [17:0] data; + input wren; + output [17:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [17:0] sub_wire0; + wire [17:0] q = sub_wire0[17:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "./Audio_Demo/Audio_Demo/marioT.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 256, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 8, + altsyncram_component.width_a = 18, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./Audio_Demo/Audio_Demo/marioT.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "8" +// Retrieval info: PRIVATE: WidthData NUMERIC "18" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "./Audio_Demo/Audio_Demo/marioT.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL "data[17..0]" +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL marioT.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL marioT.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL marioT.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL marioT.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL marioT_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL marioT_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/pokemon.qip b/pokemon.qip new file mode 100644 index 0000000..da050a1 --- /dev/null +++ b/pokemon.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pokemon.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pokemon_bb.v"] diff --git a/pokemon.v b/pokemon.v new file mode 100644 index 0000000..c5b4c0e --- /dev/null +++ b/pokemon.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: pokemon.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pokemon ( + address, + clock, + data, + wren, + q); + + input [9:0] address; + input clock; + input [17:0] data; + input wren; + output [17:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [17:0] sub_wire0; + wire [17:0] q = sub_wire0[17:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "./Audio_Demo/Audio_Demo/pokemonthemeV2.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 18, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./Audio_Demo/Audio_Demo/pokemonthemeV2.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "18" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "./Audio_Demo/Audio_Demo/pokemonthemeV2.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL "data[17..0]" +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemon.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemon.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemon.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemon.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemon_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemon_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/pokemonMIf.v b/pokemonMIf.v new file mode 100644 index 0000000..ea03e9f --- /dev/null +++ b/pokemonMIf.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: pokemonMIf.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pokemonMIf ( + address, + clock, + data, + wren, + q); + + input [8:0] address; + input clock; + input [17:0] data; + input wren; + output [17:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [17:0] sub_wire0; + wire [17:0] q = sub_wire0[17:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "../../Final Project (mif export)/pokemon.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 512, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 9, + altsyncram_component.width_a = 18, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "../../Final Project (mif export)/pokemon.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "9" +// Retrieval info: PRIVATE: WidthData NUMERIC "18" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "../../Final Project (mif export)/pokemon.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL "data[17..0]" +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonMIf.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonMIf.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonMIf.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonMIf.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonMIf_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonMIf_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/pokemonMif.qip b/pokemonMif.qip new file mode 100644 index 0000000..2a4e18f --- /dev/null +++ b/pokemonMif.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pokemonMIf.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pokemonMIf_bb.v"] diff --git a/pokemonT.qip b/pokemonT.qip new file mode 100644 index 0000000..9f00b63 --- /dev/null +++ b/pokemonT.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pokemonT.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pokemonT_bb.v"] diff --git a/pokemonT.v b/pokemonT.v new file mode 100644 index 0000000..344b8a2 --- /dev/null +++ b/pokemonT.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: pokemonT.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module pokemonT ( + address, + clock, + data, + wren, + q); + + input [8:0] address; + input clock; + input [17:0] data; + input wren; + output [17:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [17:0] sub_wire0; + wire [17:0] q = sub_wire0[17:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "./Audio_Demo/Audio_Demo/rocky.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 512, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 9, + altsyncram_component.width_a = 18, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./Audio_Demo/Audio_Demo/rocky.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "512" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "9" +// Retrieval info: PRIVATE: WidthData NUMERIC "18" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "./Audio_Demo/Audio_Demo/rocky.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 9 0 INPUT NODEFVAL "address[8..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL "data[17..0]" +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 9 0 address 0 0 9 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonT.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonT.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonT.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonT.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonT_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pokemonT_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/rocky.qip b/rocky.qip new file mode 100644 index 0000000..46440e4 --- /dev/null +++ b/rocky.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rocky.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rocky_bb.v"] diff --git a/rocky.v b/rocky.v new file mode 100644 index 0000000..55e40a4 --- /dev/null +++ b/rocky.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: rocky.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module rocky ( + address, + clock, + data, + wren, + q); + + input [9:0] address; + input clock; + input [17:0] data; + input wren; + output [17:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [17:0] sub_wire0; + wire [17:0] q = sub_wire0[17:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "./Audio_Demo/Audio_Demo/rockyV2.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 18, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./Audio_Demo/Audio_Demo/rockyV2.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "18" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "./Audio_Demo/Audio_Demo/rockyV2.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL "data[17..0]" +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL rocky.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL rocky.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rocky.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rocky.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rocky_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rocky_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/rockyT.qip b/rockyT.qip new file mode 100644 index 0000000..62d4812 --- /dev/null +++ b/rockyT.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rockyT.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rockyT_bb.v"] diff --git a/rockyT.v b/rockyT.v new file mode 100644 index 0000000..37bba2f --- /dev/null +++ b/rockyT.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: rockyT.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module rockyT ( + address, + clock, + data, + wren, + q); + + input [9:0] address; + input clock; + input [17:0] data; + input wren; + output [17:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [17:0] sub_wire0; + wire [17:0] q = sub_wire0[17:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "./Audio_Demo/Audio_Demo/rockytutorialV2.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 18, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./Audio_Demo/Audio_Demo/rockytutorialV2.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "18" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "./Audio_Demo/Audio_Demo/rockytutorialV2.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL "data[17..0]" +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL rockyT.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL rockyT.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rockyT.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rockyT.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rockyT_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL rockyT_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/zelda.qip b/zelda.qip new file mode 100644 index 0000000..cc7380b --- /dev/null +++ b/zelda.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "zelda.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zelda_bb.v"] diff --git a/zelda.v b/zelda.v new file mode 100644 index 0000000..8c55b34 --- /dev/null +++ b/zelda.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: zelda.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module zelda ( + address, + clock, + data, + wren, + q); + + input [9:0] address; + input clock; + input [17:0] data; + input wren; + output [17:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [17:0] sub_wire0; + wire [17:0] q = sub_wire0[17:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "./Audio_Demo/Audio_Demo/zeldaThemeV2.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 1024, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 10, + altsyncram_component.width_a = 18, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./Audio_Demo/Audio_Demo/zeldaThemeV2.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +// Retrieval info: PRIVATE: WidthData NUMERIC "18" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "./Audio_Demo/Audio_Demo/zeldaThemeV2.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL "data[17..0]" +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL zelda.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL zelda.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zelda.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zelda.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zelda_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zelda_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf diff --git a/zeldaT.qip b/zeldaT.qip new file mode 100644 index 0000000..a62a45d --- /dev/null +++ b/zeldaT.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.0" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "zeldaT.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zeldaT_bb.v"] diff --git a/zeldaT.v b/zeldaT.v new file mode 100644 index 0000000..fb8e690 --- /dev/null +++ b/zeldaT.v @@ -0,0 +1,174 @@ +// megafunction wizard: %RAM: 1-PORT% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: altsyncram + +// ============================================================ +// File Name: zeldaT.v +// Megafunction Name(s): +// altsyncram +// +// Simulation Library Files(s): +// altera_mf +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 18.0.0 Build 614 04/24/2018 SJ Lite Edition +// ************************************************************ + + +//Copyright (C) 2018 Intel Corporation. All rights reserved. +//Your use of Intel Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Intel Program License +//Subscription Agreement, the Intel Quartus Prime License Agreement, +//the Intel FPGA IP License Agreement, or other applicable license +//agreement, including, without limitation, that your use is for +//the sole purpose of programming logic devices manufactured by +//Intel and sold by Intel or its authorized distributors. Please +//refer to the applicable agreement for further details. + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module zeldaT ( + address, + clock, + data, + wren, + q); + + input [6:0] address; + input clock; + input [17:0] data; + input wren; + output [17:0] q; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_off +`endif + tri1 clock; +`ifndef ALTERA_RESERVED_QIS +// synopsys translate_on +`endif + + wire [17:0] sub_wire0; + wire [17:0] q = sub_wire0[17:0]; + + altsyncram altsyncram_component ( + .address_a (address), + .clock0 (clock), + .data_a (data), + .wren_a (wren), + .q_a (sub_wire0), + .aclr0 (1'b0), + .aclr1 (1'b0), + .address_b (1'b1), + .addressstall_a (1'b0), + .addressstall_b (1'b0), + .byteena_a (1'b1), + .byteena_b (1'b1), + .clock1 (1'b1), + .clocken0 (1'b1), + .clocken1 (1'b1), + .clocken2 (1'b1), + .clocken3 (1'b1), + .data_b (1'b1), + .eccstatus (), + .q_b (), + .rden_a (1'b1), + .rden_b (1'b1), + .wren_b (1'b0)); + defparam + altsyncram_component.clock_enable_input_a = "BYPASS", + altsyncram_component.clock_enable_output_a = "BYPASS", + altsyncram_component.init_file = "./Audio_Demo/Audio_Demo/zeldaT.mif", + altsyncram_component.intended_device_family = "Cyclone V", + altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", + altsyncram_component.lpm_type = "altsyncram", + altsyncram_component.numwords_a = 128, + altsyncram_component.operation_mode = "SINGLE_PORT", + altsyncram_component.outdata_aclr_a = "NONE", + altsyncram_component.outdata_reg_a = "UNREGISTERED", + altsyncram_component.power_up_uninitialized = "FALSE", + altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", + altsyncram_component.widthad_a = 7, + altsyncram_component.width_a = 18, + altsyncram_component.width_byteena_a = 1; + + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +// Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +// Retrieval info: PRIVATE: AclrByte NUMERIC "0" +// Retrieval info: PRIVATE: AclrData NUMERIC "0" +// Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +// Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +// Retrieval info: PRIVATE: Clken NUMERIC "0" +// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +// Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +// Retrieval info: PRIVATE: MIFfilename STRING "./Audio_Demo/Audio_Demo/zeldaT.mif" +// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128" +// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +// Retrieval info: PRIVATE: RegAddr NUMERIC "1" +// Retrieval info: PRIVATE: RegData NUMERIC "1" +// Retrieval info: PRIVATE: RegOutput NUMERIC "0" +// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +// Retrieval info: PRIVATE: SingleClock NUMERIC "1" +// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +// Retrieval info: PRIVATE: WidthAddr NUMERIC "7" +// Retrieval info: PRIVATE: WidthData NUMERIC "18" +// Retrieval info: PRIVATE: rden NUMERIC "0" +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +// Retrieval info: CONSTANT: INIT_FILE STRING "./Audio_Demo/Audio_Demo/zeldaT.mif" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V" +// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128" +// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7" +// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" +// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +// Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL "address[6..0]" +// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +// Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL "data[17..0]" +// Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL "q[17..0]" +// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +// Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0 +// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +// Retrieval info: CONNECT: @data_a 0 0 18 0 data 0 0 18 0 +// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +// Retrieval info: CONNECT: q 0 0 18 0 @q_a 0 0 18 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL zeldaT.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL zeldaT.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zeldaT.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zeldaT.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zeldaT_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL zeldaT_bb.v TRUE +// Retrieval info: LIB_FILE: altera_mf