[ISA] Add instructions with corresponding opcodes

[sin-diesel]

We need information about instructions opcodes (https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf)

1. Add opcodes for add, mul, sub, div, jmp instructions. Probably need to store them in some sort of class or a container (discussable)
2. Add class Instruction with decode in `Instructions.[h,cpp] method which can be applied to extract arguments and other info from instruction. Note that for different instruction this method should work differently
3. Write tests for decoding simple instructions

[sin-diesel]

Instructions found here must be implemented

addi	sp,sp,-48
 sd	ra,40(sp)
 sd	s0,32(sp)
 sd	s1,24(sp)
 addi	s0,sp,48
 mv	a5,a0
 sw	a5,-36(s0)
 lw	a5,-36(s0)
 sext.w	a4,a5
 li	a5,1
 bne	a4,a5,10584 <fibbonaci(int)+0x22>
 li	a5,1
 j	105bc <fibbonaci(int)+0x5a>
 lw	a5,-36(s0)
 sext.w	a4,a5
 li	a5,2
 bne	a4,a5,10596 <fibbonaci(int)+0x34>
 li	a5,1
 j	105bc <fibbonaci(int)+0x5a>
 lw	a5,-36(s0)
 addiw	a5,a5,-1 # 11fff <_DYNAMIC+0x21f>
 sext.w	a5,a5
 mv	a0,a5
 jal	ra,10562 <fibbonaci(int)>
 mv	a5,a0
 mv	s1,a5
 lw	a5,-36(s0)
 addiw	a5,a5,-2
 sext.w	a5,a5
 mv	a0,a5
 jal	ra,10562 <fibbonaci(int)>
 mv	a5,a0
 addw	a5,a5,s1
 sext.w	a5,a5
 mv	a0,a5
 ld	ra,40(sp)
 ld	s0,32(sp)
 ld	s1,24(sp)
 addi	sp,sp,48
 ret
main:
 addi	sp,sp,-32
 sd	ra,24(sp)
 sd	s0,16(sp)
 addi	s0,sp,32
 sw	zero,-20(s0)
 li	a0,11
 jal	ra,10562 <fibbonaci(int)>
 mv	a5,a0
 sw	a5,-20(s0)
 li	a5,0
 mv	a0,a5
 ld	ra,24(sp)
 ld	s0,16(sp)
 addi	sp,sp,32
 ret