From 878e72995da79b8d23aca58ea8cd1ace12d9616e Mon Sep 17 00:00:00 2001
From: Erik Schnetter <schnetter@gmail.com>
Date: Tue, 9 Apr 2024 12:41:18 -0400
Subject: [PATCH 1/3] Support riscv64 as binary platform

---
 base/binaryplatforms.jl | 8 ++++++--
 base/cpuid.jl           | 6 +++++-
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/base/binaryplatforms.jl b/base/binaryplatforms.jl
index 8c6fa2a5f4a03..5d1ce47909f21 100644
--- a/base/binaryplatforms.jl
+++ b/base/binaryplatforms.jl
@@ -194,7 +194,7 @@ end
 function validate_tags(tags::Dict)
     throw_invalid_key(k) = throw(ArgumentError("Key \"$(k)\" cannot have value \"$(tags[k])\""))
     # Validate `arch`
-    if tags["arch"] ∉ ("x86_64", "i686", "armv7l", "armv6l", "aarch64", "powerpc64le")
+    if tags["arch"] ∉ ("x86_64", "i686", "armv7l", "armv6l", "aarch64", "powerpc64le", "riscv64")
         throw_invalid_key("arch")
     end
     # Validate `os`
@@ -597,6 +597,7 @@ const arch_mapping = Dict(
     "armv7l" => "arm(v7l)?", # if we just see `arm-linux-gnueabihf`, we assume it's `armv7l`
     "armv6l" => "armv6l",
     "powerpc64le" => "p(ower)?pc64le",
+    "riscv64" => "riscv64",
 )
 # Keep this in sync with `CPUID.ISAs_by_family`
 # These are the CPUID side of the microarchitectures targeted by GCC flags in BinaryBuilder.jl
@@ -632,7 +633,10 @@ const arch_march_isa_mapping = let
         ],
         "powerpc64le" => [
             "power8" => get_set("powerpc64le", "power8"),
-        ]
+        ],
+        "riscv64" => [
+            "rv64imafdc_zicsr_zifencei_zca_zcd" => get_set("riscv64", "rv64imafdc_zicsr_zifencei_zca_zcd"),
+        ],
     )
 end
 const os_mapping = Dict(
diff --git a/base/cpuid.jl b/base/cpuid.jl
index 48930d8064ba9..d869059edf66b 100644
--- a/base/cpuid.jl
+++ b/base/cpuid.jl
@@ -64,7 +64,11 @@ const ISAs_by_family = Dict(
     "powerpc64le" => [
         # We have no way to test powerpc64le features yet, so we're only going to declare the lowest ISA:
         "power8" => ISA(Set{UInt32}()),
-    ]
+    ],
+    "riscv64" => [
+        # We have no way to test riscv64 features yet, so we're only going to declare the ISA used by Debian:
+        "rv64imafdc_zicsr_zifencei_zca_zcd" => ISA(Set{UInt32}()),
+    ],
 )
 
 # Test a CPU feature exists on the currently-running host

From 2544ce9bbce4e2c5d3683c79d88512b8e9c1dbda Mon Sep 17 00:00:00 2001
From: Erik Schnetter <schnetter@gmail.com>
Date: Sun, 14 Apr 2024 16:47:34 -0400
Subject: [PATCH 2/3] Update RISC-V changes according to @alexfanqi's earlier
 changes

---
 base/binaryplatforms.jl | 4 ++--
 base/cpuid.jl           | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/base/binaryplatforms.jl b/base/binaryplatforms.jl
index 5d1ce47909f21..598b618f0d1ed 100644
--- a/base/binaryplatforms.jl
+++ b/base/binaryplatforms.jl
@@ -597,7 +597,7 @@ const arch_mapping = Dict(
     "armv7l" => "arm(v7l)?", # if we just see `arm-linux-gnueabihf`, we assume it's `armv7l`
     "armv6l" => "armv6l",
     "powerpc64le" => "p(ower)?pc64le",
-    "riscv64" => "riscv64",
+    "riscv64" => "(rv64|riscv64)",
 )
 # Keep this in sync with `CPUID.ISAs_by_family`
 # These are the CPUID side of the microarchitectures targeted by GCC flags in BinaryBuilder.jl
@@ -635,7 +635,7 @@ const arch_march_isa_mapping = let
             "power8" => get_set("powerpc64le", "power8"),
         ],
         "riscv64" => [
-            "rv64imafdc_zicsr_zifencei_zca_zcd" => get_set("riscv64", "rv64imafdc_zicsr_zifencei_zca_zcd"),
+            "riscv64" => get_set("riscv64", "riscv64"),
         ],
     )
 end
diff --git a/base/cpuid.jl b/base/cpuid.jl
index d869059edf66b..876ea600ab0b0 100644
--- a/base/cpuid.jl
+++ b/base/cpuid.jl
@@ -66,8 +66,8 @@ const ISAs_by_family = Dict(
         "power8" => ISA(Set{UInt32}()),
     ],
     "riscv64" => [
-        # We have no way to test riscv64 features yet, so we're only going to declare the ISA used by Debian:
-        "rv64imafdc_zicsr_zifencei_zca_zcd" => ISA(Set{UInt32}()),
+        # We have no way to test riscv64 features yet, so we're only going to declare the lowest ISA:
+        "riscv64" => ISA(Set{UInt32}()),
     ],
 )
 

From 14a855469ccb06dc219fd0b6ccdadb86ba4dbdcc Mon Sep 17 00:00:00 2001
From: Erik Schnetter <schnetter@gmail.com>
Date: Mon, 15 Apr 2024 10:18:24 -0400
Subject: [PATCH 3/3] Correct RISC-V triple

---
 base/binaryplatforms.jl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/base/binaryplatforms.jl b/base/binaryplatforms.jl
index 598b618f0d1ed..c8a55c99a5724 100644
--- a/base/binaryplatforms.jl
+++ b/base/binaryplatforms.jl
@@ -597,7 +597,7 @@ const arch_mapping = Dict(
     "armv7l" => "arm(v7l)?", # if we just see `arm-linux-gnueabihf`, we assume it's `armv7l`
     "armv6l" => "armv6l",
     "powerpc64le" => "p(ower)?pc64le",
-    "riscv64" => "(rv64|riscv64)",
+    "riscv64" => "riscv64",
 )
 # Keep this in sync with `CPUID.ISAs_by_family`
 # These are the CPUID side of the microarchitectures targeted by GCC flags in BinaryBuilder.jl