From 4e938b0f6f04e427aaf1a515c826e6ccc9ab4402 Mon Sep 17 00:00:00 2001
From: "Jin,Zhonghui" <zhonghui.jin@intel.com>
Date: Tue, 5 Dec 2023 01:05:57 +0800
Subject: [PATCH] [Backport] 8269179: Crash in
 TestMacroLogicVector::testSubWordBoolean: assert(_base >= VectorMask && _base
 <= VectorZ) failed: Not a Vector

Summary: 8269179: Crash in TestMacroLogicVector::testSubWordBoolean: assert(_base >= VectorMask && _base <= VectorZ) failed: Not a Vector

Test Plan: ci jtreg

Reviewed-by: JoshuaZhuwj

Issue: NA
---
 src/hotspot/cpu/x86/x86.ad | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/hotspot/cpu/x86/x86.ad b/src/hotspot/cpu/x86/x86.ad
index b62a856a231..f8297bcc484 100644
--- a/src/hotspot/cpu/x86/x86.ad
+++ b/src/hotspot/cpu/x86/x86.ad
@@ -8118,7 +8118,7 @@ instruct vpternlog(vec dst, vec src2, vec src3, immU8 func) %{
 %}
 
 instruct vpternlog_mem(vec dst, vec src2, memory src3, immU8 func) %{
-  predicate(vector_length_in_bytes(n->in(1)) > 8);
+  predicate(vector_length_in_bytes(n->in(1)->in(1)) > 8);
   match(Set dst (MacroLogicV (Binary dst src2) (Binary (LoadVector src3) func)));
   effect(TEMP dst);
   format %{ "vpternlogd $dst,$src2,$src3,$func\t! vector ternary logic" %}