From 313774331975698a7a3cbcaa976da5138f8af23b Mon Sep 17 00:00:00 2001 From: Gravel Cai <37858537+gravelcai@users.noreply.github.com> Date: Sat, 5 Nov 2022 11:02:18 +0800 Subject: [PATCH] Fix the replacer bug under condition of clk_div_by_2 (#109) * fix a bug that updates the replacer's SRAM at wrong beats. --add a flip-flop, beating 'repl_state' one more cycle. * fix a mistake, make it compatible with full clk. * Now its compatible with full clk. * beats 'next_state' to next cycle instead of 'repl_state'. --- src/main/scala/huancun/BaseDirectory.scala | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/main/scala/huancun/BaseDirectory.scala b/src/main/scala/huancun/BaseDirectory.scala index b8b731a05..0e1f1b1bf 100644 --- a/src/main/scala/huancun/BaseDirectory.scala +++ b/src/main/scala/huancun/BaseDirectory.scala @@ -175,10 +175,16 @@ class SubDirectory[T <: Data]( } 0.U } else { + val next_state_s2 = Reg(UInt(repl.nBits.W)) val replacer_sram = Module(new SRAMTemplate(UInt(repl.nBits.W), sets, singlePort = true)) val repl_state = replacer_sram.io.r(io.read.fire(), io.read.bits.set).resp.data(0) - val next_state = repl.get_next_state(repl_state, way_s1) - replacer_sram.io.w(replacer_wen, RegNext(next_state), RegNext(reqReg.set), 1.U) + val next_state_s1 = repl.get_next_state(repl_state, way_s1) + next_state_s2 := next_state_s1 + if (clk_div_by_2) { + replacer_sram.io.w(replacer_wen, RegNext(next_state_s2), RegNext(reqReg.set), 1.U) + } else { + replacer_sram.io.w(replacer_wen, RegNext(next_state_s1), RegNext(reqReg.set), 1.U) + } repl_state }