cleanup + litex

Author: dlobato

Diff for: .gitignore

@@ -42,5 +42,13 @@ tmp
 rtl
 attic
 
-totesim/obj_dir
-
+*.o
+*.su
+*.d
+*.map
+*.elf
+*.bin
+*.asm
+csr.csv
+sim.gtkw
+venv

Diff for: .gitmodules

@@ -1,9 +1,3 @@
 [submodule "src/main/resources/rtl/Booth_Multipliers"]
 	path = hardware/main/resources/rtl/Booth_Multipliers
 	url = https://github.com/dlobato/Booth_Multipliers
-[submodule "libs/ELFIO"]
-	path = totesim/libs/ELFIO
-	url = https://github.com/serge1/ELFIO.git
-[submodule "libs/tensorflow"]
-	path = software/libs/tensorflow
-	url = https://github.com/dlobato/tensorflow.git

Diff for: README.md

@@ -20,119 +20,3 @@ The project depends on several tools, check the requirements on each project to
 3. RISC-V GNU Embedded Toolchain to build the software targetted to riscv. YOu can build it yourself (https://github.com/riscv/riscv-gnu-toolchain) or get a pre-built one from https://www.sifive.com or https://github.com/gnu-mcu-eclipse/riscv-none-gcc/releases
 4. [Tensorflow](www.tensorflow.org): To train and do inference.
 
-### Generate core HDL
-To generate verilog for a core run:
-```
-$> cd neuralFPGA
-$> sbt "runMain neuralfpga.core.Tote rtl"
-```
-This will generate the file _rtl/Tote.v_ and _cpu0.yaml_ (used on openocd session)
-
-### Run simulation
-First we need to build the simulator for our core:
-```
-$> cd neuralFPGA/sim/tote
-$> make
-```
-Then we need a program to run on our simulated core. You can use the [hello world example](software/helloworld). Build it with:
-```
-$> cd neuralFPGA/software/helloworld
-$> make
-```
-Run it on the simulator:
-```
-$> cd neuralFPGA/sim/tote
-$> obj_dir/VTote_tb --program ../../software/helloworld/build/helloworld.elf
-Loading program: ../../software/helloworld/build/helloworld.elf
-LOAD  [0] 0x5	0x80000000	0x22f4	0x22f4
-LOAD  [1] 0x6	0x80002300	0x70	0x80
-LOAD  [2] 0x6	0x80002370	0x0	0x10
-LOAD  [3] 0x6	0x80002370	0x0	0x800
-LOAD  [4] 0x6	0x80002370	0x0	0x4000
-_exit at 800000b4
-Simulation start
-586: Hello World!
-_exit with code=0
-```
-
-### Debug simulation
-The simulated core can be debugged with gdb attached to openocd.
-Start the simulator:
-```
-$> cd neuralFPGA/sim/tote
-$> obj_dir/VTote_tb --jtag-enabled
-Simulation start
-This emulator compiled with JTAG Remote Bitbang client.
-Listening on port 9090
-Attempting to accept client socket
-```
-
-On a different terminal start openocd:
-```
-$> cd neuralFPGA
-$> openocd -c "set VEXRISCV_YAML cpu0.yaml" -f sim/openocd/tote_remote_bitbang.tcl
-Open On-Chip Debugger 0.10.0+dev-01214-g0ace94f7 (2019-08-27-18:21)
-Licensed under GNU GPL v2
-For bug reports, read
-	http://openocd.org/doc/doxygen/bugs.html
-cpu0.yaml
-Warn : Adapter driver 'remote_bitbang' did not declare which transports it allows; assuming legacy JTAG-only
-Info : only one transport option; autoselect 'jtag'
-Info : set servers polling period to 50ms
-Info : Initializing remote_bitbang driver
-Info : Connecting to localhost:9090
-Info : remote_bitbang driver initialized
-Info : This adapter doesn't support configurable speed
-Info : JTAG tap: fpga_spinal.bridge tap/device found: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1)
-Info : Listening on port 3333 for gdb connections
-requesting target halt and executing a soft reset
-Info : Listening on port 6666 for tcl connections
-Info : Listening on port 4444 for telnet connections
-```
-
-And last on another terminal start gdb:
-```
-$> cd neuralFPGA
-$> riscv64-unknown-elf-gdb software/helloworld/build/helloworld.elf
-GNU gdb (SiFive GDB 8.3.0-2019.05.3) 8.3
-Copyright (C) 2019 Free Software Foundation, Inc.
-License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
-This is free software: you are free to change and redistribute it.
-There is NO WARRANTY, to the extent permitted by law.
-Type "show copying" and "show warranty" for details.
-This GDB was configured as "--host=x86_64-linux-gnu --target=riscv64-unknown-elf".
-Type "show configuration" for configuration details.
-For bug reporting instructions, please see:
-<https://github.com/sifive/freedom-tools/issues>.
-Find the GDB manual and other documentation resources online at:
-    <http://www.gnu.org/software/gdb/documentation/>.
-
-For help, type "help".
-Type "apropos word" to search for commands related to "word"...
-Reading symbols from software/helloworld/build/helloworld.elf...
-(gdb)
-```
-
-Now we need to connect our gdb to the target:
-```
-(gdb) target remote localhost:3333
-Remote debugging using localhost:3333
-_start ()
-    at /home/dlobato/workspace-roboclub/neuralFPGA/software/tote/riscv/start.S:7
-7	  la gp, __global_pointer$
-(gdb) monitor reset halt
-JTAG tap: fpga_spinal.bridge tap/device found: 0x10001fff (mfg: 0x7ff (<invalid>), part: 0x0001, ver: 0x1)
-(gdb) load
-Loading section .text, size 0x22f0 lma 0x80000000
-Loading section .sdata2._global_impure_ptr, size 0x4 lma 0x800022f0
-Loading section .sdata, size 0x10 lma 0x80002300
-Loading section .data, size 0x60 lma 0x80002310
-Start address 0x80000000, load size 9060
-Transfer rate: 1474 KB/sec, 2265 bytes/write.
-(gdb) continue
-Continuing.
-```
-
-On the simulator terminal (the one running obj_dir/VTote_tb --jtag-enabled) we should see the message "9611126: Hello World!" (the timestamp might be different). You can stop the program execution on the gdb terminal with Ctrl + C.
-
-Instead of continue we can set a breakpoint and debbug our code, print variable data, see registers, ...

Diff for: firmware/common.mk

@@ -0,0 +1,70 @@
+ROOT_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
+LITEX_BUILD_DIR ?= $(realpath $(ROOT_DIR)/../build/sim)
+include $(LITEX_BUILD_DIR)/software/include/generated/variables.mak
+
+TARGET_TOOLCHAIN_PREFIX ?= riscv-none-embed-
+
+CXX             := $(TARGET_TOOLCHAIN_PREFIX)g++
+CC              := $(TARGET_TOOLCHAIN_PREFIX)gcc
+AS              := $(TARGET_TOOLCHAIN_PREFIX)as
+AR              := $(TARGET_TOOLCHAIN_PREFIX)ar 
+LD              := $(TARGET_TOOLCHAIN_PREFIX)ld
+NM              := $(TARGET_TOOLCHAIN_PREFIX)nm
+OBJDUMP         := $(TARGET_TOOLCHAIN_PREFIX)objdump
+OBJCOPY         := $(TARGET_TOOLCHAIN_PREFIX)objcopy
+SIZE            := $(TARGET_TOOLCHAIN_PREFIX)size
+
+INCLUDES := -I$(SOC_DIRECTORY)/software/include \
+           -I$(BUILDINC_DIRECTORY) \
+           -I$(CPU_DIRECTORY) \
+		   -I$(ROOT_DIR)/include
+
+LDSCRIPT := linker.ld
+MAP_NAME := fw.map
+COMMON_FLAGS := $(CPUFLAGS) -MD -MP -ffunction-sections -fdata-sections -fstack-usage -ffreestanding -Wall
+ifeq ($(DEBUG),yes)
+	COMMON_FLAGS += -g -Og
+else
+	COMMON_FLAGS += -DNDEBUG -Os
+endif
+
+CFLAGS = $(CFLAGS_ARGS) \
+			$(COMMON_FLAGS) \
+			-std=gnu11
+
+CXXFLAGS = $(CXXFLAGS_ARGS) \
+			$(COMMON_FLAGS) \
+			-std=gnu++11 \
+			-fno-exceptions \
+			-fno-rtti \
+			-fno-unwind-tables \
+			-fcheck-new \
+			-fno-use-cxa-atexit
+
+LDFLAGS = -L$(BUILDINC_DIRECTORY) \
+			-nostartfiles --specs=nano.specs \
+			-Wl,--gc-sections,-Bstatic,-T,$(LDSCRIPT),-Map,$(MAP_NAME),--print-memory-usage
+
+%.o: %.c
+	$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@
+
+%.o: %.cc
+	$(CXX) $(CXXFLAGS) $(INCLUDES) -c $< -o $@
+
+%.o: %.cpp
+	$(CXX) $(CXXFLAGS) $(INCLUDES) -c $< -o $@
+
+%.o: %.S
+	$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@
+
+%.hex: %.elf
+	$(OBJCOPY) -O ihex $^ $@
+
+%.bin: %.elf
+	$(OBJCOPY) -O binary $^ $@
+
+%.v: %.elf
+	$(OBJCOPY) -O verilog $^ $@
+
+%.asm: %.elf
+	$(OBJDUMP) -S -d $^ > $@

Diff for: firmware/get_tflite_dep.sh

@@ -0,0 +1,11 @@
+!#/bin/bash
+
+set -euo pipefail
+
+TENSORFLOW_DIR=$1
+
+make -f $(TENSORFLOW_DIR)/tensorflow/lite/micro/tools/make/Makefile TARGET=esp generate_hello_world_esp_project
+cp -r $(TENSORFLOW_DIR)/tensorflow/lite/micro/tools/make/gen/esp_xtensa-esp32_default/prj/hello_world/esp-idf/components/tfmicro .
+rm -r tfmicro/CMakeLists.txt
+
+git -C $(TENSORFLOW_DIR)/src/tensorflow rev-parse --short HEAD > tfmicro/version

Diff for: firmware/helloworld/Makefile

@@ -0,0 +1,28 @@
+PROJ_NAME := helloworld
+include ../common.mk
+
+LDSCRIPT := linker.ld
+
+SRCS += isr.c main.c
+
+OBJS := $(SRCS:.c=.o)
+OBJS := $(ROOT_DIR)/rt/crt0.o \
+ 		$(ROOT_DIR)/rt/init.o \
+ 		uart.o \
+ 		$(OBJS)
+
+all: $(PROJ_NAME).elf $(PROJ_NAME).asm $(PROJ_NAME).bin
+
+$(PROJ_NAME).elf: $(OBJS)
+	$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) $(LIBS)
+
+uart.o: $(LIBBASE_DIRECTORY)/uart.c
+	$(CC) $(CFLAGS) -I$(SOC_DIRECTORY)/software/include/base $(INCLUDES) -c $< -o $@
+
+-include $(OBJS:.o=.d)
+
+.PHONY : clean
+clean:
+	-rm -f $(OBJS) $(OBJS:.o=.d) $(OBJS:.o=.su) $(PROJ_NAME).elf $(PROJ_NAME).asm $(PROJ_NAME).bin $(MAP_NAME)
+
+.SECONDARY: $(OBJS)

Diff for: firmware/helloworld/isr.c

@@ -0,0 +1,29 @@
+// This file is Copyright (c) 2020 Florent Kermarrec <[email protected]>
+// License: BSD
+
+#include <generated/csr.h>
+#include <generated/soc.h>
+#include <irq.h>
+#include <base/uart.h>
+
+void isr(void);
+
+#ifdef CONFIG_CPU_HAS_INTERRUPT
+
+void isr(void)
+{
+	__attribute__((unused)) unsigned int irqs;
+
+	irqs = irq_pending() & irq_getmask();
+
+#ifndef UART_POLLING
+	if(irqs & (1 << UART_INTERRUPT))
+		uart_isr();
+#endif
+}
+
+#else
+
+void isr(void){};
+
+#endif

Diff for: firmware/helloworld/linker.ld

@@ -0,0 +1,101 @@
+/* adapted from https://raw.githubusercontent.com/RISCV-on-Microsemi-FPGA/SoftConsole/master/riscv-simple-baremetal-bootloader/riscv_hal/microsemi-riscv-ram.ld */
+
+INCLUDE generated/output_format.ld
+ENTRY(_start)
+INCLUDE generated/regions.ld
+
+__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP (*(SORT_NONE(.text.entry)))   
+        . = ALIGN(4);
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.plt)
+        . = ALIGN(4);
+
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        *(.gcc_except_table) 
+        *(.eh_frame_hdr)
+        *(.eh_frame)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP (*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+        . = ALIGN(4);
+
+    } > main_ram
+
+    /* short/global data section */
+    .sdata : ALIGN(4)
+    {
+        __sdata_load = LOADADDR(.sdata);
+        __sdata_start = .; 
+        PROVIDE( __global_pointer$ = . + 0x800);
+        *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+        *(.srodata*)
+        *(.sdata .sdata.* .gnu.linkonce.s.*)
+        . = ALIGN(4);
+        __sdata_end = .;
+    } > main_ram
+
+    /* data section */
+    .data : ALIGN(4)
+    {
+        __data_load = LOADADDR(.data);
+        __data_start = .; 
+        *(.got.plt) *(.got)
+        *(.shdata)
+        *(.data .data.* .gnu.linkonce.d.*)
+        . = ALIGN(4);
+        __data_end = .;
+    } > main_ram
+
+    /* sbss section */
+    .sbss : ALIGN(4)
+    {
+        __sbss_start = .;
+        *(.sbss .sbss.* .gnu.linkonce.sb.*)
+        *(.scommon)
+        . = ALIGN(0x10);
+        __sbss_end = .;
+    } > sram
+  
+    /* sbss section */
+    .bss : ALIGN(4)
+    { 
+        __bss_start = .;
+        *(.shbss)
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end = .;
+    } > sram
+}
+
+PROVIDE(__stack_top = ORIGIN(sram) + LENGTH(sram));
+
+PROVIDE(_heap_start = __data_end);
+PROVIDE(_heap_end = ORIGIN(main_ram) + LENGTH(main_ram));