Merge stm32-rs#161

bors[bot] · revyakin · web-flow · commit 8f410dbfb3dc · 2023-04-22T16:51:07.000Z
161: Provide ability to clear timer UIF interrup flag r=therealprof a=revyakin

Timer interrupts cannot be used without this method.

Co-authored-by: Evgeniy Revyakin &lt;reviakinea@gmail.com&gt;
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Added
 
 - Provide getters to serial status flags idle/txe/rxne/tc.
+- Provide ability to reset timer UIF interrupt flag
 
 ### Fixed
 
diff --git a/src/timers.rs b/src/timers.rs
@@ -168,6 +168,11 @@ macro_rules! timers {
                     rcc.$apbenr.modify(|_, w| w.$timXen().clear_bit());
                     self.tim
                 }
+
+                /// Clears interrupt flag
+                pub fn clear_irq(&mut self) {
+                    self.tim.sr.modify(|_, w| w.uif().clear_bit());
+                }
             }
 
             impl CountDown for Timer<$TIM> {

Original file line number	Diff line number	Diff line change
`@@ -168,6 +168,11 @@ macro_rules! timers {`
`168`	`168`	`rcc.$apbenr.modify(\|_, w\| w.$timXen().clear_bit());`
`169`	`169`	`self.tim`
`170`	`170`	`}`
	`171`	`+`
	`172`	`+ /// Clears interrupt flag`
	`173`	`+ pub fn clear_irq(&mut self) {`
	`174`	`+ self.tim.sr.modify(\|_, w\| w.uif().clear_bit());`
	`175`	`+ }`
`171`	`176`	`}`
`172`	`177`
`173`	`178`	`impl CountDown for Timer<$TIM> {`