Generating Verilog DAVE (Deriving Automatically Verilog from English) Paper: https://arxiv.org/abs/2009.01026 LLMs for Automated Verilog Generation (VeriGen) Paper: https://arxiv.org/abs/2212.11140 Repo: https://github.com/shailja-thakur/VGen ChipChat Paper: https://arxiv.org/abs/2305.13243 AutoChip Paper: https://arxiv.org/abs/2311.04887 Repo: https://github.com/shailja-thakur/AutoChip Optimized RTL Code Generation Using MCTS Paper: https://arxiv.org/abs/2402.03289 Security Analysis of LLM Generated Code Asleep at the Keyboard Paper: https://arxiv.org/abs/2108.09293 LLMs for Bug Detection & Repair Zero-shot Vulnerability Repair Paper: https://arxiv.org/abs/2112.02125 Fixing Hardware Bugs Paper: https://arxiv.org/abs/2302.01215 Hardware Assertions Paper: https://arxiv.org/abs/2306.14027 Security Bug Finding Paper: https://arxiv.org/abs/2306.12643 LLM Metric Frameworks CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation Paper: https://arxiv.org/abs/2404.08806