From 033245f725ab72e70407cc6be7009ab7da28e3b6 Mon Sep 17 00:00:00 2001 From: Isuru Lakshan Date: Fri, 16 Jul 2021 21:42:50 +0530 Subject: [PATCH] control unit updated --- Branch n Jump unit(additional)/branchJump.v | 2 +- CONTROL UNIT module/controlUnit.v | 275 +++++++++++--------- Data Memory module/cacheMemory.v | 57 ++-- 3 files changed, 187 insertions(+), 147 deletions(-) diff --git a/Branch n Jump unit(additional)/branchJump.v b/Branch n Jump unit(additional)/branchJump.v index 3931a33..881483a 100644 --- a/Branch n Jump unit(additional)/branchJump.v +++ b/Branch n Jump unit(additional)/branchJump.v @@ -1,4 +1,4 @@ -// ######### Branch and Jump unit ######## +// ######### Branch and Jump unit(not completed) ######## //Delays should be introduced.. //whole module is asynchronous(no clock needed) diff --git a/CONTROL UNIT module/controlUnit.v b/CONTROL UNIT module/controlUnit.v index db62210..eab3729 100644 --- a/CONTROL UNIT module/controlUnit.v +++ b/CONTROL UNIT module/controlUnit.v @@ -3,15 +3,15 @@ //Delays should be introduced.. //compatible with the new datapath.. updated 6/7/2021 -module controlUnit(Instruction,mux1_select,mux2_select,mux3_select,mux4_select,mux5_select,memRead,memWrite,branch,jump,writeEnable,Immidiate,AlUop); //control unit module +module controlUnit(Instruction,mux1_select,mux2_select,mux3_select,mux4_select,memRead,memWrite,branch,jump,writeEnable,AlUop); //control unit module //port declaration input [31:0] Instruction; - output [2:0] Immidiate; output [4:0] AlUop; - output [2:0] branch_Jump; - output [1:0] mux3_select; - output mux1_select,mux2_select,mux4_select, + output branch,Jump; + output [1:0] mux4_select; + output [2:0] mux2_select; + output mux1_select,mux3_select, mux5_select,memRead,memWrite,branch,jump,writeEnable; reg [6:0] OPCODE; @@ -37,295 +37,316 @@ module controlUnit(Instruction,mux1_select,mux2_select,mux3_select,mux4_select,m always @(OPCODE) begin case(OPCODE) 7'b0110111:begin //U type (lui) instruction - instr_type = 4'b0000; - mux1_select = 1'bx; - mux2_select = 1'bx; - mux3_select = 2'b01; - mux4_select = 1'b0; - mux5_select = 1'bx; + instr_type = 4'b0000; + mux4_select = 2'b00; writeEnable = 1'b1; - memRead = 1'b0; - memWrite = 1'b0; + memRead = 1'b0; + memWrite = 1'b0; + branch = 1'b0; + jump = 1'b0; end 7'b0010111:begin //U type (auipc) instruction instr_type = 4'b0001; - mux1_select = 1'b0; - mux2_select = 1'b1; - mux3_select = 2'b01; - mux4_select = 1'b1; - mux5_select = 1'bx; + mux4_select = 2'b01; writeEnable = 1'b1; memRead = 1'b0; memWrite = 1'b0; + branch = 1'b0; + jump = 1'b0; end 7'b1101111:begin //jal instruction instr_type = 4'b0010; - mux1_select = 1'b0; - mux2_select = 1'b1; - mux3_select = 2'b10; - mux4_select = 1'b1; - mux5_select = 1'b0; + mux4_select = 2'b10; writeEnable = 1'b1; memRead = 1'b0; memWrite = 1'b0; + branch = 1'b0; + jump = 1'b1; end 7'b1100111:begin //jalr instruction instr_type = 4'b0011; - mux1_select = 1'b1; - mux2_select = 1'b1; - mux3_select = 2'b10; - mux4_select = 1'b1; - mux5_select = 1'b0; + mux4_select = 2'b10; writeEnable = 1'b1; memRead = 1'b0; memWrite = 1'b0; + branch = 1'b0; + jump = 1'b1; end 7'b1100011:begin //B type instructions instr_type = 4'b0100; - mux1_select = 1'b0; - mux2_select = 1'b1; - mux3_select = 2'bxx; - mux4_select = 1'b1; - mux5_select = 1'b1; + mux4_select = 2'b01; writeEnable = 1'b0; memRead = 1'b0; memWrite = 1'b0; + branch = 1'b1; + jump = 1'b0; end 7'b0000011:begin //I type (load) instructions instr_type = 4'b0101; - mux1_select = 1'b1; - mux2_select = 1'b1; - mux3_select = 2'b00; - mux4_select = 1'b1; - mux5_select = 1'bx; + mux4_select = 2'b01; writeEnable = 1'b1; memRead = 1'b1; memWrite = 1'b0; + branch = 1'b0; + jump = 1'b0; end 7'b0100011:begin //S type instructions instr_type = 4'b0110; - mux1_select = 1'b1; - mux2_select = 1'b1; - mux3_select = 2'bxx; - mux4_select = 1'b1; - mux5_select = 1'bx; + mux4_select = 2'b01; writeEnable = 1'b0; memRead = 1'b0; memWrite = 1'b1; + branch = 1'b0; + jump = 1'b0; end 7'b0010011:begin //I type instructions instr_type = 4'b0111; - mux1_select = 1'b1; - mux2_select = 1'b1; - mux3_select = 2'b01; - mux4_select = 1'b1; - mux5_select = 1'bx; + mux4_select = 2'b01; writeEnable = 1'b1; memRead = 1'b0; memWrite = 1'b0; + branch = 1'b0; + jump = 1'b0; end 7'b0110011:begin //R type instructions(with standard M extention) instr_type = 4'b1000; - mux1_select = 1'b1; - mux2_select = 1'b0; - mux3_select = 2'b01; - mux4_select = 1'b1; - mux5_select = 1'bx; + mux4_select = 2'b01; writeEnable = 1'b1; memRead = 1'b0; memWrite = 1'b0; + branch = 1'b0; + jump = 1'b0; end endcase end + + assign specific_OP = {funct7_A,funct7_B,funct3,instr_type}; //concatenation always @(specific_OP) begin casex(specific_OP) 9'bxxxxx0000: begin //LUI AlUop = 5'bxxxxx; - branch_Jump = 3'bxxx; - Immidiate = 3'b000; + mux1_select = 1'bx; + mux2_select = 3'b100; //forward + mux3_select = 1'b0; end 9'bxxxxx0001: begin //AUIPC AlUop = 5'b00000; - branch_Jump = 3'bxxx; - Immidiate = 3'b000; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxxxxx0010: begin //JAL AlUop = 5'b00000; - branch_Jump = 3'b000; - Immidiate = 3'b001; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxxxxx0011: begin //JALR AlUop = 5'b00000; - branch_Jump = 3'b001; - Immidiate = 3'b010; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx0000100: begin //B type instructions specific opcodes (BEQ) AlUop = 5'b00000; - branch_Jump = 3'b010; - Immidiate = 3'b011; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx0010100: begin //BNE AlUop = 5'b00000; - branch_Jump = 3'b011; - Immidiate = 3'b011; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx1000100: begin //BLT AlUop = 5'b00000; - branch_Jump = 3'b100; - Immidiate = 3'b011; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx1010100: begin //BGE AlUop = 5'b00000; - branch_Jump = 3'b101; - Immidiate = 3'b011; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx1100100: begin //BLTU AlUop = 5'b00000; - branch_Jump = 3'b110; - Immidiate = 3'b011; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx1110100: begin //BGEU AlUop = 5'b00000; - branch_Jump = 3'b111; - Immidiate = 3'b011; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end //I type(Load) and store type specific opcodes have to be finalized 9'bxx0000111: begin //I type instructions(ADDI) AlUop = 5'b00000; - branch_Jump = 3'bxxx; - Immidiate = 3'b010; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx0100111: begin //SLTI AlUop = 5'b10000; - branch_Jump = 3'bxxx; - Immidiate = 3'b010; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx0110111: begin //SLTiU AlUop = 5'b00001; - branch_Jump = 3'bxxx; - Immidiate = 3'b101; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx1000111: begin //XORI AlUop = 5'b00100; - branch_Jump = 3'bxxx; - Immidiate = 3'b010; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx1100111: begin //ORI AlUop = 5'b00011; - branch_Jump = 3'bxxx; - Immidiate = 3'b010; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'bxx1110111: begin //ANDI AlUop = 5'b00010; - branch_Jump = 3'bxxx; - Immidiate = 3'b010; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b000010111: begin //SLLI AlUop = 5'b00101; - branch_Jump = 3'bxxx; - Immidiate = 3'b010; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b001010111: begin //SRLI AlUop = 5'b00110; - branch_Jump = 3'bxxx; - Immidiate = 3'b010; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b101010111: begin //SRAI AlUop = 5'b00111; - branch_Jump = 3'bxxx; - Immidiate = 3'b010; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b001011000: begin //R type(ADD) AlUop = 5'b00000; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b101011000: begin //SUB AlUop = 5'b00001; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b001011000: begin //SLL AlUop = 5'b00101; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b001011000: begin //SLT AlUop = 5'b10000; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b001011000: begin //SLTU AlUop = 5'b10001; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b001011000: begin //XOR AlUop = 5'b00100; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b001011000: begin //SRL AlUop = 5'b00110; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b101011000: begin //SRA AlUop = 5'b00111; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b001011000: begin //OR AlUop = 5'b00011; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b001011000: begin //AND AlUop = 5'b00010; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b011011000: begin //M extention instructions (MUL) AlUop = 5'b01000; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b011011000: begin //MULH AlUop = 5'b01001; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b011011000: begin AlUop = 5'b01010; //MULHSU - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b011011000: begin //MULHU AlUop = 5'b01011; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b011011000: begin //DIV AlUop = 5'b01100; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b011011000: begin //DIVU AlUop = 5'b01101; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b011011000: begin //REM AlUop = 5'b01110; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end 9'b011011000: begin //REMU AlUop = 5'b01111; - branch_Jump = 3'bxxx; - Immidiate = 3'bxxx; + mux1_select = 1'bx; + mux2_select = 3'b000; + mux3_select = 1'b0; end endcase end diff --git a/Data Memory module/cacheMemory.v b/Data Memory module/cacheMemory.v index a89eed1..b367c66 100644 --- a/Data Memory module/cacheMemory.v +++ b/Data Memory module/cacheMemory.v @@ -8,7 +8,7 @@ module cacheMemory( writedata, readdata, busywait, - mem_Read,mem_Write,mem_Address,mem_Writedata,mem_Readdata,mem_BusyWait,Inst_hit); + mem_Read,mem_Write,mem_Address,mem_Writedata,mem_Readdata,mem_BusyWait,Inst_hit,funct3); input clock; input reset; @@ -28,55 +28,74 @@ input Inst_hit; //this signal is used to check wether there //in other words using this, I identify wether the instruction is correct for the respective PC. //since theres an asynchronous output to instruction cache, there may be incorrect instructions fetched //before the correct instruction come.so here before executing i check Inst_hit is asserted +input [1:0] funct3; //!to check which type of store instr(byte,half,full,upper) + /* Cache memory storage register files */ -reg[31:0] cache [0:7]; -reg[2:0] cacheTag [0:7]; +reg[127:0] cache [0:7]; +reg[24:0] cacheTag [0:7]; reg cacheDirty [0:7]; reg cacheValid [0:7]; -reg[1:0] Offset; +reg[3:0] Offset; reg[2:0] Index; -reg[2:0] Tag; +reg[24:0] Tag; /* dividing address to respective tag index and offset Asynchronousyly */ always@(address) begin if(Inst_hit)begin //LAB6 PART3 UPDATE:- checking Inst_hit is asserted if(read || write)begin #1 - Offset <= address[1:0]; //need to check - Index <= address[4:2]; - Tag <= address[7:5]; + Offset <= address[3:0]; //need to check + Index <= address[6:4]; + Tag <= address[31:7]; end end end /*Asynchronous comparator to compare tag and AND gate to check valid bit is set */ -wire comparatorOut; -wire hit,dirty; -wire[2:0] comparatorTagIN; -assign comparatorTagIN = cacheTag[Index]; -comparator group2_comparator(Tag,comparatorTagIN,comparatorOut); -ANDgate group2_ANDgate(cacheValid[Index],comparatorOut,hit); +// wire comparatorOut; +// wire hit,dirty; +// wire[2:0] comparatorTagIN; +// assign comparatorTagIN = cacheTag[Index]; +// comparator group2_comparator(Tag,comparatorTagIN,comparatorOut); +// ANDgate group2_ANDgate(cacheValid[Index],comparatorOut,hit); + +assign comparatorOut = (Tag == cacheTag[Index])? 1:0; //compare tags to check wether theres an entry in the cache memory_array +assign hit = (comparatorOut && cacheValid[Index])? 1:0; //resolve hit state when tag matches and entry is valid /*for future usage*/ assign dirty = cacheDirty[Index]; /*Asynchronous data extraction and assigning*/ -wire[7:0] dataExtractMuxOut; -wire[31:0] data; +// wire[31:0] dataExtractMuxOut; +// wire[127:0] data; +// assign data = cache[Index]; +// multiplexerType4 group2_dataExtractMux(data[7:0],data[15:8],data[23:16],data[31:24],dataExtractMuxOut,Offset); +// wire readdata; +// assign #1 readdata = dataExtractMuxOut; +wire[31:0] dataExtract; +wire[127:0] data; assign data = cache[Index]; -multiplexerType4 group2_dataExtractMux(data[7:0],data[15:8],data[23:16],data[31:24],dataExtractMuxOut,Offset); +always @(*) +begin + case(Offset[3:2]) + 2'b00: dataExtract = data[31:0]; + 2'b01: dataExtract = data[63:31]; + 2'b10: dataExtract = data[95:64]; + 2'b11: dataExtract = data[127:96]; +end wire readdata; -assign #1 readdata = dataExtractMuxOut; +assign #1 readdata = dataExtract; + /*set busywait whenever a write or read signal received*/ reg Busywait; reg readaccess, writeaccess; always @(read, write) begin - if(Inst_hit)begin //LAB6 PART3 UPDATE:- checking Inst_hit is asserted + if(Inst_hit)begin //checking Inst_hit is asserted Busywait = (read || write)? 1 : 0; readaccess = (read && !write)? 1 : 0; writeaccess = (!read && write)? 1 : 0;