[bug] ifnone state-dependent path delay

[likeamahoney]

Hi, All!

I found that ifnone condition used here and here is illegal due to SystemVerilog LRM IEEE 1800-2017 and it's previous versions due to section 30.4.4.4 - The ifnone condition description:

The ifnone keyword is used to specify a default state-dependent path delay when all other conditions for
the path are false. The ifnone condition shall specify the same module path source and destination as the
state-dependent module paths. The following rules apply to module paths specified with the ifnone
condition:
—
Only simple module paths may be described with an ifnone condition.
—The state-dependent paths that correspond to the ifnone path may be either simple module paths or
edge-sensitive paths

—If there are no corresponding state-dependent module paths to the ifnone module path, then the
ifnone module path shall be treated the same as an unconditional simple module path.
—
It is illegal to specify both an ifnone condition for a module path and an unconditional simple
module path for the same module path.

Which means that edge-sensitive path can't be specified under ifnone condition. Edge sensitive paths can be specified only in if conditions which correspond to ifnone .

[Blebowski]

Hi @likeamahoney,

maybe I got it wrong, but doesn't the following:

The state-dependent paths that correspond to the ifnone path may be either simple module paths or
edge-sensitive paths

allow having the edge-sensitive paths under ifnone ?

[sergeiandreyev]

Hi @Blebowski, there was a thread on this issue:
https://sourceforge.net/p/iverilog/feature-requests/32

[Blebowski]

Oh, I see, thanks.

It seems like inconsistency in the LRM itself, or not ?

The grammar says:

state_dependent_path_declaration ::=
      if ( module_path_expression ) simple_path_declaration
   | if ( module_path_expression ) edge_sensitive_path_declaration
   | ifnone simple_path_declaration

but the description says:

The state-dependent paths that correspond to the ifnone path may be either simple module paths or
edge-sensitive paths.

which would imply that edge-sensitive paths should be allowed here.

[Blebowski]

Oh, I see now:

You are misinterpreting B. It says the paths that correspond to the ifnone may be either simple or edge-sensitive not that the ifnone path can be edge-sensitive. For this definition correspond means the other state-dependent delays that have the same input and output terminals as the ifnone.

FYI this text is basically straight from the standard. 

[sergeiandreyev]

yes, basically we need to figure out how to update our specify blocks in Verilog models to be compatible with open source tools (which strictly follow the standard)
we did not catch the issue, because we're using commercial tools for PDK dev/validation, and they have some features on top of the standard as it shows up