how to use tolerances in LVS?

[olisnr]

i have MOSFETs with 15.975µm instead of 16:

what is the correct way to define tolerances for part-parameters?

[FaragElsayed2]

@olisnr Please share a small test case for this. Most probably, it's a grid issue but I need to recheck.

[olisnr]

@FaragElsayed2 yes, its a grid issue because 16µm/9 dont fit in a 5nm grid. if i change the value in the netlist, it works, but if there are many parts, that need to be changed from hand, it will be interesting to be able solve the problem via a tolerance. the testcase is: $87

OTA33_grid.zip

[FaragElsayed2]

@olisnr If you're confident that the issue is grid-related, there's no need to investigate further. To resolve it, you have two options:

1. Fix the DRC grid by trying a few methods, such as adjusting the database unit/scaling.

2. Add a tolerance for the specific parameter you need for each device, similar to the approach outlined here: KLayout LVS Global Parameters. However, this would require modifying the LVS runsets, which is not generally recommended.

By default, we’ve only added tolerances for inductors due to the complexity of geometry calculations.

[olisnr]

i think it should be possible for all parts that have some division in it, like FETs with multiple gates, to have a tolernace. also the resistors with bends show a different values in the PCell and the LVS-list.
would it be possible to make a w-tolerance for FETs, and a l-tolerance for the resistors as optional parameter?

[FaragElsayed2]

@olisnr I believe this isn't the ideal use case, but it might be worth discussing internally first.
CC @atorkmabrains.