From 4452f0acbaf378c579b20beaa602ad156842dd4d Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig <alyssa@rosenzweig.io> Date: Sun, 31 Mar 2024 19:57:40 -0400 Subject: [PATCH 1/2] ConstProp: optimize rmif with 0 for clc Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> --- .../Source/Interface/Core/JIT/Arm64/ALUOps.cpp | 2 +- FEXCore/Source/Interface/IR/Passes/ConstProp.cpp | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp index 129d05a4f4..218342ce65 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp @@ -334,7 +334,7 @@ DEF_OP(RmifNZCV) { auto Op = IROp->C<IR::IROp_RmifNZCV>(); LOGMAN_THROW_A_FMT(CTX->HostFeatures.SupportsFlagM, "Unsupported flagm op"); - rmif(GetReg(Op->Src.ID()).X(), Op->Rotate, Op->Mask); + rmif(GetZeroableReg(Op->Src).X(), Op->Rotate, Op->Mask); } DEF_OP(SetSmallNZV) { diff --git a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp index 192ae6520c..617de397b3 100644 --- a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp +++ b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp @@ -1138,6 +1138,21 @@ bool ConstProp::ConstantInlining(IREmitter *IREmit, const IRListView& CurrentIR) break; } + case OP_RMIFNZCV: + { + auto Op = IROp->C<IR::IROp_RmifNZCV>(); + + uint64_t Constant1{}; + if (IREmit->IsValueConstant(Op->Header.Args[0], &Constant1)) { + if (Constant1 == 0) { + IREmit->SetWriteCursor(CurrentIR.GetNode(Op->Header.Args[0])); + IREmit->ReplaceNodeArgument(CodeNode, 0, CreateInlineConstant(IREmit, 0)); + Changed = true; + } + } + + break; + } case OP_CONDADDNZCV: { auto Op = IROp->C<IR::IROp_CondAddNZCV>(); From b64a594b16b02f0476c53ea2c4306c962991709e Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig <alyssa@rosenzweig.io> Date: Sun, 31 Mar 2024 19:57:48 -0400 Subject: [PATCH 2/2] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> --- unittests/InstructionCountCI/FlagM/Primary.json | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 743376c771..631f337dfc 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -2353,11 +2353,10 @@ ] }, "clc": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0xf8", "ExpectedArm64ASM": [ - "mov w20, #0x0", - "rmif x20, #63, #nzCv" + "rmif xzr, #63, #nzCv" ] }, "stc": {