From 44c65c35c8c2f454c8941bf199ba834dc1bd74fc Mon Sep 17 00:00:00 2001 From: Paulo Matos Date: Wed, 29 Jan 2025 10:53:58 +0100 Subject: [PATCH] Revert "Enable RA of SVE Predicate Registers" This reverts commit fcbf0de05a470c1e92f1a5b828a855f5a2717f90. The initial user of this code has been re-implemented in b148cc6c. This is not needed any longer so we're removing it. --- FEXCore/Scripts/json_ir_generator.py | 10 ++++----- .../Core/ArchHelpers/Arm64Emitter.cpp | 21 ------------------- .../Interface/Core/ArchHelpers/Arm64Emitter.h | 1 - FEXCore/Source/Interface/Core/JIT/JIT.cpp | 1 - FEXCore/Source/Interface/Core/JIT/JITClass.h | 13 ------------ .../Source/Interface/Core/JIT/MemoryOps.cpp | 1 - FEXCore/Source/Interface/IR/IR.json | 3 --- FEXCore/Source/Interface/IR/IRDumper.cpp | 3 --- FEXCore/Source/Interface/IR/IREmitter.cpp | 1 - .../Interface/IR/Passes/RAValidation.cpp | 3 --- 10 files changed, 4 insertions(+), 53 deletions(-) diff --git a/FEXCore/Scripts/json_ir_generator.py b/FEXCore/Scripts/json_ir_generator.py index cda8d9c509..141ab5be5a 100755 --- a/FEXCore/Scripts/json_ir_generator.py +++ b/FEXCore/Scripts/json_ir_generator.py @@ -101,8 +101,7 @@ def is_ssa_type(type): if (type == "SSA" or type == "GPR" or type == "GPRPair" or - type == "FPR" or - type == "PRED"): + type == "FPR"): return True return False @@ -151,8 +150,8 @@ def parse_ops(ops): RHS += f", {DType}:$Out{Name}" else: # Single anonymous destination - if LHS not in ["SSA", "GPR", "GPRPair", "FPR", "PRED"]: - ExitError(f"Unknown destination class type {LHS}. Needs to be one of SSA, GPR, GPRPair, FPR, PRED") + if LHS not in ["SSA", "GPR", "GPRPair", "FPR"]: + ExitError(f"Unknown destination class type {LHS}. Needs to be one of SSA, GPR, GPRPair, FPR") OpDef.HasDest = True OpDef.DestType = LHS @@ -222,8 +221,7 @@ def parse_ops(ops): if (OpArg.IsSSA and (OpArg.Type == "GPR" or OpArg.Type == "GPRPair" or - OpArg.Type == "FPR" or - OpArg.Type == "PR")): + OpArg.Type == "FPR")): OpDef.EmitValidation.append(f"GetOpRegClass({ArgName}) == InvalidClass || WalkFindRegClass({ArgName}) == {OpArg.Type}Class") OpArg.Name = ArgName diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp index b49abc0e54..56796eabbd 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp +++ b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp @@ -56,12 +56,6 @@ namespace x64 { ARMEmitter::Reg::r24, ARMEmitter::Reg::r25, ARMEmitter::Reg::r30, ARMEmitter::Reg::r18, }; - // p6 and p7 registers are used as temporaries no not added here for RA - // See PREF_TMP_16B and PREF_TMP_32B - // p0-p1 are also used in the jit as temps. - // Also p8-p15 cannot be used can only encode p0-p7, p2 is a special register, so we're left with p3-p5. - constexpr std::array PR = {ARMEmitter::PReg::p3, ARMEmitter::PReg::p4, ARMEmitter::PReg::p5}; - constexpr unsigned RAPairs = 6; // All are caller saved @@ -109,12 +103,6 @@ namespace x64 { ARMEmitter::Reg::r16, ARMEmitter::Reg::r17, ARMEmitter::Reg::r30, }; - // p6 and p7 registers are used as temporaries no not added here for RA - // See PREF_TMP_16B and PREF_TMP_32B - // p0-p1 are also used in the jit as temps. - // Also p8-p15 cannot be used can only encode p0-p7, p2 is a special register, so we're left with p3-p5. - constexpr std::array PR = {ARMEmitter::PReg::p3, ARMEmitter::PReg::p4, ARMEmitter::PReg::p5}; - constexpr unsigned RAPairs = 6; constexpr std::array SRAFPR = { @@ -246,12 +234,6 @@ namespace x32 { constexpr unsigned RAPairs = 12; - // p6 and p7 registers are used as temporaries no not added here for RA - // See PREF_TMP_16B and PREF_TMP_32B - // p0-p1 are also used in the jit as temps. - // Also p8-p15 cannot be used can only encode p0-p7, p2 is a special register, so we're left with p3-p5. - constexpr std::array PR = {ARMEmitter::PReg::p3, ARMEmitter::PReg::p4, ARMEmitter::PReg::p5}; - // All are caller saved constexpr std::array SRAFPR = { ARMEmitter::VReg::v16, ARMEmitter::VReg::v17, ARMEmitter::VReg::v18, ARMEmitter::VReg::v19, @@ -375,7 +357,6 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl* ctx, void* EmissionPtr GeneralRegisters = x64::RA; StaticFPRegisters = x64::SRAFPR; GeneralFPRegisters = x64::RAFPR; - PredicateRegisters = x64::PR; PairRegisters = x64::RAPairs; #ifdef _M_ARM_64EC ConfiguredDynamicRegisterBase = std::span(x64::RA.begin(), 7); @@ -389,8 +370,6 @@ Arm64Emitter::Arm64Emitter(FEXCore::Context::ContextImpl* ctx, void* EmissionPtr StaticFPRegisters = x32::SRAFPR; GeneralFPRegisters = x32::RAFPR; - - PredicateRegisters = x32::PR; } } diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h index d61f14a8da..babcf0d5b7 100644 --- a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h +++ b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h @@ -107,7 +107,6 @@ class Arm64Emitter : public ARMEmitter::Emitter { std::span ConfiguredDynamicRegisterBase {}; std::span StaticRegisters {}; std::span GeneralRegisters {}; - std::span PredicateRegisters {}; std::span StaticFPRegisters {}; std::span GeneralFPRegisters {}; uint32_t PairRegisters = 0; diff --git a/FEXCore/Source/Interface/Core/JIT/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/JIT.cpp index 6cd71bb469..1929719c8f 100644 --- a/FEXCore/Source/Interface/Core/JIT/JIT.cpp +++ b/FEXCore/Source/Interface/Core/JIT/JIT.cpp @@ -540,7 +540,6 @@ Arm64JITCore::Arm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::In RAPass->AddRegisters(FEXCore::IR::GPRFixedClass, StaticRegisters.size()); RAPass->AddRegisters(FEXCore::IR::FPRClass, GeneralFPRegisters.size()); RAPass->AddRegisters(FEXCore::IR::FPRFixedClass, StaticFPRegisters.size()); - RAPass->AddRegisters(FEXCore::IR::PREDClass, PredicateRegisters.size()); RAPass->PairRegs = PairRegisters; { diff --git a/FEXCore/Source/Interface/Core/JIT/JITClass.h b/FEXCore/Source/Interface/Core/JIT/JITClass.h index 4e836b35d5..3023161449 100644 --- a/FEXCore/Source/Interface/Core/JIT/JITClass.h +++ b/FEXCore/Source/Interface/Core/JIT/JITClass.h @@ -95,19 +95,6 @@ class Arm64JITCore final : public CPUBackend, public Arm64Emitter { FEX_UNREACHABLE; } - [[nodiscard]] - ARMEmitter::PRegister GetPReg(IR::NodeID Node) const { - const auto Reg = GetPhys(Node); - - LOGMAN_THROW_A_FMT(Reg.Class == IR::PREDClass.Val, "Unexpected Class: {}", Reg.Class); - - if (Reg.Class == IR::PREDClass.Val) { - return PredicateRegisters[Reg.Reg]; - } - - FEX_UNREACHABLE; - } - [[nodiscard]] FEXCore::IR::RegisterClassType GetRegClass(IR::NodeID Node) const; diff --git a/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp b/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp index 47fdacfedf..155731e146 100644 --- a/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/MemoryOps.cpp @@ -11,7 +11,6 @@ tags: backend|arm64 #include "Interface/Core/ArchHelpers/Arm64Emitter.h" #include "Interface/Core/CPUID.h" #include "Interface/Core/JIT/JITClass.h" -#include "Interface/IR/IR.h" #include #include diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index d265046b90..bf4da61c7e 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -7,7 +7,6 @@ " SSA = untyped", " GPR = GPR class type", " FPR = FPR class type", - " PRED = Predicate register class type", "Declaring the SSA types correctly will allow validation passes to ensure the op is getting passed correct arguments", "", "Arguments must always follow a particular order. :", @@ -84,7 +83,6 @@ "constexpr FEXCore::IR::RegisterClassType GPRFixedClass {1}", "constexpr FEXCore::IR::RegisterClassType FPRClass {2}", "constexpr FEXCore::IR::RegisterClassType FPRFixedClass {3}", - "constexpr FEXCore::IR::RegisterClassType PREDClass {4}", "constexpr FEXCore::IR::RegisterClassType ComplexClass {5}", "constexpr FEXCore::IR::RegisterClassType InvalidClass {7}", "", @@ -150,7 +148,6 @@ "SSA": "OrderedNode*", "GPR": "OrderedNode*", "FPR": "OrderedNode*", - "PRED": "OrderedNode*", "FenceType": "FenceType", "RegisterClass": "RegisterClassType", "CondClass": "CondClassType", diff --git a/FEXCore/Source/Interface/IR/IRDumper.cpp b/FEXCore/Source/Interface/IR/IRDumper.cpp index 14051bf286..fab30b4074 100644 --- a/FEXCore/Source/Interface/IR/IRDumper.cpp +++ b/FEXCore/Source/Interface/IR/IRDumper.cpp @@ -77,8 +77,6 @@ static void PrintArg(fextl::stringstream* out, [[maybe_unused]] const IRListView *out << "FPR"; } else if (Arg == FPRFixedClass.Val) { *out << "FPRFixed"; - } else if (Arg == PREDClass.Val) { - *out << "PRED"; } else { *out << "Unknown Registerclass " << Arg; } @@ -100,7 +98,6 @@ static void PrintArg(fextl::stringstream* out, const IRListView* IR, OrderedNode case FEXCore::IR::GPRFixedClass.Val: *out << "(GPRFixed"; break; case FEXCore::IR::FPRClass.Val: *out << "(FPR"; break; case FEXCore::IR::FPRFixedClass.Val: *out << "(FPRFixed"; break; - case FEXCore::IR::PREDClass.Val: *out << "(PRED"; break; case FEXCore::IR::ComplexClass.Val: *out << "(Complex"; break; case FEXCore::IR::InvalidClass.Val: *out << "(Invalid"; break; default: *out << "(Unknown"; break; diff --git a/FEXCore/Source/Interface/IR/IREmitter.cpp b/FEXCore/Source/Interface/IR/IREmitter.cpp index a65c58ea69..61d7d4bcb6 100644 --- a/FEXCore/Source/Interface/IR/IREmitter.cpp +++ b/FEXCore/Source/Interface/IR/IREmitter.cpp @@ -41,7 +41,6 @@ FEXCore::IR::RegisterClassType IREmitter::WalkFindRegClass(Ref Node) { case FPRClass: case GPRFixedClass: case FPRFixedClass: - case PREDClass: case InvalidClass: return Class; default: break; } diff --git a/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp b/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp index bd10556b96..75e4ede6f7 100644 --- a/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp +++ b/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp @@ -47,7 +47,6 @@ struct RegState { // On arm64, there are 16 Fixed and 12 normal FPRsFixed[Reg.Reg] = ssa; return true; - case PREDClass: PREGs[Reg.Reg] = ssa; return true; } return false; } @@ -60,7 +59,6 @@ struct RegState { case GPRFixedClass: return GPRsFixed[Reg.Reg]; case FPRClass: return FPRs[Reg.Reg]; case FPRFixedClass: return FPRsFixed[Reg.Reg]; - case PREDClass: return PREGs[Reg.Reg]; } return InvalidReg; } @@ -84,7 +82,6 @@ struct RegState { std::array FPRsFixed = {}; std::array GPRs = {}; std::array FPRs = {}; - std::array PREGs = {}; fextl::unordered_map Spills; };