diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json
index 21fadc9802..4c78ab9cd2 100644
--- a/unittests/InstructionCountCI/FlagM/H0F38.json
+++ b/unittests/InstructionCountCI/FlagM/H0F38.json
@@ -12,28 +12,23 @@
   },
   "Instructions": {
     "ptest xmm0, xmm1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 12,
       "Comment": [
         "0x66 0x0f 0x38 0x17"
       ],
       "ExpectedArm64ASM": [
         "and v2.16b, v16.16b, v17.16b",
         "bic v3.16b, v17.16b, v16.16b",
-        "cnt v2.16b, v2.16b",
-        "cnt v3.16b, v3.16b",
-        "addv h2, v2.8h",
-        "addv h3, v3.8h",
+        "umaxv h2, v2.8h",
+        "umaxv h3, v3.8h",
         "umov w20, v2.h[0]",
         "umov w21, v3.h[0]",
         "mov w27, #0x0",
         "mov w26, #0x1",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
         "cmp x21, #0x0 (0)",
         "cset x21, eq",
-        "lsl x20, x20, #30",
-        "orr w20, w20, w21, lsl #29",
-        "msr nzcv, x20"
+        "tst w20, w20",
+        "rmif x21, #63, #NzCv"
       ]
     },
     "adcx eax, ebx": {
diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
index 42390392e4..57ff770de0 100644
--- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json
@@ -1431,13 +1431,12 @@
       ]
     },
     "rcl al, 1": {
-      "ExpectedInstructionCount": 8,
+      "ExpectedInstructionCount": 7,
       "Comment": "GROUP2 0xd0 /2",
       "ExpectedArm64ASM": [
         "uxtb w20, w4",
         "cset w21, hs",
-        "lsl w22, w20, #1",
-        "orr w21, w22, w21",
+        "orr w21, w21, w20, lsl #1",
         "bfxil x4, x21, #0, #8",
         "rmif x20, #6, #nzCv",
         "eor w20, w21, w20",
@@ -1567,13 +1566,12 @@
       ]
     },
     "rcl ax, 1": {
-      "ExpectedInstructionCount": 8,
+      "ExpectedInstructionCount": 7,
       "Comment": "GROUP2 0xd1 /2",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
         "cset w21, hs",
-        "lsl w22, w20, #1",
-        "orr w21, w22, w21",
+        "orr w21, w21, w20, lsl #1",
         "bfxil x4, x21, #0, #16",
         "rmif x20, #14, #nzCv",
         "eor w20, w21, w20",
@@ -1581,26 +1579,24 @@
       ]
     },
     "rcl eax, 1": {
-      "ExpectedInstructionCount": 7,
+      "ExpectedInstructionCount": 6,
       "Comment": "GROUP2 0xd1 /2",
       "ExpectedArm64ASM": [
         "mov w20, w4",
         "cset w21, hs",
-        "lsl w22, w20, #1",
-        "orr w4, w22, w21",
+        "orr w4, w21, w20, lsl #1",
         "rmif x20, #30, #nzCv",
         "eor w20, w4, w20",
         "rmif x20, #31, #nzcV"
       ]
     },
     "rcl rax, 1": {
-      "ExpectedInstructionCount": 7,
+      "ExpectedInstructionCount": 6,
       "Comment": "GROUP2 0xd1 /2",
       "ExpectedArm64ASM": [
         "mov x20, x4",
         "cset w21, hs",
-        "lsl x22, x20, #1",
-        "orr x4, x22, x21",
+        "orr x4, x21, x20, lsl #1",
         "rmif x20, #62, #nzCv",
         "eor x20, x4, x20",
         "rmif x20, #63, #nzcV"
diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json
index d0a30a9b1f..8c173f88d8 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary.json
@@ -779,13 +779,12 @@
       ]
     },
     "shld ax, bx, cl": {
-      "ExpectedInstructionCount": 24,
+      "ExpectedInstructionCount": 23,
       "Comment": "0x0f 0xad",
       "ExpectedArm64ASM": [
         "uxth w20, w7",
         "uxth w21, w4",
-        "uxtb w22, w5",
-        "and x22, x22, #0x1f",
+        "and x22, x5, #0x1f",
         "mov w23, #0x10",
         "sub x23, x23, x22",
         "lsl x24, x21, x22",
@@ -809,15 +808,13 @@
       ]
     },
     "shld eax, ebx, cl": {
-      "ExpectedInstructionCount": 24,
+      "ExpectedInstructionCount": 22,
       "Comment": "0x0f 0xad",
       "ExpectedArm64ASM": [
         "mov w20, w7",
         "mov w21, w4",
-        "uxtb w22, w5",
-        "and x22, x22, #0x1f",
-        "mov w23, #0x20",
-        "sub x23, x23, x22",
+        "and x22, x5, #0x1f",
+        "neg x23, x22",
         "lsl x24, x21, x22",
         "lsr w20, w20, w23",
         "orr x20, x24, x20",
@@ -839,14 +836,12 @@
       ]
     },
     "shld rax, rbx, cl": {
-      "ExpectedInstructionCount": 22,
+      "ExpectedInstructionCount": 20,
       "Comment": "0x0f 0xad",
       "ExpectedArm64ASM": [
         "mov x20, x4",
-        "uxtb w21, w5",
-        "and x21, x21, #0x3f",
-        "mov w22, #0x40",
-        "sub x22, x22, x21",
+        "and x21, x5, #0x3f",
+        "neg x22, x21",
         "lsl x23, x20, x21",
         "lsr x22, x7, x22",
         "orr x22, x23, x22",
diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json
index 5e80376203..3ffd30520f 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary_REP.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json
@@ -14,7 +14,7 @@
   },
   "Instructions": {
     "popcnt ax, bx": {
-      "ExpectedInstructionCount": 12,
+      "ExpectedInstructionCount": 9,
       "Comment": "0xf3 0x0f 0xb8",
       "ExpectedArm64ASM": [
         "uxth w20, w7",
@@ -23,16 +23,13 @@
         "addp v0.8b, v0.8b, v0.8b",
         "umov w20, v0.b[0]",
         "bfxil x4, x20, #0, #16",
+        "tst w20, w20",
         "mov w27, #0x0",
-        "mov w26, #0x1",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "mov w26, #0x1"
       ]
     },
     "popcnt eax, ebx": {
-      "ExpectedInstructionCount": 11,
+      "ExpectedInstructionCount": 8,
       "Comment": "0xf3 0x0f 0xb8",
       "ExpectedArm64ASM": [
         "mov w20, w7",
@@ -40,28 +37,22 @@
         "cnt v0.8b, v0.8b",
         "addv b0, v0.8b",
         "umov w4, v0.b[0]",
+        "tst w4, w4",
         "mov w27, #0x0",
-        "mov w26, #0x1",
-        "cmp x4, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "mov w26, #0x1"
       ]
     },
     "popcnt rax, rbx": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 7,
       "Comment": "0xf3 0x0f 0xb8",
       "ExpectedArm64ASM": [
         "fmov d0, x7",
         "cnt v0.8b, v0.8b",
         "addv b0, v0.8b",
         "umov w4, v0.b[0]",
+        "tst w4, w4",
         "mov w27, #0x0",
-        "mov w26, #0x1",
-        "cmp x4, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "mov w26, #0x1"
       ]
     },
     "tzcnt ax, bx": {
diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json
index 75bb9401e7..84e93079a9 100644
--- a/unittests/InstructionCountCI/FlagM/VEX_map2.json
+++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json
@@ -164,61 +164,43 @@
       ]
     },
     "vptest xmm0, xmm1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 12,
       "Comment": [
         "Map 2 0b01 0x16 128-bit"
       ],
       "ExpectedArm64ASM": [
         "and v2.16b, v16.16b, v17.16b",
         "bic v3.16b, v17.16b, v16.16b",
-        "cnt v2.16b, v2.16b",
-        "cnt v3.16b, v3.16b",
-        "addv h2, v2.8h",
-        "addv h3, v3.8h",
+        "umaxv h2, v2.8h",
+        "umaxv h3, v3.8h",
         "umov w20, v2.h[0]",
         "umov w21, v3.h[0]",
         "mov w27, #0x0",
         "mov w26, #0x1",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
         "cmp x21, #0x0 (0)",
         "cset x21, eq",
-        "lsl x20, x20, #30",
-        "orr w20, w20, w21, lsl #29",
-        "msr nzcv, x20"
+        "tst w20, w20",
+        "rmif x21, #63, #NzCv"
       ]
     },
     "vptest ymm0, ymm1": {
-      "ExpectedInstructionCount": 25,
+      "ExpectedInstructionCount": 12,
       "Comment": [
         "Map 2 0b01 0x16 256-bit"
       ],
       "ExpectedArm64ASM": [
         "and z2.d, z16.d, z17.d",
         "bic z3.d, z17.d, z16.d",
-        "cnt z2.b, p7/m, z2.b",
-        "cnt z3.b, p7/m, z3.b",
-        "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z2.d",
-        "addv h1, v2.8h",
-        "addv h0, v0.8h",
-        "add v2.8h, v0.8h, v1.8h",
-        "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z3.d",
-        "addv h1, v3.8h",
-        "addv h0, v0.8h",
-        "add v3.8h, v0.8h, v1.8h",
+        "umaxv h2, p7, z2.h",
+        "umaxv h3, p7, z3.h",
         "umov w20, v2.h[0]",
         "umov w21, v3.h[0]",
         "mov w27, #0x0",
         "mov w26, #0x1",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
         "cmp x21, #0x0 (0)",
         "cset x21, eq",
-        "lsl x20, x20, #30",
-        "orr w20, w20, w21, lsl #29",
-        "msr nzcv, x20"
+        "tst w20, w20",
+        "rmif x21, #63, #NzCv"
       ]
     },
     "vmaskmovps xmm0, xmm1, [rax]": {
@@ -472,127 +454,89 @@
       ]
     },
     "pdep eax, ebx, ecx": {
-      "ExpectedInstructionCount": 29,
+      "ExpectedInstructionCount": 16,
       "Comment": [
         "Map 2 0b11 0xf5 32-bit"
       ],
       "ExpectedArm64ASM": [
         "mov w20, w7",
         "mov w21, w5",
-        "cbz w21, #+0x68",
-        "mov w3, wzr",
-        "mrs x0, nzcv",
-        "str w0, [x28, #728]",
-        "stp x4, x5, [x28, #8]",
-        "str x6, [x28, #24]",
-        "mov w4, w20",
-        "mov w5, w21",
-        "mov w6, wzr",
-        "rbit w0, w5",
-        "clz w0, w0",
-        "lsr w1, w4, w3",
-        "and w1, w1, #0x1",
-        "sub w2, w5, #0x1 (1)",
-        "add w3, w3, #0x1 (1)",
-        "ands w5, w5, w2",
-        "lsl w0, w1, w0",
-        "orr w6, w6, w0",
-        "b.ne #-0x24",
-        "mov w3, w6",
-        "ldr w4, [x28, #728]",
-        "msr nzcv, x4",
-        "ldp x4, x5, [x28, #8]",
-        "ldr x6, [x28, #24]",
-        "mov w4, w3",
-        "b #+0x8",
-        "mov w4, wzr"
+        "mov w4, wzr",
+        "cbz w21, #+0x34",
+        "mov w0, w20",
+        "mov w1, w21",
+        "neg w2, w1",
+        "and w2, w2, w1",
+        "sbfx w3, w0, #0, #1",
+        "eor w1, w1, w2",
+        "and w2, w3, w2",
+        "neg w3, w1",
+        "orr w4, w4, w2",
+        "lsr w0, w0, #1",
+        "and w2, w1, w3",
+        "cbnz w2, #-0x1c"
       ]
     },
     "pdep rax, rbx, rcx": {
-      "ExpectedInstructionCount": 27,
+      "ExpectedInstructionCount": 14,
       "Comment": [
         "Map 2 0b11 0xf5 64-bit"
       ],
       "ExpectedArm64ASM": [
-        "cbz x5, #+0x68",
-        "mov x3, xzr",
-        "mrs x0, nzcv",
-        "str w0, [x28, #728]",
-        "stp x4, x5, [x28, #8]",
-        "str x6, [x28, #24]",
-        "mov x4, x7",
-        "mov x5, x5",
-        "mov x6, xzr",
-        "rbit x0, x5",
-        "clz x0, x0",
-        "lsr x1, x4, x3",
-        "and x1, x1, #0x1",
-        "sub x2, x5, #0x1 (1)",
-        "add x3, x3, #0x1 (1)",
-        "ands x5, x5, x2",
-        "lsl x0, x1, x0",
-        "orr x6, x6, x0",
-        "b.ne #-0x24",
-        "mov x3, x6",
-        "ldr w4, [x28, #728]",
-        "msr nzcv, x4",
-        "ldp x4, x5, [x28, #8]",
-        "ldr x6, [x28, #24]",
-        "mov x4, x3",
-        "b #+0x8",
-        "mov x4, xzr"
+        "mov x4, xzr",
+        "cbz x5, #+0x34",
+        "mov x0, x7",
+        "mov x1, x5",
+        "neg x2, x1",
+        "and x2, x2, x1",
+        "sbfx x3, x0, #0, #1",
+        "eor x1, x1, x2",
+        "and x2, x3, x2",
+        "neg x3, x1",
+        "orr x4, x4, x2",
+        "lsr x0, x0, #1",
+        "and x2, x1, x3",
+        "cbnz x2, #-0x1c"
       ]
     },
     "bextr eax, ebx, ecx": {
-      "ExpectedInstructionCount": 19,
+      "ExpectedInstructionCount": 12,
       "Comment": [
         "Map 2 0b00 0xf7 32-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, w7",
-        "mov w21, w5",
-        "mov w22, #0x1f",
-        "uxtb w23, w21",
-        "lsr w20, w20, w23",
-        "mov w24, #0x0",
-        "cmp w23, #0x1f (31)",
-        "csel w20, w20, w24, ls",
-        "ubfx w21, w21, #8, #8",
+        "uxtb w20, w5",
+        "lsr w21, w7, w20",
+        "mov w22, #0x0",
+        "cmp w20, #0x1f (31)",
+        "csel w20, w21, w22, ls",
+        "ubfx w21, w5, #8, #8",
+        "mov x22, #0xffffffffffffffff",
+        "lsl w22, w22, w21",
+        "bic w22, w20, w22",
         "cmp w21, #0x1f (31)",
-        "csel w21, w21, w22, ls",
-        "mov w22, #0x1",
-        "lsl w21, w22, w21",
-        "sub w21, w21, #0x1 (1)",
-        "and w4, w20, w21",
-        "cmp x4, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "csel w4, w22, w20, ls",
+        "tst w4, w4"
       ]
     },
     "bextr rax, rbx, rcx": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 12,
       "Comment": [
         "Map 2 0b00 0xf7 64-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, #0x3f",
-        "uxtb x21, w5",
-        "lsr x22, x7, x21",
-        "mov w23, #0x0",
+        "uxtb x20, w5",
+        "lsr x21, x7, x20",
+        "mov w22, #0x0",
+        "cmp x20, #0x3f (63)",
+        "csel x20, x21, x22, ls",
+        "ubfx x21, x5, #8, #8",
+        "mov x22, #0xffffffffffffffff",
+        "lsl x22, x22, x21",
+        "bic x22, x20, x22",
         "cmp x21, #0x3f (63)",
-        "csel x21, x22, x23, ls",
-        "ubfx x22, x5, #8, #8",
-        "cmp x22, #0x3f (63)",
-        "csel x20, x22, x20, ls",
-        "mov w22, #0x1",
-        "lsl x20, x22, x20",
-        "sub x20, x20, #0x1 (1)",
-        "and x4, x21, x20",
-        "cmp x4, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "csel x4, x22, x20, ls",
+        "tst x4, x4"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json
index 14646f118c..277bfad731 100644
--- a/unittests/InstructionCountCI/FlagM/VEX_map_group.json
+++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json
@@ -10,98 +10,76 @@
   },
   "Instructions": {
     "blsr eax, ebx": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 6,
       "Comment": [
         "Map group 17 0b001 32-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, w7",
-        "sub x21, x20, #0x1 (1)",
-        "and x21, x21, x20",
-        "mov w4, w21",
-        "tst w21, w21",
-        "mrs x21, nzcv",
-        "cmp x20, #0x0 (0)",
-        "cset x20, ne",
-        "orr w20, w21, w20, lsl #29",
-        "msr nzcv, x20"
+        "sub w20, w7, #0x1 (1)",
+        "and w4, w20, w7",
+        "cmp x7, #0x0 (0)",
+        "cset x20, eq",
+        "tst w4, w4",
+        "rmif x20, #63, #nzCv"
       ]
     },
     "blsr rax, rbx": {
-      "ExpectedInstructionCount": 8,
+      "ExpectedInstructionCount": 6,
       "Comment": [
         "Map group 17 0b001 64-bit"
       ],
       "ExpectedArm64ASM": [
         "sub x20, x7, #0x1 (1)",
         "and x4, x20, x7",
-        "tst x4, x4",
-        "mrs x20, nzcv",
         "cmp x7, #0x0 (0)",
-        "cset x21, ne",
-        "orr w20, w20, w21, lsl #29",
-        "msr nzcv, x20"
+        "cset x20, eq",
+        "tst x4, x4",
+        "rmif x20, #63, #nzCv"
       ]
     },
     "blsmsk eax, ebx": {
-      "ExpectedInstructionCount": 13,
+      "ExpectedInstructionCount": 6,
       "Comment": [
         "Map group 17 0b010 32-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, w7",
-        "sub x21, x20, #0x1 (1)",
-        "eor x21, x21, x20",
-        "mov w4, w21",
-        "mov w22, #0x50000000",
-        "mrs x23, nzcv",
-        "bic x22, x23, x22",
-        "cmp x20, #0x0 (0)",
+        "sub w20, w7, #0x1 (1)",
+        "eor w4, w20, w7",
+        "cmp x7, #0x0 (0)",
         "cset x20, eq",
-        "msr nzcv, x22",
-        "rmif x20, #63, #nzCv",
-        "lsr w20, w21, #31",
-        "rmif x20, #61, #Nzcv"
+        "tst w4, w4",
+        "rmif x20, #63, #nzCv"
       ]
     },
     "blsmsk rax, rbx": {
-      "ExpectedInstructionCount": 11,
+      "ExpectedInstructionCount": 6,
       "Comment": [
         "Map group 17 0b010 64-bit"
       ],
       "ExpectedArm64ASM": [
         "sub x20, x7, #0x1 (1)",
         "eor x4, x20, x7",
-        "mov w20, #0x50000000",
-        "mrs x21, nzcv",
-        "bic x20, x21, x20",
         "cmp x7, #0x0 (0)",
-        "cset x21, eq",
-        "msr nzcv, x20",
-        "rmif x21, #63, #nzCv",
-        "lsr x20, x4, #63",
-        "rmif x20, #61, #Nzcv"
+        "cset x20, eq",
+        "tst x4, x4",
+        "rmif x20, #63, #nzCv"
       ]
     },
     "blsi eax, ebx": {
-      "ExpectedInstructionCount": 9,
+      "ExpectedInstructionCount": 5,
       "Comment": [
         "Map group 17 0b011 32-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, w7",
-        "neg w21, w20",
-        "and w4, w20, w21",
+        "neg w20, w7",
+        "and w4, w7, w20",
         "tst w4, w4",
-        "mrs x20, nzcv",
-        "cmp x4, #0x0 (0)",
-        "cset x21, ne",
-        "orr w20, w20, w21, lsl #29",
-        "msr nzcv, x20"
+        "cset w20, ne",
+        "rmif x20, #63, #nzCv"
       ]
     },
     "blsi rax, rbx": {
-      "ExpectedInstructionCount": 8,
+      "ExpectedInstructionCount": 5,
       "Comment": [
         "Map group 17 0b011 64-bit"
       ],
@@ -109,11 +87,8 @@
         "neg x20, x7",
         "and x4, x7, x20",
         "tst x4, x4",
-        "mrs x20, nzcv",
-        "cmp x4, #0x0 (0)",
-        "cset x21, ne",
-        "orr w20, w20, w21, lsl #29",
-        "msr nzcv, x20"
+        "cset w20, ne",
+        "rmif x20, #63, #nzCv"
       ]
     }
   }
diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json
index 0a4375536b..2d4e4e84cd 100644
--- a/unittests/InstructionCountCI/H0F38.json
+++ b/unittests/InstructionCountCI/H0F38.json
@@ -389,27 +389,25 @@
       ]
     },
     "ptest xmm0, xmm1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "0x66 0x0f 0x38 0x17"
       ],
       "ExpectedArm64ASM": [
         "and v2.16b, v16.16b, v17.16b",
         "bic v3.16b, v17.16b, v16.16b",
-        "cnt v2.16b, v2.16b",
-        "cnt v3.16b, v3.16b",
-        "addv h2, v2.8h",
-        "addv h3, v3.8h",
+        "umaxv h2, v2.8h",
+        "umaxv h3, v3.8h",
         "umov w20, v2.h[0]",
         "umov w21, v3.h[0]",
         "mov w27, #0x0",
         "mov w26, #0x1",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
         "cmp x21, #0x0 (0)",
         "cset x21, eq",
-        "lsl x20, x20, #30",
+        "tst w20, w20",
+        "mrs x20, nzcv",
         "orr w20, w20, w21, lsl #29",
+        "and w20, w20, #0x7fffffff",
         "msr nzcv, x20"
       ]
     },
diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json
index 8c3ee4fc23..08abd68e5c 100644
--- a/unittests/InstructionCountCI/PrimaryGroup.json
+++ b/unittests/InstructionCountCI/PrimaryGroup.json
@@ -1636,13 +1636,12 @@
       ]
     },
     "rcl al, 1": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 15,
       "Comment": "GROUP2 0xd0 /2",
       "ExpectedArm64ASM": [
         "uxtb w20, w4",
         "cset w21, hs",
-        "lsl w22, w20, #1",
-        "orr w21, w22, w21",
+        "orr w21, w21, w20, lsl #1",
         "bfxil x4, x21, #0, #8",
         "ubfx x22, x20, #7, #1",
         "mrs x23, nzcv",
@@ -1828,13 +1827,12 @@
       ]
     },
     "rcl ax, 1": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 15,
       "Comment": "GROUP2 0xd1 /2",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
         "cset w21, hs",
-        "lsl w22, w20, #1",
-        "orr w21, w22, w21",
+        "orr w21, w21, w20, lsl #1",
         "bfxil x4, x21, #0, #16",
         "ubfx x22, x20, #15, #1",
         "mrs x23, nzcv",
@@ -1850,13 +1848,12 @@
       ]
     },
     "rcl eax, 1": {
-      "ExpectedInstructionCount": 15,
+      "ExpectedInstructionCount": 14,
       "Comment": "GROUP2 0xd1 /2",
       "ExpectedArm64ASM": [
         "mov w20, w4",
         "cset w21, hs",
-        "lsl w22, w20, #1",
-        "orr w4, w22, w21",
+        "orr w4, w21, w20, lsl #1",
         "ubfx x21, x20, #31, #1",
         "mrs x22, nzcv",
         "mov w0, w22",
@@ -1871,13 +1868,12 @@
       ]
     },
     "rcl rax, 1": {
-      "ExpectedInstructionCount": 15,
+      "ExpectedInstructionCount": 14,
       "Comment": "GROUP2 0xd1 /2",
       "ExpectedArm64ASM": [
         "mov x20, x4",
         "cset w21, hs",
-        "lsl x22, x20, #1",
-        "orr x4, x22, x21",
+        "orr x4, x21, x20, lsl #1",
         "lsr x21, x20, #63",
         "mrs x22, nzcv",
         "mov w0, w22",
diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json
index 591b8751ba..2c13ad430c 100644
--- a/unittests/InstructionCountCI/Secondary.json
+++ b/unittests/InstructionCountCI/Secondary.json
@@ -1593,13 +1593,12 @@
       ]
     },
     "shld ax, bx, cl": {
-      "ExpectedInstructionCount": 28,
+      "ExpectedInstructionCount": 27,
       "Comment": "0x0f 0xad",
       "ExpectedArm64ASM": [
         "uxth w20, w7",
         "uxth w21, w4",
-        "uxtb w22, w5",
-        "and x22, x22, #0x1f",
+        "and x22, x5, #0x1f",
         "mov w23, #0x10",
         "sub x23, x23, x22",
         "lsl x24, x21, x22",
@@ -1627,15 +1626,13 @@
       ]
     },
     "shld eax, ebx, cl": {
-      "ExpectedInstructionCount": 28,
+      "ExpectedInstructionCount": 26,
       "Comment": "0x0f 0xad",
       "ExpectedArm64ASM": [
         "mov w20, w7",
         "mov w21, w4",
-        "uxtb w22, w5",
-        "and x22, x22, #0x1f",
-        "mov w23, #0x20",
-        "sub x23, x23, x22",
+        "and x22, x5, #0x1f",
+        "neg x23, x22",
         "lsl x24, x21, x22",
         "lsr w20, w20, w23",
         "orr x20, x24, x20",
@@ -1661,14 +1658,12 @@
       ]
     },
     "shld rax, rbx, cl": {
-      "ExpectedInstructionCount": 26,
+      "ExpectedInstructionCount": 24,
       "Comment": "0x0f 0xad",
       "ExpectedArm64ASM": [
         "mov x20, x4",
-        "uxtb w21, w5",
-        "and x21, x21, #0x3f",
-        "mov w22, #0x40",
-        "sub x22, x22, x21",
+        "and x21, x5, #0x3f",
+        "neg x22, x21",
         "lsl x23, x20, x21",
         "lsr x22, x7, x22",
         "orr x22, x23, x22",
diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json
index 71004c1fba..46b84496d6 100644
--- a/unittests/InstructionCountCI/Secondary_REP.json
+++ b/unittests/InstructionCountCI/Secondary_REP.json
@@ -399,7 +399,7 @@
       ]
     },
     "popcnt ax, bx": {
-      "ExpectedInstructionCount": 12,
+      "ExpectedInstructionCount": 9,
       "Comment": "0xf3 0x0f 0xb8",
       "ExpectedArm64ASM": [
         "uxth w20, w7",
@@ -408,16 +408,13 @@
         "addp v0.8b, v0.8b, v0.8b",
         "umov w20, v0.b[0]",
         "bfxil x4, x20, #0, #16",
+        "tst w20, w20",
         "mov w27, #0x0",
-        "mov w26, #0x1",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "mov w26, #0x1"
       ]
     },
     "popcnt eax, ebx": {
-      "ExpectedInstructionCount": 11,
+      "ExpectedInstructionCount": 8,
       "Comment": "0xf3 0x0f 0xb8",
       "ExpectedArm64ASM": [
         "mov w20, w7",
@@ -425,28 +422,22 @@
         "cnt v0.8b, v0.8b",
         "addv b0, v0.8b",
         "umov w4, v0.b[0]",
+        "tst w4, w4",
         "mov w27, #0x0",
-        "mov w26, #0x1",
-        "cmp x4, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "mov w26, #0x1"
       ]
     },
     "popcnt rax, rbx": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 7,
       "Comment": "0xf3 0x0f 0xb8",
       "ExpectedArm64ASM": [
         "fmov d0, x7",
         "cnt v0.8b, v0.8b",
         "addv b0, v0.8b",
         "umov w4, v0.b[0]",
+        "tst w4, w4",
         "mov w27, #0x0",
-        "mov w26, #0x1",
-        "cmp x4, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "mov w26, #0x1"
       ]
     },
     "tzcnt ax, bx": {
diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json
index 336a21492f..29850b5b3f 100644
--- a/unittests/InstructionCountCI/VEX_map2.json
+++ b/unittests/InstructionCountCI/VEX_map2.json
@@ -683,60 +683,48 @@
       ]
     },
     "vptest xmm0, xmm1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "Map 2 0b01 0x16 128-bit"
       ],
       "ExpectedArm64ASM": [
         "and v2.16b, v16.16b, v17.16b",
         "bic v3.16b, v17.16b, v16.16b",
-        "cnt v2.16b, v2.16b",
-        "cnt v3.16b, v3.16b",
-        "addv h2, v2.8h",
-        "addv h3, v3.8h",
+        "umaxv h2, v2.8h",
+        "umaxv h3, v3.8h",
         "umov w20, v2.h[0]",
         "umov w21, v3.h[0]",
         "mov w27, #0x0",
         "mov w26, #0x1",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
         "cmp x21, #0x0 (0)",
         "cset x21, eq",
-        "lsl x20, x20, #30",
+        "tst w20, w20",
+        "mrs x20, nzcv",
         "orr w20, w20, w21, lsl #29",
+        "and w20, w20, #0x7fffffff",
         "msr nzcv, x20"
       ]
     },
     "vptest ymm0, ymm1": {
-      "ExpectedInstructionCount": 25,
+      "ExpectedInstructionCount": 15,
       "Comment": [
         "Map 2 0b01 0x16 256-bit"
       ],
       "ExpectedArm64ASM": [
         "and z2.d, z16.d, z17.d",
         "bic z3.d, z17.d, z16.d",
-        "cnt z2.b, p7/m, z2.b",
-        "cnt z3.b, p7/m, z3.b",
-        "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z2.d",
-        "addv h1, v2.8h",
-        "addv h0, v0.8h",
-        "add v2.8h, v0.8h, v1.8h",
-        "not p0.b, p7/z, p6.b",
-        "compact z0.d, p0, z3.d",
-        "addv h1, v3.8h",
-        "addv h0, v0.8h",
-        "add v3.8h, v0.8h, v1.8h",
+        "umaxv h2, p7, z2.h",
+        "umaxv h3, p7, z3.h",
         "umov w20, v2.h[0]",
         "umov w21, v3.h[0]",
         "mov w27, #0x0",
         "mov w26, #0x1",
-        "cmp x20, #0x0 (0)",
-        "cset x20, eq",
         "cmp x21, #0x0 (0)",
         "cset x21, eq",
-        "lsl x20, x20, #30",
+        "tst w20, w20",
+        "mrs x20, nzcv",
         "orr w20, w20, w21, lsl #29",
+        "and w20, w20, #0x7fffffff",
         "msr nzcv, x20"
       ]
     },
@@ -3329,75 +3317,49 @@
       ]
     },
     "pdep eax, ebx, ecx": {
-      "ExpectedInstructionCount": 29,
+      "ExpectedInstructionCount": 16,
       "Comment": [
         "Map 2 0b11 0xf5 32-bit"
       ],
       "ExpectedArm64ASM": [
         "mov w20, w7",
         "mov w21, w5",
-        "cbz w21, #+0x68",
-        "mov w3, wzr",
-        "mrs x0, nzcv",
-        "str w0, [x28, #728]",
-        "stp x4, x5, [x28, #8]",
-        "str x6, [x28, #24]",
-        "mov w4, w20",
-        "mov w5, w21",
-        "mov w6, wzr",
-        "rbit w0, w5",
-        "clz w0, w0",
-        "lsr w1, w4, w3",
-        "and w1, w1, #0x1",
-        "sub w2, w5, #0x1 (1)",
-        "add w3, w3, #0x1 (1)",
-        "ands w5, w5, w2",
-        "lsl w0, w1, w0",
-        "orr w6, w6, w0",
-        "b.ne #-0x24",
-        "mov w3, w6",
-        "ldr w4, [x28, #728]",
-        "msr nzcv, x4",
-        "ldp x4, x5, [x28, #8]",
-        "ldr x6, [x28, #24]",
-        "mov w4, w3",
-        "b #+0x8",
-        "mov w4, wzr"
+        "mov w4, wzr",
+        "cbz w21, #+0x34",
+        "mov w0, w20",
+        "mov w1, w21",
+        "neg w2, w1",
+        "and w2, w2, w1",
+        "sbfx w3, w0, #0, #1",
+        "eor w1, w1, w2",
+        "and w2, w3, w2",
+        "neg w3, w1",
+        "orr w4, w4, w2",
+        "lsr w0, w0, #1",
+        "and w2, w1, w3",
+        "cbnz w2, #-0x1c"
       ]
     },
     "pdep rax, rbx, rcx": {
-      "ExpectedInstructionCount": 27,
+      "ExpectedInstructionCount": 14,
       "Comment": [
         "Map 2 0b11 0xf5 64-bit"
       ],
       "ExpectedArm64ASM": [
-        "cbz x5, #+0x68",
-        "mov x3, xzr",
-        "mrs x0, nzcv",
-        "str w0, [x28, #728]",
-        "stp x4, x5, [x28, #8]",
-        "str x6, [x28, #24]",
-        "mov x4, x7",
-        "mov x5, x5",
-        "mov x6, xzr",
-        "rbit x0, x5",
-        "clz x0, x0",
-        "lsr x1, x4, x3",
-        "and x1, x1, #0x1",
-        "sub x2, x5, #0x1 (1)",
-        "add x3, x3, #0x1 (1)",
-        "ands x5, x5, x2",
-        "lsl x0, x1, x0",
-        "orr x6, x6, x0",
-        "b.ne #-0x24",
-        "mov x3, x6",
-        "ldr w4, [x28, #728]",
-        "msr nzcv, x4",
-        "ldp x4, x5, [x28, #8]",
-        "ldr x6, [x28, #24]",
-        "mov x4, x3",
-        "b #+0x8",
-        "mov x4, xzr"
+        "mov x4, xzr",
+        "cbz x5, #+0x34",
+        "mov x0, x7",
+        "mov x1, x5",
+        "neg x2, x1",
+        "and x2, x2, x1",
+        "sbfx x3, x0, #0, #1",
+        "eor x1, x1, x2",
+        "and x2, x3, x2",
+        "neg x3, x1",
+        "orr x4, x4, x2",
+        "lsr x0, x0, #1",
+        "and x2, x1, x3",
+        "cbnz x2, #-0x1c"
       ]
     },
     "mulx eax, ebx, ecx": {
@@ -3473,55 +3435,43 @@
       ]
     },
     "bextr eax, ebx, ecx": {
-      "ExpectedInstructionCount": 19,
+      "ExpectedInstructionCount": 12,
       "Comment": [
         "Map 2 0b00 0xf7 32-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, w7",
-        "mov w21, w5",
-        "mov w22, #0x1f",
-        "uxtb w23, w21",
-        "lsr w20, w20, w23",
-        "mov w24, #0x0",
-        "cmp w23, #0x1f (31)",
-        "csel w20, w20, w24, ls",
-        "ubfx w21, w21, #8, #8",
+        "uxtb w20, w5",
+        "lsr w21, w7, w20",
+        "mov w22, #0x0",
+        "cmp w20, #0x1f (31)",
+        "csel w20, w21, w22, ls",
+        "ubfx w21, w5, #8, #8",
+        "mov x22, #0xffffffffffffffff",
+        "lsl w22, w22, w21",
+        "bic w22, w20, w22",
         "cmp w21, #0x1f (31)",
-        "csel w21, w21, w22, ls",
-        "mov w22, #0x1",
-        "lsl w21, w22, w21",
-        "sub w21, w21, #0x1 (1)",
-        "and w4, w20, w21",
-        "cmp x4, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "csel w4, w22, w20, ls",
+        "tst w4, w4"
       ]
     },
     "bextr rax, rbx, rcx": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 12,
       "Comment": [
         "Map 2 0b00 0xf7 64-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, #0x3f",
-        "uxtb x21, w5",
-        "lsr x22, x7, x21",
-        "mov w23, #0x0",
+        "uxtb x20, w5",
+        "lsr x21, x7, x20",
+        "mov w22, #0x0",
+        "cmp x20, #0x3f (63)",
+        "csel x20, x21, x22, ls",
+        "ubfx x21, x5, #8, #8",
+        "mov x22, #0xffffffffffffffff",
+        "lsl x22, x22, x21",
+        "bic x22, x20, x22",
         "cmp x21, #0x3f (63)",
-        "csel x21, x22, x23, ls",
-        "ubfx x22, x5, #8, #8",
-        "cmp x22, #0x3f (63)",
-        "csel x20, x22, x20, ls",
-        "mov w22, #0x1",
-        "lsl x20, x22, x20",
-        "sub x20, x20, #0x1 (1)",
-        "and x4, x21, x20",
-        "cmp x4, #0x0 (0)",
-        "cset x20, eq",
-        "lsl x20, x20, #30",
-        "msr nzcv, x20"
+        "csel x4, x22, x20, ls",
+        "tst x4, x4"
       ]
     },
     "shlx eax, ebx, ecx": {
diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json
index ebc6f16754..6ed4366dd0 100644
--- a/unittests/InstructionCountCI/VEX_map_group.json
+++ b/unittests/InstructionCountCI/VEX_map_group.json
@@ -609,19 +609,17 @@
       ]
     },
     "blsr eax, ebx": {
-      "ExpectedInstructionCount": 10,
+      "ExpectedInstructionCount": 8,
       "Comment": [
         "Map group 17 0b001 32-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, w7",
-        "sub x21, x20, #0x1 (1)",
-        "and x21, x21, x20",
-        "mov w4, w21",
-        "tst w21, w21",
+        "sub w20, w7, #0x1 (1)",
+        "and w4, w20, w7",
+        "cmp x7, #0x0 (0)",
+        "cset x20, eq",
+        "tst w4, w4",
         "mrs x21, nzcv",
-        "cmp x20, #0x0 (0)",
-        "cset x20, ne",
         "orr w20, w21, w20, lsl #29",
         "msr nzcv, x20"
       ]
@@ -634,75 +632,63 @@
       "ExpectedArm64ASM": [
         "sub x20, x7, #0x1 (1)",
         "and x4, x20, x7",
-        "tst x4, x4",
-        "mrs x20, nzcv",
         "cmp x7, #0x0 (0)",
-        "cset x21, ne",
-        "orr w20, w20, w21, lsl #29",
+        "cset x20, eq",
+        "tst x4, x4",
+        "mrs x21, nzcv",
+        "orr w20, w21, w20, lsl #29",
         "msr nzcv, x20"
       ]
     },
     "blsmsk eax, ebx": {
-      "ExpectedInstructionCount": 15,
+      "ExpectedInstructionCount": 8,
       "Comment": [
         "Map group 17 0b010 32-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, w7",
-        "sub x21, x20, #0x1 (1)",
-        "eor x21, x21, x20",
-        "mov w4, w21",
-        "mov w22, #0x50000000",
-        "mrs x23, nzcv",
-        "bic x22, x23, x22",
-        "cmp x20, #0x0 (0)",
+        "sub w20, w7, #0x1 (1)",
+        "eor w4, w20, w7",
+        "cmp x7, #0x0 (0)",
         "cset x20, eq",
-        "mov w0, w22",
-        "bfi w0, w20, #29, #1",
-        "mov w20, w0",
-        "lsr w21, w21, #31",
-        "bfi w20, w21, #31, #1",
+        "tst w4, w4",
+        "mrs x21, nzcv",
+        "orr w20, w21, w20, lsl #29",
         "msr nzcv, x20"
       ]
     },
     "blsmsk rax, rbx": {
-      "ExpectedInstructionCount": 11,
+      "ExpectedInstructionCount": 8,
       "Comment": [
         "Map group 17 0b010 64-bit"
       ],
       "ExpectedArm64ASM": [
         "sub x20, x7, #0x1 (1)",
         "eor x4, x20, x7",
-        "mov w20, #0x50000000",
-        "mrs x21, nzcv",
-        "bic x20, x21, x20",
         "cmp x7, #0x0 (0)",
-        "cset x21, eq",
-        "bfi w20, w21, #29, #1",
-        "lsr x21, x4, #63",
-        "bfi w20, w21, #31, #1",
+        "cset x20, eq",
+        "tst x4, x4",
+        "mrs x21, nzcv",
+        "orr w20, w21, w20, lsl #29",
         "msr nzcv, x20"
       ]
     },
     "blsi eax, ebx": {
-      "ExpectedInstructionCount": 9,
+      "ExpectedInstructionCount": 7,
       "Comment": [
         "Map group 17 0b011 32-bit"
       ],
       "ExpectedArm64ASM": [
-        "mov w20, w7",
-        "neg w21, w20",
-        "and w4, w20, w21",
+        "neg w20, w7",
+        "and w4, w7, w20",
         "tst w4, w4",
         "mrs x20, nzcv",
-        "cmp x4, #0x0 (0)",
-        "cset x21, ne",
+        "cset w21, ne",
         "orr w20, w20, w21, lsl #29",
         "msr nzcv, x20"
       ]
     },
     "blsi rax, rbx": {
-      "ExpectedInstructionCount": 8,
+      "ExpectedInstructionCount": 7,
       "Comment": [
         "Map group 17 0b011 64-bit"
       ],
@@ -711,8 +697,7 @@
         "and x4, x7, x20",
         "tst x4, x4",
         "mrs x20, nzcv",
-        "cmp x4, #0x0 (0)",
-        "cset x21, ne",
+        "cset w21, ne",
         "orr w20, w20, w21, lsl #29",
         "msr nzcv, x20"
       ]